Re: gEDA-user: Error message when creating a SUBCKT
Yes I've followed the tutorial you linked, gsymcheck give no errors for the sym I use (generic 7408 sym provided with geda) for drc2 check, I've already done it and the result is some warning : WARNING: Pin(s) with pintype 'output': U2:6 are connected by net 'unnamed_net11' to pin(s) with pintype 'input/output': P6:1 WARNING: Unused slot 3 of uref U2 WARNING: Unused slot 4 of uref U2 I'm really lost and cannot found what's wrong in my schematic. Regards, Ludovic I've check the pinseq and pinnumber but I've not seen something wrong. On Fri, Aug 15, 2008 at 7:25 PM, John Doty [EMAIL PROTECTED] wrote: On Aug 14, 2008, at 2:28 AM, Ludovic SMADJA wrote: I'm creating a SUBCKT to simulate a 74191 counter. I use the schema provided in the datasheet and in this schema, there is an AND ic whith 5 entries. Have you looked at: www.brorson.com/gEDA/SPICE/intro.html Invalid wanted_pin passed to get-nets [unknown] A common reason for this message is components with duplicated refdes and pin numbers. found pin with no pinseq attribute. Ignoring. . . . Pins *must* have pinseq attributes for spice-sdb. Have you checked your symbols with gsymcheck -vv? Have you used gnetlist -g drc2 to check your schematic? Pure digital schematics are what it's designed for. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ [EMAIL PROTECTED] John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ [EMAIL PROTECTED] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Ludovic SMADJA ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Error message when creating a SUBCKT
Note I've not precised in my precedent post, I use generic schematic with slot (without slot, it's working well, and custom symbol with slot is working well). Ludovic On Sat, Aug 16, 2008 at 8:55 AM, Ludovic SMADJA [EMAIL PROTECTED]wrote: Yes I've followed the tutorial you linked, gsymcheck give no errors for the sym I use (generic 7408 sym provided with geda) for drc2 check, I've already done it and the result is some warning : WARNING: Pin(s) with pintype 'output': U2:6 are connected by net 'unnamed_net11' to pin(s) with pintype 'input/output': P6:1 WARNING: Unused slot 3 of uref U2 WARNING: Unused slot 4 of uref U2 I'm really lost and cannot found what's wrong in my schematic. Regards, Ludovic I've check the pinseq and pinnumber but I've not seen something wrong. On Fri, Aug 15, 2008 at 7:25 PM, John Doty [EMAIL PROTECTED] wrote: On Aug 14, 2008, at 2:28 AM, Ludovic SMADJA wrote: I'm creating a SUBCKT to simulate a 74191 counter. I use the schema provided in the datasheet and in this schema, there is an AND ic whith 5 entries. Have you looked at: www.brorson.com/gEDA/SPICE/intro.html Invalid wanted_pin passed to get-nets [unknown] A common reason for this message is components with duplicated refdes and pin numbers. found pin with no pinseq attribute. Ignoring. . . . Pins *must* have pinseq attributes for spice-sdb. Have you checked your symbols with gsymcheck -vv? Have you used gnetlist -g drc2 to check your schematic? Pure digital schematics are what it's designed for. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ [EMAIL PROTECTED] John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ [EMAIL PROTECTED] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Ludovic SMADJA -- Ludovic SMADJA ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Error message when creating a SUBCKT
On Sat, 2008-08-16 at 08:56 +0200, Ludovic SMADJA wrote: Note I've not precised in my precedent post, I use generic schematic with slot (without slot, it's working well, and custom symbol with slot is working well). Ludovic On Sat, Aug 16, 2008 at 8:55 AM, Ludovic SMADJA [EMAIL PROTECTED] wrote: Yes I've followed the tutorial you linked, gsymcheck give no errors for the sym I use (generic 7408 sym provided with geda) for drc2 check, I've already done it and the result is some warning : WARNING: Pin(s) with pintype 'output': U2:6 are connected by net 'unnamed_net11' to pin(s) with pintype 'input/output': P6:1 WARNING: Unused slot 3 of uref U2 WARNING: Unused slot 4 of uref U2 I'm really lost and cannot found what's wrong in my schematic. Without seeing it, we can't know for sure, but the warning text would suggest that you've used only 2 out of 4 of the gate slots in your 7408. This could cause stability problems, excess power dissipation etc.., hence the warning. If you don't use them, put them on the schematic anyway, and tie the inputs to some defined logic level. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Error message when creating a SUBCKT
On Aug 16, 2008, at 2:55 AM, Ludovic SMADJA wrote: WARNING: Unused slot 3 of uref U2 WARNING: Unused slot 4 of uref U2 I believe that unused slots are poison to the way spice-sdb works. For a slotted component, it expects that the model will implement all slots. Since pins are positional in SPICE netlists, it needs to list every pin on the component. It is unclear to me what you're intending to accomplish here: a SPICE model of a 7408 may be difficult to find, and it is unlikely that it will represent the detailed electrical properties of an interior gate within an MSI chip. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ [EMAIL PROTECTED] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [icarus] task automatic causes assertion
I think there is a bug report related to this in the icarus verilog bugs tracker already. automatic tasks are not supported yes, and there is a patch that I recently applied that reports this as a proper error. Günter Dannoritzer wrote: Hi, I tried compiling some Verilog code with a 'task automatic' statement using Icarus Verilog 0.9.devel s20080429 and got the following assertion: iverilog -o auto2.vvp auto.v auto.v:16: syntax error auto.v:3: assert: pform.cc:359: failed assertion lexical_scope == pform_cur_module sh: line 1: 8518 Done/usr/lib64/ivl/ivlpp -L -F/tmp/ivrlg2784ffa93 -f/tmp/ivrlg784ffa93 -p/tmp/ivrli784ffa93 8519 Aborted | /usr/lib64/ivl/ivl -C/tmp/ivrlh784ffa93 -C/usr/lib64/ivl/vvp.conf -- - -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [iverilog] running the git source of Icarus Verilog
Günter Dannoritzer wrote: Hi, I tried to install Icarus Verilog from git and wonder whether I did something wrong, as when things go wrong it crashes with a segmentation fault. I have to say that I have the latest development snapshot installed in parallel in the standard path. That should be fine. So what I did with the git version is that I checked it out to my home folder, did the 'source autoconf.sh' and then configured it with the --prefix set to a path in my home folder. Then just typed make and make install, without any other options. That should be fine, too. The installation went fine and in order to use it I prepended the new bin/ folder to my path. Also added the new lib/ and lib/ivl/ folder to the LD_LIBRARY_PATH in the shell I want to use it. The LD_LIBRARY_PATH bit is not necessary because the compiler and run time use explicit loading and not implicit loading to bring in any loadable modules. I don't think adding the paths to your LD_LIBRARY_PATH will hurt, but that is certainly not helping you. It seems to work with code that runs without error, but when I try other examples that cause problems it ends with a segmentation fault. Did I do something wrong with my installation? How can I check that it works correct? It is just as likely that you found a bug that is segfaulting instead of tripping an assert. That is rare in Icarus Verilog because we're so liberal with assertions, but it does happen from time to time. The best thing to do (as I se you have done) is to submit a bug report. Even assertions deserve a bug report because it should not trip the assert even with completely random input. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Error message when creating a SUBCKT
About the unused slots, it doesn't seems to be the problem. When I add the 2 unused slots to my schematics and link theirs input pins to ground and output pin to NC symbol, drc2 removes the warning but the spice-sdb give me more Invalid wanted_pin passed to get-nets [unknown] I've already use slots in another circuit without any problem. Ludovic On Sat, Aug 16, 2008 at 4:51 PM, Peter Clifton [EMAIL PROTECTED] wrote: On Sat, 2008-08-16 at 09:26 -0400, John Doty wrote: On Aug 16, 2008, at 2:55 AM, Ludovic SMADJA wrote: WARNING: Unused slot 3 of uref U2 WARNING: Unused slot 4 of uref U2 I believe that unused slots are poison to the way spice-sdb works. For a slotted component, it expects that the model will implement all slots. Since pins are positional in SPICE netlists, it needs to list every pin on the component. Perhaps for the spice backend, but IIRC, spice-sdb renames each slot, so U2 becomes. U2.1 U2.2 U2.3 U2.4 e.g. 4 components instantiated. I might be wrong in the fine-print though. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Ludovic SMADJA ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [icarus] task automatic causes assertion
Stephen Williams wrote: I think there is a bug report related to this in the icarus verilog bugs tracker already. automatic tasks are not supported yes, and there is a patch that I recently applied that reports this as a proper error. Are there any plans to add automatic tasks or is that too complicated or can their use be easily avoided? Guenter ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Error message when creating a SUBCKT
Hmm, I wonder if the problem is the hidden power pins, combined with slotting. Oh, Stuart... On Aug 16, 2008, at 2:53 PM, Ludovic SMADJA wrote: About the unused slots, it doesn't seems to be the problem. When I add the 2 unused slots to my schematics and link theirs input pins to ground and output pin to NC symbol, drc2 removes the warning but the spice-sdb give me more Invalid wanted_pin passed to get-nets [unknown] I've already use slots in another circuit without any problem. Ludovic On Sat, Aug 16, 2008 at 4:51 PM, Peter Clifton [EMAIL PROTECTED] wrote: On Sat, 2008-08-16 at 09:26 -0400, John Doty wrote: On Aug 16, 2008, at 2:55 AM, Ludovic SMADJA wrote: WARNING: Unused slot 3 of uref U2 WARNING: Unused slot 4 of uref U2 I believe that unused slots are poison to the way spice-sdb works. For a slotted component, it expects that the model will implement all slots. Since pins are positional in SPICE netlists, it needs to list every pin on the component. Perhaps for the spice backend, but IIRC, spice-sdb renames each slot, so U2 becomes. U2.1 U2.2 U2.3 U2.4 e.g. 4 components instantiated. I might be wrong in the fine-print though. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Ludovic SMADJA ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ [EMAIL PROTECTED] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [iverilog] running the git source of Icarus Verilog
Stephen Williams wrote: Günter Dannoritzer wrote: ... How can I check that it works correct? It is just as likely that you found a bug that is segfaulting instead of tripping an assert. That is rare in Icarus Verilog because we're so liberal with assertions, but it does happen from time to time. I am not sure. I think it must have to do with my setup. This is the output I am getting when I run the 'task automatic' example that I have submitted for the bug report with my git installation: iverilog -o auto.vvp auto.v auto.v:16: syntax error sh: line 1: 28234 Done /home/hubert/dev//lib/ivl/ivlpp -L -F/tmp/ivrlg2294fdd02 -f/tmp/ivrlg294fdd02 -p/tmp/ivrli294fdd02 28235 Segmentation fault | /home/hubert/dev//lib/ivl/ivl -C/tmp/ivrlh294fdd02 -C/home/hubert/dev//lib/ivl/vvp.conf -- - make: *** [auto.vvp] Error 139 So with the latest development snapshot it gave me an assertion, but with the git version a segmentation fault. The reason I think it has to do with my setup is that this assertion gave a segmentation fault with the git source and the pli example that I provided with the cbValueChange bug report also caused a segmentation fault with the git source. Guenter ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Error message when creating a SUBCKT
On Aug 16, 2008, at 3:32 PM, John Doty wrote: Hmm, I wonder if the problem is the hidden power pins, I note that it there is no mechanism to tell gnetlist what subcircuit pin a hidden net should attach to. Again, it is strange to use a symbol designed for slotted printed circuit layout in a SPICE simulation. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ [EMAIL PROTECTED] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Error message when creating a SUBCKT
On Sat, 2008-08-16 at 20:53 +0200, Ludovic SMADJA wrote: About the unused slots, it doesn't seems to be the problem. When I add the 2 unused slots to my schematics and link theirs input pins to ground and output pin to NC symbol, drc2 removes the warning but the spice-sdb give me more Invalid wanted_pin passed to get-nets [unknown] I've already use slots in another circuit without any problem. Specifically which gEDA version are you using. Please could you post the full console output of the gnetlist run. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Error message when creating a SUBCKT
On Aug 16, 2008, at 4:21 PM, Peter Clifton wrote: Please could you post the full console output of the gnetlist run. He did, at the start of this thread 2.5 days ago. Also the schematic. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ [EMAIL PROTECTED] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [iverilog] running the git source of Icarus Verilog
On Sat, Aug 16, 2008 at 12:55 PM, Günter Dannoritzer [EMAIL PROTECTED] wrote: So with the latest development snapshot it gave me an assertion, but with the git version a segmentation fault. I saw this behavior as well, so I don't think it is your setup. Something must have changed in git between the snapshot and your bug report that prevented the assertion from firing and it went on to segfault. Note that the bug has been fixed in git now (although for some reason I had to make clean then re make for it to pick up the new parsing code, maybe there is a bug in the Makefiles?) Jared ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [iverilog] running the git source of Icarus Verilog
Jared Casper wrote: On Sat, Aug 16, 2008 at 12:55 PM, Günter Dannoritzer [EMAIL PROTECTED] wrote: So with the latest development snapshot it gave me an assertion, but with the git version a segmentation fault. I saw this behavior as well, so I don't think it is your setup. Something must have changed in git between the snapshot and your bug report that prevented the assertion from firing and it went on to segfault. Note that the bug has been fixed in git now (although for some reason I had to make clean then re make for it to pick up the new parsing code, maybe there is a bug in the Makefiles?) Thanks, after an update both segfaults that I had are gone. Guenter ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Error message when creating a SUBCKT
On Sat, 2008-08-16 at 16:29 -0400, John Doty wrote: On Aug 16, 2008, at 4:21 PM, Peter Clifton wrote: Please could you post the full console output of the gnetlist run. He did, at the start of this thread 2.5 days ago. Also the schematic. So he did.. I came in at the end there. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Error message when creating a SUBCKT
On Sat, 2008-08-16 at 15:59 -0400, John Doty wrote: On Aug 16, 2008, at 3:32 PM, John Doty wrote: Hmm, I wonder if the problem is the hidden power pins, I note that it there is no mechanism to tell gnetlist what subcircuit pin a hidden net should attach to. You are correct. Remove the hidden power pins, and the warnings go away. A little debugging code I added to gnetlist confirmed that these pins are being passed as unknown into the C function behind get-nets. The netlist output is correct (by some definition of correct) though, in both cases. However.. perhaps your model for that gate wants power pins passing to it... Best make up a custom symbol. Again, it is strange to use a symbol designed for slotted printed circuit layout in a SPICE simulation. +1. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Renaming ben mode
Tried to send this to DJ directly, but that's not going to work... On Sat, Aug 16, 2008 at 06:26:16PM -0400, DJ Delorie wrote: It's been suggested that we choose a more functional name for this. Would that upset you? ;-) Heh, no, perfectly fine with me. I always figured you chose that name more out of laziness than in my honor. :) Any suggestions before the flame wars start? Well, when I name the images I called them pretty. Or you could go with something like photo. -- Ben Jackson AD7GD [EMAIL PROTECTED] http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
