gEDA-user: View-Displayed element name-Value
Hi guys, I've noticed I could set on gschem's the `value' attribute for each symbol which could be then shown on the final layout, which I find so nice and I prefer over the default scheme. Is there anyway I can control it's text's size once on pcb? I have tried changing the `text scale' option's value from within the preferences menu and restarting pcb, but it only seems to apply for newly/manualy created text. Also, I've noticed that `gsch2pb' truncates white spaces on symbols' value attributes to underscores, though nothing wrong seems to happen if I emacs the resulting pcb and remove them. Is there anyway to let gsch2pcb not to do this? Ah, and another thing yet!. I got to a point where I had to delete the ground plane layer and rebuild it/regroup it because after some retouches, the ground plane got completely twisted. By times not even turning off `thin draw poly' I could see it at all. I've just noticed that not letting routes lay too near from components (especially when it will stay in parallel with such components' pins) will somehow cause the logic to confuse less. For example, it seems that for this time, a route from top to bottom in the middle of a vertically placed dip28 package, was causing this behaviour cose of beeing drawn too near to the pins (the package was placed vertically also). I found this out on a completely trial and error scheme, but after I did redraw it a bit more separated I haven't had to rebuild the ground plane anymore, even when I've made several changes to the layout afterwards. And sorry for the very long post, but that leads me to another question in regards to the previous answer from Delorie to me. I've finally kept the component layer on my layout as advised. I've temporally placed there guides used to rebuild the ground plane when needed. Now, I'm just curious cose Delorie said that I can disable the layer so (I understood) it won't be rendered at output time time even if it got things drawn on it. However, I don't seem to be able to achieve it. The only way I could think of disabling a layer is pressing on it's name up in the upper left hand side stack behind the menu bar, but then it get's written to the output file (postscript is what I'm using). Is there anyway to avoid this? Thanks, Eduardo. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: View-Displayed element name-Value
On Thu, 2008-10-30 at 16:47 +, Eduardo Santana wrote: Hi guys, Ah, and another thing yet!. I got to a point where I had to delete the ground plane layer and rebuild it/regroup it because after some retouches, the ground plane got completely twisted. By times not even turning off `thin draw poly' I could see it at all. I've just noticed that not letting routes lay too near from components (especially when it will stay in parallel with such components' pins) will somehow cause the logic to confuse less. Save - Reload the PCB layout is a common way to cure that, less drastic than deleting and re-building the power planes. This said, this is of course not what we want, and a lot of these bugs got fixed recently. What version of PCB are you using? If you feel able, building a version of PCB from CVS is a good way to get all the latest bug fixes. https://sourceforge.net/cvs/?group_id=73743 cvs -d:pserver:[EMAIL PROTECTED]:/cvsroot/pcb login When prompted for a password for anonymous, simply press the Enter key. cvs -z3 -d:pserver:[EMAIL PROTECTED]:/cvsroot/pcb co -P PCB Now, I'm just curious cose Delorie said that I can disable the layer so (I understood) it won't be rendered at output time time even if it got things drawn on it. However, I don't seem to be able to achieve it. The only way I could think of disabling a layer is pressing on it's name up in the upper left hand side stack behind the menu bar, but then it get's written to the output file (postscript is what I'm using). Is there anyway to avoid this? No, clicking on the name in the layer stack doesn't prevent it from being output, it prevents it from being rendered on-screen. You might wish to print to separate .ps files, then re-join the ones you want with something like psjoin (or other various scripts you can find with Google). Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: View-Displayed element name-Value
--- El jue, 30/10/08, Peter Clifton [EMAIL PROTECTED] escribió: De: Peter Clifton [EMAIL PROTECTED] Asunto: Re: gEDA-user: View-Displayed element name-Value Para: [EMAIL PROTECTED], gEDA user mailing list geda-user@moria.seul.org Fecha: jueves, 30 octubre, 2008 4:59 On Thu, 2008-10-30 at 16:47 +, Eduardo Santana wrote: Hi guys, Ah, and another thing yet!. I got to a point where I had to delete the ground plane layer and rebuild it/regroup it because after some retouches, the ground plane got completely twisted. By times not even turning off `thin draw poly' I could see it at all. I've just noticed that not letting routes lay too near from components (especially when it will stay in parallel with such components' pins) will somehow cause the logic to confuse less. Save - Reload the PCB layout is a common way to cure that, less drastic than deleting and re-building the power planes. This said, this is of course not what we want, and a lot of these bugs got fixed recently. What version of PCB are you using? Ah ok, I never actually tried reloading the layout within the running pcb, though I tried saving, quiting and restarting the application, thanks. Yes I always tend to use software from the repository, my current version is 1.99x, checked out about two weeks ago iirc. And the save-quit- If you feel able, building a version of PCB from CVS is a good way to get all the latest bug fixes. https://sourceforge.net/cvs/?group_id=73743 cvs -d:pserver:[EMAIL PROTECTED]:/cvsroot/pcb login When prompted for a password for anonymous, simply press the Enter key. cvs -z3 -d:pserver:[EMAIL PROTECTED]:/cvsroot/pcb co -P PCB Now, I'm just curious cose Delorie said that I can disable the layer so (I understood) it won't be rendered at output time time even if it got things drawn on it. However, I don't seem to be able to achieve it. The only way I could think of disabling a layer is pressing on it's name up in the upper left hand side stack behind the menu bar, but then it get's written to the output file (postscript is what I'm using). Is there anyway to avoid this? No, clicking on the name in the layer stack doesn't prevent it from being output, it prevents it from being rendered on-screen. You might wish to print to separate .ps files, then re-join the ones you want with something like psjoin (or other various scripts you can find with Google). Sure, thanks so much, Eduardo. Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Size of symbols
On Oct 29, 2008, at 6:51 PM, John Doty wrote: I rather despise the new-fangled plop a component down and attach netnames to each of the pins, with no lines going anywhere methodology, if that's what you meant by your spaghetti reference. ;) No, I meant the opposite, where you have hundreds of long lines on the page, requiring extremely careful tracing to figure out where the one you're interested goes. I like named nets. That's what I meant...I find it much easier to trace long lines than to do what amounts to a visual free-space text search looking for net names. I guess it's a difference in how our respective brains work. with a title block, and I print them usually at 11x17. Would it be reasonable to simply use a LARGE title block (say, E size) and scale it to fit the page on the way out to the printer? Yes. That's the approach gschem supports: the paper size you give in the print dialog determines the scale of the PS output. I typically print a B titleblock on A paper. Some prefer C (screen) to A (paper). The only unreasonable thing here is that I suspect you'll find that people will need a magnifier to read E to B. But maybe your readers' eyes are better than mine. Well most of the time nobody else will see the schematics; just me and (occasionally) two other guys, and they don't mind compactness. For us, just coincidentally, the desire to have more circuit context on the page is of greater value than larger symbols. -Dave -- Dave McGuire Port Charlotte, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Size of symbols
On Oct 29, 2008, at 6:47 PM, Steve Meier wrote: I like a hierarchical schematic where I have a top.sch which has symbols for each of the major subsections and I use buses for most digital signal paths and nets for the analog paths to interconnect these symbols. I like the hierarchical structure as well. When you have designs with a thousand components on it I don't care how small your symbols are or how big your printer is it ain't readable. Most of my designs have topped out at a few hundred components at most, so I've not run into that problem. I'm sure it will become an issue if I work on a larger design. -Dave -- Dave McGuire Port Charlotte, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
I don't see any URLs in there.. -Dave On Oct 29, 2008, at 6:08 PM, Steve Meier wrote: I went looking to see if the Analog Device book was available electronically. Here are the links. Steve Meier High Speed System Applications Table of Contents High Speed System Applications Section 1: High Speed Data Conversion Overview High Speed System Applications Section 2: Optimizing Data Converter Interfaces High Speed System Applications Section 3: DAC, DDS, PLL's, and Clock Distribution High Speed System Applications Section 4: PC Board Layout and Design Tools On Tue, 2008-10-28 at 13:44 -0700, Steve Meier wrote: I won't argue this point. I will refer every one to an Analog Device publication High Speed System Applications copyright 2006 ISBN-10: 1-56619-909-3 or ISBN-13: 978-1-56619-909-4 In particular if you get a copy of this book (and they gave me mine) look at pages 4.15 and 4.16 There AD recommends connecting both of the A/D grounds digital and analog to the analog ground plane this is because it causes less problems for the relatively small amount of digital return current to be returned through the analog ground than it would to connect the converter to the much noisy digital ground. There is a lot more talked about then just that one blurb. Steve Meier On Tue, 2008-10-28 at 11:22 -0700, Joerg wrote: Stefan Salewski wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? I can't speak to that but just one word of caution: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. Regardless of what application notes say. Usually it didn't work, lots of noise. Or it kind of worked but fell apart the instant somebody whipped out a GSM cell phone or BlackBerry. Myself, I never spilt a ground place. OTOH the industry practice of splitting planes is providing part of my income :-) The only time I split is where required for safety, for example patient isolation per 60601 (ECG, ultrasound etc.). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Dave McGuire Port Charlotte, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Dave, No I struggled three times to get usable url's so go down a couple more of my attempts and then you will have to take the line breaks out of the ultra long url but you can get there. Steve Meier On Thu, 2008-10-30 at 16:29 -0400, Dave McGuire wrote: I don't see any URLs in there.. -Dave On Oct 29, 2008, at 6:08 PM, Steve Meier wrote: I went looking to see if the Analog Device book was available electronically. Here are the links. Steve Meier High Speed System Applications Table of Contents High Speed System Applications Section 1: High Speed Data Conversion Overview High Speed System Applications Section 2: Optimizing Data Converter Interfaces High Speed System Applications Section 3: DAC, DDS, PLL's, and Clock Distribution High Speed System Applications Section 4: PC Board Layout and Design Tools On Tue, 2008-10-28 at 13:44 -0700, Steve Meier wrote: I won't argue this point. I will refer every one to an Analog Device publication High Speed System Applications copyright 2006 ISBN-10: 1-56619-909-3 or ISBN-13: 978-1-56619-909-4 In particular if you get a copy of this book (and they gave me mine) look at pages 4.15 and 4.16 There AD recommends connecting both of the A/D grounds digital and analog to the analog ground plane this is because it causes less problems for the relatively small amount of digital return current to be returned through the analog ground than it would to connect the converter to the much noisy digital ground. There is a lot more talked about then just that one blurb. Steve Meier On Tue, 2008-10-28 at 11:22 -0700, Joerg wrote: Stefan Salewski wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? I can't speak to that but just one word of caution: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. Regardless of what application notes say. Usually it didn't work, lots of noise. Or it kind of worked but fell apart the instant somebody whipped out a GSM cell phone or BlackBerry. Myself, I never spilt a ground place. OTOH the industry practice of splitting planes is providing part of my income :-) The only time I split is where required for safety, for example patient isolation per 60601 (ECG, ultrasound etc.). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Steve, I don't see these other attempts. Eric Winsor Steve Meier wrote: Dave, No I struggled three times to get usable url's so go down a couple more of my attempts and then you will have to take the line breaks out of the ultra long url but you can get there. Steve Meier On Thu, 2008-10-30 at 16:29 -0400, Dave McGuire wrote: I don't see any URLs in there.. -Dave On Oct 29, 2008, at 6:08 PM, Steve Meier wrote: I went looking to see if the Analog Device book was available electronically. Here are the links. Steve Meier High Speed System Applications Table of Contents High Speed System Applications Section 1: High Speed Data Conversion Overview High Speed System Applications Section 2: Optimizing Data Converter Interfaces High Speed System Applications Section 3: DAC, DDS, PLL's, and Clock Distribution High Speed System Applications Section 4: PC Board Layout and Design Tools On Tue, 2008-10-28 at 13:44 -0700, Steve Meier wrote: I won't argue this point. I will refer every one to an Analog Device publication High Speed System Applications copyright 2006 ISBN-10: 1-56619-909-3 or ISBN-13: 978-1-56619-909-4 In particular if you get a copy of this book (and they gave me mine) look at pages 4.15 and 4.16 There AD recommends connecting both of the A/D grounds digital and analog to the analog ground plane this is because it causes less problems for the relatively small amount of digital return current to be returned through the analog ground than it would to connect the converter to the much noisy digital ground. There is a lot more talked about then just that one blurb. Steve Meier On Tue, 2008-10-28 at 11:22 -0700, Joerg wrote: Stefan Salewski wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? I can't speak to that but just one word of caution: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. Regardless of what application notes say. Usually it didn't work, lots of noise. Or it kind of worked but fell apart the instant somebody whipped out a GSM cell phone or BlackBerry. Myself, I never spilt a ground place. OTOH the industry practice of splitting planes is providing part of my income :-) The only time I split is where required for safety, for example patient isolation per 60601 (ECG, ultrasound etc.). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Ok ok ok go to my home page and look for links to hs table of contents and hs section 1 through 4 http://www.alchemyresearch.com/ Steve Meier On Thu, 2008-10-30 at 16:29 -0400, Dave McGuire wrote: I don't see any URLs in there.. -Dave On Oct 29, 2008, at 6:08 PM, Steve Meier wrote: I went looking to see if the Analog Device book was available electronically. Here are the links. Steve Meier High Speed System Applications Table of Contents High Speed System Applications Section 1: High Speed Data Conversion Overview High Speed System Applications Section 2: Optimizing Data Converter Interfaces High Speed System Applications Section 3: DAC, DDS, PLL's, and Clock Distribution High Speed System Applications Section 4: PC Board Layout and Design Tools On Tue, 2008-10-28 at 13:44 -0700, Steve Meier wrote: I won't argue this point. I will refer every one to an Analog Device publication High Speed System Applications copyright 2006 ISBN-10: 1-56619-909-3 or ISBN-13: 978-1-56619-909-4 In particular if you get a copy of this book (and they gave me mine) look at pages 4.15 and 4.16 There AD recommends connecting both of the A/D grounds digital and analog to the analog ground plane this is because it causes less problems for the relatively small amount of digital return current to be returned through the analog ground than it would to connect the converter to the much noisy digital ground. There is a lot more talked about then just that one blurb. Steve Meier On Tue, 2008-10-28 at 11:22 -0700, Joerg wrote: Stefan Salewski wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? I can't speak to that but just one word of caution: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. Regardless of what application notes say. Usually it didn't work, lots of noise. Or it kind of worked but fell apart the instant somebody whipped out a GSM cell phone or BlackBerry. Myself, I never spilt a ground place. OTOH the industry practice of splitting planes is providing part of my income :-) The only time I split is where required for safety, for example patient isolation per 60601 (ECG, ultrasound etc.). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Were you trying to format them with HTML? I bet the HTML filters on the mailing list were cutting out the links. On Oct 30, 2008, at 2:44 PM, Eric Winsor wrote: Steve, I don't see these other attempts. Eric Winsor Steve Meier wrote: Dave, No I struggled three times to get usable url's so go down a couple more of my attempts and then you will have to take the line breaks out of the ultra long url but you can get there. Steve Meier On Thu, 2008-10-30 at 16:29 -0400, Dave McGuire wrote: I don't see any URLs in there.. -Dave On Oct 29, 2008, at 6:08 PM, Steve Meier wrote: I went looking to see if the Analog Device book was available electronically. Here are the links. Steve Meier High Speed System Applications Table of Contents High Speed System Applications Section 1: High Speed Data Conversion Overview High Speed System Applications Section 2: Optimizing Data Converter Interfaces High Speed System Applications Section 3: DAC, DDS, PLL's, and Clock Distribution High Speed System Applications Section 4: PC Board Layout and Design Tools On Tue, 2008-10-28 at 13:44 -0700, Steve Meier wrote: I won't argue this point. I will refer every one to an Analog Device publication High Speed System Applications copyright 2006 ISBN-10: 1-56619-909-3 or ISBN-13: 978-1-56619-909-4 In particular if you get a copy of this book (and they gave me mine) look at pages 4.15 and 4.16 There AD recommends connecting both of the A/D grounds digital and analog to the analog ground plane this is because it causes less problems for the relatively small amount of digital return current to be returned through the analog ground than it would to connect the converter to the much noisy digital ground. There is a lot more talked about then just that one blurb. Steve Meier On Tue, 2008-10-28 at 11:22 -0700, Joerg wrote: Stefan Salewski wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? I can't speak to that but just one word of caution: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. Regardless of what application notes say. Usually it didn't work, lots of noise. Or it kind of worked but fell apart the instant somebody whipped out a GSM cell phone or BlackBerry. Myself, I never spilt a ground place. OTOH the industry practice of splitting planes is providing part of my income :-) The only time I split is where required for safety, for example patient isolation per 60601 (ECG, ultrasound etc.). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
No the first attempt was a cut and paste that didn't bring the url with it though an html filter would have removed it. The second and third attempts I was responding only too myself. Good thing too as I was getting frustrated with how my email tool automatically breaks lines into pieces. And the urls are convoluted. Steve Meier On Thu, 2008-10-30 at 19:14 -0700, Steven Michalske wrote: Were you trying to format them with HTML? I bet the HTML filters on the mailing list were cutting out the links. On Oct 30, 2008, at 2:44 PM, Eric Winsor wrote: Steve, I don't see these other attempts. Eric Winsor Steve Meier wrote: Dave, No I struggled three times to get usable url's so go down a couple more of my attempts and then you will have to take the line breaks out of the ultra long url but you can get there. Steve Meier On Thu, 2008-10-30 at 16:29 -0400, Dave McGuire wrote: I don't see any URLs in there.. -Dave On Oct 29, 2008, at 6:08 PM, Steve Meier wrote: I went looking to see if the Analog Device book was available electronically. Here are the links. Steve Meier High Speed System Applications Table of Contents High Speed System Applications Section 1: High Speed Data Conversion Overview High Speed System Applications Section 2: Optimizing Data Converter Interfaces High Speed System Applications Section 3: DAC, DDS, PLL's, and Clock Distribution High Speed System Applications Section 4: PC Board Layout and Design Tools On Tue, 2008-10-28 at 13:44 -0700, Steve Meier wrote: I won't argue this point. I will refer every one to an Analog Device publication High Speed System Applications copyright 2006 ISBN-10: 1-56619-909-3 or ISBN-13: 978-1-56619-909-4 In particular if you get a copy of this book (and they gave me mine) look at pages 4.15 and 4.16 There AD recommends connecting both of the A/D grounds digital and analog to the analog ground plane this is because it causes less problems for the relatively small amount of digital return current to be returned through the analog ground than it would to connect the converter to the much noisy digital ground. There is a lot more talked about then just that one blurb. Steve Meier On Tue, 2008-10-28 at 11:22 -0700, Joerg wrote: Stefan Salewski wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? I can't speak to that but just one word of caution: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. Regardless of what application notes say. Usually it didn't work, lots of noise. Or it kind of worked but fell apart the instant somebody whipped out a GSM cell phone or BlackBerry. Myself, I never spilt a ground place. OTOH the industry practice of splitting planes is providing part of my income :-) The only time I split is where required for safety, for example patient isolation per 60601 (ECG, ultrasound etc.). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: powermeter board, with less ground planes :-)
http://www.delorie.com/electronics/powermeter/ I merged the three ground planes into one, and draw AVdd from DVdd for each chip, with a 10R/10uF power filter. There's still a big hole in the ground plane where the Vdd plane goes, as well as all the digital signals to each chip. There's a bunch of bypass caps across the boundary between the ground and power planes; six 10u scattered plus 0.1u at each chip. All the digital signals have series resistors on them to slow down the edges, except for reset which doesn't change once the board is running. Better? (or at least, good enough? ;) 495 parts so far! 367 holes, 290 of which are vias. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
