Re: gEDA-user: Power (and other non-graphical) pins
On Wed, 2009-01-14 at 10:33 +, Peter Clifton wrote: On Tue, 2009-01-13 at 20:45 -0500, Bob Paddock wrote: On Tue, Jan 13, 2009 at 7:57 PM, DJ Delorie [1...@delorie.com wrote: It only has to live a couple of hours I've made circuits like that. Not always intentionally, though. You can buy parts from Vishay that do rapid spontaneous disassembly by design: Exploding/Magic Smoke Resistors now available off-the-shelf, [2]http://blog.obscureresearch.net/epic If you read the data-sheet, as I did, you might be amused to find this at the bottom: The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. No Vishay, but you're perfectly happy for them to be used in bombs, and munitions etc.. They do quote airbag initiation as a typical example usage, so I'd imagine that would come under life-saving application. The national appnote linked had similar amusing disclaimers: 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user Hmm.. can't a munitions detonator reasonably [be] expected to result in a significant injury if it _does_ perform properly? (Ok, so not the user... or do we count the people on the receiving end of the munitions.. the users). -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
On Tue, 2009-01-13 at 20:45 -0500, Bob Paddock wrote: On Tue, Jan 13, 2009 at 7:57 PM, DJ Delorie [1...@delorie.com wrote: It only has to live a couple of hours I've made circuits like that. Not always intentionally, though. You can buy parts from Vishay that do rapid spontaneous disassembly by design: Exploding/Magic Smoke Resistors now available off-the-shelf, [2]http://blog.obscureresearch.net/epic If you read the data-sheet, as I did, you might be amused to find this at the bottom: The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. No Vishay, but you're perfectly happy for them to be used in bombs, and munitions etc.. They do quote airbag initiation as a typical example usage, so I'd imagine that would come under life-saving application. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: compiling gaf from git repos
I compile OK from pcjc2's cairo_place_lines branch, but when I cloned http://git.gpleda.org/, made a new branch from master It stops at libgeda with errors. Is master the right branch to use? John -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: compiling gaf from git repos
On Wednesday 14 January 2009 15:29:40 John Griessen wrote: I compile OK from pcjc2's cairo_place_lines branch, but when I cloned http://git.gpleda.org/, made a new branch from master It stops at libgeda with errors. What sort of errors? Is master the right branch to use? Yes, it is. Peter -- Peter Brett Electronic Systems Engineer Integral Informatics Ltd signature.asc Description: This is a digitally signed message part. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: compiling gaf from git repos
On Wed, 2009-01-14 at 09:29 -0600, John Griessen wrote: I compile OK from pcjc2's cairo_place_lines branch, but when I cloned http://git.gpleda.org/, made a new branch from master It stops at libgeda with errors. Is master the right branch to use? master is good. It now has far more cairo support than the above branch you mentioned. To get libgeda building, you may need to: make reconfig make install at toplevel. Failing that: make reconfig make libgeda_config make libgeda_install make config make install (That probably duplicates a build or two, but since libgeda isn't make clean'd in between, it ought to be fairly fast). -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: compiling gaf from git repos
On Wed, 14 Jan 2009 15:58:40 +, Peter Clifton wrote: Just tried this route to get a fresh geda from git: $ git clone git://git.gpleda.org/gaf $ cd gaf $ gedit Makefile# change destination dir $ make reconfig $ make install However, make install produced a syntax error during config: $ make install (...) make[1]: Leaving directory `/usr/local/geda-src/gaf/symbols' ( cd libgeda; ./configure --prefix=/usr/local --with-xdgdatadir=/home/kmk/.local/share --with-kdedatadir=/home/kmk/.kde/share ) Configuring libgeda version 1.5.1.20081221 checking for a BSD-compatible install... /usr/bin/install -c checking whether build environment is sane... yes checking for a thread-safe mkdir -p... /bin/mkdir -p checking for gawk... gawk checking whether make sets $(MAKE)... yes ./configure: line 2373: syntax error near unexpected token `win32-dll,shared' ./configure: line 2373: `LT_INIT(win32-dll,shared)' make: *** [libgeda/config.h] Error 2 If I issue make libgeda_config manually, I get the same error. Anything I can do about this? ---(kaimartin)--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
On Jan 13, 2009, at 1:47 PM, Joerg wrote: John Doty wrote: Then we are working in different worlds. And that is my point. gEDA has to be flexible to accommodate the needs of different worlds, rather than some specific narrow channel. But at least we both worked with CCD imagers :-) Since 1974. Still do (ASTRO-H, TESS). In design reviews, The schematics are only part of the story. In a NASA design review, the majority of the reviewers won't even look at them. Last one I saw was mostly schematics and mechanical CAD. Then you saw only part of the process. Many reviewers are just going to look at requirements and specifications. But the real holy of holies to NASA is the parts list: there will be no mercy for those whose choice of parts is deemed blasphemous. for the TUEV inspector, and so on. They do not want to have to thumb through reams of paper to find which net something invisible is connected to. A schematic of a 2000 pin backplane is pretty useless, while the same data in a human-friendly tabular form makes it really easy to find where to put the scope probe. Sure, but I don't think that's what gEDA was meant to do. This is *exactly* what gEDA is intended to do. Electronic design automation, with the emphasis on the automation. gEDA is a toolkit for automating as much of the process as possible. That's what Excel or OpenOffice is for. Those are not tools for an automated flow: you can't easily combine them with other tools in a scripted fashion. For an automated flow, you want automation-friendly tools: awk, perl, troff, TeX, etc. The key gEDA tool here is gnetlist, which can do far more than make netlists. The backplanes in our ultrasound systems are usually north of 4000 pins and I have never seen a case where there was not a schematic for that. The existence of the schematic doesn't matter. It's the use. What good is such a schematic? For review, revision, or debugging I'd much rather have a table: all the information without the eyestrain. But with my table-to-pseudo-schematic script and gEDA, I'm free to make a schematic or not, as I choose. I can even mix approaches for different parts of a board. But those are relevant. My biggest use of gEDA is mixed-signal ASIC design. Ok, if gEDA is geared towards ASIC/FPGA that's different. It's not geared toward anything specific. I'm sure ASIC design is a minority use. gEDA is *flexible*. Then it sure won't be my kind of tool, just like BAE isn't (had tried it out lately). It's a toolkit, not a tool. They all work the same way I do, in the graphical domain all the way up to the end when the netlist for the layouter is generated. That approach doesn't scale efficiently to big projects. Graphics are superb for expressing circuit topology at moderate scales. But nobody will ever comprehend how a Pentium works from schematics. True. That would be ASIC type work. But mixed-signal boards are now getting to the complexity levels where schematics cease to be useful. 200 cm^2 of 0402's and IC's with 0.5 mm pins is an awful lot of stuff. gEDA gives me the tools to achieve the automation leverage to cope here. And I need plenty: there's only one of me, and electronic design is only part of what I do. The Veriog-AMS fans think they can eliminate schematics completely, design analog in code, and have the computer synthesize the netlist from that. That's also a nutty position, but they have a good reason: code scales better than graphics. So, if you want to do really big mixed-signal systems efficiently, you're going to need to do the higher levels with code. The nuttiness comes from thinking one kind of tool should work on all scales. So, a correlated double sampler circuit is best expressed as a schematic, but the higher levels of a system containing 96 such circuits along with a bunch of other stuff is not. At some point, your eyes can't take it all in, so you might as well start making lists. That's where the hierarchy comes in, and AFAICT gEDA handles a hierarchy nicely. True. You don't see all those 96 identical circuits, just one plus the fact that there are 96 of them. I've done a lot of those (in schematics), the biggest one 128. But the problem comes when you get to the upper levels of the hierarchy. When you just have boxes connected by busses, the topological significance of the graphics is lost. For my ASIC work, I find it easier to check the top level schematics by reading the SPICE netlists. So, I have to ask myself, what good is such a schematic? I'm doing connectors with lists instead of drawings in one current project, but maybe I should start doing lists for top level, too. Of course this isn't a new idea: the digital folks figured this out half a century ago. Ever see the design docs for a Minuteman I ICBM guidance computer? John Doty Noqsi Aerospace, Ltd.
Re: gEDA-user: Power (and other non-graphical) pins
On Jan 13, 2009, at 5:12 PM, r wrote: BTW, analog IC guys long since have given up using implicit power connections Another sweeping statement from a narrow point of view, I think. A counter-example is in order: http://research.kek.jp/people/ikeda/openIP/ If you can't read Japanese, just look at the diagrams and SPICE subcircuits. Should be clear enough. The key strength of gEDA here is that you can do this any way you need to for your specific project. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
John Doty wrote: On Jan 13, 2009, at 5:12 PM, r wrote: BTW, analog IC guys long since have given up using implicit power connections Another sweeping statement from a narrow point of view, I think. A counter-example is in order: http://research.kek.jp/people/ikeda/openIP/ If you can't read Japanese, just look at the diagrams and SPICE subcircuits. Should be clear enough. Yes, no surprise there - schematics: http://research.kek.jp/people/ikeda/openIP/openIP_16.pdf The key strength of gEDA here is that you can do this any way you need to for your specific project. Well, as we have seen with slotted parts, not any way it's needed. But it can get there, which is why I mentioned the problem. -- Regards, Joerg http://www.analogconsultants.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: Tracking the Latest with CVS
Fixed, please cvs update and build again. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
On Jan 13, 2009, at 5:12 PM, r wrote: Believe it or not, gEDA actually strongly focuses on the PCB flow. It supports PCB flow, but it's not intended to be focused on any specific application. That is part of its strength. I've designed ASICs with it, so it's hardly restricted to PCB. Just look at the symbol attributes - pin numbers, footprints, even reference designators come in PCB flavor. You can use anything you want for a reference designator. It needs PCB-centric attributes for a PCB flow, but in an ASIC flow you don't need to use them. There is only partial support for the design hierarchy, The problem with design hierarchy is that it supports a variety of downstream flows, and these don't seem to have a common way to do hierarchy. So we have a couple of different ways to do hierarchy (gschem-style, SPICE-style) with some knobs on them. That's the cost of flexibility. partial support for libraries, I see no limitation. I am increasingly reusing design fragments. That's a gEDA strength if you organize your flow to make it easy. And you are free to do so. partial support for other types of design data (RTL, netlists), Well, the AWK script I posted awhile back to merge in pinlists is pretty simple. Maybe I'll tidy it up and submit it to Ales. A key strength of gEDA is its simple, well documented file formats, which make it easy to do things like this with a few minutes of scripting. no functional netlisters, Eh? One of gEDA's strengths is its ability to export netlists to a radically wide variety of of other tools. no DRC checks on the design. drc2? These issues can often be fixed using external tools (makefiles, own netlisters and rule checkers) but they are enough to discourage most designers from even trying the tool. gEDA is a flexible toolkit, not an inflexible integrated tool. It gives you the freedom to adapt to your processes, not enforcing any narrow point of view on the designer. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: Tracking the Latest with CVS
Am Mittwoch, den 14.01.2009, 19:45 + schrieb Kai-Martin Knaak: The photo realistic png pictures posted on the list lately, made me want to try the current head in CVS. Latest pcb snapshot 20081128 supports photo realistic output. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
On Jan 14, 2009, at 12:44 PM, Joerg wrote: John Doty wrote: On Jan 13, 2009, at 5:12 PM, r wrote: BTW, analog IC guys long since have given up using implicit power connections Another sweeping statement from a narrow point of view, I think. A counter-example is in order: http://research.kek.jp/people/ikeda/openIP/ If you can't read Japanese, just look at the diagrams and SPICE subcircuits. Should be clear enough. Yes, no surprise there - schematics: http://research.kek.jp/people/ikeda/openIP/openIP_16.pdf Of course. For building blocks at this level, that's entirely appropriate. It's when you build complex multichannel systems from these blocks that schematics become incomprehensible. The key strength of gEDA here is that you can do this any way you need to for your specific project. Well, as we have seen with slotted parts, not any way it's needed. I think you're confusing wants and needs. It can do slotting just fine, but it can't read your mind. But it can get there, which is why I mentioned the problem. If you wanted to, you could no doubt solve it with a little scripting (I'm still not sure exactly what you want: I can't read your mind either). But you'd have to cross a line you've drawn. gEDA is for those who enjoy crossing such lines, I think. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: Tracking the Latest with CVS
On Wed, 14 Jan 2009 14:57:07 -0500, DJ Delorie wrote: Fixed, please cvs update and build again. Works :-) This was fast! Do you know the source by heart? ---(kaimartin)--- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: Tracking the Latest with CVS
Do you know the source by heart? Some of it. In this case, I knew right away what the *bug* was, so finding the right spot in the source was easy. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: compiling gaf from git repos
On Wed, 2009-01-14 at 19:06 +, Kai-Martin Knaak wrote: On Wed, 14 Jan 2009 15:58:40 +, Peter Clifton wrote: Just tried this route to get a fresh geda from git: $ git clone git://git.gpleda.org/gaf $ cd gaf $ gedit Makefile# change destination dir $ make reconfig $ make install However, make install produced a syntax error during config: Try installing newer libtool. If that fails, try removing both the [shared] and [win32-dll] options. (Separately, then both.) Please report back! If its too much of a burden, I'll put the old (deprecated) syntax back. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
John Doty wrote: On Jan 14, 2009, at 12:44 PM, Joerg wrote: John Doty wrote: On Jan 13, 2009, at 5:12 PM, r wrote: BTW, analog IC guys long since have given up using implicit power connections Another sweeping statement from a narrow point of view, I think. A counter-example is in order: http://research.kek.jp/people/ikeda/openIP/ If you can't read Japanese, just look at the diagrams and SPICE subcircuits. Should be clear enough. Yes, no surprise there - schematics: http://research.kek.jp/people/ikeda/openIP/openIP_16.pdf Of course. For building blocks at this level, that's entirely appropriate. It's when you build complex multichannel systems from these blocks that schematics become incomprehensible. That's when we move over to block diagrams. Not just for chip designs, also for large board level designs. The key strength of gEDA here is that you can do this any way you need to for your specific project. Well, as we have seen with slotted parts, not any way it's needed. I think you're confusing wants and needs. It can do slotting just fine, but it can't read your mind. They will be messed up upon renumbering. But who knows, someday it might get fixed. But it can get there, which is why I mentioned the problem. If you wanted to, you could no doubt solve it with a little scripting (I'm still not sure exactly what you want: I can't read your mind either). But you'd have to cross a line you've drawn. gEDA is for those who enjoy crossing such lines, I think. Didn't draw a line, but I am not a programmer. Sure, I could figure it out and somehow attempt to fix it but there are people in this community who could do that a lot better. Anyhow, I've mentioned further above in this thread what the problem is (renumbering messes up refdeses when only slot A has power visible). For me the solution right now is to just stick with my old CAD. Or maybe even resurrect ye olde OrCad. Somehow I often miss that old SDT, probably just like I'd wish I could have my first car back just one more time :-) -- Regards, Joerg http://www.analogconsultants.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Unconnected pins and missing sub-parts
Related to recent discussion: Maybe it would be nice if we can define pins in gschem symbols which can not be left floating, i.e. power pins and input of 74HCxx. (I forgot to place all slots of an 74HC04 some time ago, resulting in open input pins.) Related to multiple subpart devices like FPGA or OpAmp with separate power pins a SubParts attribute may be useful, like SubParts=Bank0, Bank1, Power indicating that a part consists of multiple sub-symbols, so that gschem/gnetlist can verify that all sub-parts are present. OK, only a simple minded note. Best regards Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Slot naming improvement methods.
Hey gang, This is a proposal that seems to have gotten lost in a debate if gEDA is the right toolkit for someone. So here is a technical discussion on how we could IMPROVE gEDA. The proposal, please comment on lapses of functionality, and one sidedness as I use gEDA in PCB and spice 'n friends workflows When adding a slotted or multi part component it should have an attribute of an unique instantiation ID (UIID) that gets matched With the other symbols of that device instance. - have a ui pop up with this is a slotted/multi part device, - have options to add to existing instance, add new, or save for hierarchy compilation - have options for specific slot, next, undecided, or best slot This works into deeper capabilities, assisted slotting and multi symbol verification. To make slotting more robust to errors like U1a and U1b both having slot 1, To make sure that multi symbol parts have all their symbols, such as a microcontroller missing one of it's three sub symbols, it would warn the designer it should match each slotted device with it's UIID it should verify that each UIID is complete to it's devices rules. - i.e. a device of type X has the symbols of: one power symbol, one foo symbol, and one foo+power symbol. - There can only be upto 4 foo slots - there can be only one of the 4 foo slots with power. - There must be one power connection - Spare slots should have a default connection scheme. slot pin 1,2,3 should be tied to GND of the power for this UIID, pin 4 to VCC, pin 5 is NoConnect - etc... - Hate to say it, but sounds like a data base :-P - ok an additional file type, *.msym for meta symbol. it should renumber a UIID to the same refdes. it should verify that a UIID is not over spent ( i.e. 5 slots on a 4 slot part ) it should list an under spent UIID - This would allow for post netlisting combinations. example in a design you have 16 sub modules that use 2 of 4 slots in a part, half of each share the same power nets, we should assist the collecting of the parts with the same power ground nets. - e.g. printout, or pop up a slot editor. with the following info. refdes U1, U2, U3, and U4 have spare slots and share the same power and ground This would require the schematic to physical stage to have a slotting tool that understood this. - this stage could output a slotting information report that PCB or other layout tools (humans) could read. - PCB could then allow for back annotating slot changes with the help of the report we should drop the refdes+letter notation going forward. - The suffix should be generated not defined as part of the refdef - I don't want U1a to point to the first slot then in U2a points to slot 3, unless you tie them together two locations can conflict/ confuse. e.g. a technician is debugging a part, they have worked on three stages, but each part calls it stage?/U1A well unfortunately each section being differently laid out had U1A being different slots. making shortcuts that are often taken they measured the wrong pins, because a b and c were pins 1 2 and 3 on U1 but 3 2 and 1 on U2. Hardkrash ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Unconnected pins and missing sub-parts
On Jan 14, 2009, at 2:02 PM, Stefan Salewski wrote: Related to multiple subpart devices like FPGA or OpAmp with separate power pins a SubParts attribute may be useful, like SubParts=Bank0, Bank1, Power indicating that a part consists of multiple sub-symbols, so that gschem/gnetlist can verify that all sub-parts are present. This is a good idea because it allows us to keep the current I'm not going to second guess the designer behavior, while giving gnetlist a way to check if the designer has provided the necessary information. Gives the designer a way to say there should be only one of these, too. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: compiling gaf from git repos
On Wed, 14 Jan 2009 20:30:59 +, Peter Clifton wrote: Try installing newer libtool. Hmm. The libtool version I have installed is identical to the one in debian/sid (v1.5.26) There is v2.26 in debian/experimental. However, apt- get wants to remove guile-1.8 -- not good. If that fails, try removing both the [shared] and [win32-dll] options. Where are the offending options? Can't grep win32-dll in config.h.in, or anywhere else in the source. If its too much of a burden, I'll put the old (deprecated) syntax back. Might be good to hold back until debian unfreezes... ---(kaimartin)--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
On Jan 14, 2009, at 1:49 PM, Joerg wrote: John Doty wrote: On Jan 14, 2009, at 12:44 PM, Joerg wrote: John Doty wrote: On Jan 13, 2009, at 5:12 PM, r wrote: BTW, analog IC guys long since have given up using implicit power connections Another sweeping statement from a narrow point of view, I think. A counter-example is in order: http://research.kek.jp/people/ikeda/openIP/ If you can't read Japanese, just look at the diagrams and SPICE subcircuits. Should be clear enough. Yes, no surprise there - schematics: http://research.kek.jp/people/ikeda/openIP/openIP_16.pdf Of course. For building blocks at this level, that's entirely appropriate. It's when you build complex multichannel systems from these blocks that schematics become incomprehensible. That's when we move over to block diagrams. Not just for chip designs, also for large board level designs. Sure. But you can't extract a netlist from a block diagram. So, you need something more. Easy enough with gEDA, as I've demonstrated. The key strength of gEDA here is that you can do this any way you need to for your specific project. Well, as we have seen with slotted parts, not any way it's needed. I think you're confusing wants and needs. It can do slotting just fine, but it can't read your mind. They will be messed up upon renumbering. But who knows, someday it might get fixed. I wrote a one-shot AWK script to renumber a particular design using slotted parts once. It had a bunch of limitations, so I never submitted it. Using hierarchy to divide the design up works better, don't have tricky renumbering problems there. But remember, fixed for you probably means broken for somebody else. But it can get there, which is why I mentioned the problem. If you wanted to, you could no doubt solve it with a little scripting (I'm still not sure exactly what you want: I can't read your mind either). But you'd have to cross a line you've drawn. gEDA is for those who enjoy crossing such lines, I think. Didn't draw a line, but I am not a programmer. That's the line. What makes you think you need to be a programmer to write programs? I'm not even an EE, I'm a physicist (at least that's what it says on my degrees). But whatever the job takes. Increasingly, design *is* programming. Software takes over from hardware as it can. Music synthesizers used to be racks of VCO's. Understanding when, where, and how to move that line is part of the job. Both in processes and products. Sure, I could figure it out and somehow attempt to fix it but there are people in this community who could do that a lot better. The one who has the clearest vision of what the problem is is often the best fixer. That's one of the strengths of free software. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: Recommendations for laptop?
Larry Doolittle wrote: On Fri, Jan 02, 2009 at 09:40:08PM -0700, Eric Brombaugh wrote: I've been glancing over some of the inexpensive Linux-based netbooks lately - a tad underpowered, but potentially useful and cheap enough to take a flyer on. I'm curious how useful a 1024x800 screen would be for gEDA/PCB. 1024x800? Where? They're all widescreen now. The lightweight, inexpensive ones are 1024*600 or so. The larger, heavier, cheap and modern notebooks get up all the way to 1280x800. The lack of height would hurt me, at least. I now use a 1024x768 Thinkpad X40 (which I have promoted here before: US$400 on eBay). I couldn't stand going any smaller in screen size. Dredging up this old thread again... I found an ASUS EEE PC 900A at a local big-box last week for $200. After a few false starts with the pre-installed Xandros distro, I loaded up Ubuntu eee which seems to be working well. gEDA/PCB were easily added with apt-get (although the Ubuntu repositories are still on 20080202 unfortunately) and gschem + PCB work fine. Surprisingly usable, even on the small screen. I do wonder if there is any way to get a newer package though. Fedora 9's yum repository is pretty much up-to-date. I guess compiling from source is the only way for now. Overall not bad though. It would work in a pinch. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Slot naming improvement methods.
Steven Michalske wrote: Hey gang, This is a proposal that seems to have gotten lost in a debate if gEDA is the right toolkit for someone. So here is a technical discussion on how we could IMPROVE gEDA. The proposal, please comment on lapses of functionality, and one sidedness as I use gEDA in PCB and spice 'n friends workflows When adding a slotted or multi part component it should have an attribute of an unique instantiation ID (UIID) that gets matched With the other symbols of that device instance. - have a ui pop up with this is a slotted/multi part device, - have options to add to existing instance, add new, or save for hierarchy compilation - have options for specific slot, next, undecided, or best slot This works into deeper capabilities, assisted slotting and multi symbol verification. To make slotting more robust to errors like U1a and U1b both having slot 1, To make sure that multi symbol parts have all their symbols, such as a microcontroller missing one of it's three sub symbols, it would warn the designer it should match each slotted device with it's UIID it should verify that each UIID is complete to it's devices rules. - i.e. a device of type X has the symbols of: one power symbol, one foo symbol, and one foo+power symbol. - There can only be upto 4 foo slots Not sure what foo means in this context but anyhow, the max number of slots for a library part should be kept high. Bus drivers, HV drivers and such can have dozens. - there can be only one of the 4 foo slots with power. Sometimes there can be parts where supplies are split between two or more dies inside a package (multi-chip like). But this is very rare. - There must be one power connection Some parts do not have a power connection at all. For example resistor arrays or diode arrays. - Spare slots should have a default connection scheme. slot pin 1,2,3 should be tied to GND of the power for this UIID, pin 4 to VCC, pin 5 is NoConnect - etc... - Hate to say it, but sounds like a data base :-P - ok an additional file type, *.msym for meta symbol. it should renumber a UIID to the same refdes. it should verify that a UIID is not over spent ( i.e. 5 slots on a 4 slot part ) it should list an under spent UIID - This would allow for post netlisting combinations. example in a design you have 16 sub modules that use 2 of 4 slots in a part, half of each share the same power nets, we should assist the collecting of the parts with the same power ground nets. - e.g. printout, or pop up a slot editor. with the following info. refdes U1, U2, U3, and U4 have spare slots and share the same power and ground This would require the schematic to physical stage to have a slotting tool that understood this. - this stage could output a slotting information report that PCB or other layout tools (humans) could read. - PCB could then allow for back annotating slot changes with the help of the report we should drop the refdes+letter notation going forward. - The suffix should be generated not defined as part of the refdef - I don't want U1a to point to the first slot then in U2a points to slot 3, unless you tie them together two locations can conflict/ confuse. e.g. a technician is debugging a part, they have worked on three stages, but each part calls it stage?/U1A well unfortunately each section being differently laid out had U1A being different slots. making shortcuts that are often taken they measured the wrong pins, because a b and c were pins 1 2 and 3 on U1 but 3 2 and 1 on U2. Just my 2 cents, but this should be defined in the library. For example, pins 1,2,3 of a particular opamp is always U?A, pins 5,6,7 is U?B and so on. -- Regards, Joerg http://www.analogconsultants.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Slot naming improvement methods.
On Jan 14, 2009, at 2:06 PM, Joerg wrote: Steven Michalske wrote: Hey gang, This is a proposal that seems to have gotten lost in a debate if gEDA is the right toolkit for someone. So here is a technical discussion on how we could IMPROVE gEDA. The proposal, please comment on lapses of functionality, and one sidedness as I use gEDA in PCB and spice 'n friends workflows When adding a slotted or multi part component it should have an attribute of an unique instantiation ID (UIID) that gets matched With the other symbols of that device instance. - have a ui pop up with this is a slotted/multi part device, - have options to add to existing instance, add new, or save for hierarchy compilation - have options for specific slot, next, undecided, or best slot This works into deeper capabilities, assisted slotting and multi symbol verification. To make slotting more robust to errors like U1a and U1b both having slot 1, To make sure that multi symbol parts have all their symbols, such as a microcontroller missing one of it's three sub symbols, it would warn the designer it should match each slotted device with it's UIID it should verify that each UIID is complete to it's devices rules. - i.e. a device of type X has the symbols of: one power symbol, one foo symbol, and one foo+power symbol. - There can only be upto 4 foo slots Not sure what foo means in this context but anyhow, the max number of slots for a library part should be kept high. Bus drivers, HV drivers and such can have dozens. this was meant as a specific example, not a defined max in the implementation. - there can be only one of the 4 foo slots with power. Sometimes there can be parts where supplies are split between two or more dies inside a package (multi-chip like). But this is very rare. interesting point, a non rare case would be bank powers on an FPGA - There must be one power connection Some parts do not have a power connection at all. For example resistor arrays or diode arrays. this is an example of a specific device X that has 4 slots of foo with one power connection method. those examples would not have a power sub symbol. - Spare slots should have a default connection scheme. slot pin 1,2,3 should be tied to GND of the power for this UIID, pin 4 to VCC, pin 5 is NoConnect - etc... - Hate to say it, but sounds like a data base :-P - ok an additional file type, *.msym for meta symbol. it should renumber a UIID to the same refdes. it should verify that a UIID is not over spent ( i.e. 5 slots on a 4 slot part ) it should list an under spent UIID - This would allow for post netlisting combinations. example in a design you have 16 sub modules that use 2 of 4 slots in a part, half of each share the same power nets, we should assist the collecting of the parts with the same power ground nets. - e.g. printout, or pop up a slot editor. with the following info. refdes U1, U2, U3, and U4 have spare slots and share the same power and ground This would require the schematic to physical stage to have a slotting tool that understood this. - this stage could output a slotting information report that PCB or other layout tools (humans) could read. - PCB could then allow for back annotating slot changes with the help of the report we should drop the refdes+letter notation going forward. - The suffix should be generated not defined as part of the refdef - I don't want U1a to point to the first slot then in U2a points to slot 3, unless you tie them together two locations can conflict/ confuse. e.g. a technician is debugging a part, they have worked on three stages, but each part calls it stage?/U1A well unfortunately each section being differently laid out had U1A being different slots. making shortcuts that are often taken they measured the wrong pins, because a b and c were pins 1 2 and 3 on U1 but 3 2 and 1 on U2. Just my 2 cents, but this should be defined in the library. For example, pins 1,2,3 of a particular opamp is always U?A, pins 5,6,7 is U?B and so on. In my imagination, the a b c would have been defined in the meta symbol, connecting them to the same pins would be good for locking them down. -- Regards, Joerg http://www.analogconsultants.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Slot naming improvement methods.
On Jan 14, 2009, at 2:08 PM, Steven Michalske wrote: Hey gang, This is a proposal that seems to have gotten lost in a debate if gEDA is the right toolkit for someone. So here is a technical discussion on how we could IMPROVE gEDA. The proposal, please comment on lapses of functionality, and one sidedness as I use gEDA in PCB and spice 'n friends workflows When adding a slotted or multi part component it should have an attribute of an unique instantiation ID (UIID) that gets matched With the other symbols of that device instance. The way gnetlist works, the refdes is the identifier. Changing this will break all of the back ends. - have a ui pop up with this is a slotted/multi part device, - have options to add to existing instance, add new, or save for hierarchy compilation - have options for specific slot, next, undecided, or best slot This works into deeper capabilities, assisted slotting and multi symbol verification. It breaks the paradigm: a program should do one thing well. To make slotting more robust to errors like U1a and U1b both having slot 1, To make sure that multi symbol parts have all their symbols, such as a microcontroller missing one of it's three sub symbols, it would warn the designer it should match each slotted device with it's UIID it should verify that each UIID is complete to it's devices rules. - i.e. a device of type X has the symbols of: one power symbol, one foo symbol, and one foo+power symbol. - There can only be upto 4 foo slots - there can be only one of the 4 foo slots with power. - There must be one power connection - Spare slots should have a default connection scheme. slot pin 1,2,3 should be tied to GND of the power for this UIID, pin 4 to VCC, pin 5 is NoConnect - etc... - Hate to say it, but sounds like a data base :-P - ok an additional file type, *.msym for meta symbol. it should renumber a UIID to the same refdes. it should verify that a UIID is not over spent ( i.e. 5 slots on a 4 slot part ) it should list an under spent UIID - This would allow for post netlisting combinations. example in a design you have 16 sub modules that use 2 of 4 slots in a part, half of each share the same power nets, we should assist the collecting of the parts with the same power ground nets. - e.g. printout, or pop up a slot editor. with the following info. refdes U1, U2, U3, and U4 have spare slots and share the same power and ground This would require the schematic to physical stage to have a slotting tool that understood this. - this stage could output a slotting information report that PCB or other layout tools (humans) could read. - PCB could then allow for back annotating slot changes with the help of the report we should drop the refdes+letter notation going forward. - The suffix should be generated not defined as part of the refdef - I don't want U1a to point to the first slot then in U2a points to slot 3, unless you tie them together two locations can conflict/ confuse. e.g. a technician is debugging a part, they have worked on three stages, but each part calls it stage?/U1A well unfortunately each section being differently laid out had U1A being different slots. making shortcuts that are often taken they measured the wrong pins, because a b and c were pins 1 2 and 3 on U1 but 3 2 and 1 on U2. Very complex. Stefan's simpler idea seems better to me. Hardkrash ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: temperature sensor
Hi, My temperature sensor/logger finaly works! http://logonex.eu/tc/ Red: The temperature of the air coming out of my server. Green: The temperature of my shirts hanging in the wardrobe. :-) Blue: The temperature of the air in my flat. The original plan was to place a sensor outside, but I was lazy to drill a hole through the frame of the window. This is the final board: http://logonex.eu/~leva/projects/temp_collector/ This is how it looks like: http://logonex.eu/gallery/tns/1043.html And the repository of files. http://logonex.eu/cgi-bin/viewvc/viewvc.cgi/temp_collector/ Cheers, -- Levente Kovacs http://logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
John Doty wrote: On Jan 14, 2009, at 1:49 PM, Joerg wrote: John Doty wrote: On Jan 14, 2009, at 12:44 PM, Joerg wrote: John Doty wrote: On Jan 13, 2009, at 5:12 PM, r wrote: BTW, analog IC guys long since have given up using implicit power connections Another sweeping statement from a narrow point of view, I think. A counter-example is in order: http://research.kek.jp/people/ikeda/openIP/ If you can't read Japanese, just look at the diagrams and SPICE subcircuits. Should be clear enough. Yes, no surprise there - schematics: http://research.kek.jp/people/ikeda/openIP/openIP_16.pdf Of course. For building blocks at this level, that's entirely appropriate. It's when you build complex multichannel systems from these blocks that schematics become incomprehensible. That's when we move over to block diagrams. Not just for chip designs, also for large board level designs. Sure. But you can't extract a netlist from a block diagram. So, you need something more. Easy enough with gEDA, as I've demonstrated. I can only speak for Orcad, but it does extract correct netlists from block diagrams. Because behind each block is a full schematic. Or on really fat designs another layer of blocks and then schematics. The key strength of gEDA here is that you can do this any way you need to for your specific project. Well, as we have seen with slotted parts, not any way it's needed. I think you're confusing wants and needs. It can do slotting just fine, but it can't read your mind. They will be messed up upon renumbering. But who knows, someday it might get fixed. I wrote a one-shot AWK script to renumber a particular design using slotted parts once. It had a bunch of limitations, so I never submitted it. Using hierarchy to divide the design up works better, don't have tricky renumbering problems there. But remember, fixed for you probably means broken for somebody else. Sure. As I said I just wanted to mention how a whole lot of other engineers design. 100% of all my clients, to be exact. But it can get there, which is why I mentioned the problem. If you wanted to, you could no doubt solve it with a little scripting (I'm still not sure exactly what you want: I can't read your mind either). But you'd have to cross a line you've drawn. gEDA is for those who enjoy crossing such lines, I think. Didn't draw a line, but I am not a programmer. That's the line. What makes you think you need to be a programmer to write programs? I'm not even an EE, I'm a physicist (at least that's what it says on my degrees). But whatever the job takes. Increasingly, design *is* programming. Software takes over from hardware as it can. Music synthesizers used to be racks of VCO's. Understanding when, where, and how to move that line is part of the job. Both in processes and products. Same here. EE by degree, must currently double-up as optics, metallurgy and mechanical stress analysis guy. Plus flooring guy. Wife said (since early last year ...) that the lab/office floors are too banged up and must be replaced. Flooring contractors said they won't do it unless I clean out the lab. Which I can't because of ongoing client projects. So ... Sure, I could figure it out and somehow attempt to fix it but there are people in this community who could do that a lot better. The one who has the clearest vision of what the problem is is often the best fixer. That's one of the strengths of free software. But when time is scarce one goes the path of least resistance until there is more free time. Which for me right now has to be to stick with the CAD I've got. Not optimal but works. -- Regards, Joerg http://www.analogconsultants.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Slot naming improvement methods.
On Jan 14, 2009, at 2:52 PM, John Doty wrote: When adding a slotted or multi part component it should have an attribute of an unique instantiation ID (UIID) that gets matched With the other symbols of that device instance. The way gnetlist works, the refdes is the identifier. Changing this will break all of the back ends. i did not say remove refdes. each part has an additional identifier for its brethren slotted parts, it UIID so if one gets renamed, they all have to be renamed. - if you edit the refdes attribute on a part with an UIID, gschem would want to rename all refdes's on the devices with the same UIID, a scheme hook could search the project for parts with the same UIID and rename them, asking the user of course. only users that wanted that hook loaded would get the additional feature. This works into deeper capabilities, assisted slotting and multi symbol verification. It breaks the paradigm: a program should do one thing well. gschem should make schematics well, since multiple slot/part symbols are in schematics, and they are broken, we don't do this part of schematics well, therefore we don't do schematic capture well. yea we have external renumber scripts, but when the renumber built into the gui breaks, it leaves a bad impression. Very complex. Stefan's simpler idea seems better to me. sounds complex, cause I gave lots of details, justifications, and examples. it should not be complex in implementation using the existing device attribute, we make a matching device.msym file each sub symbol would have to have the same device attribute. the msym file has the contents that explains the rules. it could even use Stefan's notation of SubParts=Bank0, Bank1, Power or wrap it into each symbol instead of the .msym SubParts=Bank0, Bank1, Power SubPart=Bank0 UIID=unassigned but putting it into each symbol leads to an issue of mismatched constraints and affects everyones symbols who may not care for the new system. the new system would be scheme hooks and an additional msym file and can use old symbols with out editing Now that the meta data is stored. When we place a component we call the place component scheme hook to check the for other parts of that device type, check for other UIIDs, if we find others, we either add to one of the found UIIDs, or make a new one. we then check to see if adding that part would break rules. e.g. only one BANK1 on a FPGA etc... when we rename a part, have a hook there that calls the script to check for the UIIDs if there are matching UIIDs ask if we want to renumber all of the UIIDs or split the part. with an attribute edit, i have an attribute that specifies if pick and place should be skipped for a part, that attribute should be the same on all of the symbols. the UIID isn't required, but helps. in gnetlist, stuff to check the refdes, UIID, and device.msym would go there as well. All of this could be done with out the UIID, but then there is no book keeping for gEDA. The UIID is to be set by tools, not by human entry, the whole point of the UIID is to allow the tool to track that instance of a device. in other words, the hooks and scripts could check refdes,device, and UIID or just refdes and device; but it breaks when the designer changes only one of the refdeses. A UIID being a managed attribute is robust against oversight. except in a text editor ;-) Hardkrash ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
Stefan Salewski wrote: Am Dienstag, den 13.01.2009, 13:11 -0800 schrieb Joerg: I started out with Futurenet Dash-2 in 1986, then Dash-4, then self-employed with Orcad as my tool, later through several versions of that and a few years ago switched to Eagle. That's what I am using right now until I find something better. Eagle won't handle hierarchies, other than that it is nearly ideal. Here in Germany many people think that Eagle is only usable for simple home-made stuff, not for professionals. At least in Forums like www.mikrocontroller.net. If you ask What EDA tool should I by for my small Company they will recommend names like PADS, Cadence, Altium, and say that Eagle is more for kids. This is not my opinion, I used Eagle years ago and never the other more expensive tools. But you see opinions are different. Eagle is IMHO pretty good but it does have one major disadvantage: No hierarchy support. That pretty much restricts it to smaller projects. To my surprise Cadsoft has never picked up on suggestions to fix that, version 5 doesn't have it, maybe their program structure has hemmed them in. One thing I am going to do is fire up the old DOS-OrCad again. To my surprise people have written new graphics drivers and stuff for it. If I can also get it to print well on new machines it would be time to crack out the champagne. Well, maybe beer. And one remark: When I go to my local Volkswagen dealer and tell hin how fine my Mercedes is and that I have no desire to drive a Volkswagen, only come to tell him how he may improve them ... My intentions may be good, but my strategy is not. Yeah, but: In medical electronics we listen very, very carefully to cardiologists when they talk about competitor gear. This is not to copy, but so we can continually optimize and improve our own products. Companies that do not engage in such listening tend not to last very long in the marketplace. It is really important to know what other groups or organization do wrong and what they do right. And most of all, to find out why that is the case. Since you mentioned cars, I think this is one reason why several companies are facing serious financial issues. They did not listen and now others are eating their lunch. -- Regards, Joerg http://www.analogconsultants.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: compiling gaf from git repos
On Wed, 2009-01-14 at 21:22 +, Kai-Martin Knaak wrote: On Wed, 14 Jan 2009 20:30:59 +, Peter Clifton wrote: Try installing newer libtool. Hmm. The libtool version I have installed is identical to the one in debian/sid (v1.5.26) There is v2.26 in debian/experimental. However, apt- get wants to remove guile-1.8 -- not good. If that fails, try removing both the [shared] and [win32-dll] options. Where are the offending options? Can't grep win32-dll in config.h.in, or anywhere else in the source. libgeda/configure.ac.in Try just LT_INIT([win32_dll]) LT_INIT([shared]) and LT_INIT() Please report back which (perhaps more than one) of these work. If not, change the line for the old (deprecated - although I don't know when) syntax: AC_LIBTOOL_WIN32_DLL AM_PROG_LIBTOOL If that _still_ doesn't work (and it really ought to), drop the: AC_LIBTOOL_WIN32_DLL line. I'm really interested to hear feedback on which of the above methods work for you. If its too much of a burden, I'll put the old (deprecated) syntax back. Might be good to hold back until debian unfreezes... Sure, I mistakenly didn't think to discover exactly when the deprecated AC_LIBTOOL_WIN32_DLL / AM_PROG_LIBTOOL syntax was actually deprecated. Actually, perhaps AM_PROG_LIBTOOL isn't deprecated, and is needed as well as LT_INIT.. I'm just not sure. I've got to go now, but will be back Friday. Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
Am Mittwoch, den 14.01.2009, 16:40 -0800 schrieb Joerg: Eagle is IMHO pretty good but it does have one major disadvantage: No hierarchy support. That pretty much restricts it to smaller projects. To my surprise Cadsoft has never picked up on suggestions to fix that, version 5 doesn't have it, maybe their program structure has hemmed them in. OK, Eagle is one of the cheapest commercial programs, there are much more expensive Tools available, for more than 1$. These tools must have some benefits. Indeed my impression was that not many professionals uses Eagle, indeed I was surprised that you are using it. I have worked only with Eagle 4.x for a short time years ago at university. I heard that 5.x has not much improvements. Some people say that it is good enough and that Cadsoft prefers to earn some money without spending much effort in improvement. Eagle is popular because it has a limited edition which is available without costs, and works for Windows and Linux. Yeah, but: In medical electronics we listen very, very carefully to cardiologists when they talk about competitor gear. This is not to copy, but so we can continually optimize and improve our own products. Companies that do not engage in such listening tend not to last very long in the marketplace. It is really important to know what other groups or organization do wrong and what they do right. And most of all, to find out why that is the case. Yes, I fully agree. I am interested how KiCad and other commercial Tools do their work. And I think many people on this list are. But I can understand that developers, who has spend very much work in the gEDA tools feel bad when someone writes something like My tool does this much better. I do not really want to use your tool, but I strongly advice you to do it the same way. Sometimes it's not easy to find the right wording. Best regards Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
Stefan Salewski wrote: Am Mittwoch, den 14.01.2009, 16:40 -0800 schrieb Joerg: Eagle is IMHO pretty good but it does have one major disadvantage: No hierarchy support. That pretty much restricts it to smaller projects. To my surprise Cadsoft has never picked up on suggestions to fix that, version 5 doesn't have it, maybe their program structure has hemmed them in. OK, Eagle is one of the cheapest commercial programs, there are much more expensive Tools available, for more than 1$. These tools must have some benefits. Indeed my impression was that not many professionals uses Eagle, indeed I was surprised that you are using it. Well, Windows-OrCad has crashed on me too many times and that ticked me off. But what really ticked me off was when they wanted to only sell it with a service contract, not without. I saw lots of potential in Eagle and was hoping they'd understand that a missing hierarchy is a serious market hurdle for them. And then they didn't :-( I have worked only with Eagle 4.x for a short time years ago at university. I heard that 5.x has not much improvements. Some people say that it is good enough and that Cadsoft prefers to earn some money without spending much effort in improvement. Eagle is popular because it has a limited edition which is available without costs, and works for Windows and Linux. Yeah, but: In medical electronics we listen very, very carefully to cardiologists when they talk about competitor gear. This is not to copy, but so we can continually optimize and improve our own products. Companies that do not engage in such listening tend not to last very long in the marketplace. It is really important to know what other groups or organization do wrong and what they do right. And most of all, to find out why that is the case. Yes, I fully agree. I am interested how KiCad and other commercial Tools do their work. And I think many people on this list are. Kicad isn't commercial. Like all CAD programs it has drawbacks and advantages. The way it handles library parts and slots is something that I think would be very useful for a gEDA software developer to take a good look at. It may not be the most intuitive way, has a learning curve, but it is very flexible. But I can understand that developers, who has spend very much work in the gEDA tools feel bad when someone writes something like My tool does this much better. I do not really want to use your tool, but I strongly advice you to do it the same way. Sometimes it's not easy to find the right wording. You should sit in on one of those meetings with medical folks. They can be pretty blunt. So what do you think about our XYZ gizmo? ... It sucks. ... Oh, ahem, well, can you elaborate a bit on that? What I want to say is This tool does x better. I and a lot of others can't use your tool because of it and here is how I think this could be fixed. But I can only say it from the position of a user, not as a programmer because that's the domain of the experts here. -- Regards, Joerg http://www.analogconsultants.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: compiling gaf from git repos
[snip] AC_LIBTOOL_WIN32_DLL AM_PROG_LIBTOOL I didn't try the AC_LIBTOOL_WIN32_DLL line, but I did revert back to the original AM_PROG_LIBTOOL only line. -Ales ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: temperature sensor
Levente Kovacs wrote: Hi, My temperature sensor/logger finaly works! http://logonex.eu/tc/ Red: The temperature of the air coming out of my server. Green: The temperature of my shirts hanging in the wardrobe. :-) Blue: The temperature of the air in my flat. You are heating your flat to 24C? Wow. So don't point to us in America that we'd be wasting too much energy ;-) [...] -- Regards, Joerg http://www.analogconsultants.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Slot naming improvement methods.
Steven Michalske wrote: i did not say remove refdes. each part has an additional identifier for its brethren slotted parts, it UIID so if one gets renamed, they all have to be renamed. - if you edit the refdes attribute on a part with an UIID, gschem would want to rename all refdes's on the devices with the same UIID, a scheme hook could search the project for parts with the same UIID and rename them, asking the user of course. This option could be a config setting to be normally on or not. That would allow for searching through your data for objects in different cells to act on them. Like the chip design tools allow. It could be used well by a refdes-renumber program that acts on whole hierarchies at a time. Or just to find a set of things by attribs with some logic to match them: (a*b*c) + (d*e) + a*(f+h) etc... John -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: compiling gaf from git repos
On Thu, 15 Jan 2009 00:51:17 +, Peter Clifton wrote: libgeda/configure.ac.in Try just LT_INIT([win32_dll]) LT_INIT([shared]) Configure complains if any of these lines is present. LT_INIT() This got me beyond the configure step. But make install gets stuck further down the line: $ make install (...) make[3]: Leaving directory `/usr/local/geda-src/gaf/libgeda/share' make[2]: Leaving directory `/usr/local/geda-src/gaf/libgeda/share' Making install in src make[2]: Entering directory `/usr/local/geda-src/gaf/libgeda/src' make[2]: LIBTOOL@: Command not found make[2]: *** [a_basic.lo] Error 127 make[2]: Leaving directory `/usr/local/geda-src/gaf/libgeda/src' make[1]: *** [install-recursive] Error 1 make[1]: Leaving directory `/usr/local/geda-src/gaf/libgeda' make: *** [libgeda_install] Error 2 So I tried the next recipe: AC_LIBTOOL_WIN32_DLL AM_PROG_LIBTOOL With these options the current git-head compiled and installed fine. Thanks for the detailed advice. When started gschem presents a GUI with a black background, although my local gsemrc configures a light background with the line (load (build-path geda-rc-path gschem-lightbg)) The log file contains this message: (...) Read system-gschemrc file [/usr/local/share/gEDA/system-gschemrc] In unknown file: ?: 0* [primitive-load /usr/local/share/gEDA/] In /usr/local/share/gEDA/gschem-lightbg: 60: 1* (background-color 0 grey94 null 1 1 1) /usr/local/share/gEDA/gschem-lightbg:59:0: Unbound variable: background-color Read ~/.gEDA/gschemrc file [/home/kmk/.gEDA/gschemrc] (...) The same message appears if I change gschem-lightbg to gschem-darkbg. Seems like gschem does not like the variable background-color. ---(kaimartin)--- -- Kai-Martin Knaak http://lilalaser.de/blog ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
On Jan 14, 2009, at 6:43 PM, Joerg wrote: But I can only say it from the position of a user, not as a programmer because that's the domain of the experts here. Back in 1969, I was taught that the purpose of Fortran was to erase this distinction, putting the power of the computer into the hands of the those who really understand the problems to be solved. I remain of the opinion that this is a destructive distinction to make. This tradition is alive and well in programming languages like Perl and Python (and Fortran is still used by many scientists). gEDA is part of this tradition. If, instead, you see yourself as the sort of user who is merely a consumer of programming, I think gEDA will never satisfy you. I also believe that the future of mixed- signal engineering will belong to those who can combine skills in applied physics with programming, as software moves into areas traditionally handled by circuits, and the complexity of designs exceeds the capacity of humans to handle without computer assistance. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
John, That was eloquently said. I would suggest that geda/gaf users at a minimum should attempt to understand the scripting language scheme and its interface to gaf. Steve Meier On Wed, 2009-01-14 at 20:30 -0700, John Doty wrote: On Jan 14, 2009, at 6:43 PM, Joerg wrote: But I can only say it from the position of a user, not as a programmer because that's the domain of the experts here. Back in 1969, I was taught that the purpose of Fortran was to erase this distinction, putting the power of the computer into the hands of the those who really understand the problems to be solved. I remain of the opinion that this is a destructive distinction to make. This tradition is alive and well in programming languages like Perl and Python (and Fortran is still used by many scientists). gEDA is part of this tradition. If, instead, you see yourself as the sort of user who is merely a consumer of programming, I think gEDA will never satisfy you. I also believe that the future of mixed- signal engineering will belong to those who can combine skills in applied physics with programming, as software moves into areas traditionally handled by circuits, and the complexity of designs exceeds the capacity of humans to handle without computer assistance. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Renumbering Reference Designators
I am working on a schematic and cut and pasted different pieces from different schematics. The numbering is a mess. But neither grenum or renum_refdes will renumber it. Is there a way to make it renumber like with --pageskip if the reference designators already have a number? (ie C1 as opposed to just C?) It looks like if the part already has a number, neither renumber program touches it. That is good in most cases, but not in my case. Is there a secret way to force a renumber no matter whether the part has a reference designator number or not? Failing that, is there an easy way to change all reference designators from Letter Number to Letter ? so I can renumber? Kip -- Kipton Moravec AE5IB Always do right; this will gratify some people and astonish the rest. --Mark Twain ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: compiling gaf from git repos
Peter Clifton wrote: On Wed, 2009-01-14 at 21:22 +, Kai-Martin Knaak wrote: On Wed, 14 Jan 2009 20:30:59 +, Peter Clifton wrote: Try installing newer libtool. Hmm. The libtool version I have installed is identical to the one in debian/sid (v1.5.26) There is v2.26 in debian/experimental. However, apt- get wants to remove guile-1.8 -- not good. If that fails, try removing both the [shared] and [win32-dll] options. Where are the offending options? Can't grep win32-dll in config.h.in, or anywhere else in the source. libgeda/configure.ac.in Try just LT_INIT([win32_dll]) LT_INIT([shared]) and LT_INIT() Please report back which (perhaps more than one) of these work. If not, change the line for the old (deprecated - although I don't know when) syntax: AC_LIBTOOL_WIN32_DLL AM_PROG_LIBTOOL If that _still_ doesn't work (and it really ought to), drop the: AC_LIBTOOL_WIN32_DLL line. I'm really interested to hear feedback on which of the above methods work for you. If its too much of a burden, I'll put the old (deprecated) syntax back. Might be good to hold back until debian unfreezes... Sure, I mistakenly didn't think to discover exactly when the deprecated AC_LIBTOOL_WIN32_DLL / AM_PROG_LIBTOOL syntax was actually deprecated. Actually, perhaps AM_PROG_LIBTOOL isn't deprecated, and is needed as well as LT_INIT.. I'm just not sure. I'm pretty certain the OP's problem is that older libtools did not provide the LT_INIT macro. Hence you got the unexpanded macro in the configure script. libtool-1.5.22 which is what I have on my development machine does *not* have LT_INIT. I'm not sure when LT_INIT went in. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Renumbering Reference Designators
On Wed, 14 Jan 2009 23:32:50 -0600, Kipton Moravec wrote: It looks like if the part already has a number, neither renumber program touches it. That is good in most cases, but not in my case. Is there a secret way to force a renumber no matter whether the part has a reference designator number or not? Maybe you missed the autonumber dialog at the bottom of the attributes menu. There are lots of useful options in there. One of them is a check box Overwrite existing numbers. IIRC, this dialog was introduced in 2007. Failing that, is there an easy way to change all reference designators from Letter Number to Letter ? so I can renumber? None that I know. ---(kaimartin)--- -- Kai-Martin Knaak http://lilalaser.de/blog ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Renumbering Reference Designators
Is there a way to make it renumber like with --pageskip if the reference designators already have a number? (ie C1 as opposed to just C?) refdes_renum should do this. The --gentle flag is enabled by default (i.e. only renumbers C? style refdes's). Use the --force flag to force it to renumber all refdes's. I think the online docs are out of date. refdes_renum accepts the following options: --help Displays this help message. --nocopyIf given, this flag leaves the modified files in new files whose names are generated by appending a .renum to the original file names. The default is to overwrite the original. --pgskipWhen this flag is used, components on the first schematic sheet are numbered starting with 101. On the second sheet, they start with 201, etc Specifying a value gives the step between pages. For example --pgskip 10 will start with 11, 21, 31, etc. --gentleThis flag tells refdes_renum to leave any refdeses alone if they already have numbers. Use this option to number new components in a schematic which has already been numbered. Note that --gentle is set by default! --force Set this flag to renumber all refdeses, whether they are already numbered or not. --verbose Enables verbose output. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
