Re: gEDA-user: gEDA new home on the 'net and other good changes...
On Sat, Feb 07, 2009 at 08:11:09PM -0500, Ales Hvezda wrote: Hi, Recent good news/changes: * The gEDA's project's homepage has moved. The new address is: http://www.gpleda.org I have moved most things except the mailing list archives and the wiki. Please report any problems or broken links. In theory I have setup (correctly) redirection (301) on the geda.seul.org, so if you flush your web cache, you should be redirected to the new site automatically. Let me know if that doesn't work for you. * The PCB project has a new webpage too! The new address is: http://pcb.gpleda.org * The PCB project has also moved to using git. The git repository can be browsed at: http://git.gpleda.org/?p=pcb.git;a=summary That's really good news. CVS feels so prehistoric and I'm a step closer to removing it from my machines. Now if only gerbv could also move... Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Problems cloning from git.gpleda.org
Hi there, Has something changed in the configuration of the git server in the changes of the last week? I now cannot clone from the repo at one of my machines: gar...@xdcnb047-vbox:~/devel/temp$ !406 git clone http://git.gpleda.org/gaf.git Initialized empty Git repository in /home/gareth/devel/temp/gaf/.git/ warning: remote HEAD refers to nonexistent ref, unable to checkout. Same for pcb.git. This machine is a bit of an oddball - it's at work so it's a virtualized Ubuntu guest on a Windows host, running behind a proxy (hence http: rather than git:). Proxy setup is AFAIK fine, I was happily git pulling the gaf tree until a couple of weeks back - but I suppose it might have been the proxy that has changed rather than gpleda.org. Any pointers welcome. Cheers Gareth ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA new home on the 'net and other good changes...
On Sat, 07 Feb 2009 20:11:09 -0500, Ales Hvezda wrote: * The PCB project has also moved to using git. Is gedasymbols.org going to switch to git, too? ---(kaimartin)--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Is gedasymbols.org going to switch to git, too?
Kai-Martin Knaak wrote: Is gedasymbols.org going to switch to git, too? DJ has some automation scripts creating user parts of gedasymbols.org, so it would be an effort to change it. Probably not worth the change effort for the minor developing done on symbols and footprints. Git may be more valuable for managing the history of the rest of the scripts and documentation writing there. Is there a git feature that is useful for showing the history and testing status of footprints or symbols? As in, used to make a board well used to make a pick and placed board well tweaked and optimized for IR solder paste applied with stencil of .011 inch thickness, etc., etc. Git seems useful for many contributors to use, and that is a match for symbol and footprint repositories. JG -- Ecosensory Austin TX tinyOS devel on: ubuntu Linux; tinyOS v2.0.2; telosb ecosens1 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: select all pins
Hello, How coudl I select all pins ? I try select by name, then pins, but it ask me for a pattern, I try nothing or * but I never been successfull. Thank -- --- == Patrick DUPRÉ | | Department of Chemistry| |Phone: (44)-(0)-1904-434384 The University of York | |Fax: (44)-(0)-1904-432516 Heslington | | York YO10 5DD United Kingdom | |email: pd...@york.ac.uk == ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: select all pins
Patrick Dupre wrote: Hello, How coudl I select all pins ? I try select by name, then pins, but it ask me for a pattern, I try nothing or * but I never been successfull. Don't know that. I use select by area with shift key so it adds to current selected set. JG ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA new home on the 'net and other good changes...
Is gedasymbols.org going to switch to git, too? I have no plans to do so. CVS may be archaic, but it's plentiful and low overhead. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: select all pins
On Mon, 09 Feb 2009 16:34:32 +, Patrick Dupre wrote: How coudl I select all pins ? I try select by name, then pins, but it ask me for a pattern, I try nothing or * Precede the asterisk with a full stop. The pattern .* will select all pins on the layout. The pcb manual contains a section on how to use regular expressions in search patterns: http://pcb.gpleda.org/pcb-cvs/pcb.html#Regular-Expressions ---(kaimartin)--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: schematic driven gnucap work flow gaps
I'm testing gnucap and cam across a desire to autogenerate symbols from structural verilog module definitions. Does anyone have a symbol generator ready to go from structural verilog to gschem symbol? The handy symbol-generation-from-shorthand scripts djboxsym and derived jgboxsym assume pinnumber is a number. For many simulation versions of components it is helpful to label pins p and n instead of 1 and 2 to designate polarity clearly. Alpha pin numbers are used in many chip packages, so...it's a feature we would like to use... John Griessen -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gwave: building on openSUSE, various comments
Hi Steve, On Montag, 9. Februar 2009, steve tell wrote: On Sun, 8 Feb 2009, Werner Hoch wrote: thanks very much for the detailed report, and for the patch. I've applied the patch, and plan to look at the runtime warnings soon. Thanks. If you have a tiny ngspice ascii rawfile that fails that you can send, I'll take a look at the spicefile reader. Sadly, the spice rawfile format is not defined in any written documentation than I know about - not much better than the proprietary spices in that regard. At least we have the code to look at. Yup, that's the way I wrote spice file readers, too. I've attached a package with all the simulations I've used to test my python import utility. http://www.h-renrew.de/h/python_spice/spicedata.html You can create all data files with the Makefile or run the simulations individually with ngspice. Regards Werner testcircuits.tar.gz Description: application/tgz ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Yet another footprint generator available
I just put yet another pcb footprint generator on my homepage, see http://www.ssalewski.de/SFG.html.en It is similar to footgen.py of Darrell Harmon. While making this generator I wrote a short summary of recent pcb footprint format, available at http://www.ssalewski.de/PcbFootprintRef.txt The edge2 flag is not supported by my generator currently -- I have never understood the correct use of this flag, and I have not seen any result if I include it... I think footprints will work without it, maybe I will modify the program later to use it. If someone manages to see a result which these edge2 flag makes I would be happy to see a picture of it. I think it should have an effect for pin- and pad-numbers shown inside pcb program, but I never manage to see an effect. Please note: My footprint generator program is nearly untested now. Currently I have all the footprints I need, so I think I will not do much testing in the next months myself... Best wishes Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Yet another footprint generator available
The edge2 flag is not supported by my generator currently -- I have never understood the correct use of this flag, and I have not seen any result if I include it... I suspect it's mostly used for the pinout window - it tells you which way to orient the text, by keeping track of where the pin/pad is relative to the center of the element. For pins, it's a horiz/vert flag, for pads it's the end furthest from the center. There is logic in pcb to automatically set these when the bounding box is computed, so it's likely you don't need to worry about them. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gEDA-dev: Polygon transparency
Not completely satisfied with either my GL branch's translucent rendering of layers, nor thindraw poly, I decided to make a hybrid.. http://www2.eng.cam.ac.uk/~pcjc2/geda/trans_poly.png The code to do this isn't yet in the GL branch (since it was a hideous HID abstraction breaking hack at the moment... I wanted it quickly whilst finishing off a board design). Performance isn't great (you pay for both rendering the polygons, _and_ their outlines (thin-draw poly is _slower_ than non-thin draw on the GL branch). In spite of this though, I found working with this much ore productive, as it allows me to much easier differentiate between routing resources (e.g. polygon covered board area) I can plough through. Somehow thin-draw poly looses context for me, and I find it difficult to do routing work whilst in that mode.. the hybrid seemed more usable. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-dev mailing list geda-...@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: xgsch2pcb demo videos
Hi guys, I was just filing some things into my gEDA_screenshots directory, and came across some .ogg screencasts which haven't really seen the light of day. I made these rehearsing a screencast demonstration for an undergraduate robot design course. I never did the real, mistake-free screen-cast, but I thought I'd link these here anyway. They show off xgsch2pcb for those who've never seen it, show off basic gEDA usage, (and watching them back), various basic gEDA mistakes, and workflow inefficiencies. (And I'm a gEDA developer, so looking at myself making those mistakes is painful!). DJ, perhaps you'll note how bad an idea it is for xgsch2pcb to drop components into the top corner of the schematic! http://www2.eng.cam.ac.uk/~pcjc2/geda/xgsch2pcb_demo.ogg ( 8M) http://www2.eng.cam.ac.uk/~pcjc2/geda/xgsch2pcb_idp_demo.ogg (11M) http://www2.eng.cam.ac.uk/~pcjc2/geda/xgsch2pcb_idp_demo2.ogg (26M) Perhaps watching people working like this, and making real mistakes gives clues to where the workflow is non-intuitive, or fragile. Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gnetlist verilog back end gnet-verilog.scm
This is probably a Mike Jarabek question: I don't get usable hierarchic netlist output when I have placed schematics and use the gnet-verilog.scm back-end. It drops the module definitions and endmodule statements of the placed symbols that refer to schematics. So, is that the normal behavior, and I need to not use hierarchy, and run gnetlist on every schematic, then cat them together? There seems to be no existing gnetlist concatenate function. Would handling this in scheme be difficult? By this I mean taking all the files referred to by source= attribs and running gnet-verilog.scm on each in order, then putting that to the gnetlist output. gnet-verilog.scm is ready to create a one level netlist -- one module's worth of verilog. Using a makefile is the obvious thought. Make could just take a list or all .sch in a dir and run them and cat them together to a filename. Handling it without make complexity separate from the back end chosen would be nice though, so I ask, Anyone seen existing scheme code that could use source=verilog_io.sch to trigger running it again on the referenced file then outputting that to the same place as usual? Thanks, John Griessen -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: order of defparam vs. #(.) parameters in icarus
In some Xilinx models, they make instantiations like this: block instance(ports); defparam instance.param=VALUE This normally works ok. The problem is that inside the block, generate statements are being used which are dependent on the value of the parameter. What appears to be happening is that the block is instantiated, and before the defparam line is executed, the decisions are made with the default value of the parameter. Is this a bug in Icarus or in the Xilinx models? I can send an example that illustrates this if necessary. Thanks, Matt ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problems cloning from git.gpleda.org
[snip] Has something changed in the configuration of the git server in the changes of the last week? I now cannot clone from the repo at one of my machines: Yes, I made a change which affected http git access. I have re-enabled git access via http. Please try again. -Ales ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problems cloning from git.gpleda.org
On Mon, 2009-02-09 at 19:25 -0500, Ales Hvezda wrote: [snip] Has something changed in the configuration of the git server in the changes of the last week? I now cannot clone from the repo at one of my machines: Yes, I made a change which affected http git access. I have re-enabled git access via http. Please try again. You should be careful to avoid pulling from that method too frequently though, as comparative to the git:// method, it can be a bandwidth hog. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gnetlist verilog back end gnet-verilog.scm
Hi John, There is a BASH script geda_hier_tools.bsh to generate Hierarchical Verilog netlist with example that I posted last month: http://archives.seul.org/geda/user/Jan-2009/msg00056.html Note that you need to have your gnetlistrc in each of those Verilog project to contain: (hierarchy-traversal disabled) This is needed, because Verilog needs a non-flatten hierarchy. The example shows that. Hope that helps Best Regards, Paul Tan -Original Message- From: John Griessen j...@ecosensory.com To: gEDA user mailing list geda-user@moria.seul.org Sent: Mon, 9 Feb 2009 1:22 pm Subject: gEDA-user: gnetlist verilog back end gnet-verilog.scm This is probably a Mike Jarabek question: I don't get usable hierarchic netlist output when I have placed schematics and use the gnet-verilog.scm back-end. It drops the module definitions and endmodule statements of the placed symbols that refer to schematics. So, is that the normal behavior, and I need to not use hierarchy, and run gnetlist on every schematic, then cat them together? There seems to be no existing gnetlist concatenate function. Would handling this in scheme be difficult? By this I mean taking all the files referred to by source= attribs and running gnet-verilog.scm on each in order, then putting that to the gnetlist output. gnet-verilog.scm is ready to create a one level netlist -- one module's worth of verilog. Using a makefile is the obvious thought. Make could just take a list or all ..sch in a dir and run them and cat them together to a filename. Handling it without make complexity separate from the back end chosen would be nice though, so I ask, Anyone seen existing scheme code that could use source=verilog_io.sch to trigger running it again on the referenced file then outputting that to the same place as usual? Thanks, John Griessen -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
