Re: gEDA-user: hierarchy and refdes_renum
Hi Alex, please download the newest spnet on my site and let me know
how it goes, it should be a bit more compatible.
Here is whats new:
* Comments in both .spnetlibs and .spentrc (# is the comment character)
* Won't bail out on empty lines in either file above
* NMOS_TRANSISTOR and PMOS_TRANSISTOR as 4 terminal mosfets
* It doesnt matter if a component has brackets or not like in your
original example. If there is no brackets (therefore no attributes)
the component is ignored.
* All power symbols that come with gschem now work properly
Eager to here how this new version works and how compatible it is. In
the next release (perhaps tomorrow) I will add the support to pull
librarys already defined in gedarc files. Will also try to add autonet
naming for unnamed nets.
-Anthony
On Tue, Jun 23, 2009 at 2:46 PM, Anthony Shanksyamazak...@gmail.com wrote:
Are titleblocks legal (without lack of a better term) without
brackets or were they just that way in your schematic for some reason?
I thought all components had brackets but maybe only components with
attributes have brackets?
I took a look at v2i_2v.sym, it doesn't look like it has any schematic
file attached to it. Also spnet requires subckts with lower level
schematics to have the attribute to device=SUBCKT. There is no
standard attribute in the gEDA flow to define a subckt so thats what I
choose for spnet. Take a look at my latch example on my website for
what the properties of subckts look like.
Net stitch failure happens usually when there is a net without a
netname attached to one of the nets its connected too. There is no
autonet name feature yet but I plan to add it.
Also which devices in your schematic don't have refdes?
-Anthony
On Tue, Jun 23, 2009 at 1:59 PM, A.Burinskiyalexb...@gmail.com wrote:
Hi Anthony,
The reason for the message
-E- Fatal Error: Invalid Component attr C 42200 44200 1 0 0 gnd-1.sym
Was that first component, that is title-B block listed in the
test_v2i_2.sch without pair of { } !
Symbol spice-lib.sym is a special symbol. I did it. I think netlister
should support custom symbols.
v 20090328 2
B 0 400 1900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 100 300 9 10 0 1 0 0 1
device=library
T 100 500 9 10 1 1 0 0 1
refdes=A?
T 600 500 9 10 1 0 0 0 1
SPICE LIBR
T 500 200 8 10 1 1 0 0 1
file=?
T 100 200 9 10 1 0 0 0 1
File:
T 0 -5 8 10 1 0 0 0 1
corner=TYP
And v2i_2v.sym is real subcircuit.
After artificially adding this braces I've got (please note, that
(42300;44500) corresponds to connection point of gnd symbol pin)
$ spnet test_v2i.sch
spNet v0.9.1.2
gEDA/gschem Netlister
Copyright 2009 Anthony Shanks
-I- Starting Build of Cell: test_v2i
-I- Adding Library: sym
-I- Adding Library: power
-I- Combining Cells
-W- Device in cell test_v2i does not have a refdes, ignoring.
-W- Device in cell test_v2i does not have a refdes, ignoring.
-E- Net stitch failure in cell test_v2i near point 42300,44500.
Thanks,
Alex.
On 06/23/2009 10:54 AM, Anthony Shanks wrote:
Hmm, a few things.
Is that ground symbol the default that comes with gschem (device=none,
netname=0)? Can't look right now, at work.
I also noticed a few things in your schematic that is definitely not
supported (right now):
C 47000 49500 1 0 0 spice-lib.sym
C 5 44900 1 0 0 v2i_2v.sym
What are these? I assume the spice-lib.sym is a subckt netlist but I
don't know what the other is.
A quick fix in your case with the ground symbol is just to add the
attribute device=globalnode and net=0.
-Anthony
On Tue, Jun 23, 2009 at 10:00 AM, A.Burinskiyalexb...@gmail.com wrote:
Hi Anthony,
Yes, there is device that is not in the list and this is ground symbol.
Please find diff file and test_v2i.sch attached. That is what I have
(Please
note, that your search for '=' sign, while there is no any '=' sign in the
string...)
$ spnet test_v2i.sch
spNet v0.9.1.2
gEDA/gschem Netlister
Copyright 2009 Anthony Shanks
-I- Starting Build of Cell: test_v2i
-I- Adding Library: sym
-I- Adding Library: power
-I- Combining Cells
-E- Fatal Error: Invalid Component attr C 42200 44200 1 0 0 gnd-1.sym.
$ more ~/.spnetlibs
library: /home/username/tsmc sym
library: /usr/local/share/gEDA/sym power
On 06/23/2009 09:39 AM, Anthony Shanks wrote:
Comments are not supported yet, it's on the todo list.
Is the new code working yet? the invalid compoent error will come up
with there is a symbol in your schematic without a valid device
attribute. Here is a list of devices that are current supported
(device=)
RESISTOR
CAPACITOR
INDUCTOR
NPN_TRANSISTOR
PNP_TRANSISTOR
NMOS3T
NMOS4T
PMOS3T
PMOS3T
SUBCKT
VOLTAGE_SOURCE
CURRENT_SOURCE
PIN
As stated I will add suport for [N|P]MOS_TRANSISTOR in the next
release as a 4 terminal mosfet device. Besides this, do you have any
components in your
Re: gEDA-user: Multivibrator Simulation
Hi Micheal, Sorry about that, Al Davis is right, OFF doesn't seem to help. Here are two ways to fix the problem. 1) As has already been described, if you start the simulation with the supply voltage at 9V but apply an initial condition of 0V to one of the transistor bases - using the .IC spice directive - then oscillation should start. The initial condition forces one transistor off while the other is on and then lets it go. This then starts the first cycle at time zero. Here's a netlist that does that: --- V1 V1_P 0 9 R1 V1_P R1_N 15k R2 V1_P R2_N 15k R3 V1_P R3_N 1K R4 V1_P R4_N 1K .IC V(R2_N)=0 ; this is the initial condition Q1 R3_N R2_N 0 0 Q2N3904 Q2 R4_N R1_N 0 0 Q2N3904 C1 R1_N R3_N 10u C2 R4_N R2_N 10u --- 2) Alternatively, if you do two things, it will start oscillating. i) make the 9V supply ramp up from zero at the start of the simulation. A short rise time of about 100n should be OK. ii) make one of the base resistors slightly different from the other. A difference of even 1 Ohm will do it. This adds a slight imbalance to an otherwise perfectly balanced circuit. The supply ramp up than acts to turn one transistor on slightly before the other setting up the initial conditions for the first cycle just after time zero. And here's a netlist that does that: --- V1 V1_P 0 Pulse(0 9 0 100n 100n) ; this is the supply ramp R1 V1_P R1_N 15k R2 V1_P R2_N 15.001k ; this is the base resistor imbalance. R3 V1_P R3_N 1K R4 V1_P R4_N 1K Q1 R3_N R2_N 0 0 Q2N3904 Q2 R4_N R1_N 0 0 Q2N3904 C1 R1_N R3_N 10u C2 R4_N R2_N 10u --- Try running them for about 500ms to see how the oscillations start up. I've not used gnucap or ngspice yet so I'm not familiar with how you drive them. You may need to add the transistor models to my netlists. --- .model Q2N3904 npn ( IS=2.48E-13 VAF=101.7 BF=400 IKF=0.0334 NE=1.5243 +ISE=2.113E-12 IKR=0.02 ISC=5.00E-12 NC=1.1 NR=1 BR=10 RC=0.5 CJC=3.50E-12 +FC=0.5 MJC=0.25 VJC=0.7 CJE=4.50E-12 MJE=0.33 VJE=0.75 TF=2.80E-10 +ITF=0.4 VTF=2 XTF=10 RE=1 TR=8.00E-07) *From NS Discrete 1978, Motorola DL126/D rev 4 - Process 66 * Base resistance not modelled - no info. --- Cheers, Andy. http://signality.co.uk 2009/6/23 al davis ad...@freeelectron.net: On Tuesday 23 June 2009, Michael B Allen wrote: *== Begin SPICE netlist of main design Q2 output 2 0 2N3904 .MODEL 2N3904 NPN (Is=6.734f Xti=3 Eg=1.11 Vaf=74.03 Bf=416.4 Ne=1.259 Ise=6.734 Ikf=66.78m Xtb=1.5 Br=.7371 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=3.638p Mjc=.3085 Vjc=.75 Fc=.5 Cje=4.493p Mje=.2593 Vje=.75 Tr=239.5n Tf=301.2p Itf=.4 Vtf=4 Xtf=2 Rb) This syntax is incorrect .. Rb) ??? V1 4 0 DC 9V R4 output 4 0.999K Q1 1 3 0 2N3904 .MODEL 2N3904 NPN (Is=6.734f Xti=3 Eg=1.11 Vaf=74.03 Bf=416.4 Ne=1.259 Ise=6.734 Ikf=66.78m Xtb=1.5 Br=.7371 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=3.638p Mjc=.3085 Vjc=.75 Fc=.5 Cje=4.493p Mje=.2593 Vje=.75 Tr=239.5n Tf=301.2p Itf=.4 Vtf=4 Xtf=2 Rb=10) syntax correct this time, but there should be only one .model statement. R3 1 4 1.001K R2 3 4 15K R1 2 4 15K C2 output 3 10uF C1 1 2 10uF .end You need to explicitly start the oscillator. I'm not having any luck with this. It seems the syntax of netlist vs. interpreter mode commands vs. gspiceui fields is different enough that it's totally unclear as to how to achieve non-trival things. Why I don't like the GUI .. There are hundreds of things you can do. The GUI gives you about three of them. First, do I want to use GNU-Cap or NG-Spice? Gnucap, if you want my help. If you are really into it, try both and you will see that some things work better in one, some in the other. Also, what timing do I want? I was thinking something like 50ms - 100ms in 1ms increments reasoning that it will take time for the oscillation to start. It depends on your circuit. What frequency did you design it for. You need to run it a while to start up. See the example I referenced in the other mail. Regarding simulating power on, I don't recognize the format on the page cited: Vcc (vcc 0) pulse(iv=0 pv=12 rise=.01) My netlist above does not have parenthesis. Parenthesis are optional, but make it easier to read. And it seems gspiceui overrules the voltage source properties anyway? I think you put the whole string pulse ( ...) as the value in the schematic. With Spice, you list a bunch of numbers in a particular order. Gnucap accepts that too, but I can never remember what order they go in, so the labels are a better way to do it. That statement says the initial value (iv) is 0, pulsed (final) value (pv) is 12, and the rise time is .01 seconds. Look up the pulse http://gnucap.org/gnucap-man-html/gnucap-man094.html Similarly I'm not sure where the OFF
Re: gEDA-user: hierarchy and refdes_renum
Hi Anthony,
I try your latch comparator and got next results (when I run my
schematic I have the same output - unable to open low level sch).
$ spnet comparator.sch
spNet v0.9.1.2
gEDA/gschem Netlister
Copyright 2009 Anthony Shanks
-I- Starting Build of Cell: comparator
-I- Adding Library: buck1
-I- Adding Library: sym
-I- Adding Library: power
-I- Building Cell: preamp
-E- Unable to open schematic for cell: preamp
Thanks,
Alex.
On 06/24/2009 12:19 AM, Anthony Shanks wrote:
Hi Alex, please download the newest spnet on my site and let me know
how it goes, it should be a bit more compatible.
Here is whats new:
* Comments in both .spnetlibs and .spentrc (# is the comment character)
* Won't bail out on empty lines in either file above
* NMOS_TRANSISTOR and PMOS_TRANSISTOR as 4 terminal mosfets
* It doesnt matter if a component has brackets or not like in your
original example. If there is no brackets (therefore no attributes)
the component is ignored.
* All power symbols that come with gschem now work properly
Eager to here how this new version works and how compatible it is. In
the next release (perhaps tomorrow) I will add the support to pull
librarys already defined in gedarc files. Will also try to add autonet
naming for unnamed nets.
-Anthony
On Tue, Jun 23, 2009 at 2:46 PM, Anthony Shanksyamazak...@gmail.com wrote:
Are titleblocks legal (without lack of a better term) without
brackets or were they just that way in your schematic for some reason?
I thought all components had brackets but maybe only components with
attributes have brackets?
I took a look at v2i_2v.sym, it doesn't look like it has any schematic
file attached to it. Also spnet requires subckts with lower level
schematics to have the attribute to device=SUBCKT. There is no
standard attribute in the gEDA flow to define a subckt so thats what I
choose for spnet. Take a look at my latch example on my website for
what the properties of subckts look like.
Net stitch failure happens usually when there is a net without a
netname attached to one of the nets its connected too. There is no
autonet name feature yet but I plan to add it.
Also which devices in your schematic don't have refdes?
-Anthony
On Tue, Jun 23, 2009 at 1:59 PM, A.Burinskiyalexb...@gmail.com wrote:
Hi Anthony,
The reason for the message
-E- Fatal Error: Invalid Component attr C 42200 44200 1 0 0 gnd-1.sym
Was that first component, that is title-B block listed in the
test_v2i_2.sch without pair of { } !
Symbol spice-lib.sym is a special symbol. I did it. I think netlister
should support custom symbols.
v 20090328 2
B 0 400 1900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 100 300 9 10 0 1 0 0 1
device=library
T 100 500 9 10 1 1 0 0 1
refdes=A?
T 600 500 9 10 1 0 0 0 1
SPICE LIBR
T 500 200 8 10 1 1 0 0 1
file=?
T 100 200 9 10 1 0 0 0 1
File:
T 0 -5 8 10 1 0 0 0 1
corner=TYP
And v2i_2v.sym is real subcircuit.
After artificially adding this braces I've got (please note, that
(42300;44500) corresponds to connection point of gnd symbol pin)
$ spnet test_v2i.sch
spNet v0.9.1.2
gEDA/gschem Netlister
Copyright 2009 Anthony Shanks
-I- Starting Build of Cell: test_v2i
-I- Adding Library: sym
-I- Adding Library: power
-I- Combining Cells
-W- Device in cell test_v2i does not have a refdes, ignoring.
-W- Device in cell test_v2i does not have a refdes, ignoring.
-E- Net stitch failure in cell test_v2i near point 42300,44500.
Thanks,
Alex.
On 06/23/2009 10:54 AM, Anthony Shanks wrote:
Hmm, a few things.
Is that ground symbol the default that comes with gschem (device=none,
netname=0)? Can't look right now, at work.
I also noticed a few things in your schematic that is definitely not
supported (right now):
C 47000 49500 1 0 0 spice-lib.sym
C 5 44900 1 0 0 v2i_2v.sym
What are these? I assume the spice-lib.sym is a subckt netlist but I
don't know what the other is.
A quick fix in your case with the ground symbol is just to add the
attribute device=globalnode and net=0.
-Anthony
On Tue, Jun 23, 2009 at 10:00 AM, A.Burinskiyalexb...@gmail.comwrote:
Hi Anthony,
Yes, there is device that is not in the list and this is ground symbol.
Please find diff file and test_v2i.sch attached. That is what I have
(Please
note, that your search for '=' sign, while there is no any '=' sign in the
string...)
$ spnet test_v2i.sch
spNet v0.9.1.2
gEDA/gschem Netlister
Copyright 2009 Anthony Shanks
-I- Starting Build of Cell: test_v2i
-I- Adding Library: sym
-I- Adding Library: power
-I- Combining Cells
-E- Fatal Error: Invalid Component attr C 42200 44200 1 0 0 gnd-1.sym.
$ more ~/.spnetlibs
library: /home/username/tsmc sym
library: /usr/local/share/gEDA/sym power
On 06/23/2009 09:39 AM, Anthony Shanks wrote:
Comments are not supported yet, it's on the todo list.
Is the new code working yet? the invalid compoent
Re: gEDA-user: hierarchy and refdes_renum
Hi Anthony,
I fixed that by adding library: ./ local into .spnetlibs. Now I have
following:
$ spnet test_v2i.sch
spNet v0.9.1.2
gEDA/gschem Netlister
Copyright 2009 Anthony Shanks
-I- Starting Build of Cell: test_v2i
-I- Adding Library: local
-I- Building Cell: v2i_2v
-I- Try: .//v2i_2v.sch
-E- Net stitch failure in cell v2i_2v near point 43200,49100.
Image of offending net attached.
Thanks,
Alex.
On 06/24/2009 12:19 AM, Anthony Shanks wrote:
Hi Alex, please download the newest spnet on my site and let me know
how it goes, it should be a bit more compatible.
Here is whats new:
* Comments in both .spnetlibs and .spentrc (# is the comment character)
* Won't bail out on empty lines in either file above
* NMOS_TRANSISTOR and PMOS_TRANSISTOR as 4 terminal mosfets
* It doesnt matter if a component has brackets or not like in your
original example. If there is no brackets (therefore no attributes)
the component is ignored.
* All power symbols that come with gschem now work properly
Eager to here how this new version works and how compatible it is. In
the next release (perhaps tomorrow) I will add the support to pull
librarys already defined in gedarc files. Will also try to add autonet
naming for unnamed nets.
-Anthony
On Tue, Jun 23, 2009 at 2:46 PM, Anthony Shanksyamazak...@gmail.com wrote:
Are titleblocks legal (without lack of a better term) without
brackets or were they just that way in your schematic for some reason?
I thought all components had brackets but maybe only components with
attributes have brackets?
I took a look at v2i_2v.sym, it doesn't look like it has any schematic
file attached to it. Also spnet requires subckts with lower level
schematics to have the attribute to device=SUBCKT. There is no
standard attribute in the gEDA flow to define a subckt so thats what I
choose for spnet. Take a look at my latch example on my website for
what the properties of subckts look like.
Net stitch failure happens usually when there is a net without a
netname attached to one of the nets its connected too. There is no
autonet name feature yet but I plan to add it.
Also which devices in your schematic don't have refdes?
-Anthony
On Tue, Jun 23, 2009 at 1:59 PM, A.Burinskiyalexb...@gmail.com wrote:
Hi Anthony,
The reason for the message
-E- Fatal Error: Invalid Component attr C 42200 44200 1 0 0 gnd-1.sym
Was that first component, that is title-B block listed in the
test_v2i_2.sch without pair of { } !
Symbol spice-lib.sym is a special symbol. I did it. I think netlister
should support custom symbols.
v 20090328 2
B 0 400 1900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 100 300 9 10 0 1 0 0 1
device=library
T 100 500 9 10 1 1 0 0 1
refdes=A?
T 600 500 9 10 1 0 0 0 1
SPICE LIBR
T 500 200 8 10 1 1 0 0 1
file=?
T 100 200 9 10 1 0 0 0 1
File:
T 0 -5 8 10 1 0 0 0 1
corner=TYP
And v2i_2v.sym is real subcircuit.
After artificially adding this braces I've got (please note, that
(42300;44500) corresponds to connection point of gnd symbol pin)
$ spnet test_v2i.sch
spNet v0.9.1.2
gEDA/gschem Netlister
Copyright 2009 Anthony Shanks
-I- Starting Build of Cell: test_v2i
-I- Adding Library: sym
-I- Adding Library: power
-I- Combining Cells
-W- Device in cell test_v2i does not have a refdes, ignoring.
-W- Device in cell test_v2i does not have a refdes, ignoring.
-E- Net stitch failure in cell test_v2i near point 42300,44500.
Thanks,
Alex.
On 06/23/2009 10:54 AM, Anthony Shanks wrote:
Hmm, a few things.
Is that ground symbol the default that comes with gschem (device=none,
netname=0)? Can't look right now, at work.
I also noticed a few things in your schematic that is definitely not
supported (right now):
C 47000 49500 1 0 0 spice-lib.sym
C 5 44900 1 0 0 v2i_2v.sym
What are these? I assume the spice-lib.sym is a subckt netlist but I
don't know what the other is.
A quick fix in your case with the ground symbol is just to add the
attribute device=globalnode and net=0.
-Anthony
On Tue, Jun 23, 2009 at 10:00 AM, A.Burinskiyalexb...@gmail.comwrote:
Hi Anthony,
Yes, there is device that is not in the list and this is ground symbol.
Please find diff file and test_v2i.sch attached. That is what I have (Please
note, that your search for '=' sign, while there is no any '=' sign in the
string...)
$ spnet test_v2i.sch
spNet v0.9.1.2
gEDA/gschem Netlister
Copyright 2009 Anthony Shanks
-I- Starting Build of Cell: test_v2i
-I- Adding Library: sym
-I- Adding Library: power
-I- Combining Cells
-E- Fatal Error: Invalid Component attr C 42200 44200 1 0 0 gnd-1.sym.
$ more ~/.spnetlibs
library: /home/username/tsmc sym
library: /usr/local/share/gEDA/sym power
On 06/23/2009 09:39 AM, Anthony Shanks wrote:
Comments are not supported yet, it's on the todo list.
Is the new code working yet? the invalid compoent error will come up
with there is a symbol in your schematic without a valid device
attribute. Here is a list of devices
Re: gEDA-user: hierarchy and refdes_renum
Hi Anthony,
You could be surprised with -I- Try... statement. I modify your code a
little by adding printf statement in file misc.c near line 383.
// Test to see if the schematic exists
libs_save = libs;
while(libs != NULL)
{
filename_path = malloc_str(strlen(libs-path) +
strlen(basename) + 5);
+ sprintf(filename_path,%s/%s.sch,libs-path,basename);
printf(-I- Try: %s\n,filename_path);
fp_subckt_sch = fopen(filename_path,r);
if(fp_subckt_sch != NULL)
Thanks,
Alex.
On 06/24/2009 12:19 AM, Anthony Shanks wrote:
Hi Alex, please download the newest spnet on my site and let me know
how it goes, it should be a bit more compatible.
Here is whats new:
* Comments in both .spnetlibs and .spentrc (# is the comment character)
* Won't bail out on empty lines in either file above
* NMOS_TRANSISTOR and PMOS_TRANSISTOR as 4 terminal mosfets
* It doesnt matter if a component has brackets or not like in your
original example. If there is no brackets (therefore no attributes)
the component is ignored.
* All power symbols that come with gschem now work properly
Eager to here how this new version works and how compatible it is. In
the next release (perhaps tomorrow) I will add the support to pull
librarys already defined in gedarc files. Will also try to add autonet
naming for unnamed nets.
-Anthony
On Tue, Jun 23, 2009 at 2:46 PM, Anthony Shanksyamazak...@gmail.com wrote:
Are titleblocks legal (without lack of a better term) without
brackets or were they just that way in your schematic for some reason?
I thought all components had brackets but maybe only components with
attributes have brackets?
I took a look at v2i_2v.sym, it doesn't look like it has any schematic
file attached to it. Also spnet requires subckts with lower level
schematics to have the attribute to device=SUBCKT. There is no
standard attribute in the gEDA flow to define a subckt so thats what I
choose for spnet. Take a look at my latch example on my website for
what the properties of subckts look like.
Net stitch failure happens usually when there is a net without a
netname attached to one of the nets its connected too. There is no
autonet name feature yet but I plan to add it.
Also which devices in your schematic don't have refdes?
-Anthony
On Tue, Jun 23, 2009 at 1:59 PM, A.Burinskiyalexb...@gmail.com wrote:
Hi Anthony,
The reason for the message
-E- Fatal Error: Invalid Component attr C 42200 44200 1 0 0 gnd-1.sym
Was that first component, that is title-B block listed in the
test_v2i_2.sch without pair of { } !
Symbol spice-lib.sym is a special symbol. I did it. I think netlister
should support custom symbols.
v 20090328 2
B 0 400 1900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 100 300 9 10 0 1 0 0 1
device=library
T 100 500 9 10 1 1 0 0 1
refdes=A?
T 600 500 9 10 1 0 0 0 1
SPICE LIBR
T 500 200 8 10 1 1 0 0 1
file=?
T 100 200 9 10 1 0 0 0 1
File:
T 0 -5 8 10 1 0 0 0 1
corner=TYP
And v2i_2v.sym is real subcircuit.
After artificially adding this braces I've got (please note, that
(42300;44500) corresponds to connection point of gnd symbol pin)
$ spnet test_v2i.sch
spNet v0.9.1.2
gEDA/gschem Netlister
Copyright 2009 Anthony Shanks
-I- Starting Build of Cell: test_v2i
-I- Adding Library: sym
-I- Adding Library: power
-I- Combining Cells
-W- Device in cell test_v2i does not have a refdes, ignoring.
-W- Device in cell test_v2i does not have a refdes, ignoring.
-E- Net stitch failure in cell test_v2i near point 42300,44500.
Thanks,
Alex.
On 06/23/2009 10:54 AM, Anthony Shanks wrote:
Hmm, a few things.
Is that ground symbol the default that comes with gschem (device=none,
netname=0)? Can't look right now, at work.
I also noticed a few things in your schematic that is definitely not
supported (right now):
C 47000 49500 1 0 0 spice-lib.sym
C 5 44900 1 0 0 v2i_2v.sym
What are these? I assume the spice-lib.sym is a subckt netlist but I
don't know what the other is.
A quick fix in your case with the ground symbol is just to add the
attribute device=globalnode and net=0.
-Anthony
On Tue, Jun 23, 2009 at 10:00 AM, A.Burinskiyalexb...@gmail.comwrote:
Hi Anthony,
Yes, there is device that is not in the list and this is ground symbol.
Please find diff file and test_v2i.sch attached. That is what I have
(Please
note, that your search for '=' sign, while there is no any '=' sign in the
string...)
$ spnet test_v2i.sch
spNet v0.9.1.2
gEDA/gschem Netlister
Copyright 2009 Anthony Shanks
-I- Starting Build of Cell: test_v2i
-I- Adding Library: sym
-I- Adding Library: power
-I- Combining Cells
-E- Fatal Error: Invalid Component attr C 42200 44200 1 0 0 gnd-1.sym.
$ more ~/.spnetlibs
library: /home/username/tsmc sym
library: /usr/local/share/gEDA/sym power
On 06/23/2009 09:39 AM, Anthony Shanks wrote:
Comments are not
Re: gEDA-user: hierarchy and refdes_renum
Hi Anthony,
If I add netname to the offended net, the spnet goes to the next net and
report next error. Does it mean that all nets should be named?
Thanks,
Alex.
On 06/24/2009 12:19 AM, Anthony Shanks wrote:
Hi Alex, please download the newest spnet on my site and let me know
how it goes, it should be a bit more compatible.
Here is whats new:
* Comments in both .spnetlibs and .spentrc (# is the comment character)
* Won't bail out on empty lines in either file above
* NMOS_TRANSISTOR and PMOS_TRANSISTOR as 4 terminal mosfets
* It doesnt matter if a component has brackets or not like in your
original example. If there is no brackets (therefore no attributes)
the component is ignored.
* All power symbols that come with gschem now work properly
Eager to here how this new version works and how compatible it is. In
the next release (perhaps tomorrow) I will add the support to pull
librarys already defined in gedarc files. Will also try to add autonet
naming for unnamed nets.
-Anthony
On Tue, Jun 23, 2009 at 2:46 PM, Anthony Shanksyamazak...@gmail.com wrote:
Are titleblocks legal (without lack of a better term) without
brackets or were they just that way in your schematic for some reason?
I thought all components had brackets but maybe only components with
attributes have brackets?
I took a look at v2i_2v.sym, it doesn't look like it has any schematic
file attached to it. Also spnet requires subckts with lower level
schematics to have the attribute to device=SUBCKT. There is no
standard attribute in the gEDA flow to define a subckt so thats what I
choose for spnet. Take a look at my latch example on my website for
what the properties of subckts look like.
Net stitch failure happens usually when there is a net without a
netname attached to one of the nets its connected too. There is no
autonet name feature yet but I plan to add it.
Also which devices in your schematic don't have refdes?
-Anthony
On Tue, Jun 23, 2009 at 1:59 PM, A.Burinskiyalexb...@gmail.com wrote:
Hi Anthony,
The reason for the message
-E- Fatal Error: Invalid Component attr C 42200 44200 1 0 0 gnd-1.sym
Was that first component, that is title-B block listed in the
test_v2i_2.sch without pair of { } !
Symbol spice-lib.sym is a special symbol. I did it. I think netlister
should support custom symbols.
v 20090328 2
B 0 400 1900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 100 300 9 10 0 1 0 0 1
device=library
T 100 500 9 10 1 1 0 0 1
refdes=A?
T 600 500 9 10 1 0 0 0 1
SPICE LIBR
T 500 200 8 10 1 1 0 0 1
file=?
T 100 200 9 10 1 0 0 0 1
File:
T 0 -5 8 10 1 0 0 0 1
corner=TYP
And v2i_2v.sym is real subcircuit.
After artificially adding this braces I've got (please note, that
(42300;44500) corresponds to connection point of gnd symbol pin)
$ spnet test_v2i.sch
spNet v0.9.1.2
gEDA/gschem Netlister
Copyright 2009 Anthony Shanks
-I- Starting Build of Cell: test_v2i
-I- Adding Library: sym
-I- Adding Library: power
-I- Combining Cells
-W- Device in cell test_v2i does not have a refdes, ignoring.
-W- Device in cell test_v2i does not have a refdes, ignoring.
-E- Net stitch failure in cell test_v2i near point 42300,44500.
Thanks,
Alex.
On 06/23/2009 10:54 AM, Anthony Shanks wrote:
Hmm, a few things.
Is that ground symbol the default that comes with gschem (device=none,
netname=0)? Can't look right now, at work.
I also noticed a few things in your schematic that is definitely not
supported (right now):
C 47000 49500 1 0 0 spice-lib.sym
C 5 44900 1 0 0 v2i_2v.sym
What are these? I assume the spice-lib.sym is a subckt netlist but I
don't know what the other is.
A quick fix in your case with the ground symbol is just to add the
attribute device=globalnode and net=0.
-Anthony
On Tue, Jun 23, 2009 at 10:00 AM, A.Burinskiyalexb...@gmail.comwrote:
Hi Anthony,
Yes, there is device that is not in the list and this is ground symbol.
Please find diff file and test_v2i.sch attached. That is what I have
(Please
note, that your search for '=' sign, while there is no any '=' sign in the
string...)
$ spnet test_v2i.sch
spNet v0.9.1.2
gEDA/gschem Netlister
Copyright 2009 Anthony Shanks
-I- Starting Build of Cell: test_v2i
-I- Adding Library: sym
-I- Adding Library: power
-I- Combining Cells
-E- Fatal Error: Invalid Component attr C 42200 44200 1 0 0 gnd-1.sym.
$ more ~/.spnetlibs
library: /home/username/tsmc sym
library: /usr/local/share/gEDA/sym power
On 06/23/2009 09:39 AM, Anthony Shanks wrote:
Comments are not supported yet, it's on the todo list.
Is the new code working yet? the invalid compoent error will come up
with there is a symbol in your schematic without a valid device
attribute. Here is a list of devices that are current supported
(device=)
RESISTOR
CAPACITOR
INDUCTOR
NPN_TRANSISTOR
PNP_TRANSISTOR
Re: gEDA-user: hierarchy and refdes_renum
Hi Alex,
All cells that have a lower level schematic (subckt) should be in the
.spnetlibs file so it know where to look when opening up the schematic
and symbol. And yes, for now there no auto-netnaming feature so if
spnet comes across a net that isn't named any any connection point or
there is no pin attached on the net (from the pin symbol in my sym
gzip file) it will produce a netstitch error (which just means it
couldn't find a name for the net anywhere).
Did you try attaching a name to the net and netlist it yet?
-Anthony
On Wed, Jun 24, 2009 at 9:50 AM, A.Burinskiyalexb...@gmail.com wrote:
Hi Anthony,
If I add netname to the offended net, the spnet goes to the next net and
report next error. Does it mean that all nets should be named?
Thanks,
Alex.
On 06/24/2009 12:19 AM, Anthony Shanks wrote:
Hi Alex, please download the newest spnet on my site and let me know
how it goes, it should be a bit more compatible.
Here is whats new:
* Comments in both .spnetlibs and .spentrc (# is the comment character)
* Won't bail out on empty lines in either file above
* NMOS_TRANSISTOR and PMOS_TRANSISTOR as 4 terminal mosfets
* It doesnt matter if a component has brackets or not like in your
original example. If there is no brackets (therefore no attributes)
the component is ignored.
* All power symbols that come with gschem now work properly
Eager to here how this new version works and how compatible it is. In
the next release (perhaps tomorrow) I will add the support to pull
librarys already defined in gedarc files. Will also try to add autonet
naming for unnamed nets.
-Anthony
On Tue, Jun 23, 2009 at 2:46 PM, Anthony Shanksyamazak...@gmail.com wrote:
Are titleblocks legal (without lack of a better term) without
brackets or were they just that way in your schematic for some reason?
I thought all components had brackets but maybe only components with
attributes have brackets?
I took a look at v2i_2v.sym, it doesn't look like it has any schematic
file attached to it. Also spnet requires subckts with lower level
schematics to have the attribute to device=SUBCKT. There is no
standard attribute in the gEDA flow to define a subckt so thats what I
choose for spnet. Take a look at my latch example on my website for
what the properties of subckts look like.
Net stitch failure happens usually when there is a net without a
netname attached to one of the nets its connected too. There is no
autonet name feature yet but I plan to add it.
Also which devices in your schematic don't have refdes?
-Anthony
On Tue, Jun 23, 2009 at 1:59 PM, A.Burinskiyalexb...@gmail.com wrote:
Hi Anthony,
The reason for the message
-E- Fatal Error: Invalid Component attr C 42200 44200 1 0 0 gnd-1.sym
Was that first component, that is title-B block listed in the
test_v2i_2.sch without pair of { } !
Symbol spice-lib.sym is a special symbol. I did it. I think netlister
should support custom symbols.
v 20090328 2
B 0 400 1900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 100 300 9 10 0 1 0 0 1
device=library
T 100 500 9 10 1 1 0 0 1
refdes=A?
T 600 500 9 10 1 0 0 0 1
SPICE LIBR
T 500 200 8 10 1 1 0 0 1
file=?
T 100 200 9 10 1 0 0 0 1
File:
T 0 -5 8 10 1 0 0 0 1
corner=TYP
And v2i_2v.sym is real subcircuit.
After artificially adding this braces I've got (please note, that
(42300;44500) corresponds to connection point of gnd symbol pin)
$ spnet test_v2i.sch
spNet v0.9.1.2
gEDA/gschem Netlister
Copyright 2009 Anthony Shanks
-I- Starting Build of Cell: test_v2i
-I- Adding Library: sym
-I- Adding Library: power
-I- Combining Cells
-W- Device in cell test_v2i does not have a refdes, ignoring.
-W- Device in cell test_v2i does not have a refdes, ignoring.
-E- Net stitch failure in cell test_v2i near point 42300,44500.
Thanks,
Alex.
On 06/23/2009 10:54 AM, Anthony Shanks wrote:
Hmm, a few things.
Is that ground symbol the default that comes with gschem (device=none,
netname=0)? Can't look right now, at work.
I also noticed a few things in your schematic that is definitely not
supported (right now):
C 47000 49500 1 0 0 spice-lib.sym
C 5 44900 1 0 0 v2i_2v.sym
What are these? I assume the spice-lib.sym is a subckt netlist but I
don't know what the other is.
A quick fix in your case with the ground symbol is just to add the
attribute device=globalnode and net=0.
-Anthony
On Tue, Jun 23, 2009 at 10:00 AM, A.Burinskiyalexb...@gmail.com
wrote:
Hi Anthony,
Yes, there is device that is not in the list and this is ground symbol.
Please find diff file and test_v2i.sch attached. That is what I have
(Please
note, that your search for '=' sign, while there is no any '=' sign in
the
string...)
$ spnet test_v2i.sch
spNet v0.9.1.2
gEDA/gschem Netlister
Copyright 2009 Anthony Shanks
-I- Starting Build of Cell: test_v2i
-I- Adding Library: sym
-I- Adding Library: power
-I- Combining Cells
-E- Fatal Error: Invalid Component attr
Re: gEDA-user: hierarchy and refdes_renum
Btw, I don't know if it was clear but you should only have to name one
part of the net. Everything else attached to that net should pick up
the same name.
On Wed, Jun 24, 2009 at 10:52 AM, Anthony Shanksyamazak...@gmail.com wrote:
Hi Alex,
All cells that have a lower level schematic (subckt) should be in the
.spnetlibs file so it know where to look when opening up the schematic
and symbol. And yes, for now there no auto-netnaming feature so if
spnet comes across a net that isn't named any any connection point or
there is no pin attached on the net (from the pin symbol in my sym
gzip file) it will produce a netstitch error (which just means it
couldn't find a name for the net anywhere).
Did you try attaching a name to the net and netlist it yet?
-Anthony
On Wed, Jun 24, 2009 at 9:50 AM, A.Burinskiyalexb...@gmail.com wrote:
Hi Anthony,
If I add netname to the offended net, the spnet goes to the next net and
report next error. Does it mean that all nets should be named?
Thanks,
Alex.
On 06/24/2009 12:19 AM, Anthony Shanks wrote:
Hi Alex, please download the newest spnet on my site and let me know
how it goes, it should be a bit more compatible.
Here is whats new:
* Comments in both .spnetlibs and .spentrc (# is the comment character)
* Won't bail out on empty lines in either file above
* NMOS_TRANSISTOR and PMOS_TRANSISTOR as 4 terminal mosfets
* It doesnt matter if a component has brackets or not like in your
original example. If there is no brackets (therefore no attributes)
the component is ignored.
* All power symbols that come with gschem now work properly
Eager to here how this new version works and how compatible it is. In
the next release (perhaps tomorrow) I will add the support to pull
librarys already defined in gedarc files. Will also try to add autonet
naming for unnamed nets.
-Anthony
On Tue, Jun 23, 2009 at 2:46 PM, Anthony Shanksyamazak...@gmail.com
wrote:
Are titleblocks legal (without lack of a better term) without
brackets or were they just that way in your schematic for some reason?
I thought all components had brackets but maybe only components with
attributes have brackets?
I took a look at v2i_2v.sym, it doesn't look like it has any schematic
file attached to it. Also spnet requires subckts with lower level
schematics to have the attribute to device=SUBCKT. There is no
standard attribute in the gEDA flow to define a subckt so thats what I
choose for spnet. Take a look at my latch example on my website for
what the properties of subckts look like.
Net stitch failure happens usually when there is a net without a
netname attached to one of the nets its connected too. There is no
autonet name feature yet but I plan to add it.
Also which devices in your schematic don't have refdes?
-Anthony
On Tue, Jun 23, 2009 at 1:59 PM, A.Burinskiyalexb...@gmail.com wrote:
Hi Anthony,
The reason for the message
-E- Fatal Error: Invalid Component attr C 42200 44200 1 0 0 gnd-1.sym
Was that first component, that is title-B block listed in the
test_v2i_2.sch without pair of { } !
Symbol spice-lib.sym is a special symbol. I did it. I think netlister
should support custom symbols.
v 20090328 2
B 0 400 1900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 100 300 9 10 0 1 0 0 1
device=library
T 100 500 9 10 1 1 0 0 1
refdes=A?
T 600 500 9 10 1 0 0 0 1
SPICE LIBR
T 500 200 8 10 1 1 0 0 1
file=?
T 100 200 9 10 1 0 0 0 1
File:
T 0 -5 8 10 1 0 0 0 1
corner=TYP
And v2i_2v.sym is real subcircuit.
After artificially adding this braces I've got (please note, that
(42300;44500) corresponds to connection point of gnd symbol pin)
$ spnet test_v2i.sch
spNet v0.9.1.2
gEDA/gschem Netlister
Copyright 2009 Anthony Shanks
-I- Starting Build of Cell: test_v2i
-I- Adding Library: sym
-I- Adding Library: power
-I- Combining Cells
-W- Device in cell test_v2i does not have a refdes, ignoring.
-W- Device in cell test_v2i does not have a refdes, ignoring.
-E- Net stitch failure in cell test_v2i near point 42300,44500.
Thanks,
Alex.
On 06/23/2009 10:54 AM, Anthony Shanks wrote:
Hmm, a few things.
Is that ground symbol the default that comes with gschem (device=none,
netname=0)? Can't look right now, at work.
I also noticed a few things in your schematic that is definitely not
supported (right now):
C 47000 49500 1 0 0 spice-lib.sym
C 5 44900 1 0 0 v2i_2v.sym
What are these? I assume the spice-lib.sym is a subckt netlist but I
don't know what the other is.
A quick fix in your case with the ground symbol is just to add the
attribute device=globalnode and net=0.
-Anthony
On Tue, Jun 23, 2009 at 10:00 AM, A.Burinskiyalexb...@gmail.com
wrote:
Hi Anthony,
Yes, there is device that is not in the list and this is ground symbol.
Please find diff file and test_v2i.sch attached. That is what I have
(Please
note, that your search for '=' sign, while there is no any '=' sign in
the
string...)
Re: gEDA-user: hierarchy and refdes_renum
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Anthony Shanks wrote: What is your end goal here? Just to have hierarchical schematics or do be able to produce a hierarchical netlist? IMHO hierarchical schematics in gschem work perfectly fine, it's netlisting them that as of right now is very hackery/broken which is why I started a new netlister spNet. You can download the latest version here http://spnet.code-fusion.net but be warned the documentation is very shotty/inaccurate since I haven't officially released it yet. Refer to my last post on this list for more details. I'm planning a stepper motor card for 4 motors, so I wanted to put the motor drivers and all the stuff around in one subcircuit. The problem is that for example the out-1.sym instrace called HOME (=the HOME pin of the symbol) is renamed into HOME1 by gnetlist. I run gnetlist only on the subcircuit. Don't know if it's OK to do so ... But I will check out spnet tomorrow! CU - - cl -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.7 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFKQpj9Wo2QgtqY4K8RAj6OAJ47i1qezl2KVH0sC8ZHqOyBn3jIWQCguc3U CEgduZnw/gcgYKsfNnoY1OI= =Fabh -END PGP SIGNATURE- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: hierarchy and refdes_renum
On Jun 24, 2009, at 3:22 PM, Christoph Lechner wrote: I'm planning a stepper motor card for 4 motors, so I wanted to put the motor drivers and all the stuff around in one subcircuit. The problem is that for example the out-1.sym instrace called HOME (=the HOME pin of the symbol) is renamed into HOME1 by gnetlist. I run gnetlist only on the subcircuit. Don't know if it's OK to do so ... In that approach, you run gnetlist on the top level schematic to produce a flat netlist, as required by may (most?) printed circuit layout programs. Running gnetlist on the subcircuit will treat the IO connectors as physical components. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Freedog-like groups in Southern California?
Hello gEDA/PCB users, I wonder, is there perchance a local user group in Southern California similar to the Freeedaug on the East Coast? Or if there is no established group, are there any individual gEDA/PCB users in Southern California who might be interested in starting such a group? I would really like to find someone local from whom I could learn how to use PCB for simple tasks. Because of the way my brain is wired, tasks that are inherently graphical by their nature (such as PCB layout) are very unnatural and difficult for me, so I know I will probably never do my own complex PCB layouts of professional quality, instead I'll have to outsource them like I did with the OSDCU (Ineiev did an outstanding job in my opinion!), however, I would like to at least be able to do simple things with PCB. I would like to be able to view existing layouts and examine areas of interest to me, make minor edits and do my own layouts of very simple boards that have maybe 2 or 3 components and fewer than 10 or so traces. My difficulty is that my disability when it comes to graphical tasks makes it harder for me than it would be for an average person, so whereas a normal person would have no difficulty learning how to use PCB from the various resources on the web, I think I would need to learn from someone I can interact with in person. Hence I wonder if there is anyone local in Southern California who would be willing to teach me some basic use of the PCB GUI. I do have pcb-20081128 installed and working with the lesstif HID on my Slackware Linux laptop. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Freedog-like groups in Southern California?
Sorry man if you were in Northern California I'd have no problem helping you. Good luck with your search. On Wed, Jun 24, 2009 at 5:04 PM, Michael Sokolovmsoko...@ivan.harhan.org wrote: Hello gEDA/PCB users, I wonder, is there perchance a local user group in Southern California similar to the Freeedaug on the East Coast? Or if there is no established group, are there any individual gEDA/PCB users in Southern California who might be interested in starting such a group? I would really like to find someone local from whom I could learn how to use PCB for simple tasks. Because of the way my brain is wired, tasks that are inherently graphical by their nature (such as PCB layout) are very unnatural and difficult for me, so I know I will probably never do my own complex PCB layouts of professional quality, instead I'll have to outsource them like I did with the OSDCU (Ineiev did an outstanding job in my opinion!), however, I would like to at least be able to do simple things with PCB. I would like to be able to view existing layouts and examine areas of interest to me, make minor edits and do my own layouts of very simple boards that have maybe 2 or 3 components and fewer than 10 or so traces. My difficulty is that my disability when it comes to graphical tasks makes it harder for me than it would be for an average person, so whereas a normal person would have no difficulty learning how to use PCB from the various resources on the web, I think I would need to learn from someone I can interact with in person. Hence I wonder if there is anyone local in Southern California who would be willing to teach me some basic use of the PCB GUI. I do have pcb-20081128 installed and working with the lesstif HID on my Slackware Linux laptop. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Freedog-like groups in Southern California?
My difficulty is that my disability when it comes to graphical tasks makes it harder for me than it would be for an average person, so whereas a normal person would have no difficulty learning how to use PCB from the various resources on the web, I don't know how relevant this is to PCB, but some people can copy artwork in extraordinary detail by turning it upside down. The brain stops trying to process the picture that way, that gets in the way in tasks like this. How do you get your monitor to display something upside down, with out turning the monitor over? Seems like there would be some simple way to do that. Preferably on a per-window basis. I think I would need to learn from someone I can interact with in person. There are always things like VNC and RFB et.al that let people interact with you on your own screen. -- http://www.wearablesmartsensors.com/ http://www.softwaresafety.net/ http://www.designer-iii.com/ http://www.unusualresearch.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Freedog-like groups in Southern California?
On the Northern California front. I'm in sunnyvale, CA. Any other users in the area On Jun 24, 2009, at 5:08 PM, Anthony Shanks wrote: Sorry man if you were in Northern California I'd have no problem helping you. Good luck with your search. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Freedog-like groups in Southern California?
On Wednesday 24 June 2009, Steven Michalske wrote: On the Northern California front. I'm in sunnyvale, CA. Any other users in the area There's a oseda group that meets third wednesday every month. The location varies, but Bangkok Spoon Thai restaurant, 702 Villa St. (corner of Villa St. and Hope St.) Mountain View, seems to be one of their top places. I usually make it about once a year, maybe twice, I don't live in California but travel there often enough to hook up once in a while. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Freedog-like groups in Southern California?
I'm also in Sunnyvale. :) On Jun 24, 2009, at 6:22 PM, Steven Michalske wrote: On the Northern California front. I'm in sunnyvale, CA. Any other users in the area On Jun 24, 2009, at 5:08 PM, Anthony Shanks wrote: Sorry man if you were in Northern California I'd have no problem helping you. Good luck with your search. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: test suite versus fab drawing
I've added the start of a test suite for pcb. It checks the export HID's. I haven't come up with good ideas for checking other aspects yet. One trick is how to compare a generated output file to a stored reference one. For example, the bill of materials and x-y (centroid) files contain the name of the person who generated the file as well as a date/time stamp. So I use awk to clear out those bits followed by diff. For RS274-X files, I run the reference and the generated one through gerbv to export both to png files and then do a pixel by pixel compare. That way if we change comments or some other thing in our output that produces an identical mask, we're still ok. But... the fab drawing includes the name of the person who generated it along with a date/time stamp. I don't see a good way to clear that out and so of course I can't check fab drawings because I get a failure every time. Would it make sense to teach pcb to accept a pair of new command line options that set the author name (--originator name) and a time stamp string (--time time string) to use in place of whats detected from the user info and the system time? I could even see the --originator option being useful if you wanted to put a different name in the drawings. Comments? Thanks -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: test suite versus fab drawing
There's already an option for the originator: --fab-author string I would prefer an option to not include the time, over one that lies about the time, unless you want to include the timestamp in the testsuite. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
