Re: gEDA-user: transition of pcb internal units to metric (SI, mm)
Am 08.02.2011 um 08:44 schrieb rickman: Do you expect these tools to be used to design chips costing far, far over $3 Million just for the mask set? I'm trying to think 20 years into the future. Especially if it's only a matter of allowing a compile time flag or not. Markus - - - - - - - - - - - - - - - - - - - Dipl. Ing. (FH) Markus Hitter http://www.jump-ing.de/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: transition of pcb internal units to metric (SI, mm)
On Feb 7, 2011, at 2:05 PM, Markus Hitter wrote: Isn't a nanometer pretty big when doing chip design? Others might have more/any experience in this area. I doubt PCB will ever be a suitable tool for chip design. 1 nm is good enough for models that assume materials are continuous and homogeneous. Atomic radii are typically ~0.1 nm, so this model isn't very accurate at the 1 nm scale: you need to account for the granularity. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: transition of pcb internal units to metric (SI, mm)
On 08/02/11 09:20, Markus Hitter wrote: Am 08.02.2011 um 08:44 schrieb rickman: Do you expect these tools to be used to design chips costing far, far over $3 Million just for the mask set? I'm trying to think 20 years into the future. Especially if it's only a matter of allowing a compile time flag or not. Markus - - - - - - - - - - - - - - - - - - - Dipl. Ing. (FH) Markus Hitter http://www.jump-ing.de/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user First off, is PCB in its current state even remotely usable for chip design (sincere question - I have no idea what actually goes into that), and if not, are there any plans to change that in the near future? If the answer to both questions is no, then I don't see any problem. As for 20 years in the future, that's a /long/ time (as is anything else over 10 years or so, really). I personally don't think ensuring compatibility with something that far away is worth causing problems on lower-end hardware now. Seeing as 32-bit operating systems (even on 64-bit machines!) are still widely used, and anything smaller than a nanometre is overkill for the time being, I'd say playing nice with 32-bit is, at the moment, more important than making sure people can design chips that can't even be manufactured for another decade or two anyway. Besides, what, ultimately, is to stop the user from simply printing the design at 1:1000 scale? If you're doing something that exotic, the default footprints won't be any good anyway, and if you're creating new ones, you can just as easily create them at 1000 times the actual size and tape-out the final design at 1:1000 scale. Peter ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: transition of pcb internal units to metric (SI, mm)
John Doty j...@noqsi.com writes: I doubt PCB will ever be a suitable tool for chip design. Why? It should not make that a priority. But the hierachical features outlined elsewhere, layer types, a sufficiently generic via mechanism, its not too far from making it possible to do chip design. Hierachy, blind and burried vias, all these PCB features are on the list. Just steer the development just a little bit to make it general enough in the core/file formats. The GUI may be 100% PCB by default and hide the generality from the user. Chip design will then need another pile of code to interpret the drawing in terms a silocon technology, at least a gds2 exporter. -- Stephan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: transition of pcb internal units to metric (SI, mm)
On Feb 8, 2011, at 3:48 AM, Stephan Boettcher wrote: John Doty j...@noqsi.com writes: I doubt PCB will ever be a suitable tool for chip design. Why? Because it's far too ad hoc in its design. It's a collection of special features, lacking any fundamental notion of a design as a composition of geometric objects with properties. Hierachy, blind and burried vias, all these PCB features are on the list. Yes, and in PCB's development paradigm they will be added ad hoc as features, rather than as emerging naturally as capabilities of clean design. But the unplanned capabilities that are natural consequences of orthogonal design upon a solid foundation are essential to flexibility. PCB would need this sort of flexibility to transcend the straightjacket of use cases and become a truly general-purpose toolkit. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: numslots=0
On Feb 4, 2011, at 9:07 PM, Kai-Martin Knaak wrote: Another cite from the master attribute list: A basic problem is that the master attribute list, symbol creation guide, and gsymcheck all represent a much narrower vision than the actual breadth of the gEDA application space. A symbol intended for printed circuit layout has different (incompatible) needs from a symbol intended for SPICE simulation. One good thing is that the various printed circuit netlisters are pretty similar in their use of attributes, so it's relatively easy to make symbols that are portable among those flows. This is unfortunately not true in the wider application space. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: transition of pcb internal units to metric (SI, mm)
From: rickman [1]gnuarm.g...@arius.com Date: Tue, 08 Feb 2011 02:44:09 -0500 Subject: Re: gEDA-user: transition of pcb internal units to metric (SI, mm) The cost to [1]tape-out a chip at 90 nm is at least US$1,000,000 and exceeds US$3,000,000 for 65 nm.^[2][40] Do you expect these tools to be used to design chips costing far, far over $3 Million just for the mask set? [2]http://en.wikipedia.org/wiki/Multi-project_wafer_service You can share space on the IC wafer with multiple other companies, where everyone splits the cost of the masks roughly equally. The mask design accounts for the vast majority of the cost, the raw materials are essentially gimmes, and the production of a batch of wafers from a mask set is cheap compared to the mask cost. The current standard for wafer diameter is 300 mm (11.8) = 109 sq inches. You would loose about 1/4 of the area to the edge effects on the wafer so you are looking at ~75 in sq of usable space. When you consider that most of the parts that we use on our PCBs have an IC die size of (much) less than 1/2 of a sq inch, you could reasonably hope to fit 100 different chips on a wafer. That would drop the $1 to $3 million dollars down to $10,000 to $30,000 per chip on the wafer. They can then make a hundred wafers easily on the first batch, so there would be 100 of each chip for that cost. If you were talking about a 0.1 sq inch chip, as a student project, you might be able to get in cheaper than that. Granted, PCB is NOT a VLSI layout tool, as John Doty eluded to, so I don't think we need to force 1 nm internal units for that reason. I would not be inclined to make PCB a VLSI layout tool either. Andy Miner References 1. mailto:gnuarm.g...@arius.com 2. http://en.wikipedia.org/wiki/Multi-project_wafer_service ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: transition of pcb internal units to metric (SI, mm)
Andrew Miner wrote: The current standard for wafer diameter is 300 mm (11.8) = 109 sq inches. You would loose about 1/4 of the area to the edge effects on the wafer so you are looking at ~75 in sq of usable space. When you consider that most of the parts that we use on our PCBs have an IC die size of (much) less than 1/2 of a sq inch, you could reasonably hope to fit 100 different chips on a wafer. That would drop the $1 to $3 million dollars down to $10,000 to $30,000 per chip on the wafer. They can then make a hundred wafers easily on the first batch, so there would be 100 of each chip for that cost. If you were talking about a 0.1 sq inch chip, as a student project, you might be able to get in cheaper than that. I am not an expert on ASIC manufacture, but I think that you've made some incorrect assumptions there. Yes, the standard wafer at current cutting-edge processes is 300 mm (although for older and non-standard processes, smaller wafers are common); however, I don't believe that you'd be able to get a mask (a.k.a. reticle) set that would cover the entire surface of that wafer. A reticle will only cover a proportion of the wafer's surface, and to cover the whole wafer surface, the reticle will be used to expose the surface of the wafer repeatedly, using a piece of equipment called a stepper. Therefore, the maximum number of different chips you can have on a wafer is limited by the maximum reticle size, not the wafer size. At a guess, I'd say that the maximum image size would be about 100 mm x 100 mm (once exposed on the wafer surface). Also, the larger the reticle, the more uneven the spread of devices (e.g. one device in the MPW may get 4 working impressions, but another may get two because it's hanging over the edge of the wafer in the other two instances). This would, however, still give you one hundred 100mm^2 different devices within a single reticle, and 100mm^2 is still a lot of transistors at 90 nm or 65 nm. Of course, you could in theory make multiple mask sets to image different parts of the wafer, but that would defeat the object of the MPW. You would also have to take into account that you're unlikely to get all the MPW's customers to agree to a uniform die size, so some of the dice will be lost as the wafer is cut up, since the saws used will typically only make straight cuts all the way across the surface of the wafer - you can't turn corners. So, out of the 100-wafer lot, maybe 25 of them will be cut for your die. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: transition of pcb internal units to metric (SI, mm)
On Feb 7, 2011, at 10:41 AM, DJ Delorie wrote: * nanometer internal units * 32-bit values on 32-bit machines, 64-bit on 64-bit. * configure option for 64-bit values regardless of machine in case you need a board larger than seven feet across. What about storing both imperial and metric? This way, the measurements are ket separate until the very last moment when they need to be converted to one value. A metric element can be manipulated on screen in an imperial grid and no errors build up. Using a two column one row matrix, store both imperial and metric values. The actual measurement is the sum of the two converted to the proper units. In exclusively imperial or metric projects, one value will be zero. In mixed projects, both may take on a non-zero value. [imperial metric] All arithmetic operations use matrix manipulation. For example, addition: z.imperial = a.imperial + b.imperial z.metric = a.metric + b.metric Multiplication: z.imperial = k * a.imperial z.metric = k * b.metric At the last moment, convert one value, add it to the other to get a single number for output. result = [ k0 ] * [imperial metric] [ k1 ] Where k0 and k1 are the appropriate conversion factors. Cheers, Ed ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: transition of pcb internal units to metric (SI, mm)
From: David Smith [1]dave.sm...@st.com Date: Tue, 8 Feb 2011 14:32:24 + I am not an expert on ASIC manufacture, but I think that you've made some incorrect assumptions there. Yes, the standard wafer at current cutting-edge processes is 300 mm (although for older and non-standard processes, smaller wafers are common); however, I don't believe that you'd be able to get a mask (a.k.a. reticle) set that would cover the entire surface of that wafer. A reticle will only cover a proportion of the wafer's surface, and to cover the whole wafer surface, the reticle will be used to expose the surface of the wafer repeatedly, using a piece of equipment called a stepper. Okay, I was not fully awake this morning, so I did make some mistakes. Yes the 300 mm wafers use steppers, and that is how they can get down to the 65 nm and finer resolutions. In that case you would have a small portion of the die image. I was still half asleep and thinking along the um scale technology we have at my (former) university with a 4 wafer line that uses a full 4 mask. There were some masks there that had many unique designs over the whole 4 mask (not just step and repeat), and we were able to fab those on wafers in house. One of the companies that currently offers this service is MOSIS [2]http://www.mosis.com/about/whatis.html and as I remember they did offer great prices for students as this albeit old pdf shows: [3]http://users.ece.gatech.edu/rincon-mora/research/mosis_submsn.pdf You would need to quote out current prices, but a student use to get a custom ASIC for as little as $3250. Commercial prices would be higher especially as you approach 90 nm or finer. Andy Miner References 1. mailto:dave.sm...@st.com 2. http://www.mosis.com/about/whatis.html 3. http://users.ece.gatech.edu/rincon-mora/research/mosis_submsn.pdf ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: transition of pcb internal units to metric (SI, mm)
On Tue, 8 Feb 2011 07:27:01 -0800 Edward Hennessy ehen...@sbcglobal.net wrote: On Feb 7, 2011, at 10:41 AM, DJ Delorie wrote: * nanometer internal units * 32-bit values on 32-bit machines, 64-bit on 64-bit. * configure option for 64-bit values regardless of machine in case you need a board larger than seven feet across. What about storing both imperial and metric? This way, the measurements are ket separate until the very last moment when they need to be converted to one value. A metric element can be manipulated on screen in an imperial grid and no errors build up. What problem does this solve? It certainly makes things much more complex and will impact performance for no benefit. Regards, Colin ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Soldering iron tip turns black
John Coppens wrote: So, the soldering point has a fine layer of a metal which does accept solder, deposited during the manufacturing. IMHO, this layer is usually iron and not that fine -- abut half a mm. There might be some additional chemical activation involved. But I am not sure. If the point was too hot, this fine layer peels off, I'd say, it oxidizes. Unlike oxidized solder, this rust sticks to the tip. It requires more force to rub it off. ---)kaimartin(--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: transition of pcb internal units to metric (SI, mm)
On 2/8/2011 12:23 PM, Colin D Bennett wrote: On Tue, 8 Feb 2011 07:27:01 -0800 Edward Hennessyehen...@sbcglobal.net wrote: On Feb 7, 2011, at 10:41 AM, DJ Delorie wrote: * nanometer internal units * 32-bit values on 32-bit machines, 64-bit on 64-bit. * configure option for 64-bit values regardless of machine in case you need a board larger than seven feet across. What about storing both imperial and metric? This way, the measurements are ket separate until the very last moment when they need to be converted to one value. A metric element can be manipulated on screen in an imperial grid and no errors build up. What problem does this solve? It certainly makes things much more complex and will impact performance for no benefit. Exactly, it solves no problems. Working with 1 nm internal units preserves the exact inch dimensions down to 0.01 mil. Of course, this is convertible back in to inches with no loss of accuracy. Rick ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: transition of pcb internal units to metric (SI, mm)
On 2/8/2011 11:24 AM, Andrew Miner wrote: From: David Smith[1]dave.sm...@st.com Date: Tue, 8 Feb 2011 14:32:24 + I am not an expert on ASIC manufacture, but I think that you've made some incorrect assumptions there. Yes, the standard wafer at current cutting-edge processes is 300 mm (although for older and non-standard processes, smaller wafers are common); however, I don't believe that you'd be able to get a mask (a.k.a. reticle) set that would cover the entire surface of that wafer. A reticle will only cover a proportion of the wafer's surface, and to cover the whole wafer surface, the reticle will be used to expose the surface of the wafer repeatedly, using a piece of equipment called a stepper. Okay, I was not fully awake this morning, so I did make some mistakes. Yes the 300 mm wafers use steppers, and that is how they can get down to the 65 nm and finer resolutions. In that case you would have a small portion of the die image. I was still half asleep and thinking along the um scale technology we have at my (former) university with a 4 wafer line that uses a full 4 mask. There were some masks there that had many unique designs over the whole 4 mask (not just step and repeat), and we were able to fab those on wafers in house. One of the companies that currently offers this service is MOSIS [2]http://www.mosis.com/about/whatis.html and as I remember they did offer great prices for students as this albeit old pdf shows: [3]http://users.ece.gatech.edu/rincon-mora/research/mosis_submsn.pdf You would need to quote out current prices, but a student use to get a custom ASIC for as little as $3250. Commercial prices would be higher especially as you approach 90 nm or finer. Andy Minerhttp://www.seul.org/cgi-bin/mailman/listinfo/geda-user This is past the point of being silly. IC design was brought into this conversation to justify changing the tools to record dimensions down to picometer levels. None of this is a justification for that. To need picometers you would need to not only be willing to pay huge amounts for a mask set, far beyond anything even in production today, but you would need the capability of actually designing transistors with feature size resolution below 1 nm... in terms of the models. Then you will have to pay equally huge amounts to get such a device into the production line considering that such a fab will likely cost in excess of 10 billion USD with each wafer having equally high processing costs. Not to mention that no one is even thinking of working with standard devices and techniques at feature resolutions below 1 nm. It is really starting to look like we may not pass 10 nm for standard production chips. With all of that going on, do you really think there is even a remote justification for these tools using dimensions smaller than nm so that they can be used for advanced IC design? Rick ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: transition of pcb internal units to metric (SI, mm)
Am 08.02.2011 12:17, schrieb John Doty: On Feb 8, 2011, at 3:48 AM, Stephan Boettcher wrote: John Doty j...@noqsi.com writes: I doubt PCB will ever be a suitable tool for chip design. Why? Because it's far too ad hoc in its design. It's a collection of special features, lacking any fundamental notion of a design as a composition of geometric objects with properties. There already are free tools for chip design, like magic (http://opencircuitdesign.com/magic/), I don't see why pcb should get into chip design. Philipp ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: transition of pcb internal units to metric (SI, mm)
Am 08.02.2011 10:14, schrieb Link: Seeing as 32-bit operating systems (even on 64-bit machines!) are still widely used, and anything smaller than a nanometre is overkill for the time being, I'd say playing nice with 32-bit is, at the moment, more important than making sure people can design chips that can't even be manufactured for another decade or two anyway. Using 64 bit values on 32 bit system will probably result in a measurable, but negligible impact on speed. I don't see why that should justify the complication of having both 32 and 64 bit option in pcb instead of just going with 64 bit values everywhere. Philipp ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: transition of pcb internal units to metric (SI, mm)
rickman wrote: This is past the point of being silly. IC design was brought into this conversation to justify changing the tools to record dimensions down to picometer levels. Let's aim for the lowest possible denominator: The Planck length! http://en.wikipedia.org/wiki/Planck_length ---)kaimartin(--- -- Kai-Martin Knaak Email: k...@familieknaak.de Öffentlicher PGP-Schlüssel: http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: transition of pcb internal units to metric (SI, mm)
Stephan Boettcher wrote: I doubt PCB will ever be a suitable tool for chip design. Why? Because a jack-of-all-trades is an expert in none. ---)kaimartin(--- -- Kai-Martin Knaak Email: k...@familieknaak.de Öffentlicher PGP-Schlüssel: http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: ERC and DRC checking
So I have a 25 page schematic, and I want to do some rudimentary checks on it. For example I would like to know if I wired power pins to gnd pins or only have inputs or outputs on a given net. What tools does geda have for this type of checking? What ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: ERC and DRC checking
Oliver King-Smith wrote: So I have a 25 page schematic, and I want to do some rudimentary checks on it. For example I would like to know if I wired power pins to gnd pins or only have inputs or outputs on a given net. What tools does geda have for this type of checking? http://geda.seul.org/wiki/geda:faq-gnetlist#how_do_i_check_my_schematics To run the command on all 25 schematics at once you may wrap it in a little shell script. --)kaimartin(--- -- Kai-Martin Knaak Email: k...@familieknaak.de Öffentlicher PGP-Schlüssel: http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gattrib not showing part_numbers
I have defined a number of symbols with an embedded part # for ease of ordering. An example of such a part # is T 700 1000 8 10 0 0 0 0 1 part_number=PMBS3904 This is visible on the schematic (if you turn on invisible text). However when I run gattrib on the schematic with this in it, I don't see the part number show up. I do see my part numbers show up for items where I entered it as an attribute for the particular part (such as a capacitor). Does anyone know if this is a feature or bug? Oliver ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gattrib not showing part_numbers
On Feb 8, 2011, at 7:08 PM, Oliver King-Smith wrote: Does anyone know if this is a feature or bug? It's the way it works. Whether it's a bug depends on what you're trying to do. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
