Re: gEDA-user: General Layers questions
Martin Kupec martin.ku...@kupson.cz writes: Hi all, I appreciate the discussion. So do I. It started out a bit of a mess, because we were talking about different things, but in the end I think there was not left much disagreement about fundamental issues. There we nearly no objections to my layer concept, just to the via/footprint/composite. I have updated the page (http://geda.seul.org/wiki/geda:pcb_layers) and I hope it not reflects the 'opinion of majority'. I will now have a look at that. But what do you call majority? The most vocal people here, like John and myself did not offer to do any coding, yet. In the end, those that code (DJ, you ?) decide. I appreciate that you asked for out opinion! So again. Coments are welcome, the discussion was a bit fast so I may have missed something important again. I think it is worth to read the whole thing once again. I will send myself a digest message of the whole thread so that it is easier to read, and I may try to identify the core arguments. Thank you all for participating, Thank you! -- Stephan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
On Sat, Mar 19, 2011 at 11:02:55AM +0100, Stephan Boettcher wrote: I will now have a look at that. But what do you call majority? The most vocal people here, like John and myself did not offer to do any coding, yet. In the end, those that code (DJ, you ?) decide. I am the one who is willing to code it. And my majority I simply mean number of people involved. I am democratic, just counting heads :-). Martin Kupec ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
Am 19.03.2011 um 02:29 schrieb John Doty: ... comparison to the C language snipped ... Proper bottom-up design *never* results in impossible-to-meet requirements because it starts from capabilities. Nice description, John. What can a layered description of tame plane geometries (no fractals ;-) actually represent? To some extents I can't get rid of the feeling layouts shouldn't be considered as layers with components on them, but as tracks, holes, pads and components which happen to be manufactured on layers. For example you have holes, which happen to be plated or unplated, which happen to connect to pads, which happen to connect to layer 2-4, and so on. Low level data representation describes those elements with their properties, higher level functionality provides functions ensuring this makes sense in a layered design. Currently, components are handled this way; resistors, ICs, and that stuff are listed as parts in a .pcb file. The lacking part is, there is no clear description of all their properties, e.g. to which tracks or layers they connect. Tracks should be handled the like components. BTW., there were electronic circuitries before PCBs were invented and the future of electronics manufacturing is most likely something three-dimensional, arbitrarily shaped. my $0.02, Markus - - - - - - - - - - - - - - - - - - - Dipl. Ing. (FH) Markus Hitter http://www.jump-ing.de/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
Stephan Boettcher boettc...@physik.uni-kiel.de writes: Now consider a differential pair. It's a line but you *don't* move the *line* endpoints, you move the *pair* control points. That is a hard one. You could define a composit of type morphable The endpoints of shapes inside such a composite become pointable/selectable, and a plugin can register callbacks to be called when such an endpoint is manipulated. The plugin would check to see if a diffpair attribute is set, and decline the callback if not, so that the magic_poly plugin has a chance. The morphable composits can also support lines with soldermask opening and paste. Maybe we call the wires. These composits allow to manipulate endpoints of contained objects, where a plugin makes sure that the stack of features representing the wires move together. -- Stephan Böttcher FAX: +49-431-85660 Extraterrestrische PhysikTel: +49-431-880-2508 I.f.Exp.u.Angew.Physik mailto:boettc...@physik.uni-kiel.de Leibnizstr. 11, 24118 Kiel, Germany ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
On Mar 19, 2011, at 4:57 AM, Markus Hitter wrote: BTW., there were electronic circuitries before PCBs were invented and the future of electronics manufacturing is most likely something three-dimensional, arbitrarily shaped. Yes. I'm now working with two groups that are fabricating parts with 3-D printers. I've been wondering when the technology will reach the point where the printing could include conductors, with components placed during the build-up, and then buried. But I suppose describing this is beyond what we can conceptualize here at this time. Planes are difficult enough. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
Martin Kupec martin.ku...@kupson.cz writes: On Fri, Mar 18, 2011 at 09:00:04PM +0100, Stephan Boettcher wrote: Martin Kupec martin.ku...@kupson.cz writes: That is a bit complicated. I need a clean definition of layer types, so one can pick the right layer when needed. But some attributes in addition to layer type are possible. I do not understand that argument. Ok. We probably don't understand each other, so I will just state my fears. I would like to know about each drawing layer where it belongs to. If layers types would be defined by attributes, someone would be able to declare one layer both as conductive and as silk for example. That could cause me a nighmares. That is why I insist on 'typed' layers, not 'tagged' layer. Hmm. I think that is the old trap of overloading. When you say that a layer type defines what you can do with it, then this one type attribute becomes messily overloaded. -- Stephan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
John Doty j...@noqsi.com writes: On Mar 19, 2011, at 4:57 AM, Markus Hitter wrote: BTW., there were electronic circuitries before PCBs were invented and the future of electronics manufacturing is most likely something three-dimensional, arbitrarily shaped. Yes. I'm now working with two groups that are fabricating parts with 3-D printers. I've been wondering when the technology will reach the point where the printing could include conductors, with components placed during the build-up, and then buried. But I suppose describing this is beyond what we can conceptualize here at this time. Planes are difficult enough. As long as this 3D structure is built mainy manhattan style, with horizontal conductive layers and vias, all conductive layers become component layers, an element must define keepout zones on those layers that it's housing penetrates. It's pads are on layers that correspond to the z-positions of it's pins. Before you start making your footprint library you need to decide on the thickness and distance between the conductive layers. The kind of tool we were discussion here could do that very nicely. A GUI plugin needs to be written, that allows to move the 3delements up and down in the layer stack. Maybe even rotate off plane, but that is initially best done by hand as a separate 3dfootprint. One more argument to implement holes as shapes on a hole layers. -- Stephan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
On Mar 18, 2011, at 2:23 PM, Martin Kupec wrote: If layers types would be defined by attributes, someone would be able to declare one layer both as conductive and as silk for example. That could cause me a nighmares. That is why I insist on 'typed' layers, not 'tagged' layer. No. The nightmare is classification. It's perfectly possible to put conductive ink on a board with a silkscreen process. Layers should, of course, have electrical properties: conductivity, dielectric constant, permeability. Also thermal and mechanical. More grist for the composition machinery, of course, because users will want to use copper as shorthand for a list of properties. But the properties are what the code should be paying attention to. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
On Sat, Mar 19, 2011 at 10:14:54AM -0600, John Doty wrote: On Mar 18, 2011, at 2:23 PM, Martin Kupec wrote: If layers types would be defined by attributes, someone would be able to declare one layer both as conductive and as silk for example. That could cause me a nighmares. That is why I insist on 'typed' layers, not 'tagged' layer. No. The nightmare is classification. It's perfectly possible to put conductive ink on a board with a silkscreen process. No problem here. Just define that conductive ink as copper or conductive type layer. I don't care how that layer happens to be manufactured. Martin Kupec ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
On Sat, Mar 19, 2011 at 04:43:29PM +0100, Stephan Boettcher wrote: Martin Kupec martin.ku...@kupson.cz writes: On Fri, Mar 18, 2011 at 09:00:04PM +0100, Stephan Boettcher wrote: Martin Kupec martin.ku...@kupson.cz writes: That is a bit complicated. I need a clean definition of layer types, so one can pick the right layer when needed. But some attributes in addition to layer type are possible. I do not understand that argument. Ok. We probably don't understand each other, so I will just state my fears. I would like to know about each drawing layer where it belongs to. If layers types would be defined by attributes, someone would be able to declare one layer both as conductive and as silk for example. That could cause me a nighmares. That is why I insist on 'typed' layers, not 'tagged' layer. Hmm. I think that is the old trap of overloading. When you say that a layer type defines what you can do with it, then this one type attribute becomes messily overloaded. So far we have like 10 types. That is not that bad. Some new may come, but it is still keeping low. The other way is to have a dozen of different attributes. And probably with some constrains and hierarchy. I think that is more complicated. Martin Kupec ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
On Mar 19, 2011, at 10:50 AM, Martin Kupec wrote: On Sat, Mar 19, 2011 at 10:14:54AM -0600, John Doty wrote: On Mar 18, 2011, at 2:23 PM, Martin Kupec wrote: If layers types would be defined by attributes, someone would be able to declare one layer both as conductive and as silk for example. That could cause me a nighmares. That is why I insist on 'typed' layers, not 'tagged' layer. No. The nightmare is classification. It's perfectly possible to put conductive ink on a board with a silkscreen process. No problem here. Just define that conductive ink as copper or conductive type layer. I don't care how that layer happens to be manufactured. No. For describing geometry, I agree that the manufacturing process is irrelevant. But the layer needs properties, not some arbitrary classification. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
On Sat, Mar 19, 2011 at 10:56:27AM -0600, John Doty wrote: On Mar 19, 2011, at 10:50 AM, Martin Kupec wrote: On Sat, Mar 19, 2011 at 10:14:54AM -0600, John Doty wrote: On Mar 18, 2011, at 2:23 PM, Martin Kupec wrote: If layers types would be defined by attributes, someone would be able to declare one layer both as conductive and as silk for example. That could cause me a nighmares. That is why I insist on 'typed' layers, not 'tagged' layer. No. The nightmare is classification. It's perfectly possible to put conductive ink on a board with a silkscreen process. No problem here. Just define that conductive ink as copper or conductive type layer. I don't care how that layer happens to be manufactured. No. For describing geometry, I agree that the manufacturing process is irrelevant. But the layer needs properties, not some arbitrary classification. I never said that you cannot add additional properties(attributes) to the layers. I am just saying that there should be some, as you say, arbitrary classification. And than you refine that clasification by some properties. But the basic classification will be clean and understood by all parts of pcb. The additional properties can be admited just by some parts. Martin Kupec ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
On Mar 19, 2011, at 11:01 AM, Martin Kupec wrote: On Sat, Mar 19, 2011 at 10:56:27AM -0600, John Doty wrote: On Mar 19, 2011, at 10:50 AM, Martin Kupec wrote: On Sat, Mar 19, 2011 at 10:14:54AM -0600, John Doty wrote: On Mar 18, 2011, at 2:23 PM, Martin Kupec wrote: If layers types would be defined by attributes, someone would be able to declare one layer both as conductive and as silk for example. That could cause me a nighmares. That is why I insist on 'typed' layers, not 'tagged' layer. No. The nightmare is classification. It's perfectly possible to put conductive ink on a board with a silkscreen process. No problem here. Just define that conductive ink as copper or conductive type layer. I don't care how that layer happens to be manufactured. No. For describing geometry, I agree that the manufacturing process is irrelevant. But the layer needs properties, not some arbitrary classification. I never said that you cannot add additional properties(attributes) to the layers. I am just saying that there should be some, as you say, arbitrary classification. And than you refine that clasification by some properties. But the basic classification will be clean and understood by all parts of pcb. The additional properties can be admited just by some parts. That's a design approach that leads to metastatic problems down the road. You should avoid the sloppy mental tendency of humans to classify where nature is continuous. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
On Mar 18, 2011, at 2:19 PM, DJ Delorie d...@delorie.com wrote: I don't want to end up with the current state that some 'specialy named' layers receive special treatment. From a practical standpoint, I think it makes sense to have a fast way to scan for layers of some high-level type, as well as further typing them by name. My original design had an enumerated type for each drawing layer, that was one of (for example) copper, silk, soldermask, paste, outline, other with flags for normal, inverted and an assignment to a physical layer (1..N). That way, when you're doing something compute-intensive like connectivity checks for auto-enforce drc clearance you aren't doing a bazillion string compares. You can build a hash for storage in ram, the file format uses strings. This way you get fast integer math with flexibility of not needing to pre ordain types. The cost is on import. Where everything is string compairasons. This is a kind of premature optimization. Steve Actions that are performed less often, like mapping a footprint to an element, can use a more open-ended string-attribute with more complex rules. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
On Mar 18, 2011, at 3:07 PM, DJ Delorie d...@delorie.com wrote: That's the kind of top down design that produces a tool that meets today's requirements in the minimum amount of time, but produces an inflexible tool limited to those requirements. And your kind of bottom-up design never gets done at all, because of impossible-to-meet requirements for unlimited flexibility. Wow all my bottom up designs in shipping products must not exist A few million users disagree. Top down and bottom up are a preference, not set in stone. FWIW I use both methods. My diagnostic tools start by me normally building small useful functions that get then assembled into larger functions. The team working on the top down diagnostics gave up after my bottom up design for lab testing was doing all that they planned and more. To top the cake, they implemented a feature that they were expecting to take two weeks in about 45 minutes because my bottoms up design had functions that were the bulk of what they needed. But if you start from a data representation that spans the space of the possible, it drives you toward flexibility and extensibility in the upper layers. The problem is, the space of the possible is infinitely large, and we have a very small finite set of developers. Unless we know how the tool is going to be used, we don't even know what the space of the possible *is*. Being an engineer is partly knowing when enough is ready to ship. Bottom up designs do have high level goals, it's our job to keep feature creep at a minimum. As far as I know I have only asked for file format requirements that are used in current technology mass-produced boards and for extra data to allow the manufacturing and simulation to be enhanced. Layer materials and diamentions to allow impedance measurement in object reports Steve ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
On Mar 18, 2011, at 3:22 PM, Stephan Boettcher boettc...@physik.uni-kiel.de wrote: DJ Delorie d...@delorie.com writes: ... I think the tool we have is pretty good already. Very good. Thanks! The tool we have already is nearly impossible to maintain, though. Please do not expect that users write plugins. The tool is already too good as it is to make is worth the effort to learn how to do that. I expect the plugin mechanism to be the way to write *all* the core bits, though. The more important it is, that what is below the plugin mechanism is as general as necessary, and since that is difficult to judge up front: as general as possible, without compromising the final goals. I'd propose a very basic, very general storage data representation. Just layers, shapes, and arbitray levels of composites, the layout implicitly being the top level composit. Everything with arbitrary attributes. On top of that is a memory representation, that introduces the concepts of elements, vias, surface-layers (layer sets: copper, mask, silk, courtyard, keepout), connectivity, It provides basic operations on these concepts. The implementation of these concepts builds on the objects of the storage data layers. It must not be an error if a via has two holes, a polygon shaped hole or silk in it. DRC may flag such things, but it must not be an error. Ahh, dreaming of a via that is untented, circled automatically, and net named. Instant testpoint! Perhaps by a testpoint tool, that would make pads centered on a trace with the same properties. The attributes that this memory representation and it methods understand shall be in namespace pcb: and unknown attributes in that namespace shall emit warnings. The plugins define their own attributes. Attributes shall not be overloaded. If a plugin operates on attributes of the memory representation, it shall do that via methods of that representation, if possible. Higher level parts of the concepts element, via, surface layer may be implemented in plugins. I cannot keep up, there are 15 new messages in my inbox, lets see what what new arguments come up :-) I cannot make up my mind if I should continue to argue for hole layers, or if holes shall be shapes with hole attribute on layers. The fact that the *user* can write them *also* is a side-effect :-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Stephan Böttcher FAX: +49-431-85660 Extraterrestrische PhysikTel: +49-431-880-2508 I.f.Exp.u.Angew.Physik mailto:boettc...@physik.uni-kiel.de Leibnizstr. 11, 24118 Kiel, Germany ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
On Mar 18, 2011, at 3:43 PM, DJ Delorie d...@delorie.com wrote: I expect the plugin mechanism to be the way to write *all* the core bits, though. The more important it is, that what is below the plugin mechanism is as general as necessary, and since that is difficult to judge up front: as general as possible, without compromising the final goals. As general as neccessary, but not as general as *possible*. On top of that is a memory representation, that introduces the concepts of elements, vias, surface-layers (layer sets: copper, mask, silk, courtyard, keepout), connectivity, This is the part I wish we were discussing. It provides basic operations on these concepts. The implementation of these concepts builds on the objects of the storage data layers. It must not be an error if a via has two holes, a polygon shaped hole or silk in it. DRC may flag such things, but it must not be an error. There must be *some* limits, however, or the tools cannot be written. Defining a hole in a silk layer is nonsensical, if you wish to support it, we cannot define what the tools would do with it. I would make it mask out the area that is defined as the hole. Can't put silk on a hole. ( in the gerber exporter ) The attributes that this memory representation and it methods understand shall be in namespace pcb: and unknown attributes in that namespace shall emit warnings. You assume that attributes are the way to organize groups of things. Why? Higher level parts of the concepts element, via, surface layer may be implemented in plugins. How does a move tool plugin interact with an element plugin, then? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
On Mar 18, 2011, at 4:02 PM, DJ Delorie d...@delorie.com wrote: Except gerbers have special cases for thermals and pads, for example. So there need to be attributes on shapes. No, the exporters really need to have access to the whole collection of shapes that means pin so they can do pin-specific things. If the exporter doesn't need that high-level access, then the default action breaks it down into shapes and exports them individually. The gerber exporter needs to be given a whole pin because it has a command that means put pin here, with this aperture and thermal settings. If you wait until the core descends to circle, arc, line, it's too late to look at the attributes and figure out what's happening. CAM tools know about this, and can adjust thermals and pins as needed, but in PCB's case they can't do it because we break pins down into raw shapes. and containing other layers as sub-layouts. I have never disagreed with this! Oh. My understanding of composites is different. I assume a composite contains shapes that go on a global set of layers. This is part of the communication problem we're having, yes ;-) Consider these: * A footprint is a global resource, but an instance of a footprint (an element) must be mapped to the physical layout. When do you manage the footprint as an element (indivisible) and when do you access its parts (changing pad size)? * A sub-circuit that's replicated N times on a board. * A flex cable that has 4 layers at each end, but only 2 layers in the middle. The extra layers on the end are on opposite sides of the cable. * buried vias are limited to certain pairs of layers because of the way the fab is assembling the board. * 400 instances of a standard via, but the user needs to modify the pad stack on just one of them, and only for one layer. These are all examples of a need for both a semantic and data heirarchy, where parts of your design are grouped together and treated as a single object, sometimes replicated, sometimes customized. What we call them is not important. Well, yes, it can, except that a via is not sufficiently special to justify the distiction. What would we have in a composite, the layout being the top-level composite? Vias Elements Composits that are not Vias or Elements Lines Shapes outside of composits that are not Lines Consider: you can move a via, but for lines, you can move either the line or its endpoints. For a polygon you can move its corners. Ah, but a via can include polygons and lines - but when it's a via, you *don't* move their endpoints and corners, unless you specifically edit the via. A pin is just like a via, except you *don't* move it - you move the element it's in. Now consider a differential pair. It's a line but you *don't* move the *line* endpoints, you move the *pair* control points. So yes, a via is special. Many other composite objects will be special too, because the tools need to know what the appropriate way of interacting with them are. PCB layout is *not* a paint program, it's a design tool. It *must* understand the design if it's to be the most useful to the user. I read this as groups in the memory model should have a sort of locked flag, so that tools like move don't dig deeper to move the individual parts of a group, unless forced (unlocked). And that groups need group control point(s) When an how to map generic element layers to layout layers is another good question. Yup. Global layers can be mapped at load time. Local layers inside composits must be mapped a runtime, don't they? The mapping can be computed at load time, and just stored. I suspect there'll be lots of recurse through the data heirarchy code. I see a load time generated list of objects in a layer. That gets added to and removed from doubly linked to the composites the objects belong to. This would allow the object to manipulate the list and for the list to get right to the object. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
On Mar 18, 2011, at 4:17 PM, Stephan Boettcher boettc...@physik.uni-kiel.de wrote: DJ Delorie d...@delorie.com writes: I expect the plugin mechanism to be the way to write *all* the core bits, though. The more important it is, that what is below the plugin mechanism is as general as necessary, and since that is difficult to judge up front: as general as possible, without compromising the final goals. As general as neccessary, but not as general as *possible*. But we cannot know what is necessary. On top of that is a memory representation, that introduces the concepts of elements, vias, surface-layers (layer sets: copper, mask, silk, courtyard, keepout), connectivity, This is the part I wish we were discussing. As John said, bottom up works better in the long term :-) It provides basic operations on these concepts. The implementation of these concepts builds on the objects of the storage data layers. It must not be an error if a via has two holes, a polygon shaped hole or silk in it. DRC may flag such things, but it must not be an error. There must be *some* limits, however, or the tools cannot be written. Defining a hole in a silk layer is nonsensical, if you wish to support it, we cannot define what the tools would do with it. Why not? The tool can move it arount and not much else, like with all objects on a sliklayer. But that's why I argue for hole layers. A hole is a shape on a hole layer. The layers attributes define what needs to be drilled. Actually, they only define to which layers they electrically conduct. That is all the tools needs to know until checkout. DRC checks if all shapes are circles, unless the shape has a DRC overide attribute. There would be one hole layer for each drill pattern, i.e., one, unless there are partial vias. John's insulating layers will be mentioned in the attributes, so they get drilled too. What you call a hole layer is what I consider the insulating layer. Or do your hole layers span physical layers? Mimicking the ability of the process. (required to make the blind and burried vias your design dictates) Side note, the full stackup is a core part of the pcb design and should be chosen at an early stage. Meaning that all the materials are chosen and dimensioned. An example is: a four layer board is two double sided boards with prepreg between. Such that the top copper, fr4, and second layer are a hole layer. The bottom copper, fr4, and third copper layer are the next hole layer. And the third hole layer is the top copper all the way to the bottom copper? A via with variable hole size for different layers must be built as a composit with multiple holes on as many hole layers. Inefficient but appropriate for such an obscure case. The attributes that this memory representation and it methods understand shall be in namespace pcb: and unknown attributes in that namespace shall emit warnings. You assume that attributes are the way to organize groups of things. Why? So that everything is just shapes on layers. Very simple, very powerful. Higher level parts of the concepts element, via, surface layer may be implemented in plugins. How does a move tool plugin interact with an element plugin, then? The memory core representation provides methods to move, rotate, mirror shapes and composits. (Element composits may have an attribute that forbids mirroring.) To bring an element to the other side od the board is method of the Element plugin, relying on attributes of the relevant layers how they map to the other side. I don't think that the concept of vias and elements shall be fully implemented in plugins, for efficiency, and since most other plugings may need refer to these concepts. At least some callback hooks need to be specific to elements or vias, that a plugin can register. So that a plugin can intercept composite methods (e.g., move) for elements or vias. -- Stephan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
On Mar 18, 2011, at 4:37 PM, DJ Delorie d...@delorie.com wrote: Still, I do not see a need for outline layers anywhere, except as an attribute on a graphical layer that tells an exporter where to stop drawing. Hmmm... so you think PCB should let the user place an element in a physically impossible location, because it doesn't care about the outlines? Yes, I hate how pcb used to limit moving footprints silk off the edge of a board. Yes easily solved by adding the outline layer. It is also useful for staging your placement. Perhaps color portion off of the outline of it's base layer? In other words, if you place an element over a transition from rigid to flex, where the rigid or flex that has the most pins is defined as the base layer, I have used flexes where components are on the flex portion. Avoid resistors and ceramic caps, they tend to get their end caps ripped off, bit a sc-70 works fine usually. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
On Mar 18, 2011, at 4:39 PM, DJ Delorie d...@delorie.com wrote: It is the exporter's job to understand drilling. For geometry capture, all you need to know is the shape. Modules with no need to know should not know. The autorouter needs to know not to run traces across unplated holes... This is what bothers me about a hole layer, un plated vs plated, the holes do not define electrical contact, the plating does. Or, rivits, or the soldered wires on hand assembled multilayer boards. Well with silver ink circuit printing. The hole in the sprayed on insulators does define the connectivity ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
This message makes me think that COW should remember what master it was copied from and an edited flag. On Mar 18, 2011, at 5:16 PM, Stephan Boettcher boettc...@physik.uni-kiel.de wrote: DJ Delorie d...@delorie.com writes: Except gerbers have special cases for thermals and pads, for example. So there need to be attributes on shapes. No, the exporters really need to have access to the whole collection of shapes that means pin so they can do pin-specific things. If the exporter doesn't need that high-level access, then the default action breaks it down into shapes and exports them individually. The gerber exporter needs to be given a whole pin because it has a command that means put pin here, with this aperture and thermal settings. If you wait until the core descends to circle, arc, line, it's too late to look at the attributes and figure out what's happening. CAM tools know about this, and can adjust thermals and pins as needed, but in PCB's case they can't do it because we break pins down into raw shapes. I do not understand this. The gerber exporter exports each layer separately, no? On some layer it finds a circle with a thermal attribute surounded by a polygon. What else does in need? and containing other layers as sub-layouts. I have never disagreed with this! Oh. My understanding of composites is different. I assume a composite contains shapes that go on a global set of layers. This is part of the communication problem we're having, yes ;-) Consider these: * A footprint is a global resource, but an instance of a footprint (an element) must be mapped to the physical layout. When do you manage the footprint as an element (indivisible) and when do you access its parts (changing pad size)? Is the footprint still part of the layout? Wouldn't it's genereic layers (top,inner,bottom) be mapped to the layout layers (oben,innen1,innen2,unten) when imported? * A sub-circuit that's replicated N times on a board. composites instances are objects inside other composites, next to shapes. You can do most operations to composites, that you do to shapes (move, rotate, mirror, delete, ...). Vias and elements are special in the memory representation, as there are methods, or callback hooks that allow access to some internals without explicitly decending into the composit. It should be possible to flag any composit as Element or vise versa, to turn on and off this special access. If you exlicitly decend into an element, you can move its pins and pads. But pads size, text positions e.t.c. are still directly accessible for elements. Maybe it is not even necessary to have any special treatment and treat all composites the same. * A flex cable that has 4 layers at each end, but only 2 layers in the middle. The extra layers on the end are on opposite sides of the cable. You want to describe the rigid ends as outlines of a composite? That attaches high-level semantics to a low level concept in an inapropriate way. Here you need outline layers with attributes that tell the autorouters not to cross the lines on certain layers. * buried vias are limited to certain pairs of layers because of the way the fab is assembling the board. A DRC problem. With hole layers, the GUI tool to add/manipulate these hole layers can provide a view on the layer stack that represents the stacking and drilling order, just like you once proposed as an underlying data structure. The tool would refuse to configure holes layers that cannot be drilled, unless you say please. * 400 instances of a standard via, but the user needs to modify the pad stack on just one of them, and only for one layer. Vias may be COW by default, like they are now. But you can decend in non-copy mode into the composite, so they all change. That composit is also the master copy in the Via menu, so that future vias of that type are affected by the edit. When you edit the via definition in the Via menu, you may need to answer a question if you want all existing instances to change, of only new vias. These are all examples of a need for both a semantic and data heirarchy, where parts of your design are grouped together and treated as a single object, sometimes replicated, sometimes customized. What we call them is not important. Well, yes, it can, except that a via is not sufficiently special to justify the distiction. What would we have in a composite, the layout being the top-level composite? Vias Elements Composits that are not Vias or Elements Lines Shapes outside of composits that are not Lines Consider: you can move a via, but for lines, you can move either the line or its endpoints. For a polygon you can move its corners. Ah, but a via can include polygons and lines - but when it's a via, you *don't* move their endpoints and corners, unless you specifically edit the via. A pin is just like a via,
Re: gEDA-user: General Layers questions
On Mar 19, 2011, at 8:13 AM, John Doty j...@noqsi.com wrote: On Mar 19, 2011, at 4:57 AM, Markus Hitter wrote: BTW., there were electronic circuitries before PCBs were invented and the future of electronics manufacturing is most likely something three-dimensional, arbitrarily shaped. Yes. I'm now working with two groups that are fabricating parts with 3-D printers. I've been wondering when the technology will reach the point where the printing could include conductors, with components placed during the build-up, and then buried. Put in a conductive silver epoxy nozzle and a pick and place head, bam your done! :-) But I suppose describing this is beyond what we can conceptualize here at this time. Planes are difficult enough. You would add this capability to something like solid works. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
On Mar 19, 2011, at 1:20 PM, Steven Michalske wrote: This is what bothers me about a hole layer, un plated vs plated, the holes do not define electrical contact, the plating does. Or, rivits, or the soldered wires on hand assembled multilayer boards. Well with silver ink circuit printing. The hole in the sprayed on insulators does define the connectivity This demonstrates a flaw in the hole layer concept. It doesn't actually capture the geometry. But if the layers are physical, the objects in them might have different properties. So a plated-through hole is geometrically a place in a layer that is mostly insulator, but has a conductive annulus at a particular place. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
On Mar 19, 2011, at 9:50 AM, Martin Kupec martin.ku...@kupson.cz wrote: On Sat, Mar 19, 2011 at 10:14:54AM -0600, John Doty wrote: On Mar 18, 2011, at 2:23 PM, Martin Kupec wrote: If layers types would be defined by attributes, someone would be able to declare one layer both as conductive and as silk for example. That could cause me a nighmares. That is why I insist on 'typed' layers, not 'tagged' layer. No. The nightmare is classification. It's perfectly possible to put conductive ink on a board with a silkscreen process. No problem here. Just define that conductive ink as copper or conductive type layer. I don't care how that layer happens to be manufactured. Simulation! As long as the parameters can be specified then were good. And when I say simulation it can be either a exporter to a field solver for antennas, or a trace width calculator for current limits used while specifying line widths. i.e. Not an exporter. Imagine drawing a trace with a width of 50 ohms single ended to ground. When you move layers it would make the correct via with the proper clearances to the plane. The realtime DRC prevents you from crossing the edge of your reference plane. And when your top layer is separated from the ground plane by .2 mm of FR4 it know the width, and when it dropped to layer 3 between 2 planes it asked how to calculate the trace. Referenced to one or both. Or it could have Known that the separation of 1mm from layer 4 plane was enough not to consider it. Ahh, that would be fantastic! Martin Kupec ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
On Mar 19, 2011, at 12:33 PM, John Doty j...@noqsi.com wrote: On Mar 19, 2011, at 1:20 PM, Steven Michalske wrote: This is what bothers me about a hole layer, un plated vs plated, the holes do not define electrical contact, the plating does. Or, rivits, or the soldered wires on hand assembled multilayer boards. Well with silver ink circuit printing. The hole in the sprayed on insulators does define the connectivity This demonstrates a flaw in the hole layer concept. It doesn't actually capture the geometry. But if the layers are physical, the objects in them might have different properties. So a plated-through hole is geometrically a place in a layer that is mostly insulator, but has a conductive annulus at a particular place. Oh my! You can draw The plating on the insulator layer. Thus making the plating a real object of conductor This is more 3d cad leaking through. That would mean that drawing on a insulator/separator would define some material to replace the seperator with, and they would need properties. Plated through hole, conductive epoxy filled, thermal epoxy filled. The drawn shapes would need properties The exporter would see a hole and it's anulis and drill a hole the size of the anulis or hole based on a flag in the exporter about the fab shop's preference on finished or drill sizes. Edge plating would be a line drawn at the egge of the board that moved in the outline of the pcb by the plating thickness. A plating tool could be made to draw the required shapes on each layer through the board. Like the copper trace on the copper layers to plate to and the plating on the insulator. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Multi-Select with SHIFT, CTRL...
On Mar 18, 2011, at 4:41 PM, Stefan Salewski m...@ssalewski.de wrote: On Fri, 2011-03-18 at 19:17 -0400, DJ Delorie wrote: shift-leftclick on object Don't forget about select-region, select-touching, select-touching-line, etc. I guess that is not too common in schematics? Here is my current draft for my gschem clone: Peted intended user interface behaviour -- first draft -- LMBD: Left mouse button down (press) action LMBU: Left mouse button up (release) action MMBD: Middle mouse button down (press) action MMBU: Middle mouse button up (release) action RMBD: Right mouse button down (press) action Our intention is to have a smart AUTO mode which will allow to do the most common actions fast with minimal effort (beside traditional special modes like Move, Net, Erase, Line, Arc, Text, ...) These action include: Select, move, copy, delete, rotate, start new net. LMBD over element: Start moving element, LMBU will terminate action, element is unselected LMBD + LMBU over element (no motion): select element, unselect all other SHIFT + LMBD + LMBU over element: add element to selection CTRL + LMBD + LMBU over element: toggle element, leave other unchanged LMBD over unpopulated area: start selection rectangle No modilier: elements in rectangle will become selected, other unselected SHIFT modifier: add elements in rectangle to selection, other unchanged CTRL modifier: toggle state of elements in rectangle, other unchanged MMBD: put a copy of selected element(s) to position of mouse pointer special case: MMBD over selected element: detete it if nothing is selected or SHIFT modifier is used: panning RMBD: Context sensitive menu open Scroll wheel: rotate selection or element under mouse pointer If nothing is selected and mouse pointer is over unpopulated area or SHIFT modifier is used: Zoom in/out Track pad users may want scroll to be scrolling So consider that, although I rarely edit layouts by trackpad there are times that I do and hate zooming in and out. But when using a mouse I do want zoom in and out on the scroll wheel. If your toolkit allows for the apple trackpad gestures... That could add a few options into the mix In net mode double left click ends the current net. LMBD + LMBU over hot pin end: start new net segment You added net end, but starting at the middle of a net segment is valuable too. Missing: Zoom into rectangle For element properties we will not use a popup window opened by double click, but a separate area at the left or right of the main window. Properties of selected elements are displayed in this area and can be modified. This area can be used for various other purposes, i.e. symbol library preview, color selections, ...It should be possible to fully shrink this area. At the bottom of the main window we may have an area for log messages. We should try to allow multiple instances of our GUI window, showing different or the same content. For the last case, we can display an overview in one window, while we work on details in a different window, maybe both windows can reside on different monitors. Of course it should be possible to use only one window, and switch between different content. Have I forgotten common important actions? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Multi-Select with SHIFT, CTRL...
On Sat, 2011-03-19 at 13:14 -0700, Steven Michalske wrote: Scroll wheel: rotate selection or element under mouse pointer If nothing is selected and mouse pointer is over unpopulated area or SHIFT modifier is used: Zoom in/out Track pad users may want scroll to be scrolling So we should have an option to ignore the scroll wheel for rotate/zoom. Of course for zooming we should have additional keyboard and button support. And for zooming into a selection rectangle I currently consider using the middle mouse button. For rotating elements again we will have keyboard and button support -- but I think using the scroll wheel would be really fun, i.e for rotating text. If your toolkit allows for the apple trackpad gestures... That could add a few options into the mix PCB or gschem, one of them, has gesture support by a library -- once I have asked on this list about it, but it seem that nobody uses that. I have currently no idea about gestures, so I do not intend supporting it now. In net mode double left click ends the current net. Yes -- not a true double click (in a small time interval) but simple adding a net segment of length 0. As supported by gschem. ESC and maybe another key will also end net segments. LMBD + LMBU over hot pin end: start new net segment You added net end, but starting at the middle of a net segment is valuable too. Yes, but grabbing an element in the middle is used generally for moving or selecting, so we may have a conflict. We may try to resolve it, or have a Start new net button for that case. I consider a only onces mode beside real modal operation: For example, it may occur that we intend only a single mirror operation without leaving the current mode (comming back after one mirror operation) or we want a real mirror mode, where each click on an element will mirror that one. My current idea: If an element is selected/highlighted then mirror button or key will mirror that selected element. If noting is selected, then we will enter a permanent mirror mode. Additional, I will support highlight of elements, when the mouse pointer is hovering over it. Current highlight method is making colors brighter, move the element a few pixel to upper right, and draw a shadow, generating the impression of lifting the elements. Problem: We can not use white (pin) color, because there is no brighter shade of white, and shadow works not good for dark backgrounds. Of course we can always use fallback to a plain monochrome highlight color. Another method is drawing highlighted elements with thicker lines -- I have not tested that yet. Best regards, Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
On Mar 19, 2011, at 2:03 PM, Steven Michalske wrote: Oh my! You can draw The plating on the insulator layer. Thus making the plating a real object of conductor This is more 3d cad leaking through. DJ once made the observation that pcb's basic problem is the lack of a proper layer stackup abstraction. My opinion is that designing for metaphysical pseudo-layers like the proposed hole layer is a major barrier to correctly modeling a circuit board as a layered stack. Stacking of plane layers is fundamentally a 3D concept. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Multi-Select with SHIFT, CTRL...
On Mar 19, 2011, at 2:38 PM, Stefan Salewski m...@ssalewski.de wrote: On Sat, 2011-03-19 at 13:14 -0700, Steven Michalske wrote: Scroll wheel: rotate selection or element under mouse pointer If nothing is selected and mouse pointer is over unpopulated area or SHIFT modifier is used: Zoom in/out Track pad users may want scroll to be scrolling So we should have an option to ignore the scroll wheel for rotate/zoom. Of course for zooming we should have additional keyboard and button support. And for zooming into a selection rectangle I currently consider using the middle mouse button. For rotating elements again we will have keyboard and button support -- but I think using the scroll wheel would be really fun, i.e for rotating text. If your toolkit allows for the apple trackpad gestures... That could add a few options into the mix PCB or gschem, one of them, has gesture support by a library -- once I have asked on this list about it, but it seem that nobody uses that. I have currently no idea about gestures, so I do not intend supporting it now. In net mode double left click ends the current net. Yes -- not a true double click (in a small time interval) but simple adding a net segment of length 0. As supported by gschem. ESC and maybe another key will also end net segments. LMBD + LMBU over hot pin end: start new net segment You added net end, but starting at the middle of a net segment is valuable too. Yes, but grabbing an element in the middle is used generally for moving or selecting, so we may have a conflict. We may try to resolve it, or have a Start new net button for that case. I consider a only onces mode beside real modal operation: For example, it may occur that we intend only a single mirror operation without leaving the current mode (comming back after one mirror operation) or we want a real mirror mode, where each click on an element will mirror that one. My current idea: If an element is selected/highlighted then mirror button or key will mirror that selected element. If noting is selected, then we will enter a permanent mirror mode. Additional, I will support highlight of elements, when the mouse pointer is hovering over it. Current highlight method is making colors brighter, move the element a few pixel to upper right, and draw a shadow, generating the impression of lifting the elements. Problem: We can not use white (pin) color, because there is no brighter shade of white, and shadow works not good for dark backgrounds. Of course we can always use fallback to a plain monochrome highlight color. Another method is drawing highlighted elements with thicker lines -- I have not tested that yet. Make shadow a glow on dark backgrounds Best regards, Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
On Mar 18, 2011, at 2:25 PM, DJ Delorie wrote: Inkscape gives you complete flexibility, and it's absolutely useless as a pcb layout tool. Indeed. So please remember that the job of a layout tool is to describe the *geometry* of *physical* objects. It's *not* just a graphical tool, nor should it describe the fabrication procedure. Its foundations must be based on geometric abstractions, not metaphysical intentions. It seems to me that your conception is much closer to Inkscape than mine is. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Tragesym template problem.
Hello, I am trying to fill out the Tragesym template for an ATmega128RFA1, but the script gives me an error when I pass it the CSV file (renamed to a .sch file): error: version attribut missing In the template, I had changed the example version number to 20110319 1, following the format of the template version number. I verified that the CSV file contains a version line. Has anyone out there found a solution to this problem? I am following the tutorial at http://geda.seul.org/wiki/geda:tragesym_tutorial;, using the OpenOffice template. Thanks, Dan. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: TDSON-8 footprint
I'm using a mosfet with a TDSON-8 footprint. I looked on [1]gedasymbols.org and couldn't find anything. I also can't find anything in PCB. Does anyone have this or can someone direct me? I'd rather not have to make one. Also if a symbol would be great too. Thanks References 1. http://gedasymbols.org/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Tragesym template problem.
On Sat, 2011-03-19 at 15:57 -0700, Daniel Ross wrote: Hello, I am trying to fill out the Tragesym template for an ATmega128RFA1, but the script gives me an error when I pass it the CSV file (renamed to a .sch file): error: version attribut missing In the template, I had changed the example version number to 20110319 1, following the format of the template version number. I verified that the CSV file contains a version line. Has anyone out there found a solution to this problem? I am following the tutorial at http://geda.seul.org/wiki/geda:tragesym_tutorial;, using the OpenOffice template. Thanks, Dan. Hm -- have not used tragesym for more than a year. Tragesym is fine, but I do not like the documentation. Please note, input to tragesym is plain text. I really wonder why they advertise use of spreadsheet, I have always used a plain text editor. (OK, spreadsheet may be fine if you try to copy from pdf datasheet...) Do not call tragesym input .sch, that is for schematics. I used .txt extension, it is plain text. The version should be not current date, if I remember correctly, but something related with gschem version. I think that version is copied to symbols, if it is to high, gschem may refuse loading the symbol. My final guess: There may be something wrong with your input file for tragesym, maybe in front of version line. Watch in a plain text editor. You may find working tragesym input files for testing at www.gedasymbols.org. Or fill in tragesym's template.txt with a text editor, leaving version line unchanged. Of course, some people prefer djboxsym, available at www.gedasymbols.org. But tragesym is fine for me. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: TDSON-8 footprint
Not sure the pitch you require but I have a couple of SON's at http://www.luciani.org/geda/pcb/pcb-footprint-list.html (* jcl *) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
