Re: gEDA-user: PCB: option dumpmenu missing
Thanks for your reply! Am 01.06.2011 00:51, schrieb Kai-Martin Knaak: Second thing: In the list of HIDs (line 311-323 of your patch) is the gcode-HID missing. The gcode HID is pretty new. First time I see it mentioned in the mailing list is november 2009. Seems like it had not made it to the repo when I did the command line option patch. Oh! I did not know, that this is such a new feature! (Used pcb the first time in summer 2010) Third thing: I have started to include the first items of your patch by hand to my code. The documentation-generation stops with the message /home/felix/Downloads/geda-git-source/pcb/doc//options.texi:6: `BOM Creation' has no Up field (perhaps incorrect sectioning?). IIRC, this means, that there is a section command missing in the texi code. Thanks for the hint, I will try to figure out my mistake. Last thing: I think the same about the numbering and table-formatting as DJ said in his message http://thread.gmane.org/gmane.comp.cad.geda.user/29944/focus=30083. I think, I would prefer the last solution he suggests (extracting to multiple files), but this are just my 2 cent. I agree, that this may be better. But it escapes me, why my patch has to be perfect to be considered for application. Command line documentation in the manual is as broken as can be. Anything would be better than the current list of bogus options. Yes! [snip] ---<)kaimartin(>--- If you don't mind, I will rebase your patch and modify it to extract the docu-source to several files. Hope, this will get applied in the near future. Kind regards, Felix ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Jumpers on single layer PCBs
On 05/31/2011 04:26 PM, Thomas Oldbury wrote: Double sided boards are great, but not so great when the product is supposed to cost only $3/each What you really want is the high volume technique of using carbon conductive ink traces and insulating layers silk screened on and single copper FR4 or FR2 or composite paper/glass boards with no drilling, just punch press tooling for holes. But then you have to order by the panel full and pay some setup charges for any change once the punch press tool is made. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Jumpers on single layer PCBs
On 05/31/2011 04:26 PM, Thomas Oldbury wrote: Double sided boards are great, but not so great when the product is supposed to cost only $3/each, after an MSP430, mains power supply, heatsink, triac etc. You seem to have BOM'd out on that product... ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Fixing the attribute censorship bug
On May 31, 2011, at 11:02 PM, Peter Brett wrote: The attached script not only emits a message, but substitutes "attribute_conflict" for the attribute in question. Since that's not normally a legitimate value, it should help the user to detect the problem. From my perspective, I don't understand why this is better. 1.7.0 warns about undefined behaviour, In a scripted flow for a large project, warnings like this tend to get lost in all of the other chatter. and defaults to backwards-compatibility (which makes some sense IMHO). No, that behavior is very troublesome. The old behavior is to use the first attribute from the first symbol in the package. But that's quite confusing: in general, the user has no easy way to know or control which symbol is first. This script deliberately poisons the netlist. Exactly. This is consistent with other gnetlist behavior. If no attribute is found, the resulting value is "unknown". So, I think "attribute_conflict" makes sense when there's a conflict. In my ideal world (haha) gnetlist would generate errors on attribute conflicts. :-) What kind of error do you want? gnetlist -m censor_fix.scm (other gnetlist args) For the benefit of those who share your preference for this behaviour: does loading this scm file from a configuration file work? :-) No, because it works by redefining (unique-attribute). That's defined in gnetlist.scm, which is loaded after the configuration files. It wouldn't be hard to set up a mechanism where a configuration file could create a list of deferred actions, to be performed when gnetlist-post.scm is loaded. That would allow this redefinition to be specified in a configuration file, but performed at the right time. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Task list for: Solving the light/heavy symbol problem
> We'll have to be careful to make this transparent to the user. Yes, this is the tricky part. I suspect we'd need "standard names" for various fields, for example the search fields Digikey uses, and figure out some backend rules for how various database chunks are merged, etc. But from the user's point of view, it should be no more complex than our current chooser, perhaps. Or right-click -> attributes -> some sort of dynamic menu. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB: option dumpmenu missing
Felix Ruoff wrote: > First thing: The patch does not apply to my git repository :-(. :-| > Do you > have an actualized version of this patch, that fit to actual git head? No. I did not touch the subject since last year. > Second thing: In the list of HIDs (line 311-323 of your patch) is the > gcode-HID missing. The gcode HID is pretty new. First time I see it mentioned in the mailing list is november 2009. Seems like it had not made it to the repo when I did the command line option patch. > Third thing: I have started to include the first items of your patch by > hand to my code. The documentation-generation stops with the message > /home/felix/Downloads/geda-git-source/pcb/doc//options.texi:6: `BOM > Creation' has no Up field (perhaps incorrect sectioning?). IIRC, this means, that there is a section command missing in the texi code. > Last thing: I think the same about the numbering and table-formatting as > DJ said in his message > http://thread.gmane.org/gmane.comp.cad.geda.user/29944/focus=30083. I > think, I would prefer the last solution he suggests (extracting to > multiple files), but this are just my 2 cent. I agree, that this may be better. But it escapes me, why my patch has to be perfect to be considered for application. Command line documentation in the manual is as broken as can be. Anything would be better than the current list of bogus options. There is no hint how to get the real list of options, either. My patch not only produced a command line section with viable options. It also moved the documentation to the code, so it would have been easier to maintain. Still, it was rejected (after I had to bug the list twice for any reaction at all) because a different solution may be somewhat more elegant. If this is the yardstick improvements must meet, then contribution to geda is beyond my ability. In any case, it clearly surpassed my frustration level. So I let go and directed my efforts to other projects else (not geda). ---<)kaimartin(>--- -- Kai-Martin Knaak Email: k...@familieknaak.de Öffentlicher PGP-Schlüssel: http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Task list for: Solving the light/heavy symbol problem
DJ Delorie wrote: > >> I will put together such a combined symbol and footprint lib >> in my section of gedasymbols. May take about a week or so. > > Excellent! Thanks! After I skipped through what needs to be done, I have to admit that it will take a bit longer. > Hmmm... I don't think "easy" precludes "setting up directories". I > meant, the *internal* structure of the library should be such that the > user can unpack the tree, point to it, and go. For symbols this means a flat tree with no subdirectories at all. I'd say, the search routine of the add symbol dialog really should be enhanced recursively descend to directories. > Yes. However, I don't want us to have a zillion footprints that are > all the same shape, just because each packet has its own copy, either. This is why footprints symbols and essentially any other objects can be embedded in the packet, or referenced. It is up to the designer of the packet library to decide what is the mos useful. > However, if a packet has a *custom* footprint, that's OK. That's what I meant :-) > Your packet idea could be implemented as a subdirectory (contains all > the symbols, footprints, models, relations, etc for a single category > of component), So an object "embedded" in the packet would just be a file in the subdir. I like this. It turns embedding into a reference to the local directory. At the heart of the packet would be a file that gives all the relations and defaults. > My component DB goes one step further - the tool offers the > information it has, and the database passes back *all* the packets > that match, by way of specifying, for each empty attribute, which > values are compatible with the existing ones. Eventually you filter > it down to one option, and you get that component. How would you communicate the rules you taught the database to colleagues? Say, there is a brand new series of FPGAs you'd like to share. > So if you start with "resistor", for example, the next step might be > to pick a value, or a footprint, or a tolerance... but you have to be > able to pick from many packets across many libraries. We'll have to be careful to make this transparent to the user. Else there would be a feeling of inconsistency -- The system seems to erratically choose from different libs. I already found the m4/newlib ambiguity no fun at all. ---<)kaimartin(>--- -- Kai-Martin Knaak Email: k...@familieknaak.de Öffentlicher PGP-Schlüssel: http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Jumpers on single layer PCBs
On Wed, 1 Jun 2011 07:29:33 +1000 Stephen Ecob wrote: > On Wed, Jun 1, 2011 at 6:59 AM, Thomas Oldbury > wrote: > > Oh. Thanks anyway. Any hack-ish way to add this in? (Because I'd > > like each jumper to have a refdes and BOM entry if possible.) > > The hack I use for solder jumpers is to make a footprint that is open > circuit, and bridge where needed with copper text. DRC ignores text, > even when it is on copper layers. So placing a '-' character or a '|' > character on copper with a suitably large font provides an electrical > connection without upsetting DRC. Clever... Now THAT is a HACK in every sense!! ;-) Regards, Colin ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Jumpers on single layer PCBs
Can you still get single sided FR2? On May 31, 2011, at 2:26 PM, Thomas Oldbury wrote: > Double sided boards are great, but not so great when the product is > supposed to cost only $3/each, after an MSP430, mains power supply, > heatsink, triac etc. > > On 31 May 2011 22:09, Levente Kovacs <[1]leventel...@gmail.com> wrote: > > On Tue, 31 May 2011 21:59:04 +0100 > Thomas Oldbury <[2]toldb...@gmail.com> wrote: >> Oh. Thanks anyway. Any hack-ish way to add this in? (Because I'd like >> each jumper to have a refdes and BOM entry if possible.) > > What I'd do is define a copper layer. Draw your jumpers on the that > layer. > Don't send the layer data to the fab house. Make sure you have mask > openings > on vias. Solder jumpers in the vias. > I recommend using double sided boards. > Levente > -- > Levente Kovacs > [3]http://levente.logonex.eu > > ___ > geda-user mailing list > [4]geda-user@moria.seul.org > [5]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > > References > > 1. mailto:leventel...@gmail.com > 2. mailto:toldb...@gmail.com > 3. http://levente.logonex.eu/ > 4. mailto:geda-user@moria.seul.org > 5. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Jumpers on single layer PCBs
On Wed, Jun 1, 2011 at 6:59 AM, Thomas Oldbury wrote: > Oh. Thanks anyway. Any hack-ish way to add this in? (Because I'd like > each jumper to have a refdes and BOM entry if possible.) The hack I use for solder jumpers is to make a footprint that is open circuit, and bridge where needed with copper text. DRC ignores text, even when it is on copper layers. So placing a '-' character or a '|' character on copper with a suitably large font provides an electrical connection without upsetting DRC. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Jumpers on single layer PCBs
Double sided boards are great, but not so great when the product is supposed to cost only $3/each, after an MSP430, mains power supply, heatsink, triac etc. On 31 May 2011 22:09, Levente Kovacs <[1]leventel...@gmail.com> wrote: On Tue, 31 May 2011 21:59:04 +0100 Thomas Oldbury <[2]toldb...@gmail.com> wrote: > Oh. Thanks anyway. Any hack-ish way to add this in? (Because I'd like > each jumper to have a refdes and BOM entry if possible.) What I'd do is define a copper layer. Draw your jumpers on the that layer. Don't send the layer data to the fab house. Make sure you have mask openings on vias. Solder jumpers in the vias. I recommend using double sided boards. Levente -- Levente Kovacs [3]http://levente.logonex.eu ___ geda-user mailing list [4]geda-user@moria.seul.org [5]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:leventel...@gmail.com 2. mailto:toldb...@gmail.com 3. http://levente.logonex.eu/ 4. mailto:geda-user@moria.seul.org 5. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Jumpers on single layer PCBs
On Tue, May 31, 2011 at 2:09 PM, Levente Kovacs wrote: > On Tue, 31 May 2011 21:59:04 +0100 > Thomas Oldbury wrote: > >> Oh. Thanks anyway. Any hack-ish way to add this in? (Because I'd like >> each jumper to have a refdes and BOM entry if possible.) > > What I'd do is define a copper layer. Draw your jumpers on the that layer. > Don't send the layer data to the fab house. Make sure you have mask openings > on vias. Solder jumpers in the vias. > > I recommend using double sided boards. > I was just writing an email recommending that. If you want a BOM of jumper wires, you could make a script that takes all the traces on the jumper wire layer and spits out a list by length and location. Bonus points if it collates jumper wires of the same length and provides a count. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Jumpers on single layer PCBs
On Tue, 31 May 2011 21:59:04 +0100 Thomas Oldbury wrote: > Oh. Thanks anyway. Any hack-ish way to add this in? (Because I'd like > each jumper to have a refdes and BOM entry if possible.) What I'd do is define a copper layer. Draw your jumpers on the that layer. Don't send the layer data to the fab house. Make sure you have mask openings on vias. Solder jumpers in the vias. I recommend using double sided boards. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Two things ... or actually, three
> To my knowledge this is not the case right now. Of course the pin numbers > should not be shown on the schematics: they would use up too much schematics > real estate and are not interesting anyway (even relatively simple and cheap > FPGA devices like XC3S700A has 88 power pins in the 256 pins BGA package, > that's ~35% of the pins): you can't check anything in a BGA package and even > on package that can be probed, it is extremely hard to find, say, a bad solder > joint since all pins of the same power rail are internally connected together. I find that in FPGA design having all pins on the schematic is not an annoyance and is actually a necessity. I usually just make a single component that has all the pins of one type. Eg, a component that contains all the ground pins. I can then draw a net across all the pins connecting them all and then a single ground symbol. The separated out pins are very important for bank power as individual banks can be power by different supplies. For an XC3S700A, a single schematic page showing how power and ground pins are connected is extremely cheap and provides an easy way to do a verification against the data sheet, even by a third party review. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Jumpers on single layer PCBs
> Oh. Thanks anyway. Any hack-ish way to add this in? (Because I'd like each > jumper to have a refdes and BOM entry if possible.) Put them in the schematics :-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Jumpers on single layer PCBs
Oh. Thanks anyway. Any hack-ish way to add this in? (Because I'd like each jumper to have a refdes and BOM entry if possible.) On 31 May 2011 21:44, DJ Delorie <[1]d...@delorie.com> wrote: > Does PCB have any support for adding jumper components, where the > pins would essentially be shorted (the same net) but physically > separate? Not really. ___ geda-user mailing list [2]geda-user@moria.seul.org [3]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:d...@delorie.com 2. mailto:geda-user@moria.seul.org 3. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Jumpers on single layer PCBs
> Does PCB have any support for adding jumper components, where the > pins would essentially be shorted (the same net) but physically > separate? Not really. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Perl
Python! On 31 May 2011 11:26, Jim Lynch <[1]j...@k4gvo.com> wrote: On 05/27/2011 11:54 AM, DJ Delorie wrote: This is more anecdotal than anything else... I'm a Perl fan myself. (shudder) Javascript! ___ geda-user mailing list [2]geda-user@moria.seul.org [3]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:j...@k4gvo.com 2. mailto:geda-user@moria.seul.org 3. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Jumpers on single layer PCBs
Presently I use a second layer (such as a "jumper" layer) to draw on jumpers for single layer FR4 PCBs, however this is cumbersome; and it doesn't support zero ohm SMT resistors. Does PCB have any support for adding jumper components, where the pins would essentially be shorted (the same net) but physically separate? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Two things ... or actually, three
On Mon, 2011-05-30 at 22:59 +0200, Richard Rasker wrote: > Um, OK ... but somehow, my older xgsch2pcb (or perhaps just the older > PCB build) doesn't recognize the layout file edited with the newer PCB > version any more. As a result, I haven't succeeded in updating any > changes in my schematic into the newer PCB version (also see below). > When I try updating the schematic now with xgsch2pcb, I get a completely > new PCB window with all the elements in the upper left corner, and not > the 99% completed and routed layout I have. Hmm, if you have updated gEDA / gnetlist etc.. from git this year, but not recently - you might want to try rebuilding that from a current git version. I'm not sure if it fits your symptoms or not, but there was a nasty bug which sometimes caused problems in gsch2pcb, which was fixed recently. (xgsch2pcb uses gsch2pcb internally). If you're still stuck (and are able / willing to do so), send me a tarball with the design you're having problems with and I'll see what I can do. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Two things ... or actually, three
On Mon, 2011-05-30 at 23:34 +0200, Richard Rasker wrote: > It compiled OK after installing a bunch of dependencies, but I can't > recall at all whether dbus was enabled or not. By the looks of it, I > didn't use git, so I guess dbus is switched off. Is there a way to check > if it is enabled? xgsch2pcb will probably just hang whilst trying to update your design if PCB isn't built with DBUS support. Crappy I know, but we didn't finish all the timeouts and error messages properly yet. Since I recall you were having issues with xgsch2pcb, I wondered if your PCB might be missing DBUS support. From a terminal, run: dbus-monitor | grep pcb Then open and close PCB. (From a different terminal) I get on my machine (with PCB built with DBUS support): string "org.seul.geda.pcb" string "org.seul.geda.pcb" string "org.seul.geda.pcb" string "pcb" string "Unnamed (Unsaved.pcb) - PCB" string "Unnamed (Unsaved.pcb) - PCB" string "org.seul.geda.pcb" > > There is also a new "File" -> "Import Schematics" option which DJ > > produced, which you might like to look at as an alternative to > > xgsch2pcb. > I tried this (see another reply of mine to the mailing list), but right > now, it doesn't seem all that user-friendly, to put it mildly. As Peter Brett and I developed xgsch2pcb, I'm pretty happy with using that myself - so I'll confess that I've not used the new "Import schematics" functionality on an actual project. That said.. I've not started an actual project since that functionality was introduced. Either way, I can't really comment - other than "it looked ok" when I gave it a cursory testing. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: guile under minipack?
Hmmm... what autoconf did your autoreconf use? # Generated by GNU Autoconf 2.66 for guile 1.8.7. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Fixing the attribute censorship bug
> From my perspective, I don't understand why this is better. 1.7.0 warns > about undefined behaviour, and defaults to backwards-compatibility > (which makes some sense IMHO). This script deliberately poisons the > netlist. In my ideal world (haha) gnetlist would generate errors on > attribute conflicts. :-) No, if there's doubt about what the user intended, a hard error is MUCH better than silently (or quietly) hiding the problem. If I have two different part numbers in two slots of one chip, I want the process to STOP. If it can't stop, then anything it can do to make it obvious that something went wrong is GOOD. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gnetlist (was: Perl)
> Why have a core at all? One of the issues with the current gnetlist > is that it cannot be ported to a different Scheme implementation, > because the core is Guile-specific. Why not start from Scheme > functions for reading/writing .sch format? I never said the core had to be C, but given we already have an official "how to read a .sch" in C, it makes sense to use that library - somehow. For the PCB case, I suspect PCB will produce a scheme script that the backend can just run to "load" its data. Perhaps a sch2scm helper program is in order? By "The Core" I meant "the program called gnetlist, which loads the design files and runs the backend". Even if you turn that around and have "the core" be some library that handles the overhead of initializing a netlister, it's still some minimum amount of overhead that needs to be done every time. Basic housekeeping - parsing the command line, loading the .config and finding the backend/library locations, reading design files, etc. - always need to be done. > This is already present, in shallow form, in gnetlist.scm and > gnetlist-post.scm, but much of the digestion happens unconditionally Right. Gnetlist calls "that function" before running the backend, but IMHO the backend should call "that function" - if that's what the backend wants. I suspect a small handful of "that functions" would suffice for the netlisters we already have. > OK, I think we now have a nice creative rivalry between Schemers and > Pythonians. Let's see some code! If you wait for me to write code, it won't be in scheme :-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gnetlist
> so, "load the design files as raw data" seems to mean so that the > same input could be recreated from the internal data representation. Well, assuming we actually record *all* the data. My point was, whatever data we care about, we do the least amount of processing on, unless the backend asks for it. I didn't expect *everything* to be read in *exactly*. > You left out layout, That would be "back-annotation info". In my world, PCB asks for the netlist, so it needs to figure out how to tell gnetlist what its data is. > so I guess you mean reading data about physical stackup in 3D is not > desirable for gnetlist. I kinda agree -- it would be hard for > gnetlist to output that without a lot of physical layout code. Right, but gnetlist needs to know about, for example, pin swapping. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Two things ... or actually, three
> Do I understand correctly that heavy symbols basically have certain nets > with predefined names (e.g. VCC, GND) implicitly included, whereas light > symbols offer the pins to connect those nets oneself? The difference between light and heavy is specificity. A light resistor, for example, is just "resistor". A heavy resistor would be "Rohm 1.2k Resistor, 1%, p/n XYZ, 0603 package with RESC0603M footprint, from Digikey v/n RHM123H-ND" > I checked the PCB reference on this subject for my PCB build > (http://pcb.gpleda.org/pcb-20100929/pcb.html#Import-Action ), but it > isn't clear at all what I should do to import a set of schematic > files (say, myproject_page1.sch, myproject_page2.sch and > myproject_page3.sch, all located in > ~/electronics/customer_x/techfiles/). Simplest version: you have foo.sch and foo.pcb. Import() assumes that, does it all by default. Less simple: foo1.sch and foo2.sch become foo.pcb. Edit the layout attributes, add "import::src0" value "foo1.sch" and "import::src1" value"foo2.sch". Then Import() uses that list of schematics. Least simple: set import::mode to value "make" and do it all in a Makefile. > When I simply choose File -> Import Schematics, PCB's log shows the same > response as when I press "O" -- it tells me the number of remaining rat > lines. At this point, I'm not asked for any schematic files, changed or > not. Check the terminal too, for any gnetlist errors. If your pcb and geda were installed at different locations, gnetlist might not be able to find pcb's importer module. > Should I fill in a space-separated list for src0, pointing to the > various schematic files? And what to do about "(null)", if anything? one file per import::srcN, so src0 is one file, src1 is the next, etc. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Two things ... or actually, three
On Tue, 31 May 2011 05:09:25 +0200 Kai-Martin Knaak wrote: > Richard Rasker wrote: > > > OK, I'll start by reading up on the light vs. heavy symbol > > discussions. Do I understand correctly that heavy symbols basically > > have certain nets with predefined names (e.g. VCC, GND) implicitly > > included, whereas light symbols offer the pins to connect those > > nets oneself? > > Not quite. There seems to be a consensus, that hidden nets are bad > style. I'll throw out the most important reason that hidden nets (e.g., Vcc/GND pins) on symbols is bad: Power and ground connections are a critical part of the circuit design but would not be visible when looking at the schematic! You would have to click a symbol and bring up the attribute editing window to see to which net power and ground are connected. If you print the schematic or view it as a PDF, this important aspect of design is lost. Certainly there are other important attributes that are often hidden, like “footprint”, etc., but footprint is actually less of a concern for the schematic, and more of a concern in other workflow phases (i.e., layout, or preferably a separate future process to separate footprints from the schematic...). Regards, Colin ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcjc2 tessellation
On Mon, 30 May 2011 10:49:54 +0100 Peter Clifton wrote: > On Mon, 2011-05-30 at 09:37 +0200, Gabriel Paubert wrote: > > > > > Think i know now. Polygons can't have edges that cross other > > > > edges. > > > > > > You got it.. PCB doesn't allow self intersecting polygons, so I > > > removed support for rendering them in an attempt to manage the > > > complexity (and hopefully improve speed of) the tessellator. > > > > So, what happens if one directly tinkers with the PCB file with > > an editor or script and creates a self interscting polygon > > by mistake? > > "Bad things" (TM). > > Certainly the polygon computations will give bogus results, because > one of the key underlying assumptions of the polygon algebra routines > is violated. > > If PCB is built with asserts enabled, it will just quit immediately > when loading your file. > > > It's not so far fetched, I sometimes edit coordinates in the > > file to match mechanical design. I can make a mistake or, > > if it is a script (which also happens), it can have a bug. > > Its not ideal, but PCB doesn't report these problems unless asserts > are enabled (which makes PCB slow). We should probably add a > validation pass when loading the board and refuse to display any > damaged polygon. > > That should at least help to pick any problems up with hand (or > script) edited boards sooner rather than later. I have had problems loading layouts that contain graphics imported using pstoedit with its 'pcbfill' output driver (the other 'pcb' output driver does not accurately convert reproduce graphics since it does outlines only). In fact, I have several pcb layouts that I can't open with a debug-build since it immediately triggers an assertion failure. Regards, Colin signature.asc Description: PGP signature ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Fixing the attribute censorship bug
> The attached script not only emits a message, but substitutes > "attribute_conflict" for the attribute in question. Since that's not > normally a legitimate value, it should help the user to detect the > problem. >From my perspective, I don't understand why this is better. 1.7.0 warns about undefined behaviour, and defaults to backwards-compatibility (which makes some sense IMHO). This script deliberately poisons the netlist. In my ideal world (haha) gnetlist would generate errors on attribute conflicts. :-) > gnetlist -m censor_fix.scm (other gnetlist args) For the benefit of those who share your preference for this behaviour: does loading this scm file from a configuration file work? :-) Peter -- Peter Brett Remote Sensing Research Group Surrey Space Centre ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Darter - SPICE based IBIS modelling tool
Oh, yes. We like this! Cheers, Andy. signality.co.uk On 31 May 2011 07:11, Russell Dill wrote: > As edge rates increase, signal intergrity (SI) becomes more and more > important, even for the hobbyist. Unfortunately, the models provided > by semiconductor vendors typically come in only 2 forms, encrypted > HSPICE and IBIS. No open tools exist for handling either. An open > HSPICE decryption utility would only either encourage encryption > changes or take-down notices. > > Enter Darter, a tool for creating SPICE models based on IBIS models. > The basic idea is to create a SPICE subcircuit for each IBIS model > within an IBIS file. Each subcircuit is then wrapped in one of several > different subcircuits depending on component and pin (or signal name). > This gives subcircuit names like (note that spaces in the model name > get converted to underscores): > > DQ_FULL_ODT50_800 > > for bare buffers and: > > MT47H128M16U69A_DQ_FULL_ODT50_800_DQ14 > > for a buffer with parasitics. The buffers can then be connected with > transmission lines for simulating SI problems. > > https://gitorious.org/darter > http://www.gedasymbols.org/user/russell_dill/darter.html > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gnetlist
On 05/30/2011 09:35 PM, John Doty wrote:
On May 31, 2011, at 6:35 AM, John Griessen wrote:
I'd like the first definition
of what gnetlist does be, "Output any data it takes in, in the same format,
with lost spatial position information allowed, but keeping all other data
intact."
I think the reader should preserve *all* of the information in a .sch file.
There are several reasons:
1. Net connectivity depends on spatial information. But one approach doesn't fit all
needs here. Right now, we have a simple minded netlister that reduces the net geometry in
the schematic to a netlist model in which a net is topologically a single point. But
suppose we start putting attributes on net segments ("this segment must carry
10A")? Shouldn't a back end for a layout tool that can handle this be able to see
this, figure it out?
+1 from me. Gate drive sub-circuits in power designs come to mind, as
well as Kelvin connections.
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Re: gEDA-user: Perl
On 05/27/2011 11:54 AM, DJ Delorie wrote: This is more anecdotal than anything else... I'm a Perl fan myself. (shudder) Javascript! ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Two things ... or actually, three
On Tue, May 31, 2011 at 05:09:25AM +0200, Kai-Martin Knaak wrote: > Richard Rasker wrote: > > > OK, I'll start by reading up on the light vs. heavy symbol discussions. > > Do I understand correctly that heavy symbols basically have certain nets > > with predefined names (e.g. VCC, GND) implicitly included, whereas light > > symbols offer the pins to connect those nets oneself? > > Not quite. There seems to be a consensus, that hidden nets are bad style. Here I respectfully disagree, unless or until you can make a single schematic pin correspond to a (potentially long) list of physical pin. To my knowledge this is not the case right now. Of course the pin numbers should not be shown on the schematics: they would use up too much schematics real estate and are not interesting anyway (even relatively simple and cheap FPGA devices like XC3S700A has 88 power pins in the 256 pins BGA package, that's ~35% of the pins): you can't check anything in a BGA package and even on package that can be probed, it is extremely hard to find, say, a bad solder joint since all pins of the same power rail are internally connected together. > At least, I haven't seen anyone advocate net attributes in the default lib. That's very different. More often than not I have to override the net=VCC attribute in the existing library for simple logic devices, so the fact that there is a default can lead to errors (it would be better to have an attribute hidden_pins=list_of_pins that produces an error at netlist generation time if some of these pins have no net=attribute). We no more leave in the world where "the logic power supply is +5v, period ". In some cases it is even the net=GND:whatever that I have to override (microwave GaAs switches often work with a negative power supply, and GND is the positive power rail). Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
