Re: gEDA-user: libgeda build failure
On Dec 27, 2007, at 3:08 AM, [EMAIL PROTECTED] wrote: Hi, all, Under OS X 10.5.1 PPC, I'm getting a build error when the configure script for libgeda is called by the main Makefile: checking for CFPreferencesCopyAppValue... (cached) yes checking for CFLocaleCopyCurrent... (cached) yes checking whether included gettext is requested... no checking for GNU gettext in libc... no checking for GNU gettext in libintl... yes checking whether to use NLS... yes checking where the gettext function comes from... external libintl checking how to link with libintl... -lintl -Wl,-framework - Wl,CoreFoundation ./configure: line 28854: syntax error near unexpected token `0.35.0' ./configure: line 28854: `IT_PROG_INTLTOOL(0.35.0)' I'm building from the latest git. If you're building from git, you need to make sure you have the development package for intltool installed. If just building from source tarballs, you don't. This is a new dependency required for translating the new .desktop files installed. I installed the latest intltool from http://ftp.gnome.org/pub/gnome/sources/intltool/0.37/ and it was not impressed ... -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: libgeda build failure
On Dec 27, 2007, at 4:18 AM, Stuart Brorson wrote: ./configure: line 28854: syntax error near unexpected token `0.35.0' ./configure: line 28854: `IT_PROG_INTLTOOL(0.35.0)' This is happening because the macro IT_PROG_INTLTOOL present in configure.ac hasn't been expanded in your configure file. How did you run the top-level gEDA Makefile? You should do something like: make reconfig make install make reconfig re-runs the autotools on the code. If this doesn't help, you many need to update your autoconf utility. Do autoconf --version and check that your autoconf version is up to date compared to that available from the GNU website. It's autoconf 2.61, which is the latest version. I did the make reconfig make install and it failed in the same location. Interesting, in Makefile.in, found in gaf/libgeda/intl/, a comment starting at line 311 says, # We must not install the libintl.h/libintl.a files if we are on a # system which has the GNU gettext() function in its C library or in a # separate library. # If you want to use the one which comes with this version of the # package, you have to use `configure --with-included-gettext'. So in gaf/libgeda, I did a ./configure --with-included-gettext and that did not have an impression. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: libgeda build failure
On Dec 27, 2007, at 8:12 PM, Peter Clifton wrote: On Thu, 2007-12-27 at 19:49 -0700, Andy Peters wrote: On Dec 27, 2007, at 3:08 AM, [EMAIL PROTECTED] wrote: Hi, all, Under OS X 10.5.1 PPC, I'm getting a build error when the configure script for libgeda is called by the main Makefile: checking for CFPreferencesCopyAppValue... (cached) yes checking for CFLocaleCopyCurrent... (cached) yes checking whether included gettext is requested... no checking for GNU gettext in libc... no checking for GNU gettext in libintl... yes checking whether to use NLS... yes checking where the gettext function comes from... external libintl checking how to link with libintl... -lintl -Wl,-framework - Wl,CoreFoundation ./configure: line 28854: syntax error near unexpected token `0.35.0' ./configure: line 28854: `IT_PROG_INTLTOOL(0.35.0)' I'm building from the latest git. If you're building from git, you need to make sure you have the development package for intltool installed. If just building from source tarballs, you don't. This is a new dependency required for translating the new .desktop files installed. I installed the latest intltool from http://ftp.gnome.org/pub/gnome/sources/intltool/0.37/ and it was not impressed ... Oh dear.. If you haven't done so, try running make reconfig before the start of the build. This is needed if the build infrastructure is changed. Assuming you already did this, or it still doesn't work, can you post the build logs and any error messages from the failure please, so we can try to debug the problem. Specifically, lets work on libgeda manually. What is the output of: cd libgeda ./autogen.sh Here it is: macaroon:libgeda andy$ ./autogen.sh processing . autogen.sh running: autopoint ... Copying file po/Makefile.in.in autogen.sh running: intltoolize ... autogen.sh running: libtoolize ... You should update your `aclocal.m4' by running aclocal. autogen.sh running: aclocal ... configure.ac:82: warning: AC_COMPILE_IFELSE was called before AC_USE_SYSTEM_EXTENSIONS /var/tmp/autoconf/autoconf-14~76/SRC/autoconf/lib/autoconf/ specific.m4:421: AC_USE_SYSTEM_EXTENSIONS is expanded from... /usr/share/aclocal/lock.m4:78: gl_LOCK_EARLY_BODY is expanded from... /usr/share/aclocal/lock.m4:25: gl_LOCK_EARLY is expanded from... /usr/share/aclocal/lock.m4:258: gl_LOCK is expanded from... /usr/share/aclocal/intl.m4:265: gt_INTL_SUBDIR_CORE is expanded from... /usr/share/aclocal/intl.m4:166: AM_INTL_SUBDIR is expanded from... /usr/share/aclocal/gettext.m4:362: AM_GNU_GETTEXT is expanded from... configure.ac:82: the top level configure.ac:82: warning: AC_RUN_IFELSE was called before AC_USE_SYSTEM_EXTENSIONS configure.ac:82: warning: AC_COMPILE_IFELSE was called before AC_AIX /var/tmp/autoconf/autoconf-14~76/SRC/autoconf/lib/autoconf/ specific.m4:455: AC_AIX is expanded from... configure.ac:82: warning: AC_RUN_IFELSE was called before AC_AIX configure.ac:82: warning: AC_COMPILE_IFELSE was called before AC_MINIX /var/tmp/autoconf/autoconf-14~76/SRC/autoconf/lib/autoconf/ specific.m4:474: AC_MINIX is expanded from... configure.ac:82: warning: AC_RUN_IFELSE was called before AC_MINIX autogen.sh running: autoheader ... configure.ac:82: warning: AC_COMPILE_IFELSE was called before AC_USE_SYSTEM_EXTENSIONS /var/tmp/autoconf/autoconf-14~76/SRC/autoconf/lib/autoconf/ specific.m4:421: AC_USE_SYSTEM_EXTENSIONS is expanded from... aclocal.m4:8679: gl_LOCK_EARLY_BODY is expanded from... aclocal.m4:8626: gl_LOCK_EARLY is expanded from... aclocal.m4:8859: gl_LOCK is expanded from... aclocal.m4:1015: gt_INTL_SUBDIR_CORE is expanded from... aclocal.m4:916: AM_INTL_SUBDIR is expanded from... aclocal.m4:402: AM_GNU_GETTEXT is expanded from... configure.ac:82: the top level configure.ac:82: warning: AC_RUN_IFELSE was called before AC_USE_SYSTEM_EXTENSIONS configure.ac:82: warning: AC_COMPILE_IFELSE was called before AC_AIX /var/tmp/autoconf/autoconf-14~76/SRC/autoconf/lib/autoconf/ specific.m4:455: AC_AIX is expanded from... configure.ac:82: warning: AC_RUN_IFELSE was called before AC_AIX configure.ac:82: warning: AC_COMPILE_IFELSE was called before AC_MINIX /var/tmp/autoconf/autoconf-14~76/SRC/autoconf/lib/autoconf/ specific.m4:474: AC_MINIX is expanded from... configure.ac:82: warning: AC_RUN_IFELSE was called before AC_MINIX autogen.sh running: automake ... configure.ac:82: warning: AC_COMPILE_IFELSE was called before AC_USE_SYSTEM_EXTENSIONS /var/tmp/autoconf/autoconf-14~76/SRC/autoconf/lib/autoconf/ specific.m4:421: AC_USE_SYSTEM_EXTENSIONS is expanded from... aclocal.m4:8679: gl_LOCK_EARLY_BODY is expanded from... aclocal.m4:8626: gl_LOCK_EARLY is expanded from... aclocal.m4:8859: gl_LOCK is expanded from... aclocal.m4:1015: gt_INTL_SUBDIR_CORE is expanded from... aclocal.m4:916: AM_INTL_SUBDIR is expanded from... aclocal.m4:402: AM_GNU_GETTEXT is expanded from... configure.ac:82: the top level configure.ac:82: warning: AC_RUN_IFELSE was called
Re: gEDA-user: libgeda build failure
On Dec 27, 2007, at 8:42 PM, Peter Clifton wrote: On Thu, 2007-12-27 at 20:23 -0700, Andy Peters wrote: I did the make reconfig make install and it failed in the same location. Interesting, in Makefile.in, found in gaf/libgeda/intl/, a comment starting at line 311 says, # We must not install the libintl.h/libintl.a files if we are on a # system which has the GNU gettext() function in its C library or in a # separate library. # If you want to use the one which comes with this version of the # package, you have to use `configure --with-included-gettext'. So in gaf/libgeda, I did a ./configure --with-included-gettext and that did not have an impression. I don't expect it would. The intl dir should only be built / installed for systems which need it. Looking over your configure log, it seems that this was detected correctly. My guess is that your aclocal isn't finding intltool.m4 correctly. Can you email me the output aclocal.log file from: cd libgeda aclocal --verbose aclocal.log Attached! -a aclocal.log Description: Binary data ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: could not connect nets gschem/gsch2pcb/pcb
On Dec 20, 2007, at 2:47 PM, Steve Meier wrote: On Thu, 2007-12-20 at 14:44 -0700, Andy Peters wrote: On Dec 20, 2007, at 5:47 AM, Klaus Rudolph wrote: Having multiple netnames should not be a problem and work sometimes. Methinks that having multiple netnames for the same net should ALWAYS trigger a DRC error. -a Well hierarchicaly I use presidence to determine the netname. The netname is set from the top out. So no having multiple netnames for the same net shouldn't always trigger a drc error. Ah, yeah, I forgot hierarchy, even as I'm working on a large hierarchical FPGA design with several instances of a couple of low- level modules. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Parts DB API
On Dec 19, 2007, at 8:34 AM, DJ Delorie wrote: That is true. But why do we need this? Why should pcb know that the attribute value=LM2596 came from a database, or from manual input, script generated? I'm thinking of the case where an attribute is defaulted by some BOM manager because it's the only option that fits. For example, if you pick a manufacturer's part number and a preferred vendor, the vendor part number is defaulted. This is different than picking a vendor part number and letting the manufacturer be defaulted. This is the argument (one with which I agree) for using your own organization-internal part numbers for each component. Some database can then map the internal part number to one or more vendor part numbers for purchasing. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: youngest user?
On Dec 19, 2007, at 10:20 PM, DJ Delorie wrote: New slogan: gEDA: An 8 year old can use it! Does that mean I don't have to finish the tutorial? ;-) It means you found a potential user who hasn't been tainted by exposure to any other EDA tool! -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
On Dec 4, 2007, at 8:23 PM, Steve Meier wrote: What is the deffinition of a heavy symbol? And secondly why put a data base behind one? I have been pondering this from several levels. To me, a heavy symbol (or, in the parlance of other EDA packages, a component) is one that includes footprint information and either a vendor part number or a company-internal one (which gets mapped to a vendor part number for ordering). A heavy symbol may also contain a pointer to a Spice library but I don't use that. Why is this good? Simply put: the schematic becomes the master drawing. From the schematic, one can generate a netlist including package information for layout and a BOM for parts ordering. The former is very important. We've seen examples of different flavors of transistors with different TO-92 pinouts. Things like opamps can have different pinouts when in different packages. So one can avoid all sorts of confusion by placing an AD8138ARZ on my schematic, knowing that it will automatically pull in the expected footprint (SOIC) and populate the BOM with a valid orderable part number. We have added the AD8138ARM to the library because we need the smaller footprint, and this part also has a different internal part number. One level is about how heavy large components have become and the tasks that are used in building a working programed printed circuit board. Take a large fpga that has a large number of io pins that can have many different functions. these are typically broken up into groups other wise called banks. On a bank by bank basis it is possible to sellect the following logic families 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 3.3-V PCI 3.3-V PCI-X mode 1 LVDS LVPECL Differential 1.5-V HSTL Class I and II Differential 1.8-V HSTL Class I and II Differential SSTL-18 Class I and II Differential SSTL-2 Class I and II Within a bank a pair of io pins can be used differentialy or as single ended inputs. At lay out time pin swapping to detangle the netlist becomes very attractive. Which pins can be swapped? It's even worse than that, as (certainly with Xilinx) there are plenty of limitations to pin placement. Some pins are inputs only. You need to make sure you get your differential polarity correct. You need to specify particular clock input pins. Differential inputs on Spartan 3E don't have built-in terminations (but differential I/O does). You need to avoid using the configuration control pins for most general I/O. But this, in my estimation, doesn't have anything to do with the heavy vs light symbol debate. We like to break up FPGA symbols into banks. For example, XC3S250E-FT256 has four banks so our symbol is really five parts, one for configuration connections and core power and ground, and four symbols, one for each bank which include VCCIO connectors for that bank. Pin names are as noted in the Xilinx data sheet. This allows for some reasonable options for pin swapping. The other FPGA school-of-thought involves making a logic symbol (or set of symbols) for each design (which of course includes footprint and part number info) with particular FPGA design pins on the correct location in each symbol. By logical symbol I mean that you have, say, one symbol for CPU interface, another for DDR SDRAM interface, a third for Ethernet PHY, a fourth with config/power, etc. The downside of this is pretty obvious: make a change that requires adding pins and it gets ugly. On a second level, even a resistor has limitations. For a given manufacturor of a given product line there exists only a finite number of resistance values? To support manufacturing I would like to know what are the options for a particular package? Can I expect the package to survive the expected power levels? The obvious solution to this is to have heavy symbols for each and every resistor value, package size and tolerance. Of course your resistor library can grow quite large in a hurry, although creating a new symbol is a simple as copying an older one and changing the relevant fields. On a third level, I would like to tie models and/or code (verilog, vhdl, spice) to a symbol and have the ability to generate simulatable netlists. The problem with having schematics that support simulation (either HDL or Spice) and layout is that there are things on a layout that don't have models (connectors etc) and Spice-specific things don't translate to layout. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter
On Nov 28, 2007, at 1:49 PM, Ben Jackson wrote: On Wed, Nov 28, 2007 at 02:09:22PM -0500, Timothy Normand Miller wrote: We've discovered that the clock generators in the Xilinx FPGA part are lousy for generating video clocks. DCMs have lousy jitter, yes. Indeed. The Spartan 3E claims +/- 100 ps jitter on the DCM's CLK0 (in- phase) output and +/- 150 ps on the CLK90, CLK180 and CLK270 (phase- shifted) outputs. The clock-doubler outputs claim +/- 1% of the clock- in period + 150 ps jitter. When doing integer division, the CLKDV outputs claim +/- 150 ps jitter. When doing non-integral division, the CLKDV output claims +/- 1% of the clock-in period + 200 ps jitter. Then when one reads the footnotes, one learns that these numbers are in addition to any input clock jitter. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA/gaf capabilities
On Nov 7, 2007, at 12:56 PM, Peter Clifton wrote: On Wed, 2007-11-07 at 13:47 -0500, [EMAIL PROTECTED] wrote: Thanks for the replies. I'm sure that geda/gaf will satisfy my needs in terms of coming up with new designs - I'm looking at making small circuit boards for 1-2 kW motor drive applications - nothing in RF or high speed - and I try to keep them to 2 layers so that I can make cheap protos. That being said, the feature comparison checklist is a nice marketing tool. I do have one specific question on capability - I have an existing designs (schematics + layout) in PCAD and PADs formats. Is there a method which will allow me to preserve some of this work? I'm not aware of any, however can you check what the PCAD / PADS file look like when you open in a text editor? If it looks human readable, then send us some examples, and we'll see if we can help. Unfortunately, many of the packages seem to use binary only file-formats which are of course undocumented. Do either package export to any other formats beside their native? (If so, send a list, and it might give us some ideas for possible routes). The PCAD pcb layout tool will let you save a design as either binary (the default) or an ASCII format similar to EDIF. I don't remember if the schematic capture tool can do the same (it's been a few years). -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: QFP fan-out tips
On Oct 6, 2007, at 6:37 AM, Randall Nortman wrote: On Sat, Oct 06, 2007 at 07:21:22AM -0400, Bob Paddock wrote: I route power inwards under the chip, with vias to the power planes and the decoupling cap on the other side. Sometimes doing that adds enough inductance to cause problems, in high frequency boards. What does high frequency mean? I'm in the 50MHz range. It's not the frequency that's important, it's the rise time of the signals. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: database driven component chooser - part II
On Sep 30, 2007, at 6:13 AM, Greg Cunningham wrote: On Sun, 2007-09-30 at 08:12 -0300, Cesar Strauss wrote: DJ Delorie wrote: And another thing. I have no name for my program. If someone have an idea, it is welcome too. gheavy? ;-) part2sym dbsym sympick Bruce Alex Fiona Celeste John Paul George Ringo -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Probably parenthesis mismatch error on OS X
On Sep 27, 2007, at 12:47 PM, John Doty wrote: Build from source is what worked for me. Same here. -a On Sep 27, 2007, at 1:45 PM, Steven Ball wrote: On Sep 27, 2007, at 1:26 PM, John Doty wrote: Have you tried installing guile18, and then reinstalling geda- bundle? I really suspect the Guile compatibility issues are biting you here. There are some hoops the installer needs to jump through depending on which version of Guile you have, and Fink handles this differently from other free software distros. And I'm having no problem with guile18. The binary packages built for OS X depend on guile16 being installed. Maybe I should try building from source and see what happens. -Steve ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ [EMAIL PROTECTED] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: ngspice simulation with microcontrollers
On Sep 26, 2007, at 5:05 PM, Dan McMahill wrote: That can get you closer. You probably don't want to build a complete model for a microcontroller in verilog to the point of being able to run the same firmware image as the real hardware, but you probably could. While it's a pretty simple processor, I've simulated designs with Xilinx Picoblaze processors including the firmware. worked well enough. Anything more complex could get slow and ugly. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA 1.2.0, opamp-1.sym pin numbers?
On Sep 23, 2007, at 7:40 AM, Dan McMahill wrote: Peter Clifton wrote: On Sat, 2007-09-22 at 20:35 +0200, Stefan Salewski wrote: I think that opamp-1.sym will not be compatible with SOT23-5 footprints -- in TI datasheet of OPA656 pin 1 is output for SOT23 package. Maybe opamp-1.sym is compatible with SC70-5 configuration, which I have newer seen. Or opamp-1.sym and opamp-2.sym are only abstract representations of an OpAmp, without any relationship to a concrete footprint? In any case, there seems to be no symbol in gEDA related to an ordinary OpAmp in DIP8 (or SO8) package. This may look very strange for new gEDA/pcb users. There are various heavy symbols, such as lm741-1.sym. It is a well known problem though, the mapping between a light symbol and a real package is not something which is easily solved. which is why I'm in favor of a heavy symbol generator for op-amps like the one I demonstrated for bipolar transistors. You use a small set of symbols and then have a text file which is essentially a spread sheet that for each actual part number (the full vendor part number including package code) you give the mapping from symbol pin to the footprint pin # as well as list the actual footprint. Its pretty simple, you don't have to continually wonder if you have the right footprint or right pinout, and you only have to maintain a small number of graphical symbols. Adding new part number is then a snap. I'm more and more convinced it is the way to go. This is one MAJOR reason to use heavy symbols. I'd rather select a part number from a library, knowing that it always has the correct footprint and vendor part number (or numbers) every time, rather than go through an intermediate step to match ALL parts on the schematic with the proper footprints. That's just too easy to screw up. Sure your library ends up having lots of symbols. That can be handled with a reasonable library directory structure. Creating, say, a new resistor is as easy as copying an existing resistor symbol and changing the part number and value fields. I've been in favor of the heavy symbols including a manufacturer part number, but this is limiting because multiple manufacturers make compatible devices, so how do you choose which manufacturer's number to use? Either you allow multiple vendor part numbers or you create your own part-number system. After using the latter system for a couple of years, I see its advantages. All that's needed is a way to take a BOM generated by the schematic and run it against a database to get vendor part numbers (and prices and whatever else). To further complicate things: for cases like 0805 resistors, where you have a lot of different values, perhaps the simplification is a light/heavy symbol. This can work where the only variation is the resistance value; everything else (footprint, tolerance, etc) stays the same. The part number in the symbol is a base part number. When you place an instance of the RES0805 symbol on the schematic, you modify the value as needed. Then you generate the BOM, and your database lookup uses the base part number and the value to get a manufacturer part number. It's funny how complex this can get ... -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA 1.2.0, opamp-1.sym pin numbers?
On Sep 23, 2007, at 1:57 PM, Dan McMahill wrote: The neat thing with resistors is it is easier to script the whole thing. I haven't done it yet, but before I do my next board I'll probably write a generator to produce all 1% and 5% resistor values in 0201's through 1206's. It will probably take 15 minutes and I'll never have to deal with resistors again. While you're at it, have the script generate a Panasonic part number. That scheme is pretty straightforward; for each size, the only variance in the part number is the four-digit code for the value. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: buzzing board
On Sep 19, 2007, at 11:42 AM, DJ Delorie wrote: What dielectric are those ceramic caps? Y5V, X5R, X7R? X5R (Possibly) Interesting article about the piezo-electric effect in ceramic capacitors: http://www.kemet.com/kemet/web/homepage/kfbk3.nsf/vaFeedbackFAQ/ 242F5F2E69DCEC7485256EDF004CA495 -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: buzzing board
On Sep 19, 2007, at 1:12 PM, DJ Delorie wrote: Most relevant part of that article, Use a part with thicker dielectric, usually corresponding to a higher voltage rating. This reduces the voltage gradient, which reduces piezoelectric noise, if the package size increase is acceptable. What about switching to tantalums? I can fit the EIA 3216 (1206-sized) parts in that slot, allowing a 10uF 16v tant instead of the 22uf 16v (or 10uF 25v) ceramic. Tantalums will work. Just make sure you get surge rated parts. Otherwise, watch out for explosions at power-up. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: buzzing board
On Sep 19, 2007, at 1:34 PM, DJ Delorie wrote: Tantalums will work. Just make sure you get surge rated parts. Hmmm... how would I know? That's not one of the checkboxes on the digikey search engine. Sometimes catalog searches don't tell all. Kemet does have a surge-robust family, the T495 series. Under tantalums (http://www.kemet.com/kemet/web/homepage/ kechome.nsf/weben/products#sur-tan) look for Surge robust parts: http://www.kemet.com/kemet/web/homepage/kechome.nsf/weben/ 5CC0F4F059FD0E92CA2570A500160921/$file/F3102_T495.pdf DigiKey search: http://search.digikey.com/scripts/DkSearch/dksus.dll? lang=ensite=USkeywords=Kemet+Tantalum+T495x=0y=0 Good luck, -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Question regarding 1st LTSpice simulation
On Sep 18, 2007, at 11:40 AM, John Griessen wrote: Andy Peters wrote: One obvious caveat is that the LTC switcher models are all proprietary and as such can't be used with any other spice. Are they hidden or licensed, or just a format that could be translated? They are in a binary format. The program is smart enough to know which models are spice models and which are the proprietary binary models. The format is not published so far all calls to open it have been ignored. There's also some legalese about how the models are proprietary and cannot be reverse-engineered, etc etc. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Question regarding 1st LTSpice simulation
On Sep 17, 2007, at 4:23 PM, gene wrote: Honestly, I haven't even tried either gnucap nor ng-spice but use ltswitchercad quite a bit. I'm up for the change, but how's the learning curve? Anyone care to comment or compare the two? One obvious caveat is that the LTC switcher models are all proprietary and as such can't be used with any other spice. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Question regarding 1st LTSpice simulation
On Sep 18, 2007, at 12:07 PM, al davis wrote: So, for LT-spice What is the organic matter being added to the soil? What are the beneficial insects? And finally: What are the weeds they want to choke out? These are interesting questions. The answer is that LTC's business is selling chips, and by providing a tool that does very fast and very accurate simulations of their parts, they increase the chance that an engineer will choose an LTC part over a competitor's device. After all, switchmode power supplies can be tricky and an accurate simulation gives one a warm- fuzzy feeling that at least the topology and the component selection are correct. Their reason for not opening the format is simple: if one could use LTSpice to simulate a TI or National or whoever's part, then obviously the engineer could choose the competition as easily as choosing the LT part, and THAT is not in LT's interests. Linear Technology supports LTSpice as a means to an end. It would be nice if LT had standard spice models for their switchers that one could use in another program, even if these models were slower than the proprietary models. They DO provide spice models for their amplifiers, comparators and linear regulators, but clearly they think their switchers are the crown jewels. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Question regarding 1st LTSpice simulation
On Sep 16, 2007, at 12:49 PM, Robert Butts wrote:
I'm doing an LTSpice simulation and following Stuart's howto. In the
Running LTSpice with gEDA designs step 5 is:
Create a link from your netlist output.net and a netlist in the
directory
in which SwCADIII lives. Make the netlist suffix .cir. For example:
ln -s
${DESIGN_HOME}/output.net ${WINE_HOME}/.wine/fake_windows/Program
Files/LTC/SwCADIII/MyDesign.cir
My questions are these:
1. Earlier in the howto I was directed to netlist my design and
name it
design.cir. This is the netlist in my design directory and it ends
in .cir
not .net. Should Stuart's howto read ${DESIGN_HOME}/output.cir and
not
output.net?
LTSpice doesn't care whether the netlist is called .net or .cir.
2. Did I miss something and I was supposed to copy the netlist to the
directory in which SwCADIII lives or does the link create a phantom
netlist?
you can open the file from anywhere; it does not have to be in the
SwCAD III directory. However, SwCADIII has a ridiculous hard-coded
library directory structure ...
-a
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Re: gEDA-user: buzzing board
On Sep 12, 2007, at 9:34 PM, DJ Delorie wrote: The PCB for my alarm clock buzzes. 2. What kind of components *can* make that kind of noise? 3. If you know what's causing it, how do I fix it? Once upon a time I was at the local rock venue doing a soundcheck and one of the musicians on stage said, Hey, there's a weird buzz coming from the monitors. I picked up my talkback mic and said, Really? What does it sound like? and then he said, Huh ... it just went away. I put down the talkback and then he said, Hey, it's back. I picked up the talkback, said, Huh! and he said, Now it's gone. I put the talkback down again, and he said, it's bck! The talkback was not muted but it was routed only to the stage monitors, so I couldn't hear the buzz. Turns out that I put the talkback mic on top of a Lexicon MIDI Remote Control box. I soloed the talkback into my headphones, and heard the buzz. I picked up the mic and the buzz went away. Put it back onto the MRC, and the buzz came back. H ... and the buzz was worst when it was right on top of the MRC's LCD. Very weird. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: A4 Printing
On Sep 10, 2007, at 7:10 PM, Greg Cunningham wrote: On Mon, 2007-09-10 at 20:33 -0400, DJ Delorie wrote: However, the pdf barfs. Is there a wrap error in your post, or is $ a construct I'm not familiar with? When using pattern rules (wildcards) in Makefiles, there are some variables you can use to expand to the part of the filenames that match the wildcards. Example: %.pdf : %.ps Makefile ps2pdf $ $@ If we're converting page.ps to page.pdf, some useful variables are as follows: $@ page.pdf (the target) $ page.ps (the first depends-on file) $^ page.ps Makefile (all depends-on files) $* page (the part that matched the '%') Thanks again DJ. Over the last 10 years, I have had 2 or 3 attempts (my only ventures into a bit of serious code...)to climb the Makefile plateau. But, seeing 99.99*% of my work is sys-admin for a regional daily newspaper, I just keep forgetting almost everything I read. Not enough playtime... FWIW, there's a good O'Reilly book about creating and using Makefiles: http://www.oreilly.com/catalog/make3/index.html Don't worry ... it's not as thick as the sendmail bat book. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: alarm clock update
On Sep 9, 2007, at 8:58 AM, Bob Paddock wrote: As for Digikey pricing if you compare it to Mosuer over the last six months, Digikey prices have risen significantly. I've noticed that if Mouser has an identical product (same manufacturer, same part number) or a compatible product, they tend to be a lot cheaper than DigiKey. Of course there are products carried by one that the other doesn't have, so you still might need to use both. But given the option, I use Mouser. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: alarm clock update
On Sep 8, 2007, at 11:28 PM, DJ Delorie wrote: Unfortunately, Digikey put the wrong parts in the PIC24's envolope, so I'm short two CPUs. I'm sure they'll fix that error before I need the other two boards. Has anyone else had problems with Digikey shipping the wrong parts? This is the second time it's happened to me. This has happened to us a few times. We'd get things like capacitors in a power-resistor package and other such blatantly-wrong packing errors. Our purchasing guy has told the factory contact: Take your wireless phone, go out into the warehouse and look in the bin labeled 'foo,' and tell me if there are 'foos' in that bin, or if there are 'bars'. Yup, it's full of 'bars'. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Marketing gEDA - was - Re: Professional PCB help using geda?
On Sep 7, 2007, at 8:06 PM, al davis wrote: On Thursday 06 September 2007, Larry Doolittle wrote: PCB can't do the automated parasitic extraction and signal integrity simulations that high end software suites can. Actually, a first cut, without crosstalk, is fairly easy to do. First, we need a translator, to translate from the PCB format to a simulation language. Then, we need electrical models of the traces, vias, etc. Then, we need to model the drivers and receivers, which are usually specified as IBIS models. I would LOVE to see gEDA incorporate an IBIS simulator! -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Marketing gEDA - was - Re: Professional PCB help using geda?
On Sep 5, 2007, at 6:07 PM, Samuel A. Falvo II wrote: I'm talking about people who offer complaints about inconsistencies between the UI of gschem versus PCB (something that I've since gotten used to, after a VERY long period of acclimation). Invariably we hear the usual rhetoric of people not reading manuals anymore, and that powerful software is never easy to learn, etc. Developers of any sort of software must always keep in mind the Prime Directive of usability: If the user cannot find it, the feature does not exist. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: C++ (was Re: interesting links)
On Aug 30, 2007, at 6:39 PM, Dave McGuire wrote: On Aug 30, 2007, at 9:26 PM, Timothy Normand Miller wrote: I'm no longer obsessed with maximizing performance of the machine. Now, I want to maximize my performance as a programmer. Be very, very careful with that attitude. Back in the 1970s, some blithering idiot came up with the idea that programmer time is more important than processor time. This has given rise to things like Windows, which takes hundreds of megabytes of RAM and multi-GHz processors to do even the very simplest of things. That moron back in the 1970s (whoever it was) should be put up against a wall and shot. #include mooreslaw.h -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB displaying netnames and/or pin numbers (Was: Last code sprint's IRC log and pictures)
On Aug 20, 2007, at 11:07 PM, Bert Timmerman wrote: Hi all, As one can see in the picture (made by Christoph Lechner), there are also netnames and pin numbers shown. This could be a handy feature for pcb when doing manual routing without a netlist (no rat lines). Just my EUR 0.02 ;-) I completely agree (and I've suggested it, too)! -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: First release of uEDA
On Aug 19, 2007, at 3:53 PM, DJ Delorie wrote: uEDA fully embraces the UNIX philosophy that revolves around vi and make for scripted, iterative, non-WYSIWYG flow, You do realize that X and Motif were invented for Unix, long before Linux came around, yes? Well, he IS trying to do PCB layout in a non-WYSIWYG flow, so draw your own conclusions! -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Unwanted compent markings
On Jul 28, 2007, at 7:32 AM, Kai-Martin Knaak wrote: On Fri, 27 Jul 2007 14:50:16 -0400, DJ Delorie wrote: Yeah, but I bet some people want a value on the assembly drawings ;-) Indeed. I tend to make two prints for my prototypes: One with values for initial populating the board. And a second with refdeses to link parts to the schematics when debugging the notorious blunders. I suppose I'm so used to the assembly people working from an assembly drawing (w/ refdes only) and a BOM which lists refdeses and our internal part numbers. A part value, especially on something like SMT ceramic caps, isn't all that helpful. Engineering debug needs the schematic and the assembly drawing. The former tells me what's what and the assembly drawing just tells me where it is. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Unwanted compent markings
On Jul 27, 2007, at 11:25 AM, Philipp Klaus Krause wrote: DJ Delorie schrieb: I just updated my pcb version to 20070208. When I load a design there are descriptions like U1, R1, CONN1, etc near the components now. I don't want these. How can I get rid of them? Um, pcb should have been showing those all along. I don't think you can hide *just* the labels, but if you disable the silkscreen layer those (and other silk) will be hidden. Or you can change *which* label is drawn (refdes, value, description). Value would be fine (0.22µ instead of C1). How do I change it? I suspect that most people would prefer to see a refdes instead of a value on the silkscreen. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Is the Guile 1.8.x dependancy holding back testing?
On Jul 24, 2007, at 2:42 PM, Stuart Brorson wrote: I would *love* to have guile-1.6.x back again. The guile issue is one of the big reasons I haven't spun a CD recently. Guile 1.8 depends upon GNU's bignum package gmp, which isn't normally pre-installed on most common distros. For my CD to successfully install gEDA, it needs to install guile-1.8. To install guile-1.8 I now need to install the bugnum stuff. This is too many dependencies for me to feel comfortable about bundling onto a CD with a fairly dumb installer. The maintainer for the bignum stuff (gmp) is openly hostile to Mac OS X and refuses to deal with the platform. So anything that works around that lossage would be nice. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Significance of names for Panasonic TS series cap footprints ?
On Jul 24, 2007, at 1:59 PM, armdeveloper wrote: I am using a Panasonic ECO-S1HP223EA capacitor in a design. (TS series, 22000uF, 50V, 35mm, 2 prongs, Digikey part number P6946-ND.) I see capacitor footprint names like CAPPR-1000P-3000D-2500L-200d__Panasonic_UP-TS_Series in the 3rd party footprint libraries. What is the significance of the numbers in that name ? P = distance between pins D = diameter of the device package L = height of the thing d = pin diameter -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Can't route
On Jul 15, 2007, at 9:01 AM, Stephen Williams wrote: DJ Delorie wrote: In theory, via-in-pad lets you bring an extra row out on the top layer. It might mean the difference between 12 and 14 layers. Also, if you avoid masking the bottom side of the via, you suddenly have scope access to every pad of the BGA, which I've found to be amazingly useful in my day-job work. (No I didn't make those boards, and no they were not done with PCB.) Bringing all balls of an FPGA out to vias is very useful for those last-minute green-wire ECOs. One problem is that many tools will flag a single-node net as a DRC error. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Can't route
On Jul 14, 2007, at 11:48 AM, Steve Meier wrote: Hmmm, This is an area that writting some code could be very usefull. How about a limited auto router that takes the bga io traces out just past the nearest edge? A fanout command, like what DXP and others have, is VERY useful. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Component selector dialog
On Jul 9, 2007, at 11:34 AM, Matthew Wilkins wrote: OK - place the selected component, remove dialog (permanently) Apply - place the selected component, leave dialog up. Cancel - revert to previous mode, remove dialog (permanently) This makes sense, but the 'apply' button seems redundant. As soon as you select a component from the list, it should be available for placement, with no button required. Seems to me that if you're placing symbols, you need two buttons: a) Place -- lets you place the selected symbol but keeps the dialog open. b) Done -- dismisses the dialog. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: segfault in latest gschem snapshot 1.0.1-20070626
On OS X 10.4.10, Intel, I get a segfault when attempting to load a previously-created schematic file (one made with the old fink snapshot). Here is the gdb session: dizbuster:~/Devel/remote/pcb andy$ gdb GNU gdb 6.3.50-20050815 (Apple version gdb-573) (Fri Oct 20 15:50:43 GMT 2006) Copyright 2004 Free Software Foundation, Inc. GDB is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. Type show copying to see the conditions. There is absolutely no warranty for GDB. Type show warranty for details. This GDB was configured as i386-apple-darwin. (gdb) file ~/geda/bin/gsch gsch2pcbgschem gschem.log gschemdoc gschlas gschupdate (gdb) file ~/geda/bin/gschem Reading symbols for shared libraries .. done Reading symbols from /Users/andy/geda/bin/gschem...done. (gdb) run Starting program: /Users/andy/geda/bin/gschem Reading symbols for shared libraries ..+++ +. ...+++...++ done gEDA/gschem version 1.0.1-20070626 gEDA/gschem comes with ABSOLUTELY NO WARRANTY; see COPYING for more details. This is free software, and you are welcome to redistribute it under certain conditions; please see the COPYING file for more details. Reading symbols for shared libraries . done Reading symbols for shared libraries . done Loading schematic [/Users/andy/Devel/remote/pcb/untitled_1.sch] Loading schematic [/Users/andy/Devel/remote/pcb/analog.sch] Program received signal EXC_BAD_ACCESS, Could not access memory. Reason: KERN_INVALID_ADDRESS at address: 0xa1b1c1d3 0x013887a2 in g_type_check_instance_cast (type_instance=0xa1b1c1d3, iface_type=3 8870080) at gtype.c:3143 3143 if (type_instance-g_class) (gdb) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: segfault in latest gschem snapshot 1.0.1-20070626
On Jul 4, 2007, at 12:05 PM, Peter TB Brett wrote: On Wednesday 04 July 2007 20:00:44 Andy Peters wrote: On OS X 10.4.10, Intel, I get a segfault when attempting to load a previously-created schematic file (one made with the old fink snapshot). Here is the gdb session: Hi there, A backtrace would be useful. ;) I'd love to provide one ... if I knew how! I'm a gdb dummy. I notice that it also crashes with a segfault if I create a new schematic and try to save it. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: segfault in latest gschem snapshot 1.0.1-20070626
On Jul 4, 2007, at 12:05 PM, Peter TB Brett wrote: On Wednesday 04 July 2007 20:00:44 Andy Peters wrote: On OS X 10.4.10, Intel, I get a segfault when attempting to load a previously-created schematic file (one made with the old fink snapshot). Here is the gdb session: Hi there, A backtrace would be useful. ;) Perhaps the following gdb disassemble output is helpful? 0x0138890c g_type_check_instance_cast+390:cmpl $0x8,28(%edx,% eax,4) 0x01388911 g_type_check_instance_cast+395:je 0x1388966 g_type_check_instance_cast+480 0x01388913 g_type_check_instance_cast+397:xor%esi,%esi 0x01388915 g_type_check_instance_cast+399:mov-32(%ebp),%eax 0x01388918 g_type_check_instance_cast+402:mov%eax,(%esp) 0x0138891b g_type_check_instance_cast+405:call 0x139c38e dyld_stub_g_static_rw_lock_reader_unlock 0x01388920 g_type_check_instance_cast+410:test %esi,%esi 0x01388922 g_type_check_instance_cast+412:jne0x138885b g_type_check_instance_cast+213 0x01388928 g_type_check_instance_cast+418:mov8(%ebp),%edx 0x0138892b g_type_check_instance_cast+421:mov(%edx),%edx 0x0138892d g_type_check_instance_cast+423:mov%edx,-36(%ebp) 0x01388930 g_type_check_instance_cast+426:jmp0x1388821 g_type_check_instance_cast+155 0x01388935 g_type_check_instance_cast+431:mov12(%ebp),%eax 0x01388938 g_type_check_instance_cast+434:call 0x1387574 type_descriptive_name_I 0x0138893d g_type_check_instance_cast+439:mov%eax,12(%esp) 0x01388941 g_type_check_instance_cast+443:lea67176(%ebx),%eax 0x01388947 g_type_check_instance_cast+449:mov%eax,8(%esp) 0x0138894b g_type_check_instance_cast+453:movl $0x10,4(%esp) 0x01388953 g_type_check_instance_cast+461:lea47244(%ebx),%eax 0x01388959 g_type_check_instance_cast+467:mov%eax,(%esp) 0x0138895c g_type_check_instance_cast+470:call 0x139c073 dyld_stub_g_log 0x01388961 g_type_check_instance_cast+475:jmp0x138885b g_type_check_instance_cast+213 0x01388966 g_type_check_instance_cast+480:movzwl 6(%edi),%eax 0x0138896a g_type_check_instance_cast+484:test $0x1ff0,%ax 0x0138896e g_type_check_instance_cast+488:je 0x1388913 g_type_check_instance_cast+397 0x01388970 g_type_check_instance_cast+490:mov24(%edi),%esi 0x01388973 g_type_check_instance_cast+493:sub$0xc,%esi 0x01388976 g_type_check_instance_cast+496:shr$0x4,%ax 0x0138897a g_type_check_instance_cast+500:mov%eax,%ecx 0x0138897c g_type_check_instance_cast+502:and$0x1ff,%ecx 0x01388982 g_type_check_instance_cast+508:mov28(%edx),%edi 0x01388985 g_type_check_instance_cast+511:jmp0x138898f g_type_check_instance_cast+521 0x01388987 g_type_check_instance_cast+513:sub%edx,%ecx 0x01388989 g_type_check_instance_cast+515:mov%eax,%esi 0x0138898b g_type_check_instance_cast+517:test %ecx,%ecx 0x0138898d g_type_check_instance_cast+519:je 0x1388913 g_type_check_instance_cast+397 0x0138898f g_type_check_instance_cast+521:lea1(%ecx),%edx 0x01388992 g_type_check_instance_cast+524:shr%edx 0x01388994 g_type_check_instance_cast+526:lea(%edx,%edx,2),% eax 0x01388997 g_type_check_instance_cast+529:lea(%esi,%eax,4),% eax 0x0138899a g_type_check_instance_cast+532:cmp(%eax),%edi 0x0138899c g_type_check_instance_cast+534:je 0x13889a5 g_type_check_instance_cast+543 0x0138899e g_type_check_instance_cast+536:ja 0x1388987 g_type_check_instance_cast+513 0x013889a0 g_type_check_instance_cast+538:lea-1(%edx),%ecx 0x013889a3 g_type_check_instance_cast+541:jmp0x138898b g_type_check_instance_cast+517 0x013889a5 g_type_check_instance_cast+543:mov$0x1,%esi 0x013889aa g_type_check_instance_cast+548:jmp0x1388915 g_type_check_instance_cast+399 End of assembler dump. (gdb) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: segfault in latest gschem snapshot 1.0.1-20070626
On Jul 4, 2007, at 12:37 PM, Peter TB Brett wrote: On Wednesday 04 July 2007 20:30:47 Andy Peters wrote: On Jul 4, 2007, at 12:05 PM, Peter TB Brett wrote: On Wednesday 04 July 2007 20:00:44 Andy Peters wrote: On OS X 10.4.10, Intel, I get a segfault when attempting to load a previously-created schematic file (one made with the old fink snapshot). Here is the gdb session: Hi there, A backtrace would be useful. ;) I'd love to provide one ... if I knew how! I'm a gdb dummy. I notice that it also crashes with a segfault if I create a new schematic and try to save it. That's not good. In gdb, wait until it crashes and then type backtrace. If you could make a bug report with all this information (platform, version, steps to reproduce, and backtrace) that would be great. Also, please provide (attached to the bug report, 'cos they'll be huge) the following: - config.log for libgeda and gschem - output of make -s clean install for libgeda and gschem OK, I've submitted a bug report. It's request #1748079. I've attached the files that Peter has requested. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA/gaf stable version 1.0.1-20070626 released!
On Jun 26, 2007, at 10:01 PM, Ales Hvezda wrote: Hi, I am pleased to announce the first ever stable release of gEDA/gaf: 1.0.1-20070626. The focus of this release was bug fixing. This is also the first release created using git. Many thanks to everybody involved. You can find this release at: http://geda.seul.org/devel/1.0/1.0.1-20070626 After much futzing with dependencies, I have successfully built this release from source on my MacBook Pro running OS X 10.4.10! I was stuck on the gtk+ stuff. I'd followed the instructions in http://www.macdevcenter.com/pub/a/mac/2007/06/22/graphical-tool-kits- for-apples-os-x-gtk2.html, and that port is broken in ways I don't understand (and it also installed it in /opt/gtk, rather than in /usr/ local). So started from the GTK+ website (http://www.gtklib.org/ download) and grabbed the 2.10.13 sources. The GTK folks were kind enough to include a list of the dependencies, which I grabbed and built (and had to get their dependencies) and that all went smoothly. I used the libpng and libjpeg packages from http:// ethan.tira-thompson.com/Mac%20OS%20X%20Ports.html rather than building those from source. I used the guile 1.8.1 from http:// rudix.org/ and that worked. So now to build pcb and gerbv. That's project for tomorrow night (tonight). -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA/gaf stable version 1.0.1-20070626 released!
On Jun 27, 2007, at 3:45 AM, Andy Peters wrote: So now to build pcb and gerbv. That's project for tomorrow night (tonight). Oh, that was easy ... they built right out of the box from the latest snapshots. Anyways ... since the geda/gaf stuff, by default, gets installed in my home directory, is there a recommended way to install it in /usr/ local in the usual way? I suppose I could symlink everything, but that seems wrong. I could have changed the install directory at build/configure time, but that requires building as root. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA/gaf stable version 1.0.1-20070626 released!
On Jun 27, 2007, at 4:26 AM, Stuart Brorson wrote: Anyways ... since the geda/gaf stuff, by default, gets installed in my home directory, is there a recommended way to install it in /usr/ local in the usual way? What I usually do is edit the top level Makefile, and change this line: prefix?=$(HOME)/geda to prefix?=/usr/local/geda Then I do the rest of the install as usual. I could have changed the install directory at build/configure time, but that requires building as root. Well, if you want to put anything into a system directory, you need to be root. I was using the top-level Makefile, which builds everything and then installs in one shot. I know I have to be root to install into /usr/ local! I'll do as Peter suggests and build everything individually. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Thoughts using gschem
On Jun 26, 2007, at 9:20 AM, John Griessen wrote: John Doty wrote: what *I'd* really like is explicit support for the project symbol library concept. Specify it in gafrc. When you place a symbol from the regular library, a copy should be automagically placed in the project library. Symbols in the project library should have priority without duplicate symbol warnings. The project library should be first in the component dialog's list. A project symbol library concept sounds logically attractive to many, and me too. That's a common practice in the $$$ EDA world. A function to update project symbols from global library is useful, too. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Mac OS X 10.4: GNU MP required by guile-1.8.1 ..
On Jun 26, 2007, at 1:53 AM, Steven Michalske wrote: Use fink to install guile and gmp, save yourself all the work that others have done for you. Use fink to install all your dependencies. The developers and maintainers of fink do a lot of patching. I also know an apple co worker that patched up GMP a couple of times before and trust me GMP won't fall out of graces at apple, we do to much scientific computing, oddly enough the patches seem pretty darned small to make it work on macintosh intel platform, I don't know why they don't fix the 4.x branch for them. Basically the assembly for ELF vs darwin have some differences, from reading the fink info files. I did some googling, looking for solutions to this, and apparently the GMP maintainer is openly hostile towards anything Macintosh. On GMP support listservs, he comes off as, pardon my New Jersey, a big dick. The Rudix packages I mentioned yesterday have a version of both guile and GMP, which seems to work. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: latest git make failure
I think I've got my dependencies sorted out. But when I do a make config, it bombs with the following: = dizbuster:~/Devel/gaf andy$ make config ( cd libgeda; ./configure --prefix=/usr/local/geda ) Configuring libgeda version 20070526 checking for a BSD-compatible install... /usr/bin/install -c checking whether build environment is sane... yes checking for gawk... no checking for mawk... no checking for nawk... no ... ... checking for X... libraries /usr/X11R6/lib, headers checking for gethostbyname... yes checking for connect... yes checking for remove... yes checking for shmat... yes checking for IceConnectionNumber in -lICE... yes checking for pkg-config... /usr/local/bin/pkg-config ./configure: line 21658: syntax error near unexpected token `GTK24,' ./configure: line 21658: `PKG_CHECK_MODULES(GTK24, gtk+-2.0 = 2.4.0, GTK24=yes, no_GTK24=yes)' make: *** [libgeda_config] Error 2 = I set up an FC5 environment in Parallels, gitted (got?) the gaf stuff, and then did a make config in Linux, and it failed with the same error. Any ideas? -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Mac OS X 10.4: GNU MP required by guile-1.8.1 ..
Hi all, I'm trying to build the latest gEDA code from the git repository on my Intel OS X box, and I don't have guile-1.8 installed. So I downloaded the sources for guile-1.8.1 and did the usual ./configure, which failed because it could not find GNU MP. So I grabbed the sources for GMP from GNU, did the ./configure, which succeeded, then did a make, which also succeeded, then finally did the recommended make check, which failed. Further checking on the GMP page (http://gmplib.org) shows a Status from 04 May 2006: GMP does not build on MacInteltosh machines. No fix planned for GMP 4.x. Oh, great. So I can't build guile because I can't trust GMP. So nobody uses guile on Intel Macs? Is there a workaround?? -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Mac OS X 10.4: GNU MP required by guile-1.8.1 ..
On Jun 25, 2007, at 1:46 PM, Andy Peters wrote: Hi all, I'm trying to build the latest gEDA code from the git repository on my Intel OS X box, and I don't have guile-1.8 installed. So I downloaded the sources for guile-1.8.1 and did the usual ./configure, which failed because it could not find GNU MP. So I grabbed the sources for GMP from GNU, did the ./configure, which succeeded, then did a make, which also succeeded, then finally did the recommended make check, which failed. Further checking on the GMP page (http://gmplib.org) shows a Status from 04 May 2006: GMP does not build on MacInteltosh machines. No fix planned for GMP 4.x. Oh, great. So I can't build guile because I can't trust GMP. So nobody uses guile on Intel Macs? Is there a workaround?? reply to myself ... Turns out that the people at http://rudix.org have a package of Unix ports, one of which is gmp, and other is guile. I installed both. I guess I'll see if it works! I'm now following the instructions from http://www.macdevcenter.com/ pub/a/mac/2007/06/22/graphical-tool-kits-for-apples-os-x-gtk2.html as to how to build gtk2+ under OS X. Gettin' there ... -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How to divide large symbols in smaller units?
On Jun 20, 2007, at 4:29 PM, Ben Jackson wrote: If you allow the Quartus II tools to do their talkback feature (sends design summaries to Altera) then you get free access to SignalTap (equiv of Chipscope, which you cannot get for free). This is huge, imo. I didn't know that (been a couple of years since I did an Altera design). That IS huge. All Xilinx parts want a 2.5V VCCAUX. So you're going to need VCCIO, VCCINT and VCCAUX for any Xilinx part, and if VCCIO is not 2.5 (eg 3.3V in my project) then you need 3 voltages. The Altera parts have a single core voltage. The PLLs need an analog supply, but it's the same voltage as the core and you can make it with some caps and a bead. Xilinx got beat over the head about that. Unlike the earlier Spartan 3 and 3E parts, the 3A and 3AN parts can use a 3.3V VCCAUX. They still use a 1.2V core so you need at least two supplies. The killer feature of the 3AN parts, of course, is the internal configuration EEPROM. Lattice was there first but it's good that Xilinx is finally addressing the concerns of potential customers who don't like their IP living in an easily-cloned memory. Hopefully, they'll actually ship the smallest parts sometime this year. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: speaker source
On May 21, 2007, at 11:48 AM, DJ Delorie wrote: The real speakers are Radio Shack Minimus 7's (dual driver). Those little speakers rock. Many a recording studio had 'em on the meter bridge. Natch, the Shack didn't know what to do with a Good Thing and now they're history. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: theremin
On Apr 23, 2007, at 8:41 PM, Steve Meier wrote: How does a Theremin differ from a pickup on an electric guitar? A theremin doesn't use metal strings to modulate a magnetic field! -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Multiple open pages in gschem
On Apr 2, 2007, at 8:26 PM, Ales Hvezda wrote: [snip] There is yet another page-navigation metaphor available to us.. the tabbed notebook, but to do this properly (as I discovered over the summer), requires major data-structure changes. H... Here's something I hacked up a few nights ago: http://geda.seul.org/misc/gschem-tabs.png I've worked out all the details yet (read: hardly fully functional), but the implementation looks fairly straightforward. The question is, are the tabs really that useful since they do sorta clutter things up. Tabs are VERY cool. [Commercial EDA tool I use every day] uses them and they're quite handy. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Looking for a project
On Mar 31, 2007, at 5:15 AM, Bob Paddock wrote: On Friday 30 March 2007 21:32, Randall Nortman wrote: And don't forget automatic weekday/weekend adjustments. http://www.thingsyouneverknew.com/website/store/product_detail.asp? UID=2007020820322012item%5Fno=80153keyword=F1JScat% 5Fkeyword=F1JSsearch%5Fpage%5Fno=page% 5Fno=ltype=featWT.svl=FeaturedItem1WT.ac=FeaturedItem1 That clock advances one *day* at a time. A Sun Dial has more resolution. It is the antithesis of the Time-Nuts clock that keep time in sub parts per trillion. http://www.leapsecond.com/time-nuts.htm This reminds me of an old joke: Kirk: Mr. Spock, what time is it? Spock: It is precisely 11:57:02.0123 AM. McCoy: It's NOON, Spock! -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Looking for a project
On Mar 31, 2007, at 10:29 AM, al davis wrote: Once we have this, we have a schematic program that can draw as well as Labview can, we are working on interprocess communication anyway, we are working on waveform analysis tools anyway, we have a simulator that will soon have real behavioral modeling. We would need some interface software for your board. Then we have a free/open-source alternative to Labview! Give me drivers for my existing NI hardware, and you've got a deal! -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus Verilog with Xilinx simprims...
On Mar 17, 2007, at 7:56 PM, CSB wrote: Wow, thanks for the quick responses ! Does iverilog support SDF backannotation? The SDF has the delay information. Ah ! Now you mention it, I remember removing a $sdf_annotate line from the generated verilog file. It was causing an error with vvp, so I just removed the offending line and quickly forgot about it... The error is: $sdf_annotate: This task is not defined by any modules. I just found a topic about iSDF in this mailing list; I will see what I can do with that. Ah! Now that you mention it, I remember running into $sdf_annotate issues with ModelSim, too, and the problem was how the Xilinx tools generated the Verilog timing sim source. The trick was to delete the $sdf_annotate line in the Verilog source, and then tell ModelSim to use the correct SDF through the GUI (there's also a command-line switch for it). Then it all worked. The Xilinx WebCase I opened about this was handled in the usual Xilinx manner (we'll fix it in a later revision of the tools). Now that I'm back on the VHDL side of the fence, I haven't paid attention to this. Any specific reason why you're running a post-fit simulation? The RTL simulation tells you if your logic is functionally correct, and the static timing analyzer (using your timing constraints) tells you if you've met timing. If both are good, there's no need to run a post-fit simulation. Well, that's where I'm most confused. I followed some instructions that explained how to use TestBencher (part of ISE). Is that what you are referring to? What I saw of it didn't impress me much... For my design, I didn't specify any timing constraints since I'm not concerned so much about speed as correct operation. Also, the amount of specify-able stuff was overwhelming, so I decided to skip that part 8~) The simplest timing constraint is simply clock frequency. That covers 99% of most designs. The other basic constraints deal with input and output delays through the I/O pins; basically, you specify what you need the input set-up and hold to be so you can correctly capture incoming synchronous signals, and you can specify what you'd like the maximum clock-to-out time based on an external synchronous device's requirements. Look for OFFSET IN and OFFSET OUT. If you're doing an asynchronous design, then you're on your own! Current CPLD and FPGA methodologies don't lend themselves well to async design. My reasoning was that I would run a post-fit simulation, and see if there were any glitches, or unusual operation. Mostly, I was thinking about timing hazards. But your comment makes me ask: does the fitted design guarantee a glitch-free operation ? (the only remaining issue would be speed, hence the timing constraints) I should also add that I'm fairly new to digital design, so I might be missing the point entirely. Certainly the fitted design will have glitches, as delays through various paths will be different. The point of synchronous design is that you can ignore those glitches; all you care about is if the inputs to all of your registers are settled by the setup time before the clock edge. And for each clock, that is what the static timing analyzer tells you -- the length of all paths through all registers. As long as the prop delay from register A through logic to the D input of register B is less than the clock period, you win. The timing analyzer accounts for register clock-to-out delay and register input setup and hold. If your design is purely combinatorial, then of course you will have glitches, and remember that a post-fit timing simulation will show you these glitches for the particular routing the tools just used, which may change for each place-and-route run as you tweak the design. The delays are worst-case (high temperature, low supply voltage, wrong phase of the moon), which means that your design will probably be better (path delays not as long). How much Better is not defined, and anyways you should never rely on datasheet typical values. One final comment: Rather than staring at a screen full of logic traces looking for set-up and hold failures, read up about Verilog's $setup and $hold and other timing-check functions that you can use in your test bench. Computers are good at this sort of tedious checking! -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: File corrupted after segmentation fault in pcb
On Mar 18, 2007, at 8:06 PM, Igor2 wrote: On Sun, 18 Mar 2007, Mikael W. Bertelsen wrote: If I take a look at the bright side, this incident did convinced me to finish my backup script which takes an hourly snapshot. Backup is not so bad after all. Why don't you use some sort of version control instead? :) What if the crash occurred before he was ready to commit a change? -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus Verilog with Xilinx simprims...
On Mar 17, 2007, at 3:15 PM, CSB wrote: Hi all, I am trying to use Iverilog along with xilinx's SIMPRIMS. Well, I managed, but I am getting strange results with simulations. I'll try to explain how I'm doing this (I'm new to CPLDs, Verilog and Icarus...) First, I generate the post-fit verilog module from Xilinx ISE project navigator. This is the .v file containing all the nets and gates, for example X_AND2, etc... If I'm correct, those are defined in the *.v files of the XILINX/verilog/src/simprims/ directory, one file for each module. They all contain timing information, which is what I'm after. So, I add -y%XILINX%/verilog/src/simprims/ to my iverilog command, and it generates no error. Then, I run vvp, and generate a VCD from my testbench. So far, so good. I open the VCD, but it seems like the timing information hasn't been simulated. For example, there is no delay between a clock event and a counter update, etc. The levels are all OK, states are the same as the pre-synthesis simulation, so I really have no clue of what's wrong. One thing I've noticed is that the SIMPRIMS modules all have a `timescale directive, the glbl.v file has a different one, and my testbench is again different... could it be that some timing gets rounded off ? Thanks for any info, Christian Does iverilog support SDF backannotation? The SDF has the delay information. Any specific reason why you're running a post-fit simulation? The RTL simulation tells you if your logic is functionally correct, and the static timing analyzer (using your timing constraints) tells you if you've met timing. If both are good, there's no need to run a post-fit simulation. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Flame about XML (was: Some footprints I tried to create)
On Mar 14, 2007, at 8:03 PM, Michael Sokolov wrote: Steve Meier [EMAIL PROTECTED] wrote: I really am interested in why or why not going with XML? How would I use XML with punched cards or paper tape? Why would you use punched cards or paper tape? So a few more details would be nice. OK, here are a few more details about me for you to mull over. I have been called things like Neo-Amish or Techno-Luddite. I am fundamentally and totally against all forms of modern technology. (snip) I fully and totally embrace the computing philosophy and world view of the 1970s that has produced my OS of choice. Punk rocker Mike Watt (formerly of the Minutemen (no, not those idiots patrolling the Arizona/Mexico border)) once said, kids today should defend themselves against the 70s. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Some footprints I tried to create
On Mar 14, 2007, at 2:26 PM, Steve Meier wrote: The only tool ever needed is a hammer2LBs Claw/hammer From a previous job, I have a hammeremacs/hammer To emacs, everything looks like a nail. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: Flame about XML
On Mar 14, 2007, at 3:07 PM, Levente wrote: I am totaly agree with Michael's view of the world. I'd add my favourite phrase on this topic: some time ago, two 8bit MCUs @1MHz were enough to set a satellite into its orbit. Nowdays, a 3GHz CPU is not enough to load an office suit. Something went wrong. Yeah, would you want to do PCB layout on a pair of 8-bit MCUs running at 1 MHz? I didn't think so. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: How to program PAL/GAL?
On Mar 14, 2007, at 4:04 PM, Dave McGuire wrote: On Mar 14, 2007, at 6:55 PM, John Griessen wrote: A GAL programmer isn't difficult at all. High-end, currently supported professional programmers (big Data I/O units come to mind...I recently replaced my 2900 with a UniSite) are easy to come by on eBay these days Does a unisite work with windows? Generic serial port? same question for 2900... It's a standalone device. Well, aside from a terminal. :) That's the main reason I love these Data I/O UniFamily programmers (UniSite, 2900, 3900, etc). Also, no PC-proprietary parallel ports...100% standard RS232 serial I/O. You could run this thing from a PDP-11 if you wanted to. Windows is persona non grata here, and I'm certainly not going to depend on it for something critical to my work like controlling a device programmer. You just connect an ASCII ANSI terminal (I use a VT420) or a computer running a terminal emulator and interact with it directly. The user interface is very good, fast, and easy to use. If you really want to, it does have a mode that you can set which makes it communicate using a remote control protocol over the serial port, and Data I/O has software for Windows which can control the unit via that protocol. The 2900 has a floppy drive from which it boots and loads programming algorithms when you select a device. The later models, including the UniSite, optionally have a hard drive which stores all of that. My recently-acquired UniSite has a hard drive and two floppy drives. They all read and write FAT-formatted floppies. I really can't recommend them highly enough. I've used a bunch of programming systems, and these are, by far, the best I've ever seen in every regard. We had a 2900 at my last job. I hadn't seen one since my first job out of college, where I used one to program Altera MAX7192 parts. The magic adapter cost like $500 (in 1992 dollars). The stupid floppy disk on the thing kept failing for no reason, and Data I/O charged boo-coo bucks to fix it. Anyways, the 2900 at the last job. It sat on a work table, turned off and collecting dust, for the entire four years of my tenure there. When the New Corporate Overlords decided to close our office, it was one of the things I packed up and sent to the California office, where I'm sure it's sitting in a corner, collecting dust. I hope I never see one of those fscking things again. Gimme a JTAG dongle and in-system-programmable parts any day over UV- erasable ancient crap. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: Flame about XML
On Mar 14, 2007, at 4:55 PM, Dave McGuire wrote: On Mar 14, 2007, at 7:51 PM, Andy Peters wrote: I am totaly agree with Michael's view of the world. I'd add my favourite phrase on this topic: some time ago, two 8bit MCUs @1MHz were enough to set a satellite into its orbit. Nowdays, a 3GHz CPU is not enough to load an office suit. Something went wrong. Yeah, would you want to do PCB layout on a pair of 8-bit MCUs running at 1 MHz? I didn't think so. You know...quite a few companies did PCB layout on computers of similar clock speeds in the early 1970s. It can certainly be done, and assuming that it'd be painful to do is just that...an assumption. Seriously. There is some grand assumption that just because the capabilities we have now are good that the capabilities we had twenty years ago sucked. That is not always the case. I have a Sun SparcStation 10 at home. It sits, unused. Every once in a while, I talk about it, and I say, You know, I used to do Real Work on that machine. I used to do Real Work on Apollo workstations (before HP bought 'em and dissolved 'em), running Mentor Graphics (which shipped on cartridge tapes). It was a Big Deal upgrading from the 68030 processor to the 68040, and the upgrade was Not Cheap. The company I used to work for (the one with the unused Data I/O 2900) got its start doing PCB CAD machines based on 68000 processors and custom graphics boards, all on VME backplanes. (The guys who founded the company told me that they ate their own dog food, in a very real way.) I got the chance to fire one up, and it worked, but the PC on my desk running PCAD ate it for breakfast. So, yeah, we used to do Real Work with these old hunks-o-junk (... and we were happy to have the tools!), but the sad fact is that the $500 Mac mini sitting next to my TV set runs circles around all of them, and part of being a Smart Engineer is choosing the right tool for the job. Sticking with archaic hardware because of some romantic notion about computing purity strikes me as fucking stupid, pardon my New Jersey. Of course, regarding the topic of XML, I'm firmly on the side of those who say, Ixnay on the XML-ay. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: How to program PAL/GAL?
On Mar 14, 2007, at 5:07 PM, Dave McGuire wrote: On Mar 14, 2007, at 8:01 PM, Andy Peters wrote: We had a 2900 at my last job. I hadn't seen one since my first job out of college, where I used one to program Altera MAX7192 parts. The magic adapter cost like $500 (in 1992 dollars). The stupid floppy disk on the thing kept failing for no reason, and Data I/O charged boo-coo bucks to fix it. That's why I maintain my own equipment. My 2900 had a dead floppy drive when I bought it. I replaced it with one from the closet and it has worked great ever since. At the time, I worked for a Big Defense Contractor (hey, I was young and stupid), and the thing was under a repair contract. If it broke, a call was made and it got fixed. Anyways, the 2900 at the last job. It sat on a work table, turned off and collecting dust, for the entire four years of my tenure there. When the New Corporate Overlords decided to close our office, it was one of the things I packed up and sent to the California office, where I'm sure it's sitting in a corner, collecting dust. I hope I never see one of those fscking things again. ...because it gave you so much trouble, sitting there collecting dust. ;) I *use* mine several times per week, have for years, and it is 100% perfect...Every single time. Well, once we migrated to ISP devices, its reason for living went away. It may have even still worked, and we had tubes of 27C256 and 27C512 EPROMs laying around, but we didn't need it. Gimme a JTAG dongle and in-system-programmable parts any day over UV-erasable ancient crap. So, in your world Data I/O 2900 somehow implies UV-erasable and ancient? You are making grandiose negative statements about something that you clearly don't know a whole lot about. (and I'm not trying to sound like a prick here...just being honest) Honestly, yes, it does imply ancient to me. I do know that Data I/O still sells programming tools, and I know that you can program a lot of modern devices on a 2900, and I also know that if you're doing huge production runs, you'd have things programmed (even ISP devices) before stuffing on some big Data I/O rig that does a tray-load at a time. But for prototyping and small-to-moderate production runs, given the choice between a JTAG dongle and a Data I/O that occupies a whole table, we'd rather have the table space. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hi.... first post
On Mar 13, 2007, at 9:20 AM, C P Tarun wrote: geda and pcb don't care if the pinnumbers are numbers or strings. As long as they are the same. From a preference point of view I like the pin numbers to match the component data sheet. This is the part I too would have thought was natural. I would have thought that B, C, and E were more sensible pin numbers in the symbols than 1, 2, and 3. Also, I have read the section about transistor pin mapping between symbol and footprint here: http://geda.seul.org/docs/current/tutorials/gsch2pcb/transistor- guide.html The author specifies two schemes for achieving this, and chooses one. I would have thought a third scheme would be better, where all transistor symbols have pins labelled B, C, and E, and there will be different versions of the TO92 (or TO5 or whatever) footprint, called TO92- EBC, TO92-CBE, and so on. To preserve my sanity, I simply prefer that the footprints have pin numbers 1, 2 and 3 in the usual order. That way I have ONE TO92 footprint that can be used with any TO92 device (like a voltage regulator or a reference or temperature sensor or whatever, in addition to transistors). And people think heavy symbols are a problem! Multiple footprints that are identical except for the pin numbers sounds like overkill to me. What is the general opinion about keeping symbol pin numbers for transistors as B, C and E? Isn't this better? See above. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Google Summer of Code on gEDA Webpages
On Mar 11, 2007, at 3:02 AM, Werner Hoch wrote: Hi Ben, On Saturday 10 March 2007 22:47, Ben Jackson wrote: On Sat, Mar 10, 2007 at 09:53:07AM +0100, Werner Hoch wrote: I'm currently drafting a better spice integration into gschem. Maybe that could be a project, too. Anyone who is thinking of improving a spice GUI has got to try Linear Technology's free SwitcherCAD (aka ltspice). It's the nicest spice I've ever used. It's a better schematic entry program than most, too (and that would include Eagle and gschem). I've played with LTSpice an hour. Things I like: * the current and voltage probing (visible marks are missing) * all entries (simulations and voltage sources) are done with dialog widgets and also printed in plain text. * changing the model of a diode or transistor * the property dialog for each circuit element (right mousebutton) Things I don't like: * schematic entry (selecting, moving, ...) * only one simulation at a time. This is o.k. for tinkering, but not for real work. I hate it when using PSpice (schematics) at work. You can't split your workflow into entry, simulation and postprocessing with it. I use LTSpice fairly regularly. I like the same things Werner likes. I also like the ease of creating new library components. I like how it's easy to specify parasitics for passives (such as ESR for caps, etc). I am annoyed by the schematic capture. Zoom in and out are not on any reasonable key (how about pgup and pgdwn or + and -?) and its panning algorithm never seems to work right (try placing a symbol off the edge of the screen and it doesn't pan as it should). I like how the schematics are ASCII, which makes them SCC friendly. I hate how the libraries must be in the same set location. I haven't figured out a good way of keeping my libraries separate from the LTC libraries, so updates don't fsck up my libraries when I run the program updater. You can set up the usual Monte Carlo runs, etc etc, and you can run it in batch mode if you like. Like most people who use some sort of Spice program, I keep the simulation schematic separate from what will be used for layout, for all of the usual reasons: some components on the layout schematic can't be simulated, and some things needed for simulation shouldn't be on the layout schematic. I don't think LTSpice is an example of vendor lock-in, except for the obvious, which is that LTC makes their switcher part library models available only with LTSpice. You can't use the models with another simulator, and they won't open up that simulation engine for use with other vendors' devices. LTSpice began as a means to an end -- to get people to buy LT's parts (which are pretty good). The fact that it's a full-featured Spice comparable to the non-free (as in beer) programs is a nifty bonus. And it doesn't suck, unlike National Semiconductor's Web Bench and TI's castrated TINA. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Feedback
On Mar 10, 2007, at 6:41 PM, Matthew Sager wrote: I have been working on a program to convert Gerbers to gcode. So far it is not completely working. It should output a good gcode file for drilling the vias as long as you have drill bits for all the via sizes that you used on the PCB. Parsing out the trace edges is still a work in progress. I am trying to clean up the code some and support rectangular pads right now. It might work ok for a very simple PCB, but most likely you would have to do a lot of editing by hand to fix the problems. Why use gerbers for the drill locations? Use the excellon NC drill file instead. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: What's your way of syncing CPLD design and gschem symbols???
On Mar 8, 2007, at 9:35 AM, Christoph LECHNER wrote: Hi! How do you keep your Xilinx CPLD design in sync w/ your gschem symbol files? I mean, after you have drawn all your schematics and build up the essentials of your CPLD design (esp. the pins must exist :)), when doing the PCB artwork shuffling the CPLD pins can give a really improved PCB layout ... But the problem for me was to keep the symbol in sync w/ the Xilinx Fitter report, so to do the work auto- matically I hacked a Perl script (~6kB) last year, but before adding some required upgrades improvements to the script I just wanted to ask how you do the sync job! For those not familiar with the Xilinx report files I added a example Xilinx pin-out report for a small Xilinx device (sorry for the attachment!) Files with this structure are converted to symbols. It might be easier to work backwards, from the schematic, and have it back-annotate into the .ucf (user constraint file), which is the file used by the Xilinx tools for pinouts (and timing specs, etc etc). It gets even more complicated when schematic net names don't match the CPLD design pin names, or when you connect the same schematic net to two FPGA pins (like when doing external clock feedback). This isn't really a problem for small CPLDs but it's a right royal PITA with large FPGAs. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: What's your way of syncing CPLD design and gschem symbols???
On Mar 8, 2007, at 2:47 PM, Christoph Lechner wrote: Andy Peters schrieb: It might be easier to work backwards, from the schematic, and have it back-annotate into the .ucf (user constraint file), which is the file used by the Xilinx tools for pinouts (and timing specs, etc etc). It's true that ripping off everything exept the pairing Pin Names - Pin Numbers from the gschem symbol is a snap compared to building/ updating a symbol from the Fitter report. But how would you make sure that the user of gschem doesn't put an input pin at an reserved location, i.e. a JTAG or PWR pin. I guess we're talking about creating symbols that are CPLD-design specific, so that pin names will change with the design. This is as opposed to creating generic symbols, as noted in my other e-mail in this thread. Generic symbols have the vendor-assigned pin name which includes information about pin type, such as differential pairs, global/regional clocks, config pins, etc. To answer the question. One of two ways: a) Have Yet Another Attribute attached to the symbol pins that would throw up an error if a user attempted to attach a regular signal wire to one of the reserved pins. b) Assume that the gschem user is not an idiot, and is actually looking at the vendor-provided pinout tables while deciding which pins to assign. I just got through doing this last week for a 100- pin VQFP Xilinx FPGA. This might be the simplest approach. I had the schematic and layout windows up and a printout of the pinout diagram, and assigned pins based on how it routed while also noting the pin type. Of course, what would be cool is if after this all completed, it would back-annotate to the .ucf. A guy can dream ... The timing issues following from forcing the Xilinx tool to use a user-defined pin-out are non-trivial IMHO, at least for CPLDs. So I guess it would be better regarding timing issues to run Xilinx ISE (or another vendor's tool) first and then go to gschem and create/update the symbol. For older architectures, it was definitely a requirement that you let the tools assign the pins. But in my recent designs, using CoolRunner CPLDs and Spartan IIE and 3E and Acex FPGAs, I assign pins as needed by the layout, and I've never had problems meeting timing, nor have I had fitting issues. The XC3000 and 95xx parts are dead! The (at the moment) missing link between logic design tools and gschem is a big show-stopper for the gEDA suite, I guess. Commercial tools charge big bucks for this missing link, and it's still not ideal. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: C question
On Mar 3, 2007, at 4:57 PM, [EMAIL PROTECTED] wrote: Thanks. I threw the question to the group because I know there's plenty of knowledgable people reading willing to answer it. Anyway, I was trying to get the compiler to generate 2 versions of an initialized array: ROM, and RAM. The processor I am using has more ROM than RAM, so placing the code into ROM makes more sense, yet I was having trouble getting access it correctly due to a routine expecting a const ptr. So, I was trying it in RAM, but not sure if the code was correct. Thanks again for the help :) You didn't say which compiler you're using, nor which architecture. But Keil's 8051 compiler has the code keyword, which tells the compiler that the variable should be put into CODE space, which is by definition ROM. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: home made hot plate
On Mar 2, 2007, at 12:57 PM, Ryan Seal wrote: Dave N6NZ wrote: Seeing DJ's hot plate photo brought to mind a link I once saw, where a guy built a home-brew SMT hot plate. I can't find the link, but as I recall, he used a few low-ohm high-watt power resistors epoxied to a piece of aluminum sheet. He drove it with a 0-30V bench supply and controlled the temperature manually by varying the voltage. Seems to me that one should be able to build a pretty good hot plate that way for not a lot of money. Although I would think that copper might give more uniform heat spreading than aluminum (at much greater expense, however, unless you get lucky). And a thermostatic temperature control shouldn't be hard. -dave Why not heating wire? How would you attach it to the hot plate? -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Which are the biggest looking gEDA warts?
On Feb 25, 2007, at 4:53 PM, Ben Jackson wrote: On Sun, Feb 25, 2007 at 05:07:59PM -0600, John Griessen wrote: No back-annotation. This is VERY important to me. As part of general cleanup after finishing a layout, I renumber all of the reference designators in geographical order. This gives technicians a fighting chance to find parts on a cluttered board. PCB: Rats don't move when you drag a group. And sometimes they don't move in other situations. Having seen the internals now, I can see why it's a crapshoot. Also a show-stopper. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Ones Zeros Technologies Pays PCB Design Engineers Royalties Same as Artists and Musicians
On Feb 22, 2007, at 5:38 PM, Bob Paddock wrote: I'm sure this has problems in so many different ways, but thought you'd find it interesting none the less: http://www.pcb007.com/anm/templates/article.aspx? articleid=14561zoneid=79v= OZT has revolutionized the industry by announcing the company's plans to additionally compensate design engineers for production of their PCB designs. No method exists today for PCB designers to track and/or benefit from the current and future production runs of their designs. This new business method should create a paradigm shift in the industry, states Todd Stewart, CEO of OZT. By registering with http://www.microgrouppcb.com/ , a division of OZT, the design engineer receives a unique registration identifier (ID) administered from the client system. This ID is perpetually assigned to the PCB Design Engineer Get the full article here: http://www.pcb007.com/anm/templates/article.aspx? articleid=14561zoneid=79v= Has anyone noticed a revolution in PCB design? I've apparently missed it. :-) Anyone signing up? All well and good, except for the part in most employee/contractor agreements which stipulates, the company paying you the money owns everything. It's all work for hire, unless the agreement specifically says otherwise. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: vhdl and gschem
On Feb 16, 2007, at 6:49 PM, Ostheller, Joel A. wrote: Yes. Pick yourself up a copy of Peter Ashenden's The Designer's guide to VHDL. Additionally you may want to get a copy of the IEEE VHDL LRM. There is no reason to use schematic capture packages to do Verilog or VHDL. Some have claimed that using it to import your VHDL/Verilog such that it auto-generates a system block diagram is an acceptable use... I usually will give them that, but not much more. I totally agree. Skip schemtics entirely when doing FPGA designs. My FPGA testbenches include bus-functional models of everything the FPGA talks to. To support this, I use either vendor-supplied models (memories and such) or I write them myself. (PLX wanted me to give them my Verilog models of their 9030 and 9656 chips, so my company said, you'll need to pay us... and that ended that discussion quite quickly.) The microcontroller or whatever talks to the FPGA, which does something interesting, and interesting outputs result, which are compared to an expected result. The automatic block diagram is interesting, if only to put on a slide for a design review, but I'd argue that you should have your block diagram draw BEFORE you start coding ... -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: www.66each.com
On Feb 13, 2007, at 12:10 AM, DJ Delorie wrote: And there's an intro offer at www.pcbnet.com for 4 layer 60 sq in, $50 with no minimum. But it is an intro offer... And... company name required So make up a company name. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: www.66each.com
On Feb 13, 2007, at 8:37 AM, DJ Delorie wrote: Oh absolutely. It's just a matter of whether the capabilities, the open nature and the low, low price are enough to overcome the bugs and the, uh, quirks of the user interface. I'm not likely to use 53 layers and a 40 acre board, but I would like the ratsnesting to work in a sane fashion and I'd like auto DRC to let me actually draw traces to pads in the same net... Please be specific about which version and what bugs, as we're doing a lot of work on it these days and bugs are getting fixed all the time. The problems you see may already be fixed in the CVS version, or perhaps we need to work on documenting how some of our features work. One bug/annoyance I can think of is when moving a footprint, with rats-nest enabled, the rats-nest lines don't move smoothly with the footprint. After you drop the part in the new location, you have to zoom in or out to clean up the rats-nest. I'm on PCB version 20060822 (the latest in fink) on OS X 10.4.8 on Intel. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: ground plane fill
On Feb 12, 2007, at 6:58 AM, Dan McMahill wrote: Peter Baxendale wrote: For that matter, why isn't it just automatic that lines and arcs in the same net as the polygon merge, and others clear? Well, before the poly exists, or before any lines connect to it, how do you know what net it belongs to? If the net is unknown, it would mean no polygons could ever connect to anything - they begin life not belonging to any net so all nets would be prohibited from connecting to them. I have to admit, this is one of the few aspects of Orcad I actually liked better than pcb. When creating a copper fill you got (amongst other things) a drop down list of nets, and you chose which one you wanted the polygon connected to. This makes the connectivity dependent on the net, rather than some flag in the many bits of track on the board, which sort of made sense to me. me too. Thats how it works in PCAD. And DXP, and Ultiboard/Electronics Workbench, and Mentor. I think it's the expected functionality. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: LED 100 != 5mm LED ?
On Feb 12, 2007, at 10:07 PM, Dan McMahill wrote: Andy Peters wrote: However, when an install of pcb comes with a warning that there are errors in the m4 libraries, yet doesn't say what footprints have errors (not to mention: why haven't these errors been fixed?), leads one to simply not trust the provided libraries at all. Could you point me to where that warning is? It needs to be updated. It's in the wiki: http://geda.seul.org/wiki/ geda:pcb_tips#how_do_pcb_s_footprints_work and I know I've seen it elsewhere. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB manufacture
On Jan 27, 2007, at 8:11 PM, Lares Moreau wrote: Anyone ever used the following service? http://www.goldphoenixpcb.biz/index.php There is something that is setting off my spidey sense about them. In particular, the 'fail rate' of 15%. What exactly does this mean? It means you get what you pay for. No rules checking, no error checking, just run-and-gun. Relative to other places I've been looking at they are really inexpensive. I've had good luck with PCB Express (now called Sunstone) and Advanced Circuits (4pcb.com) for quick-turn small quantity stuff. At the day job we use Circuit Express (http:// www.circuitexpress.com/) in Tempe, AZ; they're real good. If they find any issues with your gerbers, they call and sort things out with you. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Another m4 problem.... SOLVED and broken Footprint :|
On Jan 14, 2007, at 5:42 AM, John Luciani wrote: On 1/14/07, Lares Moreau [EMAIL PROTECTED] wrote: Really Solved the problem... It's the Footprint afterall. QFP-80P-1780L1-1780L2-64N is the culprit. I don't know why... but it seems to be. I can use the symbol I made with any other 64N and it works just fine. I tried two other symbols with 64 pins and they fail with the above Footprint. :| I looked at it, but can't seem to find why it's doing something weird. Thanks DJ, and ping luciani -Lares This problem has happened a few times. I believe it is due to the way that the m4 macros parse the footprint name. A few options --- (1) fix the m4 macro or (2) rename the footprint or (3) move the m4 macro libraries so they are never called. (* jcl *) Sounds like the problem I was having a few weeks ago. The only solution was to delete the m4 libraries, which is no loss. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GEDA Code Sprint: Idea
On Jan 9, 2007, at 4:34 PM, DJ Delorie wrote: One thing I would like to see in pcb, is have the option of Keyboard shortcuts printed in the menu drop downs. Preferably 'dynamic' so if a key is updated, the new shortcut is printed. The lesstif HID already does that ;-) So how do I know if I'm using the lesstif HID or gtk or ... ? -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GND vs. PGND
On Jan 9, 2007, at 10:38 AM, John Luciani wrote: On 09 Jan 2007 18:13:35 +0100, David Kuehling [EMAIL PROTECTED] wrote: Hi, I used both (analog) GND and PGND symbols in my layout. Now after running gschem2pcb and loading the netlist file I see that those symbols create two separated nets. Still I want to connect GND and PGND somewhere in my layout without making the DRC complain. I tried to add a connection between GND and PGND in my schematic, but that doesn't help. If you attach two named nets to a component pin they will connect. See my simple example below. A net with two names should throw a Big Fat DRC Error! -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: random observations
In no particular order. All observations pertain to the latest version in fink (20061020). + Assume the symbol is not embedded in a schematic. If one edits an element (text line, attribute whatever) in the symbol (either in a text editor or using gschem), the next time the schematic is loaded, only visible elements get updated. If you make all of the hidden attributes visible, select a component and use ep (Update Component), the attribute still doesn't update. + After gschm2pcb runs, it gives a list of Next steps. Step 1 says From within PCB, select `File-disperse all elements.' Actually, disperse all elements is in the Select menu. + Step 3 is From within PCB, enter :ExecuteFile(boardname.cmd) to propagate the pin mames of all footprints to the layout. It wasn't obvious that you need to choose Window-Command Entry from the main PCB menu. Also, the colon in front of :ExecuteFile causes the command to fail (the terminal shows a log message, unknown action `:ExecuteFile). Removing the colon does the trick. + It would be nice if the PCB Command Entry dialog's command-entry drop-down listbox retained any previously-entered commands. + If you give a pin a pinlabel that includes parentheses (or perhaps simply has a close parenthesis as the last character), for example, VOut (tab), the ExecuteFile(boardname.cmd) complains with unknown action `)' + gsch2pcb handles netnames with \_ \_ delimiters that indicate active-low signals and has no trouble creating a netlist with these characters included. Importing that netlist into pcb is fine, too. However, if you save the pcb file, close pcb, then re-open the pcb file in pcb, you get a syntax error in the pcb file at the first instance of \_. + Having zoom in and zoom out as part of the history is driving me bonkers. According to the archives, this is a religious issue. Perhaps a way to toggle this would appease all gods? + Is there any way to have the net name appear on the pads and pins in pcb? + Ratsnest rubberbanding seems to turn off for no reason. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: random observations
On Jan 4, 2007, at 3:11 AM, Kai-Martin Knaak wrote: On Thu, 04 Jan 2007 01:06:09 -0700, Andy Peters wrote: + If you give a pin a pinlabel that includes parentheses (or perhaps simply has a close parenthesis as the last character), for example, VOut (tab), the ExecuteFile(boardname.cmd) complains with unknown action `)' A preprocessor that checks for malformed net names, refdes, pin labels, and values is generally missing. Such a cript would have saved my a bunch of head scratching. My favorite is gsymcheck, which will print out Read garbage in symbol foo.sym and yet report that the symbol is perfect. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random observations
On Jan 4, 2007, at 12:41 PM, DJ Delorie wrote: Oh, that's too bad. It's an amazingly useful feature. Perhaps, but difficult logistically. My initial question is, where on the net do you put the text? On pads, pins or vias. What's usually done is that the netname appears on the pad/pin/via only if the view is zoomed in enough. Zoom out and the netnames turn off to prevent clutter. What we do have is the netlist dialog; you can click on a net to highlight it on the pcb. Perhaps a reverse feature (click on the pcb, have the net name highlighted) would be a good short-term compromise? That requires clicking on something. The idea is that you can see the netnames and decide which signals to route first. It's just a convenience, but like I said, it's one that's very useful. Of course I realize that many people use netnames only for significant nets, or those that go to other sheets, so nets not given that attribute don't have a netname (other programs automatically assign a netname if one is not given) so perhaps this is less useful for others. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Success! was Re: gEDA-user: gsch2pcb : coming up empty
On Jan 3, 2007, at 2:12 PM, Hans Nieuwenhuis wrote: On Wed, 3 Jan 2007 10:32:19 -0700 Andy Peters [EMAIL PROTECTED] wrote: On Jan 3, 2007, at 8:03 AM, Hans Nieuwenhuis wrote: Sorry for me jumping in, but I remembered a situation a while ago having the same problem also. The cause of the problem is the dashes in the filename of the footprint. If the OP had not used multiple dashes there would not have been a problem. After I figured out I forgot about it and I should have filed a bug instead. That's not it; John Luciani's library is full of parts with all manner of dashes and underscores. My problem went away after finding and removing some old geda libraries (I know it is a FAQ :-) and re-installing the latest versions from source, maybe that helps for you too. Whilst browsing the archives of this list, I came across a message that asked how to force gsch2pcb to ignore the old m4 libraries entirely (answer: simply delete or rename the directory). From its output, it appeared that the gsch2pcb program seemed to think that the bad symbols were somehow supposed to be in the m4 library. So I shitcanned the m4 library entirely ($ mv /sw/share/pcb/m4 /sw/ share/pcb/_m4) and gsch2pcb works ... Progress! -a PS: I found in the archives a rather heated discussion about the relevance of the m4 libraries in particular and the m4 macro processor itself in general. Somebody wondered what Unix programs, other than pcb, used m4, and there was no answer. Turns out there IS an answer, and it's a biggie: sendmail configuration files are all written to use m4. One wonders if sendmail's inscrutable configuration was the reason exim, qmail and postfix were developed! The sendmail book is by far the thickest of all of the O'Reilly books, even if you consider that it's printed on the thinnest- possible paper in the smallest possible typeface. I like the bat, though. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: good idea - bad idea ?
On Jan 3, 2007, at 3:09 PM, John Luciani wrote: On 1/3/07, Ostheller, Joel A. [EMAIL PROTECTED] wrote: I can not get gsch2pcb / pcb to stop using the M4 library as a default. What does your gsch2pcb command line look like? Are you using the --use-files switch? gsch2pcb --use-files --elements-dir ~/YOUR_FOOTRPINT_DIR SCHEMATIC_NAME --use-files doesn't cause gsch2pcb to ignore the m4 libraries. Maybe a switch can be added to gsch2pcb: --no-m4-libs ?? -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gsch2pcb : coming up empty
Happy New Year, gang ... Here's an odd problem. I'm on Mac OS X 10.4.8, using the latest fink release. I've created a handful of symbols with footprint attributes attached. I've also created a couple of newlib footprint using Darrell Harmon's footgen; the relevant one here is an SOT223. I'm also using John Luciani's footprint library dated 18 Dec 2006. I've set up the following directory structure for the libraries: /Users/andy/Library/gEDA/symbols/ - symbols under here /Users/andy/Library/gEDA/pcb/jcl/ - John's footprints here /Users/andy/Library/gEDA/pcb/asp/ - my footprints here The symbols pass gsymcheck with no warnings and no errors. I've created a simple schematic, and the schematic passes DRC (using 'gnetlist -o drc_output.txt -g drc2 test.sch') with no errors. Next, I tried to run gsch2pcb to get the PCB files, using: $ andy$ gsch2pcb -v --use-files --elements-dir /Users/andy/Library/ gEDA/pcb power.sch gs.txt and I get an odd failure. The three components on the schematic that use footprints in my library (~/Library/gEDA/pcb/asp/) are not handled by the netlister. Here's what's in the gsch2pcb dump: : have m4 element , but trying to replace with a file element. No file element found. : added new m4 element for footprint(value=) The blank reference should have found my SOT223 footprint. If I change the footprint to something in John's library (anything, it doesn't matter), the component is processed properly and the footprint is found. So, what causes gsch2pcb to crap out like this? Attached is a simple test schematic that uses referenced standard symbols for resistors and a connector and an embedded symbol for a voltage regulator. The resistors use the 0805 footprint (probably pulled from the m4 library). The voltage regulator uses my SOT223- footprint (also attached). The connector is supposed to use the 0.1_inch_2pin footprint from the newlib but it fails to load (and an error is displayed). Again, for some reason, gsch2pcb can't deal with my SOT223-xxx footprint and I don't know what's wrong with it. Any help is appreciated. test.sch Description: Binary data SOT223-230P-650W-356L-4N Description: Binary data ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gsch2pcb : coming up empty
On Jan 2, 2007, at 6:01 PM, John Griessen wrote: Andy Peters wrote: Happy New Year, gang ... I tried to run gsch2pcb to get the PCB files, using: $ andy$ gsch2pcb -v --use-files --elements-dir /Users/andy/ Library/gEDA/pcb power.sch gs.txt and I get an odd failure. The three components on the schematic that use footprints in my library (~/Library/gEDA/pcb/asp/) are not handled by the netlister. . . . If I change the footprint to something in John's library (anything, it doesn't matter), the component is processed properly and the footprint is found. So, what causes gsch2pcb to crap out like this? Have you got a file in the local dir called gafrc with contents like: lib-newlib = /home/john/EEProjects/now/circuitboards/footprints_pcb? If not, and you're using the latest code, you need it. I have a gafrc in ~/.gEDA, which includes the component-library lines for all of my symbol libraries. I don't have the elements-dir line in gafrc (I didn't know it could/ should be there), but my command-line has one, and I know that it's being honored because if I change the footprint= line in the schematic that references the bad footprint with a good footprint in my library directory, it works. (Apologies for the run-on sentence!) I created a project file which includes a use-files directive and an elements-dir line, and used that instead of the command-line above and it still fails in the same way. So I think that my footprint is broken, but I dunno how or why! -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gsch2pcb : coming up empty
On Jan 2, 2007, at 7:59 PM, John Luciani wrote: On 1/2/07, Andy Peters [EMAIL PROTECTED] wrote: So I think that my footprint is broken, but I dunno how or why! -a If your footprint is a simple newlib footprint you may want to post it. Actually, I did, in the message that started this thread, but I'll include it here (in case this list rejects attachments). It's called SOT223-230P-650W-356L-4N. Thanks, -a - Element[0x00 SOT223-230P-650W-356L-4N 0 0 0 0 0 100 0x00] ( Pad[-9055 11418 -9055 13386 3937 1200 4537 1 1 0x0100] Pad[0 11418 0 13386 3937 1200 4537 2 2 0x0100] Pad[ 9055 11418 9055 13386 3937 1200 4537 3 3 0x0100] Pad[-3543 -12402 3543 -12402 5906 1200 6506 4 4 0x0100] ElementLine [ 12992 17324 -12992 17324 1000] ElementLine [-12992 17324 -12992 -17324 1000] ElementLine [-12992 -17324 12992 -17324 1000] ElementLine [ 12992 -17324 12992 17324 1000] ) - ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gsch2pcb : coming up empty
FWIW, here's the input file for footgen.py: # PCB footprints # Convert to newlib by using footgen.py # This file is not copyrighted # You may use these footprints as you wish. # There is no guarantee that the data is accurate # check the datasheets for you components # SOT223 parts elementdir = sot223 silkwidth = 10 mils silkstyle = inside silkboxheight = 6.5 mm silkboxwidth = 3.56 mm silkoffset = 0.5 mm maskclear = 6 mil polyclear = 6 mil type = tabbed pins 3 pitch = 2.3 mm height = 4.8 mm padwidth = 1 mm padheight = 1.5 mm tabwidth = 3.3 mm tabheight = 1.5 mm part SOT223-230P-650W-356L-4N ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gsch2pcb : coming up empty
On Jan 2, 2007, at 8:28 PM, John Luciani wrote: On 1/2/07, Andy Peters [EMAIL PROTECTED] wrote: On Jan 2, 2007, at 7:59 PM, John Luciani wrote: On 1/2/07, Andy Peters [EMAIL PROTECTED] wrote: So I think that my footprint is broken, but I dunno how or why! -a If your footprint is a simple newlib footprint you may want to post it. Actually, I did, in the message that started this thread, but I'll include it here (in case this list rejects attachments). It's called SOT223-230P-650W-356L-4N. That symbol loaded for me without any problems. What version of gsch2pcb are you using? The version in fink is 1.5. PS: the IPC-style SOT partnames don't have a width and length parameter just a leadspan. It probably should be something like --- SOT223-230P-xxxL1-4N Ah, OK ... I'll fix it once I sort out this gsch2pcb issue... -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Interesting Cygwin/X observation
(No, I haven't gotten the gEDA tools to work under Cygwin ...) I'm running Cygwin/X on a XP box and ssh-ing into the Mac Book Pro (OS X 10.4.8). When I run gschem, I'm greeted with an 'Xlib: extension RENDER missing on display localhost:10.0.' message. gschem will crash soon afterwards. After some googling, I find out that this has something to do with ssh tunnels and such. If I get into the remote machine by doing: $ ssh -X [EMAIL PROTECTED] I get the Xlib RENDER message. If I get into the remote machine by doing: $ ssh -Y [EMAIL PROTECTED] (using so-called fake authorization blah blah) I don't get the message and gschem is stable. Just an FYI ... -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: adding footprints attribute to schematics symbols
On Dec 26, 2006, at 3:29 AM, csanyipal wrote: I'm newbe in electronics and with gEDA so please help me with few advices! I try to make a PCB board for a PC interface for educational purpose. The PC interface should to get +5V from USB port. I assume that you're not designing a USB device. Don't steal power from the USB interface. First off, it goes against the USB spec. Second, it may not work. You design may want to draw too much current from the port and it may just stop working as there are current limits for each port. Yeah, yeah, yeah, I know, there are all sorts of broken USB devices (like USB cooling fans and USB lights and such). Let's try not to make matters worse, eh? -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: licensing (GPL or otherwise) for hardware?
On Dec 19, 2006, at 10:38 AM, DJ Delorie wrote: That's not illegal even is US then as you say. Right, unless you patented it. Even if it was patented. The patent hold would have to defend the patent. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
subversion usage (was: Re: gEDA-user: Symbol submission)
On Dec 15, 2006, at 3:56 PM, DJ Delorie wrote: There seems to be a way to deal with just sub directories of a tree, after you have the whole tree. If you move that subdir to a new place, it still functions as a svn working copy of that much of the tree, and you could then delete the rest with no impact on the repository. But if you do an update to a specific version (or date) after moving the subdir, it re-creates the subdir. Which is as it should be, because you update to the specific state of the repository as of whatever revision you choose. But if you update to HEAD, then assuming that subdirectory move was done properly (and if done from a working copy, committed back to the repo), the moved subdirectory vanishes from updated working copies. The thing that svn can't do is check out a tree WITHOUT getting specific subdirs. For example, getting pcb without the documentation. I have no idea what the tree looks like, but for argument's sake, assume it's like: pcb/src /docs /foo /bar /whatever One could certainly do: $ svn checkout http://svn.pcb.org/svn/pcb ./pcb and get the whole tree. One could just as easily do: $ svn checkout http://svn.pcb.org/svn/pcb/src ./pcbsrc and get just the sources. This is a big problem for binutils/gdb/newlib/cygwin because they share a repository and a lot of common top-level files. The usual subversion solution to this is to maintain the common, top- level files as their own projects within the repo (or even in a different repo), and include them using the svn:externals property. When using externals, a reasonable use case is to always use tagged versions of the external-ed modules. By subversion convention, tags are immutable, and the idea is that you always know which version of every external you use. If you were to simply use the trunk of each external-ed module, checking out your project always gives you the latest version of the submodules. When working on your project's trunk, that might be OK. But, as noted, a tag is immutable, so if someone has changed submodule foo's trunk, and someone else checks out and builds your project's release tag, they may not get what you think they should get. (Does that make sense? Simply stated, submodules are projects unto themselves, with their own trunks, branches and tags.) Anyways, regarding how binutils/etc are organized: if they wish to switch to svn, a repo reorganization might be in the future. That, of course, is up to the people who maintain it. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gschem and heterogeneous symbols
I was looking through the various gschem for answers to this, but I've come up with nothing. Does gschem support the notion of heterogeneous schematic symbols? Consider a dual op-amp chip. I like the symbol for part A to include the power pins, and the symbol for part B to not include the power pins. Another use of this would be where you have an FPGA with several logical interfaces (a memory interface, a microcontroller bus interface, etc etc). I find schematics with a big 256-pin part with a bunch of wires sticking out of it to be rather messy, so the ability to create a custom symbol for each part cleans things up considerably. Anyways, about the closest I can come to this idea is to create a pair of symbols for my dual op-amp. One symbol has the power pins; the other doesn't. Both symbols get the same ref des. I'm not sure how to set slot numbers and slotdef. If this feature doesn't exist, then consider it a feature request! -- a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Symbol submission
On Dec 15, 2006, at 2:21 AM, Karel Kulhavy wrote: If I won't be able to submit through the old mechanism I won't probably submit anymore. gedasymbols.org are just too complicated for me. Subscription, password management, directories, CVS - takes too much time. gEDA should dump cvs and switch to subversion ... ;) -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
