Re: gEDA-user: Google Summer of Code 2011
On Wed, Mar 2, 2011 at 1:37 PM, Kai-Martin Knaak k...@lilalaser.de wrote: The other caveat: Don't choose an overly ambitious project, even if it is as cool as liquid nitrogen. Ask Anthony Blake for the reason... Well if you want to do an ambitious project, you have to commit long term to the project, and I didn't do that. I don't really want to go into the reasons for why I quit (theres a few of them), but Kai-Martin's attitude is a good example of why I'm no longer a gEDA developer. Kai-Martin: As well as using me as a counter-example, could you provide some good examples of the sorts of projects you would like to see? Regards, -- Anthony Blake ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Help with board layout
Hi Oliver, I'm the developer of PCB's toporouter[1]. I have a few questions, if you don't mind: - Do you mind curvilinear wiring? - How many power supplies? - How much are you paying for the job? - Have the schematics already been captured in gschem? - Have footprints for components already been captured and verified? - Can you give me any hints about the complexity of the routing? Is it really nasty all-to-all stuff? Or is there some structure to it? Any info you could give me would be appreciated. Cheers, Anthony [1] http://anthonix.resnet.scms.waikato.ac.nz/toporouter On Tue, Mar 1, 2011 at 7:34 PM, Oliver King-Smith oliver...@yahoo.com wrote: I hope this is not considered list abuse, but I am looking for someone to layout a board in geda's PCB. The board consists of approximately 100 ICs and associated components. There is a lot of repetition on the board, and most of the ICs are single opamps, so the board is not as big or scary as it might seem. All the footprints have been made and the schematic was done in gschem. The design is mostly analog signals and these operate below 1KHz. The signals get digitized with a 20bit ADC. All the power supplies are linear regulars. These is no impedance control needed for the board. The digital section of the board is galvanically isolated from the analog section which makes grounding issues pretty straightforward. I don't have any space constraints, but I anticipate it should fit nicely onto a 10x10 inch or smaller board. I anticipate that a 6 layer design should be more than sufficient to get a good layout (an aggressive layout can probably get away with 4 layers. I am on a schedule. I would like to have the board laid out within the next 3 weeks. The board is testing an ASIC, and if I am going to meet the later summer shuttle run, I really need the board built by the early of April. I am located in northern California, but you can be located anywhere in the world. If you are interested in doing this contract, or if you have any questions, please email me directly. Please include any a brief description of any experience you have had with using PCB. Thank you in advance Oliver ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Anthony Blake ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter VERY slow?
On Wed, Dec 8, 2010 at 11:46 AM, al davis ad...@freeelectron.net wrote: One point I disagree with you on, which indicates there is still hope The silent majority do want progress. The vocal majority you refer to is really a vocal minority. Ahh yeah, thats what I meant sorry. On Sat, Dec 18, 2010 at 2:07 PM, Kai-Martin Knaak kn...@iqo.uni-hannover.de wrote: Alternatively, cut the job into handy sub jobs and ge one of us lurkers on the mailing list to do the coding. I've tried that several times and it didn't work. In any case, I have other priorities, so I'm sorry, but I'm not going to be working on PCB anymore. When I have some free time I'll add some more comments to the code so someone else might pickup where I left off. Best Wishes, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FUNDING
On Tue, Dec 14, 2010 at 2:23 PM, timecop time...@gmail.com wrote: Anyway tl;dr version: RS sucks, DesignSpark sucks, Eagle sucks, buying a EDA suite to pimp to your customers as the only benefit of your shitty stock/price practice = stupid. Also any designer too lazy to make symbols/footprints for a new part should just /quit. Yeah, I don't think we should be trying to integrate the symbol/footprint library with some vendors database or webservices. We already have a decent footprint/symbol library.. But it would be worth replacing the footprints data structures code and adding a decent padstack editor. I think DJ proposed this as part of the LinuxFund work.. has there been any progress towards this? Cheers, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FUNDING (was: Random thoughts on the future interface of PCB)
On Sun, Dec 12, 2010 at 9:26 AM, Justyn Butler justynbutler+g...@googlemail.com wrote: On 10 December 2010 00:09, Stephen Ecob silicon.on.inspirat...@gmail.com wrote: On Fri, Dec 10, 2010 at 10:27 AM, asom...@gmail.com wrote: How about a Kickstarter project for the toporouter? Let Anthony make a proposal and put it on www.kickstarter.com, and then gEDA users can pledge donations. If it raises enough money by graduation (or whatever other deadline), then we all fund Anthony to work on it. If we don't raise enough, then nobody gets charged, the toporouter languishes, and Anthony has to get a real job like (some of) the rest of us. If we can raise enough for Anthony to get the toporouter working well (say to the point where it's working better than the existing autorouter for 2L and 4L boards), let's do it. Count me in for $4K. Anthony, how much funding would you need to get the toporouter working well ? A kickstarter project sounds like a great idea. I'd certainly contribute. As the funding only occurs if the goal is met, I'd personally recommend: 1) Giving plenty of time before the deadline 2) Considering bringing the target down from $4K, if that is possible. Pledges can still continue once the target is met. Yeah, someone suggested a kickstarter a few months ago.. it might be worth a shot. When I had a look at kickstarter a while back, most projects offered different levels of rewards depending on the donation. Any ideas about what sort of rewards I should send to people who donate? I was thinking stuff like a toporouted arduino circuit board would make good gifts for those who donate. If I do it, I think I should aim for a full years worth of funding, which would be at least 50k. Three months is too short. What do you guys think? Regards, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Random thoughts on the future interface of PCB
On Thu, Dec 9, 2010 at 10:12 PM, Stephen Ecob silicon.on.inspirat...@gmail.com wrote: On Thu, Dec 9, 2010 at 7:06 PM, Peter Brett pe...@peter-b.co.uk wrote: 1. Would any of the existing maintainers be able to devote more time to gEDA if they had financial support to do so ? In my case: yes. :-/ Peter OK, so that's a 'yes' for question 1! Now for question 2 - money. A few weeks back I was seriously considering paying $5K for Altium. In the end I decided against it (closed source p*sses me off too much), but it did make me realise that I could justify spending that kind of money on pcb software. Now if we're thinking in terms of a $200K per year developer then $5K will achieve next to nothing - but let's think of alternatives. I can't remember the details, but I vaguely recall that a second Google Summer of code with funding of ~$15K would have allowed Anthony to finish the toporouter. http://www.linuxfund.org/projects/pcb/ tells me that $3330 allowed DJ to improve PCB's file import system. So we don't necessarily have to think in $100K's for achieving real results. Now many of us aren't in a position to spend money on PCB software - but what if two other members of our community were also able to afford $5K ? Perhaps three of us could chip in to fund a GSOC equivalent. If that allowed a result like finishing the toporouter (say), I could well judge that to be money well spent. If 7 other people came forward and it was $2K each I'd find it a no brainer. But I realise I'm really ignorant of my own community - am I the only one who would consider funding PCB development by others ? Are there 7 who could afford $2K ? Are there 20 who could afford $750 ? I'm aiming to finish University in a few months.. if people would like to fund work on the toporouter, then I would be pretty keen to work on it full time. Regards, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Random thoughts on the future interface of PCB
On Sun, Dec 5, 2010 at 10:02 PM, Armin Faltl armin.fa...@aon.at wrote: There are blackboards for freelance engineers, to make a defined feature in opensource software. This seems a good model of payment to me. The problem to me in our case is atm: - the writer of a certain feature is not required to understand enough of the app, to avoid new bugs in other parts - the writer is not required to run extensive regression tests after the change and provide tests for his feature as well - there is noone fully coordinating the work of contributors and saveguarding the internal interfaces Since we do not have the documentation Bob requests, it's practically impossible, to meet above standards and without above quality measure in place I'm unwilling to pay any money. Btw., fixing bugs in a well designed, well documented, cleanly written application is a lot more fun than in insert_decription_of_choice and orders of magnitude faster. That's why I suggested to personally throw out BS like '#define END_LOOP }}' and all it entails. Since this was not welcomed, I decided to not try and dive into the code any further. Yes, if you were having difficulty with the END_LOOP macro, I can understand why you didn't venture any deeper into the code. Best wishes, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Random thoughts on the future interface of PCB
On Mon, Dec 6, 2010 at 3:40 AM, timecop time...@gmail.com wrote: Yes, if you were having difficulty with the END_LOOP macro, I can understand why you didn't venture any deeper into the code. I just saw the rest of the crap in the header file containing #define END_LOOP }} and I'm with Armin on that one, this is pretty ridiculous. I don't particularly like it either. But its a weak excuse not to dive into the code any further. Best wishes, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Random thoughts on the future interface of PCB
On Mon, Dec 6, 2010 at 4:18 AM, Armin Faltl armin.fa...@aon.at wrote:
Anthony Blake wrote:
Yes, if you were having difficulty with the END_LOOP macro, I can
understand why you didn't venture any deeper into the code.
I had no difficulty finding or understanding the macro, but I have a huge
problem
to work on code, where others deliberately introduce stuff, that is a
maintenance
nightmare. There is a reason, the compiler disallows unmacht '{' in one
file.
Relax, the macros aren't part of an elaborate plan to *deliberately*
obfuscate the code. That file is over 15 years old.
I don't think a few 'maintenance nightmares' or matching '{' problems
are good reasons for giving up and just doing nothing instead. You
don't have to like the macros and so on to fix bugs, and IMO just
nutting up and dealing with the matching '{' issues etc is worth it to
nail a bug that may have been bothering you. Its better than doing
nothing or writing large parts of PCB from scratch.
Best wishes,
Anthony
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter VERY slow?
On Mon, Dec 6, 2010 at 10:03 AM, kai-martin knaak k...@familieknaak.de wrote: Anthony Blake wrote: Any chance, this is going to change? I'm busy with school work at the moment.. I'll get to it eventually, if someone else doesn't do it first.. I'll take this as a no. Yep, thats a no. Most people who use PCB prefer a MS paint style interface where they spend a long time drawing lots of straight lines by hand, so I can't really be bothered. Good luck with that! Best wishes, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter VERY slow?
On Mon, Dec 6, 2010 at 11:25 AM, Stefan Salewski m...@ssalewski.de wrote: I must have missed a lot of that postings? See pcjc2's thread on a futuristic interface. You may be disappointed that no other people have continued working on your great router -- I guess the reason is that many of us feel that we are not smart enough to understand the internal working. Extending user interface and adding new features may be not to hard, but finding reasons for segfaults or bugs in the core code can be really hard, at least too hard for me -- in this winter of code. I don't expect other people to help out. But I do find it rather discouraging the number of people (unfortunately a vocal majority) who are actively hostile towards anything that would threaten their job spending 100's of hours laying out straight line PCB's by hand. Why the fuck do people send me private email telling me that they don't use/trust autorouters, and thus it is pointless trying to improve an autorouter? The 70's called, and they want their manual tapeouts back. And yes, the bugs in the toporouter are nasty. Over the last few months I've spent well over 100 hours trying to fix the topological sketch - curvilinear wiring exporter. I've tried so many fixes that didn't work in all cases, or introduced new bugs, until I finally nailed down what was going on. Along with the fact that no one is helping me, the rate at which I've been chopping and changing algorithms as I experiment with them is the reason I haven't documented anything yet. Now I've almost stabilized and verified the curvilinear export code, I'll start to document it. I'm doing things at my own pace, and I'll push when I'm ready. Best wishes, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter VERY slow?
On Mon, Dec 6, 2010 at 12:10 PM, Steven Michalske smichal...@gmail.com wrote: I look forward to your hard work, it is very impressive, and reminds me of the layouts from years ago, where they were taped out and pretty. None of this manhattan grid. Yeah, I love the curvilinear hand layouts in old hardware like the early Cray supercomputers. I know that Adding via's are non trivial for an auto router, with your topological auto router, will it use a via that I manually place? Yes it will, as long as it is attached to a net.. so you can manually fanout your pads and use the toporouter. Unfortunately using fanouts from pads to vias increases the likelyhood of a curvilinear wiring error, unless the stub's are totally straight. This is due to the bug I've been working on and will soon release a patch for. In the mean time, make sure those stubs are totally straight, otherwise the curvilinear wiring will go weird on you. Best wishes, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter VERY slow?
On Sat, Dec 4, 2010 at 1:16 AM, Kai-Martin Knaak kn...@iqo.uni-hannover.de wrote: Anthony Blake wrote: It was probably an impossible problem to solve without vias, and vias aren't implemented yet. Any chance, this is going to change? I'm busy with school work at the moment.. I'll get to it eventually, if someone else doesn't do it first.. Regards, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter VERY slow?
On Fri, Dec 3, 2010 at 10:42 AM, Stefan Dröge ste...@sdroege.de wrote: Is my design just too complicated, or are there some dubious settings that prevent the toporouter from beeing faster? It was probably an impossible problem to solve without vias, and vias aren't implemented yet. Regards, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Random thoughts on the future interface of PCB
Cool.. yeah I've always thought the future is in sketching topology and defining constraints.. sounds awesome! I remember talking about basically the same thing a couple of times over the last few years.. I was referring to it as semi-automatic routing where you sketch the topology of a net with the mouse (or some other input device). Regards, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Need papers of Toporouter
The most relevant of those can be found with a google search. Good luck! -- Anthony Blake ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: New branch of PCB
On Wed, Nov 17, 2010 at 12:09 AM, timecop time...@gmail.com wrote: With TopoR having a freeware version for 2 layers and up to 256 nets (or some other fairly high for 'hobby' use limitation), there's not really any point on bothering improving built in autorouter... Does PCB have Specctra DSN/SES export/import? Just use that (or implement if it doesn't) and then use any of the autorouters that work. hahaha. no. -Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: New branch of PCB
On Wed, Nov 17, 2010 at 11:13 AM, Stephen Ecob silicon.on.inspirat...@gmail.com wrote: On Tue, Nov 16, 2010 at 10:09 PM, timecop time...@gmail.com wrote: With TopoR having a freeware version for 2 layers and up to 256 nets (or some other fairly high for 'hobby' use limitation), there's not really any point on bothering improving built in autorouter... Does PCB have Specctra DSN/SES export/import? Just use that (or implement if it doesn't) and then use any of the autorouters that work. -tc TopoR does look very nice - a good target for our toporouter to try to better. The free version of TopoR is limited to 125 signals - much too small for my current board. Keep in mind that most of the screenshots on their site required extensive post-processing after autorouting.. if you read the captions, the main board they show off took 20 minutes of autorouting and 40 minutes of fixing by hand. I've never actually heard of anyone in industry using it. -Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: a small run with the Toporouter
On Tue, Sep 7, 2010 at 1:36 AM, Kai-Martin Knaak kn...@iqo.uni-hannover.de wrote: Atommann wrote: 1. The Toporouter really works and it's very cool. Last time I checked, it wasn't possible to let the topo router do only selected rats. Did this change? It has always been able to do only selected rats. You are probably thinking of the existing traces bug, which has been problematic on SMT boards. -- Anthony Blake ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: A topo auto router code base that is tested and works.
On Thu, Jul 29, 2010 at 4:34 AM, joshua wojnas josh...@gmail.com wrote: A topo auto router code base that is tested and works. Sounds made up.. Well their is graphical drawing open source software in graphvis neato fdp sfdp are all used to make graphs from things like netlists... Given that I couldn't get any of those graph programs to layout a signal flow graph of a certain FFT (it was rather trivial to do by hand), I'm doubt you are going to have any success. Basically, their algorithms sucked and seemed to favor runtime performance over quality of results. But I would love to be proven wrong =) Let me know how it goes.. -- Anthony Blake ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: TopoRouter Status
On Fri, Jul 9, 2010 at 6:10 AM, Felipe De la Puente Christen fdelapue...@gmail.com wrote: Hi, On Thu, 2010-07-08 at 13:57 -0400, joshua wojnas wrote: anyone sucsesfuly use the topo autorouter yet? I have tried it in two pcb designs, and in both cases it seg faulted. I think it's in a very premature stage. Lots of people have let me know about their segfaults over the years, but hardly anyone gives me any useful information. E.g., someone on this list just laughed about some silkscreen bug, but then wouldn't tell me anything about it. WTF is with that? Detailed bug reports (with .pcb file demonstrating bug) would be the way to help. By the way, haven't read the code yet, but is there any recommended place to study the theory of this tool? At the top of toporouter.c there is a list of references to get you started. Cheers, -- Anthony Blake ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Toporouter: Line constraints
I've just pushed an update to the toporouter which enables existing line traces (no arcs or planes yet). At the moment the CDT is being rebuilt *alot*, because of GTS's lack of constraint deletion.. This means it can only be used on small boards. If anyone finds any bugs, please send a small board demonstrating the bug. Cheers, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter: Line constraints
It is now possible to add a few vias and their stubs, and autoroute the rest, as in the following screenshot: http://anthonix.resnet.scms.waikato.ac.nz/existing_lines.png ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter: Line constraints
And DJ's Linksys board routed with vias: http://anthonix.resnet.scms.waikato.ac.nz/linksys_with_vias.png ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter: Line constraints
kai-martin knaak wrote: What is the metric of small in this regard? The number of connections to be auto routed? The size of the netlist includes connections ignored by the auto router The physical size of the board? The number of constraint edges. Where would I download and how would I install the bleeding edge version of the greenstone (?) router? Clone the PCB repo at gpleda.org.. Cheers, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter: Line constraints
kai-martin knaak wrote: Anthony Blake wrote: And DJ's Linksys board routed with vias: http://anthonix.resnet.scms.waikato.ac.nz/linksys_with_vias.png The layout surely looks special :-) So you helped the router with a few vias connected to pads with short tracks, right? Yup. I ran the toporouter, and then reran it with a few vias to help it route all nets. Cheers, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter: Line constraints
Ethan Swint wrote: On 03/20/2010 04:06 PM, Anthony Blake wrote: kai-martin knaak wrote: What is the metric of small in this regard? The number of connections to be auto routed? The size of the netlist includes connections ignored by the auto router The physical size of the board? The number of constraint edges. Constraint edges - those are the edges of the pads, pins, polygons, and existing tracks? Yes. Although polygons aren't imported yet... maybe later on today. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter: Line constraints
Steven Michalske wrote: On Mar 20, 2010, at 2:16 PM, Anthony Blake wrote: Ethan Swint wrote: On 03/20/2010 04:06 PM, Anthony Blake wrote: kai-martin knaak wrote: What is the metric of small in this regard? The number of connections to be auto routed? The size of the netlist includes connections ignored by the auto router The physical size of the board? The number of constraint edges. Constraint edges - those are the edges of the pads, pins, polygons, and existing tracks? Yes. Although polygons aren't imported yet... maybe later on today. I love the silk line support, I can now get connections drawn in conductive silk! Oh, Wait I found a bug, The toporouter used the silk layer for making connections. I've never seen that before. Can you please describe how to replicate the bug, and/or send a small board that I can just run the toporouter on to immediately demonstrate the bug. -Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter: Line constraints
Steven Michalske wrote: On Mar 20, 2010, at 2:16 PM, Anthony Blake wrote: Ethan Swint wrote: On 03/20/2010 04:06 PM, Anthony Blake wrote: kai-martin knaak wrote: What is the metric of small in this regard? The number of connections to be auto routed? The size of the netlist includes connections ignored by the auto router The physical size of the board? The number of constraint edges. Constraint edges - those are the edges of the pads, pins, polygons, and existing tracks? Yes. Although polygons aren't imported yet... maybe later on today. I love the silk line support, I can now get connections drawn in conductive silk! Oh, Wait I found a bug, The toporouter used the silk layer for making connections. Or you could even send a patch =) It doesn't sound like a tricky bug.. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Need boards for toporouter tests
Hi, If you have boards containing a mix of routed and unrouted nets, and they currently don't work with the toporouter, could you please send them to me to use as tests (privately is OK, if you don't want them public)? I've just started working on the code to handle existing traces and planes in the toporouter, and I'm going to need a range of boards for testing at some stage today.. It would really help if people sent some in, so I don't have to spend an hour or so scratching around the net for test cases.. Cheers, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter update?
John Griessen wrote: kai-martin knaak wrote: Anthony Blake wrote: greenlight --- I'd strongly suggest to invent a new word rather than take an existing buzzword. The term greenlight currently yields 1.5 Mio google hits. A greenlight router would be almost as invisible to internet searches as pcb ;-) Oh, it wouldn't be that bad. Pcb is the tool's category name as well as being a common term. Searching for greenlight router would narrow down just fine. I would have liked to use the name 'greenstone', which has special meaning for NZ.. it is a type of jade only found here. Unfortunately my uni supervisor has already used that name for a project: http://www.greenstone.org/ Maybe we could call it the greenstone router? Cheers, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Need boards for toporouter tests
Stefan Salewski wrote: Feel free to try my DSO board (fully routed) from http://www.ssalewski.de/DAD.html.en -- maybe a too big challenge? That took me about 500 hours for manually routing, some day your router will manage it in a few minutes. Would be great! Thanks.. thats a nice layout =) Probably a little too complex for the moment, but something to aim towards. Cheers, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter update?
Peter Clifton wrote: On Thu, 2010-03-18 at 11:14 -0500, John Griessen wrote: Anthony Blake wrote: On Thu, Mar 18, 2010 at 12:56 PM, Windell H. Oskay wind...@oskay.net wrote: Also, can anyone think of a new name for the toporouter? There is already a commercial tool called the 'toporouter', which I don't want us to be confused with. greenlight -- Despite being the least router-ish of these names, I really like this one. Hmm.. me too.. Since gEDA wasn't accepted into GSoC, I'm not going to be able to work on it as much as I would have liked unfortunately.. =( ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: toporouter update
Harry Eaton wrote: Can you guys keep this on the geda-dev list in future.. it is always fun to see how things are progressing. Certainly, if Anthony and I discuss anything now that GSoc is not to be. I'm not going to stop working on the toporouter (greenlight?) just because Google didn't fund us. If people keep hassling me, I'll probably find the time for small commits here and there.. e.g., most of my work last year was an answer to some scathing criticism from Harry.. I *had* to do something after that =) Cheers, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter Update
Harry Eaton wrote: I'm not going to stop working on the toporouter (greenlight?) just because Google didn't fund us. If people keep hassling me, I'll probably find the time for small commits here and there.. e.g., most of my work last year was an answer to some scathing criticism from Harry.. I *had* to do something after that =) Gosh, I was thinking about making a parody of your website comparing the two routers in pcb, where I would show test cases where boards had SMD parts on both sides and the toporouter couldn't route it but the autorouter could, then some with some existing hand-routing on the board, one with a ground plane going unused by the toporouter, etc. But I thought that would be mean so I didn't do it. (Even though I figured it would goad you in to fixing those problems). Haha, don't worry, I can handle it.. I'm sure I would have had a come back.. But yes, in retrospect the website is crap.. I would like to replace it with a script that automatically generates the website (including all the images and results) each time I change the algorithms. I do stand by my decision to spend more effort on single layer performance before implementing vias though. My single layer performance improved considerably, for example on Windell's MeggyJr board, the wiring was reduced by over 30 inches by some changes. Not only that, *many* bugs were eliminated as I worked on single layers only.. those bugs would have been much harder to fix if the situation were complicated with vias. I actually found it a little frustrating that I was simultaneously being told by some people to implement vias, but also to spend time stabilizing and fixing existing code.. I just couldn't please everybody! Seriously, I didn't think my criticisms were scathing, they were meant to be helpful. In any event, I'm still happy to give my blunt assessment and crazy ideas going forward. Sorry, scathing was the wrong word.. What I meant was the criticism was well targeted and straight to the point (because of your knowledge of the internals of autorouters), which was hugely helpful (even if I didn't agree.. it was great to talk about the issues). In the cases where I didn't agree, I felt I needed to prove it, and that was the motivation for most of my commits last year. Thanks Harry =) Cheers, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GSoC -- Not accepted :-(
On Fri, Mar 19, 2010 at 2:15 PM, kai-martin knaak k...@familieknaak.de wrote: If you're interested, here's the list of accepted groups: http://socghop.appspot.com/gsoc/program/accepted_orgs/google/gsoc2010 ... Facebook ... Mozilla ... Gentoo Not exactly organizations I'd expect to need funding ;-) Browsing through the accepted applications almost all project goals would would make its little contribution to the potential success of one of the major google products -- many of them provide apps or software infrastructure for smart phones. (Selenium, coreboot, thousend parsec, NUI Group, etc). Unfortunately, the HTC dream wasn't designed with gschem and pcb... A few of the accepted organizations seem a little odd.. I suspect someone just flicked through the pile of applications pulling out names they recognized.. There is even one accepted organization that seems like more of a feel good social club than an open source project.. I've been facepalming all morning. -- Anthony Blake ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter update?
On Fri, Mar 19, 2010 at 2:27 PM, kai-martin knaak k...@familieknaak.de wrote: So let's concentrate to the most blocking of all issues: If I got it right, these are the inability to deal with preexisting tracks and the missing way to confine the router to selected nets. If these issues were solved, even the router would already be valuable as an abbreviation during manual routing. The toporouter will already route a selection of nets if some nets are selected when the toporouter is invoked. But yes, if this worked with existing geometry it would be useful. Cheers, -- Anthony Blake ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter update?
On Fri, Mar 19, 2010 at 2:33 PM, kai-martin knaak k...@familieknaak.de wrote: Anthony Blake wrote: The toporouter will already route a selection of nets if some nets are selected when the toporouter is invoked. Nice! Also, it will only route on the currently visible layers. -- Anthony Blake ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter update?
Hi, On Wed, Mar 17, 2010 at 4:48 AM, Kai-Martin Knaak k...@familieknaak.de wrote: On Wed, 24 Feb 2010 09:10:29 -0500, Ethan Swint wrote: On 02/23/2010 06:46 PM, Anthony Blake wrote: Ok, then. Can you compile a list of tasks that need to be accomplished before the topo router is ready for general use? The smaler the individual tasks, the more likely they can be tackled by low time hackers like me... For sure. It would require some careful consideration though.. I'll get back to you within a week. Keep me in the loop, too. bump the topic up... Since this thread started, I've discussed continuing work on the toporouter with my Uni supervisors. They are OK with me taking time off from my PhD if the GSoC thing goes ahead. I would prefer to do most of the core work myself, rather than try and get others to implement my 'half baked' and untested ideas.. The idea of getting someone to implement something that I'm not even sure of myself doesn't seem right.. As for smaller individual tasks.. I was thinking that an abstraction layer for the autorouters might be a good idea. We now have 1.5 autorouters (very soon to be 2x complete autorouters), and an abstraction layer would help future work built on top of the autorouters, such as the auto-plow feature Harry Eaton mentioned, seamlessly switch between the underlying autorouters.. An abstraction layer would also be a good first step towards untangling the toporouter from PCB, and making it more of a general open source autorouter. Another small task, which would *really* help me, would be an automated testing framework for the autorouters. I would like to have some tool which I could throw a directory of unrouted boards at, and for each board it comes back with images of the output from the toporouter the autorouter, as well as performance results (wiring length, runtime etc). Someone also suggested switching out the absolute wiring length metric with sum of each nets wiring length to MST length ratio.. That would be a good small task to familiarize oneself with the toporouter autorouter code.. and the results would be very interesting if that metric is also used as the cost function in the net ordering. btw, if there are other little projects or features you would like to add.. I'm happy to help in anyway I can, including being available on IM/IRC to answer questions.. Also, can anyone think of a new name for the toporouter? There is already a commercial tool called the 'toporouter', which I don't want us to be confused with. Regards, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter update?
On Thu, Mar 18, 2010 at 12:56 PM, Windell H. Oskay wind...@oskay.net wrote: Also, can anyone think of a new name for the toporouter? There is already a commercial tool called the 'toporouter', which I don't want us to be confused with. How about Awesomerouter? :D Haha nice.. I used to route boards by hand, but then I became awesome instead. True story. -- Anthony Blake ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter update?
On Thu, Mar 18, 2010 at 1:24 PM, kai-martin knaak k...@familieknaak.de wrote: Anthony Blake wrote: btw, if there are other little projects or features you would like to add.. Last time I checked, there were some real show-stoppers. E.g, the topo router would choke on preexisting tracks. I'd rather see these major issues resolved than divert energy toward added features. Absolutely agree with you about fixing those show-stoppers first.. the problem is none of those issues (e.g., vias, existing geometry etc) are small tasks suitable for people new to the toporouter to take on. I would prefer to deal with those issues myself as part of the GSoC this year. That said, I can surely come up with loads of feature requests. All kinds of suggestions to the router, layers exclusively for specific signals, customizable preferred directions, design rules that depend on the net, ... ;-) Yup, those are the features I really want to get other people implementing, so I can spend my time working on core features like vias and existing traces.. Cheers, -- Anthony Blake ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter update?
On Thu, Mar 18, 2010 at 1:37 PM, Windell H. Oskay wind...@oskay.net wrote: Haha nice.. I used to route boards by hand, but then I became awesome instead. True story. tea - keyboard I suggest it because (1) it's awesome and (2) it's suggestive of 'autorouter. Back on topic now, we might get some good hints for future features from Toporouter (the commercial autorouter product). One of the ones that they tout is understanding logical equivalence of certain pins. You could further imagine a very advanced version of this that could select which slot of (say) a quad op-amp to use. I've already had a first stab at implementing that, in an effort to generate a good solution for DDR2-SDRAM - FPGA routing. It is very hard to do well, as the problem just gets even more NP-complete =) Since my first attempt year ago, I've learnt a few data mining/machine learning tricks, and I'm feeling much more confident about doing it *well* a second time around. btw, those toporouter guys are rather misleading with their results.. they show off pictures of boards which have been fixed up afterwards.. e.g., 20 mins of toporouter time, and 40 mins of hand editing for one of their boards. And while I'm on the subject of comparing autorouters.. I was looking at a Mentor license agreement the other day.. and I was shocked to see that they prohibit you from using it to compare results with other tools.. wtf.. Honestly, optimization beyond what's already there would be great for a future version, but I'm so craving just what I've seen so far. Thanks for your support! -- Anthony Blake ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter update?
John Griessen wrote: I guess the last thing the CAD companies want is a straight comparison. We might be able to setup a system where people can anonymously post results generated with commercial tools, sort of like how deepchip.com works. Who's going to mentor you for GSOC purposes? Since Harry Eaton has never been shy with lots of really good criticism and comments regarding the toporouter (off list), I asked if he would be interested a few weeks ago.. I hope Mentor or Cadence don't find out about you and make you an offer you can't refuse. I doubt we are even on their radar =) In any case, I'm still a student for the next while, which isn't going to change.. Cheers, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter update?
Kai-Martin Knaak wrote: On Tue, 23 Feb 2010 11:16:45 +1300, Anthony Blake wrote: I don't get a lot of time atm.. please jump in =) Ok, then. Can you compile a list of tasks that need to be accomplished before the topo router is ready for general use? The smaler the individual tasks, the more likely they can be tackled by low time hackers like me... For sure. It would require some careful consideration though.. I'll get back to you within a week. Cheers, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter update?
Ethan Swint wrote: The last update on the toporouter looks like it was last June. Any news since then, or is it waiting for me to jump in to the code? ;) It looks fantastic. I don't get a lot of time atm.. please jump in =) FWIW - I think a better metric of router performance (instead of total track length as used on the web page http://www.wand.net.nz/~amb33/toporouter/detour.html), would be a statistical aggregation of the ratio of the individual nets track length compared to the minimal point-to-point length (think rat's nest). Hmm.. yup probably =) -Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter update?
On Tue, Feb 23, 2010 at 12:18 PM, Larry Battraw lbatt...@gmail.com wrote: On Mon, Feb 22, 2010 at 5:16 PM, Anthony Blake [1]tony...@gmail.com wrote: Ethan Swint wrote: The last update on the toporouter looks like it was last June. Any news since then, or is it waiting for me to jump in to the code? ;) It looks fantastic. I don't get a lot of time atm.. please jump in =) Does anyone know how to turn on the detour optimization or is it on by default? It is on by default. At some point, for the purposes of comparison with earlier algorithm, there was a switch for it, but there isn't anymore. Regards, -- Anthony Blake ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: topo router for PCB
On Mon, Feb 22, 2010 at 11:39 AM, Larry Battraw lbatt...@gmail.com wrote: On Sun, Feb 21, 2010 at 1:32 PM, Stefan Salewski m...@ssalewski.de wrote: On Sat, 2010-02-20 at 22:20 -0500, Larry Battraw wrote: I had a quick question. I know there are several sparsely-documented plugins for PCB but I am trying to locate the one that makes the traces on the board look like they were laid out by hand the old-fashioned way with tape, resulting in curving, contoured traces instead of the standard auto-routed straight You may looking for the topological router, included in pcb 2009 snapshot. http://www.wand.net.nz/~amb33/toporouter/ That's it!! Thanks so much for your answer the puller and global puller were somewhat similar but I knew there had to be a way for it to autoroute that way. Do you know where the latest code for it can be found? The toporouter is contained in toporouter.c and DJ's puller is puller.c I believe. -- Anthony Blake ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: arcs in pcb
Mark Rages wrote: So I guess I need to change the Arc object to store the angles in floating-point and bump the file format version. Any objections? It looks like a fair amount of work, including the dark and foreboding puller.c. I'd be interested in how this pans out.. some time ago I was thinking of doing the same thing to fix a problem I was having with the toporouter, but the problem turned out to be a little more complex that I initially thought. You might want to check out the discussion on the geda-dev mailing list a few weeks ago. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: toporouter use question
DJ Delorie wrote: I was under impression it needed a board with no nets to start? I think this is still the case. I told Tony I'd add the needed functionality to one of the underlying libraries that he needs to pre-fill for existing traces, haven't had a chance to do it yet. Yes that is correct. Like DJ, I just haven't had the time.. I'm sure one of us will get to it eventually. I prioritized other stuff because DJ was going to implement padstacks as part of the linuxfund work, which would eliminate all the weird pins in pads workarounds. I did code the workarounds, and for some time boards with existing stuff worked.. but I cut it when I came across a bug and decided it wasn't worth the time to fix. -Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB: AutoRouter
Ineiev wrote: On 11/21/09, Stefan Salewski m...@ssalewski.de wrote: The new topological autorouter is available too, if compiled with --enable-toporouter option. Actually, it is enabled by default, but to tell the truth, I could never make it do any real work --- just pictures that I could not understand. Yeah sorry about that, the images were never intended to be used by anyone, they were only for debug. Any images it might have been generating would have been of whatever I was working on when it was committed. -Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB: AutoRouter
Stefan Salewski wrote: Is option --enable-toporouter-output only for debugging -- needs cairo, what does it? Huh? That is only referring to the debugging output.. if that option is not enabled, the router will still try and exported geometry back to PCB. I tried :toporouter(), but have seen in list archive something like :toporouter(h31, ...) Is there a documentation for the parameters? Those parameters are no longer current. There are a few new parameters, but they haven't yet been pushed through to the user interface. If you want to have a play with new parameters, hybrid_router() in toporouter.c would be a good place to start. From there you can change stuff like the thresholds for ROAR, number of iterations, termination conditions (effort), order and frequency of wiring optimization passes.. the results can sometimes be quite interesting even with minor modifications. Just be careful not to waste too much time tuning for a specific board. I guess if someone had some time it wouldn't be too hard to push all that stuff through to a dialog in PCB. -Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter Changes
Bill Gatliff wrote: On the pdhobbs board, the toprouted output shows a failed net at the top-left corner of the board that seems like a trivial case. Funny that it would miss that one--- and if it had found it, I think it could have completed at least one more net as well. Ahh yes.. I know why that happened. Since taking that shot, the algorithms have changed and the board no longer looks like that.. So next time I see that problem crop up I'll take care of it. I'd be curious to see how the total track lengths compare between your toporouter output and the geometric autorouter's, and what the statistical variation in lengths is between the individual tracks of the two boards. Does your output tend to find shorter paths but with occasional outliers, for example? The answers might be interesting to the RF and power guys, and might also help you automate the tests to see if toporouter changes improve the test case outputs. I've put up a new page (http://wand.net.nz/~amb33/toporouter/detour.html) showing some results of a simple adjustment to the detour optimizations, which includes wiring lengths for comparisons. A few boards such as LED and Meggy Jr have a few inches less wiring now. All boards I tried have improved wiring, and sometimes route more nets. The one exception was the laminator board which now fails 6 nets because early optimizations prevent some of the huge detours needed to finish with only 2 failures. Cheers, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter Changes
John Griessen wrote: Seems like the force-field approach just tweaks his better definition based on user input and not just the board geometrics. Right. To move in one direction from a point that repels is one way to code such a function. Another would be a straight line, and even better, a hand drawn line-segment line carving out regions of circuitry that should stay some distance away from eachother. Then rerun the program with wider DRC rules for the next region to pack against the first. and so on. I would prefer to implement this sort of functionality with topological directives or constraints, and avoid geometric constraints if possible. Cheers, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter Changes
Bob Paddock wrote: I think Harry may have implemented part of A* in the existing auto router. Yes, and I have used A* with two different toporouters. The difference is in the data structure which A* is used to find a path through. I've used RBS (rubberband sketch) and TCS (triangulation crossing sketch). Cheers, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter Changes
Ethan Swint wrote: I would prefer to implement this sort of functionality with topological directives or constraints, and avoid geometric constraints if possible. Yes, you've just described geometric constraints in great detail. :P As I understand it, topological constraints are something completely different! A little late to the discussion, but here's my $0.02: topological router is the only practical way of finding prospective routes between two points, but the geometric constraints are what really matter (provided a path is found!) to the performance of the circuit. So once a topological solution is provided, optimizing artificial potential or cost functions based on geometric and electromagnetic criteria would be the best way to route within a Voronoi cell, possibly with an edge from the corresponding Delaunay diagram as a starting candidate. (It looks like this may be the way it's done already?) If multiple paths are found, the 'best' path would be chosen by evaluating the cost functions. Hmm.. for example, if there is some EMC consideration which might lead a human to make a geometric constraint, wouldn't it be possible to define those EMC constraints so that the toporouter can make the same decisions the human did, with the aid of in-layout simulation? And cut out the middle man, so to speak. Cheers, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter Changes
Kai-Martin Knaak wrote: On Tue, 07 Jul 2009 09:52:11 -0500, John Griessen wrote: These kinds of topo constraint criteria sound good. I'd prefer to see the current usability issues fixed first. Most importantly: Let the toporouter cope with existing tracks and a way to do do only selected vias. I'll let you know when those are done. Unfortunately, some of the usability issues such as existing tracks, are not very interesting problems to work on. Cheers, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter Changes
John Griessen wrote: Hmm.. for example, if there is some EMC consideration which might lead a human to make a geometric constraint, wouldn't it be possible to define those EMC constraints so that the toporouter can make the same decisions the human did, with the aid of in-layout simulation? Doubtful. There's never just one consideration. There's typically 6. And three merge into a chip package or several related ones inside which we have no physical map. Then there's the other three... I don't doubt it is hard... For instance what to do with analog and digital grounds on some chips like A2Ds? any signal crossing a gap in ground plane is bad, yet we have AGND and DGND often. The answer(s) to this kind of question is(are) long. I don't think it would be that hard to constrain a signal to be always coupled to its return path. -Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter Changes
Anthony Blake wrote: John Griessen wrote: Hmm.. for example, if there is some EMC consideration which might lead a human to make a geometric constraint, wouldn't it be possible to define those EMC constraints so that the toporouter can make the same decisions the human did, with the aid of in-layout simulation? Doubtful. There's never just one consideration. There's typically 6. And three merge into a chip package or several related ones inside which we have no physical map. Then there's the other three... I don't doubt it is hard... For instance what to do with analog and digital grounds on some chips like A2Ds? any signal crossing a gap in ground plane is bad, yet we have AGND and DGND often. The answer(s) to this kind of question is(are) long. I don't think it would be that hard to constrain a signal to be always coupled to its return path. Actually, I meant it wouldn't be impossible. -Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter Updates
Bill Gatliff wrote: Amazing! Very, very exciting work. Thanks. I have a very small, mixed through-hole and smt design that I'd be happy to throw at you. About 70 components, the board is pretty sparse at 4x1.8--- but a much denser version is in the works. :) Sure, send them through. At some stage I'm going to build an automated test system so after any changes I can just set it running on a big set of boards. Anyway, let me know the best way to get this file to you, both the version I'm having built now and unrouted ones that you can play with. And whatever else you'd like. Either send it through as an attachment off list or send a link. Cheers, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: topo router
Hi, John Griessen wrote: Your router is looking great. Even without the vias it's really doing well, you must have spent some deep thought on making heuristics to decide what to do in jams! Thanks. At the moment, it isn't that smart about it.. it is a combination of two greedy algorithms. Sometime in the future I'll attempt some smarter approaches. As is, we could put in a trace to a via and re rerun and it will use the pre placed via as a starting point on the other layer, or would it be best to also put a stub of a trace on the desired layer to complete am missing route? I have done some simple stuff with existing vias and traces, but a lot of it requires a re-write of some code, which is just a work around for something DJ is planning to fix in the LF work anyway (padstacks). So I'm not in any hurry to deal with that. Cheers, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Toporouter Updates
Hi Everyone, I've recently updated the toporouter website with some screenshots showing the recent changes. http://www.wand.net.nz/~amb33/toporouter By the way, I could do with some more small to mid sized boards for testing if anyone wants to send one through. Cheers, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter Updates
Stefan Salewski wrote: One (maybe silly) question: It was my impression that Gerber format supports only line segments for traces, but your router use arbitrary shapes. If we use multiple line segments in the gerbers to build the traces then the file size should be very, very large? I just googled the gerber format, and it does support arcs. I'm hoping PCB does export arcs rather than arcs approximated with line segments. -Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter Updates
Eric Brombaugh wrote: BTW - I like the formatting of your web page. Something feels very familiar about it. ;) Well spotted =) Yes I had your cheap graphic LCD project page open when I decided to write up the toporouter stuff. I hope you don't mind! By the way, the LCD project was very cool. Will the board be available at some stage? Cheers, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: autorouter fixes and enhancements (Harry Eaton)
Kai-Martin Knaak wrote: Are these instructions valid for the new topological autorouter too? By the way, when is this autorouter going to hit the streets. Or at least be acessible for beta testing? It's been almost a year since the gSoC 2008. With this sub project I feel like having smelled the good food but then xnot allowed to actually taste it. Haha. No, the toporouter is a bit different. It has been taking a long time because I don't have a lot of spare time to spend on it, and I didn't want to spend a lot of time polishing and stabilizing something which works, but only has OK or not so great results. Instead I've been trying to build something which has great results before putting a lot of effort into polishing and optimizing. It is slowly getting there though. Here are some shots of Harry's LED board, with two different net ordering heuristics: http://wand.net.nz/~amb33/toporouter/LED.png http://wand.net.nz/~amb33/toporouter/LED-layerhint.png All nets were routed with no vias. After seeing Harry's results using no vias, I realized there was a problem in my net ordering which was resulting in some big detours. It's on the list of things to fix. I've also been playing with automatic length matching: http://wand.net.nz/~amb33/toporouter/matching.png - Now I have an idea about how to do it better. BTW, if anyone wants to help, adding the ability to remove and insert vertices in the GNU GTS CDT code after building the CDT would really help, and is out of the way of what I'm currently working on. This would enable via's to be added by the toporouter. At the moment, I'm in the middle of three changes which are going to fix a lot of problems, at which point it might be ready for some people to start playing with it, although it is still a way off from being usable. I'll keep everyone posted. Thanks to Harry, DJ Dan for helping out.. pointing out problems, testing some of the dodgey code, and with their suggestions. -Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: autorouter fixes and enhancements
Stefan Salewski wrote: I wonder if the PCB autorouter should be more closely bound to the gschem schematics. For example, in the schematics we may specify priority of nets (fast signals, power, ...), trace width or clearance for net segments. Maybe by attributes? I have no idea how commercial EDA software handles this. I think being able to define constraints as attributes in gschem as well as having a constraints editor that can be used from gschem and PCB would be the way to go. I'm not sure how the constraints editor would look though.. Dan pointed out the Specctra format, and the constraints editor should probably just be a front end for that. -Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: autorouter fixes and enhancements (Harry Eaton)
Kai-Martin Knaak wrote: [...] Any hints that let me actually use the router appreciated. Uhh, I don't think you could actually use it for anything useful, as it's pretty broken.. but if you still want to go ahead try :toporouter(). There is a 'h' parameter which makes it re-evaluate the netordering after a number of routes, so :toporouter(h20) would make it recompute a net ordering after 20 routes. To keep it out of a layergroup, use 'l' followed by the layergroup number. There are a few major problems which will be sorted out in the next commit: I have a whole lot of really bad code to try and make the layout more aesthetic by forcing traces to leave pads orthogonal to the edge. This messes with some of the clearance code and can sometimes result in impossible arcs. For example, to get the LED board to work, you must change the square pin of J3 to a round one. I'm removing this code. The way the curvilinear wiring is computed is overly complicated and breaks in all sorts of situations (lots of slithery triangles shows it up quite nicely, e.g., under a TQFP). In retrospect I'm embarrassed I tried to do it that way. I reckon the new code will shave over 2k lines too, its *way* simpler. There is a whole lot of dodgey clearance code duplicated all over the place, which gets messed up by the situation where another route is on both sides of some other route simultaneously (where a hairpin occurs), and also gets messed up by the special cased arcs coming out of pads. This is all being replaced by one set of functions which actually work. Good luck with that.. -Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: autorouter fixes and enhancements (Harry Eaton)
Kai-Martin Knaak wrote: I noticed, that the router did not introduce any via. Is this a missing feature, or do I have to through some switch? That hasn't been implemented yet. It requires the ability to insert and delete vertices in the CDT, while properly managing the data on the edges (without having to rebuild it). GNU GTS only allows dynamic insertion and deletion when it is not a CDT. Is there a way to make the toporouter do only some of the rats? If there are rats selected, it only routes those. -Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: autorouter fixes and enhancements (Harry Eaton)
Kai-Martin Knaak wrote: On Tue, 23 Jun 2009 10:20:40 +1200, Anthony Blake wrote: That hasn't been implemented yet. It requires the ability to insert and delete vertices in the CDT, while properly managing the data on the edges (without having to rebuild it). Ok. I didin't quite understand this when you mentioned it some posts ago. Sorry about the double post, Peters mail arrived as I was writing. Just in case you don't already know: The first time I select some rats, the toporouter works ok. However, if I select some more rats, the router crashes immediately after :toporouter(h20). That would be because the code for dealing with the conflicting constraints has been commented out. With existing routing and pads, the line exiting the pad and the pad edge cannot be inserted as constraints into a CDT. -Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: autorouter fixes and enhancements (Harry Eaton)
Kai-Martin Knaak wrote: That is, in its present state, the toporouter can only deal with boards from scratch. This is indeed a major constraint in terms of usefulness. At this point I'm not really worried about usefulness. BTW, what does CDT stand for? Constrained Delaunay Triangulation. Here is a dump of what a CDT looks like: http://wand.net.nz/~amb33/toporouter/cdt.png And here is a refined CDT from before I took out the ability to work with existing routing: http://wand.net.nz/~amb33/toporouter/refined-cdt.png BTW, that is DJ's SDRAM board. -Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
DJ Delorie wrote: Just for fun, I figured out how to make room to add traditional serpentines and a few other tricks, and have all the SDRAM traces within 7 mil of the CLK length (1.89). That looks really cool. Did you write some code to do that? -Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Bad news about gEDA's participation in GSoC 2009
Stefan Salewski wrote: On Fri, 2009-03-20 at 15:25 +, Kai-Martin Knaak wrote: By the way, when are the results of the 2008 projects expected to hit main stream testing? The autorouter looked quite promising. What about the project manager? I hope the topological autorouter is still alive? I've been pretty slack, and have not had much time to put into it, but I'm not going to stop working on it (please keep hassling me for progress!). In the last few months I made the switch to GNU GTS, and completed most of the code which will handle SMT constraints and so on. I want to add code to handle a few peculiar cases in a more general way (e.g., square pins inside pads with a collinear edge). There is a small bug in GTS which needs a fix for my code to compile. I sent a patch off to the maintainer over a month ago, but haven't heard anything back yet, so I'm not sure about what to do next there. I am really surprised that projects such as BZFlag were accepted to the GSoC and gEDA was not. -Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: auto routing with variable track width
DJ Delorie wrote: The netlist pcb loads has an option for specifying the route style for each net, but as far as I know, nothing actually creates or uses that option. I did mention this to Tony and he said the router *could* do it eventually, but not yet. Yes, it currently imports the route style for each net, but only uses the routing style in Settings. It would be fairly simple to complete this so it uses a nets route style if it is defined. -Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Free router support?
Stefan Salewski wrote: But maybe the new pcb router of Anthony Blake is the better, really free way. Yes, I'm still working on the autorouter. The algorithms in the autorouter I implemented for the summer of code give great solutions to some problems, but they really fail on others. So unfortunately, the autorouter isn't really usable on real world boards just yet. To address some of these issues, I'm trying some new algorithms. The main problem is the commitment to a certain topology early on, so I'm implementing a sort of tentative pre-route to guide the layer assignment and net ordering, before the actual routing. Unforuntately I haven't had much time in the last few weeks as I've been catching up with school work, finding a new house, and I've had the flu.. =( Hopefully I should have some results with the new algorithms in the next few weeks.. Cheers, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
