Re: gEDA-user: reasons for wikibook (was: plugins)
On Tue, Sep 13, 2011 at 8:59 AM, Markus Hitter m...@jump-ing.de wrote: Am 12.09.2011 um 16:43 schrieb DJ Delorie: 1. The easier it is to contribute, the more likely you are to be vandalized. Wikipedia has seen plenty of this problem. You need some method of authorizing trusted contributors and approving changes by others. As a heavy user of another technical wiki I can report this doesn't happen there. Wikipedia is a special thing in that matter, because it's a lot about opinions and politics. +1 I think it unlikely that a gEDA wiki would be targeted. I think wikimedia keeps a history so it may be trivial to restore an older version in the event someone does vandalise a page. If creating login is not a huge overhead then just disable anonymous edits - that way there is a degree of ownership of any changes to content. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: why some skip KiCAD and gEDA
On 11/09/2011 9:13 AM, Markus Hitter [1]m...@jump-ing.de wrote: But how close is gEDA here? To be honest, I think gEDA couldn't be farther away. It can't even agree on an equivalent GUI design for both major tools, gschem and pcb. Instead of doing something about that, lots of discussions about picky details on keyboard accelerators. Using a keyboard to do anything but writing text is a thing of the past, to start with. I think you will find that a pretty much all high end commercial CAD tools put a lot of effort into getting the keyboard accelerators right. Your concept of the keyboard being only for text has no basis in any CAD tool I have ever heard of. To get an idea of a fairly intuitive tool, have a look at Fritzing. Fritzing is great, so is intuitive design. I don't really understand why gEDA gets slammed on its UI so much. It is different, and like anything worth learning takes some effort. References 1. mailto:m...@jump-ing.de ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Electromagnetic bike
On Fri, Sep 9, 2011 at 11:16 AM, Rob Butts r.but...@gmail.com wrote: I have asked this question on this forum before but I never got a definitive answer so forgive me for asking it again. Does anyone know the theory behind the design of an electromagnetic bicycle. I thought it was bringing in magnetic fields close to a spinning metal disc but I'm not sure so I'm asking here. Are you referring perhaps to an electromagnet brake? TLDR version. A moving conductor in a magnetic field produces an electric current which produces an electromagnetic field which oposes the initial magnetic field resulting in a braking effect. More detailed version: http://www.lmgtfy.com/?q=electromagnetic+brakel=1 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Electromagnetic bike
I've not looked into this in great detail myself, but I believe this physics suggests this could be as simple as a spinning metal (conductive) disk with a permanent magnet at an adjustable distance to the spinning disk. It sounds like you understand how it works, but are perhaps looking for the catch? I don't believe there is one... Note this works only as brake - however if you want the same phenomenon to work as a motor you are looking at a squirrel cage motor (http://en.wikipedia.org/wiki/Induction_motor). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Electromagnetic bike
So if I have an electromagnetic and I hold it next to the spinning metal disc as I increase the intensity of the magnetic field the metal disc should be harder to spin? Yes. Define conductive? The eddy current breaks says non-ferromagnetic which means to me not having any magnetic properties like aluminum. Conducts electricity. Doesn't magnetise. Eg aluminium, copper. NOT iron. I'm strictly interested in generating the magnetic resistance. There is no catch. Generate away. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Solving the light/heavy symbol problem
This post kind of blew out a bit - TLDR version - I have a database idea that may be helpful in the pin swapping under discussion. The database would provide a device representation that captures *everything*. The database would help inform the pin swapping decision process rather than provide any gEDA plugin automation. It would be a standalone tool (at this stage). long version... I have some thoughts on this - as my original reason for starting a database for managing symbols and components was trying to come up with some sane method of capturing all possible configurations of an ARM chip while only displaying those that are currently in use in the schematic. I am not convinced that the schematic is the correct place to capture the full detail of all possible functional variations of a symbol, otherwise the component symbol becomes bloated or split into many many subcomponents either of which is likely to be unreadable or obfuscated. I want a schematic that describes succinctly what the design is intended to do. I *do* however need to have some representation somewhere that captures what a device is capable of so that I can implement the design as easily as possible - the idea is to not have to manually create a new component symbol by hand for each design variation. Pin/function swapping to enable better routing I think *has* to be a fairly user involved process - although I suppose in theory it may be somewhat possible to tie into an autorouter of some description... off topic - but would it be possible to have a second class of rats nest that is one link per function? - ie 1 point to point line to indicate a data bus path etc - or just colored rats-nest where common function nets are color coded/off topic I think DJs description of pin swapping makes sense - it seems like a more complete version of slotting. In the design I have been working on recently, I used a slotted resistor package. The process for changing which device was used was actually very easy with the 'import schematic option'. I had the schematic and layout open side by side - hover the mouse over the footprint to determine the net - then swap the slot in the schematic and hit import schematic - then 'O' in PCB to refresh the rats nest. This was quite pleased at the efficiency, and pushing the design flow from schematic to layout makes sense to me. I could be handy to be able to pull some schematic information from the PCB, however how you indicate the change to the net from pcb is beyond me. (I don't think laying copper would be correct - what if you had an accidental short somewhere?) More on the capturing of functional component information - my current plan is to create an entirely self sufficient database of component information. This would redefine the concept of a device to encompass all possible variations of the device. (noting that not all of them are required for a device description to be useful) Eg, * A logical device is made up of a number of logical pins (one pin may exist across a number of device packages/footprints) * A logical pin can be tied to a number of functions (eg UART-TX, SPI-MOSI) * A function can be grouped in a functional class (eg UART) * A physical-device is defined by joining a device, footprint and pinout * The pinout mapping allows a logical pin to be defined once and remapped across multiple packages - ie DIP, SOIC, QFN * Functional class awareness allows a package with multiples of the same function to be swapped with a degree of automation, including grouping pins that together form a functional group (ie a data or address bus, a serial port etc) * Pins and functions are somewhat separated - so it's easy to handle the situation where UART1_TX can be on pin 15, or pin 47. * This allows for the possibility of remapping a generic UART function between UART_1 and UART_2, along with the option of configuring UART_1 to use pins 15 and 16, or pins 47 and 48. This concept does not in any way replace DJs description of pin swapping - this is more about the capture of information than the mechanics of an implementation at this stage. I think I have the bulk of the database schema worked out, with a few minor details about some of the linkages to finalize - the harder part is providing a workable interface to the information. Particularly an efficient way to capture and describe the information in the first place, and then methods of manipulation and output. My initial thoughts are to have some of the information captured from a spreadsheet - this is most likely the easiest way to enter the data that is read from a datasheet - this can then be pulled into the database (similar to tragesym I suppose). The next issue is then view and manipulating the data - again my first
Re: gEDA-user: Task list for: Solving the light/heavy symbol problem
+1 python :) On Fri, May 27, 2011 at 4:52 AM, Andrew Poelstra [1]as...@sfu.ca wrote: On Thu, May 26, 2011 at 10:56:40AM -0400, DJ Delorie wrote: Opportunity to pick a more modern language, too. Something more os-agnostic, we've had issues with scheme on Windows before. I'm a Perl fan myself. Although Perl is probably better for string-handling, I think Python would be a better choice. It feels a lot more like a Lisp and quite a bit more well-known these days. It is also platform-agnostic, handles errors more cleanly, and is usually easier to read. Having said that, I have only a passing knowledge of both Perl and Python. -- Andrew Poelstra Email: asp11 at [2]sfu.ca OR apoelstra at [3]wpsoftware.net Web: [4]http://www.wpsoftware.net/andrew/ ___ geda-user mailing list [5]geda-user@moria.seul.org [6]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:as...@sfu.ca 2. http://sfu.ca/ 3. http://wpsoftware.net/ 4. http://www.wpsoftware.net/andrew/ 5. mailto:geda-user@moria.seul.org 6. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Task list for: Solving the light/heavy symbol problem
I don't claim to have any great level of experience in writing APIs at all - but I have already started some parts db stuff I would like to continue - put me down against some parts db work. cheers, Geoff On Wed, May 25, 2011 at 4:38 PM, DJ Delorie [1]d...@delorie.com wrote: The what phase seems to have drawn to a close, so now it's time for the how phase. How do we do the things we want to do? What tasks will lead us to the features we want? Here, in no particular order, are the tasks I think we need to undertake to get started (others will come up as we progress). If you were one of the proponents of one of these ideas, it's up to you to make sure it happens. Don't worry about pretty - just put together something that shows off the concept, so we can see it in action and evaluate it. We need to create a few small heavy symbol libraries. These are the self-contained starter libraries we talked about. Since these do not require any software changes, we should start on these right away. The purpose of these will be to give new users an opportunity to learn the editing tools without having to simultaneously learn how to make a library. These libraries should be packaged such that it's easy for the user to replace the standard library with them, and immediately be productive. gschem and pcb both need to be better at referencing multiple libraries of arbitrary depth. This includes a better way to manage the libraries (gui, config, query rules), enable/disable them, and browse them. This information should be sharable between tools, specifically, at least, between gschem, gnetlist, and pcb. While I do not wish to start a discussion about what kind of data should go in our metadata, we need tools to work with it. I think that breaks down to the following: * On the database end, design an API or two with which we talk to the data servers. Implement a few servers to see how it works. I've started some ideas at [2]http://www.delorie.com/pcb/component-dbs.html at the How is the database stored? text. * In gschem and pcb, we need a way to query the data servers in the attribute editors, in order to suggest attributes. * In gschem and pcb, be able to choose symbols/footprints based on metadata queries - use the metadata as a filter for the library dialog. * gnetlist needs the most work. It needs to be able to read a set of rules, query the database, and fill in additional attributes based on the rules. This need not be more than just fill in the blanks for now. gschem, pcb, and the sims need ways to query remote libraries. I suggest HTTP as the protocol, so we can use pretty much any web server out there. Gedasymbols is the obvious candidate, and I can work with whoever does this task to install any needed server-side logic. Someone needs to build a test library where the symbols have symbolic pin names, and the metadata maps those to physical pins in footprints. I suggest using the transistor problem as a basis for this library. Gnetlist will need to be modified to apply the mappings, although for this first step, there's no need to include pin or gate swapping information. Gschem and pcb need a way to swap variants on symbols and footprints, for example, switching between resistor-1 and resistor-2, or RESC1608N and RESC1608M. This depends on the metadata being available (above). Modify gschem's symbol chooser to allow filtering based on attributes within the symbol, not just the symbol name. I think it would be better if, at this point, people choose tasks and develop a quick prototype to (1) see if it works, (2) provide a basis for comparison against other potential solutions. Less talkie, more typie! ;-) Send a reply letting us know what you're working on, to make sure nothing gets left out. It's OK (in fact desirable) to have multiple people working on different solutions to the same tasks, so don't worry if someone else took your favorite. ___ geda-user mailing list [3]geda-user@moria.seul.org [4]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:d...@delorie.com 2. http://www.delorie.com/pcb/component-dbs.html 3. mailto:geda-user@moria.seul.org 4. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: IPC standard SMT footprints (0603, 0402 vs. RESC0603N etc.)
01005 (0402 metric) : 0.016 × 0.008 (0.4 mm × 0.2 mm) 0201 (0603 metric) : 0.024 × 0.012 (0.6 mm × 0.3 mm) 0402 (1005 metric) : 0.04 × 0.02 (1.0 mm × 0.5 mm) 0603 (1608 metric) : 0.063 × 0.031 (1.6 mm × 0.8 mm) 0805 (2013 metric) : 0.08 × 0.05 (2.0 mm × 1.25 mm) 1206 (3216 metric) : 0.126 × 0.063 (3.2 mm × 1.6 mm) This is a timely thread... I am in the process of finalizing my first serious gEDA pcb and building a small library of heavy symbols... I don't think I've double checked if I have 0603-metric or 0603-imperial footprints :P This also highlights why in many respects - regardless of the source I prefer to double-check all footprints... For myself I think I'll start naming the footprints with a metric or imperial tag of some description... M0603.fp and P0603.fp or something... (P for imPerial) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Solving the light/heavy symbol problem
I really don't want any *major* changes to the core workflow and UI TBH. The changes that would make this a more complete tool (for me anyway) are: PCB: - better control over polygons. Ie better awareness/ability to tie to nets, built in crosshatching (intstead of solid), and an option to hide all polygons without having to put them on a separate layer (this messes with DRC) (thin draw poly is cool though!) - footprints: native text capability, polygons, manual solder-mask, manual paste mask - A manual paste layer - Not sure about how to describe this, but I think it comes under the back-annotation editing of symbols... PCB is a little thin on the ground when it comes to editing elements on the fly (can you even edit text from the gui once placed?) gschem: not too many changes as I see it... - A footprint viewer - when selecting/setting a footprint it would be nice to have a preview (this could most likely be done as some sort of plugin) - A more complete channelisation/subcircuit/bus concept - basically just tie buses and subcircuits together (i think I may try and do this myself - i've asked about it before and got some useful feedback) Light vs heavy I think this has all been said but *my* summary is * you can never have *all* the heavy symbols - and chances are most of your heavy symbols will be useful as is to less than half gEDAs users. * purely light symbols leave beginners wondering why their projects don't compile out of the box solution (as discussed) - set up a default beginner/base library with a subset of the most commonly used components (defined by how much time and effort people are prepared to put in I guess) that is shipped - don't do anything to over complicate the heavyfication process - as it stands is fine :) I think tying gschem and pcb together more closely is a separate task - DJs database. I've been thinking of attempting to do this myself for some time - i'm as far along as writing a base schema to capture the core information... A functional component can take on many forms - the alignment of function to pin and whether the function is available is interdependent with the choice of footprint, functions can be remapped amongst pins (look at most ARM chips). Ideally one should be able to define a functional requirement in the schematic, swapping which pin provides said function in the final layout shouldn't be a major chore. I don't think this is an improvement that needs to be made in gschem - gschem is for schematic capture, which it does fine. Parts/symbol/component management is a separate task, so long as gschem doesn't hinder this process great - if it can include some plugins to make the task better integrated (such as a footprint preview) even better. A tool like gschem shouldn't be tied up trying to define and handle all variations of what any given person thinks makes up a symbol. It already has the capability to have arbitrary text attributes - that's enough. Just link the gschem symbol to the database/tool (separate program) that handles the various symbol permutations via a unique ID of some description or other... Anyway - the database idea has been looked at before, and from memory even implemented somewhat; so its nothing new. Geoff (If anyone is interested in the schema I've started [1]http://nixotic.com/partsdb.png) References 1. http://nixotic.com/partsdb.png ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Reinventing the wheel
We're going over old ground now... [1]http://www.delorie.com/pcb/component-dbs.html First, in gschem/gattrib, the the GUI has a way of querying the database for potential values of attributes - such as choosing variants, picking parts from official part lists, sticking to on-hand inventory, etc. Agreed on both counts. Default footprints would be misleading - having some choice and an easy way to select seems the most logical compromise. I have a bunch of symbols I've created myself where I put a footprint attribute in but set it TBD - because I know that depending on project I'll be switching between through hole and SMT... References 1. http://www.delorie.com/pcb/component-dbs.html ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Expansion of the footprint definition
I am sure there has been discussion around this in the past - but I am keen to know if there is any chance of PCBs understanding of what a footprint can contain being expanded in the near future? Primarily just two things I would really like... text and polygons... Is this something that requires a major refactor - or is it something that someone who is new to the pcb source may have a chance of looking at? cheers, Geoff ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: polystitch vs pcb+gl_experimental
I have been attempting to build polystitch.c against pcb+gl_experimental without much luck. Also had some issue against pcb git head... Has anyone else had any luck with polystitch.c building against recent versions? cheers, Geoff ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: polystitch vs pcb+gl_experimental
cheers, I'll look more closely at me setup On Thu, May 19, 2011 at 12:16 PM, DJ Delorie [1]d...@delorie.com wrote: I have been attempting to build polystitch.c against pcb+gl_experimental without much luck. Also had some issue against pcb git head... Has anyone else had any luck with polystitch.c building against recent versions? I build mine with head as of May 1. Let me rebuild and see what happens... ... seems to work OK ___ geda-user mailing list [2]geda-user@moria.seul.org [3]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:d...@delorie.com 2. mailto:geda-user@moria.seul.org 3. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Hiding individual layers of a layer-group
Hi folks, I've just started using separate layers so for my polygons so that I can hide them when necessary. This works fine until I group them with the appropriate layer. Ie - top and ground in a layer grouping - with ground being the layer I am putting polygons on. When I go to hide the ground layer - the top layer is also hidden. If I put them in separate groups this doesn't happen - however it seems that if I put them in separate groups the DRC breaks... is there any way around this?? cheers, Geoff ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hiding individual layers of a layer-group
I was already running pcb+gl - so that was a very fast fix. I didn't know about thin-draw :P I still think it would be handy to be able to turn of individual layers regardless of whether they are grouped though... On Thu, May 12, 2011 at 3:45 AM, Peter Clifton [1]pc...@cam.ac.uk wrote: On Wed, 2011-05-11 at 07:16 -0700, Colin D Bennett wrote: On Wed, 11 May 2011 13:12:55 +0100 Peter Clifton [2]pc...@cam.ac.uk wrote: On Wed, 2011-05-11 at 21:41 +1000, Geoff Swan wrote: Hi folks, I've just started using separate layers so for my polygons so that I can hide them when necessary. This works fine until I group them with the appropriate layer. Ie - top and ground in a layer grouping - with ground being the layer I am putting polygons on. When I go to hide the ground layer - the top layer is also hidden. If I put them in separate groups this doesn't happen - however it seems that if I put them in separate groups the DRC breaks... is there any way around this?? To achieve the visual clarity I guess you're looking for, switch to the pcb+gl branch and turn on thin draw polygons. Alternatively, thin draw polygons in git HEAD might still help you. The keyboard short-cut is Ctrl + Shift + P I do find that Thin Draw Polygons is helpful sometimes. However I also find many times that I would like to be able to show only specific layers (not whole layer groups). For instance, if I want to rip up all my ground plane polygons, I would like to be able to show only the ground plane layer (which is in the top layer's group) so that I can select all to select only the ground plane copper. How about some middle ground compromise - let it switch the layers off for the purposes of selection / rendering etc.., but still draw a faded (or de-saturated) version of their contents to aid not drawing geometry which would clash with other (hidden) sub-layers in the group. Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: [3]+44 (0)7729 980173 - (No signal in the lab!) Tel: [4]+44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list [5]geda-user@moria.seul.org [6]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:pc...@cam.ac.uk 2. mailto:pc...@cam.ac.uk 3. tel:%2B44%20%280%297729%20980173 4. tel:%2B44%20%280%291223%20748328 5. mailto:geda-user@moria.seul.org 6. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Segfault in pcb when exporting (latest branch)
pcjc2/pcb+gl_experimental confirmed (ubuntu 10.04 AMD64) On Sat, Apr 23, 2011 at 6:05 PM, Link [1]l...@penguindevelopment.org wrote: On 23/04/11 05:42, Andrew Poelstra wrote: With the current git HEAD, pcb segfaults as soon as you click 'png' in the export list. Can anyone confirm this isn't just me? Assuming it is an actual bug, I have filed a report and attached a patch at [2]https://bugs.launchpad.net/pcb/+bug/769336 Confirming. (Gentoo Linux, amd64.) ___ geda-user mailing list [3]geda-user@moria.seul.org [4]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:l...@penguindevelopment.org 2. https://bugs.launchpad.net/pcb/+bug/769336 3. mailto:geda-user@moria.seul.org 4. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Attribute Net (without pin assignment) - for Power and Port Symbols
I would advise a note of caution. What some people do not like is the visible :1 in schematics -- can we simple suppress that output for symbols with only one pin and digit 1 after the : That would be a not too dangerous patch, because it concerns only graphical output. +1 Special case seems wrong. This would be a much nicer alternative. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Footprint/symbol generating scripts + question
(having not seen this post) I created something similar yesterday in python. It only does SMD dual column footprints with an outline - and at the moment only takes mm. I'll push it to github or something like that if folks are interested. I assumed at the time that this sort of tool must get made all the time - but not having net access to search for one I thought I'd have a go at it too :P On Wed, Apr 6, 2011 at 9:22 PM, Stephan Boettcher [1]boettc...@physik.uni-kiel.de wrote: Richard Rasker [2]ras...@linetec.nl writes: One last question: the project I'm working on has several schematic pages, with several nets spanning multiple pages. For me, this is the first project of this size, and I wondered about one thing: Are there special symbols to indicate nets connected to other schematic pages? In the reference design on which this project is based (probably made in OrCAD), those nets have double arrows, but I can't find anything similar in gschem. So now I have quite a few nets ending in little red squares, giving the impression that they're open-ended. The actual connection is there, of course, so it's more of a cosmetic issue, but I have the feeling that this is not how it's supposed to look. You could draw a bus, and connect the nets to a bus. The bus could be labeled with the sheet the nets connect to. All this is just cosmetics, though. -- Stephan ___ geda-user mailing list [3]geda-user@moria.seul.org [4]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:boettc...@physik.uni-kiel.de 2. mailto:ras...@linetec.nl 3. mailto:geda-user@moria.seul.org 4. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: subcircuit definition and channelised design
Lots is possible, but I'm not sure how you would best go about it. gEDA's bus support is almost non-existent... it is just a graphical nicety, and relies upon named nets. (I vaguely recall that Altium buses can work like this too if you want) I haven't really used busses properly in Altium - as you described, I've primarily used them just as a graphical nicety while explicitly naming all the connected nets. There may have been a few cases where I named the bus and then connected nets were given the bus prefix, or something like that. But at the time I was just experimenting and didn't really need or find this sort of functionality added much value. (I imagine with a number of 32/64 bit busses something that removed the need to individually name nets would be handy though) In terms of the channelisation functionality my current thought is that I may be able to augment the gnetlist pcb backend to recognise something similar to a bus notation and recognise when a symbol/subcircuit needs to be replicated. (btw - I haven't yet started looking through the gnetlist backend sourcode or doco so if this sounds like something impossible - feel free to give me a heads up :) cheers, Geoff Swan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [PATCH] Drag without selection in gschem
I very much like the idea of this patch :) I'll have a go at testing it. On Tue, Mar 22, 2011 at 10:29 AM, Thomas Oldbury [1]toldb...@gmail.com wrote: I'd suggest making it an opt-out for people like me who like it as it is, but maybe I'll get used to it. On 21 March 2011 22:56, Peter Clifton [1][2]pc...@cam.ac.uk wrote: Could someone give this a test and come up with any counter-reasons why this attached patch is NOT a good idea? I vaguely recall a similar (or identical?) idea was discussed on the list recently? I was watching some students using gschem the other week, and noticed them struggling to move objects due to the fact they had to select them first. I wrote a patch which lets a drag action operate on whatever is under the mouse (selected or not). The user can override the mechanism and get a normal drag-selection box by holding shift when dragging. This also happens if the user drags on a blank area of the schematic. This seems to work here (in conjunction with some other cleanup I pushed to git HEAD). I'd appreciate a second pair of eyes on it though, as I just knocked it together quickly. Fwiw.. dragging of selected locked objects _does not_ work.. (never did as far as my brief skim of the code suggests.). I think we ought to fix that. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: [3]+44 (0)7729 980173 - (No signal in the lab!) Tel: [4]+44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list [2][5]geda-user@moria.seul.org [3][6]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:[7]pc...@cam.ac.uk 2. mailto:[8]geda-user@moria.seul.org 3. [9]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list [10]geda-user@moria.seul.org [11]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:toldb...@gmail.com 2. mailto:pc...@cam.ac.uk 3. tel:%2B44%20%280%297729%20980173 4. tel:%2B44%20%280%291223%20748328 5. mailto:geda-user@moria.seul.org 6. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 7. mailto:pc...@cam.ac.uk 8. mailto:geda-user@moria.seul.org 9. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 10. mailto:geda-user@moria.seul.org 11. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [PATCH] Drag without selection in gschem
I had a couple of issues with the patch process - I didn't bother checking which version I should have had (i'm using 1.7.0 20110116) but went and manually patched it myself. BTW - the first hunk worked fine - it was only the second one that failed. Otherwise it seems great, cheers :) On Tue, Mar 22, 2011 at 11:32 AM, Kai-Martin Knaak [1]k...@lilalaser.de wrote: Peter Clifton wrote: Could someone give this a test and come up with any counter-reasons why this attached patch is NOT a good idea? I vaguely recall a similar (or identical?) idea was discussed on the list recently? I like it. It is another step to gschem/pcb GUI similarity. ---)kaimartin(--- -- Kai-Martin Knaak Email: [2]k...@familieknaak.de Öffentlicher PGP-Schlüssel: [3]http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53 ___ geda-user mailing list [4]geda-user@moria.seul.org [5]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:k...@lilalaser.de 2. mailto:k...@familieknaak.de 3. http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53 4. mailto:geda-user@moria.seul.org 5. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Tragesym template problem.
Last time I saw this error it was because when I saved the file, all text fields were quoted. Ie - instead of version\t01 it read version\t01 or something along those lines. I fixed with vim... :1,$s/\//g Geoff ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: subcircuit definition and channelised design
I have been describing multiple channels in gschem by turning a subcircuit into a symbol that I can then add multiple times as required. This works well, however I have been wondering if it may be plausible to create a script or plugin that allows you to add the symbol once and then indicate the replication and connections through something like bus notation? Eg: I have a subcircuit with one control input. The micro that connects to the subcircuit is given netnames on the appropriate pins SS1, SS2, SS3, SS4. The control input pin on the subcircuit symbol is given the netname SS[1:4] The magic script/plugin is used to make sure that gsch2pcb/gnetlist knows that the subcircuit needs to be replicated 4 times with connections to the micro on SS1, SS2, SS3 and SS4. (This may sound familiar to folks who have used altium - I suspect I am ripping off their notation) I am relatively new to gEDA - so I thought I would find out if this is theoretically possible (or been done before) before I start trying to write my own script... cheers, Geoff Swan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Anyone using my gedasymbols?
Yes On Mon, Mar 14, 2011 at 12:14 PM, Kai-Martin Knaak [1]k...@lilalaser.de wrote: Hi. I am curious: Is anyone on the list using the footprints and/or symbols in my department of [2]gedasymbols.org? ---)kaimartin(--- -- Kai-Martin Knaak Email: [3]k...@familieknaak.de Öffentlicher PGP-Schlüssel: [4]http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53 ___ geda-user mailing list [5]geda-user@moria.seul.org [6]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:k...@lilalaser.de 2. http://gedasymbols.org/ 3. mailto:k...@familieknaak.de 4. http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53 5. mailto:geda-user@moria.seul.org 6. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem slots with different symbols
I have done something like this by using multiple symbols for a single device rather than slotting. From memory all that was required was to ensure the pinseq are correct and the symbols are given the same refdes. I'm sure someone will correct me if I have missed something :P On Tue, Feb 22, 2011 at 2:38 PM, Allan Hessenflow [1]allanh-g...@kallisti.com wrote: Is it possible to let gschem know two different symbols are the same type component so auto-slotting works? Alternatively, is there any way to hide some pins on some instances of a symbol? I always show power pins, and for those components where slotting makes sense, I'd like to be able to only show the power pins on one instance per package. At the moment I'm letting the power pins show on all slots and only connecting them up on one per package, which doesn't seem to cause any problems, but it doesn't meet my aesthetic requirements. allan -- Allan N. Hessenflow [2]all...@kallisti.com ___ geda-user mailing list [3]geda-user@moria.seul.org [4]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:allanh-g...@kallisti.com 2. mailto:all...@kallisti.com 3. mailto:geda-user@moria.seul.org 4. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Soldering iron tip turns black
Remember to always store your iron tips with a ball of solder on them, this helps prevent the tip from corroding in storage. Don't wipe the tip before putting it back in the holder, your wipes on the moist sponge should be when you take the tip out of the holder. Again the molten solder on the tip helps keep the tip from oxidizing while hot. Steve I can't stress how important this is!! Seriously, I have seen soldering iron tips last through heavy usage spending most of the day on - so long as the tip *always* had solder on it. The worst possible thing you can do is to clean the tip on the sponge and then put it back on the stand to sit heating away. I often put fresh solder on the tip before putting it back on the stand to ensure that the tip is completely covered while it is on - and I go to even more trouble to make sure there is plenty of solder covering it before turning the iron off. Before I learned this I had exactly the same trouble you describe. A tip would only last being used a few times before being exactly as you describe. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem: directly connecting two nets?
I like the multiple names solution. I hadn't run into this issue until I came across gEDA symbols with hardcoded nets. Not a big issue, I tend to modify symbols now on a per project basis - so the need to have two net names for a single wire is much reduced. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GPLv3 question
So just to clarify - if you distribute an embedded device that runs a GPLv3 binary; to comply with the GPLv3 you must not only provide the source, but also a hardware-programmer/uploader? I suppose in most cases this isn't necessarily a huge issue - where firmware upgrade capability is built into the device (such as most routers, and development style boards). I play with the Atmel AVR range a fair bit and typically only create boards that require a separate hardware programmer to upload firmware. In this case to distribute such a board with GPLv3 firmware I would technically need to provide the in-circuit-programmer with the board and source. I could imagine in some cases the uC may be programmed *before* it is soldered in place and no mechanism provided by the circuit for firmware modification. In this case I presume you would not be able to make use of GPLv3 firmware - as no mechinism is readily available to modify the firmware... I know these are perhaps somewhat unrealistic scenarios - but if I have understood them correctly it certainly seems that GPLv3 could have been a little more embedded platform friendly. cheers, Geoff On Thu, Oct 7, 2010 at 7:01 AM, DJ Delorie d...@delorie.com wrote: You don't need to deliver *any* source code unless it is requested by the user. In the case of an embedded product, with GPLv3, the *only* way to not include the source is to include the written offer, which opens you up for a DDNS. You can only use the web download option if the binary is itself web downloaded. Also - for embedded products, to comply with GPLv3 you must enable the user to change the code *in the device*. Just providing source code isn't enough unless they can use it too. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GPLv3 question
ah, cheers - really appreciate the clarification. Geof On Thu, Oct 7, 2010 at 9:30 AM, asom...@gmail.com wrote: No. GPLv3 says that it must be _possible_ for the user to update his GPLed code, but it need not be easy. You can even ship GPLv3 code in an OTP chip. Basically, just don't use DRM to prevent the user from changing his code when he could otherwise. The intent is to prevent GPLed code from being locked down, trusted computing style. On Wed, Oct 6, 2010 at 4:20 PM, Geoff Swan shinobi.j...@gmail.com wrote: So just to clarify - if you distribute an embedded device that runs a GPLv3 binary; to comply with the GPLv3 you must not only provide the source, but also a hardware-programmer/uploader? I suppose in most cases this isn't necessarily a huge issue - where firmware upgrade capability is built into the device (such as most routers, and development style boards). I play with the Atmel AVR range a fair bit and typically only create boards that require a separate hardware programmer to upload firmware. In this case to distribute such a board with GPLv3 firmware I would technically need to provide the in-circuit-programmer with the board and source. I could imagine in some cases the uC may be programmed *before* it is soldered in place and no mechanism provided by the circuit for firmware modification. In this case I presume you would not be able to make use of GPLv3 firmware - as no mechinism is readily available to modify the firmware... I know these are perhaps somewhat unrealistic scenarios - but if I have understood them correctly it certainly seems that GPLv3 could have been a little more embedded platform friendly. cheers, Geoff On Thu, Oct 7, 2010 at 7:01 AM, DJ Delorie d...@delorie.com wrote: You don't need to deliver *any* source code unless it is requested by the user. In the case of an embedded product, with GPLv3, the *only* way to not include the source is to include the written offer, which opens you up for a DDNS. You can only use the web download option if the binary is itself web downloaded. Also - for embedded products, to comply with GPLv3 you must enable the user to change the code *in the device*. Just providing source code isn't enough unless they can use it too. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: QFN soldering
For quick breadboarding of an accelerometer I've deadbug soldered one successfully. Just superglued it upside down and soldered directly to the pads with very thin wire.. On Mon, Sep 13, 2010 at 12:04 PM, DJ Delorie d...@delorie.com wrote: does anyone have experience with this package? Just did one today. I want to know if they are hard to work with. Harder than a QFP, but not impossible for home-fab. Pen flux the bottom of the chip before placing it on the paste - I wish I'd remember this more reliably :-) The exposed pad underneath is a problem for hand soldering - but maybe could be left unsoldered for prototypes. Depends on the chip. Some require an electrical connection, it may be the only ground for example. Maybe just place some solder paste under there ? If you have to solder an exposed pad manually, you have (IMHO) exactly two choices: 1. Put a via right under it, with a drill big enough to get your soldering iron in there to solder it from the back side. Keep in mind the big thermal sink this will be; your smallest iron tip might not be up to the task. Obviously, do this after soldering the edge pads :-) 2. Use a solder paste stencil of some sort and reflow it (heatgun, oven, hotplate). I make QFN stencils out of alumimum foil and UV film, I've done it with toner and thin brass too, and once with brass and a dremel drill press. But you can't just squeeze paste out of a tube and expect it to work - too little won't conduct and too much keeps the other pins from touching. Note that for home-etched boards, #1 requires a tiny wire, else you don't really have anything to solder to. Surface tension will keep the obvious idea from working :-) If the pcb pads are long enough, is it feasible to solder to the edge of the chip instead of getting it underneath the device? If you use #1 above, and the pads extend contiguously up the edges of the chip and not just on the bottom, yes. Use LOTS of pen flux and make sure the pcb's pads extend out far enough for a thermal connection with your iron. I've done this before, and the flux/iron trick can be used to fix reflow problems too. Note: some QFNs have copper on the side which is *not* contiguous with the pads on the bottom. The FT232RQ is such a chip. You have to reflow these, although the flux/iron trick can still repair them once there's *some* solder under the chip. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: analog/digital partitioning
I came across this ([1]http://www.tentlabs.com/InfoSupport/page35/files/Supply_decoupling. pdf) some time ago. I would be interested to hear peoples thoughts as there are clearly many differing views on correct grounding and supply decoupling. The article certainly made a lot of sense to me and until proven otherwise it's the approach I follow. I understand why multiple ground planes seem attractive with the idea of somehow partitioning different current flows - but I have yet to see an implementation where this worked as intended. I have debugged circuits where there were as many as 4 separate ground planes and this certainly did not help the noise problems. I recognise that this is not enough to rule out the approach - just that the person designing didn't understand what they were doing. If someone has a design/layout that has *correctly* implemented split grounds etc I would be keen to have a look. Better yet if the design approach can be explained. This is one of those elements of practical electronic design that seems to be glossed over as assumed knowledge, and not necessarily very well taught. regards, Geoff On Fri, Jul 23, 2010 at 3:56 AM, myjunk stuff [2]carzr...@optonline.net wrote: On Thu, Jul 22, 2010 at 12:37 PM, DJ Delorie wrote: One idea to consider is to start with a solid plane, and cut slots around the sensitive analog parts, like big C shaped moats, squares open on one side. You retain the big ground plane conductivity, but you prevent stray currents from using your analog area as a short-cut. Each analog chunk can have it's own moat this way, too. If they're near the edge, just cut a thin slot from the edge in. Hmmm... this reminds me of the cubicle I used to work in :-P Yeah, Dilbert calls them 'anti-productivity pods' :D Seriously though, I like your idea except that sloted planes are generally frowned upon in the SI world - there's an opportunity for eddy currents to flow around the slot, and that will radiate. As long as no signals cross the slots on any other layers, maybe this is ok. ___ geda-user mailing list [3]geda-u...@moria.seul.org [4]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. http://www.tentlabs.com/InfoSupport/page35/files/Supply_decoupling.pdf 2. mailto:carzr...@optonline.net 3. mailto:geda-user@moria.seul.org 4. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Use of Alt+Mouse1
Bahahhahah! No. :P Not referring to you at all. My response was targeted at timecop. Apologies if it my aim was off... *I* am?? -Dave On 6/15/10 11:38 PM, [1]shinobi.j...@gmail.com wrote: Wow. You're really looking to start arguments Sent via BlackBerry® from Vodafone References 1. mailto:shinobi.j...@gmail.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Database on symbols, footprints and other (was Re: gattrib)
Perhaps that's where the pain is, but customizing symbols takes little time, so endure the brief pain and get on with it. You can't avoid it. Even if you have a heavy symbol from somebody else's library, you have to check it carefully, and that's almost as much work as customizing. My heavy symbols won't fit your needs, and vice-versa. This problem exists even in the big $$ commercial EDA tools. Symbol libraries simply don't work the way you wish they would. Too many possibilities... One company I worked for had a separate symbol for every single part. It was a 1-1 between schematic symbol and physical device. This meant that you could have multiple 10k resistors, even multiple 10k 0.1W 0805 resistors if the part was sourced from a few different manufacturers and ended up recorded as such in our CML. The actual process of creating such parts was not too arduous as it was usually a case of copy a similar part and change the necessary attributes. This was using Altium as the end to end EDA. It is interesting to note that despite an expensive, highly integrated schematic capture, parts library and pcb layout software that the same issues of component/symbol replication and redundancy exist. Although despite the proliferation of symbols in this case it did actually work ok. There isn't a magic bullet that will fix these issues. By having as much as possible light symbols that are easily modified, a public repository of customised heavier symbols this provides people with options. Perhaps in the hobby market having a set of predifined heavy symbols would be attractive however this really only suits those people who for whatever reason are not inclined to thoroughly check the symbol against their component and intended application. In these cases an 0805 resistor has no variants. This however is not the case for a design that goes through many iterations or has a particularly stringent set of design rules. Symbols need to be customised. Often on a project by project basis. All that can be done is to make this process easier where possible. regards, Geoff ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Microwave simulation
Hi, I am very interested to find out what you choose to use for this sort of analysis. I have played a bit with qucs and agree that's a good place to start. Please post back your findings! Geoff On Fri, Apr 30, 2010 at 6:08 AM, al davis [1]ad...@freeelectron.net wrote: On Thursday 29 April 2010, [2]ignacio.dieg...@estumail.ucm.es wrote: how can i perform scattering S-parameter analysis with gEDA? Can i create a model from a s2p (touchstone) file model? Nothing with gEDA that does it directly and is ready to go. Your best bet is probably Qucs. It's GUI driven, and focuses on RF. It also does a good job at the beginner level in general. ___ geda-user mailing list [3]geda-u...@moria.seul.org [4]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:ad...@freeelectron.net 2. mailto:ignacio.dieg...@estumail.ucm.es 3. mailto:geda-user@moria.seul.org 4. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: A little puzzled about the purpose of gschem
Most tools require some preliminary investment in terms of setting up libraries to the satisfaction of the user, plus general familiarisation. I think you will find you only need to modify your symbol once to include the appropriate SPICE directives. If you save this symbol you can then reuse it (not trying to make you suck eggs here but this argument seems stalled to the point of stating the obvious). The purpose of gschem does not include containing a library of symbols that include all possible spice and pcb footprint information. gEDA includes gattrib to ease the process of customising symbols - this is not the only method of adding/editing attributes though. Comparing gEDA with LTSpice is a bit odd once you understand the purpose of gEDA. LTSpice by definition has all the SPICE information for all its library components - but I'll warrent it has very little information about component footprints. gEDA is much more powerful and versatile than LTSpice but does require you to do a bit of manual work to begin with. There is discussion about creating a database separate to gschem that may in the future provide SPICE symbol data for standard components. Depending on how this is integrated into the workflow, perhaps this would ease your concerns. Not much help at this stage though... All the best, Geoff ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Idea/suggestion for improving the gschem GUI
Remember, the bare hardware without any software at all has the greatest potential. Every line of code added to the software system takes away from that potential. This is necessary, of course. You have the hardware for specific purposes, and the software serves these. But one should not ignore the cost in lost capability. Sorry, this to me is the most surreal argument I have come across for a while. This hardware capability that is suggested reduced by every line of code added by the programmer is certainly not intrinsic to the hardware. The capability comes from the programmer. This argument seems similar to suggesting that somehow the canvas that Leonardo da Vinci painted the Mona Lisa on contained the capability rather than da Vinci. I agree with advocacy for well factored code, and agree that it often seems that programmers are generating a glut of code, rather than thinking ahead and producing less lines but of better written work. But better that we have poor code with *some* functionality than hardware that has infinit potential, zero lost capability and no functionality whatsoever. As someone who often falls into the trap of not doing something at all because I don't feel I have the time or capability to do a job to a percieved high standard; I would warn against arguments like these because often just getting some sort of functionality is better than nothing at all. I presume the real concern here is that gEDA will lose capability by people adding features or functionality that restrict existing capability or similar. This perhaps is a valid concern. I enjoy reading this list because I am constantly coming across people using gEDA in such a way that capability of the gEDA suite that I had no idea was there is revealed. I think one of the PR problems gEDA has is that on the surface it often does not appear capable (but ongoing changes to the wiki and website are helping greatly in this respect). Perhaps as more people become aware of the capability of gEDA and how to leverage it, arguments about additional features etc will become less frequent. Geoff PS I hope I do not cause offence with my 2 cents in this argument. I am simply doing my best to disagree respectfully. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Symbol creation
One thing, I made it by copying the symbol for a triac. I did not pay careful attention to pin numbering. Am I going to regret that if I ever decide to do a layout / make a PCB? I guess that depends if you got the numbering wrong :P ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB Realign Grid
Never used pcb View - Align Grid. What may be the intended function? My guess: If you realign grid, all other components will become off grid. What I did: Align the new component to the grid, by grabbing its center or a single pin. For aligning a single pin it may be necessary/helpful activating Settings/Orthogonal Moves. I use the align grid for components that are not based around metric spacings or vice versa. In this case the first pin is aligned, but every pin thereafter is increasingly off grid. I like to run a fairly course grid when doing the bulk of my layout - I find that I can place and align things fairly quickly. However this hinges on being able to re-align the grid to different pins/pads so that I can for example put a via down that is exactly perpendicular to the pad. I can confirm, that realign grid does not do anything useful with the default configuration of pcb (GTK-GUI). However, with the lesstif GUI realign grid works as advertised in section 3.1.2 of the pcb manual: When choosing the new align point, the crosshair still locks to the old grid, but the cursor points to the new grid point. Cheers, I will have a bit of a play with the lesstif GUI. I had thought that the locking to grid may have been an issue - but I had hoped that would be overridden by the fact that the cross-hair was snapping to the pin/pad. I was also careful to ensure the curser was at the same point, so in theory either returning the cross-hair or the curser location should have resulted in a change. thanks heaps for the responses, Geoff ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PCB Realign Grid
I am having some trouble with pcb View - Align Grid. I am trying to use it to align the snap grid to a component pin. However it is not having any effect. I have tried various permutations of adjusting grid size and units - turning snap to pin on and off and anything else that I thought may potentially have an impact. I also tried closing and re-opening and starting a new layout adding a single footprint then trying to realign to that. Perhaps I am misunderstanding how Align Pin is intended to function. cheers, Geoff (I am using the pcjc2 -gl before pours branch with the polygon.c #define adjustment and the latest toporouter.c updates) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: toporouter update
+1 *hassle* (i really like toporouter :) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: On integrating simulator in gschem
I've seen commercial tools that have some predefined grids like rectangular, polar, smith but so far none have taken it to the next level of letting you add custom ones or the custom readout. Just in case you missed it - qucs has a number of plotting outputs including a Smith chart. I don't recall how good it is in terms of the interactivity with datapoints on the various graphs. Geoff ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: NE 555 and simulation issue
Seriously - simulating for things like this is not going to be the best way to design circuits.. physical variation between parts, and discrepancies between the model and reality, plus limited choices of real-world resistor values will mean it is pretty pointless trying to get any more accurate than what I've just calculated above. It has been my experience that circuit modeling tools although useful are not able to negate the need to understand the low level principles of the underlying circuit. The better you understand the physics of what is going on the more value you will get from your circuit modelling. All the best, Geoff. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: TO-92 Best Practices
What's considered Best Practices for TO-92 packages? Redesign with SOT-23. Easier to solder, faster than stuffing TO-92. +1 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: TO-92 Best Practices
Ignoring the response(s) from timecop, I don't believe the suggestion to try sot-23 was intended to be either elitist or unhelpful. *if* the option to use a different footprint is available then in many cases there is a great deal of advantage to using the sot-23 layout. If the work is being done by someone familiar with the pointy end of a soldering iron then it is as Mark points out potentially faster and easier to populate. I concede that in Windell's scenario that through hole components are much better for beginners rendering the suggestion moot, likewise if the part is not available or usable due to some other constraint. I hate it when you ask for help with one thing, and people suggest you do something else. Without a lot of background information as to why a job *has* to be done a particular way there is sometimes value in trying a different approach. Although because it doesn't answer the original question the suggestion is not always helpful... oh well... ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
don't even consider ordering boards without loading up the photoplot files into something like gerbv and doing some sanity checks. This advice applies to a design done with any layout tool and not just pcb. A minimal list would be: - From 20,000 feet, does each layer look right or are there glaring errors like a big missing chunk of a ground plane. - On your plane layer(s), make sure that you see some pins/vias that go through the plane *without* connecting. Now make sure you see some that *do* connect. Yes, I have seen a case where someone (not me) ordered a board that had exactly 0 connections to the ground plane. All thermals were missing. Didn't work so well. As another interesting aside - not likely to happen if you're using gEDA - a tech in the company I work for sent off a pcb design in the raw Altium pcb format (ie - not the generated gerb files). This was a not uncommon practice as Altium was considered *industry standard* and every pcb fab house we deal with has a copy. In this case however the fab house opened the designs in a slightly older version than what the files were generated in. AFTER the boards were fabbed AND populated it was discovered that due to the difference in version a whole bunch of nets had been fused to various power planes. The whole thing was fubar. Expensively fubar. The pcb fab house were not at fault as we hadn't specified which version of Altium had been used etc etc. There are a multitude of serious process errors involved in how the build was handled... if you follow what has been discussed so far I don't think you will have the same problems. Geoff ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: analog/code co-simulation and schematics and netlists for silicon
I have daydreamed about the possibility of linking gEDA with qucs and simavr/gdb for example. To be able to create a circuit layout and perform harmonic ballance simulation combined with microcontroller code simulation... Oh, and while I daydream, an integrated tool for doing FEM analysis the pcb design to improve RF circuit layout. I am only new to gEDA so forgive me if I some of this is already possible.. From the little I have seen getting the circuit information out of gEDA must be fairly straight forward - it is getting the other tools to play nicely that would be tricky. This is something that I certainly would like to look into. Geoff Australia On Wed, Feb 24, 2010 at 4:49 AM, John Griessen j...@ecosensory.com wrote: al davis wrote: I proposed a translator system, using an intermediate language, to translate both ways between schematic, layout, and simulation. It needs to happen. I've got a phone call to Reid Wenders of Triad scheduled this PM. Anyone have any ideas you'd like mentioned to him? Questions I should ask? I'm just planning on telling him the status of verilog-ams backend of gnetlist and that it can run some simulations from a netlist -- the way it needs to be for many chip design/verification work flows. Just in case there's any development money or new developers available. Reference: http://www.edn.com/article/CA6670945.html “We have been working with Keil to simulate mixed-signal peripherals. But, eventually, we are going to need a full analog/mixed-signal simulator on the desktop—something that can pull together Verilog, Spice, and software simulations on the desktop for a low price,” he says. “We are still searching.” Reid Wenders EDN, 7/23/2009 John Griessen Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: let's play guess the netlist with gsch2pcb!
On Thu, Feb 18, 2010 at 8:59 AM, Steven Michalske smichal...@gmail.com wrote: here is what i got V3 R1-1 V5 R1-2 with gsch2pcb --version gsch2pcb 1.6 Ditto. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: let's play guess the netlist with gsch2pcb!
Please run gschlas -e filename.sch and post the result to the list.
Thanks,
cat untitled.sch~
v 20090328 2
C 4 4 0 0 0 title-B.sym
C 47800 46400 1 0 0 resistor-1.sym
{
T 48100 46800 5 10 0 0 0 0 1
device=RESISTOR
T 48000 46700 5 10 1 1 0 0 1
refdes=R1
T 47600 46200 5 10 1 0 0 0 1
footprint=0805
}
C 47300 46800 1 0 0 generic-power.sym
{
T 47500 47050 5 10 1 1 0 3 1
net=V3:1
}
C 48800 46800 1 0 0 generic-power.sym
{
T 49000 47050 5 10 1 1 0 3 1
net=V5:1
}
N 47500 46800 47500 46500 4
N 47500 46500 47800 46500 4
N 48700 46500 49000 46500 4
N 49000 46500 49000 46800 4
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