Re: gEDA-user: sharing presentation materials for gEDA talks
On 29/07/09 13:22, John Luciani wrote: There is a video of Stuart's gEDA presentation at [1]http://tinyurl.com/bbt2rc This was from Ignite Boston, Feb 2009. (* jcl *) Thanks John, Already had that video in my archives, any more sources or hints would be very welcome. Best regards, Jelle ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Outsourcing PCB layout
Michael Sokolov wrote: Hello fellow gEDA/PCB users, I hope this post is not too off-topic/inappropriate for this list. I have an open source hardware design (an SDSL hacking board) that's getting close to entering the layout phase, and I will soon need to hire someone to do the PCB layout. (I have to outsource it because it's a task well outside my skills range.) Right now I'm just looking for a very rough guess order-of-magnitude estimate of how much this is going to cost me, so that I can tell whether I can foot that bill on my own or if I'll need to procure some sponsorship before this project can proceed. It's a totally non- commercial open source hardware design, I share the design freely with the world and I'll do the same with the PCB and Gerber files which I'll be paying someone to create, and if I do make and sell any physical hardware units, I'll sell them for the cost of production without any profit margin. If anyone here does PCB layouts for hire, I would appreciate it if you could take a quick look at my summary below and give me a rough approximate estimate of how much you would charge to do this layout. I would prefer for it to be done in PCB so that the resulting product will be in an open source format, but nonetheless my main overriding concern is cost, so in the admittedly unlikely case that person A offers to do it in PCB, person B offers to do it in some proprietary format and person B charges significantly less than person A, I'll have to go with person B - but again I think that scenario is very unlikely because I would imagine that those into proprietary tools are likely to be more commercially-minded, be less friendly to non-profit hobbyist open source projects and charge more. Summary of the board design that needs to be laid out: * Schematics: 10 B-size sheets; the circuit complexity should be roughly equal to that of an average DSL modem of the older generation that hasn't been shrunk down to one chip. * Estimated board size: I would like to fit it into a 130x165 mm 6 layer PCB if possible (again matching the average DSL modem). * No BGAs, 3 QFPs, the rest is mostly SOICs, TSOPs and SMT discretes, very few TH parts. * MC68302 microprocessor (QFP) with 20 address lines and 16 data lines wired, non-multiplexed; these buses need to go to two 8 bit wide SRAM chips, two 8 bit wide flash chips (covering the 16 bit wide data bus), the SDSL transceiver chip (only 8 address lines and 8 data lines) and an FPGA (13 address lines, all 16 data lines). * A lot of synchronous serial data and clock signals for the SDSL data path, including 4 muxes. * Mostly digital, but there is a small analog section between the SDSL transceiver chip and the jack. * No RF, the fastest signals would be the M68K bus which I may want to run at up to 25 MHz. Additional documentation: Project home page: http://ifctfvax.Harhan.ORG/OpenSDSL/ Schematics as they stand currently: http://ifctfvax.Harhan.ORG/OpenSDSL/OSDCU/OSDCU_schem.pdf http://ifctfvax.Harhan.ORG/OpenSDSL/OSDCU/OSDCU_schem.ps The design is done in uEDA, my own offshoot of gEDA which I'm in the process of polishing up for release. I don't expect the person hired to do the PCB layout to mess with uEDA, but I can export the netlist in the PCB format as well as a bundle of PCB elements for all components. Design spec (very detailed): http://ifctfvax.Harhan.ORG/OpenSDSL/OSDCU/hwdesign.txt That's all I have for now. I hope someone is willing to do the PCB layout for a price I can afford. :-) Nice project and thanks for the offering to hire developers that use free software development tools. I think this is an important step towards a more complete free software culture. I can offer you my services to route the PCB layout. The only problem is I will be available starting from the end of August 2009 before that I can not free the time. Also I live in an European country and do this work for a living so I have to charge a hour rate of around 40 euro to make enough for food and shelter. I think it will be around a week of work. Best regards, Jelle de Jong ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: good books about footprint and land patterns
Duncan Drennan wrote: What are good books that explain how to create good save footprints from datasheet specs. I am searching for best practices, math rules and so forts. IPC-7531A, http://portal.ipc.org/Purchase/ProductDetail.aspx?Product_code=81B562C1-B8F8-DB11-8A6A-005056875B22 If I buy this document and let somebody make software around it, released under GPLv3 and developed in community style will this be possible and legal? What are the alternatives? Would it be realist to develop a open standard for the creation and data storage for footprints that will be accepted by all open EDA tools, like gEDA, pcb, KiCad etcetra? Best regards, Jelle ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: good books about footprint and land patterns
Hello everybody, What are good books that explain how to create good save footprints from datasheet specs. I am searching for best practices, math rules and so forts. I need to create save footprints for BGA's and other very small components that probably go into reflow soldering. I would like to know how to make footprints if only the dimensions of the part is know and no recommended pad layout is provided there is also an difference between layout when reflow and wave soldering. I would like to see more science and less trial and error, because it takes to much time and money. http://tinyurl.com/pp8xnv http://tinyurl.com/octvzu Thanks in advance, Jelle ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: naming and creation of 54-pin TSOP II (400 mil) footprint, request for help
Bert Timmerman wrote: Hi Jelle, On Wed, 2009-05-13 at 14:45 +0200, Jelle de Jong wrote: Hello everybody, I am trying to create a footprint with a correct name using the IPC-7351 Naming Convention for Standard SMT Land Patterns. But I am having some issues, i am using the below document to learn about the naming convention: https://secure.powercraft.nl/svn/openarm/trunk/working/pcb/documents/footprint-name-spec.pdf The footprint I want to make is a 54-pin TSOP II (400 mil), see: https://secure.powercraft.nl/svn/openarm/trunk/doc/SDRAM/MT48LC16M16A2P-7E/256MSDRAM.pdf # page 75, 54-Pin Plastic TSOP I tried to figure it out but I don't know what the lead span 1(L1) is? footprint: TSSOP-65P-640L1-54N 54-pin TSOP II (400 mil) TSSOP pin spacing, lead span 1, pin count P pin spacingdimension L1 lead span 1dimension N pin count count I also learned to create footprints with the following document: https://secure.powercraft.nl/svn/openarm/trunk/working/pcb/documents/land_patterns_20070818.pdf I had my ups and downs learning this and had some help trough IRC. However the creation of a 54-pin TSOP II seems to be able to automate using a script. I looked at the following, but it uses a license I disagree with and I can't figure out how it works, I prefer OSI and GPL compatible licenses. http://www.luciani.org/geda/pcb/pcb-perl-library.html Would somebody be able to help me out, what should the name of the footprint become and what scripts can I use to make the footprint and how can I do this? I would go for a name like: TSSOP80P1176X120-54N.fp as in the IPC standard IPC-7351 0.80 mm pitch, 11.76 mm lead span, X 1.20 mm height - 54 leads with Nominal pad conditions (as one of the following: Least, Nominal, Most). Maybe it is a wise thing to avoid - characters in footprint file names or to have a use-files line in your gsch2pcb config file and pass a --skip-m4 flag to disable m4 macro generated footprints to goof up your pcb stuff. Maybe include a vendor and part name too, while footprint artwork recommendations may vary across vendors and specific parts. Thanks Bert for the feedback, I am confused, I calculated the pitch on 0.65 mm how did you came to 0.80mm, and could you explain what exactly the lead span is. If I look at page 75 of the datasheet how can I exactly calculate this lead span? Why did you include the height where did you find this requirement in the IPC-7351 for TSSOP footprints? And why should one avoid the - character in footprint names? I see a lot of footprints with this character, would you be willing to discuss the arguments? I call the gsch2pcb with the following arguments: gsch2pcb --use-files --skip-m4 ~/openarm/working/gschem/openarm-sbc.prj --elements-dir ~/openarm/working/pcb/footprints/ I hope that is ok... Sorry for al the questions, I am kind of confused, and searching for answers and help. Best regards, Jelle de Jong ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: collapsing or non-collapsing balls, how can i tell?
I am trying to make the correct name for my LFBGA320 footprint I have some questions: What is the differences between: * Ball Grid Array’s * BGA w/Dual Pitch * BGA w/Staggered Pins * Collapsing or Non-collapsing Balls and how can I figure out what type of BGA component I have? The footprint and device info can be found here: https://secure.powercraft.nl/svn/openarm/trunk/doc/CPU/LPC3180FEL320/ (use http://www.cacert.org/ for root ca authority) The IPC naming conventions tells me I need to use the following format: Ball Grid Array’s: BGA + Pin Qty + C or N + Pitch P + Ball Columns X Ball Rows _ Body Length X Body Width X Height https://secure.powercraft.nl/svn/openarm/trunk/working/pcb/documents/IPC-7351ANamingConvention.pdf Can somebody help me? I am gambling the following: BGA-320N-50P-4X4_1300x1300x90.fp LFBGA320: plastic low profile fine-pitch ball grid array package; 320 balls; body 13 x 13 x 0.9 mm SOT824-1 If somebody can check the footprint and name on errors I would be very thankful this is the first time I am working with BGA's. Best regards, Jelle de Jong ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: collapsing or non-collapsing balls, how can i tell?
John Luciani wrote: There is a new version of the naming convention, IPC-7351B Naming Convention for Standard SMT Land Patterns, that lists the various BGA types. Dual pitch has Col Pitch x Row Pitch attributes Staggered pins is BGAS A C or N suffix is added for collapsing or non-collapsing balls Thanks you for responding, your library looks great, I am still trying to figure out how you created and named the footprints. There may be a B version for the naming convention but I can't find the documents with an popular internet search engine. My question in the original mail where more focused on the how and why. I under stead that C and N stands for collapsing or non-collapsing balls but I am not very experienced in BGA and I have no idea what this exactly is and how I can see what type of BGA I have. The same goes about Dual Pitch BGA what is a dual pitch BGA, how can one tell. Please see my original mail for all questions. Thanks in advance, Cheers, Jelle ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: naming and creation of 54-pin TSOP II (400 mil) footprint, request for help
Hello everybody, I am trying to create a footprint with a correct name using the IPC-7351 Naming Convention for Standard SMT Land Patterns. But I am having some issues, i am using the below document to learn about the naming convention: https://secure.powercraft.nl/svn/openarm/trunk/working/pcb/documents/footprint-name-spec.pdf The footprint I want to make is a 54-pin TSOP II (400 mil), see: https://secure.powercraft.nl/svn/openarm/trunk/doc/SDRAM/MT48LC16M16A2P-7E/256MSDRAM.pdf # page 75, 54-Pin Plastic TSOP I tried to figure it out but I don't know what the lead span 1(L1) is? footprint: TSSOP-65P-640L1-54N 54-pin TSOP II (400 mil) TSSOP pin spacing, lead span 1, pin count P pin spacingdimension L1 lead span 1dimension N pin count count I also learned to create footprints with the following document: https://secure.powercraft.nl/svn/openarm/trunk/working/pcb/documents/land_patterns_20070818.pdf I had my ups and downs learning this and had some help trough IRC. However the creation of a 54-pin TSOP II seems to be able to automate using a script. I looked at the following, but it uses a license I disagree with and I can't figure out how it works, I prefer OSI and GPL compatible licenses. http://www.luciani.org/geda/pcb/pcb-perl-library.html Would somebody be able to help me out, what should the name of the footprint become and what scripts can I use to make the footprint and how can I do this? Could somebody help me out by making an example for the 54-pin TSOP II footprint? I got a lot more footprints to make, and I can use all the help, since time is getting really sparse. OpenARM Single Board Computer Project: https://secure.powercraft.nl/websvn/openarm/ Thanks in advance, Jelle de Jong ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: naming and creation of 54-pin TSOP II (400 mil) footprint, request for help
Jelle de Jong wrote: Hello everybody, I am trying to create a footprint with a correct name using the IPC-7351 Naming Convention for Standard SMT Land Patterns. But I am having some issues, i am using the below document to learn about the naming convention: https://secure.powercraft.nl/svn/openarm/trunk/working/pcb/documents/footprint-name-spec.pdf The footprint I want to make is a 54-pin TSOP II (400 mil), see: https://secure.powercraft.nl/svn/openarm/trunk/doc/SDRAM/MT48LC16M16A2P-7E/256MSDRAM.pdf # page 75, 54-Pin Plastic TSOP I tried to figure it out but I don't know what the lead span 1(L1) is? footprint: TSSOP-65P-640L1-54N 54-pin TSOP II (400 mil) TSSOP pin spacing, lead span 1, pin count P pin spacingdimension L1 lead span 1dimension N pin count count I also learned to create footprints with the following document: https://secure.powercraft.nl/svn/openarm/trunk/working/pcb/documents/land_patterns_20070818.pdf I had my ups and downs learning this and had some help trough IRC. However the creation of a 54-pin TSOP II seems to be able to automate using a script. I looked at the following, but it uses a license I disagree with and I can't figure out how it works, I prefer OSI and GPL compatible licenses. http://www.luciani.org/geda/pcb/pcb-perl-library.html Would somebody be able to help me out, what should the name of the footprint become and what scripts can I use to make the footprint and how can I do this? Could somebody help me out by making an example for the 54-pin TSOP II footprint? I got a lot more footprints to make, and I can use all the help, since time is getting really sparse. OpenARM Single Board Computer Project: https://secure.powercraft.nl/websvn/openarm/ Thanks in advance, Jelle de Jong The secure links are using a CAcert.org authority this is true open security. However not all web browsers have this authority in there lists. So you may have to add them. If you added the authority the secure pages should not show an security exception. Certificate Authority: http://www.cacert.org/index.php?id=3 OpenARM Single-board Computer: http://www.tuxcrafter.net/pages/projects.html#openarm-single-board-computer Cheers, Jelle de Jong ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Another gEDA-based project working
Eric Brombaugh wrote: I've just finished assembling a new board that I did with gschem / PCB. Web page with description, photos design info here: http://members.cox.net/ebrombaugh1/synth/armfpga/index.html Thanks to all the contributors to gEDA for helping to make this possible. Eric Great work! Keep up the good work. Would it be possible to order it as demo kit for gEDA demonstrations that I like to start doing. Best regards, Jelle ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Ignite Boston 5 talk slides
Stuart Brorson wrote: Hi -- As some of you know, I gave a lightening talk about the gEDA Project at Ignite Boston 5 last week. The Ignite * events are odd networking evenings for geeks (and related marketing types) sponsored by the publisher O'Reilly in various cities around the USA. They feature a social hour and then a main speaker followed by a series of lightening 5 minute talks on a wide range of subjects. The main speaker is pre-arranged by O'Reilly, but anybody can submit an idea for a lightening talk. This event also featured free beer courtesy of Google. Thanks, Google and O'Reilly! I put my slides up on the gEDA website here: http://geda.seul.org/talks/ Folks interested in presenting their own talks about gEDA are encouraged to plunder my slides for useful material. Cheers, Stuart Thanks, I am also invited to give an presentation about open hardware development on http://opencommunitycamp.org/2009/ I will make sure to set gEDA in the spotlight. Best regards, Jelle ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Enlarge a via
Duncan Drennan wrote: :ChangeDrillSize(selectedvias,=38,mil) :ChangeSize(selectedvias,=90,mil) Where can I find a list of all of these commands? http://pcb.sourceforge.net/manual.html On the end on the manual there is documentation about the pcb commands, hopes this helps you. Kind regards, Jelle ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
