Re: gEDA-user: Gschem and footprints
Friends - On Wed, Aug 17, 2011 at 12:43:50AM +0200, Kai-Martin Knaak wrote: Colin D Bennett wrote: For instance, here are some footprint file names from my library: Abracon_ABM8G.fp ADAM_TECH_2PH_2.00_mm_pin_header_SMT_2_pin.fp ADAM_TECH_2PH_2.00_mm_pin_header_SMT_3_pin.fp ADAM_TECH_2PH_2.00_mm_pin_header_SMT_4_pin.fp Antenna_Inverted_F__Ember__2.4GHz__62milFR4.fp Antenna_Meandered_Inverted_F__2.4GHz__TI_AN043.fp I like to have the footprint explicitly printed on the schematic. So _my_ footprint names tend to be short :-) I decided what I really want (and will probably whip up a quick perl script to implement) is to have the schematic list _package_, not footprint. That way I can happily show 0805 or SOIC-8 as a _visible_ attribute in the schematic. Then the mapping script (and _its_ database) will turn that into RESC2012N or SO8M or whatever keeps me and PCB happy. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Linux Desktop für gEDA
On Thu, Aug 04, 2011 at 02:25:05PM -0400, DJ Delorie wrote: What desktop are you using for gEDA? I'm using fvwm2 but my setup is far from normal in many ways ;-) evilwm FTW! Unless someone out there is using ratpoison. :-p Ditto about my setup. ;-) - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: possible collaborators on PCB, gschem [Kicad (or another FOSS tool)]
John - On Tue, Jul 26, 2011 at 01:07:51PM -0500, John Griessen wrote: Larry Doolittle is going to be there in person. What can we tell them to get them interested in gEDA more than KiCAD? Not push and shove, unless someone (not me) goes wild programming between now and October. I have an outline of some ideas I'd like to get across in the talk, and I know I need to review other people's talks on the subject first. Maybe someone (John?) would like to go over my material ahead of time? Not that I need to toe the party line or anything, but it would be nice to give a clear message, consistent with the larger community. There's lots of time. I haven't even boarded the plane yet! - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Task list for: Solving the light/heavy symbol problem
Friends - On Thu, May 26, 2011 at 01:41:08PM -0700, Jared Casper wrote: On Thu, May 26, 2011 at 11:52 AM, Andrew Poelstra as...@sfu.ca wrote: On Thu, May 26, 2011 at 10:56:40AM -0400, DJ Delorie wrote: I'm a Perl fan myself. I think Python would be a better choice. Scala anyone? It's probably a long shot, but I would give my vote for any language backed up by an independent standards committee. The standards document is a contract between the language implementor and the coding in that language. It takes a big step away from the it works for me mind-set and towards a long-term supportable investment in reliable code. Scheme fits: IEEE 1178-1990, reaffirmed in 2008. Not that I'm any fan of IEEE's copyright behavior. ECMAScript? gdr - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Solving the light/heavy symbol problem
On Sat, May 21, 2011 at 09:19:21AM -0400, Bob Paddock wrote: On Sat, May 21, 2011 at 9:09 AM, Kai-Martin Knaak k...@lilalaser.de wrote: My proposal to tackle many of the library related issues is the notion of packages. These would be data structures that can contain all information relevant to an entity us humans like to build electronics from. Specifically, they may contain * symbols * footprints * simulation models * data sheets Not clear to me if your proposal means the data sheets are included in the distributed package? If so, that most likely runs afoul of the company's copyrights and would require permission from said copyright owner, for *each* data sheet. OK, URL(s) and SHA1 of the data sheet. I've had to contact legal departments to use information in data sheets in some of my work, and they've always been happy to grant such access, but you still have to go through the time consuming steps. I have done that, too, but only rarely. It's a royal PITA. Do those guys *cough*Marvell*cough* want us to use their parts, or not? - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: zview/ngscope
Peter - On Wed, Apr 20, 2011 at 12:55:31PM +0100, Peter Clifton wrote: On Tue, 2011-04-19 at 21:34 -0700, Larry Doolittle wrote: My RF gear makes a plausible vector oscilloscope Sounds awesome, can you post some pictures - screen-shots and HW? I've plugged the HW here before: http://recycle.lbl.gov/llrf4/ Here's a screenshot of a GUI based on fltk+opengl: http://recycle.lbl.gov/~ldoolitt/llrf/rgui_image.jpg Sorry the trace doesn't show anything interesting, that's just the white noise background. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: zview/ngscope
Rick - On Tue, Apr 19, 2011 at 10:27:54PM -0400, rickman wrote: ... Providing a real time display with a high update rate would be a challenge for me. If that part is done, then the first major hurtle is done. Some part of the hardware design depends on what the software requires to facilitate the real time data transfer. My RF gear makes a plausible vector oscilloscope (my waveforms that are centered around a carrier get downconverted to vector baseband), although I haven't worked on a spiffy or flexible user interface. Multiple 3-D wire-frame traces of ~1000 points updating faster than the eye can follow, on crappy old Intel laptop graphics chips. I use fltk+opengl, based on the fltk cubeview demo code, processing data brought in over USB at typically 8 Mbyte/sec. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: RFC using SVG with semantic markup as an EDA format
On Mon, Apr 11, 2011 at 08:55:12PM +0200, Kai-Martin Knaak wrote: Peter Clifton wrote: TBH, I've not seen SVG anywhere on the main-stream internet. Wikipedia prefers SVG for anything that is not a photograph. The servers render SVG graphics to PNG as needed before handing it out to the browser. Linux desktops use SVG a lot for desktop graphics, but it really isn't as prevalent as it should be. Microsoft and Apple do not like What excuse is there for OpenOffice / LibreOffice being so appallingly bad at working with SVG files? Actually, SVG import is among the first features of libreoffice beyond openoffice: http://www.libreoffice.org/download/new-features-and-fixes/ Why can't we paste them right into TeX, LaTeX or whatever? They are all open source, yet this open format is not supported. IMHO, latex development reached a state of virtual feature freeze before SVG became a viable alternative. Surely you can convert SVG to EPS, which TeX/LaTeX happily embed. Looks like UniConvertor/sK1 is the usual Free tool to script that conversion. Would it make any sense to leverage that software base, and add Gerber or native gEDA/PCB to its list of import and export filters? http://sk1project.org/modules.php?name=Productsproduct=uniconvertor - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: RFC using SVG with semantic markup as an EDA format
On Mon, Apr 11, 2011 at 10:43:08PM +0100, Peter Clifton wrote: On Mon, 2011-04-11 at 12:37 -0700, Larry Doolittle wrote: Surely you can convert SVG to EPS, which TeX/LaTeX happily embed. http://sk1project.org/modules.php?name=Productsproduct=uniconvertor I use pdfLaTeX with LyX almost exclusively now, so my workflow is Inkscape - PDF - LyX - pdfLaTeX. I didn't mention PDF, but that's relevant for the pdf(la)tex variants that your flow uses, and sK1/UniConvertor has a PDF output filter. Inkscape is nice, but doesn't feel right for embedding in a Makefile. I haven't tried UniConvertor for this purpose. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Footprint/symbol generating scripts + question
Friends - On Thu, Apr 07, 2011 at 01:52:10PM +0200, Kai-Martin Knaak wrote: DJ Delorie wrote: python. It only does SMD dual column footprints with an outline - and at the moment only takes mm. Seems to be a popular thing to do. I did one a while ago, and mine wasnt the first either... How about inclusion of some of the more sophisticated scripts augmented with hooks in the GUI? This might prevent reinvented wheels. And of course, it also improves the user experience of those who tend to adapt to what is already there. http://archives.seul.org/geda/user/Feb-2006/msg00656.html - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Toporouter site non-responsive
Hi - The nice pages that Anthony Blake had up describing his toporouter efforts are currently unavailable. Anthony, can you kick your server? If anyone has an out-of-band method of reaching Anthony, can you point this out? And if someone has a mirror up somewhere, can you post a link? http://www.wand.net.nz/~amb33/toporouter/ redirects to http://anthonix.resnet.scms.waikato.ac.nz/toporouter/ - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: US Distributor for Balloon Board
On Sat, Mar 26, 2011 at 08:50:36PM -0400, Patrick Doyle wrote: I'm looking for a US distributor for a Balloon Board Kind of orthogonal question, how about the MilkyMist One? http://www.milkymist.org/mmone.html It doesn't have a separate processor chip, they implement their own processor in the FPGA. But like the Balloon Board, I don't see a U.S. distributor - only Asia and Europe. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: nice C++ (was Re: pcb plugin smartdisperse fails on load)
On Fri, Feb 25, 2011 at 12:32:13PM -0500, DJ Delorie wrote: So, could you, pretty please, point me to some nice C++ code. Sorry, the work I did back then was not OSS. I'll have to write some more nice C++ for you :-) Tastes may vary, but some years ago when I went looking for a clean C++ matrix math class library, I was favorably impressed by newmat http://www.robertnz.net/nm_intro.htm Operator overloading with a clear purpose! - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb plugin smartdisperse fails on load
On Thu, Feb 24, 2011 at 09:23:44AM -0700, Russell Dill wrote: On Thu, Feb 24, 2011 at 8:50 AM, Peter Clifton pc...@cam.ac.uk wrote: On Thu, 2011-02-24 at 08:38 -0700, John Doty wrote: On Feb 24, 2011, at 8:22 AM, Peter Clifton wrote: Means C didn't find the function, and it assumes it returns integer in that case. Dumb convention IMO. [chop] I believe the behaviour in question dates back to the days where prototypes were very different, and C sometimes had to assume. ...if only there was some sort of flag or option that could be passed to the compiler to convince it otherwise... /me puts on straight-man hat You mean -Werror=implicit-function-declaration? (or just -Wall, and scrutinize warnings) - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb plugin smartdisperse fails on load
On Thu, Feb 24, 2011 at 01:29:08PM -0800, Colin D Bennett wrote: On Thu, 24 Feb 2011 20:48:39 + Peter Clifton pc...@cam.ac.uk wrote: You could add it to PCB I guess - we could even teach PCB how to invoke the compiler and build plugins if we were feeling over-keen! (But perhaps that is encroaching on being too clever). That would actually be very cool. Third-party (non-core) plugins could be distributed as '.c' source files which you load into pcb and it automatically compiles them on the fly and loads the resulting '.so'. Octave does that for its octave-forge packages. It's pretty cool when it works. It sucks when it doesn't. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: new vhd2vl on its way
Friends - On Wed, Nov 17, 2010 at 11:12:46PM -0800, Larry Doolittle wrote: I have a new release of vhd2vl pretty much ready to post. Version 2.4 is now posted at the usual place: http://doolittle.icarus.com/~larry/vhd2vl/ Enjoy! - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: icarus, fork, and recursive tasks
DJ - On Mon, Nov 08, 2010 at 04:46:35PM -0500, DJ Delorie wrote: That's unfortunate. I've been getting some good mileage out of the XC3S200A-VQ100 parts. Too bad Xilinx hasn't made that size available in the 3AN family. I suppose that you chose the AN variant because you wanted to avoid dealing with the configuration memory. And board space. Just boot the FPGA from the processor. That's what I always do. When I have a processor, that is. The only overhead is the four GPIO pins attached to the FPGA JTAG, and those can be put to good use after booting as well. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: FPGA, uC, and JTAG (was Re: icarus, fork, and recursive tasks)
On Mon, Nov 08, 2010 at 05:09:30PM -0500, DJ Delorie wrote: Just boot the FPGA from the processor. That's what I always do. When I have a processor, that is. The only overhead is the four GPIO pins attached to the FPGA JTAG, and those can be put to good use after booting as well. I used the SPI pins, just streamed the bitstream at full speed. The RX board uses jtag, so I have to convert the bitstream to XSVF and play it into the chip, but I don't have to include that code (or bitstream) in any normal apps. I always like the satisfaction of seeing the JTAG ID of the chip before blindly bit-banging a megabyte to a chip that might not really be there. I also use JTAG to access registers on the running chip; it works about as well as SPI in that regard. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FPGA, uC, and JTAG
On Mon, Nov 08, 2010 at 05:24:21PM -0500, DJ Delorie wrote: True, but the xsvf file is much bigger than a simple serial bitstream, and the xsvf player is bigger than a raw spi dump... A JTAG bit-banger is not hard to write (I've written at least two of them), and a lot smaller than an xsvf file player. The one I use routinely now takes a small fraction of the 8K program space of an 8051 derivative (CY7C68013). The input file is the straight bitfile. Granted it will run a little slower than SPI, because unless you're exceptionally lucky it won't be hardware accelerated. It would be fun to take a crack at the bit speed limit on that 96 MHz processor, though. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FPGA, uC, and JTAG
DJ - On Mon, Nov 08, 2010 at 05:55:04PM -0500, DJ Delorie wrote: A JTAG bit-banger is not hard to write (I've written at least two of them), and a lot smaller than an xsvf file player. Can you bit-bang a spartan 3 that way? Yes. Shameless plug (and almost back OT, since the board was laid out with pcb): http://recycle.lbl.gov/llrf4/ - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB format wishlist
Rick - On Mon, Sep 06, 2010 at 10:31:15PM -0400, Rick Collins wrote: Several times now in this thread I keep thinking that the language Forth is being described. 'Words' built up on previously defined 'words'... I have often thought that I would prefer to write an HDL that works like Forth. If used in this way, it becomes a bit Lisp like in that the data and program would need to become one and the same. The Forth that describes the design would be executed to create the design in memory or to be output as a set of Gerber files. But to do things like DRC, you would need to analyze either the image in memory or the design source itself as data. Ideas like this are cool, but take extra attention to their security implications. Is the file format capable of infinite loops? Are there primitives to read or write files? Hmm. It's not impossible to get right. There's an old security saying; my Google-fu failed me, but it goes something like: Users are receptive to all sorts of ideas of what computers should do, and vendors are all too ready to make them happen. By the time a security expert exclaims are you nuts?, it's too late. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Subnets
On Mon, Aug 16, 2010 at 07:32:23PM +0200, Stephan Boettcher wrote: I usually have hierarchical schematics with multiple instances of the same subcircuits referenced from the main page. The deepest until now were three layers of hierarchy. I make do with two, but that's how I work also. All the cutting, sed-ing and pasting of the subcircuits to multiple instances, with replication of later changes on all copies is pretty unflexible. Agree 100%. Hierarchical sub-cells (like with ASIC layouts) would allow to make and maintain such circuits much easier. What I am asking for here is, when you now talk about layout zones/partitions/whatever it's called in the end, please consider the application of the concept for this kind of hierarchy. Maybe the new concepts can be easily applied for that as well, with a little vision into that direction. Maybe it is trivial to allow multiple copies of a layout zone on a board, with a common netname/refdes prefix substituted on the copies. When you edit the layout of any copy, all instances follow the change. I don't know about the trivial adjective, but I assert that's the goal, and would give me (and I suspect many others) a dramatic improvement in productivity and usability. The old get an electic circular saw after years of only using a hand saw analogy. My eagle-using colleagues envy me for the hierarchical schematics that I can draw in gschem. I do this in xcircuit, but at some point I may move to gschem. My biggest motivation, believe it or not, will be the better BOM support. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Yet another Icarus question
On Wed, Aug 04, 2010 at 10:58:51AM -0400, Patrick Doyle wrote:
Can anybody tell me if the following is an Icarus feature or a Verilog
feature.
Verilog. Probably.
reg [5:0] offset;
reg [9:0] enablemask;
initial begin
enablemask = 10'b0_00110;
offset = 0;
$display(%b, {enablemask, (16'h0 + 8'h80 + offset )});
$display(%b, {enablemask, (16'h0 + (8'h80 + offset))});
end
This can be explained as long as the default addition order
in Verilog is left-to-right, thus
16'h0 + 8'h80 + offset is defined as (16'h0 + 8'h80) + offset.
16'h0 + 8'h80 is 17 bits wide, to account for carry.
Adding the 6-bit offset to a 17-bit number also needs to
account for carry; the notion of a value-constrained
17-bit number is too subtle for Verilog. Thus the
result is 18 bits.
With the other order of addition, 8'h80 + offset is 9 bits
wide, after accounting for carry. Adding a 9 and a 16 bit
number, with carry, gives a 17 bit result.
Just this morning I got started again thinking about a post-Verilog
language that would have more powerful bookkeeping behind the scenes,
thus allowing more compact and reliable code. Value-constrained
integers (or more generally, fixed-point numbers) are on the list.
The last time I wrote notes to myself about this was August 2009:
Inspired by, but presumably not compatible with, the base Verilog language.
It will need a translator so you get something that a synthesizer and
simulator could handle. In the long run, extending Icarus to handle this
language would have advantages, especially in making a vcd (or lxt or ...)
file that is more closely related to the original source.
- Larry
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Re: gEDA-user: OT Verilog syntax question
On Tue, Aug 03, 2010 at 09:12:00AM -0400, Patrick Doyle wrote: I have some verilog test code in which I would like to display an integer value, which is known to be between 0 and 15, as a binary vector, i.e. integer result; $display(%4b, result); of course I get a 64 bit vector displayed. Is there any way to cast my integer variable result as a 4 bit vector just for use in a $display statement? integer result; reg [3:0] result_disp; always @(foo) begin result_disp = result; $display(%4b, result_disp); end Simpler still is to use reg [3:0] result in the first place, but maybe that breaks other parts of the code. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: analog/digital partitioning
On Thu, Jul 22, 2010 at 09:57:11AM -0700, Steven Michalske wrote: On Jul 22, 2010, at 9:50 AM, Eric Brombaugh ebrombau...@cox.net wrote: On 07/22/2010 09:37 AM, DJ Delorie wrote: One idea to consider is to start with a solid plane, and cut slots around the sensitive analog parts, like big C shaped moats, squares open on one side. You retain the big ground plane conductivity, but you prevent stray currents from using your analog area as a short-cut. Now each side of this debate can call you a heretic -- that's a good thing! I'm generally on the single-ground-plane side of this fence, and the one time I ran into trouble, the solution was just as you describe. Just make sure that if you've got high-speed digital lines that cross into the 'cubicles' they have gnd plane underneath them where they enter - don't let fast signals cross the cuts because then the return currents have to take a different path and that will screw up the signal integrity. The question is how fast?. Because you loops may not even matter. But just remember to keep them small. :-) If you have _any_ signals crossing the slots, you're doing it wrong. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: spice libs ( a little puzzled)
On Mon, May 03, 2010 at 03:14:22PM +, Kai-Martin Knaak wrote: You don't need a data base for this kind of indirection. Any download script would do. However, it makes the process depend on stability of external sources --sources that can change, or go away without any day. Experience shows that this will happen for one reason or another. Yup, and in some sense this is even true of free material. When I have put together download scripts, my checklist is: - rollover to a series of URLs - accept uncompressed, .gz, and .bz2 versions transparently - include an sha1sum to confirm you got what was intended - the last URL in the rollover list is a URL I control For the non-redistributable case, the last item is problematic. You still need it, but it has to be somehow not publicly accessible, so it can qualify as a legal backup copy. If the original becomes unavailable, the backup can become the reference copy for a clean-room reimplementation. So this trick becomes a way to defer and prioritize development of truly free models, not eliminate them. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB configuration skin
Dave - On Fri, Apr 23, 2010 at 12:15:36PM -0400, Dave McGuire wrote: Lots of people speak Esperanto. It's all relative. Compared to, say, Spanish? I'm one of them. Multaj homoj parolas Esperanton. Mi estas unu el ili. Very cool. Translation? Come on, Dave. Pattern match. Multaj - multiple(many) homoj - homo(man) (and at this point you figure a j suffix might mean plural) parolas - like French parlez (talk) Esparanton - not sure about the n suffix Mi - My, Me estas - like latin est, spanish es: to be unu - latin unu, game/spanish uno, one el - spanish ili - wouldn't have guessed in isolation, but clearly them - Larry [who has never spoken a word of Esperanto in his life] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Patch to PCB build system needs testing/feedback
Jared - Sent privately, maybe you can summarize responses (or if I'm the only one, tell me, and I'll post to the list). On Sun, Apr 18, 2010 at 04:05:16PM -0700, Jared Casper wrote: I think it makes the build much cleaner and readable overall and, more importantly, makes the errors and warnings much easier to see. I don't mind the short form, until I run into trouble. Then I want a documented way to turn it off, so I can see what make is actually trying to do. The explicit command lines are wonderful sources of cutting-and-pasting experiments on the command line. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Patch to PCB build system needs testing/feedback
On Sun, Apr 18, 2010 at 08:38:28PM -0700, Larry Doolittle wrote: Sent privately, maybe you can summarize responses Yeah, well, I got distracted at exactly the wrong moment. So kick me. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Magnetic bike operation
Rob - On Mon, Mar 29, 2010 at 11:14:51AM -0400, Rob Butts wrote: I've read about the eddy current breaks but it's still not clear to me how to construct one. The wikipedia talks about a rotor connected to a spinnning coil. I would think the rotor would spin inside a coil. Any time you have a conductor (aluminum is a good choice) moving in a magnetic field (a permanent magnet is fine) it will have a repulsive force (not always easy to detect) and a drag (actually decreases at high speeds, as the repulsive forces kick in). It's easy to try out yourself with a spinning aluminum disk and a strong permanent magnet. This is also how an old-fashioned mechanical speedometer works. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: TO-92 Best Practices
Al - On Wed, Mar 03, 2010 at 10:18:59AM -0500, al davis wrote: Along that line ... You could get what they call reading glasses from a supermarket. Get the strongest ones they have. They make great magnifying glasses. I didn't need them in college, but I sure need them now! You really should wear eye protection while soldering anyway. Right. Funny story. We had a big safety audit here a few months ago. Lots of new work practices, including mandated eye protection -- safety glasses -- when soldering. So .. I start doing some rework on a particularly tricky section of an 0603-scale board. A flock of managers cruised by and said -- Hey! you don't have safety glasses on! I show them that I don't get any benefit from safety glasses when I'm soldering under a 10X microscope. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: I am such a troll for posting to slashdot
On Sat, Feb 27, 2010 at 09:03:41AM -0500, Bob Paddock wrote: The other thing that is holding back gEDA Schematics is the lack of available publication quality symbols. If I'm doing a PCB I use gEDA. If I'm after a nice looking schematic I use XCircuit. I'd like to be able to have it both ways, a nice looking schematic that I can make a PCB from. You do know about XCircuit's built-in pcb-compatible netlist exporter? I build boards using XCircuit+PCB. The ugly part for me is the (lack of) BOM support. That doesn't sound so hard to fix. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
Hi - On Wed, Feb 24, 2010 at 02:40:50PM -0500, Bob Paddock wrote: I'm making the assumption you will have a contractor build quantities someday, in automated equipment. These will (at least should) lower production costs: Although OT, I appreciate and try to learn from discussions like this. Do you have at least three Fudicuals on all of your boards? I know what fiducials look like, but haven't seen a footprint for one within pcb. Am I blind? Is there a standard recipe for making one? These compensate for film stretching, board alignment during assembly etc. The last time I asked a board loading house about fiducials, they said they gave up and just optically register to the component footprint itself. Have you specified tooling holes for panels?: [chop] Have you specified how to route and/or score the boards? This is something I have never gotten into. I guess my boards are always too large and/or the order too few to care. Have you put Fudicuals on components, such as tiny QFN packages, or even massive TQFP and BGAs. I don't think you said what you wanted to say. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: Latex
Like others in this group, I'm a TeX partisan, and yes that includes pdftex most of the time. I converted to TeX from VAX runoff in 1987. On Sat, Feb 06, 2010 at 12:10:04PM +, Peter Clifton wrote: pdflatex also supports .png and .jpg files natively - which is (probably) better than .eps for some applications. I guess you haven't discovered jpeg2ps. jpeg2ps V1.9: convert JPEG files to PostScript Level 2 or 3. (C) Thomas Merz 1994-2002 ... without uncompressing the image. It makes use of PostScript's DCTDecode filter. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Pick-And-Place Extract
Tony - On Mon, Jan 25, 2010 at 10:18:07AM -0500, Tony Radice wrote: I have written a Perl script to extract pick and place data from a pcb file - is anyone else interested in looking at it, using it or critiquing it? You know pcb already has a pick and place data extractor? This is the .xy file people talk about on this list. As I am also developing a Perl script to write an IPC-D-356 data file Standards are good, and unless we got really lucky and that standard is very loose, we don't follow it now. Adding that option to the existing xy file generator would be wonderful! - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: powermeter results!
On Mon, Nov 16, 2009 at 01:19:44PM +0900, Torsten Wagner wrote: a) just buy a bigger machine and use virtualisation technologies [chop] b) get some of this little ARM based boards or Atom based boards [chop] c) Computers which does not need to run 24/7 but always on because [chop] d) Replace an obsolete server with a cast-off-for-mechanical-reasons laptop. I'm thinking of cracked cases or screens. You get quiet, low power, small footprint, and a built-in UPS. And its price ranges from small (*cough* ebay *cough*) to free. (You're welcome, Steve) - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Eliminate separate Vcc planes?
Neil - On Mon, Oct 19, 2009 at 01:20:23PM -0700, Neil Hendin wrote: If you look at the RF S-Parameters of the capacitor at frequencies above the self resonance, they look inductive, not capacitive. I'm not sure what the precise definition is for the S-Parameters of a two-terminal device, but the conclusion is accurate. Good RF decoupling standard practice is to use a smaller cap (e.g. 20pF in parallel with some larger ones such as 1000pF _and_ 0.1uF or larger as needed) to get a good broad band capacitive reactance across frequency). I have yet to see a 20pF or 1000pF cap with less parasitic inductance than a decent (e.g., X5R) 0402 cap up in the uF range. Say, in particular, TaiyoYuden JMK105BJ225MV-F 2.2uF 0402 6.3V X5R 0.1560 in 100's If you're going to occupy board area with a cap and its connection to the power nets, can anyone explain why I should choose anything other than the largest value available in that size and voltage? OK, I suppose if you're building cell phones and selling them by the hundreds of thousands, the nickel you could save by using a lower value would add up. But for me, the cost of assembly and documentation probably exceeds the cost of the component itself. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Blind and buried vias?
John - On Fri, Sep 25, 2009 at 10:27:02AM -0600, John Doty wrote: Remember, pcb is a separate tool, not part of gEDA. But it does fall under the gaf umbrella, and this is the proper mailing lists for things pcb-related. Probably very few pcb users capture schematics with anything but gschem, Hey! Some of us (cough) are still xcircuit partisans! - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb option --fab-author not working
On Sun, Sep 20, 2009 at 06:00:11PM +, Michael Sokolov wrote: In my code of honor a PCB designer who lays out an Open Source Hardware board deserves to have his/her name on the silk screen, at least on the bottom side if there is no room on the top component side. I personally think author information is important enough to put in copper, not just silk. Also, don't forget to include the date, and either an internal documentation reference number or (the more modern alternative) a URL for board documentation. Finally, most people and organizations try to squeeze a logo on the board somewhere. I know I do. There are certainly other uses for documentation incorporated in the file but not part of the final artwork. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: logic analyzers, verilog, and gtkwave...
DJ - On Sun, Aug 09, 2009 at 05:51:40AM -0400, DJ Delorie wrote: The LA module I wrote is a DDR dual-bank capture, [chop] A perl script turns them into a VCD file that gtkwave can read :-) Awesome. I hope you'll write this up more, and publish code. Question: Can gtkwave be told to break up a bus into its component signals? It's in the Edit menu, called Expand (F3). - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: logic analyzers, verilog, and gtkwave...
DJ - On Sun, Aug 09, 2009 at 01:22:20PM -0400, DJ Delorie wrote: It's in the Edit menu, called Expand (F3). Sweet. Hmmm... Expand again on one of those individual lines should re-combine them. No, you have to select a bunch of individual signals (they need not be the full set of the original bus, or even all related) and then Combine Up (or Combine Down). That step is smart enough to label continuous bits as you'd expect. Non-related bits get an artificial tag. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: RFC: Towards a better symbol/package pin-mapping strategy (was: Re: slotting and power pins)
Bill - On Sun, Jun 28, 2009 at 12:26:10PM -0500, Bill Gatliff wrote: [greatly trimmed] It would be nice if there was an additional layer of abstraction somewhere between the symbol and footprint, such that actual pin assignments weren't made until the footprint (and slot, if necessary) were specified. It's just an additional layer of abstraction above/replacing the slotdef= parameter. I basically agree with the argument. The final trick that would make a larger audience happy is the ability to back-annotate the schematic with the physical pins -- and presumably a switch for whether to display the physical or virtual pin IDs -- so that the engineer can print out (for the field technician) a schematic that has physical pins on it. Even the original design engineer wants such a printout when bringing the board up for the first time. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Looking for PCB fab recommendations
Michael - On Fri, Jun 19, 2009 at 06:52:14AM +, Michael Sokolov wrote: Ineiev ine...@gmail.com wrote: BTW why unplated holes may be preferable for this case? [pcbfabexpress.com] charge $50 extra for unplated drill and I'm OK with that. (That's for the whole order, not per board.) That's payment so that _they_ can make undersized plated holes, and then drill them out -- maybe by hand, maybe in their CNC drill. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Looking for PCB fab recommendations
Michael - On Fri, Jun 19, 2009 at 02:52:10AM +, Michael Sokolov wrote: * Both plated and unplated drill. Some parts have plastic mounting elements and I want unplated holes for those. Get all your holes plated and drill out your mounting holes by hand. Otherwise you will end up with a more expensive process. Choose your hole sizes with this post-processing in mind. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB layout design patterns
Saritha - On Wed, May 20, 2009 at 01:47:03PM -0700, Saritha Kalyanam wrote: 3) escape routing for BGA? Here's a start: http://recycle.lbl.gov/~ldoolitt/ft256/ (or finish, for that particular device) Generalized, it represents normal industry practice. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Looking for tips to debug Icarus Verilog
Patrick- On Thu, Apr 09, 2009 at 08:23:55AM -0400, Patrick Doyle wrote: I tried firing up gdb on iverilog, but that doesn't do much good, as iverilog is simply the driver program. Is there a howto one can point me at for debugging iverilog? see email from Steve Tue, 05 Jun 2007 12:33:19 -0700 ~/lib/ivl/ivl -v -Ctgt-stub/stub.conf -Cgo.conf -Pa.pf -Na.net -- $VERILOG gdb ~/lib/ivl/ivl run -v -Ctgt-stub/stub.conf -Cgo.conf -Pa.pf -Na.net -- $VERILOG --- 2008-11-12 ~/lib/ivl/ivl -v -Cgo.conf -Pa.pf -Na.net -- $VERILOG $ cat go.conf generation:3.0 sys_func:vpi/system.sft warnings:implicit debug:eval_tree debug:elaborate out:a.out ivlpp:/home/ldoolitt/lib/ivl/ivlpp -D__ICARUS__ -L sys_func:system.sft $ YMMV. HTH. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Looking for tips to debug Icarus Verilog
Patrick - On Thu, Apr 09, 2009 at 10:01:06AM -0400, Patrick Doyle wrote: For those of you who might be interested... I found the bug in my verilog code that was triggering the crash. I had a spelling mistake in one of my nets that resulted in a net being implicitly declared. Personally, I don't think that this should trigger a crash of the compiler (and perhaps it doesn't on other systems), but I'm past my current hurdle. If the compiler crashes, it has a bug, and you should report it. 1) Add a page to the iverilog wiki outlining some tips for debugging iverilog (such as the use of the -v flag, the use of the IVERILOG_ICONFIG environment variable, the importance of spelling IVERILOG_ICONFIG correctly, etc...) If such information already exists somewhere, then I missed it, and I probably don't need to replicate it. That's a good idea, go for it. 4) Narrow my code down to the barest minimum set of code that reproduces the crash and try steps 2 or 3. Maintainers always appreciate it if you can put some time into this step. 3) Send some combination of my current verilog code and/or the intermediate files to somebody else to see if the problem can be replicated on another platform. Ideally that somebody would be intimately familiar with the code and would be able to spot the bug in less than 5 minutes (assuming that it is reproducible). The best place to post your code is on the Sourceforge/Icarus bug tracker. http://sourceforge.net/tracker/?atid=775997group_id=149850func=browse - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: chipscope vs. rerouting signals to test pads/pins
On Mon, Apr 06, 2009 at 09:42:30AM -0700, Eric Brombaugh wrote: I've had no trouble installing the full ISE on Fedora and I've been using it since 2005 or so. Webpack's installer is limited to 32-bit systems though, so if you're on a 64-bit system that might be getting in your way. It's pretty easy to run the installer on 64-bit (amd64) Linux, and get a working install. No chroots necessary. The programs do still run the processor in 32-bit mode, of course. I have done it on Debian, but the details are not distribution-specific. The biggest hack is bypassing the stoopid shell scripts that autodetect architecture and figure out which version to install. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PALs GALs and SPLDs going the way of the Dodo?
DJ - On Fri, Mar 27, 2009 at 04:29:12PM -0400, DJ Delorie wrote: [the XC9536XL is] huge compared to a 16v8, though, but once you have the bitstream files (xilinx runs with Makefiles on Linux) you can program them with open source or home-brew toools. Funny, I was just trying to hack my Xilinx-on-Linux Makefiles (actually the script called by the Makefile) that work with FPGAs, to make it target an XC9536XL. I've posted my xil_syn script here before, has anyone else put something together like it for an XC95xx? - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How to fit REFDES on PCB with Hierarchy
On Mon, Mar 09, 2009 at 12:40:47PM -0500, John Griessen wrote: Its hard to pick a set of single letter names to use as instance names to use with a separator, since so many are used up by first letters of component names: Cap Diode Fuse J(connector) L(inductor) Q(transistor) Resistor Terminal U(IC) Varactor Xtal X is sometimes used, since the proper designation for a crystal is Y. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: What is the current procedure and location to submit patches for PCB?
On Sun, Mar 08, 2009 at 06:41:31PM -0400, DJ Delorie wrote: is there any type of regression test suite for PCB? Nope. That, itself, sounds like a bug. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus Verilog: How to exit simulator with non-zero status?
Patrick -
On Tue, Mar 03, 2009 at 11:39:28AM -0500, Patrick Doyle wrote:
I have an Icarus Verilog question (which may, perhaps be a more
general Verilog question). I would like to write a test bench that
exits with a non-zero status when it detects an error. That way I can
simply run make to test a bunch o' code and come back later to see if
everything exited cleanly.
Is there a way to exit the simulator with a non-zero status?
There is no standard way, so historically we used post-processing.
Peek at the output for a PASS result, using a Makefile rule like:
# Generic regression test
%_check: %_tb testcode.awk
vvp $ | awk -f $(filter %.awk, $^)
where testcode.awk is
---cut here---
# very general processing of vvp output to set a return code
# since apparently Verilog running inside vvp does not have
# a way to affect that directly
BEGIN{code=1}
/PASS/{code=0}
{print $0}
END{exit(code)}
---cut here---
Assuming you can get your simulator to save the results to stdout
or a file, this is about as general-purpose as it gets.
While functional, that technique still seems hackish. The Icarus
developers eventually added their own Verilog extension, the
VPI function $finish_and_return(exit_status). That will work in
any development version since May 22, 2008.
- Larry
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Re: gEDA-user: Icarus Verilog: How to exit simulator with non-zero status?
Patrick - On Tue, Mar 03, 2009 at 12:37:17PM -0500, Patrick Doyle wrote: developers eventually added their own Verilog extension, the VPI function $finish_and_return(exit_status). Oh... I like that! That's just what I was hoping my buddy Google would have found for me. It's tough to ask Google for something you don't know the name of. Maybe they're working on that. ;-) Should I have been able to find that somewhere else? (I am asking in a tone of voice of I would like to know where to look for answers such as these so I don't have to pester the mailing list and not in a whiny tone of voice of where's the docs?) That function/extension was extensively discussed on the mailing list. http://sourceforge.net/mailarchive/forum.php?thread_name=20080522154426.GA3860%40recycle.lbl.govforum_name=iverilog-devel I don't see it documented anywhere. Maybe it should go in extensions.txt? - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Another gEDA-based project working
Eric - On Fri, Feb 27, 2009 at 11:32:40AM -0700, Eric Brombaugh wrote: As far as kits go, sorry. I'm not set up to sell parts (there are probably about $70 worth on this board if bought in small qty). If you'd like to take the gerbers to your own fab though feel free to do so. It cost me about $80 for two boards shipped from BatchPCB. I bought a kit recently from TPpacks.com, that was pretty nicely set up. The kit is really a bare board (US$49) plus a BOM ready to submit to Mouser (US$60-ish) and a PDF of assembly instructions. The ttpacks.com website is too strange to let me give a direct link, but if you use their search button with BMS you'll go straight to their 4-24 - Cell Battery Management System. A lot more people are willing to buy and assemble parts, than deal with getting a PCB made from Gerbers. Of course, it's also a significant cost savings to get one large batch of PCBs made, rather than many small batches. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: more board fab discussion (was Re: Interesting board defect)
Gabriel - On Tue, Feb 17, 2009 at 03:47:10PM +0100, Gabriel Paubert wrote: Did not nee for this, and my RF designs use Rogers' substrates which are much more reproducible than FR4 at frequencies above 2GHz. I'm currently searching for a U.S. fab for prototype quantity of Rogers' boards that doesn't charge 4X what I'm used to for FR4. I have some leads, but a lot of places I expected to be reasonable are not. Have you or others on this list found such a place? - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Google SoC : Potential Candidate seeking Info
Dan - On Tue, Feb 17, 2009 at 10:01:57PM -0500, Dan McMahill wrote: The tool worked and really my primary complaint was that you quickly ended up with an expression that a) was not at all a low entropy expression (see various papers by Middlebrook or the textbook by Vorperian) Hey! I still remember getting back homework stamped by Middlebrook (yes he had the stamp custom made) that said Unilluminating Form. No credit. You learn real fast in that environment. Thirty years later, it's as clear as ever that Middlebrook was absolutely right. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB + GL latest (patch for indirect rendering support)
Peter - On Wed, Feb 11, 2009 at 03:39:23PM +, Peter Clifton wrote: On Wed, 2009-02-11 at 09:44 -0500, Joshua Boyd wrote: Either with or without my change to Makefile.am, aclocal complains with a lot of warnings: I've noticed more and more noise from aclocal on Ubuntu systems. Its probably nothing which will break the build, just an indication that we're being naughty somewhere with our use of AC_... macros. It's not just Ubuntu. I see that on Debian machines, too. Would you like help cleaning it up? - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: label printing
Levente - On Wed, Feb 04, 2009 at 11:30:53PM +0100, Levente Kovacs wrote: I would like to print labels. For this I'd generate N times some labels, with slight different content. Then I have N *.eps file. Question. How do I merge them into one A4 postscript page? Look into mpage http://www.mesa.nl/pub/mpage (probably also in your favorite Linux distribution) * LaTex. It is pain to do it, but once it's done, it's okay. I've done that. Well, plain TeX. * Xfig. Ditto. I've done that. * Postscript. It should be possible to include *.eps into the main page. That should be the most portable. I don't know what it takes to implement the include *.eps part. * Buy a label printer, and not to use sheet labels. :-p Does anyone have any experience with Postscript programming? Yes. ;-) - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: geda in Lenny (was Re: Creating system-gafrc again)
On Mon, Jan 26, 2009 at 02:32:18AM +, Peter Clifton wrote: On Sun, 2009-01-25 at 17:21 -0800, Gary L. Roach wrote: [chop] I'm running 1;1.4.0-2 on Lenny. I presume by reinstalled, you mean that you re-installed the debian package, not installed from source. [chop] Speaking of Debian/Lenny/gEDA, can someone turn up the heat on getting a license-fixed (at least) geda into Debian? The time is fast approaching when packages with RC bugs will get kicked out. My guess is that it's already too late to get a significant update into Lenny, and y'all should content yourselves with the license fixes, and maybe throw in a fix for #507363 for good measure. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
John - On Tue, Jan 13, 2009 at 12:54:21PM -0700, John Doty wrote: It seems you want gEDA to cater to your unwillingness to master new skills, learn better ways to do things. But gEDA's power is that it frees you to use the better way, not constraining you to inefficient ways of doing things. John, we've heard this all before. My ideas about an ideal work flow even parallel yours completely! But gEDA's flexibility should _include_ the ability to deal with people who don't think like us. So please stop telling people how to do their work. Do make sure gEDA maintains its ability to use the better way, and don't discourage others from using it in inefficient ways, and even improving its ability to work so inefficiently (?). The expert modes will then be on their desk, ready for them when _they_ are ready to adapt. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: Recommendations for laptop?
On Fri, Jan 02, 2009 at 09:40:08PM -0700, Eric Brombaugh wrote: I've been glancing over some of the inexpensive Linux-based netbooks lately - a tad underpowered, but potentially useful and cheap enough to take a flyer on. I'm curious how useful a 1024x800 screen would be for gEDA/PCB. 1024x800? Where? They're all widescreen now. The lightweight, inexpensive ones are 1024*600 or so. The larger, heavier, cheap and modern notebooks get up all the way to 1280x800. The lack of height would hurt me, at least. I now use a 1024x768 Thinkpad X40 (which I have promoted here before: US$400 on eBay). I couldn't stand going any smaller in screen size. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: Recommendations for laptop?
On Fri, Dec 26, 2008 at 02:01:12PM -0800, Dave N6NZ wrote: One thing I've always liked about the Thinkpad's/Lenovo's is the excellent feel and behavior of the pressure stick. Works great. My new Lenovo has both a stick (which I like and use) and also a scratcher, which keeps getting in the way because I keep accidentally dragging a finger over it and losing my cursor... Seconded. I have had laptops with all combinations. I quickly adapt to the pressure stick (http://xkcd.com/243/), but to the track-pad, not so much. One more plus for the X40 with pressure stick only: three mouse buttons. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: Recommendations for laptop?
Stuart - On Fri, Dec 26, 2008 at 07:33:13AM -0500, Stuart Brorson wrote: Ordinarily I'd buy a reconditioned IBM Stink Pad from IBM, and then stick Fedora on it. Stink Pads are mechanically robust, and they play with Linux easily. However, IBM has sold the Stink Pad division to China, and I am reluctant to get a Levano because of quality concerns. I have no regrets getting a ThinkPad X40 from eBay for US$400, a few months ago. Maybe a little larger, slower, and less glitzy than a similiarly priced netbook. But a good clear 1024x768 screen, and mechanically robust as you say. The X40 was the last true IBM model, before Lenovo took over. You can find them at 1.2, 1.4, and 1.5 GHz, and with a variety of wireless cards. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
DJ - On Tue, Oct 28, 2008 at 03:09:37PM -0400, DJ Delorie wrote: App notes and example designs are special cases: there is only one chip straddling the analog and digital divide. If you have more than one (e.g., both an ADC and a DAC) all those ideas pretty much go out the window, and you're better off with a single ground plane. I have 16 of these chips, all talking to a single MCU. The 8 on one side have their own analog power/gnd, and the 8 on the other side have their own. Split power supplies: almost always good. Split ground planes: almost always bad. Two layer boards are a special challenge, because you never quite get a full ground plane. Your board looks decent. What kind of voltage resolution are you looking for (e.g., what IC are Uxx0)? The first thing that leaps out at me is the large loop for power supply filtering on those chips (both AGND to AVdd, and DGND to DVdd). Oh, and do you really want REF filtered to digital ground? If you have noise troubles with that layout, I can offer suggestions to improve it. Hint: it will involve more closely approximating a real ground plane over the whole board. One major trouble with split ground planes is when tracks cross the split, and the return path becomes high inductance. Your board doesn't suffer too badly from that disease. Most cases that look like that are actually differential signals, where the plane is not part of the circuit. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
DJ - On Tue, Oct 28, 2008 at 12:49:51PM -0700, Larry Doolittle wrote: Your board looks decent. What kind of voltage resolution are you looking for (e.g., what IC are Uxx0)? I see now, ADE7753ARSZ, $3.834 in 25's at DigiKey. 16-bit Sigma-Delta under the hood. Good luck with that. The first thing that leaps out at me is the large loop for power supply filtering on those chips (both AGND to AVdd, and DGND to DVdd). Oh, and do you really want REF filtered to digital ground? No, you don't. If you have noise troubles with that layout, I can offer suggestions to improve it. Hint: it will involve more closely approximating a real ground plane over the whole board. I guess your layout will need at least one more rev before you can get to the noise limit of that chip. OTOH, maybe that isn't the goal. I do really like the idea behind that board! I have a Kill-A-Watt at home. It's really handy, but a real multi-channel power datalogger would be even better. I thought about building one myself many years ago, but never got the traditional Round Tuit. Don't let my snarky comments about grounds keep you from building yours. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Joerg - On Tue, Oct 28, 2008 at 02:07:30PM -0700, Joerg wrote: Tried to load your layout but got an error and I could not find any pointers via web search. Error parsing file ... line: 801 description: font position out of range I hit this too. I just deleted the Symbol that tarts on line 800. The board didn't seem any the worse for wear. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
John - On Tue, Oct 28, 2008 at 10:11:38PM -0500, John Griessen wrote: Larry Doolittle wrote: I have seen exactly one case where a split (very carefully done) on the ground plane was needed to avoid a source of ground return crosstalk. I'd like to hear more about that, if you will. The ADC and its input connector (vertical SMA) were in the middle of the board. On one side was a power supply, and on the other some variable load (I forget what, maybe a DAC). Low frequency return currents travelling along the ground plane created (with Ohm's law) voltages that mimicked changes in the input pin. The ground plane needed a C shaped cut, with the SMA and its four ground posts in the middle and the ADC input on the right, to keep the interfering current away from the signal, or more precisely its return path. I hope that made sense. It was hard to find, but pretty clear to us after the fact. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: SFP modules to FPGA
Friends - Just wondering how lazy I can be: Has anyone here made an SFP footprint for PCB? (SFP = Small Form-factor Pluggable transceiver, http://en.wikipedia.org/wiki/SFP_transceiver) (e.g., AMP UE75-A20-3000T plus U77-A4114-2001) Has anyone here connected such a device to a Xilinx XC5VxXxxT? I assume the answer is no, but I thought I'd check. What's the largest FPGA/BGA package this community has laid out with PCB? I've done 256, and I assume others have done bigger. I want to at least do some design studies on an XC5VLX50T-FF1136. Scary! - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: SFP modules to FPGA
Marvin - On Tue, Oct 21, 2008 at 12:16:01AM -0400, Marvin Dickens wrote: I made an SFP footprint couple of years ago for a project. As I recall, this is a 20 pin DIP package with .8mm pitch Right, but the two rows are staggered. And then there is the cage to deal with. Let me look back through the retired files and see if I can find it. Cool. Thanks! - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [OT] MIT Flea
Guys - On Sun, Sep 21, 2008 at 08:53:29PM -0400, evan foss wrote: On 9/21/08, Stuart Brorson [EMAIL PROTECTED] wrote: But I did see this strange contraption from the street: http://www.luciani.org/photos/pic1/2008-09-21-mit-flea/IMG_1612.JPG Do you have any idea what it is? I think that is a gyroscope. Those things connecting the rings are likely resolvers or encoders of some kind. I think the word you're looking for is goniometer, specificially a two-axis goniometer. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: free-open workarounds similar to SolidWorks
Evan - On Sun, Sep 07, 2008 at 02:51:48AM -0400, evan foss wrote: I just have to wonder aloud what would happen if someone made a beer that was actually open sourced. Stallman would have to make a new saying to avoid confusion. http://www.freebeer.org/ http://en.wikipedia.org/wiki/Open_Source_Beer_Project I haven't tried it myself. :-( - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Laser diode operation?
Guys - On Sat, Aug 30, 2008 at 07:38:06AM -0400, Bob Paddock wrote: On Friday 29 August 2008 11:15:03 pm Robert Butts wrote: I'm using ten [laser diodes in] parallel. I WAS going to just use a 1 amp 5 vdc power supply with a 2.8 V zener diode to adjust the voltage to 2.2 V. Does not have to be complicated, but you never want to parallel LEDs/LASER Diodes as they are a current driven device. Right. The traditional and easy way to get a bunch of LEDs (or equivalent) to light up equally is to put them in _series_. Then you only need _one_ current limiting resistor (or fancier circuit). Can you trade in your 5V supply for a 24V supply? - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: suffix for Verilog include files
On Sun, Jul 20, 2008, [redacted] wrote: On Sat, Jul 19, 2008 at 1:09 AM, Larry Doolittle [EMAIL PROTECTED] wrote: OK, really stupid question: is there a standard suffix to use for Verilog include files? [chop] Where I work (a large and very widely known communications company), we use .vh . I got two votes by private e-mail for .vh, and no suggestions for anything else. I'm convinced! I have now switched to .vh in my projects. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: suffix for Verilog include files
Friends - OK, really stupid question: is there a standard suffix to use for Verilog include files? I need something different from .v, so my Makefiles and scripts can tell them apart: include files don't get listed on the Icarus command line, even though they are a dependency listed in the Makefile. I have used .vp and .iv myself in the past. If there is a consensus I will happily switch to it. Consistency is good! - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Gnetlist -g PCB
On Mon, Jun 30, 2008 at 12:00:48AM -0400, al davis wrote: On Sunday 29 June 2008, John Doty wrote: It looks to me that geda has mixed the concepts of discipline and direction. Yes, but the real problem is the mixing of such clerical concepts into what is really a set of applied physics issues. Interesting point .. There is nothing keeping you from describing things like a one femtoHertz oscillator or a new CPU with a 100 TeraHertz clock. Building it, on the other hand, might be a little difficult. I agree with both of you. Let me add a little spin: Most designs don't challenge conventional rules to enter applied physics territory. Some people are not qualified to design, analyze, and debug such circuits. Other people are, but they have better things to do. Even when they break new ground on part of the circuit, they still want their conventional control and monitoring junk around the outside to work right the first time, without some silly d'oh moment. As long as DRC covers the 90% usage case properly, and has a clean way to be told don't look at this part of the circuit, I don't have time or interest to shoehorn my understanding of the applied physics into DRC nomenclature, DRC can be useful for everyone. - Larry If we knew what we were doing, it wouldn't be called research! ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: (Vhdl help)
On Thu, Jun 26, 2008 at 02:56:22PM -0700, Ben Jackson wrote: On Thu, Jun 26, 2008 at 07:47:57PM +0100, Peter Clifton wrote: In the case of I2C where you only want inputs and pulldowns, 'O' is always 0 (zero) and T should be true when you want to pull down. My own i2c module has inputs sda, scl and outputs sda_pull and scl_pull. At the top level they're connected like: assign SDA_PIN = sda_pull ? 0 : 1'bZ; assign sda = SDA_PIN; I have lots of practice writing and using serial communication in Xilinx, including what I believe is I2C for a TCN75. Even though it's Verilog, I'll attach a working (production) module that gateways SPI and I2C devices to a non-real-time computer. And yes, buried in there you will see the line assign SDA75 = tcn_drive ? 1'bz : 1'b0 ; - Larry // sportx.v // Serial device support for MAX1202, MAX5742, TCN75, and ADF4001 // $Id$ // Larry Doolittle, LBNL // llc-suite Copyright (c) 2004, The Regents of the University of // California, through Lawrence Berkeley National Laboratory (subject // to receipt of any required approvals from the U.S. Dept. of Energy). // All rights reserved. // Your use of this software is pursuant to a BSD-style open // source license agreement, the text of which is in license.txt // (md5sum a1e0e81c78f6eba050b0e96996f49fd5) that should accompany // this file. If the license agreement is not there, or if you // have questions about the license, please contact Berkeley Lab's // Technology Transfer Department at [EMAIL PROTECTED] referring to // llc-suite (LBNL Ref CR-1988) // November 19, 2002: TCN75 support is obviously flawed and // incomplete; all other device waveforms need checking // November 25, 2002: all waveforms look proper in simulation; // Xilinx ISE 4.2 reports 32 FF, 70 4-LUT, 41 Slices `timescale 1ns / 1ns module sportx( input host_clk, // interconnect input host_we, // interconnect input [15:0] host_data, // interconnect output reg [15:0] data, // register SPORTX_DATA output [15:0] status, // register SPORTX_CNTL input select_data, // select SPORTX_DATA input select_cntl, // select SPORTX_CNTL output pll_muxout_, // interconnect output reg SCLK, // pin a output reg SDIN, // pin b output reg CS1202,// pin c output reg CS5742,// pin d inout SDA75, // pin e input DOUT1202, // pin f output reg PLL_CLK, // pin g output reg PLL_DATA, // pin h output reg PLL_LE,// pin i output reg PLL_CE,// pin j input PLL_MUXOUT // pin k ); // reads are passive // host_we is guaranteed to be valid for exactly one (posedge host_clk) // ADF4001 pins are kept separate for noise reasons. // Leave them quiet when using other devices. // end of Verilog interface definition // Software register map: // 16 bit data shift register // control: //0x01 running shared for all devices // devseltwo bits to choose active device // 00 - MAX1202 // 01 - TCN75 // 10 - ADF4001 // 11 - MAX5742 //0x08 MUXOUTfrom ADF4001 (read only) //0x10 CEto ADF4001 (1 to turn on chip) //0x20 LEto ADF4001 (0 during shifts) //0x40 tcn_ckhi force TCN75 clock high (use for start/stop) //0x80 CSto MAX5742 (0 during shifts) // // All serial devices share a common data shift register and a common // timing state machine. The software may only interact with one at a time. // // Software driver notes (also see the associated sportx_tb for example use): // // all: writing a '1' to the run bit starts a serial shift operation // to the specified device. Software should poll the status // register until that bit drops back to '0' at completion. // // max1202: put the 8 control bits into the msb of data, and trigger // a transaction. The 12 bits of the result land in data[14:3]. // CS pin handling is automatic. // //tcn75: Since the TCN75 SDA pin is open collector, there is no difference // coded here between reads and writes. The pin status is always // recorded in the shift register (data). Make sure to write a 1 // during any bit time that you want to receive from the TCN75. // Transactions use 10 data bits: 8 data, 1 ack, and one trailer. // Create the start/stop protocol in software, using the tcn_ckhi // bit of the status register. Writes to data[9] show up immediately // on the SDA pin; in general, data[9] of any given write should // match data[0] of the previous write. // // adf4001: data is written 8 bits at a time. Lower 'LE', send // 24 bits split
Re: gEDA-user: Using mm units in .pcb files
Steven - On Tue, Jun 10, 2008 at 02:57:33PM -0700, Steven Michalske wrote: Remember the high school science teacher docking points for not using units? It's burned into my skull! What unit should we define for PCB default units? They are mill/100, one hundred thousandth of an inch, or a dmil; deci-mil ha ha a pun for a unit :-P Nice try, but 1/100 of a mil is a centi-mil. FIrst p0st! - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: poll: How do you geda?
Sorry to tack on to another response. On Wed, Jun 04, 2008 at 01:15:24PM -0300, John Coppens wrote: On Wed, 4 Jun 2008 09:55:26 + (UTC) Kai-Martin Knaak [EMAIL PROTECTED] wrote: * What OS do you run geda applications on? Debian, Ubuntu, x86 and amd64. * How did you install your copy of geda apps? Either stock from the distribution, or build from latest CVS/git sources if I need a new feature. * Which apps do you use. What is your typical workflow? xcircuit - pcb - gerbv iverilog - gtkwave Xilinx gschem wasn't ready for prime time when I started. * Did you (have to) modify portions of geda to suit your needs? Not recently. * What is the general flavor of your projects? (analog, digital, HF) Analog, digital, both up to ~100 MHz. My attempts to go higher frequency have had mixed results. * What is the greatest weakness of gEDA? Churn in file formats and user interface. I know other people label this as progress, but it does keep me from advocating gEDA for non-hackers. Disorganized and questionable quality component libraries. This has been discussed to death, but without any concrete results. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: poll: How do you geda?
Peter - On Wed, Jun 04, 2008 at 06:41:25PM +0100, Peter TB Brett wrote: On Wednesday 04 June 2008 17:30:11 Larry Doolittle wrote: Churn in file formats and user interface. I know other people label this as progress, but it does keep me from advocating gEDA for non-hackers. I need to step in here -- there has not been a single change in the gschem schematic file format while I've been on the project. There have only been cosmetic changes to the gschem user interface while I've been on the project. I can only assume you're talking about PCB. Yes, PCB and xcircuit. I haven't used gschem. Both PCB and xcircuit attempt (and generally succeed at) back-compatibility, but not forward compatibility. That means I have to be careful to use the same version on my multiple computers, and if I upgrade, anyone else who wants to use my designs also has to upgrade. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: poll: How do you geda?
On Wed, Jun 04, 2008 at 02:04:34PM -0400, Stuart Brorson wrote: Just out of curiosity, who is maintaining xcircuit? Is it Tim Edwards? Is it under active development, or static? I use 3.6.130, released February 5, 2008 at 2:40am. I now see 3.6.131, released May 16, 2008 at 2:40am: Changed the package require -exact to package require in tkcon.tcl, so that xcircuit will work on Tcl/Tk version 8.5. Tim Edwards is still the developer/maintainer. reference: http://opencircuitdesign.com/xcircuit/changes.html - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [Icarus Verilog] Unable to synthesize synchronous process
On Tue, Jun 03, 2008 at 02:09:34AM +0400, [EMAIL PROTECTED] wrote: I've started with free Xilinx ISE, but now i'm trying to do my best to take part in icarus verilog community. Welcome! iverilog -tfpga test.v test.v:7: sorry: Forgot to implement NetCondit::synth_sync test.v:6: error: Unable to synthesize synchronous process. 2 error(s) in post-elaboration processing. Where is my mistake? What should i read to understand my problem? I guess you use the devel tree. If you really want to synthesize, you should use 0.8.6 instead. If you want to help port the synthesizer from 0.8.6 to current devel, read the source and start hacking! Synthesis in Icarus is historically weak compared to commercial tools. Steve mentioned to me privately that he might find time to think about this again in s23%%43qaazz [carrier lost] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus build problem?
Evan - On Thu, May 08, 2008 at 06:41:39PM +0100, Evan Lavelle wrote: I can't run configure after downloading from git and sourcing autoconf.sh. The output from configure ends with: checking for BZ2_bzdopen in -lbz2... yes checking for BZ2_bzdopen in -lbz2... (cached) yes ../../git2/verilog/vpi/configure: line 4002: syntax error near unexpected token `fmin' ../../git2/verilog/vpi/configure: line 4002: `AC_CHECK_FUNCS_ONCE(fmin fmax)' configure: error: /bin/sh '../../git2/verilog/vpi/configure' failed for vpi I get the same error when running configure in the Verilog directory. Any ideas? It works for me. Please describe your system, especially the version of autoconf. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Using 60Hz mains frequency for timing?
Randall - On Fri, May 02, 2008 at 12:33:03PM -0400, Randall Nortman wrote: Just a quick non-gEDA design question -- I have the choice between using the zero crossings of the 60Hz mains voltage or my MCU clock (generated from an 18.432MHz quartz crystal producing a 48MHz CPU clock via PLL built into the MCU) for low-resolution timing. 60 Hz mains timing is terrible. Use the crystal. The only thing mains can be used for is long-term (more than 1 day) absolute accuracy, and then only if you are really careful with both hardware and software design to avoid noise spikes, and your customer doesn't decide to run it from a generator or inverter. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Using 60Hz mains frequency for timing?
On Fri, May 02, 2008 at 01:06:47PM -0400, Ian Chapman wrote: Crystal usually cut to + or - 100 ppm for a general use like a CPU and it will not change too much with temperature and age. Ethernet crystals were at one time cut to a better spec 50 ppm. Special communications crystal can be a lot better. The mains are very good in most places for the morning alarm however in remote communities with diesel generators ... no way. Sounds like all of us are in violent agreement. But before you start thinking that crystals are _too_ wonderful, let me quote from my introduction to using network time standards at http://doolittle.icarus.com/ntpclient/HOWTO First, a note on typical 1990's and 2000's computer crystals. They are truly pathetic. A real crystal oscillator (TCXO) usually has an initial set error of less than 5 ppm, and variation over time, voltage, and temperature measured in tenths of a ppm (and an OCXO can reach ±0.3 ppm stability over ten years and 85°C temperature swing). The devices used in conventional PC motherboards and single board computers, however, often have initial set errors up to 150 ppm, and will vary 5 ppm over the course of a day-night cycle in a pseudo-air-conditioned space. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
Steve - On Fri, Mar 28, 2008 at 10:27:28AM -0700, Steve Meier wrote: On Fri, 2008-03-28 at 10:20 -0700, Larry Doolittle wrote: OK. Just be sure to give the FPGA direct access (via PHY) to Ethernet. The same concept also applies to network performance. I'd venture to say you want four RJ-45's: two for the traditional microprocessor and two for the FPGA. Good idea add to that taking advantage of the optical networking capabilities of the fpgas. If you're willing to make the jump from $30 to $300 FPGAs, that is. The cheap ones don't have the high speed serial capability. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
Guys - On Thu, Mar 27, 2008 at 04:22:34PM -0700, Jesse Gordon wrote: DJ Delorie wrote: http://www.xilinx.com/products/boards/ml410/index.html They have a lot of support chips on that board, though. Like the south bridge, CF controller, PCI bridge, etc. I was thinking more like every connector goes directly to an FPGA pin. Maybe one fpga for the cpu core and one for the peripherals, though. I like the idea. If the main FPGA was big enough, maybe it'd only need one, but I guess we're trying to avoid more then 4 layers, and big bga=more then 4 layers. But if two fpgas were sitting right besides eachother, with about 25 pins lining up, and just connected right together, (with qfp) the run would be short, straight, and all the same length, it could be over ground-plane layer there. I think considerable fpga-fpga speeds could be attained. If the run was short enough, it may /work/ without termination. By having several such fpgas in a row, each connected likewise to the one near it, or maybe having 1 in the middle then 4 around it, one on each side, I'm sure enough pins could be attained to feed all the peripherals. It may even be doable on a 2 layer board, but four is much more then twice as good as 2. (I think it's more then twice the cost too :-) Interfacing to the ram at high speeds could be tricky, so it might be better to have the ram in parallel (wider data bus) rather then longer address space, to allow faster byte/sec without faster addresses/second. All interesting ideas, but fundamentally not new. The bigger/faster/cheaper FPGAs get, the more interesting it gets. A few comments on details: 1. Self-reconfigurable FPGAs have been promised for years, but aren't ready, and probably never will be. Think carefully about the boot sequence, and how one FPGA can boot the next. Having more than one FPGA is probably a good thing. 2. For Ethernet, you don't want a PHY+MAC, just a PHY. The pin count is lower and the result is more FPGA-like. I have a demo of Gigabit-compatible IP/ARP/UDP in 200 cells plus 32 kbits RAM. I will probably even work on making it useful for real-time communications in the next year. 3. A large BGA can be useful even without a lot of board layers. Assume 1mm pitch and 5/5 space/trace. In concept, reaching all n^2 pads can take approximately n/2-2 routing layers, although that's an overestimate because many interior pads are power and ground. Practically, it takes six layers for 170 user I/O on a 256-pad BGA, and the layer count rises rapidly for those 600 to 1200 pad monsters. If you only route the outer four rows, however, you get 16*(n-4) pads with two routing layers (four physical layers with power/ground). A 676-pad package (26x26) gives you 352 routable pads like that. 4. You can do a lot with FPGA plus DDR SDRAM, outside of traditional CPU design. Just look at Elphel's model 333 camera. http://www3.elphel.com/ Ogg Theora _en_coding faster than most PC's can _de_code it. 5. I have always been impressed by Jan Gray's CPU in FPGA designs. http://fpgacpu.org/ Jan himself has moved on to other work. If anyone wants to talk shop about CPUs in FPGA, like how to add Cache, MMU, and SDRAM to a 32-bit Gray-esque processor, let's find a better list. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
On Thu, Mar 27, 2008 at 09:28:23PM -0500, John Griessen wrote: Larry Doolittle wrote: Self-reconfigurable FPGAs have been promised for years, but aren't ready, and probably never will be. I guess that's because the fpga makers seem to not want to let out their programming details -- probably because they let Mentor and Synplicity and the like do all their tools and THEY don't want it let out. Tools are certainly part of the story. But it also strikes me as a chicken-and-egg problem. The user's don't demand or exercise the tools because of the conceptual problems and the silicon limitations. On Thu, Mar 27, 2008 at 08:59:47PM -0400, DJ Delorie wrote: What about the new flash-based FPGAs? Maybe not as big, but they seem to be instant-on. I suppose we could have a CPLD sequence the boot/reset/run sequence. Where the boot information is kept isn't as important as how to reprogram it without risk of bricking the board. If we can fit it into 6/6 trace/space with 12 mil via holes, that's within spec for common prototype fabs (pcb-pool, specifically, which does 4 and 6 layer). 6/6 is doable if you slightly cheat the size of the solder pads. Now, if I could solder [a spartan-3 FB676] on my hotplate... :-) I have seen instructions for home-soldering BGAs. I haven't tried them myself, and I don't know what the size limits are. On Thu, Mar 27, 2008 at 09:34:27PM -0500, John Griessen wrote: If anyone wants to talk shop about CPUs in FPGA, like how to add Cache, MMU, and SDRAM to a 32-bit Gray-esque processor, let's find a better list. I'm not sure about as far as a MMU linux running processor in FPGA, I think of buying that in hardware, but how hard is it to take a ethernet MAC and program it to hook up to a low power C8051 from silabs and put the fpga machine in a Actel smallest igloo fpga? The small CPU jobs are certainly practical in small FPGAs, Jan's and many others. Opencores is riddled with them. But for the motherboard concept that started this discussion, I think people would be interested in something beefier. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
Jesse - On Thu, Mar 27, 2008 at 08:28:29PM -0700, Jesse Gordon wrote: Igor2 wrote: If we are at tools, I wonder... Is there an FPGA family that I could use without using non-free software at all? I was going to ask that very question. The closest I've come to free was xilinx's ISE Impact webpack which of course is only free to use and only free for non-comercial projects. I was wondering if xilinx would ever release the information to allow people to make a completely open source truely free synthesis tool. Of course, synthesis is the easy part, Icarus (almost, sort of) does that already. Place and Route is hard, especially because so little experience exists in the open source community. The real sticking point is bitstream generation, where Xilinx and Altera are traditionally anal. This question has a long history. Perhaps the most notable discussion is the 173-long thread titled FPGA openness in 2000 in comp.arch.fpga. I don't think anything important has changed since then regarding Xilinx or Altera. On the free front, we have the excellent research of Adam Megacz http://research.cs.berkeley.edu/project/slipway/ Too bad the targeted device is so pathetic. Also as a curiosity, see Reinoud's MPGA, an open source meta-FPGA. That one seems to have dropped off the 'net. Does anyone have an archived copy? - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PC emulator and HDL
John - On Thu, Mar 13, 2008 at 07:24:03PM -0500, John Griessen wrote: Larry Doolittle wrote: On Fri, Mar 14, 2008 at 12:19:30AM +0200, Ahmad Sayed wrote: The PC emulator will treat the HDL code as real hardware component. This style of simulation is of course useful. Steve W. and I have both done similar work. I'm not sure what the parallel port does in this method. Are you meaning the PC+parallel port emulates some hardware at speeds of parallel port wires? My interpretation is that there is hardware attached to the PC parallel port that is modeled by (and maybe synthesized from) HDL. That hardware interacts with software running on the computer. The goal is to model the combination of hardware and software, by making the actual software interact with simulated hardware. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: RFC: Footprint Builder
Robert - On Wed, Mar 05, 2008 at 09:24:48PM +, Robert Fitzsimons wrote: I decided to try knocking up a interactive program which could be used to create the footprints. Welcome to the club. I've to take a bit of a break until the weekend to work on another project, but I would appreciate your comments. Check to see what features you like, and can steal, from qfp-ui (part of stock pcb). Also I trust you have seen the non-interactive footprint builders like Darrell Harmon's footgen. See my previous rant on the subject: http://archives.seul.org/geda/user/Feb-2006/msg00656.html - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: multi-page hierarchy
gene -
On Thu, Feb 14, 2008 at 06:50:13AM -0500, gene wrote:
Larry Doolittle wrote:
Right. This is a prime example of the tools being expert-friendly.
It's no sweat for someone like me to add a perl script to the
processing chain to rename the resistors in a consistent and
design-appropriate fashion.
any chance you could share that script?
No sweat. That part is really only two lines of a perl
script that handles a lot of other features of my design
flow, like attaching power to all the banks of an FPGA
based on the pin definition file from Xilinx.
I'll attach the script. The key lines for this purpose are
s/inch_(\d)\/(\S+)1(\d\d)/$2$1$3/g;
s/\S+\///g;
which replaces instances of e.g., inch_3/R101 with R301.
I happen to have four instantiations of the subcircuit,
named inch_1, inch_2, inch_3, and inch_4. All components in
the subcircuit take the form C101, C102, R101, R102, U101, etc.
All the rest of the circuit needs to use components outside
those ranges, especially R1 through R99, but I do have another
section that uses R801-R899 etc. The second line above strips
off the instance names from those parts.
My flow actually starts from Xcircuit, not gschem, but as long
as they agree on the format of a netlist (I think they do),
this processing step is not affected.
You can see this script in its full design context at
http://recycle.lbl.gov/llrf4/
which I have mentioned many times before on this list.
- Larry
#!/usr/bin/perl
# see board2/scripts/post for other ideas
# input is combo.pcbnet
#
# cut and paste non-connected messages from pcb message log after
# an O command, into the mess2 file.
# awk '$8==U1{gsub(\,,$4);print $4,U1-$10}' mess2 mess2x
#
# mess2x is also a reasonable source of info for a .ucf file
if (open(X,mess2x)) {
while (X) {
chomp();
($a,$b)=split();
# print found $a,$b\n;
$fpga{$a}=$b;
}
}
%smap = (
GND= GND,
VCCINT = +1.2VD,
VCCAUX = +2.5VD,
VCCO_0 = +2.5VD,
VCCO_1 = +2.5VD,
VCCO_2 = +3.3VD,
VCCO_3 = +3.3VD,
VCCO_4 = +3.3VD,
VCCO_5 = +3.3VD,
VCCO_6 = +2.5VD,
VCCO_7 = +2.5VD
);
if (open(S,spartan3_ft256.csv)) {
while (S) {
chomp();
($dum,$dum,$pad,$sig,$dum,$dum,$dum,$dum,$dum,$bank)=split(,);
# print $sig $smap{$sig} $pad\n;
if ($smap{$sig}) {
$spartan{$smap{$sig}} .=U1-.$pad. \\\n;
}
}
}
while () {
chomp();
s/inch_(\d)\/(\S+)1(\d\d)/$2$1$3/g;
s/\S+\///g;
($name,@rest)=split();
if ($fpga{$name}) {$append=$fpga{$name};}
if ($append !/\\$/) {print $_ $append\n; $append=;}
elsif ($spartan{$name}) {$r=join( ,@rest); print $name
$spartan{$name} $r\n;}
else { print $_\n;}
}
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Re: gEDA-user: multi-page hierarchy
On Wed, Feb 13, 2008 at 05:13:45PM -0600, John Griessen wrote: gene wrote: When you lay out your board you get this fun issue that your refdes for a 0402 resistor is about 5 miles long. Really? I haven't tried this yet - but are you saying the refdes gets prefixed with the path? It makes sense for the nets, but not the refdes. The path in front is what makes each refdes unique and each refdes is the whole path to a symbol. If you present a simpler view it just means you are hiding the complexity somewhere, and at this point, gschem/gnetlist aren't hiding anything. Right. This is a prime example of the tools being expert-friendly. It's no sweat for someone like me to add a perl script to the processing chain to rename the resistors in a consistent and design-appropriate fashion. I would even argue that this is a common enough task that one of us should generalize and publish our internal scripts so that non-programmers can also work like this. Adding complexity to the existing tools, however, is probably a mistake. At most, they should have hooks to handle pre/post processing programs. For myself, I will always use a Makefile for that purpose. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: multi-page hierarchy
gene - On Wed, Feb 13, 2008 at 10:18:40PM -0500, gene wrote: So I wind up with something like /instantiation1/R1 and /instantiation2/R1. OK, fine. I can't say I like that, but I get it. I've always liked the notion of a unique base refdes per section. For example, 4 analog front-ends. All the same schematic, just 4 instantiations of it. I prefer to number them like instantiation-1 has refdes R100, instantiation-2 has R200, etc. That's my general pattern, too. But there are aways other parts to the rule, if for no other reasons that only parts of the board are not repeated. Larry Doolittle wrote: Right. This is a prime example of the tools being expert-friendly. It's no sweat for someone like me to add a perl script to the processing chain to rename the resistors in a consistent and design-appropriate fashion. So you write a script to massage the netlist? Correct. Sorry I wasn't clear. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: finding shorts with gschem
John - On Mon, Feb 04, 2008 at 06:13:51PM -0700, John Doty wrote: Does anybody use 4000 series CMOS anymore? Yes: Slow interfaces on noisy cables. Simple logic on unregulated power. Radiation tolerant circuits. High voltage mixed signal circuits. /me nods head Right, where high voltage means more than 3.3V. - Larry1/2 ;-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design with a 144 pin QFP
Simon - On Sun, Feb 03, 2008 at 01:26:40PM +, ST de Feber wrote: The device in mind is an Altera Cyclone-3 FPGA. Most probably the ep3c5. FPGAs are the easiest chips to lay out, as long as you keep an open mind about pin assignments until you're halfway through the layout. Unless there is some other complex part of the board, four layers is probably enough. One for power, one for ground, and the top layer has most of the routing away from the FPGA to its peripherals. That leaves one layer for anything that doesn't quite fit on the other three. Stare at a PCI Ethernet or SCSI card for inspiration on how routing is supposed to look. I use graphics cards as a model for boards with higher pin-count FPGAs. As for the function, it will do audio-dsp like functions. I2S in, 3 to 4 channel FIR filtering (1024-tap) and I2S out. When not filled completely i will try to add a simple uc. I suggest reading Jan Gray's essays (now all historical) on uc design in FPGAs: fpgacpu.org. He's a Xilinx partisan, but many of the concepts still apply to Altera. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus Verilog vvp32 on 64bit systems
Steve - On Thu, Jan 24, 2008 at 09:03:39PM -0800, Stephen Williams wrote: Does *anybody* use or even see value in the 32bit runtime support that Icarus Verilog includes in 64bit builds? Not purists like me, that have everything built from source on any given platform. The interest would presumably come from people who get binaries from third parties. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: a project documentation system
Peter - On Fri, Jan 18, 2008 at 10:45:12PM +, Peter Clifton wrote: Can you persuade your webserver to serve mime-types such as: application-x-pcb-layout application-x-pcb-footprint application-x-pcb-netlist application-x-geda-schematic application-x-geda-symbol If gEDA 1.3.x or later, and CVS pcb is installed correctly, this should cause the right program to load up automagically. (netlists just open in a text editor, but might get a mime-type icon) Cool. A new attack vector! - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Silkscreen over pads again
Friends - A pcb fab just complained to me about the perennial silkscreen-over-pads issue. In the most recent discussion I found http://archives.seul.org/geda/user/Jan-2006/msg00672.html DJ said This was fixed at one point, such that pcb itself would remove the silk over pins and pads, but I haven't migrated that code into the HID version yet. I'm using PCB from CVS, and gerbv 1.0.2 (stock Debian). Are there any patches out there that I can test? - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Silkscreen over pads again
Friends - On Thu, Jan 17, 2008 at 12:38:08PM -0500, Dan McMahill wrote: DJ Delorie wrote: We changed our minds about this. We changed PCB so that it showed silk over pads if that's what your design calls for, so if you see silk over pads on the screen, you'll get silk over pads on the board. The magic we chose to go with to deal with the fabs that can't handle cuts is to convert all cuts to multiple polygons instead, so that we never have to use cuts or negative layers. That was what we used to remove the silk, and too many fabs didn't like it. Which fab is it? Are they unable to fix the problem themselves? A DRC check for silk on pads would probably be good. In my past life, we always had in house reviews of the gerbers and weren't allowed to send them to a board vendor until there was no silk on the pads I think the message was actually from a turn-key board manufacturer, who will also buy the parts and stuff the board. They apparently ran a DRC as Dan did, before sending the Gerbers out for fab. Since it's not easy for PCB, they to agreed do the masking themselves. I don't fault them for noticing and asking me to do something about it. I agree that a DRC for this in PCB would be nice (hmm, switchable, default on, performed at the same time as the other DRCs). Then I'd take the time to fix all my footprints. But that doesn't let Levente http://archives.seul.org/geda/user/Jan-2008/msg00201.html do what he wants. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA website face lift
Ales - On Wed, Jan 09, 2008 at 02:49:15AM -0500, Ales Hvezda wrote: It's a New Year, so it's time for a slightly (very slight) new look on the gEDA (http://geda.seul.org) website. [chop] I humbly suggest you check your new pages against validator.w3.org. It's easy and fun! After you add a DOCTYPE and character encoding, if you have any problems give me a shout. The links in the error reports are usually pretty good about giving suggestions, though. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
