Re: gEDA-user: TO-92 Best Practices
On Tue, Mar 02, 2010 at 11:38:00AM +0100, Gabriel Paubert wrote: On Tue, Mar 02, 2010 at 02:01:51AM -0500, DJ Delorie wrote: For matching, can you just press them onto a pcb carrier? Something that plugs into a breadboard, and gives you three big copper pads to contact? Assuming holding them down with your finger or even just letting gravity do the work, it might be sufficient. From my experience, gravity is insufficient. The contact quality is too poor if you don't have anything to press the device against the pads. I was testing at ~1GHz, but it should not affect that much, except that you need some plastic stick insted of a finger (too much disturbance, probably stray capacitance). And at the DC extreme, the heat of the finger will make any attempt to match offset a joke (other parameters maybe not so much). So, no, usually fingers need to stay away from the DUT. -- There's one way to find out if a man is honest: ask him; if he says yes, you know he's crooked. -- Twain ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: opamp slew rate limiting
On Tue, Nov 10, 2009 at 06:08:41AM -0500, gene glick wrote: SR definition is SR = 2 * pi * f * Vpk Nope. That's the maximum *signal* rate of change for a sinewave. I think you know that, but since there seems to be a lot of vague misunderstanding about slew rate in this thread... So I need SR 6.28 * 5000 cycles/sec * 15 Volts, or 471,000 Volts/Second. If my math is right, that works out to 0.471 V/uS. Lots of margin there too, the part can do 20. That's about how it looks to me, too. 15V peak would be about 6db overdrive (IIRC that the opamp is on +- 7.5 volt supplies). I agree about the linear/saturation description, but couldn't find any hard literature on the subject. If that refers to the comment I think it does, then it's half wrong. SR is the symptom of NONlinear operation: it's the output rate of change observed when the input stage is saturated by an input signal that changes so quickly that it outruns the feedback. The saturated stage is usually then charging or discharging an internal capacitance with a more or less constant current, hence the relatively straight and predictable (but *not* always symmetrical) output slopes. Clipping is normally due to output stage saturation, and yes, there can be a significant recovery time due to (once again) earlier stages having gone into saturation trying to push the output to the unreachable level that would satisfy the feedback loop. There can be some recovery after slew limiting as well, though that's rarely as severe and is often insignificant. great point. Maybe I should increase the gain to force the saturation earlier into the cycle. I was trying just the opposite. Nah. You should use a good comparator with controlled hysteresis. An opamp, any opamp, makes at best a mediocre comparator. If phase jitter is important, as I believe you said it was, then you should be targeting a point very near the zero crossing for that critical transition, as that is where the sinusoidal signal has its maximum rate of change, and hence whatever noise is in the system will cause the least jitter. -- I didn't write a whole, free operating system, either. I wrote some pieces and invited other people to join me by writing other pieces. So I set an example. I said, I'm going in this direction. Join me and we'll get there. And enough people joined in that we got there. -- R M Stallman ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Using the power instead of fighting it
On Tue, Sep 29, 2009 at 11:11:25AM -0600, John Doty wrote: On Sep 27, 2009, at 10:54 AM, Martin Maney wrote: I suppose it depends on whether gEDA is only for those who use it for hours every day and thus find the cost of learning to and configuring things to work just the way they want them an obvious net win, or if it's desired for it to be useful to a larger audience. I think you have it exactly backwards. When you work on a project every day it isn't hard to remember the project structure and the operations you need to manipulate it. But the part-timer can't remember that stuff: it's extremely important to automate it. No, we agree, you just express it very oddly. wink How is a newcomer supposed to automate all this *before* they've learned all of the often obscure tricks (and over the years, a fair number of times the docs tutorials have said the exact wrong thing according to the enlightened advice provided on this list; or, to beat a dead horse, the right stock script defaults to a PCB layer stack that no one thinks is sensible, yet it's still suggested to use it). First you have to develop a clue about how it *should* work... and in many cases, Mr. Noob either doesn't get that far before looking for something that lets him get his work done (been there, did that... but for some reason I came back for another go at it a year or two later), or learns enough to bull through. Maybe he comes back and has a less difficult time of it the second time, and eventually sees things clearly enough to put at least a few of the most-used bits into a makefile - which is, as best I recall, about where I was when I got the gerbers off to the shop and had no excuse to spend more time tinkering. I have so far completed only a very few rather small boards using gEDA. That's the cost of learning I'm talking about, and I totally agree that casual users need better automation than gEDA has to offer - but for some reason you're violently opposed to such if it gets slick enough to be called integration. :-/ As it is, the people who *can* automate the process are exactly _not_ the ones who need the automation just to get things to work at all. I think you also overlook the value of a GUI integration layer in making it easier to recall things. The CLI tools may be sharp, but they offer minimal affordances, do nothing to make discovery easy, etc. And I say that as someone who more often finds himself arguing for having that cryptic but powerful CLI interface where it's lacking. :-) That's when the scripts are essential. They embody the project structure in a way that's easy to use. It's very handy to be able to go back to a project you haven't touched for a couple of years, make a small change, type make, and have all of the data products rebuilt. True, and been there many times, though so far just a weak version of it - after a month or two's interruption - with gEDA. I *love* heavy symbols. Must have confused someone else's comment with yours. Sorry! We already have a database structure if you look more than skin deep. A .sym file is a fine container for relations, so a directory containing .sym files is a relational database. Do we really need more? No, we need *less*. .sym files - we're talking about heavy symbols here, right? - tie too much together in too fixed a state. At best that directory is like a RDB with a nasty schema - everything crammed into one hugely denormalized table, with all the problems you'd expect from that. And that's arguably the real reason to be dubious about heavy symbols - they're the implementation of a lousy data design. (I'm going to have to think about this... it's either new or comes from a source I have no memory of, and at least right at the moment I'm very fond of the conceit.) I hope gEDA can do better, so that I can curse it less next time I reach that stage! Learn make. Know make; know it well. Doesn't help until you've sussed out just what sequence of steps, what CLI options, etc., to use. Seven years should be enough for that, sure. :-) ... so where's the set of standard make rules for gEDA files? They don't ship with (gnu)make, at least. While intended for software development, it's effective ... Make is fine, but the software development tool that I've found most insanely useful while developing hardware with gEDA is, hands down, version control. I prefer git, but mercurial isn't bad. -- If there is a lesson to be learnt from Adobe's eBook fiasco, it is that litigation is no substitute for well-designed software. -- The Economist ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Blind and buried vias?
I was going to comment on one point, but once you start writing... On Sun, Sep 27, 2009 at 06:16:42AM -0600, John Doty wrote: More useful and friendly to *what kind* of user? The kind that would prefer spending an hour mousing around to solve a problem once, or 15 minutes writing a script to solve it for all time? I suppose it depends on whether gEDA is only for those who use it for hours every day and thus find the cost of learning to and configuring things to work just the way they want them an obvious net win, or if it's desired for it to be useful to a larger audience. I'd be an example of that - although I have rather enjoyed the work I did about a year ago using gEDA, the fact is that I haven't had occasion to touch it since those boards got sent off. Sure, I have other projects in mind, but they've been stuck on the back burner, and seem likely to stay there for some time yet. Too many todos, too little time. People want prefabricated heavy symbols in a library, not considering how massive the problem is. Too many variables. What we need is an easier way to customize symbols for a particular project. And perhaps better BOM post-processing support, so the user can say I want to use footprint xxx and vendor part number yyy for all 100nF X5R capacitors in this project. gattrib is a nice tool for quick touch up, but not productive when you have hundreds of footprints to change. +1 about gattrib's shortcomings when there's more than a few items to tweak. I would like to add that some of that seems to be a really weird UI - things behave oddly compared to other GUI tools, IMO. OTOH, if there were a rich library of those heavy symbols you dislike, there'd be a lot less need for tweaking things (at least IME). But I have to agree that creating a huge library like that shouldn't be part of gEDA's mission, especially when manufacturer's so often make this stuff available... but in formats gEDA can't use. Yeah, it's hard. The database-driven idea sounds wonderful, but my impression is that it's a hella bike shed - lots of talk about it but little if anything of general interest gets done... or maybe everyone's waiting for one of the personal hacks to be just the color and glossiness they wish for. And it still sounds like a lot of setup work for casual or occasional use. The biggest hole in the gEDA documentation concerns the scripting that gschem/gnetlist can do using Scheme. There's no real API documentation here, so few are aware of the latent power here, and even fewer know how to harness it. +1e6 - not that Scheme is my favorite scripting language, but if there were a documented API it would be a viable option. And many who find shortcomings in gEDA don't want a toolkit. I have very mixed feelings about that, though the above has mostly come down on one side. And I'm not sure I'd call it a toolkit - some of the pieces just don't work together very well. The mess of issues that arise between gschem and PCB are perhaps the most discussed, but all the parts I've had occasion to use feel more like a random collection of tools than a proper toolset - one size Phillips screwdriver, a couple of flat blades but none really small or really large, a hacksaw blade but you have to make your own frame for it... The individual parts are good quality, but... But I'm extremely grateful that gEDA *isn't* a massive time-wasting integrated point and click thing designed for sales So am I, but I don't think that's the only kind of better-integrated thing that *could* be made, even if the commercial EDA toolmakers don't have a clue about it. :-) I hope it stays that way. I hope gEDA can do better, so that I can curse it less next time I reach that stage! -- [the combination of iPod and iTunes is like] buying a 21st-century device to live in the seventies. -- Wes Phillips ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Blind and buried vias?
On Sun, Sep 27, 2009 at 01:45:46PM -0500, Bill Gatliff wrote: Martin Maney wrote: +1e6 - not that Scheme is my favorite scripting language, but if there were a documented API it would be a viable option. OT, but Gimp also uses Scheme. Another app I've never yet attacked from the loadable script direction, although in the case of the Gimp I've heard that other languages can be used, Python in particular. :-) And IIRC GnuCash is full of Scheme (or is it another of the free lisps they used?), and frankly that's an app which I use only because the alternatives have been so bad (by now, there's a lot of momentum and all that data that would need to be migrated adding inertia). Slow and not very flexible, though perhaps the latter is because I don't think I should need to learn to write an extension to do trivial things. Or maybe my notion that one short line of SQL is a fair analog for trivial is a bit off. :-) -- One lesson I've learned from my years as Linux's hood ornament is that there's something worse: some folks can't be content to just take things too seriously on their own. They're not happy unless they can convince others to go along with their obsession. -- Linus ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: copper fill
On Wed, Aug 26, 2009 at 09:19:06PM -0400, DJ Delorie wrote: Maybe it's just now becoming an FAQ, but it's been confusing people all along. Maybe it's not a very good default. It's not the default. It hasn't been the default for a long time. IIRC it comes from gsch2pcb, which has a built-in starter board, which has the wrong defaults. ...which is, or was up until not so long ago, the way most if not all the tutorial examples taught us to use the tools. I totally agree with both it's not a very good default and it's not PCB's default, but if you want to be able to say that it's unqualifiedly not the default then other parts of gEDA need to be let in on that plan. Just sayin' - I haven't had occasion to use gschem/PCB since around this time last year. Too many projects, too little time. :-( -- The true danger is when liberty is nibbled away, for expedients, and by parts. -- Edmund Burke ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Can we fix the HTML stripping on this list?
On Tue, Jun 09, 2009 at 11:12:40AM +0200, Gabriel Paubert wrote: What does HTML stand for anyway (and all these makeup languages) ? My wife claims that her immediate thought on seeing HTML is hate mail. -- Here's my message to the record industry and its allies: I'm not a thief. I'm a customer. When you treat me like a thief, I won't be your customer. -- Dan Gillmor ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: (no subject)
* Spice netlister for gnetlist R5 1 +9V 1M V1 n0 0 AC R4 0 4 100K R3 0 3 470 Q1 1 3 2 2N5245 R2 2 +9V 1K R1 0 1 1M C3 2 4 4.7uf C2 3 0 .052uf C1 n0 1 4.7uf .END I don't see a DC source connected to the +9V node. -- Unlike some other template languages, you can not arbitrarily put Python code into a [Django] template. The language is intentionally limited so as to encourage you to properly separate your presentation logic from your business logic. -- Jeff Croft ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: footprint
On Mon, Nov 03, 2008 at 07:42:56PM +, Peter Clifton wrote: Either teach gsch2pcb to spot these and complain (short term), or in the Absolutely. It should always have done that. :-/ Bonus points for some heuristic which can spot if the PCB file obviously just contains one element, and adds a single-click fix this problem button to the resulting dialog box. Or maybe provide a less obscure and error-prone way to create the footprints in the first place, since no one seems to be able to do any real work without creating at least a few of the things? Myself, I've always found it 'way less trouble to create footprints by editing the file as text. I've done more symbols that way than t'other, too, but that was partly because I started with footprints and didn't realize that gschem has more usable support for doing that in the GUI. Still, if I were creating a simple variation on an existing symbol (most any heavy symbol), I think I'd still find the text editor more productive. -- One lesson I've learned from my years as Linux's hood ornament is that there's something worse: some folks can't be content to just take things too seriously on their own. They're not happy unless they can convince others to go along with their obsession. -- Linus ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
On Tue, Oct 28, 2008 at 02:49:37PM -0400, DJ Delorie wrote: What about high precision ADCs? I'm working on a design using ADE7753 power monitor chips (16-bit ADCs) , and their own app note (AN564) shows a ferrite isolating analog ground, and a 10R resistor isolating AVdd. http://www.tentlabs.com/Components/Shuntcomp/assets/Supply_decoupling.pdf -- The reason [limited term of copyright is] important is this: Publishers are in the business of expanding capital. The writers who supply them are in the business of expanding civilization itself. -- John Bloom ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Howto get a layout print with part numbers/values?
Is there an easy way to get a layout print similar to PCB's fab.ps but showing the part number/value (what PCB calls the value, and doesn't seem to use except in the BOM outputs)? I'm thinking that something made from the .xy file, printing those values rotated and placed would be close enough. The latter is probably what I'd throw together if I needed this badly, but at this point I'm inclined to think it would cost me time rather than save it. (whereas asking here costs very little time, and I have too many other chores to do while waiting to see someone knows of an easier way to do this for that time to count at all, at all grin) Thanks! -- The avoidance of idiocy should be the primary and constant concern of every intelligent person. -- Nero Wolfe ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Howto get a layout print with part numbers/values?
On Sat, Aug 30, 2008 at 03:14:01PM +, Kai-Martin Knaak wrote: To display the values rather than refdes at each component, choose from the menu (I assume, you use the GTK-GUI): View - Displayed_Element_Name - Value This setting affects the Postscript output too. If I want to populate a board, I do two postscript outputs. One with refdes and another one with values activated. BTW, I'd love to see a way to avoid this tedious double printing. Thanks, that worked pretty well. Easier than working from the drawing with component names and cross referencing it as I place 'em, anyway! The best hack it myself thought I'd had was to take the .xy file, which contains all the component names and value strings as well as placements and rotation, and generate output - postscript, I guess - with the values placed accordingly. It would be a bit schematic, especially where the mark isn't body centered, which is most of the components here (leaded). I was also dubious about how much time I'd save overall doing it that way. :-/ -- One discharges fancy homunculi from one's scheme by organizing armies of idiots to do the work. -- Dennett ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: panel2pcb bug
On Thu, Aug 28, 2008 at 11:44:49PM -0400, DJ Delorie wrote: Try this patch to panel.pl: - next if /\b(Via|Pin|Pad|ElementLine|Line|Arc|ElementArc)/; + next if /\b(Via|Pin|Pad|ElementLine|Line|Arc|ElementArc|Text)/; The first board is used as a template for the panel, which is probably where the extra text came from. That did the job for the original panelization job - just realized I haven't tried it with my minimal test case. I'm sure that one's okay, too. :-) Thanks! -- I've just realised that one of the things I really hate hate hate about Windows is that it doesn't have any personality. It's corporate and it hates me but it wouldn't ever do anything but smile falsely and refuse to talk to me. -- Jo Walton http://www.zorinth.net/bluejo/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: panel2pcb bug
Unfortunately, this bit me on a board with a top-side ground plane, and I didn't catch it until I got the boards back (1) ... perhaps because much of the erroneous copper was lost in that plane. What I've found - just did a simple test case that shows it - is that if one has a copper legend (text in the component side copper layer) of the first board given to pcb2panel, and that board needs to be rotated (counterclockwise tried) while editing tmp.pcb, then the copper legend from that board will appear twice in the output of panel2pcb: once where it should be, and again where it was in the original layout produced by pcb2panel (if that had had actual board elements in it rather than just the board outlines). Interestingly, my test case took two copies of the same board, which contained only a text legend in upper left part of the board. Both were rotated and repositioned in the same order left to right (after resizing the virtual board; it was resized back to the result's size before saving tmp.pcb). panel2pcb produced a board with a spurious copy of the first board's text as described. The second board's original text position was within the result's outline, but there's no copy of it in the result. Archive with files at http://www.two14.net/~maney/pcb2panel-bug.tar.gz (1) Advanced Circuits bare bones prototypes with one day turn, no silk or soldermask. I was in a bit of a hurry by the time I'd finished all the little projects that were being composited. Boards look very nice - the tinned surfaces (I believe they said these are all leadfree now) look really neat, more white than shiny silvery. Three 5 x 10 boards (one to break, one to play with, one to make as clean as possible for demo) were about $130 with 2nd day shipping. Could have gotten 4 with masks and silks for just a bit more ($33 special), but by the time this was ready to send off I didn't want to have to explain another week's delay. :-/ -- We found that we were making mistakes due to the complexity. Then we wrote scripts to write the configs for us, and using these scripts, we made mistakes in a faster, more automated manner. Something needed to be done. -- Jeff Allen, A Gentle Introduction to Cricket ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How to layout footprints overhanging edge of board?
On Mon, Aug 18, 2008 at 06:12:20PM -0400, [EMAIL PROTECTED] wrote: The wiki shows how you can make your outline by opening your *.pcb file with a text editor (like gedit or emacs) ... which is a quick way to get accurate results if you're comfortable working that way. It's good to have an escape hatch to get around the program's limitations... as long as it's not necessary in the vast majority of cases! -- GUIs are just what some developer thinks you'll be needing -- PJ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: printing from PCB
On Mon, Aug 11, 2008 at 01:38:44AM -0400, DJ Delorie wrote: Use the export-postscript option. D'oh! I really was up too late. Thanks! -- vi is a microcosm of the Unix world. Don't expect to learn all of it at once; perhaps you shouldn't expect to learn all of it at all. -- Jon Lasser (Think Unix) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Footprints over the edge
On Fri, Aug 08, 2008 at 01:21:51PM -0400, [EMAIL PROTECTED] wrote: What if you have an outline layer that you hang the parts over the outline? From what I saw yesterday during a major what if revision, PCB doesn't care a hoot if parts are inside the outline or not, as long as they're within the configured PCB size (it was picky about drawing the outline if the line would run over a pin, though; dunno about dropping a pin on top of it, but they could be dragged across it just fine). As I also inadvertently discovered, however, pcb2panel pays no attention whatsoever to the outline, so if you're panelizing you need to set the real size anyway... You can make two footprints for your over-the edge parts ... say one without the the silk information that you're using for alignment. After doing the layout, switch to the footprint without the silk (?). That would work, but doesn't seem to me to be an improvement - at least not given that I already have the connectors I need for now in mark over the edge form. :-) I should give it a try next time I need to create a horizontal PC mount connector and find out. As for hanging parts over the outline layer ... it'll come down to your board maker. I don't think PCB will shear off the stuff over the line (I suppose someone could make it so(?)). Either they won't notice because they automatically trim anything outside of the outline, or they'll suspend your job until you tell them it's okay. I've sent boards to advanced circuits before and they didn't even notice there were parts of connectors (in silk) hanging over the edge. Which suggests a variation - just one footprint with a mounting plane indication in silk (and perhaps indicating the required clearances for mounting as well), the rest of the outline designed to stay within the likely board area. Though that still only works for the two free sides if panelizing... -- I'm not proud. We really haven't done everything we could to protect our customers ... Our products just aren't engineered for security. -- Brian Valentine, Microsoft Senior VP in charge of the Windows development team ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: printing from PCB
This may just be me being up later than I should be working on this, but I can't find a clue just now: can PCB be asked to print just the one or two pages I want rather than the set of 12, most of which just become needless waste paper as soon as they come out of the printer? How about getting it to print to a file - it might be cumbersome, but then I could somehow get just the pages that are useful. I briefly had high hopes for the separate files checkbox, but it didn't seem to have any effect at all. :-( /me goes to bed, which /me ought to have done an hour ago... -- The avoidance of idiocy should be the primary and constant concern of every intelligent person. -- Nero Wolfe ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Footprints over the edge
On Wed, Aug 06, 2008 at 02:04:14PM -0500, Martin Maney wrote: will mount to. After pondering this for a while, I have come to the not really savory conclusion that a small kluge is as good a solution as possible: I placed the footprint's mark on the center line of the connector's axis, in the plane of that external panel. So in normal use these would all be placed somewhat off the edge of the PC board, which doesn't seem quite right, but does seem less awful than having no indication of the mounting plane present at all (really didn't care for having a silk line out there, although the vendor I expect to be using says they simply delete such extraneous silkscreen marks). As it turns out, there are issues with having anything off the edge of the board. As I was reminded when trying to juggle some changes found only after I'd reduced the board dimensions to the actual size (1), you aren't allowed to push silk over the edge. In a simpler test situation, PCB didn't seem to be bothered by having the mark hanging off the board, but when I had tried to make changes to the real board after sizing it, I got all sorts of weird behavior. Some things couldn't be moved. At least once it locked up (well, nothing could be moved; exiting was an option). At one point after making the changes - this was before I'd seen any of the odd behaviors - it would segfault trying to load the finished board. So there are drawbacks to abusing the mark to indicate the position of a mounting plane that in the nature of such things needs to be (slightly) past the edge of the PC board... at least with PCB version 20080202. (1) speaking of setting the board size, is there a way to do that other than editing the file by hand? I'm sure I used to know the answer to this, but I can't find anything about it now (which is why I suspect it's still done by hand). -- Self-pity is like sitting there and peeing your pants: at first, it's warm and comfy, but pretty soon it gets cold and then it starts to stink. - anonymous, as is traditional ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Footprints and their symbols, conventions for
A couple of questions that have come up as I've been making some symbols and footprints for various parts for a project that I need to send off real soon now: Looking at Bill Wilson's guide to defining transistors (1), despite an initial feeling of unease, I find I'm pretty much convinced this is a good plan. So how come I don't see evidence that it's ever been implemented (or where did I not look to find it)? A couple of parts I needed to draw both symbols and footprints for are PC-mounting connectors for external connections - so they need to be mounted at an edge of the board, with attention to aligning their individual mounting planes with the intended location of the panel they will mount to. After pondering this for a while, I have come to the not really savory conclusion that a small kluge is as good a solution as possible: I placed the footprint's mark on the center line of the connector's axis, in the plane of that external panel. So in normal use these would all be placed somewhat off the edge of the PC board, which doesn't seem quite right, but does seem less awful than having no indication of the mounting plane present at all (really didn't care for having a silk line out there, although the vendor I expect to be using says they simply delete such extraneous silkscreen marks). There was one more... oh, right. Not immediately relevant, but pondering the location of the mark for the horizontal connectors led me to think about the footprints for vertical mounting versions. In this case it seems to me that the mark should be placed at the center (for a round bodied connector) or other mechanical reference point. As with the horizontal sort described earlier, the mounting requirements are what really determines the placement, and PCB has to accomodate the resulting pad positions, be they on the grid or off. At least that's how my thinking is working today. :-) (1) http://geda.seul.org/wiki/geda:transistor_guide -- During much of that epoch [the thirties and early forties], I gained my livelihood writing for the silver screen, an occupation which, like herding swine, makes the vocabulary pungent but contributes little to one's prose style. -- S J Perelman ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: geda 1.4.0 in Hardy - is xgsch2pcb supposed to work now?
Having as my main - and not pleasant - memory of using the geda/PCB tools half a year ago be the incredibly annoying repetitive typing of commands (both at the normal CLI, where the really common ones could be scripted, as well as inside PCB, where... well, I never did, anyway), I thought I'd take the fresh new install for a spin and give try xgsch2pcb. It worked fine for the project I'd finished half a year ago, so I thought I'd give it a small piece of the upcoming one to try. Had to create a symbol, yeah, boring and annoying, but old hat - schematic entry went well enough, shook the rust off the muscle memories. Then xgsch2pcb just tanked. Couldn't find any of my footprints. I couldn't find anything that said anything useful about how to tell it where to find the footprints. No provision for it at all, at all, int he x-- interface. Tried variations on the elemnts-dir lines shown in one tutorial (buried under mounds of finger exercises - I do wish there was documentation for this stuff, not just rambling, ill-organized narratives. no, sorry, I can't write it - if i could, I might be doing it, and i certainly wouldn't need to ask this question. oh, wait, you aren't the project who always responds to complaints about the docs by saying so send a patch. never mind...) ... So if I pu them in the project then running gsch2pcb by hand works just fine - finds the footprints as expected. But if I load that project file into xgsch2pcb, it just goes blank - all the controls grey, can't do anything (it does show the right name in the PCB file slot, IIRC). So what's the secret? Or is this just something that needs another year of simmering, as I think someone put it about a year ago? Thanks. -- And in the end, reality always tends to hit theory hard in the face when you least expect it. - Linus ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [gattrib] OS X cut/paste
On Thu, Dec 13, 2007 at 09:36:35PM -0700, John Doty wrote: On Dec 13, 2007, at 9:19 PM, Dave N6NZ wrote: Is there something wacky about OS X's implementation of X11 w.r.t. copy/paste, or have I stumbled into a gattrib bug? When in gattrib, I can select and copy (or at least appear to copy) data from a cell, but the paste menu entry never activates. I've never seen menu paste activate in OSX X11. Paste current selection, X11-style, using option-click or middle click. However: Using the version packaged in Ubuntu Gutsy (200706-something), I had rather the opposite experience: the usual X11 mouse select/paste has never worked for me, but the (right-click context menu) paste does. Well, except when it doesn't, but I'm not sure if the pins tab is supposed to be of any use - the only thing I tired to fixup that way ran into can't paste (probably only tried to use context menu?) as well as you can type new text in but it will be reverted (when focus leaves that cell, IIRC), so I went back to hacking in a text editor. I've also found that gattrib (only) is quite dysfunctional when working remotely through an ssh tunnel. gschem and pcb both work fine, albeit very, very slowly for some things (or all things when the tubes are feeling clogged), but in gattrib I never get anything but a hollow cross mouse pointer and can't do anything to the data cells (scrolling, menus, etc. work okay). The X server in this case is on a Feisty install, client on the same Gutsy machine. This works from gattrib to other apps, but it doesn't work when gattrib is the destination of the paste. I think this directionality matches my experience. I'm sure the can't paste from elsewhere into gattrib part is ringing a bell. -- An education that does not teach clear, coherent writing cannot provide our world with thoughtful adults; it gives us instead, at the best, clever children of all ages. -- Richard Mitchell ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Pads do not clear polygons
On Mon, Dec 10, 2007 at 02:24:29PM +, Peter Clifton wrote: PCB and gsch2pcb both provide default layer groupings. It depends on which you started your layout with, which you'll get. Yes. The backwards masking item was created in PCB, with a dotfile that had gotten scrambled somewhere along the way. Likely I hadn't noticed before because aside from simple little tests I'd been working with layouts initialized by gsch2pcb that brought in their own sane layer stack. That mixup was definitely *not* PCB's default, as it was sane when I ran it from a test account that didn't have a messed-up (or any) local config in ~/.pcb I really hope neither of these is setting the component and solder stackup wrong! Nope. Their defaults are different (and gsch2pcb should be easier to change than editing the source (IIRC the FAQ item I just skimmed over)), but they are both sane by default. File-Preferences Layers option on left, Groups tab on the right pane. Yeah, that was it. :-) And I had even found it once before... -- During almost fifteen centuries has the legal establishment of Christianity been on trial. What have been its fruits? More or less in all places, pride and indolence in the Clergy, ignorance and servility in the laity, in both, superstition, bigotry and persecution. -- James Madison ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Pads do not clear polygons
On Sat, Dec 08, 2007 at 10:12:45AM -0800, Harry Eaton wrote: Actually this is simply that you have the layer named component on the solder side and the layer named solder on the component side. That's a really bad way to set up the layer groups. Yes, that seems logical. As best I recall *I* didn't do any setup of the layers - that was how PCB had them by default. So of course I never thought to check that. That's interesting - it's in ~/.pcb/preferences, and it does seem to be different than what it sets up de novo, but I have no memory of intentionally changing groups, either through the GUI or by editing preferences (well, until I edited it just now to put it back to sane). Speaking of the layers/groups GUI, I stumbled across that once upon a time, but now I can't find it. Hints? Thanks! -- [the combination of iPod and iTunes is like] buying a 21st-century device to live in the seventies. -- Wes Phillips ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
On Wed, Dec 05, 2007 at 08:07:45AM +0100, Bert Timmerman wrote: I think we should not create heavy symbols on build time but during run time (when the part is needed). +1 What's the difference between a light symbol and a heavy one? It's just that the heavy symbol has more attributes that specify it for a particular component in various ways, no? And so it's really just about what you begin with when you add a new symbol to the schematic, unless you expect that a heavy were resistant to being edited (those heavy attributes nailed down as it were) or... other things? Levente Kovacs has set up a database concept which could be expanded on (the bookmarked link I have does not seem to work anymore). In this way we could have both: generic light symbols and single purpose heavy symbols. My thinking so far - and it's certainly not complete! - has been that with a bit of care light and heavy symbols should play nicely together. It may not be this simple when all's done - the discussion about FPGAs suggests there may be inherent complications I'm not thinking of yet. It's certainly not so simple to the extent that the schematic editor needs to do stuff (beyond editing and maybe displaying) with the attributes... See also: http://www.seul.org/pipermail/geda-dev/2007-September/003665.html Might be copies of the files at http://web.interware.hu/lekovacs/ - try poking in the Public files section. I'm not sure what's going on there - clicking on things seems to cause unexpected changes, and some intriguing filenames vanished and I couldn't get them back again... -- You arguably have quite a few inalienable rights, but being taken seriously isn't one of them. Neither is being respected. -- Rick Moen linuxmafia.com/~rick/faq/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
On Wed, Dec 05, 2007 at 09:56:41AM -0800, Steve Meier wrote: I also agree that flat files really arn't a good way to capture a lot of relevent information. I shudder thinking about a library of 10 million resistors one for each manufacturor each package, each value etc. This reminds a little of something I stole for the sig-quote database (which is just a bunch of flat files, as it happens, but nowhere near a million of them grin): This is like making a car shorter by cutting off a few inches from each end with a Sawzall. Of course there's little benefit, because that's a dumb way to do it. There would be ten million resistor symbols only if you ignore the natural regularities of that universe of components. This does require a little more logic, to apply the reduced volume of tabular data appropriately. And, yeah, those things are a little ad-hoc. And some things will be so much their own weird thing that they do need a totally unique description per part. blinkSo it goes./blink -- And in the end, reality always tends to hit theory hard in the face when you least expect it. - Linus ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [pcb] first board docs
On Wed, Dec 05, 2007 at 10:22:46AM -0800, Ben Jackson wrote: On Wed, Dec 05, 2007 at 11:35:03AM -0500, DJ Delorie wrote: Comments? Ideas? Don't shy away from new symbol and footprint creation. That's a very necessary part of building any but the simplest boards. +1 The tutorials I saw all looked so simple that it was quite a shock when I tried a real board (c. two dozen simple parts) and found that the transistors all didn't work because of the EBC vs 321 mismatch. And finding the right names for the m4 footprints was another surprise - don't recall where I came across a probably incomplete list that was adequate for that layout. Hmmm. One thing I had fun with was the odd and unanticipated behavior of a drawing frame - I wanted to switch to portrait, I think it was, and while it's easy to stick a frame and title block in, until you stumble across locking it down it tends to get selected and moved around accidentally a lot. :-/ It's not that it's very obscure, just that when everything is new, there's a lot of stuff you don't yet recognize... I'd actually like to see a video that goes through the entire process so you can't cheat and skip steps... The not skipping steps is important, but I don't care for an actual video. It's too easy to miss details that pass by - they're there, they just aren't as obvious as if they had to be mentioned in words. But both would be no bad thing. :-) -- There is nothing perhaps so generally consoling to a man as a well-established grievance; a feeling of having been injured, on which his mind can brood from hour to hour, allowing him to plead his own cause in his own court, within his own heart, and always to plead it successfully. -- Anthony Trollope ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Symbols and footprints and stuff, oh my
So I've been fairly happy with these tools (currently using the packaged stuff from Ubuntu's Gutsy release), but there are a couple little things I've run into, aside from the peculiar behavior that arises when one tries to make an oval pin and use it in a ground plane... So I did a smallish circuit full of discrete transistors and Rs and Cs, and found usable footprints for all of them, but the pins from the transistor symbols - npn-2 and pnp-2 - didn't match the numeric pin names on the footprints. gsch2pcb spit out a script that I would have thought was intended to deal with that sort of thing, but no, it's all just identities like this: ChangePinName(Q9, E, E) ChangePinName(Q9, C, C) ChangePinName(Q9, B, B) I thought I did everything as described in the schematic-to-pcb writeup, but if this makes you think I forgot a step don't hesitate to mention it, of course. Then there's the footprints, which are good enough to use but not ideal (eg, the m4 TO92 calls out pin 1 backwards from what seems to be the usual practice for that package, at least for the inline-pins variant; then too, I don't really want that square pad, useful as it was for identifying the numbering the footprint used). While chasing links all over creation, I came across Bill Wilson's discussion of transistor pinouts: http://furrr.two14.net/cgi-bin/dwww/usr/share/doc/geda-doc/wiki/geda_transistor_guide.html At first I didn't care for it, having used other tools with a more heavyweight symbol approach, but I've decided he's on to something. I'll talk about a half-formed thought about a possibly better compromise between lightweight and heavyweight symbols, but for the moment I'm just wondering if (1) Bill's approach is generally approved of, and (2) if anyone's already run up footprints (I guess the existing symbols will suffice, aside from that letters vs numbers thing) for this approach. Thanks! -- ...and of course you must be careful not to overwrite the bounds of memory blocks, free a memory block twice, forget to free a memory block, use a memory block after it's been freed, use memory that you haven't explicitly allocated, etc. We C++ programmers have developed tricks to help us deal with this sort of thing, in much the same way that people who suffer severe childhood trauma develop psychological mechanisms to insulate themselves from those experiences. -- Joseph A. Knapka ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Symbols and footprints and stuff, oh my
On Tue, Dec 04, 2007 at 06:49:10PM -0500, Dan McMahill wrote: This is a known problem in the current flow. I think the right answer here As you'll see, I don't disagree, basically, about the long-term answer. Are there any shorter-term solutions planned, or is that the realm of a little sed script or some such that each of us arranges as we prefer? is to use a script to generate a library of heavy symbols for things like transistors. Search for a post by me that has something like symbol generator in the body. My thinking, as far as it's gotten, goes something like this: 1) it would be really nice to be able to maintain close compatibility with the lightweight symbol approach. One thing I don't like about really heavy symbols (at least in the form I've encountered them in other software) is that they're a pain to change (this is likely more of an issue for schematic - simulation). In principle there could be a convenient change [transistor] type, but it always seems to bite me with a half-assed let the user delete it and put a new one in by hand, with messye details like part numbering and such left to fall where they may. So my thoughts are along the lines of what would be the least that would allow the glue tools (schematic - netlist, - minimal pcb, etc.) to do the work? For transistors, the convention seems to be to use, eg., value=2N3904. Now, suppose there were a package=TO92 attribute, and a simple table of value+package - footprint+pin_mapping... with the option to override the footprint at least with an explicit one for backwards compatability (or a package not in the table)... Something similar (perahps the same table?) would take care of simulation, though for most parts I'm familiar with the package wouldn't change much except the thermal resistance. But I don't play around in the GHz range, so I dunno if it should be one table or two. Anywhow, this doesn't *require* any changes to gscheme (or PCB or *spice), though there's certainly room to make it more conveninent to select parts there. But if I were going to try for a proof of concept - which I really haven't time for right now, gotta *use* the programs to get some boards prototyped in the next couple weeks - it could be done by hand and wouldn't be much different than current usage that way. On some other symbols, you might see things like the pin called 1 being renamed to IN or OUT. That file is purely for cosmetic purposes, i.e. if you skip it, your final artwork will not change. Ahhh. It did do something with + and - for polarized caps, didn't notice if it was actually necessary. Then there's the footprints, which are good enough to use but not ideal (eg, the m4 TO92 calls out pin 1 backwards from what seems to be the usual practice for that package, at least for the inline-pins Does it match the JEDEC drawing? I thought I'd come across a scan-in-pdf of the TO92 docs, but I can't find it now; perhaps that's at the lab. I do have the closely-related TO226, and JEDEC doesn't show pin numbers on that. It refers to pin two w.r.t. the triangular pinout (leadformed from inline or molded that way), but of course that's the same either way. :-( I hacked together a proof of concept thing for transistors and it works well. I posted it to the list a while back. I'd send again, but I'm in the middle of trying to find a computer to read that hard drive :( Bah, more stuff I need to look for. :-) -- Happy Holidays! Cry Charge it! and let slip the dogs of more. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
