Re: gEDA-user: cygwin geda tools

2011-09-13 Thread Peter Baxendale
On Tue, 2011-09-13 at 06:30 -0700, Colin D Bennett wrote:
 I want to recommend gEDA to colleagues and online contacts, but
 unless I can point them to a one-click Windows download, gEDA won't
 be considered -- it'll surely be KiCad or (grimace) EAGLE.

It's a one click download but remember its cygwin, not native windows.
That puts some people off, although with the import schematics feature
in pcb it's now possible to pretty well avoid the command line (if
you're careful with paths).

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Re: gEDA-user: Win32 build with native printing support (via Cairo)

2010-01-27 Thread Peter Baxendale
I've done a little bit of experimentation but not found much.

I have all the footprints in ./packages, all the symbols in ./symbols
and a local gafrc with (component-library ./symbols) in it.

If I move the packages directory gsch2pcb complains about missing
footprints, so it's finding them. If I move one footprint out of
packages it complains about that one missing footprint, so it's looking
for and finding the right footprint files. Converting projectfile, gafrc
and footprint files to crlf makes no difference.

Looking through the gsch2pcb sources I see that :
/* The gnetlist backend gnet-gsch2pcb.scm generates PKG_ lines:
|
|PKG_footprint(footprint{-fp0-fp1},refdes,value{,fp0,fp1})

These are the lines I see in the pcb file produced by gsch2pcb. Looks
like pkg_to_element() should convert these to elements, but at the
moment I'm struggling to see how or why it doesn't.

Probably doesn't help much...

On Tue, 2010-01-26 at 20:32 -0500, Bob Paddock wrote:
 On Fri, Jan 22, 2010 at 8:21 PM, Kai-Martin Knaak k...@familieknaak.de 
 wrote:
 
  We already almost do this. The difference: We use a project file and the
  elements-dir points to the library of my local symbols. Both of Bob
  Paddocks suggestions might apply. The project file may be affected by the
  cr/lf problem because it went through a samba server and a windows
  machine. In addition, the path is located in a path with spaces.
 
  Like I mentioned before -- I'll investigate next week.
 
 Any findings?
 
 
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Re: gEDA-user: Win32 build with native printing support (via Cairo)

2010-01-22 Thread Peter Baxendale
Does gsch2pcb generate a valid pcb file for you? I get a file with these
kind of lines in (and no elements):

PKG_0603.fp(0603.fp,C8,4.7u)
PKG_0603.fp(0603.fp,R49,8K2)
PKG_0603.fp(0603.fp,R48,470)

No error messages from gsch2pcb. All my footprints are in ./packages .
The same schematics, footprints and gsch2pcb project file work ok on my
Linux box.

On Fri, 2010-01-22 at 13:16 +, Kai-Martin Knaak wrote:
 We just tried to do a gschem-gsch2pcb-pcb work flow with a small but
 real 
 world project:
 
 * gsch2pcb crashes if m4 isn't explicitly disabled with skip-m4 in
 the 
 project file. CMD-window output contains a backtrace. Unfortunately, 
 windows is unable to copy-paste tjhis text. So we made a screenshot
 -- 
 see attachment
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gEDA-user: centroid file generation

2009-08-21 Thread Peter Baxendale
Is it possible to generate a centroid file from pcb for use by a pick
and place machine? The pcb manual and various old postings seem to
suggest you can, but I can't see how to do it.

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Re: gEDA-user: centroid file generation

2009-08-21 Thread Peter Baxendale

 And seems that I am wrong, we may need the xy-file:
 
 ste...@amd64-x2 ~/gEDA/DAD $ pcb --help
 
 bom options:
  --bomfile string   BOM output file
  --xyfile stringXY output file
  --xy-in-mm   XY dimensions in mm instead of mils

Yes indeed,

pcb -x bom --xyfile foo.txt foo.pcb

does the trick. Thanks! I'd forgotten the --help and it hadn't occurred
to me that it would be a bom option.

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Re: gEDA-user: Investigating gEDA for commercial use

2009-06-17 Thread Peter Baxendale
On Wed, 2009-06-17 at 11:07 +, Kai-Martin Knaak wrote:

 Peter Baxendale is almnost there with his cygwin port. He does it once a 
 year to serve the local students. For whoever missed the announcement 
 last month: I put the latest port by Peter along with the latest direct 
 windows port by Cesar for download on my wiki in Hannover. I will update 
 as soon as one of them releases a new version.

I should say that this is just a cygwin build, and it's now rather old,
but it certainly works - tested by students. It's also available on my
own web page (www.dur.ac.uk/peter.baxendale/stuff, please ignore the
other ancient stuff there) but without the helpful text that Kai-Martin
provides. I'll be building it again this summer for the new academic
year.

I'm also going to go for a native windows build, but last time I tried
that it wasn't too successful with gschem or pcb (gerbv worked fine). If
it goes ok, of course I'll make it available, but I have to say I'm no
Windows expert. Unfortunately I don't have as much time as I would like
to spend on this, and to be honest, if I could persuade our people to
dual boot Linux I wouldn't bother at all.

-- 

Peter Baxendale   University of Durham
peter.baxend...@durham.ac.uk  School of Engineering
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fax +44 191 33 42408  Durham DH1 3LE
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Re: gEDA-user: geda cygwin package

2009-05-14 Thread Peter Baxendale
On Wed, 2009-05-13 at 13:19 -0400, al davis wrote:
 
 Gnucap has always worked on windows.  It works with gEDA, with 
 gnetlist generating a spice file, as well as any simulator does. 
 How about using Gnucap?

Well, for this particular course, for these particular students I needed
something they could start doing very simple simulations with reasonable
graphical output with about a 5 minute intro. Last time I looked at
gnucap there was a steeper learning curve, which I just didn't have time
for on this course. I'd certainly look at gnucap for anything more
advanced - something that's been on my summer list of things to do for
the past few years.

-- 

Peter Baxendale   University of Durham
peter.baxend...@durham.ac.uk  School of Engineering
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fax +44 191 33 42408  Durham DH1 3LE
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gEDA-user: geda cygwin package

2009-05-13 Thread Peter Baxendale
On Tue, 2009-05-12 at 23:31 +, Kai-Martin Knaak wrote:

 I'd love to point my coworkers to a place where they can get everything 
 they need to install gschem/pcb in a windows context. If web space is an 
 issue, I may dedicate bandwidth either on my private website or at the 
 university of Hannover.

I routinely package up cygwin with built gEDA cygwin executables once a
year for our Windows users here. Because it's once a year it gets a bit
out of date, but I'd be happy to make it available to anyone interested.
It has a readme to tell you how to install it all and includes swcad and
the windows installer for gerbv. Unfortunately the zip is too big (133M)
for the measly quota I get on our externally accessible servers here.
It's tested on students, which is usually a pretty tough test to pass...

-- 

Peter Baxendale   University of Durham
peter.baxend...@durham.ac.uk  School of Engineering
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fax +44 191 33 42408  Durham DH1 3LE
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gEDA-user: attribute promotion query

2008-02-08 Thread Peter Baxendale
Having read the gschem user guide (on-line version) on attributes and
attribute promotion (several times) I am even more confused, and I'd be
grateful if someone could clarify things for me.

For investigation purposes I instantiate a 7400-1.sym on my gschem page.
I have (attribute-promotion enabled) in my gafrc file, and I don't
have promote-invisible enabled. (Incidentally, the manual says to use
gschemrc to set these - is this wrong or can it be either?)

I edit attributes for the 7400 component, and I see just device, refdes
and footprint.

Q1 are these the promoted attributes?

Q2 the gschem user guide (on line) says The device= attribute is not
promoted. So why does it appear in the attributes list?

Q3 the gschem user guide says if you place an unattached visible
attribute inside a symbol and then instantiate that symbol, then that
unattached attribute gets “promoted”; that is, it becomes an attached
attribute. But the footprint attribute is not visible and seems to get
promoted. Why? The slot attribute (and others) looks just the same (not
visible) but is not promoted.

Q4 How do I tell if an attribute is attached or unattached?

Is this just a case of documentation lagging development, or am I
missing something?

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Re: gEDA-user: gschem slotting bug

2008-02-08 Thread Peter Baxendale
Thanks for responding to this, and I've found out what's going wrong. I
had promote-invisible enabled in my gafrc file and was editing the
slot attribute which was then visible.

If instead I turn off promote-invisible, then add a slot attribute with
the required number it works fine - pins updated at once.

I'm re-reading the gschem manual to try to understand this - it's not
immediately obvious to me why it doesn't work the way I was doing it, or
why you need a hidden slot attribute in addition to the visible one. I'm
sure there are good reasons, though.


On Thu, 2008-02-07 at 15:36 +, Peter Clifton wrote:
 Can you check the version again, and whether 1.4.0 still gives issues
 for you? I can't think of anything which has been fixed since 1.3.1.
 
 Werner committed a fix prior to 1.4.0 which updates the pinnumbers in
 o_update_component(), but that doesn't sound to be the same code-path
 as
 you're exercising here.
 
 Best wishes,

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gEDA-user: gschem slotting bug

2008-02-07 Thread Peter Baxendale
Using gschem 1.3.1.20080110, if I start a new design, insert a
7400-1.sym (for example) and change the slot number, the displayed pin
numbers don't change. If I save and exit, then restart gschem with the
design, the pin numbers are now correct. In fact, I can then change the
slot number and the pin numbers now change as they should. Seems to be a
problem with any slotted symbol you've just inserted - have to save,
exit and restart before the pin numbers display properly.

Is this a known bug?

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Re: gEDA-user: gerbv potential problem

2008-01-24 Thread Peter Baxendale
Wow, that was quick! Hate to think what that kind of service would cost
commercially. Many thanks!

On Thu, 2008-01-24 at 10:59 +0100, Stefan Petersen wrote:
 Peter Baxendale wrote:
  Hi gerbv people,
  
  Just posted a gerbv 2.0.0 feature to the gerbv bug tracker. Working
  with a reference design from Nordic Semiconductor I found that gerbv
  wasn't showing some bits around the antenna correctly (ie as shown in
  the Nordic documentation). Stripped it down to a few lines and the
  problem  seems to relate to when circular interpolation should revert to
  linear. All the other viewers I've tried (3 of them) show as per
  Nordic's design, gerbv doesn't. Of course, I can see you might argue
  that the others are all wrong...
 
 Hi Peter!
 
 Thanks for the bug report. While I have been sleeping Julian has fixed 
 the problem in CVS. If you're daring you can try out the CVS version. 
 I've tested it and it looked like in your PNG's.
 
 It seems like it was one of the grey corners of Gerber that reared it's 
 ugly head. This is the reason we like to release the code for public 
 scrutiny to put some light on these dark corners.
 
 For those interested in the exact cause of this, please look at Julians 
 explanation attached to the (now closed) bug report on gerbv's SF site.
 
 Thanks for your report and very good sample files.
 
 Regards,
 /Stefan
 
 
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Re: gEDA-user: gerbv potential problem

2008-01-24 Thread Peter Baxendale
Unfortunately there's nothing in the gerbers to indicate where they came
from. The schematic (a pdf) has a reference to Protel in it, which may
or may not be a clue.

On Thu, 2008-01-24 at 15:30 +0100, Stefan Petersen wrote:
 Hi again!
 
 BTW I forgot to ask, is it possible to determine which CAD program that 
 has been used to generate these gerber files? It usually says in the top 
 of the file after some G04 remark command.
 
 Regards,
 /Stefan
 

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gEDA-user: gerbv potential problem

2008-01-23 Thread Peter Baxendale
Hi gerbv people,

Just posted a gerbv 2.0.0 feature to the gerbv bug tracker. Working
with a reference design from Nordic Semiconductor I found that gerbv
wasn't showing some bits around the antenna correctly (ie as shown in
the Nordic documentation). Stripped it down to a few lines and the
problem  seems to relate to when circular interpolation should revert to
linear. All the other viewers I've tried (3 of them) show as per
Nordic's design, gerbv doesn't. Of course, I can see you might argue
that the others are all wrong...

-- 
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Re: gEDA-user: SPICE newbie -- was: Re: Simulation troubles ...

2007-11-08 Thread Peter Baxendale
Richard, I don't see a file attribute anywhere in your schematic to say
where your spice model is. You can add a file attribute to each opamp
symbol or add a spice directive symbol with the file attribute set
to your spice model file. You should see the opamp subcircuit model
included in the spice netlist.
Also make sure the pinseq attributes of each pin in your opamp symbol
match the order of the parameters to your spice model. In my
experience the gschem opamp symbols usually need changing.

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Re: gEDA-user: pcb-20070912

2007-09-17 Thread Peter Baxendale
This isn't the problem I reported a while back is it? Fedora 7 comes
with automake 1.10 and doesn't include aclocal-1.9. Configure apparently
runs ok and you can miss the error message when you run make. I ran
autogen.sh first, and then everything is happy.


On Fri, 2007-09-14 at 17:30 +0100, Peter Clifton wrote:
 On Fri, 2007-09-14 at 09:52 -0500, Harold D. Skank wrote:
  Dan,
  
  I've awaited this release for some time now, as I've been having
  difficulty with some polygon issues on a large design.  However,
  following download, I was some surprised that I could not get the file
  to compile.
  
  I should mention that I'm running Fedora-7 on an AMD-64, and I was
  attempting to compile in the 32-bit mode to avoid some operational
  issues that I have faced.  I could run:
  
CFLAGS='m32 ./configure --with-hid=gtk
  
  however a subsequent make command responded as though configure had
  not completed.  In the end I had to go back to pcb-20070208.
 

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gEDA-user: fedora 7 build pcb from cvs

2007-09-06 Thread Peter Baxendale
For the benefit of anyone like me who's not familiar with the
complexities of automake, configure scrips and the like, if you're
trying to build pcb from cvs, you need to run autogen.sh before
configure because Fedora 7 comes with automake-1.10, not 1.9.

Also, the version I just checked out had newlib/keystone missing from
configure.ac, which stops the build.

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gEDA-user: pcb build problem

2007-08-28 Thread Peter Baxendale
Anyone know what the following means when running configure for pcb? :

config.status:742: creating Makefile
config.status:877: WARNING:  Makefile.in seems to ignore the
--datarootdir setting

I'm using:
./configure --prefix=/home/des0prb/geda --enable-maintainer-mode

under Fedora 7 on pcb checked out from cvs today. I get a similar
message in config.log for the other Makefiles as well, and make install
fails because it tries to install to /pcb (ie it really does ignore
datarootdir).

I've a feeling I'm doing something daft, but I can't see what. Be
grateful for any advice.

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Re: gEDA-user: schematic hierarchy netlist problem

2007-07-19 Thread Peter Baxendale
OK, thanks for the response. Attached is a very simple hierarchical
design. The .pcb and .net files were generated by gsch2pcb --skip-m4.
You can see the U?-? in the .net file.

On Wed, 2007-07-18 at 07:11 -0400, John Luciani wrote:
 On 7/18/07, Peter Baxendale [EMAIL PROTECTED] wrote:
  I don't know where the U?-? comes from. It's not in any of the
  schematics, just in the netlist produced by gsch2pcb. Every net that
  connects to one of the io symbols ends in a U?-?. The line I quoted
  should only have 3 nodes, the extra U?-? looks to be entirely spurious.
  I should have said, I'm using the gschem 1.0.1-20070626 release.
 
 You may want to post a simple schematic that demonstrates the problem.
 
 (* jcl *)
 
-- 

Peter Baxendale   University of Durham
[EMAIL PROTECTED]  School of Engineering
tel +44 191 33 42492  South Road
fax +44 191 33 42408  Durham DH1 3LE
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simple.tar.gz
Description: application/compressed-tar


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Re: gEDA-user: schematic hierarchy netlist problem

2007-07-19 Thread Peter Baxendale
Found the answer to my own question by playing around a bit. The pins on
the top level symbol didn't have a pinnumber attribute - I didn't think
I needed them since they are meaningless. When I put them in, the
problem goes away. I've made them invisible so as not to give
meaningless info on the top level schematic.

On Thu, 2007-07-19 at 10:06 +0100, Peter Baxendale wrote:
 OK, thanks for the response. Attached is a very simple hierarchical
 design. The .pcb and .net files were generated by gsch2pcb --skip-m4.
 You can see the U?-? in the .net file.
 
 On Wed, 2007-07-18 at 07:11 -0400, John Luciani wrote:
  On 7/18/07, Peter Baxendale [EMAIL PROTECTED] wrote:
   I don't know where the U?-? comes from. It's not in any of the
   schematics, just in the netlist produced by gsch2pcb. Every net that
   connects to one of the io symbols ends in a U?-?. The line I quoted
   should only have 3 nodes, the extra U?-? looks to be entirely spurious.
   I should have said, I'm using the gschem 1.0.1-20070626 release.
  
  You may want to post a simple schematic that demonstrates the problem.
  
  (* jcl *)
  
 
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Re: gEDA-user: schematic hierarchy netlist problem

2007-07-18 Thread Peter Baxendale
I don't know where the U?-? comes from. It's not in any of the
schematics, just in the netlist produced by gsch2pcb. Every net that
connects to one of the io symbols ends in a U?-?. The line I quoted
should only have 3 nodes, the extra U?-? looks to be entirely spurious.
I should have said, I'm using the gschem 1.0.1-20070626 release.

On Tue, 2007-07-17 at 14:39 -0700, Steve Meier wrote:
 It looks like it is partially working.
 
 Your net list has S2/R2-1 which is one hierarchical level down from
 SW1-2.
 
 Is the U?-? the symbol that has the lower level schematic?
 
 
 Steve Meier
 
 
 On Tue, 2007-07-17 at 17:04 +0100, Peter Baxendale wrote:
  Been experimenting with hierarchical design with gschem. When I generate
  the netlist using gsch2pcb I get a  U?-? on every net that goes to one
  of the io objects.
  

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gEDA-user: schematic hierarchy netlist problem

2007-07-17 Thread Peter Baxendale
Been experimenting with hierarchical design with gschem. When I generate
the netlist using gsch2pcb I get a  U?-? on every net that goes to one
of the io objects.

As per the wiki (I think), I've used an in-1.sym in the sub schematics
where they get input from the top level schematic, and an out-1.sym for
outputs to the top level. In each case, I've set the io symbol's refdes
to the same as the pinlabel attribute of the corresponding pin of the
top level symbol. The generated netlist picks up all the things it
should do from the sub pages, eg:
unnamed_net5S2/R2-1 S2/U1-1 SW1-2 U?-?

I'd much appreciate it if someone could tell me where I'm going wrong.

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Re: gEDA-user: geda, pcb and cygwin

2007-06-20 Thread Peter Baxendale
On Wed, 2007-06-20 at 18:05 +, Kai-Martin Knaak wrote:
 * There is an error report on start-up of pcb: Error message is actually 
 german because this is the native language of my winXP. Roughly 
 translated it says: Can't find file ListLibraryContents.sh and 

The file is a shell script which, I think, lists the files in the
library path to standard out. It should probably be removed from the
source in win32 or replaced with something which works or is harmless. I
temporarily replaced it with a 'do nothing' win32 executable.

 * I like to work with local component libraries. Setting the path to the 
 local lib fails.  The reason seems to be misinterpretation of the colon 
 in windows paths. What syntax should be used for the list of paths?
 Maybe this is a consequence of the missing ListLibraryContents.sh?

I know that in msys you access c: by /c/ (ie the c drive is available as
directory c in the root). I don't know if this works in the pcb
executable?

I too have played with building a win32 version of pcb and ended up with
something which sort of works for most things but with quirks. For
me, that's not good enough to let loose on my students. Even though I
have no interest in using a win32 version of pcb and geda myself, I'm
prepared to spend some time on getting this working for my students. But
I find it hard going because of my lack of knowledge of win32 and mingw
- for instance on those issues of path specifications - and there seems
little documentation around. If anyone wants to share their
knowledge/experiences off this list, I'd be happy to hear from them.
-- 
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Durham University
School of Engineering



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Re: gEDA-user: gschem cvs repo issue FC6

2007-05-10 Thread Peter Baxendale
Yes, I do that on my desktop with all the packages, especially pcb. I
couldn't be bothered on my laptop, which I rarely use for real work of
this type. This way I can have 2 different versions going at the same
time and get myself really confused (not hard).

On Tue, 2007-05-08 at 16:44 -0500, Craig Niederberger wrote:
 You might want to consider building  installing gschem from the cvs
 repo.  I found the performance significantly improved in FC6 compared
 to the latest rpm snapshot.
 Craig
  


-- 
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Re: gEDA-user: DJ's back

2007-04-19 Thread Peter Baxendale
 It actually hits me why the English don't write Metres when they write
 litres, but that's probably me being ignorant.
 
Hey, don't expect us to be consistent - that would take all the fun out
of it. We measure beer in pints, farm land in acres, road distances in
miles and petrol in litres. Meanwhile the kids only learn metric in
school (which gives us oldies a small advantage).

-- 
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Re: gEDA-user: Where to place pcb footprints?

2007-03-16 Thread Peter Baxendale
If you mean where pcb finds footprints, displayed in its library
window, then you can set this in ~/.pcb/preferences. I have a line:
library-newlib = ./footprints:/home/des0prb/pcb/geda/footprints in
there.

Personally I don't ever use the pcb library window though, because I
always do pcbs from schematics. Here what matters is where gsch2pcb
looks for its footprints. I put this in a project file in the working
directory for the design, using a line like
elements-dir /home/des0prb/pcb/geda/footprints
I believe you can also specify this on the command line to gsch2pcb, but
I find the project file approach more convenient. Make is an alternative
of course.

Hope this helps. If others have better ways of doing this, I'd be glad
to hear them.

On Fri, 2007-03-16 at 00:02 +0100, Philipp Klaus Krause wrote:
 Where is a good place to store pcb footprints? For previous projects I
 just copied them to the global footprint directories, but I suppose
 that's not really the right place. The pcb documentation tells me to
 place project-specific footprints in pkg/newlib. I'd prefer some place
 under my home directory for footprints used by multiple projects, but
 how do I tell pcb and gsch2pcb to look there? Is there some
 configuration file for this? The pcb documentation mentions nothing
 about configuration files. Maybe pcb doesn't have one? Is the command
 line option to gsch2pcb the only way to tell it where to look for
 footprints?

-- 
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Re: gEDA-user: Re: How to program PAL/GAL?

2007-03-15 Thread Peter Baxendale
We used to use CUPL here a few years ago (a good old command line
version), which I always found easier to use than palasm. A couple of
weeks back I programmed a 22v10 for a student demo. I used a free (beer)
windows version called WinCUPL I found on the Atmel site. Unfortunately
its a gui driven thing and I couldn't get it to run under wine, but it
did the job on a windows machine.

On Tue, 2007-03-13 at 19:16 -0400, Dave McGuire wrote:
 On Mar 13, 2007, at 6:22 PM, Stephen Williams wrote:
  Is Icarus PAL still alive?
 
  Not especially. No one seems to be programming pals these days,
  and using FPGAs instead.
 
I know of a few people using PALs, and I use them myself.  I use  
 PALASM under DOS on an x86 emulator.  It works fine.
 
-Dave

-- 
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Re: gEDA-user: Flame about XML (was: Some footprints I tried to create)

2007-03-14 Thread Peter Baxendale
 Seriously though, I have absolutely no need for an office suite.
 Writing papers: 99% of the time I write them in plain text files in vi.

What a wimp. What's wrong with ed?




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Re: gEDA-user: freedog pictures

2007-03-09 Thread Peter Baxendale
 That board is the Zigbee radio board for my MSP430F169 board. The DB-9 is
 an RS-232 port (the uC board has a USB port). The T-shaped trace is a
 folded dipole
 that should match the Chipcon 2500 reference design. I do not see a TO220 ;-)

I'd be interested to know how you copied the reference design. I made
some Chipcon 2420 Zigbee boards a couple of years ago using Orcad and
just tried my best to get the layout and dimensions right by measuring
things on the reference gerbers using a gerber viewer (the boards work
fine as it turns out).

Since it's quite common to get reference designs that include gerbers, I
was wondering if it would be feasible to to convert these back into,
effectively, a pcb footprint. I'd have thought there was enough
information in the gerber and drill files to do this - but I admit I
haven't thought it through.

-- 
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Re: gEDA-user: freedog pictures

2007-03-09 Thread Peter Baxendale
 A different point:  In the past we have discussed creating a utility
 which would read a Gerber file and output either a .pcb or a .fp file
 corresponding to the contents of the Gerber.  Maybe the utility could
 be instructed to know which file is associated with which PCB layer?
 In any event, the utility would make it easy to load a legacy board
 Gerber, and then make easy edits in it.

That's the kind of thing I had in mind. Reconstructing the higher level
information sounds hard (or maybe impossible), but getting it into a
form you could load into pcb sounds more feasible. With the help of a
suitable config file you could guide it which layers to map to which
files, and maybe even assign pseudo pin connections to the points that
need to connect to other circuitry.

-- 
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Re: gEDA-user: freedog pictures

2007-03-09 Thread Peter Baxendale
 Since gEDA is completely free (both cost-free and open source), it's a
 good, neutral vehicle for chip vendors to distribute reference
 designs.  Any engineer who wants to use the reference design can grab
 the tools off teh web, open the reference design file, 
 and make immediate use of the reference design. Indeed, it
 would speed up the design process if I could just open a vendor's
 reference design  copy/paste the parts I wanted directly into my
 schematic instead of having to re-draw everything.  Now that's design
 re-use!

I swear a pig just flew past my window.

-- 
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Re: gEDA-user: Why use gEDA?

2007-03-07 Thread Peter Baxendale
Sorry to start yet another Windows/Other OS war - it wasn't my
intention. And don't take me for a Windows advocate. I agree with most
of the points made by various people here. I've been arguing strongly
here for diversity in operating systems, both for educational and
security reasons, for some time. I don't want either Microsoft only or
Linux only, we need a variety. I strongly believe the same applies
outside university as well. Personally, I dumped Windows years ago and
have never looked back. Since then, several other members of staff here
have switched away from Windows. This is not for cost reasons, since our
site licence gives us a lot of free (for the end user, not the
University) Microsoft software. We'll get there, but not this year and
probably not next, so meanwhile I have to live with the reality of
almost all teaching on Windows boxes. Given this, I'd still like to use
gEDA so I need to look at ways to run it on Windows boxes.

 How about setting up a server, with remote X display on the 
 windows boxes?
 

We've done this and are evaluating it for next year. Performance looks
very good for one user but we need to see what happens with a class of
20 or so (can't afford a new server at the moment). But for firewall and
performance reasons this is unlikely to work for those who want to run
the software at home on their own PCs.

 They need to learn to deal with more than one system.  Faculty 
 need to learn this too.  They need to learn it early.
 
I agree entirely.

 They can't run commercial windows software at home because of 
 cost and licensing.  If you run all windows stuff, they need to 
 come into the lab for work that should not take lab time.
 
Theoretically yes. But there are many student deals, particularly from
Microsoft (eg MDA giving them free access to all the software
development tools, about 30 UKpounds for the entire Office suite - all
to run at home on their own PC). Secondly, a surprising number of them
have copies of expensive packages of their own. I assume they have rich
parents, but I don't like to ask.

We use many other engineering software packages which are prohibitively
expensive and for which there are no equivalents with less restrictive
licensing, so there's no alternative to the students doing the work in
the department. It's just not practical to run our entire engineering
course on free software (it's general engineering, which covers
everything from civil to IC design for half of the course).

 The real benefit is that if they want to run it at home, they 
 are only blocked by their own unwillingness to do it.
 
Quite right, but if they see the pain barrier as too high then they
won't do it, and I'd like them to do it, so I'd like to lower the
barrier a bit for them. Maybe if they see how good open source software
can be it might open their minds to other possibilities.


-- 
Peter Baxendale
School of Engineering
Durham University
South Road
Durham
DH1 3LE
tel 0191 33 42492
fax 0191 33 42408



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Re: gEDA-user: thermal vias in pcb

2007-03-07 Thread Peter Baxendale
On Tue, 2007-03-06 at 22:02 -0800, Dave N6NZ wrote:
 What is the easiest way to create thermal vias? Not a via with a 
 thermal relief -- I can do that :) .. but a via with no thermal relief 
 punched into polygons on both sides of the board that ends up getting 
 filled with solder to help create a large thermal mass to be used as a 
 heat sink.
I thought you just put a thermal relief on the via and then shift
clicked on it to cycle through to the one with no relief. Or isn't that
what you meant?



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gEDA-user: pictures of symbols

2007-03-07 Thread Peter Baxendale
Is there an easy command line way to generate an image (png or whatever)
from a gschem symbol file? I'd like to catalogue my symbols for other
users and a little picture would be nice.

Also, the same question for pcb footprints.
-- 
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Re: gEDA-user: thermal vias in pcb

2007-03-07 Thread Peter Baxendale

 
 Depends on how new your version of PCB is.  Peter's suggestion is
 appropriate for recent releases since this feature was added not too
 long ago.  I'm running 20060822.  If Dave is using an older
 version, then my suggestion is appropriate.
  
 Joe T
  
 
Sorry. Hard to keep track of what came in when. I've found this feature
really useful so I rather took it for granted.



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Re: gEDA-user: Why use gEDA?

2007-03-06 Thread Peter Baxendale
 And i do a question, is gEDA an proper software to use during the
 formation academical  process? I think yes that, this can be used for
 that.
 
 What do you think about?

A bit late to reply to this, but ...

We used gEDA in our Engineering course here at Durham University (UK)
School of Engineering for the first time this year. We previously used
Orcad for teaching purposes. Since I don't use Windows myself this
wasn't an option for me personally so I had already been using gEDA.
When it came to buying a load more Orcad licenses to support a new ECAD
course I decided instead to switch to gEDA because (in no particular
order)
1. it seems to give us pretty well everything we need
2. the licensing allows students and staff to have their own copies
3. well documented text file formats are used
4. it's open source
5. it's well supported (eg here)
These all seem to me good reasons for getting students to use it. In
addition, I think the fact that parts of the process involve using a
command line interface makes for a good learning experience for students
who are too used to clicking without thinking.

We set a very simple assignment for our students to get some experience
of the schematic entry/simulation/pcb design process, adapted from the
earlier Orcad exercise. If you're interested to see what we did take a
look at
http://www.dur.ac.uk/peter.baxendale/stuff/gEDA/assignment_desc.pdf .
It's limited because it's a short course, the electronics had to be
simple because of the level these students were at, and it had to use
components I could find spice models for.

I think if you use Linux machines for teaching there's no reason at all
not to use gEDA. Unfortunately, here all our teaching machines currently
run Windows only, so we use a rather old Windows distribution which is
not entirely satisfactory. Also, I found that students wanting to use it
on their own machines were put off by the relatively complicated
installation, including having to install Cygwin first (that is, for the
majority of students who only use Windows). When I get the time I want
to find better solutions. Native Windows versions of gschem and pcb with
an installer would be attractive to the students, but it doesn't seem
easy to build these out of the box. I'd like to encourage more to use
gEDA, and unfortunately that means getting my hands dirty with Windows.

All things considered, it's been pretty successful and I intend to stick
with it for next year.



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Re: gEDA-user: autogenerate footprints

2007-01-05 Thread Peter Baxendale
 Yeah, great idea... is there any standard Perl Script under svn that most
 people use? 

As well as Perl, there's a short Python program at
http://dlharmon.com/geda/footgen.html which I've found very useful. It's
easy to understand and customise even if you only have a little bit of
understanding of Python. It's really very easy to use and I've generated
all my own footprints this way. I've added a few modest bits and pieces
to it which I'd be happy to pass on if anybody is interested.




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Re: gEDA-user: PCB Trim/extend traces

2006-12-21 Thread Peter Baxendale
Do you mean apart from grabbing the ends and dragging them (which seems
to work ok for me)?

On Thu, 2006-12-21 at 07:47 +0100, Jonatan Åkerlind wrote:
 Hi!
 
 Is there a way to trim and/or extend traces in PCB? 
 If not, this would be a very nice feature to have.
 
 /Jonatan
 
 
 
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-- 
Peter Baxendale
School of Engineering
Durham University
South Road
Durham
DH1 3LE
tel 0191 33 42492
fax 0191 33 42408



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Re: gEDA-user: making gnetlist calm down

2006-12-08 Thread Peter Baxendale
 problem 2:
 I get several errors like this:
 
 ERROR: Pin(s) with pintype 'unknown': U47:10 U48:10 U49:10 U50:10 U45:10
 [snip]
 are connected to pin(s) with pintype 'unknown': U47:10 U48:10
 U49:10 U50:10 U45:10
 [snip]

If you look in the gschem master attributes list it tells you what the
pintype is for. It can be (is?) used for design rule checking. Many
symbols haven't got these attributes defined, which causes the warning.
I ignore these.

 problem3:
 ERROR: Net unnamed_net58 is not driven.
 
 How do I figure out where unnamed_net58 actually is?
 

If gnetlist generates a netlist file you can maybe look for
unnamed_net58 in there and see what it's connected to (presumably just
one thing).




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Re: gEDA-user: about DJ

2006-11-08 Thread Peter Baxendale
We used to use DJGPP in our C programming classes. Now the students use
pcb in their ECAD classes. Wonder what he will turn his hand to next...

On Tue, 2006-11-07 at 18:11 -0500, Dave McGuire wrote:
 On Nov 7, 2006, at 6:05 PM, Paul Bunyk wrote:
  Brings back fond memories of compiling my code with PharLap, then with
  djgpp and getting like 30% better performance with the latter! :-)
  Moving to GNU toolchain completely right after that and to Linux
  (Hey, it actually *comes* will all the tools!) around kernel version
  0.93. First Slackware base install living on 16MB partition on my PC
  with /usr/ NFS-mounted from Interactive UNIX server... 1991-1992, I
  think...
 
  Thanks, DJ!
 
I echo this thanks to DJ.  I was working on a 386DX/20 running  
 DOS, and had gotten about as far as I could with Turbo C.  It was a  
 good system, but it was like pulling teeth when compared to  
 developing on [what at the time was my] modern system, a Sun 4/110  
 running SunOS 4.1.  I finally found djgpp and it was like a breath of  
 fresh air.
 
-Dave




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Re: gEDA-user: slotting problem

2006-11-03 Thread Peter Baxendale
   That's bizarre.  Can anybody else reproduce this behavior?  
 On my box, I select the component, pick Edit/Slot..., type in the 
 new slot number (2 for a 7474-1), hit okay, and boom, I get the pins
 to change.

Weird. I just tried it again to make sure I wasn't going crazy. Here's
what I did:
run gschem
click on add component
select 7400-1.sym
click in main window
close add component window
click on the 7400
select Edit menu, slot... (Edit slot number dialogue appears)
change slot=1 to slot=2, click OK

The pin  numbers don't change and if I edit attributes the slot number
hasn't been changed either. A bit more investigation shows that this
only applies to newly added components. That is, if I save the file and
exit gschem, then run it again, Edit/slot... now works on the 7400 I
added before, but if I add another one it doesn't work on that one.

Maybe it's my version? 20061020 built from sources. Or can I screw this
up with something in my gschemrc or gafrc file?




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gEDA-user: slotting problem

2006-11-02 Thread Peter Baxendale
I seem to be having slotting problems with gschem. If I add a 7474
component, for instance, and change its slot number to 2, the pin
numbers don't update. In the gschem log I see:

Opened file [/home/des0prb/geda/share/gEDA/sym/74/7474-1.sym]
numslots attribute missing
Slotting not allowed for this component
numslots attribute missing
Slotting not allowed for this component
numslots attribute missing
Slotting not allowed for this component

If I save and reload, the pin numbers are then right. Also, if I save
before changing the slot number, then reload and change the slot number,
the pins update ok.

Am I doing something wrong, or is this a known bug? I'm using
gschem-20061020 built from sources (the latest ones on the source
download page). There's some reference on the list to a similar problem,
but only a suggestion to upgrade to a newer version, which I thought I
had.



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Re: gEDA-user: pcb refdes name restrictions?

2006-10-31 Thread Peter Baxendale
Thanks for the comment on refdes values. I'll add a few things to next
year's notes for the students.

It had never occurred to me to use anything but an upper case alpha
character followed by a numeric value for a refdes, but students have a
habit of trying the unexpected. It threw me for quite a while trying to
understand what pcb was complaining about, since it referred to a CONN
part which wasn't in either the schematic or the pcb netlist or the pcb
file. Now I know about the lower case feature I'll know what to look for
next time.

Correct me if I'm wrong, but only lower case at the end of a refdes is
ignored by pcb (but not by gsch2pcb), so something like Rp4 is ok.



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Re: gEDA-user: pcb refdes name restrictions?

2006-10-31 Thread Peter Baxendale
 I am curious to know if your notes are available online, or are released
 under such a license that we can make them available to students here?
 

I've put them on my web page
( http://www.durham.ac.uk/peter.baxendale ). They are pdfs but I can
send you openoffice files if they are any use to you. They are just
brief notes to support a simple assignment (4x2 hour sessions) so you
may find them a bit basic. I'd be interested in hearing your own
experiences using geda with students.



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gEDA-user: pcb refdes name restrictions?

2006-10-30 Thread Peter Baxendale
Another dumb question. I teach a class of undergraduates about ECAD and
this year abandoned commercial tools in favour of geda. Students being
students, they tend to try things I wouldn't think of doing. Today, a
couple of them decided to be creative and on their schematic used names
like CONNpower and CONNsignal for refdes values. Whilst I thought it
unconventional and probably inadvisable, I couldn't offhand see why they
shouldn't do that.

Gsch2pcb happily produced a netlist and pcb file which both looked fine,
as far as I could tell. But when loaded into pcb, optimising the netlist
causes error messages such as Can't find CONN pin 4 called for in
netlist.

So does pcb require that all reference designators be in the form of a
string followed by a numerical value? If so, are there any other refdes
restrictions I should know about? Given time, they're bound to find
them...

Thanks,
PB



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Re: gEDA-user: pcb refdes name restrictions?

2006-10-30 Thread Peter Baxendale
 A reason not to have long refdes values is clutter. Names that are seven and
 eight characters get difficult to place (legibly) on dense schematics and
 PCBs. A seven character refdes will probably take up more board area than most
 of you SMD components.

Yes, I agree entirely. What I meant was that I was surprised that pcb
doesn't work with this kind of refdes. For instance, Ja doesn't work
either.





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Re: gEDA-user: pcb refdes name restrictions?

2006-10-30 Thread Peter Baxendale
 Any lower case suffix is ignored. This is so you can, for example, place
 4 discrete NAND gates on the schematic called U1a, U1b, U1c and U1d, and
 they will netlist into a single footprint / component, U1.
 

Ah, thanks - that explains exactly what I was seeing - CONNpower became
CONN.

 I'm not sure of any other restrictions. Spaces are probably unwise  ,
 but I've not tested that.

The students tried that - as you'd expect, spaces are a bad idea.



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gEDA-user: gschem symbol search order

2006-10-26 Thread Peter Baxendale
If you have a  (component-library ...) line in your local gafrc file
(in $HOME/.gEDA), should that directory be searched before any others
for symbols?

I seem to find that if I save the design then reload it, gschem picks up
a symbol of the same name from the geda library instead of the one from
my own library. I can rename my own symbol, of course, just wondered...



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Re: gEDA-user: Re: Board fabrication -- outline

2006-10-11 Thread Peter Baxendale

 Also the auto-router creates lines 

 that have the join flag consistent with the setting for newly created lines 

 (although the auto-router will never place a line within a polygon, 

 people seem to want to add polygons to layers that the auto-router has used

  after it's done its routing. Seems strange to me.)
 

On a 2 layer board, I use the auto-router to draw an initial ground net,
tidy it up by hand, do the same with power net(s), route the rest of the
board then draw a polygon over the whole lot which connects to ground.
Thus I'm adding a polygon to a layer that the auto-router has used after
it's done its routing. Maybe I'm missing something, but I couldn't see
how else you would do it.

Peter.



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Re: gEDA-user: Newbie PCB DRC questions

2006-10-04 Thread Peter Baxendale
Ah, my mistake then. Maybe they were auto routed segments I'd ripped up
and manually routed. Apologies for the unwarranted slur on the auto
router.

 I don't believe these small segments are due to the autoroute process.  
 I see them a lot and I've never used the auto-router.  I believe they 
 can occur when:
 You add a line containing several segments with snap to pins and pads 
 turned on.  This can put a short ( 1 grid long) segment in the line.





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Re: gEDA-user: Clearance in polygons

2006-09-27 Thread Peter Baxendale
Now I'm confused. I've ended up with some of the tracks showing a
polygon clearance of 10 mil (in an object report) whilst others show 5
mil. After a little experimentation it seems that if I draw a track
manually using the signal style (with clearance set to 10 mil and
line width set to 10 mil) I get 10 mil spacing between the edge of my
track and the polygon. If I autoroute using the same style I get 5 mil
spacing between the edge of the track and the polygon. Should they be
different, and if so, why?

On Wed, 2006-09-27 at 10:45 -0400, DJ Delorie wrote:
  Where is this default clearance set? Under Route Style there's just
  a clearance, set at 10 mil.
 
 That's it.  Note that clearance is defined as what you add to
 thickness to get the cut thickness.  I.e. for a 5 mil gap, you need a
 10 mil clearance.  For a 6 mil gap, you'd need a 12 mil clearance,
 etc.
 
 
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