Re: gEDA-user: howto toporoute?
Have you tried the old PCB autorouter? When I tried it years ago it worked not really good, but in the meantime the author has made some serious improvements, as he told us. Yes, the normal autorouter is what I settled for. The result was reasonable and completely acceptable for this particular project. See the attached layout. That's a neat layout. It will look even neater if you use the Miter trace optimiser - it really helps to tidy up after the autorouter. Make sure to uncheck the Only autorouted nets flag first. Stephen Ecob Silicon On Inspiration Sydney Australia www.sioi.com.au $39 Spartan 6 board with 32MB DDR DRAM ? http://www.sioi.com.au/shop/product_info.php/products_id/47 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: revert vs reload
On Tue, Sep 6, 2011 at 6:40 AM, Richard Barlow rbar...@studentrobotics.org wrote: I've made a couple of small modifications to the message that's displayed to the user in the info bar[1]. It would also be good if when reloading/reverting the file the state of the UI wasn't reset too, it's quite annoying for all of the layers to be re-enabled if you're in the middle of routing. I'll look into that later. +1 Very annoying with multi layer boards and a work flow that involves frequent changes to the PCB from gedit. Stephen Ecob Silicon On Inspiration Sydney Australia www.sioi.com.au $39 Spartan 6 board with 32MB DDR DRAM ? http://www.sioi.com.au/shop/product_info.php/products_id/47 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Fwd: Re: [OH Updates] How can you help solve the proprietary tool problem?
2011/9/6 Kai-Martin Knaak kn...@iqo.uni-hannover.de: Steven Michalske wrote: +1 to bundling plugins with pcb sources.. +1 to merging plug-ins into the main project. There is no point in keeping useful features outside. The necessity to compile and keep distinct plugins for different versions of PCB is a pain. Also, they tend to bit-rot and break when the main source moves on. +1 also If you are the author of a PCB plugin - Next time you do some maintenance on your plugin, please consider incorporating it into git head. Your plugin will benefit more people, and you'll no longer have to deal with the bit rot by yourself. Stephen Ecob Silicon On Inspiration Sydney Australia www.sioi.com.au $39 Spartan 6 board with 32MB DDR DRAM ? http://www.sioi.com.au/shop/product_info.php/products_id/47 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How to find which specific part of a PCB is shorted?
On Fri, Sep 2, 2011 at 11:16 PM, Thomas Oldbury toldb...@gmail.com wrote: When I delete the shorted objects (a microSD card connector, and a 3 pin header) the short location moves!! I can't see a short anywhere on this board. I've searched the PCB file for shorted thermals, no luck. Is there a patch which improves the functionality and actually locates the position of this short, or do I have to rip up large areas of my board until I get to it? The orange ring on the left pad of I2 looks suspicious - what happens if you delete I2 ? Stephen Ecob Silicon On Inspiration Sydney Australia www.sioi.com.au $39 Spartan 6 board with 32MB DDR DRAM ? http://www.sioi.com.au/shop/product_info.php/products_id/47 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How to find which specific part of a PCB is shorted?
I remember the old Quake maps had to be sealed, so any loose seam
would cause problems. Because the map editor doesn't know what you
meant to be outside/inside, etc, the map editor had a feature to deal
with this, it would create a line that would start in one area, and
head to another. All you had to do was follow the line.
A similar solution in PCB would be neat. if VCC and GND are shorted,
pick a random GND pin and a random VCC pin. Find a path between them
and show it as a orange dotted line. This could later be extended to
find either the shortest orange dotted line, or the point on the board
where several such lines meet.
Yes, plenty of possible algorithms - the one that I though of was:
For each element in the set of elements in the two shorted nets
{
Temporarily disable this element (ie consider it an open circuit)
If (the two nets are still shorted)
{
re-enable this element;
continue;
}
re-enable this element;
Visually highlight this element;
Alert user(This is the offending element);
}
The algorithm fails if the short consists of parallel shorting
elements - but the very common case is just a single fault, very often
that via with extra thermals on a wrong layer.
If only I had time for more than pseudo code at the moment!
Stephen Ecob
Silicon On Inspiration
Sydney Australia
www.sioi.com.au
$39 Spartan 6 board with 32MB DDR DRAM ?
http://www.sioi.com.au/shop/product_info.php/products_id/47
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Re: gEDA-user: How to find which specific part of a PCB is shorted?
Usually, when I have power and ground shorted, it's because of a via placed some where that was accidentally assigned thermals to the wrong layer. -Ethan +1 Often when this happens I find it easiest to fix in a text editor, it's easier to spot a via connected to too many layers there than in the GUI. Stephen Ecob Silicon On Inspiration Sydney Australia www.sioi.com.au $39 Spartan 6 board with 32MB DDR DRAM ? http://www.sioi.com.au/shop/product_info.php/products_id/47 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Foss-pcb Proposed plan from CERN
Even conversion of old legacy Altium designs could be done given access I expect there will be a growing demand for exit options for Altium users once the full impact of their recent upheaval settles in. It could benefit the gEDA community to adopt Altium refugees - they're used to spending $4K per year for their layout software, perhaps they could funnel some of that into improving gEDA. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Layer button backgrounds - summary
A few hours in the future, Andrew Poelstra as...@sfu.ca wrote: Nope, uploaded it wrong :-}. The URL works now. Looks good, a definite improvement on what we have now! This may be out of scope for the current work, but I have some related items on my PCB wish list: * Hide all layers button * Show all layers button * Layer visibility memory - this would have a Store button and a Recall button. Store just stores the current visibility state, Recall changes it to the stored value. Perhaps 2 or 3 memories like this would be really useful when working with multi layer boards. * Store layer colours and visibility data in the .pcb file. I often work with a flow where I make changes to a .pcb in a text editor and then import them into PCB with the revert function. It's a real nuisance to lose my layer visibility state every time I revert. -- Stephen Ecob Silicon On Inspiration Sydney Australia www.sioi.com.au ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Layer button backgrounds - summary
A few hours in the future, Andrew Poelstra as...@sfu.ca wrote: On Tue, Aug 23, 2011 at 09:52:19AM +1000, Stephen Ecob wrote: A few hours in the future, Andrew Poelstra as...@sfu.ca wrote: * Hide all layers button * Show all layers button These would be easy enough to add to the widget. Just tack an `All Layers' entry below the other non-selectable entries. Whether there would be demand for this, I don't know. Would it affect the pins, pads and via layers? Would it affect the solder mask layer? Why would you want to hide everything? Often I want to see one layer alone, so it would be convenient to be able to hide all and then show a single layer, using just 2 clicks. In your example artwork there are 14 layers, going from all visible to just one visible would take 13 clicks. When I'm finished checking that single layer I generally want to go back to all layers visible, so another 13 clicks! That's why I'd like a show all button. I don't expect there would be enough of a consensus on these questions. That may well be. Does this idea appeal to any of you other PCB users out there ? -- Stephen Ecob Silicon On Inspiration Sydney Australia www.sioi.com.au ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Layer button backgrounds - summary
3 hours and 55 minutes ago, Vanessa Ezekowitz vanessaezekow...@gmail.com wrote: Another thought comes to mind: How about a simple horizontal rule separating the read-only layers from the rest? Good idea. 3 hours and two minutes in the future, Andrew Poelstra as...@sfu.ca wrote: This might work. So might coloring the text. But this has the same problem as putting text in parentheses: at first glance, this visual indicator might mean -anything-. I agree - italics / parentheses would leave me wondering what does that mean ? Other possibly helpful indicators: 1. As the user moves their pointer over the layers, dynamically show a half strength current-layer indicator - but of course only for the layers that can be selected. half strength could be done by (say) averaging the colour used to indicate the current layer with the background colour. The half strength changes to full strength and actual selection when the mouse is clicked. 2. If the user insists on clicking on a non selectable layer then display text that explains why they can't select it. The text could be displayed in the Message Log window, or possibly in a pop up dialog box. 'Layer Vias can be displayed or hidden, but cannot be selected as the current editing layer' Just my $0.02, don't know how much work it would be to code these. Regards, Stephen Stephen Ecob Silicon On Inspiration Sydney Australia www.sioi.com.au ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Off topic: request for a little help
Thanks to all who have replied, I've received some really useful feedback. The most commonly repeated comment was that the animated price tags are just plain irritating. I'll put their removal on the slate for the first refresh of the web site ;-) Thanks and best regards, Stephen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Gschem and footprints
But when I import a schematic into pcb it seems to throw away anything that has an unknown footprint Is this just the way pcb works or am I missing something PCB doesn't throw away - but it doesn't have a visible placeholder for missing footprints. It helps to have the Message Log window open (you'll find it in the Window menu). IIRC missing footprints are listed in the message log when you load the board. Stephen Ecob Silicon On Inspiration Sydney Australia www.sioi.com.au ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Layer button backgrounds
Good point. I do like the full color fill you show, Andrew. However, I think we need a better way of indicating which layers are visible. Perhaps a little X or checkbox icon on the button? I already dislike the current buttons' indication of which layers are visible (change of fill color and text color with inset or outset border). Maybe something better can be done. Photoshop (and also GIMP) use a small on/off icon that looks like an eye to control layer visibility. This may or may not be a good way to do it, but it is certainly a familiar UI to many people. Stephen Ecob Silicon On Inspiration Sydney Australia www.sioi.com.au ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Layer button backgrounds
On Thu, Aug 18, 2011 at 11:23 AM, Steven Michalske smichal...@gmail.com wrote: http://wpsoftware.net/andrew/dump/mockup.png I really like this one. Bonus points for setting layer color by clicking on the colored rectangle. Er, maybe shift-click for that. I would have assumed that clicking would toggle visibility on/off. One thing I like about Andrew's most recent mockup is that the visibility of the currently selected layer is greater than the present arrangement (radio buttons). It's an advantage for me to have good peripheral vision visiiblity of which is the current layer, as my focus is usually close to the center of the screen. Stephen Ecob Silicon On Inspiration Sydney Australia www.sioi.com.au ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Off topic: request for a little help
Hi Andy, On Wed, Aug 17, 2011 at 6:07 PM, Andy Fierman andyfier...@signality.co.uk wrote: Hi Stephen, FWIW, It's not clear to me if the prices shown are in $AU or $US and the option to select one or the other doesn't appear to change the prices shown on the products or in the cart. Which browser and OS are you using ? I'm in the UK on a fairly throttled broadband connection and the pictures took some seconds to load. How big are the pictures? Can they be shrunk and still be clear enough not to look silly? That would speed up page loading. Thanks, I think I'll do that. There's nothing to say what SOI is all about. Some sort of About page would give the customer a bit more of a feel for what SOI is offering, what makes it special, different from any other place. All the usual business speak about Unique Selling Point etc. I'm a customer: talk to me; give me a reason to walk in your shop, poke about your shelves and buy your stuff. The Conditions of use page maybe should be renamed Terms and Conditions to make it clear that that is what they are as opposed to some conditions of use of the website, which they are not. Thanks for those pointers, they are just the sort of thing I was looking for :-) Best regards, Stephen Stephen Ecob Silicon On Inspiration Sydney Australia www.sioi.com.au ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Gschem and footprints
On Wed, Aug 17, 2011 at 6:35 AM, kqt4a...@comcast.net wrote: I am sure this has been done to death but I have to ask I am a beginner and the way I am using gschem and pcb is quite awkward I open my schematic in gschem and open pcb Then when I add a component in gschem I switch to pcb to search for a footprint When I find the proper footprint in pcb I switch back to gschem and manually edit the properties to add the footprint name I MUST be doing something wrong A little help please Richard, there are a few different ways of doing this. My favorite is to use the gattrib program. I lay out my schematic without assigning footprints, and then open the schematic in gattrib and assign them in one go. gattrib has a spreadsheet style layout so I can quickly and easily assign footprints, change values etc. gattrib is included in most distributions of gEDA. Stephen Ecob Silicon On Inspiration Sydney Australia www.sioi.com.au ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: personal component library frustration-HELP/suggestions please?
Hi John, On Tue, Aug 16, 2011 at 10:07 PM, John Hudak jjhu...@gmail.com wrote: Thank you Stephen. When you say 'others rely on them'..Why do they rely on them? I get the feeling that there is some feature or property that some ppl find important enough to use them (over the other libraries). M4 footprints are macros - each one describes a family of footprints. For example one M4 footprint can describe a whole family of footprints such as the DIP family. When the macro is called you just specify how many pins - so calling the macro with value 8 gives you an 8 pin DIP package, calling it with 14 gives you a 14 pin DIP package etc. M4 is not essential - it's still possible to manually belt out DIP8, DIP14, DIP16, etc instead. My first attempt at creating symbols is with DJboxsym. It was successful but the second two bullet points at the website made for more questions without answers that could possibly throw up roadblocks further down the road: 1. symbols are in my compromise' format..u HOW compromised? What is compromised? I don't know what compromise DJ is referring to. It doesn't matter though - DJ has defined a simple text format that DJboxsym converts into a symbol. Once it has been converted to a symbol you can work with it just like any other symbol - it is not 'compromised' in any way. 2. No DRC support (use my sym2/csv2sym programs for that). What the heck is DRC (not spelled out anywhere - first rule in writing a document that I learned in grade school was ALWAYS spell out an acronym the first time it is used), and now I need another special program that does what??? And how does it alter the route to attaining my goal?? DRC = Design Rule Check. For a schematic typical DRCs include checks for unconnected pins and for shorted nets (eg GND shorted to VCC) Computerised DRC is not essential but rather a useful aid. The old school (pen paper) way to achieve DRC is to have another engineer look through a print out of your schematic and check for errors. DRC programs aid this task by automatically detecting some simple but common mistakes and drawing your attention to them. As an enduser, I personally don't care if it is written in perl, python, pascal, smalltalk, lisp, algol68 or Cray Fortran. As a developer, it may be important. As a result, thinking that there is something 'non-native' in this approach, I looked for others. BTW, the link does not work - Wireshark informs me that the route is established but does not respond..time out error. You can use a cached copy: http://webcache.googleusercontent.com/search?q=cache:http://vivara.net/cgi-bin/djboxsym.cgi Stephen Ecob Silicon On Inspiration Sydney Australia www.sioi.com.au ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Off topic: request for a little help
Sorry to be off topic, but I can't think of a better place to ask for help. I've recently set up a web shop to sell Xilinx FPGA development boards: www.sioi.com.au Yes, the PCBs were all designed with gEDA :-) The server is here in Australia, and I believe it's virtualised and thus can have a significant start up delay. I'm worried that the site may be too slow to load in countries distant from Australia, or that the site may in some way fail to attract people to the product. If you're willing to help then please check out the shop and let me know if there's anything amiss - would you consider buying the product, or is there something in the site that would deter you ? TIA, Stephen Stephen Ecob Silicon On Inspiration Sydney Australia www.sioi.com.au ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: personal component library frustration-HELP/suggestions please?
Hi John, On Tue, Aug 16, 2011 at 7:24 AM, John Hudak jjhu...@gmail.com wrote: I always add the options skip-m4 and use-files because I don't want any of the M4 generated footprints, ever. But this may be due to personal prejudice. This brings up another issue I am havingAs a neophyte to this tool set (but not to EDA tools in general), what is the deal with m4 files? I've read through a lot of stuff in this area, dating from 2003 through now, and I still don't know if m4 files are good/bad? to be used/avoided? I'd guess the majority of the community don't use it, but there are certainly some who rely on it. I am attempting to put a EDA workbench together in a reasonably integrated way. Part of this is to create a (local) big symbol library so that it can be used and managed. What I don't want to do is grab component and footprint libraries that are old, brittle, or cause gschem or PCB to die. From my perspective, all of the inconsistent information is very confusing. Quite simply, where is the 'best' symbol and footprint library and the best way to create compatible symbols and footprints? Sorry, there is no agreed 'best' way. Various members of the community use the tools in widely varying ways. The tools are flexible enough to work well for for applications ranging from AC power wiring looms to ASIC layout. (After going through 3 different methods of generating symbols, it seems that creating one graphically within gschem is the one least laden with holes...true?) I sometimes use that method, but my current work is with FPGAs and I find the best way for making the symbols I need is DJboxsym: http://vivara.net/cgi-bin/djboxsym.cgi This tool is very convenient for my FPGA work, but when I'm working with BJTs, FETs, diodes and triacs I use the graphical route. Stephen Ecob Silicon On Inspiration Sydney Australia www.sioi.com.au ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: personal component library frustration-HELP/suggestions please?
Hi John, I think you'll find it easiest if you ignore M4 at the start - you don't need it. One great resource is gedasymbols: http://www.gedasymbols.org/ There are are lots of symbols and footprints there that have been contributed by the community. You can search for them by name or browse through the contributions of the various contributors. You may well find that one of the contributors has similar interests to your own, and has already created many of the symbols and footprints that you need. In that case download them and start modifying and adding to them as needed. Contribute you mods back to the community when you're done, if you wish. Stephen Ecob Silicon On Inspiration Sydney Australia www.sioi.com.au ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Tag-Connect TC2030-MCP(NL) footprint, expert review
Hi Colin, On another note, have any of you used spring-pin connectors for programming/debug connectors to save space and BOM cost? I have been thinking about how I would design my own spring-pin programming connector. I've been using AVX solo stacker 16 way parts for this type of thing: http://www.avx.com/docs/catalogs/9158.pdf Those Tag Connect parts look nicer though, Solo Stacker has optional lugs for alignment but no mechanism for locking What's the pricing like for the Tag Connect parts ? Regards, Stephen Stephen Ecob Silicon On Inspiration Sydney Australia www.sioi.com.au ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Gallery of PCBs designed with PCB
Can someone refresh my memory ? A while back someone mentioned a web page that has a gallery of PCBs laid out with gEDA PCB - but I can't remember where it is. Anyone know ? I've recently completed a PCB that I'm quite proud of and would like to submit it for inclusion if possible. TIA, Stephen -- Stephen Ecob Silicon On Inspiration Sydney Australia www.sioi.com.au ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Gallery of PCBs designed with PCB
On Wed, Aug 10, 2011 at 4:25 PM, DJ Delorie d...@delorie.com wrote: That would be www.gpleda.org, our own home page ;-) Click on Links in the upper right. Thanks DJ :) I'm embarassed - I looked at www.gpleda.org but totally missed it! Stephen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Anybody ever had a board assembled (pick and place)?
On Thu, Jul 28, 2011 at 5:35 AM, yamazakir2 yamazak...@gmail.com wrote: I sometimes get boards done at 4pcb, I didn't know they do assembly. How much to they charge? And how big of a reel do you have to send them? And you just cut tape the amount of parts you need to assemble the amount of boards you want to manufacture? A length of tape with no reel can be put onto a spare reel quite easily, there's usually no charge. The tape does need a leader of around 300mm (varies) that has no components. If your tape has no leader then one option is to junk the components on the leader length - not very expensive if you're talking about 60 millicent resistors but a problem for expensive components. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT - non-contact digital current loop sniffer
On Thu, Jul 14, 2011 at 1:18 AM, David C. Kerber dker...@warrenrogersassociates.com wrote: Hi, electronics gurus - We have an application where we need to passively monitor a digital current loop (no data sending by us), with a data rate of 9600 baud. We already have solutions for tapping into the circuit, but in some of our customers' cases the circuits don't have enough drive capability to add another load to it. So we're looking for a non-loading, and preferably non-contact solution, such as a inductive pickup or hall-effect pickup, that hopefully wouldn't require us to break into the circuit. Does anybody know of such an animal? If not, it's also possible that we might contract to have one designed, but that's not decided for sure yet. It's a fairly electrically noise environment, but not extreme, and the sensor itself would likely be installed inside an already-existing box on the wall. The circuit runs at 45mA for the high signal, and the low is 2mA. Is the current flowing through a length of accessible wire at some point, or is it only accessible in a PCB trace ? If it flows through a length of wire then running it through a current transformer could work well. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Remove solder mask from polygons
On Thu, Jun 30, 2011 at 2:23 AM, George Boudreau george.boudr...@gmail.com wrote: Hi. I am working on a micro-stripline layout and the presence of the soldermask on portions of the board will cause problems. With gEDA/pcb micro-stripline work is a drafting task consisting of numerous polygons. Is there a method/switch that will allow me to remove blocks of the solder mask. This exposed copper will be gold plated. Regards, George gEDA/pcb has no easy way to do this task. If I were doing it, I'd use this approach: 1. create a new layer, let's call it mask openings 2. place polygons in the new layer that correspond to the extra mask openings that you want 3. when you're done, export gerbers 4. hack the gerbers - a. Remove the drill holes from mask openings gerber (PCB will have assumed it's a copper layer and added all through holes) b. Merge the mask openings gerber with the standard mask gerber To do the gerber hacking I'd use gerbv to find out which apertures are used for what and then a text editor to remove the through holes and merger the gerbers. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB invalid free with latest git
On Fri, Jun 24, 2011 at 9:43 AM, Ethan Swint eswint.r...@verizon.net wrote: On 06/23/2011 07:21 PM, Ethan Swint wrote: On 06/24/2011 03:45 AM, Andrew Poelstra wrote: On Wed, Jun 22, 2011 at 09:26:09PM -0700, Russell Dill wrote: I was selecting a net when PCB crashed. Has anyone else seen this? I can confirm valgrind is unhappy but cannot produce a crash. Yes, I see it multiple times a day. ;) A bit more detail - I've seen this crash for a couple of years, but hadn't had anyone else reproduce it. I last reported it a few days ago: http://www.seul.org/pipermail/geda-user/2011-June/054585.html Yes, I see it also. I've been using vanilla gtk-hid builds and experiencing it for around the last year or so. Stephen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB DRC accuracy?
On Wed, Jun 22, 2011 at 6:50 AM, Andrew Poelstra as...@sfu.ca wrote: We are working on moving pcb toward metric base units -- then a mm would be 10^6 nm rather than about 3937.00787 cmils like we have now. Thanks for your work on this Andrew, it is a much anticipated improvement :) I see that you've made quite a few commits, is the changeover almost complete ? Stephen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Jumpers on single layer PCBs
On Wed, Jun 1, 2011 at 6:59 AM, Thomas Oldbury toldb...@gmail.com wrote: Oh. Thanks anyway. Any hack-ish way to add this in? (Because I'd like each jumper to have a refdes and BOM entry if possible.) The hack I use for solder jumpers is to make a footprint that is open circuit, and bridge where needed with copper text. DRC ignores text, even when it is on copper layers. So placing a '-' character or a '|' character on copper with a suitably large font provides an electrical connection without upsetting DRC. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Two things ... or actually, three
- Zero length lines in PCB: I found that when drawing lines in PCB, I think you're tripping over the metric-rouding bug, where what you're seeing is lines that are 0.01 mil long. We're working on that with the metrification of PCB. Is there already some sort of script to eliminate those micro-lines? And would it be a good idea if I wrote such a script? Or is it not advisable to eliminate those lines, for reasons of connectivity? Connects - Optimize routed tracks - simple optimization will remove micro-lines. Generally it is a good thing to do so - they are a nuisance for hand editing, and prevent the mitering optimizer from mitering corners that contain them. One thing to be careful of is that removal of micro lines that are inside a pad can cause a DRC violation. They often appear for pads that are off grid, connecting the nearest grid point to the pad center. Removal of these ones can cause a insufficient copper join overlap DRC violation. I suggest saving before trace optimizing, and also running DRC and netlist optimization before and after, and comparing results. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Two things ... or actually, three
On Tue, May 31, 2011 at 7:21 AM, Richard Rasker ras...@linetec.nl wrote: Op donderdag 26-05-2011 om 22:56 uur [tijdzone +1000], schreef Stephen Ecob: Then two more usage questions: - Zero length lines in PCB: I found that when drawing lines in PCB, sometimes dots (zero length lines) get created inadvertently on corners and bends. This isn't much of a problem, until I start dragging lines and end points in rubber band mode: those dots then get stretched into undesired line segments which I sometimes don't notice until I get DRC errors and warnings about short circuits. Do I recall correctly that someone created a script to filter out those zero-length lines? I can't find anything in the mailing list archives, and it turns out that a regex recognizing Line[X Y X Y ... ] doesn't seem all that trivial to construct. These *may* be fixed up by Connects - Optimize routed tracks - simple optimization. Use this feature with care - it usually removes zero length lines but occasionally it also erases needed trace segments by mistake. I recommend saving first and performing DRC check and net connectivity check (o key) both before and after, checking for any changes - there /should/ be none. The trace optimizer only touches autorouted tracks by default - if you want it to work on manually routed traces you need to clear the Connects - Optimize routed tracks - [/] Only autorouted nets checkbox. Thanks for the suggestion, but it messed up the layout something wicked: over a 100 short circuits in my 1800+ nets. I'd prefer a simple script to weed out lines of 0 and 1 mil length, and I don't mind writing it myself if necessary. Anyway, thanks again, best regards, Richard Rasker Oh sorry, we're writing emails at the same time! You could consider making a stripped down version of Connects - Optimize routed tracks - simple optimization. Part of if removes microlines. The code is in pcb/src/djopt.c around line 1200. Look for the text LONGEST_FRECKLE ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Two things ... or actually, three
The trace optimizer only touches autorouted tracks by default - if you want it to work on manually routed traces you need to clear the Connects - Optimize routed tracks - [/] Only autorouted nets checkbox. Thanks for the suggestion, but it messed up the layout something wicked: over a 100 short circuits in my 1800+ nets. I'd prefer a simple script to weed out lines of 0 and 1 mil length, and I don't mind writing it myself if necessary. One way to help the community is to file a bug report at Launchpad for this. https://launchpad.net/pcb/+bugs?field.status=Newsearch=Searchstart=0 If you are happy to share your layout with the world you can attach it to the bug report so that the developers can easily reproduce the bug. If you can't share the layout then consider stripping away most of the layout until you have a small fragment that still triggers the bug. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Two things ... or actually, three
Then two more usage questions: - Zero length lines in PCB: I found that when drawing lines in PCB, sometimes dots (zero length lines) get created inadvertently on corners and bends. This isn't much of a problem, until I start dragging lines and end points in rubber band mode: those dots then get stretched into undesired line segments which I sometimes don't notice until I get DRC errors and warnings about short circuits. Do I recall correctly that someone created a script to filter out those zero-length lines? I can't find anything in the mailing list archives, and it turns out that a regex recognizing Line[X Y X Y ... ] doesn't seem all that trivial to construct. These *may* be fixed up by Connects - Optimize routed tracks - simple optimization. Use this feature with care - it usually removes zero length lines but occasionally it also erases needed trace segments by mistake. I recommend saving first and performing DRC check and net connectivity check (o key) both before and after, checking for any changes - there /should/ be none. The trace optimizer only touches autorouted tracks by default - if you want it to work on manually routed traces you need to clear the Connects - Optimize routed tracks - [/] Only autorouted nets checkbox. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Task list for: Solving the light/heavy symbol problem
On Wed, May 25, 2011 at 5:25 PM, Tom Pope introc...@gmail.com wrote: Just dwelling on the 'what' phase a little more, can we start a few pages on the wiki for people to list: a) all the workflows people would like supported (maybe break it down into newby GUI workflows, 'power user' GUI workflows and scripted flows. b) new features wishlist c) jobs that need doing (and who's doing them) If someone can spell out what's desired I'm happy to help out making symbol and footprint libraries. One of the things I'd like to see is to a library containing all(most) of the land patterns for some of the popular chip vendors eg maxim- http://www.maxim-ic.com/design/packaging/index.mvp?a=2f= ,TI -http://focus.ti.com/lit/an/sbfa015a/sbfa015a.pdf , Atmel etc. http://www.xilinx.com/support/documentation/user_guides/ug385.pdf ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: cvs.gedasymbols.org and gschem
I would like to see some options added to the symbol library dialogue: 1. Create a new (e.g. local) library 2. Copy an existing symbol to another (e.g. local) library 3. Create a completely new symbol (perhaps using a wizard interface) Incorporating DJboxsym (or similar) into the wizard would be nice. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Reinventing the wheel
On Sat, May 21, 2011 at 1:26 AM, Kai-Martin Knaak kn...@iqo.uni-hannover.de wrote: Colin D Bennett wrote: Not to get into the whole light/heavy symbol debate Maybe, it is time to look at this issue again. When I first read geda documentation, there were already references that this had been discussed ad nauseam. As a result, the default lib was the way it was and is. This is six year back now. Since then, this topic has not been raised on the mailing list. But there are Except for some bug fixes, the default lib stayed the same for all the years. No symbols were added, none was removed, nothing was restructured. If the default lib is to be changed now, then there should be some kind of new consensus on the heavy/light issue. Else, the effort might end in religious war and, or frustration. There will always be a place for both heavy and light. People's work flows vary too much to limit gEDA to just one. One thing worth thinking about is closer integration of gschem and pcb with gedasymbols.org. If our programs obtained symbols directly from there it would get people out of the mind-set that there is just one library of symbols. The reality is that our community provides a bazaar of different symbols and philosophies of symbol creation. It would be great if we also had an easier way to contribute symbols back (perhaps with just a mouse click or two). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB crash
footprint converts fine for PCB fetched from GIT on 2011-03-29 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Setup Groups in PCB for 4-layers
On Thu, May 5, 2011 at 5:43 AM, Rob Butts r.but...@gmail.com wrote: I'm not clear on the groups in the PCB preferences. If I want to auto route a board in 4 layers how do I set up the groups? Thanks From PCB Preferences - Layers - Change group you can add or remove layers, and change their order. Groups are a convenience - you can use them to map multiple layers in the PCB program to one physical copper layer. Useful, but it's probably easiest to ignore this feature when you're starting out. Use PCB Preferences - Colors - Layer colors to give the layer colors that suit you. Make sure to save your colors, as they are will not be stored in your PCB file. To start autorouting: * Select the Rout Style that suits you (bottom left) Signal/Power/Fat/Skinny. You can edit their thickness and spacing by clicking the Route Style button. * Hide the layers that you want the autorouter to leave untouched (colored buttons at top left) * Refresh ratlines (keypress o) * Select the ratlines that you wish to route (eg Select all visible objects) * Start the autorouter (Connects - Auto-route selected rats) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB+GL - now with background image rendering support!
On Wed, May 4, 2011 at 7:37 AM, Peter Clifton pc...@cam.ac.uk wrote: On Tue, 2011-05-03 at 19:46 +0200, Kai-Martin Knaak wrote: Peter Clifton wrote: I'm very close to being able to push the basic 2D portions of PCB+GL into git HEAD. I feel like a supporter at the course of a marathon race: Go, Peter. Go! Ok, spurred on by that encouragement, I've tidied up and pushed the first couple of PCB+GL patches to git HEAD. git HEAD PCB will now render using OpenGL by default with a GTK HID Excellent, opening the champagne now! ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Out and In symbols in gschem getting net names to come out in PCB
On Mon, May 2, 2011 at 8:49 AM, Rob Butts r.but...@gmail.com wrote: I'm using out and in symbols in gschem to label nets in a schematic and tie nets together without traces running everywhere. I set the net attribute of the corresponding out and in symbols in the schematic to the same value (clk for example) and connect these symbols to various pins of various chips. When I run gsch2pcb and look at the netlist I don't see those nets listed which makes me feel the pins of all the chips I tie the out and in symbols to are not connected. How do I use these symbols correctly? Thanks For some reason gschem insists that all nets end in the two characters :1 So a net that I would normally call VCC I call VCC:1 in gschem I don't know why, but that's the way it is. Failure to add the :1 results in behaviour like what you describe. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Out and In symbols in gschem getting net names to come out in PCB
On Mon, May 2, 2011 at 9:16 AM, Rob Butts r.but...@gmail.com wrote: Really? So now instead of having a nice clean schematic with net names like clk, _clk, reset and _reset I have to have clk:1, _clk:1... Is the way around that making the net attribute not visible and making the value attribute visible giving it the net name I want to show up on the schematic? That would work, but then you have the burden of strictly keeping your net attributes and name attributes synchronised. Failure to keep them synchronised would result in nasty inconsistencies between your human readable schematic and the machine output netlist. Are there any gschem oldtimers around who can explain the rational for the :1 requirement ? If there's no good reason for it I'd be happy to write a patch that removes it. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Split ground planes and zero ohm jumpers
What, if there was a way to flag a track as don't look for connectivity check? You'd attach the flag to the segment that bridges the domains. That way, the DRC check would still be sensitive to violations at other places. Such a DRCignore flag might have more legitimate uses. E.g, the outline lines may be be marked like this if vias deliberately hang over the edge of the board. It would certainly be useful - I'd use it on just about every board I lay out. This idea is close to what was discussed in January 24-28 in the thread gEDA-user: gschem: directly connecting two nets? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: place to buy SMPS transformers?
On Fri, Mar 25, 2011 at 5:36 PM, yamazakir2 yamazak...@gmail.com wrote: Anybody know of a source, other than digikey, that sells prefabbed prewound SMPS transformers? Digikey has a few, but their selection pretty limited. Shinhom have some: http://www.shinhom.com/produc6-1.htm Their prices are pretty good, but MOQ is usually 600 - 2000. If you're only after a few then the quickest way is probably to rip up an ATX PSU - they have a push pull transformer that does mains voltage down to 12V, 5V, 3V3 and -12V they also have a flyback that does AC to 5V at 2-3A for the standby power. There are plenty of schematics for them on the web, there's very little variation from brand to brand - someone good did the design about 20 years ago and it's been endlessly copied with minor tweaks. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Soldering tips
My favorite tool for desoldering is a hot air blower. It may look like a glorified hair dryer, but it works like a charm. No damaged tips either :-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PCIe x1 connector footprints
I'm looking for PCIe x1 footprints, both card and motherboard sides. Ethan Swint posted PCIe x4 footprints to this list in February 2009, my current plan is to reduce these down to PCIe x1. Has anyone used Ethan's footprints ? It'd be nice to know if they've been fabbed and loaded successfully, or if anyone has improved them in some way. BTW thanks for posting the x4 footprints Ethan! ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Board cleaner recommendations
It's crucial for parts to be quite dry *before* soldering - otherwise the rapid boiling of trapped moisture can cause components to crack. *After* soldering, it's much less of an issue. Many components can be washed with water and detergent, no problem. Most resistors, ceramic caps and tantalum caps should be fine. Wire wound components (inductors, transformers) may be a problem as there's lots of gaps for moisture to get in. Aluminium caps often come in washable and unwashable versions - it may be worth paying a little more for washable. If you do wash with water it's probably a good idea to follow up with a wash in alcohol - the alcohol displaces the water and then evaporates better. Isopropol alcohol is good, methylated spirits is probably OK. Finally, a good dry is needed before powering up. Regarding de-ionised water: it's cheaper than distilled water and not as pure, you can use distilled water in its place. Depending on where you live, tap water may be fine or not fine - the mineral content varies hugely from location to location. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Board cleaner recommendations
Thanks for the helpful information. Are ICs and LEDs generally fine to wash in water and/or detergent? Yes, should be fine - but probably a good idea to post wash with alcohol and certainly give them a good dry. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Board cleaner recommendations
On Thu, Feb 24, 2011 at 8:46 AM, yamazakir2 yamazak...@gmail.com wrote: So am I getting this right? Step 1. Flux Remover Step 2. Wash with soap and water (dish soap) Step 3. Wash with Isopropyl Alcohol Step 4. Dry Yes, if the water has low mineral content. That should leave me with a nice clean board correct? Assume I have a high mineral content tap water. If your tap water has a high mineral content then you should get some distilled water - it's not expensive and will work better. I also just read this: http://nuxx.net/wiki/Flux_Removal A bit different from my normal procedure, but seems to work well. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Board cleaner recommendations
On Thu, Feb 24, 2011 at 9:34 AM, yamazakir2 yamazak...@gmail.com wrote: Can I use this instead of distilled water? http://www.mgchemicals.com/products/406b.html Looks like you could use it after IPA for cleaning off rosin type fluxes. Could be worth a try. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb plugin smartdisperse fails on load
So DJ's teardrop plugin and Ben Jackson's smartdisperse plugin are now both broken because of changes made to PCB head in the last few months. This raises a question for me - should these plugins be incorporated into PCB head ? These plugins were written before I joined this list, has the rationale for keeping them separate vs. incorporating them into head been thoroughly discussed ? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb plugin smartdisperse fails on load
The policy is that we allow anyone to write plugins for their own use, and if they want to share them, they may. I see no reason to require authors to contribute their plugins to the core pcb code if they do not wish to. I don't want to /require/ anyone to do anything :) Both plugins are free SW (GPL 2), so the developers are /free/ to incorporate them into PCB head. They both sound useful, so I suggest we incorporate them. Are there good reasons not to ? Cheers ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: polygon regression in pcb+gl
On Mon, Feb 21, 2011 at 1:51 PM, Kai-Martin Knaak k...@lilalaser.de wrote: Ineiev wrote: Pushed to git-head. Great! Congrats to your new status! The geda project got a new dev! This is really good news :-) +1 :-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB fab with = $5 with 50 qty order?
On Thu, Feb 17, 2011 at 7:59 AM, yamazakir2 yamazak...@gmail.com wrote: The board size is 6.275x1.705. Modest amount of holes/vias, nothing too crazy. Tolerances are standard, I think the default setup in pcb. Shipping to the US, specifically CA. Then it's certainly do-able. The price from custompcb.com for those dimensions is $75 set up, $2.59 per board and shipping to USA ~$14 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB fab with = $5 with 50 qty order?
On Thu, Feb 17, 2011 at 8:38 AM, Ben Jackson b...@ben.com wrote: I would not recommend CustomPCB (aka Silver Circuits) for a 50 board run. I've used them before and the individual boards have required too much attention to imagine using them for 50+. I got one batch where most of the vias did not conduct (my board easily exceeded the DRC requirements). They were happy to replace my order but they screwed up the drill sizes for some connectors (which I worked around by mangling the connectors). Some of my 8mil traces were barly 3mil wide in places. I will note that I have ordered from them knowing full well what I'll get for the price, but for qty 50 I'd want more plug and play. I would never use them for a PCB going in a kit! Ouch! I'll think twice before ordering from them again ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pads, mask and solder paste
I've added this patch to the corresponding LaunchPad bug, #718342 My opinion is that the patch improves PCB's generation of the solder paste and has a very low risk of creating undesired side effects. I recommend it for early incorporation into GIT head. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pads, mask and solder paste
On Mon, Feb 14, 2011 at 8:08 AM, Kai-Martin Knaak k...@lilalaser.de wrote: 2) Pads partly covered by solder mask should receive a solder mask pillow that corresponds to the hole in the mask, rather than to the pads copper dimensions. Such partly covered pads are useful as a heat sink. This patch against GIT head does what you describe: --- a/src/draw.c +++ b/src/draw.c @@ -544,7 +544,10 @@ DrawEverything (BoxTypePtr drawn_area) || (!TEST_FLAG (ONSOLDERFLAG, pad) side == COMPONENT_LAYER)) if (!TEST_FLAG (NOPASTEFLAG, pad)) - DrawPadLowLevel (Output.fgGC, pad, false, false); + if (pad-Mask pad-Thickness) + DrawPadLowLevel (Output.fgGC, pad, true, true); + else + DrawPadLowLevel (Output.fgGC, pad, false, false); } ENDALL_LOOP; } I've only given this a quick test, it works for the S005.fp mentioned before. I'd appreciate it if other could check the patch to see if it causes problems in other areas. Limiting the paste size to min(Mask, Thickness) seems like a good idea, but can anyone think of a case where you'd actually want the paste opening to be larger than the solder mask opening ? Stephen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Best use of my time? [WAS: Re: Open Collector Error Checking]
Right now I've got PhD work which I'm failing at (I'm on medical leave due to being depressed), and some part-time paid work trying to avoid going broke (which is otherwise imminent) so I can keep paying the rent. Do take care - I've had depression and know how debilitating it is. I really value your contributions to GEDA, and hope that your situation will improve soon! With best wishes for your well being, Stephen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pads, mask and solder paste
On Tue, Feb 15, 2011 at 10:14 AM, DJ Delorie d...@delorie.com wrote:
Limiting the paste size to min(Mask, Thickness) seems like a good
idea, but can anyone think of a case where you'd actually want the
Can you add a check for a fully tented pad? I.e. if mask==0, don't
draw anything?
Sure.
--- a/src/draw.c
+++ b/src/draw.c
@@ -543,8 +543,13 @@ DrawEverything (BoxTypePtr drawn_area)
if ((TEST_FLAG (ONSOLDERFLAG, pad) side == SOLDER_LAYER)
|| (!TEST_FLAG (ONSOLDERFLAG, pad)
side == COMPONENT_LAYER))
- if (!TEST_FLAG (NOPASTEFLAG, pad))
- DrawPadLowLevel (Output.fgGC, pad, false, false);
+ if (!TEST_FLAG (NOPASTEFLAG, pad) pad-Mask 0L)
+ {
+ if (pad-Mask pad-Thickness)
+ DrawPadLowLevel (Output.fgGC, pad, true, true);
+ else
+ DrawPadLowLevel (Output.fgGC, pad, false, false);
+ }
}
ENDALL_LOOP;
}
I've given it a quick check, works fine for my current project (mixed
TH SMD, some SMD with mask opening smaller than copper area for
sinking heat).
Any other feedback ? I'll let this sit for a day or so, if there are
no further corrections or suggestions I'll then log it on LP.
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Re: gEDA-user: pads, mask and solder paste
On Mon, Feb 14, 2011 at 6:27 AM, Kai-Martin Knaak k...@lilalaser.de wrote: Hi. The solder paste pattern emitted by PCB seems to coincide exactly with the copper of the pads. This is a reasonable default. But there are use cases where a different solder paste size is better. 1) A pad completely covered with solder mask should not receive any solder paste. This kind of pads are useful a way to achieve tracks in footprints. I've tried to do this - see the attached footprint ResCu250mOhm-fab.fp This doesn't quite work. In the GTK hid the solder mask is rendered as a very thin line. The gerbers contain the solder mask opening as a line of width 0, iirc. When I had this PCB fabricated the fab house got confused and changed the width of the solder mask opening to be the same as the track width! Next time I send out to fab, I'll hack the gerbers in an editor to totally nuke the undesired solder mask opening paths. 2) Pads partly covered by solder mask should receive a solder mask pillow that corresponds to the hole in the mask, rather than to the pads copper dimensions. Such partly covered pads are useful as a heat sink. Yes, that works fine - see S005.fp. This is for a SMD bridge and works exactly as you've described. Is there a way to achieve these goals? 1.5 out of 3 is a start :-) ResCu250mOhm-fab.fp Description: application/pcb-footprint S005.fp Description: application/pcb-footprint ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pads, mask and solder paste
2) Pads partly covered by solder mask should receive a solder mask pillow that corresponds to the hole in the mask, rather than to the pads copper dimensions. Such partly covered pads are useful as a heat sink. Yes, that works fine - see S005.fp. This is for a SMD bridge and works exactly as you've described. Yes, the solder mask is smaller than the copper of the pad. But no, if I render the gerbers, the solder paste is still as large as the copper. See attachment. If the stencil would be fabricated from these files without modification, there would be solder paste printed on top of solder mask. Oh yes, you're right - I remembered that the solder mask was correct for that part, and mistakenly thought that the paste layer would have been the same as the solder mask. I've successfully made PCBs with this footprint, but haven't needed a solder paste stencil yet (still at the hand assembly stage). I imagine that just a few lines of changed code in PCB would be able to handle this case correctly. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: refdes_renum_slots update
On Tue, Feb 1, 2011 at 9:25 AM, Joshua jos...@laserlinc.com wrote: Here is an update for refdes_renum_slot. New Feature: The tool now takes into consideration the components x position along with its y position when assigning a part number. Thus a screen full of components will be numbered from left to right and then top down. Thank you, sounds useful :-) Existing Features: Assigns a refdes values: Converts refdes values from U?, U?, R?, etc to U1, U2, R1 etc... Respects slotted components. Slotted components are grouped with the same refdes number based on their physical proximity to each other. Do be careful with this - it can cause real pain in cases like: * Two LM324 quad op amp chips in the schematic * One powered from +-5V rails, the other from +-12V Great care needs to be taken when swapping slots in this situation ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Thermals on Pads
The main problem I have is not code, but deciding what such geometry needs to look like it and how to specify it. Whatever we decide we have to live with, as we can't go changing geometry on users with existing boards. I think it would be acceptable to change geometry on the community if it happens at the same time as a new version of the PCB file format. That way PCB files in old file formats could have the old geometry (legacy mode), and newly created ones could have new geometry. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Soldering minute smt
Flux is the secret... Applying flux is the crucial step to success. +1 Get yourself some good quality flux, it makes this sort of problem disappear. I've used Electrolube SMFL (aerosol with dispenser tube) with good results, but there are many good options. Look for something with surface mount rework solder flux or similar in its description. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem: directly connecting two nets?
Perhaps I was going a bit far to suggest full DRC for the actual antenna design. What I really meant was not loosing information for net connectivity checking leading up the antenna. Thinking longer term, why not support DRC checking of inductance and resistance for specially tagged traces ? Of course most nets can simply be thought of as perfect conductors, but if we introduce the concept of a resistive and/or inductive trace it would be very helpful for making small inductors and resistors directly out of copper. My current design implements resistors of 2.5mOhms up to 0.25 ohms purely with copper. PCB's DRC doesn't understand and highlights these resistors in orange, but I can imagine a future PCB where I specified that a particular trace should have a resistance of (say) 10 mOhm and DRC would handle it gracefully. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem: directly connecting two nets?
A similar track is component scenario: PCB fuse track - a dirty trick I've seen in some Honywell boiler controllers.. where a deliberately thin trace is used to act as a fuse. That certainly is a dirty trick! (But on a very tight budget it could make sense). So there are several use cases for treating copper as non-connecting: * low value resistors * fuses * low value inductors * aerials * contacts for solder switches (eg SPDT in solder) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem: directly connecting two nets?
Similar to the last is a jumper location that is connected by copper by default to be cut if an open is needed. Consider this to be a 1 bit PROM. Rick Yes, they're useful. I use them a lot on early revision boards when the design is still subject to change in some areas. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB antenna pattern
On Fri, Jan 14, 2011 at 7:22 AM, Tamas Szabo sza2k...@freemail.hu wrote: I made a loop antenna (for ZigBee too), same problem. I ignore DRC. There was a thread about it, maybe a year ago or more, without any good solution. I've had similar problems when making low value resistors out of copper tracks and when making SPDT solder jumpers with one side closed by default in copper. The PCB codebase currently has no concept that two nets can be joined by copper and yet still be separate nets. Significant architectural changes would need to be made to support this concept. Such changes would be useful, but would need careful thought in these areas: * how PCB defines two nets to be connected * introduction of the concept of non-connecting copper * changes to file formats to support non-connecting copper * what classes of non conducting copper ? RF delay copper / resistive copper / other ? * how to display non-connecting copper ? * how should DRC handle non-connecting copper ? * how should the find command handle non-connecting copper ? Stephen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Random thoughts on the future interface of PCB
On Thu, Dec 9, 2010 at 7:06 PM, Peter Brett pe...@peter-b.co.uk wrote: 1. Would any of the existing maintainers be able to devote more time to gEDA if they had financial support to do so ? In my case: yes. :-/ Peter OK, so that's a 'yes' for question 1! Now for question 2 - money. A few weeks back I was seriously considering paying $5K for Altium. In the end I decided against it (closed source p*sses me off too much), but it did make me realise that I could justify spending that kind of money on pcb software. Now if we're thinking in terms of a $200K per year developer then $5K will achieve next to nothing - but let's think of alternatives. I can't remember the details, but I vaguely recall that a second Google Summer of code with funding of ~$15K would have allowed Anthony to finish the toporouter. http://www.linuxfund.org/projects/pcb/ tells me that $3330 allowed DJ to improve PCB's file import system. So we don't necessarily have to think in $100K's for achieving real results. Now many of us aren't in a position to spend money on PCB software - but what if two other members of our community were also able to afford $5K ? Perhaps three of us could chip in to fund a GSOC equivalent. If that allowed a result like finishing the toporouter (say), I could well judge that to be money well spent. If 7 other people came forward and it was $2K each I'd find it a no brainer. But I realise I'm really ignorant of my own community - am I the only one who would consider funding PCB development by others ? Are there 7 who could afford $2K ? Are there 20 who could afford $750 ? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: component names hide all
On Thu, Dec 9, 2010 at 7:46 PM, uv u...@peterpapp.com wrote: Dears, Is there any simple way to hide all component numbers on the board? Thank you Péter Papp Yes: 1. Select all (Alt+A or use the menu Edit - Select all visible) 2. Enter command mode by typing : 3. Type the command ToggleHideName(SelectedElements) You can make them all visible again by repeating this process. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Random thoughts on the future interface of PCB
I'm aiming to finish University in a few months.. if people would like to fund work on the toporouter, then I would be pretty keen to work on it full time. Regards, Anthony Good, we've established that money could help to improve gEDA :) What I'm *very* unsure of is whether we could raise enough to make a difference. Does anyone have any idea of how many of us make commercial use of gEDA ? As a business user I face the fact that if I choose to use commercial EDA software such as Altium then I'll pay $4K every year for a program that will make me go prematurely bald as I pull my hair out in frustration at bugs that I have no power to fix. I've chosen to use free software instead. Yes, PCB has many shortcomings - but I'm free to fix them. My business is just starting up, so cashflow is tight. At this stage I'm more inclined to contribute to gEDA by coding myself than by paying others to do it for me - but in the future I may have less time and more money. At that stage paying others to improve gEDA would make good business sense. I could easily justify $4K per year, perhaps more - businesses who use Cadence or Zuken are probably paying $20K per year. One business contributing $4K per year is almost insignificant - but 10 could achieve something worthwhile, 50 could fund a full time developer. But it's nothing more than a pipe dream unless there are others out there who think the same. Does anyone else think the same ? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: TRACKERS [was: Re: gEDA-dev: Dev list [was: Random thoughts onthe future interface of PCB]]
I'd welcome feedback from people who actively encounter and report bugs (especially in favour of the move ;)). I'd also welcome feedback from anyone who works with bug reports, test patches, merge code etc... (Doesn't have to be with gEDA / PCB, anything regarding Launchpad / SourceForge). We're hearing complaints that some submitted patches aren't receiving enough attention, but there simply isn't enough maintainer time available to give everyone as much attention as they'd like. If Launchpad makes it quicker and easier for maintainers to process patch submissions then it will help, let's adopt it. If you do trial Launchpad I'd be happy to funnel my bug reports and patches through it, I'd be interested to see how it compares to SF from the patch submitter's point of view. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Removing My* memory alllocation functions
On Fri, Dec 10, 2010 at 2:09 PM, Peter Clifton pc...@cam.ac.uk wrote: On Fri, 2010-12-10 at 11:26 +1100, Stephen Ecob wrote: Hi Peter, Here's my patch that should be equivalent to your patches 0001 followed by 0002. My patch is against GIT head as at commit 466b0183758ef3ca44623c43de60a233b175d2ad Tue, 7 Dec 2010 13:43:19 + (13:43 +) I suggest you check that our patches are equivalent, hopefully that will ensure that no mistakes slip through. It caught a few things I'd changed where I shouldn't have, and although we didn't end up with completely identical changes, I've fixed up my patches and pushed them. Speaking of which.. I really meant to get your name on the commit log, and I did not. VERY sorry about that, especially after all the help you've given me with testing things. AH HECK.. I'm going to break a rule and non-fast-forward push them again with the appropriate credit. Oh, thanks - you didn't have to do that! Anyway, the main thing is it's nice to see all of the tidying up that you've pushed today :-) Best regards, Stephen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Removing My* memory alllocation functions
On Thu, Dec 9, 2010 at 12:10 AM, Peter Clifton pc...@cam.ac.uk wrote: On Wed, 2010-12-08 at 13:40 +1100, Stephen Ecob wrote: Regarding 0002-Not-so-sure-about-these-MyStrdup-calls.patch: buffer.c:984: I can't tell, and suggest playing it safe with STRDUP() if (line) line-Number = strdup (pad-Number); I lumped this one in because we also used strdup for pad-Number when creating the pad. Yes, it will be fine. A pad must always have a valid number. create.c:593: My $0.02: CreateNewText() called with a NULL pointer should be stopped in its tracks with a segfault rather than propagating the error. If you're unsure, though, just hit it with STRDUP() - it preserves the current functionality. Tempting to make it a separate patch at the very least, deliberately stating in the commit that we are changing behaviour. Yes, a separate patch would be better. create.c:788 This is definitely *unsafe*, I have observed calls with NULL pointers at run time. Your line-numbers don't agree with mine, My line numbers are slightly higher than yours. I suspect this is because mine are pre patch 0001 whereas yours are post. In many places patch 0001 removes a line as a result of removing the second parameter to MyStrdup(). For example: - NAMEONPCB_NAME (Element) = MyStrdup (line-Number, - ConvertBufferToElement); + NAMEONPCB_NAME (Element) = strdup (line-Number); So your line numbers will be 1 less than mine for each such entry in patch 0001. but if this is pin-Name, I didn't change that one.. only pin-Number. Oh yes, my mistake - I forgot that there are two calls on adjacent lines. strdup (Number) should be fine as a pin must always have a number. create.c:875 This is definitely *unsafe*, I have observed calls with NULL pointers at run time. Same as above, I left pad-Name as MyStrdup, - STRDUP in the mechanical patch. Yes, same as above. TBH, there are so few cases left, we might even just expand the STRDUP macro in the places where it is required. Sure, sounds good. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Removing My* memory alllocation functions
On Thu, Dec 9, 2010 at 12:24 AM, Peter Clifton pc...@cam.ac.uk wrote: On Wed, 2010-12-08 at 14:26 +1100, Stephen Ecob wrote: Patch0002: we're getting close. I see only one remaining issue: create.c:900: you address this both in patch 0001 and patch 0002 In patch 0001 you preserve the behaviour of the existing code It was still a save MyStrdup - strdup change, so is valid there. Yes, I think it is the correct solution. In patch 0002 you unconditionally call strdup() Was basically what you suggested I think, regarding TextString != NULL. I had presumed it was similar to the CreateNewText() case, but now you point it out below, I see now why that might not have been correct. Yes I've looked at the code further, and I think that the approach you take in patch 0001 is correct. Each element has three names: Description, NameOnPCB and Value. It's entirely possible that at least one of them will be NULL, so an unconditional call would be dangerous. Please disregard my comment of 42 minutes ago create.c:900 Same issue as create.c:593 It's not the same issue. My $0.02 re create.c:593 still stands, but perhaps a better solution would be to put an assert(TextString != NULL); at the start of CreateNewText() I'd be ok with that as a separate patch adding the assert. Beware that asserts typically aren't switched on in a normal build of PCB though. Yes, I've enabled assert() once or twice and it wasn't pretty - too many of the assert()s have suffered code rot. On my list of things to address when I can find the time :) TextTypePtr text = GetTextMemory (Layer); if (!text) return (text); Love to hate that line.. What it means: if (text == NULL) return NULL; It would be tempting to make that TextType *text; if (TextString == NULL) return NULL; text = GetTextMemory (Layer); if (text == NULL) return NULL; But it does have the downside of making things fail silently. Perhaps the assert is the best way to go.. it adds a note to the programmer of what we expect, and the segfault in strdup will still catch any errors if asserts are disabled. I like the code you've written above. If anyone is foolish enough to call CreateNewText() with NULL text it pushes the problem straight back at them. Given that assert()s generally fall on deaf ears, I think that a patch with this code would be best. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: print all sheets in a hierarchy
On Thu, Dec 9, 2010 at 4:22 AM, Kai-Martin Knaak kn...@iqo.uni-hannover.de wrote: Hi. Thanks to the little scheme script print.scm distributed with geda, I finally managed to do non-interactive print of more complex projects. Attached to this mail you can find a little script that descends recursively down a hierarchy of schematics. It prints the contents to postscript in a /tmp and assembles them to a single PDF document. Duplicates are dropped. So subcircuits used multiple times are rendered only once. Thanks Kaimartin, that sounds useful! I've only needed to make a schematic larger than one A3 sheet once. A quick read about gschem's approach to multiple page schematics quickly convinced me that I'd rather shrink my symbols and keep to one page :-( Any improvement to gschem's handling of multiple page schematics is much appreciated :) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Removing My* memory alllocation functions
On Thu, Dec 9, 2010 at 5:52 AM, DJ Delorie d...@delorie.com wrote: Yes, it will be fine. A pad must always have a valid number. Um, no? Oh yes, my mistake - I forgot that there are two calls on adjacent lines. strdup (Number) should be fine as a pin must always have a number. Again... Um, no? Or do you mean a non-NULL number? I mean a non-NULL number. There's no reason to require a non-empty string as a pin/pad number. OK. What about my assumption that all pads and pins must have a non-NULL number ? If that isn't the case I'll need to redo some of my thinking about the changes to MyStrdup() Cheers, Stephen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: print all sheets in a hierarchy
On Thu, Dec 9, 2010 at 5:58 AM, DJ Delorie d...@delorie.com wrote: quick read about gschem's approach to multiple page schematics quickly convinced me that I'd rather shrink my symbols and keep to one page You don't need to shrink your symbols. Symbols don't have an absolute size like footprints - the schematic is scaled to fit whatever page size you print on. Just choose a bigger title block (or no title block) and continue printing on the same paper. Yes, that's how I did it. I meant shrink in the sense of physically smaller on the piece of paper :-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Removing My* memory alllocation functions
On Thu, Dec 9, 2010 at 6:56 AM, DJ Delorie d...@delorie.com wrote: Anything that's STRING in parse_y.y starts off as NULL if it's the string. This is done in parse_l.l. My assumption was wrong, thanks for spotting that DJ. Peter, as a consequence: create.c:789 should use STRDUP() to support NULL pin Number create.c:876 should use STRDUP() to support NULL pad Number buffer.c:984 should use STRDUP() to support NULL pad Number ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: My most recent commit broke Break buffer element to pieces
Sorry about that :-( I've created a patch which fixes it, sourceforge patch ID 3132699: https://sourceforge.net/tracker/?func=detailaid=3132699group_id=73743atid=538813 FixSmash.patch Description: Binary data ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Random thoughts on the future interface of PCB
Boiling it down greatly, Clif and Kaimartin are both asking for more attention from the maintainers. Has the gEDA community given thought to the possibility of paid maintainers ? I'm a relative newbie, please let me know if this has already been thrashed through. If it is worth discussing, I guess the big questions are: 1. Would any of the existing maintainers be able to devote more time to gEDA if they had financial support to do so ? 2. Could we raise enough money to make this viable ? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Random thoughts on the future interface of PCB
On Thu, Dec 9, 2010 at 2:59 PM, DJ Delorie d...@delorie.com wrote: If you want to hire a maintainer, consider that the average senior engineer costs about $200k per year, if you include benefits - and if you want a full time engineer, you'd have to provide them because you'd be replacing their regular job. gEDA just doesn't generate that kind of revenue. I wasn't thinking of a full time maintainer - more along the lines of a couple of events in PCB's past: * I remember when we missed out on the second round of Google Summer of code funding for the toporouter. It was so disappointing! I remember thinking that $15K would have allowed a huge improvement to PCB by allowing the toporouter to be finished - but it wasn't to be. * You wrote the very useful visual DRC system with some financial help from Linux Fund. So no, I can't imagine our small community coming up with $200K per year - but I can just about bring myself to imagine we could raise $15K or so, and I know that even an amount like that can make a considerable difference. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Random thoughts on the future interface of PCB
On Thu, Dec 9, 2010 at 3:11 PM, DJ Delorie d...@delorie.com wrote: * You wrote the very useful visual DRC system with some financial help from Linux Fund. No, I did the schematic importer. Sorry, I must have misunderstood - that was the impression I got from reading this page: http://www.linuxfund.org/press/pcb/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Random thoughts on the future interface of PCB
On Thu, Dec 9, 2010 at 3:16 PM, DJ Delorie d...@delorie.com wrote: There were a bunch of projects scheduled, but even LF couldn't generate enough funding for more than one of them. I'm sorry to hear that :( ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Removing My* memory alllocation functions
On Wed, Dec 8, 2010 at 12:52 AM, Peter Clifton pc...@cam.ac.uk wrote: Note that the second patch gets my test PCB loading again, but does not consider every possible case. Before committing, these MUST be squashed, but it is convenient to keep them separate for now. Thinking about it, a pre-patch converting all safe MyStrdup calls to plain strdup would probably be best, then the MyStrdup - WHATEVER can be purely mechanical along with the rest of the mechanical patch. That sounds good. In the interest of saving your development time (I don't want to keep you from PCB+GL !), I suggest: Of the 51 calls to MyStrdup() 7 are safe because of calling with a fixed string eg MyStrdup (Font, FontEdit) 2 are safe because of calling with the UNKNOWN macro, which can never expand to NULL the remaining 42 should be assumed to be unsafe and replaced with (x) ? strdup(x) : NULL or equivalent I'd guess that many of the 42 are safe but I don't think it's worth the time to exhaustively prove each safe or unsafe. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Removing My* memory alllocation functions
On Wed, Dec 8, 2010 at 4:51 AM, Peter Clifton pc...@cam.ac.uk wrote: Stephen, I'd appreciate your Acked-by: or Reviewed-by: on the attached patches: Patch 0001 is good, but I can suggest some additional MyStrdup() calls that can safely be directly replaced with strdup(): create.c 196: safe because DefaultLayerName array properly initialised in main.c and safely updated in hid/gtk/gui-config.c 593: safe, because CreateNewText() should never be called with NULL. If it is, a segfault would aid debugging. 789: I suggest it is safe. A pin should always have a number. Better to segfault than create a pin with Number==NULL 876: I suggest it is safe. A pad should always have a number. Better to segfault than create a pad with Number==NULL 900: I suggest it is safe. Better to segfault than create a text object with text==NULL 1013: safe. Only called from ActionElementSetAttr(), protected by (argc 2) check 1014: safe. Only called from ActionElementSetAttr(), protected by (argc 2) check file.c 321: Safe. A null pointer would cause WritePipe() to return an error, causing MyStrdup() to be avoided. 393: Safe. NULL Filename would be caught by ParsePCB(), causing MyStrdup() to be avoided. 1169: Safe. A null pointer would segfault in pcb_basename()'s call to strchr() before MyStrdup reached. 1260: Safe. Settings.LibraryTree initialised to non NULL in main.c and kept valid in hid/gtk/gui-top-window.c and hid/gtk/gui-config.c 1923: I suggest it is safe. An attribute should at least have a name. Better to segfault than create an attribute with no name. rats.c 924: Safe. Called with character array. 942: Safe. Called with character array. 944: Safe. Called with character array. 915 and 946 are also safe because of the code flow: found=SearchObjectByLocation (PAD_TYPE | PIN_TYPE, ...) [...] if (found == NO_TYPE) return (NULL); [...] name2 = ConnectionName (found, ptr1, ptr2); It follows that name2 always points to character array static char name[256]; at line 962 Some of these suggestions are slightly speculative, I suggest that you reject any that you aren't comfortable with - better to have a few unnecessary call to your MYSTRDUP() macro than to possibly brake existing code. Patch 0002: I'll run my own mechanical conversion and check that we generate identical diffs. I'll let you know when I'm finished. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Removing My* memory alllocation functions
Regarding 0002-Not-so-sure-about-these-MyStrdup-calls.patch: buffer.c:984: I can't tell, and suggest playing it safe with STRDUP() create.c:593: My $0.02: CreateNewText() called with a NULL pointer should be stopped in its tracks with a segfault rather than propagating the error. If you're unsure, though, just hit it with STRDUP() - it preserves the current functionality. create.c:788 This is definitely *unsafe*, I have observed calls with NULL pointers at run time. create.c:875 This is definitely *unsafe*, I have observed calls with NULL pointers at run time. create.c:900 Same issue as create.c:593 I'll now take a look at 0001, back shortly. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Removing My* memory alllocation functions
Patch0002: we're getting close. I see only one remaining issue: create.c:900: you address this both in patch 0001 and patch 0002 In patch 0001 you preserve the behaviour of the existing code In patch 0002 you unconditionally call strdup() I've looked at the code further, and I think that the approach you take in patch 0001 is correct. Each element has three names: Description, NameOnPCB and Value. It's entirely possible that at least one of them will be NULL, so an unconditional call would be dangerous. Please disregard my comment of 42 minutes ago create.c:900 Same issue as create.c:593 It's not the same issue. My $0.02 re create.c:593 still stands, but perhaps a better solution would be to put an assert(TextString != NULL); at the start of CreateNewText() ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Small patch to aid use of lib dmalloc
On Tue, Dec 7, 2010 at 12:31 AM, Peter Clifton pc...@cam.ac.uk wrote: On Mon, 2010-12-06 at 16:58 +1100, Stephen Ecob wrote: If you use (or intend to use) lib dmalloc with PCB you will find the following useful. I've uploaded a patch against current heaad to sourceforge, ID #3129279, described as follows: Looks useful, I will push it, however, please explain the following first: +# define MyCalloc(a, b, c) calloc((a) ? (a) : 1, (b) ? (b) : 1) +# define MyMalloc(a, b) malloc((a) ? (a) : 1) +# define MyRealloc(a, b, c) ((a) ? realloc(a, (b) ? (b) : 1) : malloc((b) ? (b) : 1)) I don't see why we are adding a synonym with requesting zero bytes / zero items, with requesting one item? I preserved the semantics of the original functions, in case some part of the code relies on them. Is there anywhere (BROKEN) in PCB which requests zero items / bytes, and expects that call to work? Agreed, the semantics of the mymem allocation functions are foolish. A quick check of the parts of PCB that I'm currently using show no dependance on the 0==1 foolishness, but I haven't had time to test all 71 callers of these functions. I'd rather commit: +# define MyCalloc(a, b, c) calloc((a), (b)) +# define MyMalloc(a, b) malloc((a)) +# define MyRealloc(a, b, c) realloc((a), (b)) NB: realloc will do the right thing if the previous pointer passed is NULL, no need to check and swap for a malloc call. Yes, but note the (probably ancient) comment in mymem.c: * this is a save version because BSD doesn't support the * handling of NULL pointers in realloc() I don't know if that is still true for BSD, but we should preserve the workaround unless we are confident that all of PCB's supported platforms work correctly with realloc(NULL, ...) One final nit, I'd prefer not to see the double negative in the header files: #ifndef HAVE_LIBDMALLOC NON D-Malloc stuff #else D-Malloc stuff #endif Could more readably be defined as: #ifdef HAVE_LIBDMALLOC D-Malloc stuff #else NON D-Malloc stuff #endif Sure, happy to fix that. If you feel that your version is better as it matches the various other #ifndef HAVE_LIBDMALLOC you added, then fair enough, I'll push as is pending an answer on the #define questions. FWIW, I'd love to see our own custom memory allocation routines die in a fire. Lets plan to eventually replace them with malloc / realloc / free calls, and this won't be an issue. I thoroughly agree :) I did loose some respect for the dmalloc author(s) when I noticed on their page they can't spell Microsoft Windows correctly. Windoze In general, valgrind (probably not even conceived of when dmalloc was first written), is a much more useful tool for memory leak diagnosis, so I wouldn't go _too_ far out of our way to make things dmalloc suitable. Sure. You still won't see good back-traces for the r_tree allocations, for example. (Given your usage and symptoms, I guess some r_trees are being leaked in the autorouter code?) Just found the leak this morning, turns out it's yet another thing to dislike in mymem.c ;-) So regarding the patch: Dropping the (a) ? (a) : 1 foolishness would be cleaner, but could expose latent bugs in the 71 callers of the mymem allocators. I'm happy to proceed either way. What is your preference ? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Small patch to aid use of lib dmalloc
On Tue, Dec 7, 2010 at 11:48 AM, Peter Clifton pc...@cam.ac.uk wrote: On Tue, 2010-12-07 at 10:04 +1100, Stephen Ecob wrote: Dropping the (a) ? (a) : 1 foolishness would be cleaner, but could expose latent bugs in the 71 callers of the mymem allocators. I'm happy to proceed either way. What is your preference ? Let me push a big patch nuking the My* allocation functions, that would make me feel much happier. Great! It'll be good to lay those functions to rest :) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Small patch to aid use of lib dmalloc
I count 54 locations in head that call MyStrdup() A run time check of calls to MyStrdup() shows: create.c:197 made 0 NULL calls, 48 good calls create.c:219 made 0 NULL calls, 32 good calls create.c:238 made 0 NULL calls, 1 good calls create.c:240 made 0 NULL calls, 1 good calls create.c:286 made 127 NULL calls, 0 good calls create.c:614 made 0 NULL calls, 23 good calls create.c:809 made 364 NULL calls, 436 good calls create.c:810 made 0 NULL calls, 800 good calls create.c:896 made 40 NULL calls, 3576 good calls create.c:897 made 0 NULL calls, 3616 good calls create.c:921 made 0 NULL calls, 4212 good calls create.c:1000 made 0 NULL calls, 924 good calls create.c:1017 made 0 NULL calls, 3552 good calls file.c:321 made 0 NULL calls, 3 good calls file.c:393 made 0 NULL calls, 2 good calls file.c:431 made 0 NULL calls, 2 good calls file.c:1206 made 0 NULL calls, 53 good calls file.c:1297 made 0 NULL calls, 1 good calls main.c:960 made 0 NULL calls, 16 good calls misc.c:726 made 0 NULL calls, 20 good calls misc.c:945 made 0 NULL calls, 1 good calls So calls with a NULL pointer are rare, but there are at least 3 callers that require tolerance of it. Unfortunately my test coverage is low (based on a quick run of loading a small board and autorouting it), as my test only sees calls from 21 of the 54 possible callers. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Small patch to aid use of lib dmalloc
I propose the following solution: 1. replace all calls to MyCalloc() with calls to calloc() 2. replace all calls to MyMalloc() with calls to malloc() 3. replace all calls to MyRealloc() with calls to realloc() 4. replace all calls to SaveFree() with calls to free() 5. retain the MYFREE() macro as its pointer clearing side effect is required 6. treat calls to MyStrdup() on a case by case basis: 6a. calls known to never supply a NULL pointer: replace MyStrdup(x, y) with strdup(x) 6b. calls known to sometimes supply a NULL pointer: replace MyStrdup(x, y) with: (x) ? strdup(x) : (x) 6c. calls where we aren't sure: treat the same as 6b. Notes 7. 1,23 mean that we discard the following side effects of the mymem.c allocators: 7a. logging messages when MEM_DEBUF defined 7b. 0 == 1 logic 7c. alloc failure handling via MyFatal() - EmergencySave() My personal feeling is that 7a 7b are essentially useless and that 7c has almost zero probability of ever actually saving someone from losing their PCB. 8. Instead of simply retaining MYFREE(p) (point 5), we could replace each use of it with an explicit: free(p); p = NULL; Personally I prefer two perspicuous lines to a one line opaque macro. Comments? PS If we achieve consensus I'm happy to code the patch. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Small patch to aid use of lib dmalloc
On Tue, Dec 7, 2010 at 3:06 PM, timecop time...@gmail.com wrote:
5. retain the MYFREE() macro as its pointer clearing side effect is required
8. Instead of simply retaining MYFREE(p) (point 5), we could replace
each use of it with an explicit:
free(p);
p = NULL;
Is this MY prefix actually in the code?
Sure is :)
Most sane places call the kind of free your'e talking about here call
this macro SAFE_FREE() or SAFE_RELEASE() or something. it does
something along the lines of
if (arg) { free(arg); arg = null; }
Actually, in PCB the nearest equivalent to that is called SaveFree
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gEDA-user: Patch for some memory leaks associated with the global PCB structure
I just submitted a patch for some memory leaks that have been annoying me. The soureforge id is #3131063: https://sourceforge.net/tracker/?func=detailaid=3131063group_id=73743atid=538813 Most users won't have noticed these leaks as only around 1MB is leaked each time a new PCB is loaded. The leaks hit me because my high effort autorouter hack experiences the leak at each iteration. It can really add up on a long run. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Random thoughts on the future interface of PCB
Agreed, and I had a similar experience. I was hoping to get a review or just some comments on a couple of patches I submitted (3114991, 3117075). Now I can understand that it was probably in an off beat area and not the topic du jour, so I went ahead and posted it to the patches tracker. No comments there either, and I went to some effort to comment my code well, tried to match the formatting as best I could, and even commented the hunks in the patch set. From looking at your patch I can see that you've put in some substantial work there, and can understand your disappointment. I also contacted Stuart Brorson directly and while he said he would look at the patches he also said: As you might imagine, I'm busy with a number of other projects, so I haven't had much time to devote to gEDA for a long time. I think a lot of would be contributors are inspired to make improvements but get stymied when their first offering falls on deaf ears. As a PCB developer I'm acutely aware that developer time is in very short supply - the lead developers are very busy guys who squeeze in time for PCB as best they can. I know almost nothing about the development of gschem, but my perception is that gschem developer time is even more scarce - I'd guess there are 20 emails on this list about PCB for every email about gschem. I know there has to be a balance here, but I feel that there should always be someone in the dev group that can take the time to respond and give some constructive feedback. I feel the same way - but I recognise that there currently isn't enough gschem developer time for this to be the case. I'm sorry I can't help more, but I do suggest is that you stay on the list - when the developers do come back raise the issue again. Oh, and of course gEDA is free software - if the developers disappear into a black hole you can always start your own branch and become your own maintainer. Public GIT repositories like repo.or.cz make it very easy to host a project. I made my own branch of PCB there a few weeks ago when I wanted to indulge in some source code butchery that the PCB lead developers wouldn't want to touch with a barge pole :) Setting the whole thing up took less than a day. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Chamfer
I don't think chamfering is available. Other related features are available though: Mitering is available from Connects-Optimize routed tracks-Miter. Only works for intersections with one vertical trace meeting one horizontal trace. A puller is available from Connects-Optimize routed tracks-Puller. It shortens and smooths the selected trace. Unfortunately it is a bit unstable, use with caution. Connects-Optimize routed tracks-Global Puller pulls the entire board. The code is very unstable, back up your board before trying it. DJ has written a nice teardrops plugin, see http://www.delorie.com/pcb/teardrops/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Random thoughts on the future interface of PCB
On Sun, Dec 5, 2010 at 2:20 AM, Peter Clifton pc...@cam.ac.uk wrote: On Sat, 2010-12-04 at 11:15 +1100, Stephen Ecob wrote: branch.. sorry). [...] So, a mix of NOT LEAKS, and might be leaks. We need back-traces of the cases where callers are allocating things repeatedly and not freeing them. Because these are showing up in your DMalloc output as being where memory is allocated (pretty generic routines), we would need a back-trace to see which code caused the allocation before any could be fixed. Thanks for looking those over, your observations are helpful. I'll investigate further today. I believe valgrind is good at detecting leaks! So I hear. I should take the time to learn it some time :) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Chamfer
On Mon, Dec 6, 2010 at 9:28 AM, George M. Gallant, Jr. ggallant...@verizon.net wrote: Well that was interesting. The tracks-Miter made it look very sloppy and the completely hung PCB. Using version 20100929. look very sloppy - could you be more specific ? A couple of notes on using the Miter function: * autorouted tracks sometimes refuse to miter. Use Connects-Optimize routed tracks-Simple optimization after autorouting and before mitering. * if you want to miter hand routed tracks then clear the checkbox Connects-Optimize routed tracks-[]Only autorouted nets ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Small patch to aid use of lib dmalloc
If you use (or intend to use) lib dmalloc with PCB you will find the following useful. I've uploaded a patch against current heaad to sourceforge, ID #3129279, described as follows: PCB supports the use of the dmalloc library as a configuration option. This patch makes the PCB source code more friendly to libdmalloc in the following ways: * Some source files that allocate memory from the heap but fail to include dmalloc.h now do so * The mymem.c low level memory routines are replaced with corresponding libdmalloc calls (if libdmalloc is available). This is helpful as these routines otherwise obscure the __FILE__ and __LINE__ information of lines that use the heap. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Random thoughts on the future interface of PCB
On Fri, Dec 3, 2010 at 10:30 AM, Peter Clifton pc...@cam.ac.uk wrote: As I see it, PCB priorities (for me at least) are approximately: Release? Merge 2D parts of PCB+GL drawing Release? Merge 3D parts of PCB+GL drawing GUI to control PCB+GL rendering styles Release? Before that first release on your list I'd love to see the health of the code improved. This week I've finished my latest board (25 sq. inches, 2 layer lots of complex polygon based partial power planes). The biggest problems I had were: * Lots of segfaults. Usual triggers: 1. Find on a complex net 2. Manipulation of complex polygons, including use of MorphPolygon() * Strange GTK HID UI bug - when drawing new traces the helpful outline that appears whilst moving the mouse disappears. This leaves you in the dark, guessing where the trace will appear in 45\_ or 45_/ mode is hard. Only comes up after a few minutes of editing a complex board. Work-around is to restart PCB (painful as I lose window layout, layer visibility and command history). * lots of memory leaks - wasn't actually a problem with 4GB RAM, but I could see the address space steadily disappearing during long runs of my high effort autorouter hack. Memory leaks generally aren't show stoppers, but I'd feel a lot more comfortable about starting to code new features if the existing code was first clean and stable. FWIW a quick run of dmalloc showed the following specific leaks, plus plenty of anonymous ones. hid/common/actions.c:269' hid/common/actions.c:46' hid/common/flags.c:41' hid/common/flags.c:71' hid/common/hidinit.c:171' hid/common/hidinit.c:250' hid/common/hidinit.c:659' hid/common/hidinit.c:688' hid/gtk/gtkhid-gdk.c:352' hid/gtk/gui-log-window.c:150' hid/gtk/gui-top-window.c:266' hid/gtk/gui-top-window.c:2997' hid/gtk/gui-top-window.c:3005' hid/gtk/gui-top-window.c:3034' hid/gtk/gui-top-window.c:3042' hid/gtk/gui-top-window.c:3306' hid/gtk/gui-top-window.c:3695' main.c:780' main.c:790' main.c:800' main.c:810' main.c:820' misc.c:1704' mymem.c:663' mymem.c:707' parse_l.c:2232' res_lex.c:1857' rtree.c:453' rtree.c:455' rtree.c:762' rtree.c:835' rtree.c:992' strflags.c:169' strflags.c:169' strflags.c:171' ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: New autorouter high effort mode
On Fri, Nov 26, 2010 at 6:10 PM, Hannu Vuolasaho vuo...@msn.com wrote: And yes, I'll make a change before my next commit so that optimisation for minimum vias is also possible. Beatiful. I so see how one takes all the PCB files, exports jpg and makes them video. Very hot stuff in product presentations for management what has been done before the prototype is given to hand. BTW Did autorouter its job finally and got all nets traced? Yes :) http://commons.wikimedia.org/wiki/File:HighEffortDemo3.ogv I've also pushed a new commit to git that adds the option to optimise for fewest vias instead of shortest tracks. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
