Re: gEDA-user: Color silk layers in pcb
On 9/6/10, Peter Clifton pc...@cam.ac.uk wrote:
...
confusing non-copper with skip-drc is
probably a bad idea.
...
Thank you, your suggestion is really reasonable.
I renamed the attribute to PCB::non-copper
and corrected the variable name and comments accordingly;
probably it does not make the patch perfect,
but I have no better idea at the moment.
Regards,
Ineiev
From 5ec7e281f01fa09b041537e4f4eb8237cda1cc9c Mon Sep 17 00:00:00 2001
From: Ineiev ine...@users.berlios.de
Date: Tue, 7 Sep 2010 10:30:44 +0400
Subject: [PATCH] recognize PCB::non-copper layer attribute
layers with `PCB::non-copper' attribute are excluded
from DRC (both copper- and silkscreen-specific) and connection lookup
---
src/action.c |2 +-
src/action.h |2 ++
src/find.c | 23 +--
src/global.h |2 ++
4 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/src/action.c b/src/action.c
index 32e294c..2936080 100644
--- a/src/action.c
+++ b/src/action.c
@@ -6957,7 +6957,7 @@ find_element_by_refdes (char *refdes)
return NULL;
}
-static AttributeType *
+AttributeType *
lookup_attr (AttributeListTypePtr list, const char *name)
{
int i;
diff --git a/src/action.h b/src/action.h
index ee116e8..7b64e05 100644
--- a/src/action.h
+++ b/src/action.h
@@ -46,4 +46,6 @@ void warpNoWhere (void);
/* In gui-misc.c */
bool ActionGetLocation (char *);
void ActionGetXY (char *);
+AttributeType * lookup_attr (AttributeListTypePtr list, const char *name);
+
#endif
diff --git a/src/find.c b/src/find.c
index 593be70..17f042f 100644
--- a/src/find.c
+++ b/src/find.c
@@ -81,6 +81,7 @@
#include global.h
+#include action.h
#include crosshair.h
#include data.h
#include draw.h
@@ -826,6 +827,8 @@ LookupLOConnectionsToPVList (bool AndRats)
/* now all lines, arcs and polygons of the several layers */
for (layer = 0; layer max_layer; layer++)
{
+ if (LAYER_PTR (layer)-non_copper)
+ continue;
info.layer = layer;
/* add touching lines */
if (setjmp (info.env) == 0)
@@ -1173,6 +1176,8 @@ LookupPVConnectionsToLOList (bool AndRats)
/* loop over all layers */
for (layer = 0; layer max_layer; layer++)
{
+ if (LAYER_PTR (layer)-non_copper)
+ continue;
/* do nothing if there are no PV's */
if (TotalP + TotalV == 0)
{
@@ -2900,6 +2905,18 @@ ListsEmpty (bool AndRats)
return (empty);
}
+static void
+reassign_non_copper_flags (void)
+{
+ int layer;
+
+ for (layer = 0; layer max_layer; layer++)
+{
+ LayerTypePtr l = LAYER_PTR (layer);
+ l-non_copper = lookup_attr ((l-Attributes), PCB::non-copper) != NULL;
+}
+}
+
/* ---
* loops till no more connections are found
*/
@@ -2907,6 +2924,7 @@ static bool
DoIt (bool AndRats, bool AndDraw)
{
bool new = false;
+ reassign_non_copper_flags ();
do
{
/* lookup connections; these are the steps (2) to (4)
@@ -3349,6 +3367,7 @@ LookupConnection (LocationType X, LocationType Y, bool AndDraw,
/* check if there are any pins or pads at that position */
+ reassign_non_copper_flags ();
type
= SearchObjectByLocation (LOOKUP_FIRST, ptr1, ptr2, ptr3, X, Y, Range);
@@ -3365,8 +3384,8 @@ LookupConnection (LocationType X, LocationType Y, bool AndDraw,
int laynum = GetLayerNumber (PCB-Data,
(LayerTypePtr) ptr1);
- /* don't mess with silk objects! */
- if (laynum = max_layer)
+ /* don't mess with silk and other non-conducting objects! */
+ if (laynum = max_layer || ((LayerTypePtr)ptr1)-non_copper)
return;
}
}
diff --git a/src/global.h b/src/global.h
index bb78abc..bb82b79 100644
--- a/src/global.h
+++ b/src/global.h
@@ -301,6 +301,8 @@ typedef struct /* holds information about one layer */
char *Color, /* color */
*SelectedColor;
AttributeListType Attributes;
+ int non_copper; /* whether to ignore the layer when looking up connections
+ and checking against copper-specific design rules */
}
LayerType, *LayerTypePtr;
--
1.6.0.4
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Re: gEDA-user: Color silk layers in pcb
On Tue, 2010-09-07 at 06:56 +, Ineiev wrote: On 9/6/10, Peter Clifton pc...@cam.ac.uk wrote: ... confusing non-copper with skip-drc is probably a bad idea. ... Thank you, your suggestion is really reasonable. I renamed the attribute to PCB::non-copper and corrected the variable name and comments accordingly; probably it does not make the patch perfect, but I have no better idea at the moment. DJ, Dan, ... Shall we / I push this? I think it looks good overall. I might have put the attribute string PCB::non-copper in a #define somewhere, but if the string is canonical, I guess it doesn't hurt to place it explicitly in the code. I'm slightly weary of the lack of immediate synchronisation between the attribute being present and the (LayerType*)-non_copper flag, but I can live with it ;) This means that the -non_copper flag is only known to be valid after a call to reassign_non_copper_flags(), which is a static function only available inside find.c. This effectively means the flag is ONLY useful inside find.c at the moment. I've was (a while back) working on a hook based attribute change notification system for gschem, and perhaps in future, similar might be applied to map attribute changes to other data-structure flags immediately. OR.. we could eventually optimise the attribute lookup code to be really fast, so as to avoid the need to keep a separate flag in the layer data-structure. (Assuming lookup_attrib is too slow to use at the moment??) For a future patch: It would be nice to move some the attribute lookup helper function out of action.c, if attributes are to form a bigger role in PCB's future, perhaps more functions will be created, and can live away from the already bloated (and seemingly unrelated) action.c -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Color silk layers in pcb
I might have put the attribute string PCB::non-copper in a #define somewhere, but if the string is canonical, I guess it doesn't hurt to place it explicitly in the code. Perhaps we should tell DRC about all sorts of attributes? Then we can do layer-specific ones. I'd want to use DRC::* at that point though. And we'd need a GUI to edit them nicely. Migration to/from the old DRC() format needs to be considered. Maybe it's time for me to find time to put in the layer types change, which would cover this need anyway (copper vs non-copper at least). After Oct 16th though, no sooner. OR.. we could eventually optimise the attribute lookup code to be really fast, so as to avoid the need to keep a separate flag in the layer data-structure. (Assuming lookup_attrib is too slow to use at the moment??) Lookups are slow but we can cache both the lookup and the conversion if we need to. A hash of structs with multiple types (string, int, float) for each attribute would do. It would be nice to move some the attribute lookup helper function out of action.c, if attributes are to form a bigger role in PCB's future, perhaps more functions will be created, and can live away from the already bloated (and seemingly unrelated) action.c Core attribute lookups are in misc.c But yeah, the code's getting messy. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Color silk layers in pcb
On Sun, 05 Sep 2010 22:19:08 +0100 Peter Clifton pc...@cam.ac.uk wrote: I'd keep the non-copper / skip-drc ideas separate. We might (at some point) have DRC rules for non-copper layers (not that I can think of them at the moment, perhaps apart from silk layer(s)). Component outline vs. keep-in component layer, etc. However at this point where we are now, this patch would be great help. Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Color silk layers in pcb
Peter Clifton wrote: Why don't we just push this patch to HEAD? This works just great. One minor nit.. That is, the patch is rejected because of this minor nit? ---)kaimartin(--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Color silk layers in pcb
On Mon, 2010-09-06 at 09:30 +0200, Kovacs Levente wrote: On Sun, 05 Sep 2010 22:19:08 +0100 Peter Clifton pc...@cam.ac.uk wrote: I'd keep the non-copper / skip-drc ideas separate. We might (at some point) have DRC rules for non-copper layers (not that I can think of them at the moment, perhaps apart from silk layer(s)). Component outline vs. keep-in component layer, etc. However at this point where we are now, this patch would be great help. My point was that the patch muddles the non-copper / skip-drc concepts, and this should be fixed before the patch is applied. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Color silk layers in pcb
On Mon, 2010-09-06 at 15:32 +0200, Kai-Martin Knaak wrote: Peter Clifton wrote: Why don't we just push this patch to HEAD? This works just great. One minor nit.. That is, the patch is rejected because of this minor nit? I don't accept / reject patches per-se.. I was just making a comment having read the patch. Personally I'd like to see it fixed before it is applied. - I don't object to the patch in principle (baring the comment I made) - I'm not holding the patch to ransom, suggesting _I_ would apply it if certain changes were made. - I'm not currently intending to apply the patch myself (as I've not the time to review its design implications) Bug-fix patches are usually pretty easy to review and apply, but ones which affect the parsing / semantics of the file format (including various new attributes) need to be reviewed carefully, since forward compatibility is very important. I don't want to see PCB gathering a legacy of ill-thought out semantics which might cause difficulties in the future (either code or file-format wise). (Again, I've got nothing against the patch in question). Is attribute based layer control the direction we want to take PCB in? I personally think so - probably at least ;). Are the attribute(s) suitably name-spaced / future proof? (I just don't know). However - as I pointed out.. confusing non-copper with skip-drc is probably a bad idea. From my brief skim of the patch, this seemed like it might have only been done in code comments, so is _really_ easy to rectify. I don't have the time to dig deeper into these questions right now, but they are important before we end up with a legacy of attributes which do magic things inside PCB. (Not that I think the proposed ones are bad). -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Color silk layers in pcb
On Sun, Sep 5, 2010 at 6:42 AM, Ineiev ine...@gmail.com wrote: On 9/4/10, DJ Delorie d...@delorie.com wrote: Ineiev, thanks for the patch, it applied fine. However, I'm unable to find the (Edit-Edit attributes of-Current Layer). Is it placed somewhere else, or can I manually edit the .pcb file for the same result? I'm using pcb source tree from git, version 1.99z. Do you have a local ~/.pcb/gpcb-menu.res or something? Nope, I even removed ~/.pcb to be sure it's not interfering. The .pcb file format is documented in the doc/pcb.pdf generated file, including the Attributes() syntax. Thanks DJ, this proved helpful. In case your gpcb-menu.res lacks this item, you can issue the action through (Window-Command entry), the command is 'Attributes(Layer)'. Hope that helps Ineiev, that's a real life saver! It does exactly what I wanted. Thanks a million. Any chance it will make it's way to production in some place like File-Preferences-Layers? Kind regards, -- Paweł Kuśmierski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Color silk layers in pcb
On Sun, 2010-09-05 at 00:18 +0200, Levente Kovacs wrote: On Sat, 4 Sep 2010 11:24:38 + Ineiev ine...@gmail.com wrote: Probably this patch may be used as a workaround. Why don't we just push this patch to HEAD? This works just great. One minor nit.. I'd keep the non-copper / skip-drc ideas separate. We might (at some point) have DRC rules for non-copper layers (not that I can think of them at the moment, perhaps apart from silk layer(s)). Otherwise, seems good. Best regards, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Color silk layers in pcb
On Sat, 2010-09-04 at 22:56 +0200, Pawel Kusmierski wrote: On Sat, Sep 4, 2010 at 1:11 PM, Peter Clifton pc...@cam.ac.uk wrote: As a kludge, call your layer by one of the magic names outline or route and it will be ignored by the DRC, and treated as non-copper. Peter, thanks for the tip. I may be doing something wrong, but even following the tips at http://www.geda.seul.org/wiki/geda:pcb_tips#how_do_i_make_a_board_outline_to_go_with_my_gerbers_to_the_board_maker the outline layer still connects my vias together. Hmm, so it does.. sorry, it appears the DRC check isn't disabled for the outline layer. What is useful is that the outline / route titled layers don't get pads flashed on them when exporting gerbers. All other (copper) layers get the pads on them, which would be a problem for an outline plot. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Color silk layers in pcb
Peter Clifton wrote: What is useful is that the outline / route titled layers don't get pads flashed on them when exporting gerbers. All other (copper) layers get the pads on them, which would be a problem for an outline plot. Apparently not for my preferred fab. When asked, they told me that pads on the outline are no problem to them. They cut the pcb at places where the gerber asks for copper. For some projects I needed copper at the very edge of the PCB. So I had to ignore the corresponding DRC errors. Conclusion: I'd like to have the outline layer ignored by DRC, too. ---)kaimartin(--- -- Kai-Martin Knaak Öffentlicher PGP-Schlüssel: http://pgp.mit.edu:11371/pks/lookup?op=getsearch=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Color silk layers in pcb
On Sun, Sep 5, 2010 at 2:19 PM, Peter Clifton [1]pc...@cam.ac.uk wrote: On Sun, 2010-09-05 at 00:18 +0200, Levente Kovacs wrote: On Sat, 4 Sep 2010 11:24:38 + Ineiev [2]ine...@gmail.com wrote: Probably this patch may be used as a workaround. Why don't we just push this patch to HEAD? This works just great. One minor nit.. I'd keep the non-copper / skip-drc ideas separate. We might (at some point) have DRC rules for non-copper layers (not that I can think of them at the moment, perhaps apart from silk layer(s)). Otherwise, seems good. Best regards, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list [3]geda-u...@moria.seul.org [4]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user If PCB had the concept of a part/element body outline layer (separate from the silk), it could be used as a guide for part placement, not interfere with pads like the silk would, and could be checked with the DRC. Another vote for general, non-copper layers I guess. Joe T. References 1. mailto:pc...@cam.ac.uk 2. mailto:ine...@gmail.com 3. mailto:geda-user@moria.seul.org 4. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Color silk layers in pcb
On Fri, 2010-09-03 at 11:53 +0200, Pawel Kusmierski wrote: As a kludge, call your layer by one of the magic names outline or route and it will be ignored by the DRC, and treated as non-copper. Regards, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Color silk layers in pcb
On 9/3/10, Stefan Salewski m...@ssalewski.de wrote:
On Fri, 2010-09-03 at 11:53 +0200, Pawel Kusmierski wrote:
Can I get pcb to either treat a layer other than the default silk as
non-metal
(so it would not short pads and mess up nets),
No, currently we have only one silk layer. You may miss-use other
copper layers for that task -- it may work when that layer is not in
your real copper layer groups, but unfortunately it still connects to
vias and can generate shorts.
Probably this patch may be used as a workaround.
Put your non-copper layer into a distinct layer group
(File-Preferences-Layers, Groups Tab), add to the layer an attribute
named PCB::skip-drc (Edit-Edit attributes of-Current Layer),
and PCB should skip the layer during DRC and connections lookup.
Kind regards
From 1bec53aea09312b99ee14c40fe7efcaa80158467 Mon Sep 17 00:00:00 2001
From: Ineiev ine...@users.berlios.de
Date: Sat, 4 Sep 2010 14:12:46 +0400
Subject: [PATCH] recognize PCB::skip-drc layer attribute
layers with `PCB::skip-drc' attribute are excluded
from DRC and connection lookup
---
src/action.c |2 +-
src/action.h |2 ++
src/find.c | 23 +--
src/global.h |1 +
4 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/src/action.c b/src/action.c
index 32e294c..2936080 100644
--- a/src/action.c
+++ b/src/action.c
@@ -6957,7 +6957,7 @@ find_element_by_refdes (char *refdes)
return NULL;
}
-static AttributeType *
+AttributeType *
lookup_attr (AttributeListTypePtr list, const char *name)
{
int i;
diff --git a/src/action.h b/src/action.h
index ee116e8..7b64e05 100644
--- a/src/action.h
+++ b/src/action.h
@@ -46,4 +46,6 @@ void warpNoWhere (void);
/* In gui-misc.c */
bool ActionGetLocation (char *);
void ActionGetXY (char *);
+AttributeType * lookup_attr (AttributeListTypePtr list, const char *name);
+
#endif
diff --git a/src/find.c b/src/find.c
index 593be70..ac94f4b 100644
--- a/src/find.c
+++ b/src/find.c
@@ -81,6 +81,7 @@
#include global.h
+#include action.h
#include crosshair.h
#include data.h
#include draw.h
@@ -826,6 +827,8 @@ LookupLOConnectionsToPVList (bool AndRats)
/* now all lines, arcs and polygons of the several layers */
for (layer = 0; layer max_layer; layer++)
{
+ if (LAYER_PTR (layer)-no_drc)
+ continue;
info.layer = layer;
/* add touching lines */
if (setjmp (info.env) == 0)
@@ -1173,6 +1176,8 @@ LookupPVConnectionsToLOList (bool AndRats)
/* loop over all layers */
for (layer = 0; layer max_layer; layer++)
{
+ if (LAYER_PTR (layer)-no_drc)
+ continue;
/* do nothing if there are no PV's */
if (TotalP + TotalV == 0)
{
@@ -2900,6 +2905,18 @@ ListsEmpty (bool AndRats)
return (empty);
}
+static void
+reassign_no_drc_flags (void)
+{
+ int layer;
+
+ for (layer = 0; layer max_layer; layer++)
+{
+ LayerTypePtr l = LAYER_PTR (layer);
+ l-no_drc = lookup_attr ((l-Attributes), PCB::skip-drc) != NULL;
+}
+}
+
/* ---
* loops till no more connections are found
*/
@@ -2907,6 +2924,7 @@ static bool
DoIt (bool AndRats, bool AndDraw)
{
bool new = false;
+ reassign_no_drc_flags ();
do
{
/* lookup connections; these are the steps (2) to (4)
@@ -3349,6 +3367,7 @@ LookupConnection (LocationType X, LocationType Y, bool AndDraw,
/* check if there are any pins or pads at that position */
+ reassign_no_drc_flags ();
type
= SearchObjectByLocation (LOOKUP_FIRST, ptr1, ptr2, ptr3, X, Y, Range);
@@ -3365,8 +3384,8 @@ LookupConnection (LocationType X, LocationType Y, bool AndDraw,
int laynum = GetLayerNumber (PCB-Data,
(LayerTypePtr) ptr1);
- /* don't mess with silk objects! */
- if (laynum = max_layer)
+ /* don't mess with non-conducting objects! */
+ if (laynum = max_layer || ((LayerTypePtr)ptr1)-no_drc)
return;
}
}
diff --git a/src/global.h b/src/global.h
index bb78abc..1c7ca26 100644
--- a/src/global.h
+++ b/src/global.h
@@ -301,6 +301,7 @@ typedef struct /* holds information about one layer */
char *Color, /* color */
*SelectedColor;
AttributeListType Attributes;
+ int no_drc; /* whether to ignore the layer when checking the design rules */
}
LayerType, *LayerTypePtr;
--
1.6.0.2
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Re: gEDA-user: Color silk layers in pcb
On Sat, Sep 4, 2010 at 1:11 PM, Peter Clifton pc...@cam.ac.uk wrote: As a kludge, call your layer by one of the magic names outline or route and it will be ignored by the DRC, and treated as non-copper. Peter, thanks for the tip. I may be doing something wrong, but even following the tips at http://www.geda.seul.org/wiki/geda:pcb_tips#how_do_i_make_a_board_outline_to_go_with_my_gerbers_to_the_board_maker the outline layer still connects my vias together. Kind regards, -- Pawel Kusmierski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Color silk layers in pcb
On Sat, Sep 4, 2010 at 1:24 PM, Ineiev ine...@gmail.com wrote: Probably this patch may be used as a workaround. Put your non-copper layer into a distinct layer group (File-Preferences-Layers, Groups Tab), add to the layer an attribute named PCB::skip-drc (Edit-Edit attributes of-Current Layer), and PCB should skip the layer during DRC and connections lookup. Ineiev, thanks for the patch, it applied fine. However, I'm unable to find the (Edit-Edit attributes of-Current Layer). Is it placed somewhere else, or can I manually edit the .pcb file for the same result? I'm using pcb source tree from git, version 1.99z. I haven't found anything on editing layer attributes around google. Is there any place (apart from the source code) with some info on other possible values? Kind regards, -- Pawel Kusmierski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Color silk layers in pcb
On Sat, 4 Sep 2010 11:24:38 + Ineiev ine...@gmail.com wrote: Probably this patch may be used as a workaround. Why don't we just push this patch to HEAD? This works just great. Thanks, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Color silk layers in pcb
Ineiev, thanks for the patch, it applied fine. However, I'm unable to find the (Edit-Edit attributes of-Current Layer). Is it placed somewhere else, or can I manually edit the .pcb file for the same result? I'm using pcb source tree from git, version 1.99z. Do you have a local ~/.pcb/gpcb-menu.res or something? The .pcb file format is documented in the doc/pcb.pdf generated file, including the Attributes() syntax. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Color silk layers in pcb
On 9/4/10, DJ Delorie d...@delorie.com wrote: Ineiev, thanks for the patch, it applied fine. However, I'm unable to find the (Edit-Edit attributes of-Current Layer). Is it placed somewhere else, or can I manually edit the .pcb file for the same result? I'm using pcb source tree from git, version 1.99z. Do you have a local ~/.pcb/gpcb-menu.res or something? The .pcb file format is documented in the doc/pcb.pdf generated file, including the Attributes() syntax. In case your gpcb-menu.res lacks this item, you can issue the action through (Window-Command entry), the command is 'Attributes(Layer)'. Hope that helps ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Color silk layers in pcb
On Fri, 2010-09-03 at 11:53 +0200, Pawel Kusmierski wrote: Dear fellow GEDA-users, Can I get pcb to either treat a layer other than the default silk as non-metal (so it would not short pads and mess up nets), Please note, your SUBJECT may be misleading... No, currently we have only one silk layer. You may miss-use other copper layers for that task -- it may work when that layer is not in your real copper layer groups, but unfortunately it still connects to vias and can generate shorts. I did that for visual marks, distinct from other silk marks, and I copy that layer to silk before gerber production. (Some of us hope that sometimes we will have general propose layers, so that we can select type and other parameters separate...) Best regards Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Color silk layers in pcb
On Fri, Sep 3, 2010 at 1:51 PM, Stefan Salewski m...@ssalewski.de wrote: On Fri, 2010-09-03 at 11:53 +0200, Pawel Kusmierski wrote: Dear fellow GEDA-users, Can I get pcb to either treat a layer other than the default silk as non-metal (so it would not short pads and mess up nets), Please note, your SUBJECT may be misleading... No, currently we have only one silk layer. You may miss-use other copper layers for that task -- it may work when that layer is not in your real copper layer groups, but unfortunately it still connects to vias and can generate shorts. I did that for visual marks, distinct from other silk marks, and I copy that layer to silk before gerber production. (Some of us hope that sometimes we will have general propose layers, so that we can select type and other parameters separate...) Thanks for your answer Stefan. I have my visual marks just over vias, and it shorts them together, so I will look for some other solution. Is anybody willing to elaborate on how difficult would it be to modify the pcb source code to color-differentiate three or four silk layers and be able to selectively hide/show them? Kind regards, -- Pawel Kusmierski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Color silk layers in pcb
I can't answer your question, but I have one of my own. I use FreePCB and have requested, along with others, that we be able to designate layers as documentation such as assembly info, mechanical details, etc. Is that what you are looking for or do you want these layers to be usable to produce the silk screen Gerber files? I suppose once the layers are created, it would not be any extra effort to allow them to be used in the Gerber file. Does PCB have the ability to combine multiple layers into a single Gerber file? Rick At 12:40 PM 9/3/2010, you wrote: On Fri, Sep 3, 2010 at 1:51 PM, Stefan Salewski m...@ssalewski.de wrote: On Fri, 2010-09-03 at 11:53 +0200, Pawel Kusmierski wrote: Dear fellow GEDA-users, Can I get pcb to either treat a layer other than the default silk as non-metal (so it would not short pads and mess up nets), Please note, your SUBJECT may be misleading... No, currently we have only one silk layer. You may miss-use other copper layers for that task -- it may work when that layer is not in your real copper layer groups, but unfortunately it still connects to vias and can generate shorts. I did that for visual marks, distinct from other silk marks, and I copy that layer to silk before gerber production. (Some of us hope that sometimes we will have general propose layers, so that we can select type and other parameters separate...) Thanks for your answer Stefan. I have my visual marks just over vias, and it shorts them together, so I will look for some other solution. Is anybody willing to elaborate on how difficult would it be to modify the pcb source code to color-differentiate three or four silk layers and be able to selectively hide/show them? Kind regards, -- Pawel Kusmierski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Color silk layers in pcb
On Fri, Sep 3, 2010 at 6:49 PM, Rick Collins gnuarm.2...@arius.com wrote: I can't answer your question, but I have one of my own. I use FreePCB and have requested, along with others, that we be able to designate layers as documentation such as assembly info, mechanical details, etc. Is that what you are looking for or do you want these layers to be usable to produce the silk screen Gerber files? I suppose once the layers are created, it would not be any extra effort to allow them to be used in the Gerber file. Does PCB have the ability to combine multiple layers into a single Gerber file? That would do the trick. I just want to have more than two silk layers and be able to tell them apart by color. That would make it just so much easier to design a pcb that would fit into a case, and know where to cut holes in it at the same time. By the way, is FreePCB related to gEDA pcb in any way? Kind regards, -- Pawel Kusmierski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Color silk layers in pcb
No, FreePCB is a separate project with no links in any way. I have used it for a couple of projects and like it pretty well, but it is hard to get changes made. The developer was on a hiatus for some time, but is back now. He has a long list of bug fixes and suggestions people would like to see implemented. He also has some philosophical difference with me. I would consider creating my own branch of the project, but I don't own the tools to build it with and no one has done that yet, so I don't know how well it would be received. I don't want to muddy the waters with different versions, even if they are just small UI changes, unless we can find a way to make it part of the main branch with perhaps build options or something. In the meantime I am working on the wiki as my small contribution. Too bad it is down... :^( I may also help with some peripheral tools such as a BOM/xyrs file manager. The one someone else contributed does not fully utilize the info potentially available from the schematic. I know pretty much nothing about PCB so I can't even give you a basic comparison of the two. I am here to try to learn what this is about and where it is going. Maybe I'll want to get on board at some point. Rick At 05:40 PM 9/3/2010, you wrote: On Fri, Sep 3, 2010 at 6:49 PM, Rick Collins gnuarm.2...@arius.com wrote: I can't answer your question, but I have one of my own. I use FreePCB and have requested, along with others, that we be able to designate layers as documentation such as assembly info, mechanical details, etc. Is that what you are looking for or do you want these layers to be usable to produce the silk screen Gerber files? I suppose once the layers are created, it would not be any extra effort to allow them to be used in the Gerber file. Does PCB have the ability to combine multiple layers into a single Gerber file? That would do the trick. I just want to have more than two silk layers and be able to tell them apart by color. That would make it just so much easier to design a pcb that would fit into a case, and know where to cut holes in it at the same time. By the way, is FreePCB related to gEDA pcb in any way? Kind regards, -- Pawel Kusmierski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Color silk layers in pcb
On Fri, Sep 03, 2010 at 06:40:05PM +0200, Pawel Kusmierski wrote: Is anybody willing to elaborate on how difficult would it be to modify the pcb source code to color-differentiate three or four silk layers and be able to selectively hide/show them? It will probably be more work than it should be, since there is special logic in place to handle the silk and via layers, and a switch statement in nearly every layer-handling function to deal with it. Andrew ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
