Re: gEDA-user: discussion on what busses *mean*
DJ Delorie wrote: I can't think of a good reason to do this, but I suppose you could connect to a bus pin (aka pin with multiple signals) and name the *bus* while leaving the individual *nets* unnamed, and carry that bus name on to a second schematic page, still without naming the nets, and connect it to another bus pin with the same number of signals, and hope it all works out :-) If a bus-pin (or bus-port?) is required to have an internal representation of the pin connections and the two bus-things ;-) are required to have identical layout it should work - it's like a cable with colored wires. If the bus definition exists independently of the ports (ie. the list of wire colors aka signals, irrespective of any plug type), one has the freedom to pick any subset of the signals and define a port for it on a part. I hope this wasn't to trivial to mention. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: discussion on what busses *mean*
DJ Delorie wrote: I published my paper mostly to get a discussion going on what busses *mean* though, not the implementation details. For example, what does it mean when three busses with different names are connected? D[15:0] ==** D[15:0] || \\ A[1:16] With nets, it breaks if you do that. I would want DRC to complain to - it's a real error to give one signal two names. Do we need a separate bus thing in order to apply different rules? I don't think that's needed, but maybe a short version of a bus name would be handy when a big bus of 70 wires is referred to because it has some reason to exist as a group. How I would name the above case to get a decisive result is D[15:0],A[1:16] with a branch called A[1:16] And I want to understand the implications of pins that reflect multiple signals, too - mapping names and numbers, etc. To me, pins can be handled the same as bus names. a pin named D[15:0] can be used to generate all details necessary for netlisting and module hookup. When I say modules, I'm thinking in verilog, where a port corresponds to a pin, and a port can be multiwire. Or, you could define pin as single wire and create a new thing called a port, that has multiwire function. verilog-ams-heads would know what you mean already. -- Ecosensory Austin TX tinyOS devel on: ubuntu Linux; tinyOS v2.0.2; telosb ecosens1 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: discussion on what busses *mean*
DJ Delorie wrote: One of the things we need for pin/gate swapping in pcb is a UUID for each logical symbol in the schematic set. Refdes is not unique enough :-( Yep. Maybe it could be handled without needing to see it all the time? Since UUIDs are long... they could be a generated attribute that does not show unless you are in a debug mode, or looking at the .pcb file format. They may as well be in the gschem view also...else how do you relate them properly or back-and-forth-annotate? +1 John Griessen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: discussion on what busses *mean*
D[15:0],A[1:16] with a branch called A[1:16] I was thinking the above renames the wires but perhaps that's a bad idea. Yeah, I guess it would have to create a bundle of 32 wires. No reason you couldn't attach some random attribute to the bus that's just to give it a mnemonic name :-) When I say modules, I'm thinking in verilog, where a port corresponds to a pin, and a port can be multiwire. Or, you could define pin as single wire and create a new thing called a port, that has multiwire function. I'm worried about pcb, though, where pin == physical pin, so not only do we need to have a bus connect to a symbol, but we have to keep track of the pin numbers somehow, and still allow for pin swapping via back annotation and slotting. Which means *someone* will be constantly breaking apart busses and putting them back together again. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: discussion on what busses *mean*
DJ Delorie wrote: JG wrote: When I say modules, I'm thinking in verilog, where a port corresponds to a pin, and a port can be multiwire. Or, you could define pin as single wire and create a new thing called a port, that has multiwire function. I'm worried about pcb, though, where pin == physical pin, so not only do we need to have a bus connect to a symbol, but we have to keep track of the pin numbers somehow, and still allow for pin swapping via back annotation and slotting. Which means *someone* will be constantly breaking apart busses and putting them back together again. Packages with their fixed pin orders add another constraint beyond netnames for busses. Does a bus as we think of it need to be a row of traces in order with no vias jumping over wires to rearrange? I think giving that another name will help talking about it. To me, a bus is conceptually related, but not necessarily in row order . In other words, D[0:7] need not be arranged as D[0],D[1],D[2] in physical order. Pin swapping is motivated by wanting to have neat marching rows of traces so they take up the least space. You can get that without having to keep wires in physical number order though. Usually they would be in order, but it should not be a constraint. If I had to change 6 places in a schematic to get D[0],D[1],D[2] in physical order, but just two places to get D[0],D[2],D[1] in physical order, I'd let it be out of physical/number order. John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: discussion on what busses *mean*
Right, when we have a signal-pin-symbol relation, we have a bunch of information: * net name * pin number * pin sequence * pin label * physical pin location If I have a bus A[1:3] connected to pin EN[0:2] at pin number 4,8,7 - I mean the same as if I had connected net A1 to pin EN0 at 4, A2 to EN1 at 8, and A3 to EN2 at 7. If in PCB I decide I need to swap EN0 and EN2 to get the routing the way I want, I need to do a pin swap. Normally we'd just change the pin numbers on the symbol (slotting, pin mapping) or reconnect the nets in gschem. But reconnect the nets is difficult if they're not independent (i.e. they're a bus) so you have to do it with pin numbers, but a bus pin doesn't have *a* number, it has a *list* of numbers, so you have to swap within the list. Or between a number in one list, and another number elsewhere, if the swap map allows it. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: discussion on what busses *mean*
DJ Delorie wrote: Right, when we have a signal-pin-symbol relation, we have a bunch of information: * net name * pin number * pin sequence * pin label * physical pin location If I have a bus A[1:3] connected to pin EN[0:2] at pin number 4,8,7 - I mean the same as if I had connected net A1 to pin EN0 at 4, A2 to EN1 at 8, and A3 to EN2 at 7. So, in this example, pin label is EN[0:2], pin number list is (4,8,7), netname is A[1:3]. But reconnect the nets is difficult if they're not independent (i.e. they're a bus) so you have to do it with pin numbers, but a bus pin doesn't have *a* number, it has a *list* of numbers, so you have to swap within the list. bus pin confuses me. Is there another name for what you are thinking? Or between a number in one list, and another number elsewhere, if the swap map allows it. John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: discussion on what busses *mean*
So, in this example, pin label is EN[0:2], pin number list is (4,8,7), netname is A[1:3]. Right. bus pin confuses me. Is there another name for what you are thinking? It's a symbolic pin that means multiple physical pins. It can look the same or look different, doesn't matter to me, but I figured a bus pin would be thicker, and could connect directly to a bus, instead of having to make a net mean both a single signal and a group of signals. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: discussion on what busses *mean*
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Am 15.08.2010 22:25, schrieb DJ Delorie: D[15:0],A[1:16] with a branch called A[1:16] I was thinking the above renames the wires but perhaps that's a bad idea. Yeah, I guess it would have to create a bundle of 32 wires. No reason you couldn't attach some random attribute to the bus that's just to give it a mnemonic name :-) DJ, in general I don't like having 2 names for the same net, Maybe I'm biased with my experience of vhdl synthesis, normally the name that you don't expect survives synthesis and the other one gets lost (and that even may vary between two releases of the same tool). So having only one name has advantages. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user - -- Mit freundlichen Gruessen Dietmar Schmunkamp -BEGIN PGP SIGNATURE- Version: GnuPG v2.0.12 (GNU/Linux) Comment: Using GnuPG with SUSE - http://enigmail.mozdev.org/ iEYEARECAAYFAkxoYpkACgkQn22l+QvEah3cQACfZ/XHL0UmkWJxrS/lwtHPRRm0 c+4AmwfMeef/Gl/GmC4/m3J6WR1BqD+i =5sp3 -END PGP SIGNATURE- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: discussion on what busses *mean*
in general I don't like having 2 names for the same net, Maybe I'm biased with my experience of vhdl synthesis, normally the name that you don't expect survives synthesis and the other one gets lost (and that even may vary between two releases of the same tool). So having only one name has advantages. It's not the same NET. Each NET has a name. A *BUS* is a group of nets, you can refer to the names of the nets inside it or give the bus its own name. For example: Nets A0 to A15, D0 to D7, RD, WR, and EN are grouped into a bus. You can refer to the nets within the bus when you pull them out for a connection: A[0:15],D[0:7],RD,WR,EN - all the nets A[0:1],RD,EN - some of the nets A15,D[0:7],WR,EN - some of the nets but we could also give the *grouping* a name, like CONTROL_BUS. So, for example, you could give a bus a netname to enumerate the nets contained therein (just like we do for single-signal nets), as well as a busname to name the grouping. I can't think of a good reason to do this, but I suppose you could connect to a bus pin (aka pin with multiple signals) and name the *bus* while leaving the individual *nets* unnamed, and carry that bus name on to a second schematic page, still without naming the nets, and connect it to another bus pin with the same number of signals, and hope it all works out :-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: discussion on what busses *mean*
DJ Delorie wrote: bus pin confuses me. Is there another name for what you are thinking? It's a symbolic pin that means multiple physical pins. It can look the same or look different, doesn't matter to me, but I figured a bus pin would be thicker, and could connect directly to a bus, instead of having to make a net mean both a single signal and a group of signals. Thanks. The chip design tools don't worry with making busses look any different unless added by the user just for looks. For them, the different label does it all. But they done' have that additional constraint of a package. I guess bus pin is workable terminology. Bus port for a name might cause less head aching. Dietmar Schmunkamp wrote: No reason you couldn't attach some random attribute to the bus that's just to give it a mnemonic name :-) DJ, in general I don't like having 2 names for the same net, Maybe I'm biased with my experience of vhdl synthesis, normally the name that you don't expect survives synthesis and the other one gets lost (and that even may vary between two releases of the same tool). So having only one name has advantages. Same in chip design. Names get really long. No one complains because verification is the ultimate in chips. 2nd trips through the fab to get working silicon are deadly to company financial health. John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: discussion on what busses *mean*
Thanks. The chip design tools don't worry with making busses look any different unless added by the user just for looks. For them, the different label does it all. But they done' have that additional constraint of a package. Right, with verilog signal is more abstract - one signal can be a single wire, another signal can be a 48-bit numeric value. In pcb layout, we have to stick with what the laws of physics allow, which means multi-physical-connection things have to be explicit and distinct. I guess bus pin is workable terminology. Bus port for a name might cause less head aching. I called it bus pin meaning a pin that connects to a bus, vs a pin that connects to a net, in gschem. I mean, we already have two fundamental connection types in gschem - nets and busses. Why don't we have two pin types that correspond? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: discussion on what busses *mean*
DJ Delorie wrote: You can refer to the nets within the bus when you pull them out for a connection: A[0:15],D[0:7],RD,WR,EN - all the nets A[0:1],RD,EN - some of the nets A15,D[0:7],WR,EN - some of the nets but we could also give the *grouping* a name, like CONTROL_BUS. That's what Dietmar is warning against... one way refers to A[0:15],D[0:7],RD,WR,EN as CONTROL_BUS and then it gets confused later as just meaning A[0:1],RD,EN. But if we kept it from being used for connections and just as a shorthand for schematics readability, I'm all for that. When you get big busses and big FPGA chips and more than a few hundred pins or pads, I think schematics break down in usability anyway and verilog netlists are the thing to do. -- John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: discussion on what busses *mean*
On Aug 15, 2010, at 4:15 PM, DJ Delorie wrote: I called it bus pin meaning a pin that connects to a bus, vs a pin that connects to a net, in gschem. I mean, we already have two fundamental connection types in gschem - nets and busses. Why don't we have two pin types that correspond? But in Paul's approach, every connection is a bus. There's no separate net concept, just the possibility of single conductor* busses. Eliminating unnecessary distinctions is a good thing. So there is no need for two kinds of pins, either. But at the graphical level, of course, one would like to draw distinctions (often more than two). So it would be good to have adjustable styles (at least color and width) for both busses and pins. * Conductor is of course too specific here, given that we have users that design hydraulics with gschem. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: discussion on what busses *mean*
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Am 16.08.2010 00:07, schrieb DJ Delorie: in general I don't like having 2 names for the same net, Maybe I'm biased with my experience of vhdl synthesis, normally the name that you don't expect survives synthesis and the other one gets lost (and that even may vary between two releases of the same tool). So having only one name has advantages. It's not the same NET. Each NET has a name. A *BUS* is a group of nets, you can refer to the names of the nets inside it or give the bus its own name. For example: Nets A0 to A15, D0 to D7, RD, WR, and EN are grouped into a bus. You can refer to the nets within the bus when you pull them out for a connection: A[0:15],D[0:7],RD,WR,EN - all the nets A[0:1],RD,EN - some of the nets A15,D[0:7],WR,EN - some of the nets but we could also give the *grouping* a name, like CONTROL_BUS. So, for example, you could give a bus a netname to enumerate the nets contained therein (just like we do for single-signal nets), as well as a busname to name the grouping. DJ, I agree, and I don't have a problem with it as long that name is used consistently thruout the entire design, so your CONTROL_BUS on the first sheet is the same from there on to the last sheet. As soon as you only want to use a subset you have use the individual net names (at least in my opinion). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user - -- Mit freundlichen Gruessen Dietmar Schmunkamp -BEGIN PGP SIGNATURE- Version: GnuPG v2.0.12 (GNU/Linux) Comment: Using GnuPG with SUSE - http://enigmail.mozdev.org/ iEYEARECAAYFAkxocQkACgkQn22l+QvEah22YwCfS7BMY2/WWH5Th9Hx+3PhYyTo ebYAn091KtEaeVvWYNdOEVLcQQ/+HTs9 =fvtL -END PGP SIGNATURE- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: discussion on what busses *mean*
But in Paul's approach, every connection is a bus. To use your own words: But synthesis is not the only geda flow! With physical electronics, individual electrical connections are fundamental, and groupings are synthetic. They're totally distinct concepts, unlike in synthesis. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: discussion on what busses *mean*
I completely disagree. Yes, I expected you to. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
