[gem5-dev] changeset in gem5: cpu: Remove all notion that we know when the ...
changeset 61a0b02aa800 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=61a0b02aa800
description:
cpu: Remove all notion that we know when the cpu is misspeculating.
We have no way of knowing if a CPU model is on the wrong path with
our execute-in-execute CPU models. Don't pretend that we do.
diffstat:
src/arch/alpha/ev5.cc | 12 +++-
src/arch/alpha/faults.cc | 11 ---
src/cpu/SConscript| 3 +--
src/cpu/checker/thread_context.hh | 3 ---
src/cpu/exetrace.cc | 3 ---
src/cpu/exetrace.hh | 11 +++
src/cpu/inorder/inorder_trace.hh | 4 ++--
src/cpu/inorder/thread_context.hh | 8
src/cpu/inteltrace.hh | 11 +++
src/cpu/nativetrace.hh| 10 +++---
src/cpu/o3/thread_context.hh | 8
src/cpu/simple/base.hh| 1 -
src/cpu/simple_thread.hh | 9 -
src/cpu/thread_context.hh | 6 --
src/sim/faults.cc | 1 -
src/sim/insttracer.hh | 6 ++
16 files changed, 21 insertions(+), 86 deletions(-)
diffs (truncated from 362 to 300 lines):
diff -r fae54a666162 -r 61a0b02aa800 src/arch/alpha/ev5.cc
--- a/src/arch/alpha/ev5.cc Sun Jan 25 07:22:17 2015 -0500
+++ b/src/arch/alpha/ev5.cc Sun Jan 25 07:22:26 2015 -0500
@@ -161,8 +161,7 @@
case IPR_DTB_PTE:
{
-TlbEntry entry
-= tc-getDTBPtr()-index(!tc-misspeculating());
+TlbEntry entry = tc-getDTBPtr()-index(1);
retval |= ((uint64_t)entry.ppn ULL(0x7ff)) 32;
retval |= ((uint64_t)entry.xre ULL(0xf)) 8;
@@ -202,9 +201,6 @@
void
ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
{
-if (tc-misspeculating())
-return;
-
switch (idx) {
case IPR_PALtemp0:
case IPR_PALtemp1:
@@ -484,10 +480,8 @@
CPA::cpa()-swAutoBegin(tc, pc.npc());
-if (!misspeculating()) {
-if (kernelStats)
-kernelStats-hwrei();
-}
+if (kernelStats)
+kernelStats-hwrei();
// FIXME: XXX check for interrupts? XXX
return NoFault;
diff -r fae54a666162 -r 61a0b02aa800 src/arch/alpha/faults.cc
--- a/src/arch/alpha/faults.cc Sun Jan 25 07:22:17 2015 -0500
+++ b/src/arch/alpha/faults.cc Sun Jan 25 07:22:26 2015 -0500
@@ -147,8 +147,7 @@
// on VPTE loads (instead of locking the registers until IPR_VA is
// read, like the EV5). The EV6 approach is cleaner and seems to
// work with EV5 PAL code, but not the other way around.
-if (!tc-misspeculating()
-reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
+if (reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
// set VA register with faulting address
tc-setMiscRegNoEffect(IPR_VA, vaddr);
@@ -172,11 +171,9 @@
ItbFault::invoke(ThreadContext *tc, const StaticInstPtr inst)
{
if (FullSystem) {
-if (!tc-misspeculating()) {
-tc-setMiscRegNoEffect(IPR_ITB_TAG, pc);
-tc-setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
-tc-readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() 3));
-}
+tc-setMiscRegNoEffect(IPR_ITB_TAG, pc);
+tc-setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
+tc-readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() 3));
}
AlphaFault::invoke(tc);
diff -r fae54a666162 -r 61a0b02aa800 src/cpu/SConscript
--- a/src/cpu/SConscriptSun Jan 25 07:22:17 2015 -0500
+++ b/src/cpu/SConscriptSun Jan 25 07:22:26 2015 -0500
@@ -81,7 +81,6 @@
DebugFlag('ExecOpClass', 'Format: Include operand class')
DebugFlag('ExecRegDelta')
DebugFlag('ExecResult', 'Format: Include results from execution')
-DebugFlag('ExecSpeculative', 'Format: Include a miss-/speculation flag (-/+)')
DebugFlag('ExecSymbol', 'Format: Try to include symbol names')
DebugFlag('ExecThread', 'Format: Include thread ID in trace')
DebugFlag('ExecTicks', 'Format: Include tick count')
@@ -100,7 +99,7 @@
CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
-'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread',
+'ExecResult', 'ExecSymbol', 'ExecThread',
'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
'ExecAsid', 'ExecFlags' ])
CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
diff -r fae54a666162 -r 61a0b02aa800 src/cpu/checker/thread_context.hh
--- a/src/cpu/checker/thread_context.hh Sun Jan 25 07:22:17 2015 -0500
+++ b/src/cpu/checker/thread_context.hh Sun Jan 25 07:22:26 2015 -0500
@@ -310,9 +310,6 @@
actualTC-setStCondFailures(sc_failures);
}
-// @todo: Fix this!
-bool misspeculating() { return actualTC-misspeculating(); }
-
Counter readFuncExeInst() { return
[gem5-dev] changeset in gem5: arm: always set the IsFirstMicroop flag
changeset 3c42be107634 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3c42be107634
description:
arm: always set the IsFirstMicroop flag
While the IsFirstMicroop flag exists it was only occasionally used in
the ARM
instructions that gem5 microOps and therefore couldn't be relied on to
be correct.
diffstat:
src/arch/arm/insts/macromem.cc | 11 +++
src/arch/arm/isa/templates/mem.isa | 17 -
src/arch/arm/isa/templates/mem64.isa | 5 -
src/cpu/static_inst.hh | 1 +
4 files changed, 32 insertions(+), 2 deletions(-)
diffs (268 lines):
diff -r aef704eaedd2 -r 3c42be107634 src/arch/arm/insts/macromem.cc
--- a/src/arch/arm/insts/macromem.ccSun Jan 25 07:22:44 2015 -0500
+++ b/src/arch/arm/insts/macromem.ccSun Jan 25 07:22:56 2015 -0500
@@ -220,6 +220,7 @@
--uop;
(*uop)-setLastMicroop();
+microOps[0]-setFirstMicroop();
/* Take the control flags from the last microop for the macroop */
if ((*uop)-isControl())
@@ -335,6 +336,7 @@
assert(uop == microOps[numMicroops]);
(*--uop)-setLastMicroop();
+microOps[0]-setFirstMicroop();
for (StaticInstPtr *curUop = microOps;
!(*curUop)-isLastMicroop(); curUop++) {
@@ -360,6 +362,7 @@
*++uop = new MicroStrQTFpXImmUop(machInst, dest, base, imm);
}
(*uop)-setLastMicroop();
+microOps[0]-setFirstMicroop();
}
BigFpMemPostOp::BigFpMemPostOp(const char *mnem, ExtMachInst machInst,
@@ -380,6 +383,7 @@
}
*uop = new MicroAddXiUop(machInst, base, base, imm);
(*uop)-setLastMicroop();
+microOps[0]-setFirstMicroop();
for (StaticInstPtr *curUop = microOps;
!(*curUop)-isLastMicroop(); curUop++) {
@@ -405,6 +409,7 @@
}
*uop = new MicroAddXiUop(machInst, base, base, imm);
(*uop)-setLastMicroop();
+microOps[0]-setFirstMicroop();
for (StaticInstPtr *curUop = microOps;
!(*curUop)-isLastMicroop(); curUop++) {
@@ -435,6 +440,7 @@
}
(*uop)-setLastMicroop();
+microOps[0]-setFirstMicroop();
}
BigFpMemLitOp::BigFpMemLitOp(const char *mnem, ExtMachInst machInst,
@@ -447,6 +453,7 @@
microOps[0] = new MicroLdFp16LitUop(machInst, dest, imm);
microOps[0]-setLastMicroop();
+microOps[0]-setFirstMicroop();
}
VldMultOp::VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
@@ -540,6 +547,7 @@
assert(uopPtr);
uopPtr-setDelayedCommit();
}
+microOps[0]-setFirstMicroop();
microOps[numMicroops - 1]-setLastMicroop();
}
@@ -807,6 +815,7 @@
assert(uopPtr);
uopPtr-setDelayedCommit();
}
+microOps[0]-setFirstMicroop();
microOps[numMicroops - 1]-setLastMicroop();
}
@@ -901,6 +910,7 @@
assert(uopPtr);
uopPtr-setDelayedCommit();
}
+microOps[0]-setFirstMicroop();
microOps[numMicroops - 1]-setLastMicroop();
}
@@ -1103,6 +1113,7 @@
assert(uopPtr);
uopPtr-setDelayedCommit();
}
+microOps[0]-setFirstMicroop();
microOps[numMicroops - 1]-setLastMicroop();
}
diff -r aef704eaedd2 -r 3c42be107634 src/arch/arm/isa/templates/mem.isa
--- a/src/arch/arm/isa/templates/mem.isaSun Jan 25 07:22:44 2015 -0500
+++ b/src/arch/arm/isa/templates/mem.isaSun Jan 25 07:22:56 2015 -0500
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2010, 2012 ARM Limited
+// Copyright (c) 2010, 2012, 2014 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -883,6 +883,7 @@
#if %(use_pc)d
uops[++uopIdx] = new %(pc_decl)s;
#endif
+uops[0]-setFirstMicroop();
uops[uopIdx]-setLastMicroop();
#endif
}
@@ -905,6 +906,7 @@
uops = new StaticInstPtr[numMicroops];
uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb);
uops[0]-setDelayedCommit();
+uops[0]-setFirstMicroop();
uops[1] = new %(wb_decl)s;
uops[1]-setLastMicroop();
#endif
@@ -944,6 +946,7 @@
assert(numMicroops = 2);
uops = new StaticInstPtr[numMicroops];
uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm);
+uops[0]-setFirstMicroop();
uops[0]-setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]-setLastMicroop();
@@ -972,6 +975,7 @@
uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2,
_base, _add, _imm);
uops[0]-setDelayedCommit();
+uops[0]-setFirstMicroop();
uops[1] = new %(wb_decl)s;
uops[1]-setLastMicroop();
#endif
@@ -995,6 +999,7 @@
uops = new StaticInstPtr[numMicroops];
uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
uops[0]-setDelayedCommit();
+uops[0]-setFirstMicroop();
uops[1] = new %(wb_decl)s;
uops[1]-setLastMicroop();
[gem5-dev] changeset in gem5: sim: Clean up InstRecord
changeset aef704eaedd2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=aef704eaedd2
description:
sim: Clean up InstRecord
Track memory size and flags as well as add some comments and consts.
diffstat:
src/cpu/base_dyn_inst.hh| 10 +-
src/cpu/exetrace.cc |2 +-
src/cpu/inorder/resources/cache_unit.cc |7 +-
src/cpu/minor/lsq.cc|2 +-
src/cpu/simple/atomic.cc| 10 +-
src/cpu/simple/timing.cc| 10 +-
src/sim/insttracer.hh | 117 +++
7 files changed, 104 insertions(+), 54 deletions(-)
diffs (truncated from 302 to 300 lines):
diff -r 61a0b02aa800 -r aef704eaedd2 src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh Sun Jan 25 07:22:26 2015 -0500
+++ b/src/cpu/base_dyn_inst.hh Sun Jan 25 07:22:44 2015 -0500
@@ -917,9 +917,8 @@
}
}
-if (traceData) {
-traceData-setAddr(addr);
-}
+if (traceData)
+traceData-setMem(addr, size, flags);
return fault;
}
@@ -929,9 +928,8 @@
BaseDynInstImpl::writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res)
{
-if (traceData) {
-traceData-setAddr(addr);
-}
+if (traceData)
+traceData-setMem(addr, size, flags);
instFlags[ReqMade] = true;
Request *req = NULL;
diff -r 61a0b02aa800 -r aef704eaedd2 src/cpu/exetrace.cc
--- a/src/cpu/exetrace.cc Sun Jan 25 07:22:26 2015 -0500
+++ b/src/cpu/exetrace.cc Sun Jan 25 07:22:44 2015 -0500
@@ -120,7 +120,7 @@
ccprintf(outs, D=%#018x, data.as_int);
}
-if (Debug::ExecEffAddr addr_valid)
+if (Debug::ExecEffAddr getMemValid())
outs A=0x hex addr;
if (Debug::ExecFetchSeq fetch_seq_valid)
diff -r 61a0b02aa800 -r aef704eaedd2 src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc Sun Jan 25 07:22:26 2015 -0500
+++ b/src/cpu/inorder/resources/cache_unit.cc Sun Jan 25 07:22:44 2015 -0500
@@ -425,7 +425,7 @@
inst-totalSize = size;
if (inst-traceData) {
-inst-traceData-setAddr(addr);
+inst-traceData-setMem(addr, size, flags);
}
if (inst-split2ndAccess) {
@@ -519,9 +519,8 @@
int fullSize = size;
inst-totalSize = size;
-if (inst-traceData) {
-inst-traceData-setAddr(addr);
-}
+if (inst-traceData)
+inst-traceData-setMem(addr, size, flags);
if (inst-split2ndAccess) {
size = inst-split2ndSize;
diff -r 61a0b02aa800 -r aef704eaedd2 src/cpu/minor/lsq.cc
--- a/src/cpu/minor/lsq.cc Sun Jan 25 07:22:26 2015 -0500
+++ b/src/cpu/minor/lsq.cc Sun Jan 25 07:22:44 2015 -0500
@@ -1499,7 +1499,7 @@
}
if (inst-traceData)
-inst-traceData-setAddr(addr);
+inst-traceData-setMem(addr, size, flags);
request-request.setThreadContext(cpu.cpuId(), /* thread id */ 0);
request-request.setVirt(0 /* asid */,
diff -r 61a0b02aa800 -r aef704eaedd2 src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc Sun Jan 25 07:22:26 2015 -0500
+++ b/src/cpu/simple/atomic.cc Sun Jan 25 07:22:44 2015 -0500
@@ -317,9 +317,8 @@
// use the CPU's statically allocated read request and packet objects
Request *req = data_read_req;
-if (traceData) {
-traceData-setAddr(addr);
-}
+if (traceData)
+traceData-setMem(addr, size, flags);
//The size of the data we're trying to read.
int fullSize = size;
@@ -413,9 +412,8 @@
// use the CPU's statically allocated write request and packet objects
Request *req = data_write_req;
-if (traceData) {
-traceData-setAddr(addr);
-}
+if (traceData)
+traceData-setMem(addr, size, flags);
//The size of the data we're trying to read.
int fullSize = size;
diff -r 61a0b02aa800 -r aef704eaedd2 src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc Sun Jan 25 07:22:26 2015 -0500
+++ b/src/cpu/simple/timing.cc Sun Jan 25 07:22:44 2015 -0500
@@ -402,9 +402,8 @@
unsigned block_size = cacheLineSize();
BaseTLB::Mode mode = BaseTLB::Read;
-if (traceData) {
-traceData-setAddr(addr);
-}
+if (traceData)
+traceData-setMem(addr, size, flags);
RequestPtr req = new Request(asid, addr, size,
flags, dataMasterId(), pc, _cpuId, tid);
@@ -479,9 +478,8 @@
memcpy(newData, data, size);
}
-if (traceData) {
-traceData-setAddr(addr);
-}
+if (traceData)
+traceData-setMem(addr, size, flags);
RequestPtr req = new Request(asid, addr, size,
flags, dataMasterId(), pc, _cpuId, tid);
diff -r 61a0b02aa800 -r aef704eaedd2 src/sim/insttracer.hh
--- a/src/sim/insttracer.hh Sun Jan 25 07:22:26 2015 -0500
+++ b/src/sim/insttracer.hh Sun
[gem5-dev] changeset in gem5: cpu: Put all CPU instruction tracers in a sin...
changeset fae54a666162 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=fae54a666162 description: cpu: Put all CPU instruction tracers in a single file diffstat: src/arch/arm/ArmNativeTrace.py | 2 +- src/arch/sparc/SparcNativeTrace.py | 2 +- src/arch/x86/X86NativeTrace.py | 2 +- src/cpu/BaseCPU.py | 2 +- src/cpu/CPUTracers.py | 48 ++ src/cpu/ExeTracer.py | 36 src/cpu/IntelTrace.py | 36 src/cpu/NativeTrace.py | 37 - src/cpu/SConscript | 4 +-- 9 files changed, 53 insertions(+), 116 deletions(-) diffs (237 lines): diff -r c3fd4c020e49 -r fae54a666162 src/arch/arm/ArmNativeTrace.py --- a/src/arch/arm/ArmNativeTrace.pySun Jan 25 07:22:05 2015 -0500 +++ b/src/arch/arm/ArmNativeTrace.pySun Jan 25 07:22:17 2015 -0500 @@ -28,7 +28,7 @@ from m5.SimObject import SimObject from m5.params import * -from NativeTrace import NativeTrace +from CPUTracers import NativeTrace class ArmNativeTrace(NativeTrace): type = 'ArmNativeTrace' diff -r c3fd4c020e49 -r fae54a666162 src/arch/sparc/SparcNativeTrace.py --- a/src/arch/sparc/SparcNativeTrace.pySun Jan 25 07:22:05 2015 -0500 +++ b/src/arch/sparc/SparcNativeTrace.pySun Jan 25 07:22:17 2015 -0500 @@ -28,7 +28,7 @@ from m5.SimObject import SimObject from m5.params import * -from NativeTrace import NativeTrace +from CPUTracers import NativeTrace class SparcNativeTrace(NativeTrace): type = 'SparcNativeTrace' diff -r c3fd4c020e49 -r fae54a666162 src/arch/x86/X86NativeTrace.py --- a/src/arch/x86/X86NativeTrace.pySun Jan 25 07:22:05 2015 -0500 +++ b/src/arch/x86/X86NativeTrace.pySun Jan 25 07:22:17 2015 -0500 @@ -28,7 +28,7 @@ from m5.SimObject import SimObject from m5.params import * -from NativeTrace import NativeTrace +from CPUTracers import NativeTrace class X86NativeTrace(NativeTrace): type = 'X86NativeTrace' diff -r c3fd4c020e49 -r fae54a666162 src/cpu/BaseCPU.py --- a/src/cpu/BaseCPU.pySun Jan 25 07:22:05 2015 -0500 +++ b/src/cpu/BaseCPU.pySun Jan 25 07:22:17 2015 -0500 @@ -49,7 +49,7 @@ from XBar import CoherentXBar from InstTracer import InstTracer -from ExeTracer import ExeTracer +from CPUTracers import ExeTracer from MemObject import MemObject from ClockDomain import * diff -r c3fd4c020e49 -r fae54a666162 src/cpu/CPUTracers.py --- /dev/null Thu Jan 01 00:00:00 1970 + +++ b/src/cpu/CPUTracers.py Sun Jan 25 07:22:17 2015 -0500 @@ -0,0 +1,48 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +from m5.SimObject import SimObject +from m5.params import * +from InstTracer import InstTracer + +class ExeTracer(InstTracer): +type = 'ExeTracer' +cxx_class = 'Trace::ExeTracer' +cxx_header = cpu/exetrace.hh + +class IntelTrace(InstTracer): +type = 'IntelTrace' +cxx_class = 'Trace::IntelTrace' +cxx_header = cpu/inteltrace.hh + +class NativeTrace(ExeTracer): +abstract = True +type = 'NativeTrace' +cxx_class = 'Trace::NativeTrace' +cxx_header = 'cpu/nativetrace.hh' + diff -r c3fd4c020e49 -r fae54a666162 src/cpu/ExeTracer.py --- a/src/cpu/ExeTracer.py Sun Jan 25 07:22:05 2015 -0500 +++ /dev/null Thu Jan 01 00:00:00 1970 + @@ -1,36 +0,0 @@ -# Copyright
[gem5-dev] changeset in gem5: cpu: remove legion tracer
changeset c3fd4c020e49 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c3fd4c020e49
description:
cpu: remove legion tracer
If someone wants to debug with legion again they can restore the
code from the repository, but no need to have it hang around
indefinately.
diffstat:
src/cpu/LegionTrace.py | 36 --
src/cpu/SConscript |4 -
src/cpu/base.hh |4 +-
src/cpu/legiontrace.cc | 590 ---
src/cpu/legiontrace.hh | 83 --
src/cpu/m5legion_interface.h | 83 --
6 files changed, 3 insertions(+), 797 deletions(-)
diffs (truncated from 837 to 300 lines):
diff -r a0dab21e422f -r c3fd4c020e49 src/cpu/LegionTrace.py
--- a/src/cpu/LegionTrace.pyTue Dec 23 11:51:40 2014 -0600
+++ /dev/null Thu Jan 01 00:00:00 1970 +
@@ -1,36 +0,0 @@
-# Copyright (c) 2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black
-
-from m5.SimObject import SimObject
-from m5.params import *
-from InstTracer import InstTracer
-
-class LegionTrace(InstTracer):
-type = 'LegionTrace'
-cxx_class = 'Trace::LegionTrace'
-cxx_header = cpu/legiontrace.hh
diff -r a0dab21e422f -r c3fd4c020e49 src/cpu/SConscript
--- a/src/cpu/SConscriptTue Dec 23 11:51:40 2014 -0600
+++ b/src/cpu/SConscriptSun Jan 25 07:22:05 2015 -0500
@@ -64,10 +64,6 @@
Source('thread_state.cc')
Source('timing_expr.cc')
-if env['TARGET_ISA'] == 'sparc':
-SimObject('LegionTrace.py')
-Source('legiontrace.cc')
-
SimObject('DummyChecker.py')
SimObject('StaticInstFlags.py')
Source('checker/cpu.cc')
diff -r a0dab21e422f -r c3fd4c020e49 src/cpu/base.hh
--- a/src/cpu/base.hh Tue Dec 23 11:51:40 2014 -0600
+++ b/src/cpu/base.hh Sun Jan 25 07:22:05 2015 -0500
@@ -109,8 +109,10 @@
{
protected:
-// @todo remove me after debugging with legion done
+/// Instruction count used for SPARC misc register
+/// @todo unify this with the counters that cpus individually keep
Tick instCnt;
+
// every cpu has an id, put it in the base cpu
// Set at initialization, only time a cpuId might change is during a
// takeover (which should be done from within the BaseCPU anyway,
diff -r a0dab21e422f -r c3fd4c020e49 src/cpu/legiontrace.cc
--- a/src/cpu/legiontrace.ccTue Dec 23 11:51:40 2014 -0600
+++ /dev/null Thu Jan 01 00:00:00 1970 +
@@ -1,590 +0,0 @@
-/*
- * Copyright (c) 2001-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR
[gem5-dev] Cron m5test@zizzer /z/m5/regression/do-regression --scratch all
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing passed. * build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing passed. * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual passed. * build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic passed. * build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic passed. * build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby passed. * build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby passed. * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual passed. * build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full passed. * build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual passed. * build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby passed. * build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing passed. * build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp passed. * build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing passed. * build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 passed. * build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing passed. * build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing passed. * build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby passed. * build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor passed. * build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing passed. * build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing passed. * build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing passed. * build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic passed. * build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing passed. * build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing passed. * build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing passed. * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing passed. * build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic passed. * build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic passed. * build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic passed. * build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing passed. * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic passed. * build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing passed. * build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer passed. * build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer passed. * build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer passed. * build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer passed. * build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing passed. * build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing passed. * build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level passed. * build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level passed. * build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level passed. * build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level passed. * build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory passed. * build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory passed. * build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory passed. *
