[gem5-dev] Cron m5test@zizzer2 /z/m5/regression/do-regression quick
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing passed. * build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic passed. * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby passed. * build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic passed. * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing passed. * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual passed. * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic passed. * build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing passed. * build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing passed. * build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby passed. * build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing passed. * build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing passed. * build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing passed. * build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby passed. * build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic passed. * build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic passed. * build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing passed. * build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer passed. * build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer passed. * build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer passed. * build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer passed. * build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic passed. * build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level passed. * build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level passed. * build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level passed. * build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level passed. * build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory passed. * build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory passed. * build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory passed. * build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory passed. * build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token passed. * build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token passed. * build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token passed. [ CXX] MIPS/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.cc - .o * build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token passed. [ CXX] MIPS/python/m5/internal/param_NetworkLink_wrap.cc - .o * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing passed.diff -ubrs -I '^command line:' -I '^gem5 compiled ' -I '^gem5 started ' -I '^gem5 executing on ' -I '^Simulation complete at' -I '^Listening for' -I 'listening for remote gdb' '--exclude=stats.txt' '--exclude=outdiff' /z/m5/regression/zizzer/gem5/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/config.ini * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby passed. * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic passed. * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing passed.
[gem5-dev] changeset in gem5: mem: Align all MSHR entries to block boundaries
changeset b32578b2af99 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b32578b2af99
description:
mem: Align all MSHR entries to block boundaries
This patch aligns all MSHR queue entries to block boundaries to
simplify checks for matches. Previously there were corner cases that
could lead to existing entries not being identified as matches.
There are, rather alarmingly, a few regressions that change with this
patch.
diffstat:
src/mem/cache/base.hh | 9 +++--
src/mem/cache/cache_impl.hh | 21 -
src/mem/cache/mshr.cc | 22 +++---
src/mem/cache/mshr.hh | 30 +++---
src/mem/cache/mshr_queue.cc | 31 +--
src/mem/cache/mshr_queue.hh | 34 +++---
6 files changed, 81 insertions(+), 66 deletions(-)
diffs (truncated from 425 to 300 lines):
diff -r d524dc4f16ae -r b32578b2af99 src/mem/cache/base.hh
--- a/src/mem/cache/base.hh Fri Mar 27 04:55:54 2015 -0400
+++ b/src/mem/cache/base.hh Fri Mar 27 04:55:55 2015 -0400
@@ -217,6 +217,11 @@
MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
PacketPtr pkt, Tick time, bool requestBus)
{
+// check that the address is block aligned since we rely on
+// this in a number of places when checking for matches and
+// overlap
+assert(addr == blockAlign(addr));
+
MSHR *mshr = mq-allocate(addr, size, pkt, time, order++);
if (mq-isFull()) {
@@ -506,7 +511,7 @@
{
assert(pkt-isWrite() !pkt-isRead());
return allocateBufferInternal(writeBuffer,
- pkt-getAddr(), pkt-getSize(),
+ blockAlign(pkt-getAddr()), blkSize,
pkt, time, requestBus);
}
@@ -515,7 +520,7 @@
assert(pkt-req-isUncacheable());
assert(pkt-isRead());
return allocateBufferInternal(mshrQueue,
- pkt-getAddr(), pkt-getSize(),
+ blockAlign(pkt-getAddr()), blkSize,
pkt, time, requestBus);
}
diff -r d524dc4f16ae -r b32578b2af99 src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh Fri Mar 27 04:55:54 2015 -0400
+++ b/src/mem/cache/cache_impl.hh Fri Mar 27 04:55:55 2015 -0400
@@ -836,6 +836,9 @@
}
PacketPtr pkt = new Packet(cpu_pkt-req, cmd, blkSize);
+// the packet should be block aligned
+assert(pkt-getAddr() == blockAlign(pkt-getAddr()));
+
pkt-allocate();
DPRINTF(Cache, %s created %s addr %#llx size %d\n,
__func__, pkt-cmdString(), pkt-getAddr(), pkt-getSize());
@@ -1209,6 +1212,10 @@
completion_time += clockEdge(responseLatency) +
pkt-payloadDelay;
if (pkt-isRead() !is_error) {
+// sanity check
+assert(pkt-getAddr() == tgt_pkt-getAddr());
+assert(pkt-getSize() = tgt_pkt-getSize());
+
tgt_pkt-setData(pkt-getConstPtruint8_t());
}
}
@@ -1543,7 +1550,10 @@
// if we got new data, copy it in (checking for a read response
// and a response that has data is the same in the end)
if (pkt-isRead()) {
+// sanity checks
assert(pkt-hasData());
+assert(pkt-getSize() == blkSize);
+
std::memcpy(blk-data, pkt-getConstPtruint8_t(), blkSize);
}
// We pay for fillLatency here.
@@ -1899,7 +1909,7 @@
!miss_mshr)) {
// need to search MSHR queue for conflicting earlier miss.
MSHR *conflict_mshr =
-mshrQueue.findPending(write_mshr-addr, write_mshr-size,
+mshrQueue.findPending(write_mshr-blkAddr,
write_mshr-isSecure);
if (conflict_mshr conflict_mshr-order write_mshr-order) {
@@ -1914,7 +1924,7 @@
} else if (miss_mshr) {
// need to check for conflicting earlier writeback
MSHR *conflict_mshr =
-writeBuffer.findPending(miss_mshr-addr, miss_mshr-size,
+writeBuffer.findPending(miss_mshr-blkAddr,
miss_mshr-isSecure);
if (conflict_mshr) {
// not sure why we don't check order here... it was in the
@@ -1985,10 +1995,10 @@
if (mshr-isForwardNoResponse()) {
// no response expected, just forward packet as it is
-assert(tags-findBlock(mshr-addr, mshr-isSecure) == NULL);
+assert(tags-findBlock(mshr-blkAddr, mshr-isSecure) == NULL);
pkt = tgt_pkt;
} else {
-BlkType *blk = tags-findBlock(mshr-addr, mshr-isSecure);
+BlkType *blk = tags-findBlock(mshr-blkAddr, mshr-isSecure);
if (tgt_pkt-cmd ==
[gem5-dev] changeset in gem5: mem: Rename PREFETCH_SNOOP_SQUASH flag to BLO...
changeset d524dc4f16ae in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d524dc4f16ae
description:
mem: Rename PREFETCH_SNOOP_SQUASH flag to BLOCK_CACHED
This patch subsumes the PREFETCH_SNOOP_SQUASH flag with the more
generic BLOCK_CACHED flag. Future patches implementing cache eviction
messages can use the BLOCK_CACHED flag in almost the same manner as
hardware prefetches use the PREFETCH_SNOOP_SQUASH flag. The
PREFTECH_SNOOP_FLAG is set if the prefetch target is found in the tags
or the MSHRs in any state, so we are simply replacing calls to
setPrefetchSquashed() with setBlockCached(). The case of where the
prefetch target is found in the writeback MSHRs of upper level caches
continues to be covered by the MEM_INHIBIT flag.
diffstat:
src/mem/cache/cache_impl.hh | 21 +++--
src/mem/packet.hh | 9 +
2 files changed, 16 insertions(+), 14 deletions(-)
diffs (79 lines):
diff -r fe0972727902 -r d524dc4f16ae src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh Thu Mar 26 11:16:44 2015 -0400
+++ b/src/mem/cache/cache_impl.hh Fri Mar 27 04:55:54 2015 -0400
@@ -1651,11 +1651,11 @@
if (snoopPkt.sharedAsserted()) {
pkt-assertShared();
}
-// If this request is a prefetch and an
-// upper level squashes the prefetch request,
-// make sure to propogate the squash to the requester.
-if (snoopPkt.prefetchSquashed()) {
-pkt-setPrefetchSquashed();
+// If this request is a prefetch or clean evict and an
+// upper level signals block present, make sure to
+// propagate the block presence to the requester.
+if (snoopPkt.isBlockCached()) {
+pkt-setBlockCached();
}
} else {
cpuSidePort-sendAtomicSnoop(pkt);
@@ -1695,7 +1695,7 @@
if (pkt-cmd == MemCmd::HardPFReq) {
DPRINTF(Cache, Squashing prefetch from lower cache %#x\n,
pkt-getAddr());
-pkt-setPrefetchSquashed();
+pkt-setBlockCached();
return;
}
@@ -1789,9 +1789,10 @@
// Squash any prefetch requests from below on MSHR hits
if (mshr pkt-cmd == MemCmd::HardPFReq) {
-DPRINTF(Cache, Squashing prefetch from lower cache on mshr hit %#x\n,
+DPRINTF(Cache, Setting block present to squash prefetch from
+lower cache on mshr hit %#x\n,
pkt-getAddr());
-pkt-setPrefetchSquashed();
+pkt-setBlockCached();
return;
}
@@ -2022,8 +2023,8 @@
return NULL;
}
-if (snoop_pkt.prefetchSquashed() || blk != NULL) {
-DPRINTF(Cache, Prefetch squashed by cache.
+if (snoop_pkt.isBlockCached() || blk != NULL) {
+DPRINTF(Cache, Block present, prefetch squashed by cache.
Deallocating mshr target %#x.\n, mshr-addr);
// Deallocate the mshr target
diff -r fe0972727902 -r d524dc4f16ae src/mem/packet.hh
--- a/src/mem/packet.hh Thu Mar 26 11:16:44 2015 -0400
+++ b/src/mem/packet.hh Fri Mar 27 04:55:54 2015 -0400
@@ -261,8 +261,9 @@
/// suppress the error if this packet encounters a functional
/// access failure.
static const FlagsType SUPPRESS_FUNC_ERROR= 0x8000;
-// Signal prefetch squash through express snoop flag
-static const FlagsType PREFETCH_SNOOP_SQUASH = 0x0001;
+// Signal block present to squash prefetch and cache evict packets
+// through express snoop flag
+static const FlagsType BLOCK_CACHED = 0x0001;
Flags flags;
@@ -505,8 +506,8 @@
bool isSupplyExclusive() const { return flags.isSet(SUPPLY_EXCLUSIVE); }
void setSuppressFuncError() { flags.set(SUPPRESS_FUNC_ERROR); }
bool suppressFuncError() const { return flags.isSet(SUPPRESS_FUNC_ERROR);
}
-void setPrefetchSquashed() { flags.set(PREFETCH_SNOOP_SQUASH); }
-bool prefetchSquashed() const { return
flags.isSet(PREFETCH_SNOOP_SQUASH); }
+void setBlockCached() { flags.set(BLOCK_CACHED); }
+bool isBlockCached() const { return flags.isSet(BLOCK_CACHED); }
// Network error conditions... encapsulate them as methods since
// their encoding keeps changing (from result field to command
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] changeset in gem5: mem: Modernise MSHR iterators to C++11
changeset b2071d0eb5f1 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b2071d0eb5f1
description:
mem: Modernise MSHR iterators to C++11
This patch updates the iterators in the MSHR and MSHR queues to use
C++11 range-based for loops. It also does a bit of additional house
keeping.
diffstat:
src/mem/cache/mshr.cc | 32 ++--
src/mem/cache/mshr.hh | 21 +
src/mem/cache/mshr_queue.cc | 30 +++---
3 files changed, 30 insertions(+), 53 deletions(-)
diffs (224 lines):
diff -r ee0e03afd9da -r b2071d0eb5f1 src/mem/cache/mshr.cc
--- a/src/mem/cache/mshr.cc Fri Mar 27 04:55:57 2015 -0400
+++ b/src/mem/cache/mshr.cc Fri Mar 27 04:55:57 2015 -0400
@@ -104,7 +104,7 @@
}
}
-push_back(Target(pkt, readyTime, order, source, markPending));
+emplace_back(Target(pkt, readyTime, order, source, markPending));
}
@@ -130,9 +130,8 @@
if (!hasUpgrade)
return;
-Iterator end_i = end();
-for (Iterator i = begin(); i != end_i; ++i) {
-replaceUpgrade(i-pkt);
+for (auto t : *this) {
+replaceUpgrade(t.pkt);
}
hasUpgrade = false;
@@ -142,16 +141,15 @@
void
MSHR::TargetList::clearDownstreamPending()
{
-Iterator end_i = end();
-for (Iterator i = begin(); i != end_i; ++i) {
-if (i-markedPending) {
+for (auto t : *this) {
+if (t.markedPending) {
// Iterate over the SenderState stack and see if we find
// an MSHR entry. If we find one, clear the
// downstreamPending flag by calling
// clearDownstreamPending(). This recursively clears the
// downstreamPending flag in all caches this packet has
// passed through.
-MSHR *mshr = i-pkt-findNextSenderStateMSHR();
+MSHR *mshr = t.pkt-findNextSenderStateMSHR();
if (mshr != NULL) {
mshr-clearDownstreamPending();
}
@@ -163,9 +161,8 @@
bool
MSHR::TargetList::checkFunctional(PacketPtr pkt)
{
-Iterator end_i = end();
-for (Iterator i = begin(); i != end_i; ++i) {
-if (pkt-checkFunctional(i-pkt)) {
+for (auto t : *this) {
+if (pkt-checkFunctional(t.pkt)) {
return true;
}
}
@@ -175,13 +172,12 @@
void
-MSHR::TargetList::
-print(std::ostream os, int verbosity, const std::string prefix) const
+MSHR::TargetList::print(std::ostream os, int verbosity,
+const std::string prefix) const
{
-ConstIterator end_i = end();
-for (ConstIterator i = begin(); i != end_i; ++i) {
+for (auto t : *this) {
const char *s;
-switch (i-source) {
+switch (t.source) {
case Target::FromCPU:
s = FromCPU;
break;
@@ -196,7 +192,7 @@
break;
}
ccprintf(os, %s%s: , prefix, s);
-i-pkt-print(os, verbosity, );
+t.pkt-print(os, verbosity, );
}
}
@@ -413,7 +409,7 @@
void
-MSHR::handleFill(Packet *pkt, CacheBlk *blk)
+MSHR::handleFill(PacketPtr pkt, CacheBlk *blk)
{
if (!pkt-sharedAsserted()
!(hasPostInvalidate() || hasPostDowngrade())
diff -r ee0e03afd9da -r b2071d0eb5f1 src/mem/cache/mshr.hh
--- a/src/mem/cache/mshr.hh Fri Mar 27 04:55:57 2015 -0400
+++ b/src/mem/cache/mshr.hh Fri Mar 27 04:55:57 2015 -0400
@@ -100,13 +100,13 @@
FromPrefetcher
};
-Tick recvTime; //! Time when request was received (for stats)
-Tick readyTime; //! Time when request is ready to be serviced
-Counter order; //! Global order (for memory consistency mgmt)
-PacketPtr pkt; //! Pending request packet.
-Source source; //! Did request come from cpu, memory, or prefetcher?
-bool markedPending; //! Did we mark upstream MSHR
-//! as downstreamPending?
+const Tick recvTime; //! Time when request was received (for stats)
+const Tick readyTime; //! Time when request is ready to be serviced
+const Counter order; //! Global order (for memory consistency mgmt)
+const PacketPtr pkt; //! Pending request packet.
+const Source source; //! Request from cpu, memory, or prefetcher?
+const bool markedPending; //! Did we mark upstream MSHR
+ //! as downstreamPending?
Target(PacketPtr _pkt, Tick _readyTime, Counter _order,
Source _source, bool _markedPending)
@@ -116,9 +116,6 @@
};
class TargetList : public std::listTarget {
-/** Target list iterator. */
-typedef std::listTarget::iterator Iterator;
-typedef std::listTarget::const_iterator ConstIterator;
public:
bool needsExclusive;
@@ -126,7 +123,7 @@
TargetList();
void resetFlags() { needsExclusive = hasUpgrade
[gem5-dev] changeset in gem5: mem: Ignore uncacheable MSHRs when finding ma...
changeset 9a34e28cd2c2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9a34e28cd2c2
description:
mem: Ignore uncacheable MSHRs when finding matches
This patch changes how we search for matching MSHRs, ignoring any MSHR
that is allocated for an uncacheable access. By doing so, this patch
fixes a corner case in the MSHRs where incorrect data ended up being
copied into a (cacheable) read packet due to a first uncacheable MSHR
target of size 4, followed by a cacheable target to the same MSHR of
size 64. The latter target was filled with nonsense data.
diffstat:
src/mem/cache/mshr.cc | 14 +-
src/mem/cache/mshr_queue.cc | 11 +--
2 files changed, 18 insertions(+), 7 deletions(-)
diffs (59 lines):
diff -r 993c2baa485a -r 9a34e28cd2c2 src/mem/cache/mshr.cc
--- a/src/mem/cache/mshr.cc Fri Mar 27 04:55:59 2015 -0400
+++ b/src/mem/cache/mshr.cc Fri Mar 27 04:56:00 2015 -0400
@@ -273,6 +273,15 @@
void
MSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order)
{
+// assume we'd never issue a prefetch when we've got an
+// outstanding miss
+assert(pkt-cmd != MemCmd::HardPFReq);
+
+// uncacheable accesses always allocate a new MSHR, and cacheable
+// accesses ignore any uncacheable MSHRs, thus we should never
+// have targets addded if originally allocated uncacheable
+assert(!_isUncacheable);
+
// if there's a request already in service for this MSHR, we will
// have to defer the new target until after the response if any of
// the following are true:
@@ -283,11 +292,6 @@
// getting an exclusive block back or we have already snooped
// another read request that will downgrade our exclusive block
// to shared
-
-// assume we'd never issue a prefetch when we've got an
-// outstanding miss
-assert(pkt-cmd != MemCmd::HardPFReq);
-
if (inService
(!deferredTargets.empty() || hasPostInvalidate() ||
(pkt-needsExclusive()
diff -r 993c2baa485a -r 9a34e28cd2c2 src/mem/cache/mshr_queue.cc
--- a/src/mem/cache/mshr_queue.cc Fri Mar 27 04:55:59 2015 -0400
+++ b/src/mem/cache/mshr_queue.cc Fri Mar 27 04:56:00 2015 -0400
@@ -69,7 +69,13 @@
MSHRQueue::findMatch(Addr blk_addr, bool is_secure) const
{
for (const auto mshr : allocatedList) {
-if (mshr-blkAddr == blk_addr mshr-isSecure == is_secure) {
+// we ignore any MSHRs allocated for uncacheable accesses and
+// simply ignore them when matching, in the cache we never
+// check for matches when adding new uncacheable entries, and
+// we do not want normal cacheable accesses being added to an
+// MSHR serving an uncacheable access
+if (!mshr-isUncacheable() mshr-blkAddr == blk_addr
+mshr-isSecure == is_secure) {
return mshr;
}
}
@@ -84,7 +90,8 @@
assert(matches.empty());
bool retval = false;
for (const auto mshr : allocatedList) {
-if (mshr-blkAddr == blk_addr mshr-isSecure == is_secure) {
+if (!mshr-isUncacheable() mshr-blkAddr == blk_addr
+mshr-isSecure == is_secure) {
retval = true;
matches.push_back(mshr);
}
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] changeset in gem5: mem: Remove redundant allocateUncachedReadBuf...
changeset 993c2baa485a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=993c2baa485a
description:
mem: Remove redundant allocateUncachedReadBuffer in cache
This patch removes the no-longer-needed
allocateUncachedReadBuffer. Besides the checks it is exactly the same
as allocateMissBuffer and thus provides no value.
diffstat:
src/mem/cache/base.hh | 14 +-
src/mem/cache/cache_impl.hh | 2 +-
2 files changed, 2 insertions(+), 14 deletions(-)
diffs (50 lines):
diff -r b2071d0eb5f1 -r 993c2baa485a src/mem/cache/base.hh
--- a/src/mem/cache/base.hh Fri Mar 27 04:55:57 2015 -0400
+++ b/src/mem/cache/base.hh Fri Mar 27 04:55:59 2015 -0400
@@ -210,9 +210,7 @@
*
* allocateBufferInternal() function is called in:
* - MSHR allocateWriteBuffer (unchached write forwarded to WriteBuffer);
- * - MSHR allocateMissBuffer (cacheable miss in MSHR queue);
- * - MSHR allocateUncachedReadBuffer (unchached read allocated in MSHR
- * queue)
+ * - MSHR allocateMissBuffer (miss in MSHR queue);
*/
MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
PacketPtr pkt, Tick time, bool requestBus)
@@ -501,7 +499,6 @@
MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
{
-assert(!pkt-req-isUncacheable());
return allocateBufferInternal(mshrQueue,
blockAlign(pkt-getAddr()), blkSize,
pkt, time, requestBus);
@@ -515,15 +512,6 @@
pkt, time, requestBus);
}
-MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus)
-{
-assert(pkt-req-isUncacheable());
-assert(pkt-isRead());
-return allocateBufferInternal(mshrQueue,
- blockAlign(pkt-getAddr()), blkSize,
- pkt, time, requestBus);
-}
-
/**
* Returns true if the cache is blocked for accesses.
*/
diff -r b2071d0eb5f1 -r 993c2baa485a src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh Fri Mar 27 04:55:57 2015 -0400
+++ b/src/mem/cache/cache_impl.hh Fri Mar 27 04:55:59 2015 -0400
@@ -555,7 +555,7 @@
pkt-headerDelay;
// Reset the timing of the packet.
pkt-headerDelay = pkt-payloadDelay = 0;
-allocateUncachedReadBuffer(pkt, allocate_rd_buffer_time, true);
+allocateMissBuffer(pkt, allocate_rd_buffer_time, true);
}
assert(pkt-needsResponse()); // else we should delete it here??
return true;
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] changeset in gem5: arm, configs: Do not forward snoops from I cache
changeset 8a7285d6197e in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=8a7285d6197e description: arm, configs: Do not forward snoops from I cache This fix simply tells the I cache to not forward snoops to the fetch unit (since there is really no reason to do so). diffstat: configs/common/O3_ARM_v7a.py | 9 + 1 files changed, 5 insertions(+), 4 deletions(-) diffs (40 lines): diff -r ea35886cd847 -r 8a7285d6197e configs/common/O3_ARM_v7a.py --- a/configs/common/O3_ARM_v7a.py Fri Mar 27 04:56:03 2015 -0400 +++ b/configs/common/O3_ARM_v7a.py Fri Mar 27 04:56:10 2015 -0400 @@ -150,7 +150,8 @@ tgts_per_mshr = 8 size = '32kB' assoc = 2 -is_top_level = 'true' +is_top_level = True +forward_snoops = False # Data Cache class O3_ARM_v7a_DCache(BaseCache): @@ -161,7 +162,7 @@ size = '32kB' assoc = 2 write_buffers = 16 -is_top_level = 'true' +is_top_level = True # TLB Cache # Use a cache as a L2 TLB @@ -173,7 +174,7 @@ size = '1kB' assoc = 8 write_buffers = 16 -is_top_level = 'true' +is_top_level = True # L2 Cache @@ -185,7 +186,7 @@ size = '1MB' assoc = 16 write_buffers = 8 -prefetch_on_access = 'true' +prefetch_on_access = True # Simple stride prefetcher prefetcher = StridePrefetcher(degree=8, latency = 1) tags = RandomRepl() ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] changeset in gem5: mem: Cleanup flow for uncacheable accesses
changeset 9e521c0c3877 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9e521c0c3877
description:
mem: Cleanup flow for uncacheable accesses
This patch simplifies the code dealing with uncacheable timing
accesses, aiming to align it with the existing miss handling. Similar
to what we do in atomic, a timing request now goes through
Cache::access (where the block is also flushed), and then proceeds to
ignore any existing MSHR for the block in question. This unifies the
flow for cacheable and uncacheable accesses, and for atomic and timing.
diffstat:
src/mem/cache/cache_impl.hh | 77 +++-
1 files changed, 26 insertions(+), 51 deletions(-)
diffs (129 lines):
diff -r 9a34e28cd2c2 -r 9e521c0c3877 src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh Fri Mar 27 04:56:00 2015 -0400
+++ b/src/mem/cache/cache_impl.hh Fri Mar 27 04:56:01 2015 -0400
@@ -518,49 +518,6 @@
return true;
}
-if (pkt-req-isUncacheable()) {
-uncacheableFlush(pkt);
-
-// writes go in write buffer, reads use MSHR,
-// prefetches are acknowledged (responded to) and dropped
-if (pkt-cmd.isPrefetch()) {
-// prefetching (cache loading) uncacheable data is nonsensical
-pkt-makeTimingResponse();
-std::memset(pkt-getPtruint8_t(), 0xFF, pkt-getSize());
-// We use lookupLatency here because the request is uncacheable.
-// We pay also for headerDelay that is charged of bus latencies if
-// the packet comes from the bus.
-Tick time = clockEdge(lookupLatency) + pkt-headerDelay;
-// Reset the timing of the packet.
-pkt-headerDelay = pkt-payloadDelay = 0;
-cpuSidePort-schedTimingResp(pkt, time);
-return true;
-} else if (pkt-isWrite() !pkt-isRead()) {
-// We pay also for headerDelay that is charged of bus latencies if
-// the packet comes from the bus.
-Tick allocate_wr_buffer_time = clockEdge(forwardLatency) +
-pkt-headerDelay;
-// Reset the timing of the packet.
-pkt-headerDelay = pkt-payloadDelay = 0;
-allocateWriteBuffer(pkt, allocate_wr_buffer_time, true);
-} else {
-// We use forwardLatency here because there is an uncached
-// memory read, allocateded to MSHR queue (it requires the same
-// time of forwarding to WriteBuffer, in our assumption). It
-// specifies the latency to allocate an internal buffer and to
-// schedule an event to the queued port.
-// We pay also for headerDelay that is charged of bus latencies if
-// the packet comes from the bus.
-Tick allocate_rd_buffer_time = clockEdge(forwardLatency) +
-pkt-headerDelay;
-// Reset the timing of the packet.
-pkt-headerDelay = pkt-payloadDelay = 0;
-allocateMissBuffer(pkt, allocate_rd_buffer_time, true);
-}
-assert(pkt-needsResponse()); // else we should delete it here??
-return true;
-}
-
// We use lookupLatency here because it is used to specify the latency
// to access.
Cycles lat = lookupLatency;
@@ -590,6 +547,11 @@
bool needsResponse = pkt-needsResponse();
if (satisfied) {
+// should never be satisfying an uncacheable access as we
+// flush and invalidate any existing block as part of the
+// lookup
+assert(!pkt-req-isUncacheable());
+
// hit (for all other request types)
if (prefetcher (prefetchOnAccess || (blk blk-wasPrefetched(
{
@@ -622,7 +584,11 @@
// miss
Addr blk_addr = blockAlign(pkt-getAddr());
-MSHR *mshr = mshrQueue.findMatch(blk_addr, pkt-isSecure());
+
+// ignore any existing MSHR if we are dealing with an
+// uncacheable request
+MSHR *mshr = pkt-req-isUncacheable() ? nullptr :
+mshrQueue.findMatch(blk_addr, pkt-isSecure());
// Software prefetch handling:
// To keep the core from waiting on data it won't look at
@@ -636,6 +602,7 @@
if (pkt-cmd.isSWPrefetch() isTopLevel) {
assert(needsResponse);
assert(pkt-req-hasPaddr());
+assert(!pkt-req-isUncacheable());
// There's no reason to add a prefetch as an additional target
// to an existing MSHR. If an outstanding request is already
@@ -718,12 +685,13 @@
}
} else {
// no MSHR
-assert(pkt-req-masterId() system-maxMasters());
-mshr_misses[pkt-cmdToIndex()][pkt-req-masterId()]++;
-// always mark as cache fill for now... if we implement
-// no-write-allocate
[gem5-dev] changeset in gem5: mem: Allocate cache writebacks before new MSHRs
changeset c48310de1a51 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c48310de1a51
description:
mem: Allocate cache writebacks before new MSHRs
This patch changes the order of writeback allocation such that any
writebacks resulting from a tag lookup (e.g. for an uncacheable
access), are added to the writebuffer before any new MSHR entries are
allocated. This ensures that the writebacks logically precedes the new
allocations.
The patch also changes the uncacheable flush to use proper timed (or
atomic) writebacks, as opposed to functional writes.
diffstat:
src/mem/cache/cache.hh | 12 -
src/mem/cache/cache_impl.hh | 91 +---
2 files changed, 51 insertions(+), 52 deletions(-)
diffs (177 lines):
diff -r 9e521c0c3877 -r c48310de1a51 src/mem/cache/cache.hh
--- a/src/mem/cache/cache.hhFri Mar 27 04:56:01 2015 -0400
+++ b/src/mem/cache/cache.hhFri Mar 27 04:56:02 2015 -0400
@@ -332,18 +332,6 @@
bool invalidateVisitor(BlkType blk);
/**
- * Flush a cache line due to an uncacheable memory access to the
- * line.
- *
- * @note This shouldn't normally happen, but we need to handle it
- * since some architecture models don't implement cache
- * maintenance operations. We won't even try to get a decent
- * timing here since the line should have been flushed earlier by
- * a cache maintenance operation.
- */
-void uncacheableFlush(PacketPtr pkt);
-
-/**
* Squash all requests associated with specified thread.
* intended for use by I-cache.
* @param threadNum The thread to squash.
diff -r 9e521c0c3877 -r c48310de1a51 src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh Fri Mar 27 04:56:01 2015 -0400
+++ b/src/mem/cache/cache_impl.hh Fri Mar 27 04:56:02 2015 -0400
@@ -311,7 +311,22 @@
DPRINTF(Cache, %s for %s addr %#llx size %d\n, __func__,
pkt-cmdString(), pkt-getAddr(), pkt-getSize());
if (pkt-req-isUncacheable()) {
-uncacheableFlush(pkt);
+DPRINTF(Cache, %s%s addr %#llx uncacheable\n, pkt-cmdString(),
+pkt-req-isInstFetch() ? (ifetch) : ,
+pkt-getAddr());
+
+if (pkt-req-isClearLL())
+tags-clearLocks();
+
+// flush and invalidate any existing block
+BlkType *old_blk(tags-findBlock(pkt-getAddr(), pkt-isSecure()));
+if (old_blk old_blk-isValid()) {
+if (old_blk-isDirty())
+writebacks.push_back(writebackBlk(old_blk));
+tags-invalidate(old_blk);
+old_blk-invalidate();
+}
+
blk = NULL;
// lookupLatency is the latency in case the request is uncacheable.
lat = lookupLatency;
@@ -518,14 +533,32 @@
return true;
}
+// anything that is merely forwarded pays for the forward latency and
+// the delay provided by the crossbar
+Tick forward_time = clockEdge(forwardLatency) + pkt-headerDelay;
+
// We use lookupLatency here because it is used to specify the latency
// to access.
Cycles lat = lookupLatency;
BlkType *blk = NULL;
-PacketList writebacks;
-// Note that lat is passed by reference here. The function access() calls
-// accessBlock() which can modify lat value.
-bool satisfied = access(pkt, blk, lat, writebacks);
+bool satisfied = false;
+{
+PacketList writebacks;
+// Note that lat is passed by reference here. The function
+// access() calls accessBlock() which can modify lat value.
+satisfied = access(pkt, blk, lat, writebacks);
+
+// copy writebacks to write buffer here to ensure they logically
+// proceed anything happening below
+while (!writebacks.empty()) {
+PacketPtr wbPkt = writebacks.front();
+// We use forwardLatency here because we are copying
+// writebacks to write buffer.
+allocateWriteBuffer(wbPkt, forward_time, true);
+writebacks.pop_front();
+}
+}
+
// Here we charge the headerDelay that takes into account the latencies
// of the bus, if the packet comes from it.
// The latency charged it is just lat that is the value of lookupLatency
@@ -533,11 +566,6 @@
// In case of a hit we are neglecting response latency.
// In case of a miss we are neglecting forward latency.
Tick request_time = clockEdge(lat) + pkt-headerDelay;
-// Here we condiser forward_time, paying for just forward latency and
-// also charging the delay provided by the xbar.
-// forward_time is used in allocateWriteBuffer() function, called
-// in case of writeback.
-Tick forward_time = clockEdge(forwardLatency) + pkt-headerDelay;
// Here we reset the timing of the packet.
pkt-headerDelay = pkt-payloadDelay = 0;
@@ -743,15 +771,6 @@
if
[gem5-dev] Review Request 2708: arm, dev: Add a NAND flash timing model
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2708/ --- Review request for Default. Repository: gem5 Description --- Changeset 10786:57aa55404aac --- arm, dev: Add a NAND flash timing model This adds a NAND flash timing model. This model takes the number of planes into account and is ultimately intended to be used as a high-level performance model for any device using flash. To access the memory, use either readMemory or writeMemory. To make use of the model you will need an interface model such as UFSHostDevice, which is part of a separate patch. At the moment the flash device is part of the ARM device tree since the only use if the UFSHostDevice, and that in turn relies on the ARM GIC. Diffs - src/dev/arm/abstract_nvm.hh PRE-CREATION src/dev/arm/flash_device.hh PRE-CREATION src/dev/arm/flash_device.cc PRE-CREATION src/dev/arm/AbstractNVM.py PRE-CREATION src/dev/arm/FlashDevice.py PRE-CREATION src/dev/arm/SConscript 8a7285d6197e Diff: http://reviews.gem5.org/r/2708/diff/ Testing --- Heavily used in our ISPASS'15 paper Thanks, Andreas Hansson ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Review Request 2709: arm, dev: Add a UFS device
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2709/ --- Review request for Default. Repository: gem5 Description --- Changeset 10787:b223b4121455 --- arm, dev: Add a UFS device This patch introduces a UFS host controller and a UFS device. More information about the UFS standard can be found at the JEDEC site: http://www.jedec.org/standards-documents/results/jesd220 Note that the model does not implement the complete standard, and as such is not an actual implementation of UFS. The following SCSI commands are implemented: inquiry, read, read capacity, report LUNs, start/stop, test unit ready, verify, write, format unit, send diagnostic, synchronize cache, mode select, mode sense, request sense, unmap, write buffer and read buffer. This is sufficient for usage with Linux and Android. To interact with this model a kernel version 3.9 or above is needed. Diffs - src/dev/arm/ufs_device.hh PRE-CREATION src/dev/arm/ufs_device.cc PRE-CREATION src/dev/arm/SConscript 8a7285d6197e src/dev/arm/UFSHostDevice.py PRE-CREATION Diff: http://reviews.gem5.org/r/2709/diff/ Testing --- Heavily used in our ISPASS'15 paper Thanks, Andreas Hansson ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Review Request 2710: Correct the endianess detection
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2710/ --- Review request for Default. Repository: gem5 Description --- _BIG_ENDIAN is defined on FreeBSD even on little-endian system Diffs - src/sim/byteswap.hh 8f5993cfa916 Diff: http://reviews.gem5.org/r/2710/diff/ Testing --- done testing compilation on FreeBSD (LE) and Linux (LE) Thanks, Ruslan Bukin ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Review Request 2705: Extend access width for IDE control registers
Hello, can someone review this ? http://reviews.gem5.org/r/2705/ This makes freebsd ATA stack happy, as it want different access-width for two of registers Ruslan ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2710: Correct the endianess detection
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2710/#review5975 --- Thanks! Again, the summary should start with sim : - Andreas Hansson On March 27, 2015, 2 p.m., Ruslan Bukin wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2710/ --- (Updated March 27, 2015, 2 p.m.) Review request for Default. Repository: gem5 Description --- _BIG_ENDIAN is defined on FreeBSD even on little-endian system Diffs - src/sim/byteswap.hh 8f5993cfa916 Diff: http://reviews.gem5.org/r/2710/diff/ Testing --- done testing compilation on FreeBSD (LE) and Linux (LE) Thanks, Ruslan Bukin ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2705: Extend access width for IDE control registers
On March 27, 2015, 2:16 p.m., Andreas Hansson wrote: Looks great. Thanks for the contribution. A few minor things: 1) The summary should start with dev : (see http://gem5.org/Commit_Access for details) 2) Are any regressions affected? (or is this not impacting linux) this is not impact linux - Ruslan --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2705/#review5974 --- On March 25, 2015, 11:10 a.m., Ruslan Bukin wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2705/ --- (Updated March 25, 2015, 11:10 a.m.) Review request for Default. Repository: gem5 Description --- Add 32-bit access width for PrimaryTiming register and 16bit for UDMAControl register as FreeBSD required. Diffs - src/dev/ide_ctrl.cc 8f5993cfa916 Diff: http://reviews.gem5.org/r/2705/diff/ Testing --- Test passed OK booting FreeBSD guest. Thanks, Ruslan Bukin ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2705: Extend access width for IDE control registers
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2705/#review5974 --- Looks great. Thanks for the contribution. A few minor things: 1) The summary should start with dev : (see http://gem5.org/Commit_Access for details) 2) Are any regressions affected? (or is this not impacting linux) - Andreas Hansson On March 25, 2015, 11:10 a.m., Ruslan Bukin wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2705/ --- (Updated March 25, 2015, 11:10 a.m.) Review request for Default. Repository: gem5 Description --- Add 32-bit access width for PrimaryTiming register and 16bit for UDMAControl register as FreeBSD required. Diffs - src/dev/ide_ctrl.cc 8f5993cfa916 Diff: http://reviews.gem5.org/r/2705/diff/ Testing --- Test passed OK booting FreeBSD guest. Thanks, Ruslan Bukin ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2710: Correct the endianess detection
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2710/#review5978 --- Ship it! Ship It! - Ali Saidi On March 27, 2015, 2 p.m., Ruslan Bukin wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2710/ --- (Updated March 27, 2015, 2 p.m.) Review request for Default. Repository: gem5 Description --- _BIG_ENDIAN is defined on FreeBSD even on little-endian system Diffs - src/sim/byteswap.hh 8f5993cfa916 Diff: http://reviews.gem5.org/r/2710/diff/ Testing --- done testing compilation on FreeBSD (LE) and Linux (LE) Thanks, Ruslan Bukin ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2705: Extend access width for IDE control registers
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2705/#review5977 --- Ship it! Thanks for the change! - Ali Saidi On March 25, 2015, 11:10 a.m., Ruslan Bukin wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2705/ --- (Updated March 25, 2015, 11:10 a.m.) Review request for Default. Repository: gem5 Description --- Add 32-bit access width for PrimaryTiming register and 16bit for UDMAControl register as FreeBSD required. Diffs - src/dev/ide_ctrl.cc 8f5993cfa916 Diff: http://reviews.gem5.org/r/2705/diff/ Testing --- Test passed OK booting FreeBSD guest. Thanks, Ruslan Bukin ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2668: config: Support full-system with SST's memory system
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2668/#review5980 --- Looks much nicer. Thanks for the changes! Sorry for the long wait for the review. Nothing big, just could use a couple more comments I think. configs/common/CacheConfig.py http://reviews.gem5.org/r/2668/#comment5218 a comment explaining the need/purpose for this class would be nice configs/common/CacheConfig.py http://reviews.gem5.org/r/2668/#comment5219 please add a comment here explaining that there is an assumption being made on how the external memory system names its ports ext/sst/tests/test6_arm_4c.py http://reviews.gem5.org/r/2668/#comment5217 so does this require you to edit the file to replace /XXX/abs-path-to? couldn't this path be read from an environment variable, or perhaps you could leave it as a relative path so it would work if you ran from the gem5 directory? - Steve Reinhardt On March 3, 2015, 5:07 p.m., Curtis Dunham wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2668/ --- (Updated March 3, 2015, 5:07 p.m.) Review request for Default. Repository: gem5 Description --- Changeset 10709:a3b771cd744c --- config: Support full-system with SST's memory system This patch adds an example configuration in ext/sst/tests/ that allows an SST/gem5 instance to simulate a 4-core AArch64 system with SST's memHierarchy components providing all the caches and memories. Diffs - configs/common/CacheConfig.py 8a20e2a1562debfc20b92be4581457c4147b3733 configs/common/FSConfig.py 8a20e2a1562debfc20b92be4581457c4147b3733 configs/common/MemConfig.py 8a20e2a1562debfc20b92be4581457c4147b3733 configs/common/Options.py 8a20e2a1562debfc20b92be4581457c4147b3733 configs/example/fs.py 8a20e2a1562debfc20b92be4581457c4147b3733 ext/sst/tests/test6_arm_4c.py PRE-CREATION src/dev/arm/RealView.py 8a20e2a1562debfc20b92be4581457c4147b3733 Diff: http://reviews.gem5.org/r/2668/diff/ Testing --- Thanks, Curtis Dunham ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2668: config: Support full-system with SST's memory system
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2668/ --- (Updated March 27, 2015, 10:27 p.m.) Review request for Default. Repository: gem5 Description --- Changeset 10709:a3b771cd744c --- config: Support full-system with SST's memory system This patch adds an example configuration in ext/sst/tests/ that allows an SST/gem5 instance to simulate a 4-core AArch64 system with SST's memHierarchy components providing all the caches and memories. Diffs (updated) - src/dev/arm/RealView.py 8a7285d6197eb0d8f1642e6cdb7a21aa1ff6310e configs/common/MemConfig.py 8a7285d6197eb0d8f1642e6cdb7a21aa1ff6310e configs/common/Options.py 8a7285d6197eb0d8f1642e6cdb7a21aa1ff6310e configs/example/fs.py 8a7285d6197eb0d8f1642e6cdb7a21aa1ff6310e ext/sst/tests/test6_arm_4c.py PRE-CREATION configs/common/CacheConfig.py 8a7285d6197eb0d8f1642e6cdb7a21aa1ff6310e configs/common/FSConfig.py 8a7285d6197eb0d8f1642e6cdb7a21aa1ff6310e Diff: http://reviews.gem5.org/r/2668/diff/ Testing --- Thanks, Curtis Dunham ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2668: config: Support full-system with SST's memory system
On March 27, 2015, 6:28 p.m., Steve Reinhardt wrote: ext/sst/tests/test6_arm_4c.py, line 93 http://reviews.gem5.org/r/2668/diff/5/?file=43877#file43877line93 so does this require you to edit the file to replace /XXX/abs-path-to? couldn't this path be read from an environment variable, or perhaps you could leave it as a relative path so it would work if you ran from the gem5 directory? Yes, it does. It can work as relative; I will change it to that. - Curtis --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2668/#review5980 --- On March 27, 2015, 10:27 p.m., Curtis Dunham wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2668/ --- (Updated March 27, 2015, 10:27 p.m.) Review request for Default. Repository: gem5 Description --- Changeset 10709:a3b771cd744c --- config: Support full-system with SST's memory system This patch adds an example configuration in ext/sst/tests/ that allows an SST/gem5 instance to simulate a 4-core AArch64 system with SST's memHierarchy components providing all the caches and memories. Diffs - src/dev/arm/RealView.py 8a7285d6197eb0d8f1642e6cdb7a21aa1ff6310e configs/common/MemConfig.py 8a7285d6197eb0d8f1642e6cdb7a21aa1ff6310e configs/common/Options.py 8a7285d6197eb0d8f1642e6cdb7a21aa1ff6310e configs/example/fs.py 8a7285d6197eb0d8f1642e6cdb7a21aa1ff6310e ext/sst/tests/test6_arm_4c.py PRE-CREATION configs/common/CacheConfig.py 8a7285d6197eb0d8f1642e6cdb7a21aa1ff6310e configs/common/FSConfig.py 8a7285d6197eb0d8f1642e6cdb7a21aa1ff6310e Diff: http://reviews.gem5.org/r/2668/diff/ Testing --- Thanks, Curtis Dunham ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
