[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: be prepared for CSR changes during PT walk.
Nils Asmussen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28447 )
Change subject: arch-riscv: be prepared for CSR changes during PT walk.
..
arch-riscv: be prepared for CSR changes during PT walk.
If the address space is changed (by writing to SATP), it can happen that
a page table walk is in progress. Previously, this failed if the ASID
changed, because we then used the wrong ASID for the lookup.
This commit makes sure that we don't access CSRs after the beginning of
the walk by loading SATP, STATUS, and PRV at the beginning.
Change-Id: I8c184c7ae7dd44d78e881bb5ec8d430dd480849c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28447
Maintainer: Bobby R. Bruce
Reviewed-by: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/riscv/pagetable_walker.cc
M src/arch/riscv/pagetable_walker.hh
M src/arch/riscv/tlb.cc
M src/arch/riscv/tlb.hh
4 files changed, 33 insertions(+), 17 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/pagetable_walker.cc
b/src/arch/riscv/pagetable_walker.cc
index 02d2d94..6ec118d 100644
--- a/src/arch/riscv/pagetable_walker.cc
+++ b/src/arch/riscv/pagetable_walker.cc
@@ -184,6 +184,11 @@
tc = _tc;
mode = _mode;
timing = _isTiming;
+// fetch these now in case they change during the walk
+status = tc->readMiscReg(MISCREG_STATUS);
+pmode = walker->tlb->getMemPriv(tc, mode);
+satp = tc->readMiscReg(MISCREG_SATP);
+assert(satp.mode == AddrXlateMode::SV39);
}
void
@@ -303,7 +308,8 @@
if (pte.r || pte.x) {
// step 5: leaf PTE
doEndWalk = true;
-fault = walker->tlb->checkPermissions(tc, entry.vaddr, mode,
pte);
+fault = walker->tlb->checkPermissions(status, pmode,
+ entry.vaddr, mode, pte);
// step 6
if (fault == NoFault) {
@@ -413,10 +419,7 @@
void
Walker::WalkerState::setupWalk(Addr vaddr)
{
-vaddr &= ((static_cast(1) << VADDR_BITS) - 1);
-
-SATP satp = tc->readMiscReg(MISCREG_SATP);
-assert(satp.mode == AddrXlateMode::SV39);
+vaddr &= (static_cast(1) << VADDR_BITS) - 1;
Addr shift = PageShift + LEVEL_BITS * 2;
Addr idx = (vaddr >> shift) & LEVEL_MASK;
@@ -483,12 +486,12 @@
* permissions violations, so we'll need the return value as
* well.
*/
-bool delayedResponse;
-Fault fault = walker->tlb->doTranslate(req, tc, NULL, mode,
- delayedResponse);
-assert(!delayedResponse);
+Addr vaddr = req->getVaddr();
+vaddr &= (static_cast(1) << VADDR_BITS) - 1;
+Addr paddr = walker->tlb->translateWithTLB(vaddr, satp.asid,
mode);
+req->setPaddr(paddr);
// Let the CPU continue.
-translation->finish(fault, req, tc, mode);
+translation->finish(NoFault, req, tc, mode);
} else {
// There was a fault during the walk. Let the CPU know.
translation->finish(timingFault, req, tc, mode);
diff --git a/src/arch/riscv/pagetable_walker.hh
b/src/arch/riscv/pagetable_walker.hh
index 2d50928..60826a0 100644
--- a/src/arch/riscv/pagetable_walker.hh
+++ b/src/arch/riscv/pagetable_walker.hh
@@ -100,6 +100,9 @@
Fault timingFault;
TLB::Translation * translation;
BaseTLB::Mode mode;
+SATP satp;
+STATUS status;
+PrivilegeMode pmode;
bool functional;
bool timing;
bool retrying;
diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index 294d73f..c8b1a4c 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -213,7 +213,8 @@
}
Fault
-TLB::checkPermissions(ThreadContext *tc, Addr vaddr, Mode mode, PTESv39
pte)
+TLB::checkPermissions(STATUS status, PrivilegeMode pmode, Addr vaddr,
+ Mode mode, PTESv39 pte)
{
Fault fault = NoFault;
@@ -232,8 +233,6 @@
if (fault == NoFault) {
// check pte.u
-STATUS status = tc->readMiscReg(MISCREG_STATUS);
-PrivilegeMode pmode = getMemPriv(tc, mode);
if (pmode == PrivilegeMode::PRV_U && !pte.u) {
DPRINTF(TLB, "PTE is not user accessible, raising PF\n");
fault = createPagefault(vaddr, mode);
@@ -260,6 +259,14 @@
return std::make_shared(vaddr, code);
}
+Addr
+TLB::translateWithTLB(Addr vaddr, uint16_t asid, Mode mode)
+{
+TlbEntry *e = lookup(vaddr, asid, mode, false);
+assert(e != nullptr);
+return e->paddr << PageShift | (vaddr & mask(e->logBytes));
+}
+
Fault
TLB::doTranslate(const RequestPtr , ThreadContext *tc,
Translation
[gem5-dev] Change in gem5/gem5[develop]: misc: added news on RISC-V to RELEASE-NOTES.md.
Nils Asmussen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/28448 ) Change subject: misc: added news on RISC-V to RELEASE-NOTES.md. .. misc: added news on RISC-V to RELEASE-NOTES.md. Change-Id: I9b60cd2f533e6d4ce677e8a9b7bb5a5698e51c61 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28448 Maintainer: Bobby R. Bruce Reviewed-by: Jason Lowe-Power Tested-by: kokoro --- M RELEASE-NOTES.md 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved Bobby R. Bruce: Looks good to me, approved kokoro: Regressions pass diff --git a/RELEASE-NOTES.md b/RELEASE-NOTES.md index 1a679dd..6f80906 100644 --- a/RELEASE-NOTES.md +++ b/RELEASE-NOTES.md @@ -8,3 +8,4 @@ * The m5 utility has been revamped with a new build system based on scons, tests, and updated and more consistent feature support. * Robust support for marshalling data from a function call inside the simulation to a function within gem5 using a predefined set of rules. * Workload configuration pulled out into its own object, simplifying the System object and making workload configuration more modular and flexible. +* Sv39 paging has been added to the RISC-V ISA, bringing gem5 close to running Linux on RISC-V. -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28448 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I9b60cd2f533e6d4ce677e8a9b7bb5a5698e51c61 Gerrit-Change-Number: 28448 Gerrit-PatchSet: 2 Gerrit-Owner: Nils Asmussen Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nils Asmussen Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix MESI_Three_Level erroneous transition
Pouya Fotouhi has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28047 )
Change subject: mem-ruby: fix MESI_Three_Level erroneous transition
..
mem-ruby: fix MESI_Three_Level erroneous transition
The MESI_Three_Level protocol includes a transition in its L1
definition to invalidate an SM state but this transition does
not notify the L0 cache. The unintended side effect of this
allows stale values to be read by the L0 cache. This can cause
incorrect behaviour when executing LL/SC based mutexes. This
patch ensures that all invalidates to SM states are exposed to
the L0 cache.
Change-Id: I7fefabdaa8027fdfa4c9c362abd7e467493196aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28047
Reviewed-by: John Alsop
Reviewed-by: Pouya Fotouhi
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
1 file changed, 3 insertions(+), 2 deletions(-)
Approvals:
Pouya Fotouhi: Looks good to me, approved
John Alsop: Looks good to me, but someone else must approve
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
b/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
index 00d897a..1890bcc 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
@@ -262,7 +262,8 @@
}
bool inL0Cache(State state) {
-if (state == State:S || state == State:E || state == State:M ||
+if (state == State:S || state == State:E ||
+state == State:M || state == State:SM ||
state == State:S_IL0 || state == State:E_IL0 ||
state == State:M_IL0 || state == State:SM_IL0) {
return true;
@@ -996,7 +997,7 @@
}
// Transitions from IM
- transition({IM,SM}, Inv, IM) {
+ transition(IM, Inv, IM) {
fi_sendInvAck;
l_popL2RequestQueue;
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28047
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7fefabdaa8027fdfa4c9c362abd7e467493196aa
Gerrit-Change-Number: 28047
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: John Alsop
Gerrit-Reviewer: Marjan Fariborz
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Pouya Fotouhi
Gerrit-Reviewer: Timothy Hayes
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests: Update tests to save output on failure
Jason Lowe-Power has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19529 )
Change subject: tests: Update tests to save output on failure
..
tests: Update tests to save output on failure
The previous commit which tried to do this, did not work with parallel
execution. In this case, the fixtures that were modified were in the
child process and the parent process's fixtures were never updated.
Instead of modifying the object, use the information passed in from the
testlib.
See 4c28149ffa5d09e6fe14952dcaf8df5d0cd8f328
Previous review:
https://gem5-review.googlesource.com/c/public/gem5/+/17451
Change-Id: Ib4c06c5e3f82994199d6f0c1fa69452e93444d75
Signed-off-by: Jason Lowe-Power
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19529
Reviewed-by: Bobby R. Bruce
Reviewed-by: Nikos Nikoleris
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M tests/gem5/fixture.py
M tests/gem5/verifier.py
2 files changed, 2 insertions(+), 17 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/tests/gem5/fixture.py b/tests/gem5/fixture.py
index aa316e7..fc31b30 100644
--- a/tests/gem5/fixture.py
+++ b/tests/gem5/fixture.py
@@ -49,6 +49,7 @@
from testlib.config import config, constants
from testlib.helper import log_call, cacheresult, joinpath, absdirpath
import testlib.log as log
+from testlib.state import Result
class VariableFixture(Fixture):
@@ -67,13 +68,9 @@
self.path = tempfile.mkdtemp(prefix='gem5out')
def teardown(self, testitem):
-if self.path is not None:
+if testitem.result == Result.Passed:
shutil.rmtree(self.path)
-def skip_cleanup(self):
-# Set path to none so it's not deleted
-self.path = None
-
class UniqueFixture(Fixture):
'''
Base class for fixtures that generate a target in the
diff --git a/tests/gem5/verifier.py b/tests/gem5/verifier.py
index 73a7499..c955c40 100644
--- a/tests/gem5/verifier.py
+++ b/tests/gem5/verifier.py
@@ -47,16 +47,6 @@
return test.TestFunction(self._test,
name=name, fixtures=self.fixtures)
-def failed(self, fixtures):
-'''
-Called if this verifier fails to cleanup (or not) as needed.
-'''
-try:
-fixtures[constants.tempdir_fixture_name].skip_cleanup()
-except KeyError:
-pass # No need to do anything if the tempdir fixture doesn't
exist
-
-
class MatchGoldStandard(Verifier):
'''
Compares a standard output to the test output and passes if they match,
@@ -90,7 +80,6 @@
ignore_regexes=self.ignore_regex,
logger=params.log)
if diff is not None:
-self.failed(fixtures)
test.fail('Stdout did not match:\n%s\nSee %s for full results'
% (diff, tempdir))
@@ -195,7 +184,6 @@
if parse_file(joinpath(tempdir,
constants.gem5_simulation_stderr)):
return # Success
-self.failed(fixtures)
test.fail('Could not match regex.')
_re_type = type(re.compile(''))
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib4c06c5e3f82994199d6f0c1fa69452e93444d75
Gerrit-Change-Number: 19529
Gerrit-PatchSet: 4
Gerrit-Owner: Jason Lowe-Power
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: ext: Fix tmpfiles in testlib
Jason Lowe-Power has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19528 )
Change subject: ext: Fix tmpfiles in testlib
..
ext: Fix tmpfiles in testlib
Previously, the testlib would generate and not clean up 100s of
temporary files in /tmp. This puts all of the tempfiles in the same
directory to make sure they are cleaned up on a successful test.
Change-Id: If4dcd93ab4b5df556c046753266a71365d1388c1
Signed-off-by: Jason Lowe-Power
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19528
Reviewed-by: Bobby R. Bruce
Reviewed-by: Nikos Nikoleris
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M ext/testlib/helper.py
1 file changed, 6 insertions(+), 6 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/ext/testlib/helper.py b/ext/testlib/helper.py
index 18256ea..ac49e46 100644
--- a/ext/testlib/helper.py
+++ b/ext/testlib/helper.py
@@ -390,13 +390,13 @@
os.chown(target, st[stat.ST_UID], st[stat.ST_GID])
-def _filter_file_inplace(fname, filters):
+def _filter_file_inplace(fname, dir, filters):
'''
Filter the given file writing filtered lines out to a temporary file,
then
copy that tempfile back into the original file.
'''
reenter = False
-(_, tfname) = tempfile.mkstemp(text=True)
+(_, tfname) = tempfile.mkstemp(dir=dir, text=True)
with open(tfname, 'w') as tempfile_:
for line in _filter_file(fname, filters):
tempfile_.write(line)
@@ -414,11 +414,11 @@
if not os.path.exists(out_file):
raise OSError("%s doesn't exist in output directory" % out_file)
-_filter_file_inplace(out_file, ignore_regexes)
-_filter_file_inplace(ref_file, ignore_regexes)
+_filter_file_inplace(out_file, os.path.dirname(out_file),
ignore_regexes)
+_filter_file_inplace(ref_file, os.path.dirname(out_file),
ignore_regexes)
#try :
-(_, tfname) = tempfile.mkstemp(text=True)
+(_, tfname) = tempfile.mkstemp(dir=os.path.dirname(out_file),
text=True)
with open(tfname, 'r+') as tempfile_:
try:
log_call(logger, ['diff', out_file, ref_file],
stdout=tempfile_)
@@ -457,4 +457,4 @@
@staticmethod
def timestamp():
-return time.time()
\ No newline at end of file
+return time.time()
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If4dcd93ab4b5df556c046753266a71365d1388c1
Gerrit-Change-Number: 19528
Gerrit-PatchSet: 9
Gerrit-Owner: Jason Lowe-Power
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch-x86,cpu: Fix bpred by annotating branch instructions in x86
Jason Lowe-Power has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27972 )
Change subject: arch-x86,cpu: Fix bpred by annotating branch instructions
in x86
..
arch-x86,cpu: Fix bpred by annotating branch instructions in x86
Original Creator: Adria Armejach.
Branch instructions needed to be annotated in x86 as direct/indirect and
conditional/unconditional. These annotations where not present causing the
branch predictor to misbehave, not using the BTB. In addition, logic to
determine the real branch target at decode needed to be added as it was
also missing.
Change-Id: I91e707452c1825b9bb4ae75c3f599da489ae5b9a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27972
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/x86/isa/insts/general_purpose/control_transfer/call.py
M
src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
M src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py
M src/arch/x86/isa/insts/general_purpose/control_transfer/loop.py
M src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
M src/arch/x86/isa/macroop.isa
M src/arch/x86/isa/microops/regop.isa
M src/arch/x86/isa/microops/seqop.isa
M src/cpu/o3/decode_impl.hh
9 files changed, 113 insertions(+), 6 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git
a/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py
b/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py
index c58152c..edc0007 100644
--- a/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py
+++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py
@@ -41,6 +41,7 @@
# Make the default data size of calls 64 bits in 64 bit mode
.adjust_env oszIn64Override
.function_call
+.control_direct
limm t1, imm
rdip t7
@@ -55,6 +56,7 @@
# Make the default data size of calls 64 bits in 64 bit mode
.adjust_env oszIn64Override
.function_call
+.control_indirect
rdip t1
# Check target of call
@@ -68,6 +70,7 @@
# Make the default data size of calls 64 bits in 64 bit mode
.adjust_env oszIn64Override
.function_call
+.control_indirect
rdip t7
ld t1, seg, sib, disp
@@ -82,6 +85,7 @@
# Make the default data size of calls 64 bits in 64 bit mode
.adjust_env oszIn64Override
.function_call
+.control_indirect
rdip t7
ld t1, seg, riprel, disp
diff --git
a/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
b/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
index 87b2e6a..f92935d 100644
---
a/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
+++
b/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
@@ -40,6 +40,7 @@
{
# Make the defualt data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+.control_direct
rdip t1
limm t2, imm
@@ -50,6 +51,7 @@
{
# Make the defualt data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+.control_direct
rdip t1
limm t2, imm
@@ -60,6 +62,7 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+.control_direct
rdip t1
limm t2, imm
@@ -70,6 +73,7 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+.control_direct
rdip t1
limm t2, imm
@@ -80,6 +84,7 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+.control_direct
rdip t1
limm t2, imm
@@ -90,6 +95,7 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+.control_direct
rdip t1
limm t2, imm
@@ -100,6 +106,7 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+.control_direct
rdip t1
limm t2, imm
@@ -110,6 +117,7 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+.control_direct
rdip t1
limm t2, imm
@@ -120,6 +128,7 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+.control_direct
rdip t1
limm t2, imm
@@ -130,6 +139,7 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+.control_direct
rdip t1
limm t2, imm
@@ -140,6 +150,7 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+.control_direct
rdip t1
limm t2, imm
@@ -150,6 +161,7 @@
{
# Make the default data size of jumps 64 bits
[gem5-dev] Change in gem5/gem5[develop]: scons: Build the marshal binary in a bare minimum environment
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28428 )
Change subject: scons: Build the marshal binary in a bare minimum
environment
..
scons: Build the marshal binary in a bare minimum environment
This change adds an additional bare minimum environment that includes
python only and changes the marshal binary to compile using it.
Change-Id: Id5d1ee6899796d746d8dc1a004cfe4795f040c55
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28428
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M SConstruct
M src/SConscript
2 files changed, 10 insertions(+), 7 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index 3345148..ba4affa 100755
--- a/SConstruct
+++ b/SConstruct
@@ -709,6 +709,10 @@
if not conf.CheckLib(lib):
error("Can't find library %s required by python." % lib)
+main.Prepend(CPPPATH=Dir('ext/pybind11/include/'))
+# Bare minimum environment that only includes python
+base_py_env = main.Clone()
+
# On Solaris you need to use libsocket for socket ops
if not
conf.CheckLibWithHeader(None, 'sys/socket.h', 'C++', 'accept(0,0,0);'):
if not conf.CheckLibWithHeader('socket', 'sys/socket.h',
@@ -1100,8 +1104,6 @@
gdb_xml_dir = joinpath(ext_dir, 'gdb-xml')
Export('gdb_xml_dir')
-main.Prepend(CPPPATH=Dir('ext/pybind11/include/'))
-
###
#
# This builder and wrapper method are used to set up a directory with
@@ -1259,7 +1261,8 @@
# The src/SConscript file sets up the build rules in 'env' according
# to the configured variables. It returns a list of environments,
# one for each variant build (debug, opt, etc.)
-SConscript('src/SConscript', variant_dir = variant_path, exports
= 'env')
+SConscript('src/SConscript', variant_dir=variant_path,
+ exports=['env', 'base_py_env'])
# base help text
Help('''
diff --git a/src/SConscript b/src/SConscript
index c7251fc..134e2a5 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1,6 +1,6 @@
# -*- mode:python -*-
-# Copyright (c) 2018 ARM Limited
+# Copyright (c) 2018, 2020 ARM Limited
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
@@ -1140,7 +1140,7 @@
# Build a small helper that marshals the Python code using the same
# version of Python as gem5. This is in an unorthodox location to
# avoid building it for every variant.
-py_marshal = env.Program('marshal', 'python/marshal.cc')[0]
+py_marshal = base_py_env.Program('marshal', 'python/marshal.cc')[0]
# Embed python files. All .py files that have been indicated by a
# PySource() call in a SConscript need to be embedded into the M5
@@ -1196,8 +1196,8 @@
code.write(str(target[0]))
for source in PySource.all:
-env.Command(source.cpp, [ py_marshal, source.tnode ],
-MakeAction(embedPyFile, Transform("EMBED PY")))
+base_py_env.Command(source.cpp, [ py_marshal, source.tnode ],
+MakeAction(embedPyFile, Transform("EMBED PY")))
Source(source.cpp, tags=source.tags, add_tags='python')
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id5d1ee6899796d746d8dc1a004cfe4795f040c55
Gerrit-Change-Number: 28428
Gerrit-PatchSet: 2
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Re: m5 utility patch series
Hey Gabe, Quick follow up: It looks like the most controversial part of this change (at least to me) the conversion to scons from make has already been committed. So, I guess it makes sense to merge this as is and just focus on documentation over the next couple of weeks. The chain is still *very* long though, and there are some commit that you say "I haven't really tested this" ( https://gem5-review.googlesource.com/c/public/gem5/+/27788/8). Where should we be cutting this off for gem5-20? Can you let us know what we should be spending our next few hours looking at? We're working hard to make gem5-20 a truly *stable* release. I would like to make sure that there aren't half implemented changes in this release. Having features that are broken or only partially working makes gem5 much harder for people in the community to use it. Thanks, Jason On Fri, May 1, 2020 at 9:51 AM Jason Lowe-Power wrote: > Hey Gabe, > > Sorry for not getting to this until now. To be honest, I was a little > intimidated by the size of the changes, and it's hard to find the block of > time needed to review all of this. > > Next time, I think it would be easier for everyone if we had a discussion > about design first, and then started on the code. I'd like to have a > conversation about the high-level design, but, at this point, after you've > written all of this code, it wouldn't be fair to you to ask you to re-write > everything. At the same time, I'm not sure that it's fair to the rest of > the community to ask them to accept your changes without a design review. > > I'm trying to at least understand how to use this from a > user's perspective. I'll document what I've done to help others if they > want to pick this up. > 1. How do I build m5 now? > 1a. I guessed that I run "scons" in util/m5 (which is not what I would > have done, and I can't find it documented anywhere. I doubt other gem5 > users would know to do this.) > 1b. I get the error "sh: arm-linux-gnueabihf-g++: command not found" Does > this mean an ARM cross compiler is *required* to build the m5 command? > 2. Aha! You can use crazy scons magic to build the x86/ directory (I hate > scons) > 2a. Now I get the error "build/x86/java/gem5_Ops.h:2:10: fatal error: > jni.h: No such file or directory". I guess that's not surprising since I > don't have java dev installed. Can I build without java? How? > 2b. I'm not sure what the target should be if I don't want the java > bindings. > 2c. I tried build/x86/m5 (nope). I tried build/x86/command/m5 (nope). > 3. Oh wait, I found it! It was in the current directory, not in build.. > weird. What would happen if I wanted the arm version? Would it overwrite > the x86? > 3a. nevermind, that was the old binary, lol. > *3b. I can't seem to figure this out.* > 4. There seems to be a libm5... I wonder how to get that to compile... > 4a. Like the m5 binary, I tried a number of different names and locations, > but scons wouldn't build anything. > > I guess I'm stuck here. I've spent almost an hour on this, and if *I* > can't figure this out with 10 years of gem5 experience, I'm worried that > others also won't be able to figure out the new m5. We really need more > documentation before we can merge. I see from the previous email that you > explained things in commit messages, but our users can't be expected to > read 50+ commit messages to figure this out. > > I'd like to hear from the community how much we want to push this into > gem5-20. > > While I'm very excited to see the m5 utility updated, I'm afraid that > without more documentation we're going to be hurting most of our users. If > we *do* rush the reviews today and get this into the staging branch we > would need the following documentation by the gem5-20 release: > 1. How to build > - What is the command > - Where is the output > - What are the outputs > - What are the options > - How to make changes > 2. How to use the new m5 utility in FS mode > - What are the options > - What is required to get it onto a disk image > - What are the new features > - How you need to change your current scripts to work with the new binary > 3. How to use it with benchmarks > - How do you link to it > - (If there are any changes) how do you interact with the library (e.g., > what are the functions avaiable) > - (If there are any changes) how do you change the code that uses the > current version of the m5 utility to use the new one > 4. How do you configure things to choose between magic instructions and > addresses (mmio)? > > There's probably more we need, but that's what I can think of right now. > > So, Gabe, what do you think? Should we push to get this into gem5-20? What > do others think? To everyone that uses the m5 magic instructions (or > whatever we want to call them) have you had enough time to look at these > changes and understand what you'll need to do to change your code? > > Thanks, > Jason > > > On Wed, Apr 8, 2020 at 10:25 PM Gabe Black wrote: >
[gem5-dev] Change in gem5/gem5[master]: tests,python: Upgrading testlib to function with Python3
Hello Bobby R. Bruce,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28527
to review the following change.
Change subject: tests,python: Upgrading testlib to function with Python3
..
tests,python: Upgrading testlib to function with Python3
Change-Id: I9926b1507e9069ae8564c31bdd377b2b916462a2
Issue-on: https://gem5.atlassian.net/browse/GEM5-395
---
M ext/testlib/__init__.py
M ext/testlib/config.py
M ext/testlib/handlers.py
M ext/testlib/helper.py
M ext/testlib/loader.py
M ext/testlib/log.py
M ext/testlib/result.py
M ext/testlib/runner.py
M ext/testlib/terminal.py
R ext/testlib/test_util.py
M tests/gem5/verifier.py
M tests/main.py
12 files changed, 44 insertions(+), 33 deletions(-)
diff --git a/ext/testlib/__init__.py b/ext/testlib/__init__.py
index 893da54..8dec78e 100644
--- a/ext/testlib/__init__.py
+++ b/ext/testlib/__init__.py
@@ -29,7 +29,7 @@
from .state import *
from .runner import *
-from .test import *
+from .test_util import *
from .suite import *
from .loader import *
from .fixture import *
diff --git a/ext/testlib/config.py b/ext/testlib/config.py
index 643ef68..ec89df4 100644
--- a/ext/testlib/config.py
+++ b/ext/testlib/config.py
@@ -83,7 +83,8 @@
import os
import re
-from ConfigParser import ConfigParser
+
+from six.moves import configparser as ConfigParser
from pickle import HIGHEST_PROTOCOL as highest_pickle_protocol
from helper import absdirpath, AttrDict, FrozenAttrDict
diff --git a/ext/testlib/handlers.py b/ext/testlib/handlers.py
index 6f76940..1cd511a 100644
--- a/ext/testlib/handlers.py
+++ b/ext/testlib/handlers.py
@@ -35,7 +35,6 @@
import multiprocessing
import os
-import Queue
import sys
import threading
import time
@@ -45,9 +44,10 @@
import log
import result
import state
-import test
+import test_util as test
import terminal
+from six.moves import queue as Queue
from config import config, constants
diff --git a/ext/testlib/helper.py b/ext/testlib/helper.py
index 18256ea..ae457e4 100644
--- a/ext/testlib/helper.py
+++ b/ext/testlib/helper.py
@@ -34,7 +34,6 @@
import difflib
import errno
import os
-import Queue
import re
import shutil
import stat
@@ -43,6 +42,9 @@
import threading
import time
import traceback
+#import six
+
+from six.moves import queue as Queue
#TODO Tear out duplicate logic from the sandbox IOManager
def log_call(logger, command, *popenargs, **kwargs):
@@ -457,4 +459,4 @@
@staticmethod
def timestamp():
-return time.time()
\ No newline at end of file
+return time.time()
diff --git a/ext/testlib/loader.py b/ext/testlib/loader.py
index 8f8f60e..bc979db 100644
--- a/ext/testlib/loader.py
+++ b/ext/testlib/loader.py
@@ -73,7 +73,7 @@
import config
import log
import suite as suite_mod
-import test as test_mod
+import test_util as test_mod
import fixture as fixture_mod
import wrappers
import uid
@@ -108,11 +108,12 @@
return os.path.split(os.path.dirname(os.path.abspath((filepath[-1]
def _assert_files_in_same_dir(files):
-if __debug__:
-if files:
-directory = os.path.dirname(files[0])
-for f in files:
-assert os.path.dirname(f) == directory
+pass
+#if __debug__:
+#if files:
+#directory = os.path.dirname(files[0])
+#for f in files:
+#assert os.path.dirname(f) == directory
class Loader(object):
'''
diff --git a/ext/testlib/log.py b/ext/testlib/log.py
index 5ba6f5d..bd78c6b 100644
--- a/ext/testlib/log.py
+++ b/ext/testlib/log.py
@@ -64,13 +64,16 @@
'''
__metaclass__ = RecordTypeCounterMetaclass
+type_id = None
+
def __init__(self, **data):
self.data = data
def __getitem__(self, item):
if item not in self.data:
-raise KeyError('%s not in record %s' %\
-(item, self.__class__.__name__))
+self.data[item] = ""
+#raise KeyError('%s not in record %s' %\
+#(item, self.__class__.__name__))
return self.data[item]
def __str__(self):
diff --git a/ext/testlib/result.py b/ext/testlib/result.py
index 22c0248..d281283 100644
--- a/ext/testlib/result.py
+++ b/ext/testlib/result.py
@@ -62,7 +62,7 @@
return self._metadata.result.value != state.Result.Passed
-class InternalTestResult(object, _CommonMetadataMixin):
+class InternalTestResult(_CommonMetadataMixin):
def __init__(self, obj, suite, directory):
self._metadata = obj.metadata
self.suite = suite
@@ -77,7 +77,7 @@
)
-class InternalSuiteResult(object, _CommonMetadataMixin):
+class InternalSuiteResult(_CommonMetadataMixin):
def __init__(self, obj, directory):
self._metadata = obj.metadata
self.directory = directory
@@ -104,7 +104,7 @@
return results
-class InternalLibraryResults(object,
[gem5-dev] Change in gem5/gem5[develop]: tests: update linux boot tests
Ayaz Akram has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28427 )
Change subject: tests: update linux boot tests
..
tests: update linux boot tests
This change updates the config scripts used by linux boot
tests to make them compatible with change that deprecated
LinuxX86System
JIRA: https://gem5.atlassian.net/browse/GEM5-440
Change-Id: I04beff2915c03a2c3a774351edbba60d7ff26867
Signed-off-by: Ayaz Akram
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28427
Maintainer: Bobby R. Bruce
Maintainer: Jason Lowe-Power
Reviewed-by: Jason Lowe-Power
Tested-by: kokoro
---
M tests/gem5/x86-boot-tests/run_exit.py
M tests/gem5/x86-boot-tests/system/system.py
2 files changed, 9 insertions(+), 8 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/tests/gem5/x86-boot-tests/run_exit.py
b/tests/gem5/x86-boot-tests/run_exit.py
index 24edcc5..ecb3a84 100644
--- a/tests/gem5/x86-boot-tests/run_exit.py
+++ b/tests/gem5/x86-boot-tests/run_exit.py
@@ -51,7 +51,7 @@
if args.boot_type == "init":
# Simply run "exit.sh"
-system.boot_osflags += ' init=/root/exit.sh'
+system.workload.command_line += ' init=/root/exit.sh'
else:
if args.boot_type != "systemd":
m5.fatal("Bad option for boot_type. init or systemd.")
diff --git a/tests/gem5/x86-boot-tests/system/system.py
b/tests/gem5/x86-boot-tests/system/system.py
index 0b69be9..c55664e 100755
--- a/tests/gem5/x86-boot-tests/system/system.py
+++ b/tests/gem5/x86-boot-tests/system/system.py
@@ -30,11 +30,12 @@
from caches import *
import sys
-class MySystem(LinuxX86System):
+class MySystem(System):
def __init__(self, kernel, disk, cpu_type, num_cpus):
super(MySystem, self).__init__()
+self.workload = X86FsLinux()
self._host_parallel = cpu_type == "kvm"
# Set up the clock domain and the voltage domain
@@ -63,12 +64,12 @@
self.setDiskImages(disk, disk)
# Change this path to point to the kernel you want to use
-self.kernel = kernel
+self.workload.object_file = kernel
# Options specified on the kernel command line
boot_options =
['earlyprintk=ttyS0', 'console=ttyS0', 'lpj=723',
'root=/dev/hda1']
-self.boot_osflags = ' '.join(boot_options)
+self.workload.command_line = ' '.join(boot_options)
# Create the CPUs for our system.
self.createCPU(cpu_type, num_cpus)
@@ -235,7 +236,7 @@
###
# Add in a Bios information structure.
-self.smbios_table.structures = [X86SMBiosBiosInformation()]
+self.workload.smbios_table.structures =
[X86SMBiosBiosInformation()]
# Set up the Intel MP table
base_entries = []
@@ -293,8 +294,8 @@
assignISAInt(1, 1)
for i in range(3, 15):
assignISAInt(i, i)
-self.intel_mp_table.base_entries = base_entries
-self.intel_mp_table.ext_entries = ext_entries
+self.workload.intel_mp_table.base_entries = base_entries
+self.workload.intel_mp_table.ext_entries = ext_entries
entries = \
[
@@ -311,7 +312,7 @@
entries.append(X86E820Entry(addr = 0x, size = '64kB',
range_type=2))
-self.e820_table.entries = entries
+self.workload.e820_table.entries = entries
class CowDisk(IdeDisk):
def __init__(self, filename):
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28427
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I04beff2915c03a2c3a774351edbba60d7ff26867
Gerrit-Change-Number: 28427
Gerrit-PatchSet: 3
Gerrit-Owner: Ayaz Akram
Gerrit-Reviewer: Ayaz Akram
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Re: m5 utility patch series
Hey Gabe,
Sorry for not getting to this until now. To be honest, I was a little
intimidated by the size of the changes, and it's hard to find the block of
time needed to review all of this.
Next time, I think it would be easier for everyone if we had a discussion
about design first, and then started on the code. I'd like to have a
conversation about the high-level design, but, at this point, after you've
written all of this code, it wouldn't be fair to you to ask you to re-write
everything. At the same time, I'm not sure that it's fair to the rest of
the community to ask them to accept your changes without a design review.
I'm trying to at least understand how to use this from a
user's perspective. I'll document what I've done to help others if they
want to pick this up.
1. How do I build m5 now?
1a. I guessed that I run "scons" in util/m5 (which is not what I would have
done, and I can't find it documented anywhere. I doubt other gem5 users
would know to do this.)
1b. I get the error "sh: arm-linux-gnueabihf-g++: command not found" Does
this mean an ARM cross compiler is *required* to build the m5 command?
2. Aha! You can use crazy scons magic to build the x86/ directory (I hate
scons)
2a. Now I get the error "build/x86/java/gem5_Ops.h:2:10: fatal error:
jni.h: No such file or directory". I guess that's not surprising since I
don't have java dev installed. Can I build without java? How?
2b. I'm not sure what the target should be if I don't want the java
bindings.
2c. I tried build/x86/m5 (nope). I tried build/x86/command/m5 (nope).
3. Oh wait, I found it! It was in the current directory, not in build..
weird. What would happen if I wanted the arm version? Would it overwrite
the x86?
3a. nevermind, that was the old binary, lol.
*3b. I can't seem to figure this out.*
4. There seems to be a libm5... I wonder how to get that to compile...
4a. Like the m5 binary, I tried a number of different names and locations,
but scons wouldn't build anything.
I guess I'm stuck here. I've spent almost an hour on this, and if *I* can't
figure this out with 10 years of gem5 experience, I'm worried that others
also won't be able to figure out the new m5. We really need more
documentation before we can merge. I see from the previous email that you
explained things in commit messages, but our users can't be expected to
read 50+ commit messages to figure this out.
I'd like to hear from the community how much we want to push this into
gem5-20.
While I'm very excited to see the m5 utility updated, I'm afraid that
without more documentation we're going to be hurting most of our users. If
we *do* rush the reviews today and get this into the staging branch we
would need the following documentation by the gem5-20 release:
1. How to build
- What is the command
- Where is the output
- What are the outputs
- What are the options
- How to make changes
2. How to use the new m5 utility in FS mode
- What are the options
- What is required to get it onto a disk image
- What are the new features
- How you need to change your current scripts to work with the new binary
3. How to use it with benchmarks
- How do you link to it
- (If there are any changes) how do you interact with the library (e.g.,
what are the functions avaiable)
- (If there are any changes) how do you change the code that uses the
current version of the m5 utility to use the new one
4. How do you configure things to choose between magic instructions and
addresses (mmio)?
There's probably more we need, but that's what I can think of right now.
So, Gabe, what do you think? Should we push to get this into gem5-20? What
do others think? To everyone that uses the m5 magic instructions (or
whatever we want to call them) have you had enough time to look at these
changes and understand what you'll need to do to change your code?
Thanks,
Jason
On Wed, Apr 8, 2020 at 10:25 PM Gabe Black wrote:
>
>
> On Wed, Apr 8, 2020 at 5:39 PM Jason Lowe-Power
> wrote:
>
>> Hey Gabe,
>>
>> I still don't feel like this gives me enough context to do a good job
>> reviewing these changesets. For instance, before, I would go to util/m5 and
>> run `make -f Makefile.` to create the m5 utility. What is the new
>> process? It seems to be done with scons? Where is the binary created when
>> you build it? What binaries can be built? There's *a lot* changing here,
>> and I'd like to understand things from a high level before digging into the
>> details of the code.
>>
>> To be more specific, what I would like to see is 1) a list of the major
>> changes, and 2) what the new interface is for each of the changes. For
>> instance:
>> - These changesets update the m5 utility to be built with scons instead
>> of make. Now, you run `` to build m5.
>>
>
> scons build/{version you want}, ie scons build/aarch64, or scons build/x86
>
> The build outputs are in build/{version}/out, and are called the same
> things as before. If you have all the cross compilers set up (what you'd
>
[gem5-dev] Change in gem5/gem5[develop]: configs: Remove old boot files
Jason Lowe-Power has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/28507 ) Change subject: configs: Remove old boot files .. configs: Remove old boot files Most of these "rcS" scripts are only useful for specific disk images that have long been lost to the gem5 community. This commit deletes all of these scripts. It keeps the generally useful hack_back_cktp script and the bbench scripts that work with the android images that are still available. In the future, these remaning scripts should be moved to the gem5 resources repository. Change-Id: Iba99e70fde7f656e968b4ecd95663275bd38fd6e Signed-off-by: Jason Lowe-Power --- D configs/boot/ammp.rcS D configs/boot/ammp.symbol D configs/boot/art.rcS D configs/boot/bn-app.rcS D configs/boot/bonnie.rcS D configs/boot/bonnie.symbol D configs/boot/bzip.rcS D configs/boot/cc1.symbol D configs/boot/devtime.rcS D configs/boot/equake.rcS D configs/boot/equake.symbol D configs/boot/gcc.rcS D configs/boot/gzip.rcS D configs/boot/gzip.symbol D configs/boot/halt.sh D configs/boot/iscsi-client.rcS D configs/boot/iscsi-server.rcS D configs/boot/ls.rcS D configs/boot/mcf.rcS D configs/boot/mcf.symbol D configs/boot/mesa.rcS D configs/boot/mesa.symbol D configs/boot/micro_ctx.rcS D configs/boot/micro_memlat.rcS D configs/boot/micro_memlat2mb.rcS D configs/boot/micro_memlat8.rcS D configs/boot/micro_memlat8mb.rcS D configs/boot/micro_stream.rcS D configs/boot/micro_streamcopy.rcS D configs/boot/micro_streamscale.rcS D configs/boot/micro_syscall.rcS D configs/boot/micro_tlblat.rcS D configs/boot/micro_tlblat2.rcS D configs/boot/micro_tlblat3.rcS D configs/boot/mutex-test.rcS D configs/boot/nat-netperf-maerts-client.rcS D configs/boot/nat-netperf-server.rcS D configs/boot/nat-netperf-stream-client.rcS D configs/boot/nat-spec-surge-client.rcS D configs/boot/nat-spec-surge-server.rcS D configs/boot/natbox-netperf.rcS D configs/boot/natbox-spec-surge.rcS D configs/boot/netperf-maerts-client.rcS D configs/boot/netperf-rr.rcS D configs/boot/netperf-server.rcS D configs/boot/netperf-stream-client.rcS D configs/boot/netperf-stream-nt-client.rcS D configs/boot/netperf-stream-udp-client.rcS D configs/boot/netperf-stream-udp-local.rcS D configs/boot/nfs-client-dbench.rcS D configs/boot/nfs-client-nhfsstone.rcS D configs/boot/nfs-client-smallb.rcS D configs/boot/nfs-client-tcp-smallb.rcS D configs/boot/nfs-client-tcp.rcS D configs/boot/nfs-client.rcS D configs/boot/nfs-server-nhfsstone.rcS D configs/boot/nfs-server.rcS D configs/boot/null.rcS D configs/boot/ping-client.rcS D configs/boot/ping-server.rcS D configs/boot/setup D configs/boot/spec-surge-client.rcS D configs/boot/spec-surge-server.rcS D configs/boot/surge-client.rcS D configs/boot/surge-server.rcS 65 files changed, 0 insertions(+), 7,270 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28507 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Iba99e70fde7f656e968b4ecd95663275bd38fd6e Gerrit-Change-Number: 28507 Gerrit-PatchSet: 1 Gerrit-Owner: Jason Lowe-Power Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Fixes to PIF prefetcher
Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28487 )
Change subject: mem-cache: Fixes to PIF prefetcher
..
mem-cache: Fixes to PIF prefetcher
The temporal compactor was never initialized.
A block distance of zero would seg fault.
From the original paper, "The prediction mechanism searches for
the PC of the accessed instruction in the index table"
Change-Id: I3c3aceac3c0adbbe8aef5c634c88cb35ba7487be
Signed-off-by: Daniel R. Carvalho
---
M src/mem/cache/prefetch/pif.cc
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/src/mem/cache/prefetch/pif.cc b/src/mem/cache/prefetch/pif.cc
index 6a2983b..42b3cca 100644
--- a/src/mem/cache/prefetch/pif.cc
+++ b/src/mem/cache/prefetch/pif.cc
@@ -78,9 +78,9 @@
(succ.size() >= blk_distance) : (prec.size() >= blk_distance);
if (hit && update) {
if (pc > trigger) {
-succ[blk_distance - 1] = true;
+succ[(blk_distance - 1) % succ.size()] = true;
} else if (pc < trigger) {
-prec[blk_distance - 1] = true;
+prec[(blk_distance - 1) % prec.size()] = true;
}
}
return hit;
@@ -93,9 +93,11 @@
Addr blk_distance = distanceFromTrigger(target, log_blk_size);
bool hit = false;
if (target > trigger) {
-hit = blk_distance <= succ.size() && succ[blk_distance - 1];
+hit = blk_distance <= succ.size() &&
+succ[(blk_distance - 1) % succ.size()];
} else if (target < trigger) {
-hit = blk_distance <= prec.size() && succ[blk_distance - 1];
+hit = blk_distance <= prec.size() &&
+succ[(blk_distance - 1) % prec.size()];
} else {
hit = true;
}
@@ -134,6 +136,7 @@
// First access to the prefetcher
if (temporalCompactor.size() == 0) {
spatialCompactor = CompactorEntry(pc, precSize, succSize);
+temporalCompactor.push_back(spatialCompactor);
} else {
// If the PC of the instruction retired is in the same spatial
region
// than the last trigger address, update the bit vectors based on
the
@@ -195,12 +198,16 @@
PIF::calculatePrefetch(const PrefetchInfo ,
std::vector )
{
-const Addr addr = pfi.getAddr();
+if (!pfi.hasPC()) {
+return;
+}
+
+const Addr pc = pfi.getPC();
// First check if the access has been prefetched, this is done by
// comparing the access against the active Stream Address Buffers
for (auto : streamAddressBuffer) {
-if (sabEntry->hasAddress(addr, lBlkSize)) {
+if (sabEntry->hasAddress(pc, lBlkSize)) {
sabEntry++;
sabEntry->getPredictedAddresses(lBlkSize, addresses);
// We are done
@@ -210,7 +217,7 @@
// Check if a valid entry in the 'index' table is found and allocate a
new
// active prediction stream
-IndexEntry *idx_entry = index.findEntry(addr, /* unused */ false);
+IndexEntry *idx_entry = index.findEntry(pc, /* unused */ false);
if (idx_entry != nullptr) {
index.accessEntry(idx_entry);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28487
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3c3aceac3c0adbbe8aef5c634c88cb35ba7487be
Gerrit-Change-Number: 28487
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: show names on --debug-flags MiscRegs write:
Ciro Santilli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28467 )
Change subject: arch-arm: show names on --debug-flags MiscRegs write:
..
arch-arm: show names on --debug-flags MiscRegs write:
Before this commit it would show only numbers:
Writing to misc reg 19 (19) : 0x74178
and now it also shows the name:
Writing MiscReg lockaddr (19 19) : 0x74178
MiscReg reads were already showing names and are unchanged, e.g.:
Reading MiscReg sctlr_el1 with clear res1 bits: 0x18100800
Change-Id: If46da88359ce4a549a6a50080a2b13077d41e373
---
M src/arch/arm/isa.cc
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b3d6726..b18bbb0 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -787,12 +787,12 @@
if (upper > 0) {
miscRegs[lower] = bits(v, 31, 0);
miscRegs[upper] = bits(v, 63, 32);
-DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
-misc_reg, lower, upper, v);
+DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d:%d) : %#x\n",
+miscRegName[misc_reg], misc_reg, lower, upper, v);
} else {
miscRegs[lower] = v;
-DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
-misc_reg, lower, v);
+DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d) : %#x\n",
+miscRegName[misc_reg], misc_reg, lower, v);
}
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If46da88359ce4a549a6a50080a2b13077d41e373
Gerrit-Change-Number: 28467
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli
Gerrit-MessageType: newchange
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[gem5-dev] Re: RELEASE-NOTES file in gem5
Dear all, There is now a RELEASE_NOTES.md file in the root directory of gem5 (on develop branch for now). If anyone has any items they want included in this RELEASE_NOTES.md file, which are not noted already, then please get in touch with me and I'll add them. This list is the best way for us to communicate to users what has changed between gem5 19 and gem5 20. In general, it's a great way to advertise big-ticket items we have contributed and/or inform users of anything important that may have changed (changing APIs, etc.). As these release notes do not affect any code, I'll accept updates to this file on the staging branch. Ergo, it can continue to be updated over the next few weeks until the release of gem5 20 in the middle of the month. Kind regards, Bobby -- Dr. Bobby R. Bruce Room 2235, Kemper Hall, UC Davis Davis, CA, 95616 web: https://www.bobbybruce.net On Wed, Apr 15, 2020 at 10:01 AM Bobby Bruce wrote: > Dear all, > > I'm writing to ask if anyone has any opinions on adding a RELEASE-NOTES.md > file in the root directory of gem5. Given we now have official releases, I > believe it'd be a better user experience to record the major changes made > to the project within the repository somewhere. It would also give us a > chance to note down any changes a user would need to be aware of when > moving from one version of gem5 to another (e.g., APIs that have changed, > deprecated classes, etc.). > > I started a very rough draft of this (WIP, very incomplete). > https://gem5-review.googlesource.com/c/public/gem5/+/27807 > > Developers would need to append to this file as new changes are added, but > I don't think this is a significant overhead :) > > Kind regards, > Bobby > -- > Dr. Bobby R. Bruce > Room 2235, > Kemper Hall, UC Davis > Davis, > CA, 95616 > > web: https://www.bobbybruce.net > ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Use CircularQueue for the STeMS's RMOB
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/24539 )
Change subject: mem-cache: Use CircularQueue for the STeMS's RMOB
..
mem-cache: Use CircularQueue for the STeMS's RMOB
Replace rmobHead functionality with a CircularQueue. As a side
effect, RMOB entry's valid bit was removed.
Change-Id: If0b39cfe15de1e47dde0689a0ebc46b623ec1e55
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24539
Reviewed-by: Nikos Nikoleris
Reviewed-by: Javier Bueno Hedo
Maintainer: Nikos Nikoleris
Tested-by: kokoro
---
M src/mem/cache/prefetch/spatio_temporal_memory_streaming.cc
M src/mem/cache/prefetch/spatio_temporal_memory_streaming.hh
2 files changed, 33 insertions(+), 38 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
Javier Bueno Hedo: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/mem/cache/prefetch/spatio_temporal_memory_streaming.cc
b/src/mem/cache/prefetch/spatio_temporal_memory_streaming.cc
index 932c7f6..dd15012 100644
--- a/src/mem/cache/prefetch/spatio_temporal_memory_streaming.cc
+++ b/src/mem/cache/prefetch/spatio_temporal_memory_streaming.cc
@@ -50,7 +50,7 @@
p->pattern_sequence_table_replacement_policy,
ActiveGenerationTableEntry(
spatialRegionSize / blkSize)),
-rmob(p->region_miss_order_buffer_entries), rmobHead(0)
+rmob(p->region_miss_order_buffer_entries)
{
fatal_if(!isPowerOf2(spatialRegionSize),
"The spatial region size must be a power of 2.");
@@ -106,13 +106,12 @@
void
STeMS::addToRMOB(Addr sr_addr, Addr pst_addr, unsigned int delta)
{
-RegionMissOrderBufferEntry _entry = rmob[rmobHead];
-rmobHead = (rmobHead + 1) % rmob.size();
-
+RegionMissOrderBufferEntry rmob_entry;
rmob_entry.srAddress = sr_addr;
rmob_entry.pstAddress = pst_addr;
rmob_entry.delta = delta;
-rmob_entry.valid = true;
+
+rmob.push_back(rmob_entry);
}
void
@@ -171,13 +170,12 @@
// Prefetch generation: if this is a miss, search for the most recent
// entry in the RMOB, and reconstruct the registered access sequence
if (pfi.isCacheMiss()) {
-for (unsigned int idx = (rmobHead - 1) % rmob.size();
- idx != rmobHead && rmob[idx].valid;
- idx = (idx - 1) % rmob.size())
-{
-if (rmob[idx].srAddress == sr_addr) {
+auto it = rmob.end();
+while (it != rmob.begin()) {
+--it;
+if (it->srAddress == sr_addr) {
// reconstruct the access sequence
-reconstructSequence(idx, addresses);
+reconstructSequence(it, addresses);
break;
}
}
@@ -185,37 +183,34 @@
}
void
-STeMS::reconstructSequence(unsigned int rmob_idx,
+STeMS::reconstructSequence(
+CircularQueue::iterator rmob_it,
std::vector )
{
std::vector reconstruction(reconstructionEntries, MaxAddr);
unsigned int idx = 0;
-// process rmob entries from rmob_idx (most recent with
-// address = sr_addr) to the last one (rmobHead)
-for (int i = rmob_idx;
- i != rmobHead && idx < reconstructionEntries;
- i = (i + 1) % rmob.size())
-{
-reconstruction[idx] = rmob[i].srAddress * spatialRegionSize;
-unsigned int next_i = (i + 1) % rmob.size();
-idx += rmob[next_i].delta + 1;
+
+// Process rmob entries from rmob_it (most recent with address =
sr_addr)
+// to the latest one
+for (auto it = rmob_it; it != rmob.end() && (idx <
reconstructionEntries);
+it++) {
+reconstruction[idx] = it->srAddress * spatialRegionSize;
+idx += (it+1)->delta + 1;
}
+
// Now query the PST with the PC of each RMOB entry
idx = 0;
-for (int i = rmob_idx;
- i != rmobHead && idx < reconstructionEntries;
- i = (i + 1) % rmob.size())
-{
+for (auto it = rmob_it; it != rmob.end() && (idx <
reconstructionEntries);
+it++) {
ActiveGenerationTableEntry *pst_entry =
-patternSequenceTable.findEntry(rmob[i].pstAddress,
- false /* unused */);
+patternSequenceTable.findEntry(it->pstAddress, false /* unused
*/);
if (pst_entry != nullptr) {
patternSequenceTable.accessEntry(pst_entry);
for (auto _entry : pst_entry->sequence) {
if (seq_entry.counter > 1) {
// 2-bit counter: high enough confidence with a
// value greater than 1
-Addr rec_addr = rmob[i].srAddress * spatialRegionSize +
+Addr rec_addr = it->srAddress * spatialRegionSize +
[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Fix DCPT with CircularQueue
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/24538 )
Change subject: mem-cache: Fix DCPT with CircularQueue
..
mem-cache: Fix DCPT with CircularQueue
This patch fixes the following bugs:
- Previously when deltaPointer was 0 or 1, getting the last or penultimate
deltas
would be wrong for non-pow2 deltas.size(). For example, if the last added
delta
was to position 0, the previous should be in position 19, if
deltas.size() = 20.
However, 0-1=4294967295, and 4294967295%20=15.
- When searching for the previous late and penultimate, the oldest entry
was being
skipped.
Change-Id: Id800b60b77531ac4c2920bb90c15cc8cebb137a9
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24538
Reviewed-by: Nikos Nikoleris
Reviewed-by: Javier Bueno Hedo
Maintainer: Nikos Nikoleris
Tested-by: kokoro
---
M src/mem/cache/prefetch/delta_correlating_prediction_tables.cc
M src/mem/cache/prefetch/delta_correlating_prediction_tables.hh
2 files changed, 26 insertions(+), 36 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
Javier Bueno Hedo: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/mem/cache/prefetch/delta_correlating_prediction_tables.cc
b/src/mem/cache/prefetch/delta_correlating_prediction_tables.cc
index ba9d22f..11ea89d 100644
--- a/src/mem/cache/prefetch/delta_correlating_prediction_tables.cc
+++ b/src/mem/cache/prefetch/delta_correlating_prediction_tables.cc
@@ -48,11 +48,11 @@
{
TaggedEntry::invalidate();
-for (auto : deltas) {
-delta = 0;
+deltas.flush();
+while (!deltas.full()) {
+deltas.push_back(0);
}
lastAddress = 0;
-deltaPointer = 0;
}
void
@@ -74,8 +74,7 @@
delta = 0;
}
}
-deltas[deltaPointer] = delta;
-deltaPointer = (deltaPointer + 1) % deltas.size();
+deltas.push_back(delta);
lastAddress = address;
}
}
@@ -84,15 +83,14 @@
DeltaCorrelatingPredictionTables::DCPTEntry::getCandidates(
std::vector , unsigned int mask) const
{
-// most recent index
-unsigned int last = (deltaPointer - 1) % deltas.size();
-// second most recent index
-unsigned int last_prev = (deltaPointer - 2) % deltas.size();
-int delta_0 = deltas[last_prev];
-int delta_1 = deltas[last];
+assert(deltas.full());
+
+// Get the two most recent deltas
+const int delta_penultimate = *(deltas.end() - 2);
+const int delta_last = *(deltas.end() - 1);
// a delta 0 means that it overflowed, we can not match it
-if (delta_0 == 0 || delta_1 == 0) {
+if (delta_last == 0 || delta_penultimate == 0) {
return;
}
@@ -100,26 +98,22 @@
// delta circular array, if found, start issuing prefetches using the
// remaining deltas (adding each delta to the last Addr to generate the
// prefetched address.
-
-// oldest index
-int idx_0 = deltaPointer + 1;
-// second oldest index
-int idx_1 = deltaPointer + 2;
-for (int i = 0; i < deltas.size() - 2; i += 1) {
-int this_delta_0 = deltas[(idx_0 + i) % deltas.size()];
-int this_delta_1 = deltas[(idx_1 + i) % deltas.size()];
-if ((this_delta_0 >> mask) == (delta_0 >> mask) &&
-(this_delta_1 >> mask) == (delta_1 >> mask)) {
+auto it = deltas.begin();
+for (; it != (deltas.end() - 2); ++it) {
+const int prev_delta_penultimate = *it;
+const int prev_delta_last = *(it + 1);
+if ((prev_delta_penultimate >> mask) == (delta_penultimate >>
mask) &&
+(prev_delta_last >> mask) == (delta_last >> mask)) {
+// Pattern found. Skip the matching pair and issue prefetches
with
+// the remaining deltas
+it += 2;
Addr addr = lastAddress;
-// Pattern found, issue prefetches with the remaining deltas
after
-// this pair
-i += 2; // skip the matching pair
-do {
-int pf_delta = deltas[(idx_0 + i) % deltas.size()];
+while (it != deltas.end()) {
+const int pf_delta = *(it++);
addr += pf_delta;
pfs.push_back(Queued::AddrPriority(addr, 0));
-i += 1;
-} while (i < deltas.size() - 2);
+}
+break;
}
}
}
diff --git a/src/mem/cache/prefetch/delta_correlating_prediction_tables.hh
b/src/mem/cache/prefetch/delta_correlating_prediction_tables.hh
index c051eca..28c9987 100644
--- a/src/mem/cache/prefetch/delta_correlating_prediction_tables.hh
+++ b/src/mem/cache/prefetch/delta_correlating_prediction_tables.hh
@@ -29,6 +29,7 @@
#ifndef __MEM_CACHE_PREFETCH_DELTA_CORRELATING_PREDICTION_TABLES_HH_
#define
[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Use AssociativeSet in Stride prefetcher
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/24603 )
Change subject: mem-cache: Use AssociativeSet in Stride prefetcher
..
mem-cache: Use AssociativeSet in Stride prefetcher
Avoid replicating associative set functionality in Stride prefetcher's
pc tables.
The indexing policy used previously had some peculiarities, so both
the extractTag and extractSet have been made virtual so that previous
behavior could be kept.
Change-Id: I19a86cb3c4b40031fef427d5f7eed9d5c5673a44
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24603
Reviewed-by: Nikos Nikoleris
Maintainer: Nikos Nikoleris
Tested-by: kokoro
---
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/prefetch/stride.cc
M src/mem/cache/prefetch/stride.hh
M src/mem/cache/tags/indexing_policies/base.hh
M src/mem/cache/tags/indexing_policies/set_associative.hh
5 files changed, 86 insertions(+), 152 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/cache/prefetch/Prefetcher.py
b/src/mem/cache/prefetch/Prefetcher.py
index 51132f9..f131ccf 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -139,6 +139,11 @@
throttle_control_percentage = Param.Percent(0, "Percentage of requests
\
that can be throttled depending on the accuracy of the
prefetcher.")
+class StridePrefetcherHashedSetAssociative(SetAssociative):
+type = 'StridePrefetcherHashedSetAssociative'
+cxx_class = 'Prefetcher::StridePrefetcherHashedSetAssociative'
+cxx_header = "mem/cache/prefetch/stride.hh"
+
class StridePrefetcher(QueuedPrefetcher):
type = 'StridePrefetcher'
cxx_class = 'Prefetcher::Stride'
@@ -154,15 +159,18 @@
confidence_threshold = Param.Percent(50,
"Prefetch generation confidence threshold")
-table_sets = Param.Int(16, "Number of sets in PC lookup table")
-table_assoc = Param.Int(4, "Associativity of PC lookup table")
use_master_id = Param.Bool(True, "Use master id based history")
degree = Param.Int(4, "Number of prefetches to generate")
-# Get replacement policy
-replacement_policy = Param.BaseReplacementPolicy(RandomRP(),
-"Replacement policy")
+table_assoc = Param.Int(4, "Associativity of the PC table")
+table_entries = Param.MemorySize("64", "Number of entries of the PC
table")
+table_indexing_policy = Param.BaseIndexingPolicy(
+StridePrefetcherHashedSetAssociative(entry_size = 1,
+assoc = Parent.table_assoc, size = Parent.table_entries),
+"Indexing policy of the PC table")
+table_replacement_policy = Param.BaseReplacementPolicy(RandomRP(),
+"Replacement policy of the PC table")
class TaggedPrefetcher(QueuedPrefetcher):
type = 'TaggedPrefetcher'
diff --git a/src/mem/cache/prefetch/stride.cc
b/src/mem/cache/prefetch/stride.cc
index 101adf2..36773c6 100644
--- a/src/mem/cache/prefetch/stride.cc
+++ b/src/mem/cache/prefetch/stride.cc
@@ -53,13 +53,14 @@
#include "base/random.hh"
#include "base/trace.hh"
#include "debug/HWPrefetch.hh"
+#include "mem/cache/prefetch/associative_set_impl.hh"
#include "mem/cache/replacement_policies/base.hh"
#include "params/StridePrefetcher.hh"
namespace Prefetcher {
Stride::StrideEntry::StrideEntry(const SatCounter& init_confidence)
- : ReplaceableEntry(), confidence(init_confidence)
+ : TaggedEntry(), confidence(init_confidence)
{
invalidate();
}
@@ -67,9 +68,7 @@
void
Stride::StrideEntry::invalidate()
{
-instAddr = 0;
lastAddr = 0;
-isSecure = false;
stride = 0;
confidence.reset();
}
@@ -78,13 +77,11 @@
: Queued(p),
initConfidence(p->confidence_counter_bits, p->initial_confidence),
threshConf(p->confidence_threshold/100.0),
-pcTableAssoc(p->table_assoc),
-pcTableSets(p->table_sets),
useMasterId(p->use_master_id),
degree(p->degree),
-replacementPolicy(p->replacement_policy)
+pcTableInfo(p->table_assoc, p->table_entries, p->table_indexing_policy,
+p->table_replacement_policy)
{
-assert(isPowerOf2(pcTableSets));
}
Stride::PCTable*
@@ -104,7 +101,8 @@
{
// Create new table
auto insertion_result = pcTables.insert(std::make_pair(context,
-PCTable(pcTableAssoc, pcTableSets, name(), replacementPolicy,
+PCTable(pcTableInfo.assoc, pcTableInfo.numEntries,
+pcTableInfo.indexingPolicy, pcTableInfo.replacementPolicy,
StrideEntry(initConfidence;
DPRINTF(HWPrefetch, "Adding context %i with stride entries\n",
context);
@@ -113,28 +111,6 @@
return &(insertion_result.first->second);
}
-Stride::PCTable::PCTable(int assoc, int sets, const std::string name,
-BaseReplacementPolicy* replacementPolicy, StrideEntry init_confidence)
-
[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Cleanup of SBOOE prefetcher
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/24541 )
Change subject: mem-cache: Cleanup of SBOOE prefetcher
..
mem-cache: Cleanup of SBOOE prefetcher
Made the latencyBuffer a CircularQueue.
Improved encapsulation of the Sandbox struct.
Fixed score() to follow function declaration guidelines.
Removed redundant fatal error checking for score threshold.
Change-Id: I1904884e96f103c67930abafc28b75796aadc406
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24541
Reviewed-by: Nikos Nikoleris
Maintainer: Nikos Nikoleris
Tested-by: kokoro
---
M src/mem/cache/prefetch/sbooe.cc
M src/mem/cache/prefetch/sbooe.hh
2 files changed, 39 insertions(+), 46 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/cache/prefetch/sbooe.cc
b/src/mem/cache/prefetch/sbooe.cc
index ecbab68..2faa137 100644
--- a/src/mem/cache/prefetch/sbooe.cc
+++ b/src/mem/cache/prefetch/sbooe.cc
@@ -35,17 +35,13 @@
SBOOE::SBOOE(const SBOOEPrefetcherParams *p)
: Queued(p),
- latencyBufferSize(p->latency_buffer_size),
sequentialPrefetchers(p->sequential_prefetchers),
scoreThreshold((p->sandbox_entries*p->score_threshold_pct)/100),
+ latencyBuffer(p->latency_buffer_size),
averageAccessLatency(0), latencyBufferSum(0),
bestSandbox(NULL),
accesses(0)
{
-if (!(p->score_threshold_pct >= 0 && p->score_threshold_pct <= 100)) {
-fatal("%s: the score threshold should be between 0 and 100\n",
name());
-}
-
// Initialize a sandbox for every sequential prefetcher between
// -1 and the number of sequential prefetchers defined
for (int i = 0; i < sequentialPrefetchers; i++) {
@@ -54,34 +50,31 @@
}
void
-SBOOE::Sandbox::insert(Addr addr, Tick tick)
+SBOOE::Sandbox::access(Addr addr, Tick tick)
{
-entries[index].valid = true;
-entries[index].line = addr + stride;
-entries[index].expectedArrivalTick = tick;
-
-index++;
-
-if (index == entries.size()) {
-index = 0;
+// Search for the address in the FIFO queue to update the score
+for (const SandboxEntry : entries) {
+if (entry.valid && entry.line == addr) {
+sandboxScore++;
+if (entry.expectedArrivalTick > curTick()) {
+lateScore++;
+}
+}
}
+
+// Insert new access in this sandbox
+SandboxEntry entry;
+entry.valid = true;
+entry.line = addr + stride;
+entry.expectedArrivalTick = tick;
+entries.push_back(entry);
}
bool
SBOOE::access(Addr access_line)
{
for (Sandbox : sandboxes) {
-// Search for the address in the FIFO queue
-for (const SandboxEntry : sb.entries) {
-if (entry.valid && entry.line == access_line) {
-sb.sandboxScore++;
-if (entry.expectedArrivalTick > curTick()) {
-sb.lateScore++;
-}
-}
-}
-
-sb.insert(access_line, curTick() + averageAccessLatency);
+sb.access(access_line, curTick() + averageAccessLatency);
if (bestSandbox == NULL || sb.score() > bestSandbox->score()) {
bestSandbox =
@@ -106,14 +99,12 @@
if (it != demandAddresses.end()) {
Tick elapsed_ticks = curTick() - it->second;
+if (latencyBuffer.full()) {
+latencyBufferSum -= latencyBuffer.front();
+}
latencyBuffer.push_back(elapsed_ticks);
latencyBufferSum += elapsed_ticks;
-if (latencyBuffer.size() > latencyBufferSize) {
-latencyBufferSum -= latencyBuffer.front();
-latencyBuffer.pop_front();
-}
-
averageAccessLatency = latencyBufferSum / latencyBuffer.size();
demandAddresses.erase(it);
diff --git a/src/mem/cache/prefetch/sbooe.hh
b/src/mem/cache/prefetch/sbooe.hh
index 8076732..42deaf3 100644
--- a/src/mem/cache/prefetch/sbooe.hh
+++ b/src/mem/cache/prefetch/sbooe.hh
@@ -35,10 +35,10 @@
#ifndef __MEM_CACHE_PREFETCH_SBOOE_HH__
#define __MEM_CACHE_PREFETCH_SBOOE_HH__
-#include
#include
#include
+#include "base/circular_queue.hh"
#include "mem/cache/prefetch/queued.hh"
#include "mem/packet.hh"
@@ -51,7 +51,6 @@
private:
/** Prefetcher parameters */
-const int latencyBufferSize;
const int sequentialPrefetchers;
/** Threshold used to issue prefetchers */
@@ -70,7 +69,7 @@
* calculate the average access latency which is later used to
* predict if a prefetcher would be filled on time if issued.
*/
-std::deque latencyBuffer;
+CircularQueue latencyBuffer;
/** Holds the current average access latency */
Tick averageAccessLatency;
@@ -91,48 +90,51 @@
[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Use SatCounter in Stride prefetcher
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/24542 )
Change subject: mem-cache: Use SatCounter in Stride prefetcher
..
mem-cache: Use SatCounter in Stride prefetcher
There is no need to reimplement saturating counter functionality.
Change-Id: Ie7753089873f41a378ab88fd5f095302c3428797
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24542
Reviewed-by: Nikos Nikoleris
Maintainer: Nikos Nikoleris
Tested-by: kokoro
---
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/prefetch/stride.cc
M src/mem/cache/prefetch/stride.hh
3 files changed, 38 insertions(+), 35 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/cache/prefetch/Prefetcher.py
b/src/mem/cache/prefetch/Prefetcher.py
index 8cfefe1..51132f9 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -147,10 +147,12 @@
# Do not consult stride prefetcher on instruction accesses
on_inst = False
-max_conf = Param.Int(7, "Maximum confidence level")
-thresh_conf = Param.Int(4, "Threshold confidence level")
-min_conf = Param.Int(0, "Minimum confidence level")
-start_conf = Param.Int(4, "Starting confidence for new entries")
+confidence_counter_bits = Param.Unsigned(3,
+"Number of bits of the confidence counter")
+initial_confidence = Param.Unsigned(4,
+"Starting confidence of new entries")
+confidence_threshold = Param.Percent(50,
+"Prefetch generation confidence threshold")
table_sets = Param.Int(16, "Number of sets in PC lookup table")
table_assoc = Param.Int(4, "Associativity of PC lookup table")
diff --git a/src/mem/cache/prefetch/stride.cc
b/src/mem/cache/prefetch/stride.cc
index 8e47d9b..101adf2 100644
--- a/src/mem/cache/prefetch/stride.cc
+++ b/src/mem/cache/prefetch/stride.cc
@@ -58,7 +58,8 @@
namespace Prefetcher {
-Stride::StrideEntry::StrideEntry()
+Stride::StrideEntry::StrideEntry(const SatCounter& init_confidence)
+ : ReplaceableEntry(), confidence(init_confidence)
{
invalidate();
}
@@ -70,20 +71,18 @@
lastAddr = 0;
isSecure = false;
stride = 0;
-confidence = 0;
+confidence.reset();
}
Stride::Stride(const StridePrefetcherParams *p)
-: Queued(p),
- maxConf(p->max_conf),
- threshConf(p->thresh_conf),
- minConf(p->min_conf),
- startConf(p->start_conf),
- pcTableAssoc(p->table_assoc),
- pcTableSets(p->table_sets),
- useMasterId(p->use_master_id),
- degree(p->degree),
- replacementPolicy(p->replacement_policy)
+ : Queued(p),
+initConfidence(p->confidence_counter_bits, p->initial_confidence),
+threshConf(p->confidence_threshold/100.0),
+pcTableAssoc(p->table_assoc),
+pcTableSets(p->table_sets),
+useMasterId(p->use_master_id),
+degree(p->degree),
+replacementPolicy(p->replacement_policy)
{
assert(isPowerOf2(pcTableSets));
}
@@ -105,7 +104,8 @@
{
// Create new table
auto insertion_result = pcTables.insert(std::make_pair(context,
-PCTable(pcTableAssoc, pcTableSets, name(), replacementPolicy)));
+PCTable(pcTableAssoc, pcTableSets, name(), replacementPolicy,
+StrideEntry(initConfidence;
DPRINTF(HWPrefetch, "Adding context %i with stride entries\n",
context);
@@ -114,12 +114,12 @@
}
Stride::PCTable::PCTable(int assoc, int sets, const std::string name,
- BaseReplacementPolicy*
replacementPolicy)
+BaseReplacementPolicy* replacementPolicy, StrideEntry init_confidence)
: pcTableSets(sets), _name(name), entries(pcTableSets),
replacementPolicy(replacementPolicy)
{
for (int set = 0; set < sets; set++) {
-entries[set].resize(assoc);
+entries[set].resize(assoc, init_confidence);
for (int way = 0; way < assoc; way++) {
// Inform the entry its position
entries[set][way].setPosition(set, way);
@@ -163,26 +163,26 @@
// Adjust confidence for stride entry
if (stride_match && new_stride != 0) {
-if (entry->confidence < maxConf)
-entry->confidence++;
+entry->confidence++;
} else {
-if (entry->confidence > minConf)
-entry->confidence--;
+entry->confidence--;
// If confidence has dropped below the threshold, train new
stride
-if (entry->confidence < threshConf)
+if (entry->confidence.calcSaturation() < threshConf) {
entry->stride = new_stride;
+}
}
DPRINTF(HWPrefetch, "Hit: PC %x pkt_addr %x (%s) stride %d (%s), "
"conf %d\n", pc, pf_addr, is_secure ? "s" : "ns",
new_stride,
[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Use CircularQueue in PIF prefetcher
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/24540 )
Change subject: mem-cache: Use CircularQueue in PIF prefetcher
..
mem-cache: Use CircularQueue in PIF prefetcher
Use CircularQueue for PIF's history buffer, and change the indexing
storage to a CQ iterator.
Change-Id: I75bbb75a6be41bd063f662baedbd4c9de33644de
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24540
Reviewed-by: Nikos Nikoleris
Maintainer: Nikos Nikoleris
Tested-by: kokoro
---
M src/mem/cache/prefetch/pif.cc
M src/mem/cache/prefetch/pif.hh
2 files changed, 13 insertions(+), 29 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/cache/prefetch/pif.cc b/src/mem/cache/prefetch/pif.cc
index 8491062..6a2983b 100644
--- a/src/mem/cache/prefetch/pif.cc
+++ b/src/mem/cache/prefetch/pif.cc
@@ -41,12 +41,11 @@
precSize(p->prec_spatial_region_bits),
succSize(p->succ_spatial_region_bits),
maxCompactorEntries(p->compactor_entries),
- maxStreamAddressBufferEntries(p->stream_address_buffer_entries),
historyBuffer(p->history_buffer_size),
- historyBufferTail(0),
index(p->index_assoc, p->index_entries, p->index_indexing_policy,
p->index_replacement_policy),
- streamAddressBuffer(), listenersPC()
+ streamAddressBuffer(p->stream_address_buffer_entries),
+ listenersPC()
{
}
@@ -169,8 +168,8 @@
// updating the trigger address and resetting the vector bits
if (!is_in_temporal_compactor) {
// Insert the spatial entry into the history buffer and
update
-// the 'index' table to point to the new entry
-historyBuffer[historyBufferTail] = spatialCompactor;
+// the 'iterator' table to point to the new entry
+historyBuffer.push_back(spatialCompactor);
IndexEntry *idx_entry =
index.findEntry(spatialCompactor.trigger, false);
@@ -182,12 +181,8 @@
index.insertEntry(spatialCompactor.trigger, false,
idx_entry);
}
-idx_entry->historyIndex = historyBufferTail;
-
-historyBufferTail++;
-if (historyBufferTail == historyBuffer.size()) {
-historyBufferTail = 0;
-}
+idx_entry->historyIt =
+historyBuffer.getIterator(historyBuffer.tail());
// Reset the spatial compactor fields with the new address
spatialCompactor = CompactorEntry(pc, precSize, succSize);
@@ -206,13 +201,7 @@
// comparing the access against the active Stream Address Buffers
for (auto : streamAddressBuffer) {
if (sabEntry->hasAddress(addr, lBlkSize)) {
-// Advance to the next entry (first check if we have reached
the
-// end of the history buffer)
-if (sabEntry == &(historyBuffer[historyBuffer.size() - 1])) {
-sabEntry = &(historyBuffer[0]);
-} else {
-sabEntry++;
-}
+sabEntry++;
sabEntry->getPredictedAddresses(lBlkSize, addresses);
// We are done
return;
@@ -227,13 +216,9 @@
index.accessEntry(idx_entry);
// Trigger address from the 'index' table and index to the history
// buffer
-const unsigned int hb_entry = idx_entry->historyIndex;
-CompactorEntry *entry = [hb_entry];
+auto entry = idx_entry->historyIt;
// Track the block in the Stream Address Buffer
-if (streamAddressBuffer.size() == maxStreamAddressBufferEntries) {
-streamAddressBuffer.pop_front();
-}
streamAddressBuffer.push_back(entry);
entry->getPredictedAddresses(lBlkSize, addresses);
diff --git a/src/mem/cache/prefetch/pif.hh b/src/mem/cache/prefetch/pif.hh
index 9fef296..e3d34fb 100644
--- a/src/mem/cache/prefetch/pif.hh
+++ b/src/mem/cache/prefetch/pif.hh
@@ -40,6 +40,7 @@
#include
#include
+#include "base/circular_queue.hh"
#include "mem/cache/prefetch/associative_set.hh"
#include "mem/cache/prefetch/queued.hh"
@@ -55,8 +56,6 @@
const unsigned int succSize;
/** Number of entries used for the temporal compactor */
const unsigned int maxCompactorEntries;
-/** Max number of entries to be used in the Stream Address Buffer
*/
-const unsigned int maxStreamAddressBufferEntries;
/**
* The compactor tracks retired instructions addresses, leveraging
the
@@ -127,12 +126,12 @@
* History buffer is a circular buffer that stores the sequence of
* retired instructions in FIFO order.
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Decode SEVL instruction for A32 and T32 IS
Hello Ciro Santilli,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28450
to review the following change.
Change subject: arch-arm: Decode SEVL instruction for A32 and T32 IS
..
arch-arm: Decode SEVL instruction for A32 and T32 IS
The instruction had been defined but it was not used for AArch32
Change-Id: I2bb106e98647eaa1f4c71fffb541e76ac1688674
Signed-off-by: Giacomo Travaglini
Reviewed-by: Ciro Santilli
---
M src/arch/arm/isa/formats/branch.isa
M src/arch/arm/isa/formats/data.isa
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/arch/arm/isa/formats/branch.isa
b/src/arch/arm/isa/formats/branch.isa
index b7360fc..7c726ef 100644
--- a/src/arch/arm/isa/formats/branch.isa
+++ b/src/arch/arm/isa/formats/branch.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2010,2012-2013,2017-2018 ARM Limited
+// Copyright (c) 2010,2012-2013,2017-2018, 2020 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -187,8 +187,7 @@
case 0x4:
return new SevInst(machInst);
case 0x5:
-return new WarnUnimplemented(
-"sevl", machInst);
+return new SevlInst(machInst);
}
break;
case 0x1:
diff --git a/src/arch/arm/isa/formats/data.isa
b/src/arch/arm/isa/formats/data.isa
index a927f2b..b742951 100644
--- a/src/arch/arm/isa/formats/data.isa
+++ b/src/arch/arm/isa/formats/data.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2010,2017-2018 ARM Limited
+// Copyright (c) 2010,2017-2018, 2020 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -1136,8 +1136,7 @@
case 0x4:
return new SevInst(machInst);
case 0x5:
-return new WarnUnimplemented(
-"sevl", machInst);
+return new SevlInst(machInst);
case 0x10:
return new WarnUnimplemented(
"esb", machInst);
@@ -1283,6 +1282,8 @@
return new WfiInst(machInst);
case 0x4:
return new SevInst(machInst);
+ case 0x5:
+return new SevlInst(machInst);
default:
return new WarnUnimplemented("unallocated_hint", machInst);
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28450
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2bb106e98647eaa1f4c71fffb541e76ac1688674
Gerrit-Change-Number: 28450
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Ciro Santilli
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: fix Exec trace decode of ARM atomic instructions
Ciro Santilli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28449 )
Change subject: arch-arm: fix Exec trace decode of ARM atomic instructions
..
arch-arm: fix Exec trace decode of ARM atomic instructions
For example an STXR:
stxr w2, x1, [x0]
was decoding as:
stxr x1, x2, [x0]
and now it decodes as:
stxr x2, x1, [x0]
The w vs x part is still wrong and is not fixed by this patch.
MemoryEx64 seems to be the base class of all atomic instructions,
and I've verified that e.g. LDADD was also wrong and is now fixed.
Change-Id: Ic3bcb6a1d9b18f33dde5db369ac3903b443e53ae
JIRA: https://gem5.atlassian.net/browse/GEM5-484
---
M src/arch/arm/insts/mem64.cc
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/arch/arm/insts/mem64.cc b/src/arch/arm/insts/mem64.cc
index 0ddda95..9d4c391 100644
--- a/src/arch/arm/insts/mem64.cc
+++ b/src/arch/arm/insts/mem64.cc
@@ -182,9 +182,9 @@
{
std::stringstream ss;
printMnemonic(ss, "", false);
-printIntReg(ss, dest);
-ccprintf(ss, ", ");
printIntReg(ss, result);
+ccprintf(ss, ", ");
+printIntReg(ss, dest);
ccprintf(ss, ", [");
printIntReg(ss, base);
ccprintf(ss, "]");
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28449
To unsubscribe, or for help writing mail filters, visit
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic3bcb6a1d9b18f33dde5db369ac3903b443e53ae
Gerrit-Change-Number: 28449
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: scons: Build the marshal binary in a bare minimum environment
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28428 )
Change subject: scons: Build the marshal binary in a bare minimum
environment
..
scons: Build the marshal binary in a bare minimum environment
This change adds an additional bare minimum environment that includes
python only and changes the marshal binary to compile using it.
Change-Id: Id5d1ee6899796d746d8dc1a004cfe4795f040c55
Signed-off-by: Nikos Nikoleris
---
M SConstruct
M src/SConscript
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/SConstruct b/SConstruct
index 3345148..ba4affa 100755
--- a/SConstruct
+++ b/SConstruct
@@ -709,6 +709,10 @@
if not conf.CheckLib(lib):
error("Can't find library %s required by python." % lib)
+main.Prepend(CPPPATH=Dir('ext/pybind11/include/'))
+# Bare minimum environment that only includes python
+base_py_env = main.Clone()
+
# On Solaris you need to use libsocket for socket ops
if not
conf.CheckLibWithHeader(None, 'sys/socket.h', 'C++', 'accept(0,0,0);'):
if not conf.CheckLibWithHeader('socket', 'sys/socket.h',
@@ -1100,8 +1104,6 @@
gdb_xml_dir = joinpath(ext_dir, 'gdb-xml')
Export('gdb_xml_dir')
-main.Prepend(CPPPATH=Dir('ext/pybind11/include/'))
-
###
#
# This builder and wrapper method are used to set up a directory with
@@ -1259,7 +1261,8 @@
# The src/SConscript file sets up the build rules in 'env' according
# to the configured variables. It returns a list of environments,
# one for each variant build (debug, opt, etc.)
-SConscript('src/SConscript', variant_dir = variant_path, exports
= 'env')
+SConscript('src/SConscript', variant_dir=variant_path,
+ exports=['env', 'base_py_env'])
# base help text
Help('''
diff --git a/src/SConscript b/src/SConscript
index c7251fc..134e2a5 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1,6 +1,6 @@
# -*- mode:python -*-
-# Copyright (c) 2018 ARM Limited
+# Copyright (c) 2018, 2020 ARM Limited
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
@@ -1140,7 +1140,7 @@
# Build a small helper that marshals the Python code using the same
# version of Python as gem5. This is in an unorthodox location to
# avoid building it for every variant.
-py_marshal = env.Program('marshal', 'python/marshal.cc')[0]
+py_marshal = base_py_env.Program('marshal', 'python/marshal.cc')[0]
# Embed python files. All .py files that have been indicated by a
# PySource() call in a SConscript need to be embedded into the M5
@@ -1196,8 +1196,8 @@
code.write(str(target[0]))
for source in PySource.all:
-env.Command(source.cpp, [ py_marshal, source.tnode ],
-MakeAction(embedPyFile, Transform("EMBED PY")))
+base_py_env.Command(source.cpp, [ py_marshal, source.tnode ],
+MakeAction(embedPyFile, Transform("EMBED PY")))
Source(source.cpp, tags=source.tags, add_tags='python')
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id5d1ee6899796d746d8dc1a004cfe4795f040c55
Gerrit-Change-Number: 28428
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: be prepared for CSR changes during PT walk.
Nils Asmussen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28447 )
Change subject: arch-riscv: be prepared for CSR changes during PT walk.
..
arch-riscv: be prepared for CSR changes during PT walk.
If the address space is changed (by writing to SATP), it can happen that
a page table walk is in progress. Previously, this failed if the ASID
changed, because we then used the wrong ASID for the lookup.
This commit makes sure that we don't access CSRs after the beginning of
the walk by loading SATP, STATUS, and PRV at the beginning.
Change-Id: I8c184c7ae7dd44d78e881bb5ec8d430dd480849c
---
M src/arch/riscv/pagetable_walker.cc
M src/arch/riscv/pagetable_walker.hh
M src/arch/riscv/tlb.cc
M src/arch/riscv/tlb.hh
4 files changed, 33 insertions(+), 17 deletions(-)
diff --git a/src/arch/riscv/pagetable_walker.cc
b/src/arch/riscv/pagetable_walker.cc
index 02d2d94..6ec118d 100644
--- a/src/arch/riscv/pagetable_walker.cc
+++ b/src/arch/riscv/pagetable_walker.cc
@@ -184,6 +184,11 @@
tc = _tc;
mode = _mode;
timing = _isTiming;
+// fetch these now in case they change during the walk
+status = tc->readMiscReg(MISCREG_STATUS);
+pmode = walker->tlb->getMemPriv(tc, mode);
+satp = tc->readMiscReg(MISCREG_SATP);
+assert(satp.mode == AddrXlateMode::SV39);
}
void
@@ -303,7 +308,8 @@
if (pte.r || pte.x) {
// step 5: leaf PTE
doEndWalk = true;
-fault = walker->tlb->checkPermissions(tc, entry.vaddr, mode,
pte);
+fault = walker->tlb->checkPermissions(status, pmode,
+ entry.vaddr, mode, pte);
// step 6
if (fault == NoFault) {
@@ -413,10 +419,7 @@
void
Walker::WalkerState::setupWalk(Addr vaddr)
{
-vaddr &= ((static_cast(1) << VADDR_BITS) - 1);
-
-SATP satp = tc->readMiscReg(MISCREG_SATP);
-assert(satp.mode == AddrXlateMode::SV39);
+vaddr &= (static_cast(1) << VADDR_BITS) - 1;
Addr shift = PageShift + LEVEL_BITS * 2;
Addr idx = (vaddr >> shift) & LEVEL_MASK;
@@ -483,12 +486,12 @@
* permissions violations, so we'll need the return value as
* well.
*/
-bool delayedResponse;
-Fault fault = walker->tlb->doTranslate(req, tc, NULL, mode,
- delayedResponse);
-assert(!delayedResponse);
+Addr vaddr = req->getVaddr();
+vaddr &= (static_cast(1) << VADDR_BITS) - 1;
+Addr paddr = walker->tlb->translateWithTLB(vaddr, satp.asid,
mode);
+req->setPaddr(paddr);
// Let the CPU continue.
-translation->finish(fault, req, tc, mode);
+translation->finish(NoFault, req, tc, mode);
} else {
// There was a fault during the walk. Let the CPU know.
translation->finish(timingFault, req, tc, mode);
diff --git a/src/arch/riscv/pagetable_walker.hh
b/src/arch/riscv/pagetable_walker.hh
index 2d50928..60826a0 100644
--- a/src/arch/riscv/pagetable_walker.hh
+++ b/src/arch/riscv/pagetable_walker.hh
@@ -100,6 +100,9 @@
Fault timingFault;
TLB::Translation * translation;
BaseTLB::Mode mode;
+SATP satp;
+STATUS status;
+PrivilegeMode pmode;
bool functional;
bool timing;
bool retrying;
diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index 294d73f..c8b1a4c 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -213,7 +213,8 @@
}
Fault
-TLB::checkPermissions(ThreadContext *tc, Addr vaddr, Mode mode, PTESv39
pte)
+TLB::checkPermissions(STATUS status, PrivilegeMode pmode, Addr vaddr,
+ Mode mode, PTESv39 pte)
{
Fault fault = NoFault;
@@ -232,8 +233,6 @@
if (fault == NoFault) {
// check pte.u
-STATUS status = tc->readMiscReg(MISCREG_STATUS);
-PrivilegeMode pmode = getMemPriv(tc, mode);
if (pmode == PrivilegeMode::PRV_U && !pte.u) {
DPRINTF(TLB, "PTE is not user accessible, raising PF\n");
fault = createPagefault(vaddr, mode);
@@ -260,6 +259,14 @@
return std::make_shared(vaddr, code);
}
+Addr
+TLB::translateWithTLB(Addr vaddr, uint16_t asid, Mode mode)
+{
+TlbEntry *e = lookup(vaddr, asid, mode, false);
+assert(e != nullptr);
+return e->paddr << PageShift | (vaddr & mask(e->logBytes));
+}
+
Fault
TLB::doTranslate(const RequestPtr , ThreadContext *tc,
Translation *translation, Mode mode, bool )
@@ -281,7 +288,9 @@
assert(e != nullptr);
}
-Fault fault = checkPermissions(tc, vaddr, mode, e->pte);
+STATUS status = tc->readMiscReg(MISCREG_STATUS);
+PrivilegeMode pmode = getMemPriv(tc, mode);
+Fault fault =
[gem5-dev] Change in gem5/gem5[develop]: misc: added news on RISC-V to RELEASE-NOTES.md.
Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/28448 ) Change subject: misc: added news on RISC-V to RELEASE-NOTES.md. .. misc: added news on RISC-V to RELEASE-NOTES.md. Change-Id: I9b60cd2f533e6d4ce677e8a9b7bb5a5698e51c61 --- M RELEASE-NOTES.md 1 file changed, 1 insertion(+), 0 deletions(-) diff --git a/RELEASE-NOTES.md b/RELEASE-NOTES.md index 1a679dd..6f80906 100644 --- a/RELEASE-NOTES.md +++ b/RELEASE-NOTES.md @@ -8,3 +8,4 @@ * The m5 utility has been revamped with a new build system based on scons, tests, and updated and more consistent feature support. * Robust support for marshalling data from a function call inside the simulation to a function within gem5 using a predefined set of rules. * Workload configuration pulled out into its own object, simplifying the System object and making workload configuration more modular and flexible. +* Sv39 paging has been added to the RISC-V ISA, bringing gem5 close to running Linux on RISC-V. -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28448 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I9b60cd2f533e6d4ce677e8a9b7bb5a5698e51c61 Gerrit-Change-Number: 28448 Gerrit-PatchSet: 1 Gerrit-Owner: Nils Asmussen Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: tests: update linux boot tests
Ayaz Akram has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28427 )
Change subject: tests: update linux boot tests
..
tests: update linux boot tests
This change updates the config scripts used by linux boot
tests to make them compatible with change that deprecated
LinuxX86System
JIRA: https://gem5.atlassian.net/browse/GEM5-440
Change-Id: I04beff2915c03a2c3a774351edbba60d7ff26867
Signed-off-by: Ayaz Akram
---
M tests/gem5/x86-boot-tests/run_exit.py
M tests/gem5/x86-boot-tests/system/system.py
2 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/tests/gem5/x86-boot-tests/run_exit.py
b/tests/gem5/x86-boot-tests/run_exit.py
index 24edcc5..ecb3a84 100644
--- a/tests/gem5/x86-boot-tests/run_exit.py
+++ b/tests/gem5/x86-boot-tests/run_exit.py
@@ -51,7 +51,7 @@
if args.boot_type == "init":
# Simply run "exit.sh"
-system.boot_osflags += ' init=/root/exit.sh'
+system.workload.command_line += ' init=/root/exit.sh'
else:
if args.boot_type != "systemd":
m5.fatal("Bad option for boot_type. init or systemd.")
diff --git a/tests/gem5/x86-boot-tests/system/system.py
b/tests/gem5/x86-boot-tests/system/system.py
index 0b69be9..c55664e 100755
--- a/tests/gem5/x86-boot-tests/system/system.py
+++ b/tests/gem5/x86-boot-tests/system/system.py
@@ -30,11 +30,12 @@
from caches import *
import sys
-class MySystem(LinuxX86System):
+class MySystem(System):
def __init__(self, kernel, disk, cpu_type, num_cpus):
super(MySystem, self).__init__()
+self.workload = X86FsLinux()
self._host_parallel = cpu_type == "kvm"
# Set up the clock domain and the voltage domain
@@ -63,12 +64,12 @@
self.setDiskImages(disk, disk)
# Change this path to point to the kernel you want to use
-self.kernel = kernel
+self.workload.object_file = kernel
# Options specified on the kernel command line
boot_options =
['earlyprintk=ttyS0', 'console=ttyS0', 'lpj=723',
'root=/dev/hda1']
-self.boot_osflags = ' '.join(boot_options)
+self.workload.command_line = ' '.join(boot_options)
# Create the CPUs for our system.
self.createCPU(cpu_type, num_cpus)
@@ -235,7 +236,7 @@
###
# Add in a Bios information structure.
-self.smbios_table.structures = [X86SMBiosBiosInformation()]
+self.workload.smbios_table.structures =
[X86SMBiosBiosInformation()]
# Set up the Intel MP table
base_entries = []
@@ -293,8 +294,8 @@
assignISAInt(1, 1)
for i in range(3, 15):
assignISAInt(i, i)
-self.intel_mp_table.base_entries = base_entries
-self.intel_mp_table.ext_entries = ext_entries
+self.workload.intel_mp_table.base_entries = base_entries
+self.workload.intel_mp_table.ext_entries = ext_entries
entries = \
[
@@ -311,7 +312,7 @@
entries.append(X86E820Entry(addr = 0x, size = '64kB',
range_type=2))
-self.e820_table.entries = entries
+self.workload.e820_table.entries = entries
class CowDisk(IdeDisk):
def __init__(self, filename):
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I04beff2915c03a2c3a774351edbba60d7ff26867
Gerrit-Change-Number: 28427
Gerrit-PatchSet: 1
Gerrit-Owner: Ayaz Akram
Gerrit-MessageType: newchange
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