[gem5-dev] Change in gem5/gem5[develop]: sim: Move checkpoint parameters for ptable into seperate section
Ian Jiang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31874 )
Change subject: sim: Move checkpoint parameters for ptable into seperate
section
..
sim: Move checkpoint parameters for ptable into seperate section
In checkpoint output files, the parameters for page table including
size and entries are organized not very clearly. For example:
[system.cpu.workload]
...
ptable.size=...
[system.cpu.workload.Entry0]
vaddr=...
paddr=...
flags=...
[system.cpu.workload.Entry1]
...
This commit moves these parameters into a separate section named
'ptable'. For example:
[system.cpu.workload.ptable]
size=...
[system.cpu.workload.ptable.Entry0]
vaddr=...
paddr=...
flags=...
[system.cpu.workload.ptable.Entry1]
...
Change-Id: Iaa4129b3f4f090e8c3651bde90524abba0999c7f
Signed-off-by: Ian Jiang
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31874
Reviewed-by: Daniel Carvalho
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/mem/page_table.cc
1 file changed, 4 insertions(+), 2 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index 400500b..601b9c5 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -168,7 +168,8 @@
void
EmulationPageTable::serialize(CheckpointOut &cp) const
{
-paramOut(cp, "ptable.size", pTable.size());
+ScopedCheckpointSection sec(cp, "ptable");
+paramOut(cp, "size", pTable.size());
PTable::size_type count = 0;
for (auto &pte : pTable) {
@@ -185,7 +186,8 @@
EmulationPageTable::unserialize(CheckpointIn &cp)
{
int count;
-paramIn(cp, "ptable.size", count);
+ScopedCheckpointSection sec(cp, "ptable");
+paramIn(cp, "size", count);
for (int i = 0; i < count; ++i) {
ScopedCheckpointSection sec(cp, csprintf("Entry%d", i));
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iaa4129b3f4f090e8c3651bde90524abba0999c7f
Gerrit-Change-Number: 31874
Gerrit-PatchSet: 3
Gerrit-Owner: Ian Jiang
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Ian Jiang
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Re: The Nightly Build system is now Live (Compiler tests too!)
Thanks Bobby and Mike! These are amazing news Giacomo From: Bobby Bruce via gem5-dev Sent: 27 July 2020 19:55 To: gem5 Developer List Cc: Bobby Bruce Subject: [gem5-dev] The Nightly Build system is now Live (Compiler tests too!) Dear all, After some tinkering, we now have a nightly build system deployed, run from our Jenkins: https://jenkins.gem5.org. If I've set up the permissions correctly, everyone should be able to see the status of all our builds from there. Please note, at the time of writing, we're still experimenting with other testing/building setups, so there may be builds there that I haven't explained in this email. These can be ignored. Right now, the Nightly Builds compile the NULL, ARM, MIPS, POWER, RISCV, SPARC, and X86 ".opt" variants of gem5, run the unit tests (those executed via `scons build/null/unittests.opt`), and the "long" testlib regression tests (those executed via `scons ./main.py run --length long` from the `tests` directory) on the gem5 develop branch. In order to test that our email provider is functioning correctly, I've set this up to send an email to the gem5-dev mailing list on success or failure, though once I've confirmed the email notifications are working correctly I'll switch this to send on failure only. The nightly builds will execute every day at 11PM PST (6AM UTC). They take around 6 to 7 hours to complete, therefore normally finishing around 6 to 7 AM PST (1PM to 2PM UTC). The email sent on the failure will list the commits included since the last run (in addition to the stdout/stderr logs, and a link to an archive of the `test/.testing-results` directory) which should help us narrow down any cause-of-failure. In addition to the Nightly Builds, there are also Compile Tests, which I've setup to run every Wednesday. These take roughly 24 hours to complete in our current setups, so expect results on Thursdays. The Compiler Tests simply run the `./util/compiler-tests.sh` script on the develop branch. In short, these run all variants of gem5, ".opt" and '.fast", across all major versions of our supported compilers (not a complete cross product, but decent coverage -- please see the script if you want to know exactly what's run). That's pretty much it for now. We've got plans to expand what's tested in the near future: running more tests, more frequently, as well as improve testing for gem5 in general. I hope this email has given a decent overview of what's going on, but please don't hesitate to get in contact with me if you have any questions. I'd also like to take this opportunity to thank Mike Upton for helping us set up the Jenkins server and deal with all the teething problems. His assistance is much appreciated. Kind regards, Bobby -- Dr. Bobby R. Bruce Room 2235, Kemper Hall, UC Davis Davis, CA, 95616 web: https://www.bobbybruce.net IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Introduce the active boolean for ArmInterruptPin
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31934 )
Change subject: dev-arm: Introduce the active boolean for ArmInterruptPin
..
dev-arm: Introduce the active boolean for ArmInterruptPin
The active boolean will specify if the interrupt line is active
or not (high if it is active high or low if it is active low).
This is decoupled from the interrupt being in a pending state
within the GIC, and it can be used by a peripheral to query the
status of its interrupt pin
Change-Id: I18445b891a75767c8a72e9a7044d6d75fdb7e224
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31934
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/dev/arm/base_gic.cc
M src/dev/arm/base_gic.hh
2 files changed, 28 insertions(+), 2 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/base_gic.cc b/src/dev/arm/base_gic.cc
index a2df8ab..3181dca 100644
--- a/src/dev/arm/base_gic.cc
+++ b/src/dev/arm/base_gic.cc
@@ -121,7 +121,7 @@
ArmInterruptPin::ArmInterruptPin(
Platform *_platform, ThreadContext *tc, uint32_t int_num)
: threadContext(tc), platform(dynamic_cast(_platform)),
-intNum(int_num)
+intNum(int_num), _active(false)
{
fatal_if(!platform, "Interrupt not connected to a RealView platform");
}
@@ -143,6 +143,18 @@
return threadContext->contextId();
}
+void
+ArmInterruptPin::serialize(CheckpointOut &cp) const
+{
+SERIALIZE_SCALAR(_active);
+}
+
+void
+ArmInterruptPin::unserialize(CheckpointIn &cp)
+{
+UNSERIALIZE_SCALAR(_active);
+}
+
ArmSPI::ArmSPI(
Platform *_platform, uint32_t int_num)
: ArmInterruptPin(_platform, nullptr, int_num)
@@ -152,12 +164,14 @@
void
ArmSPI::raise()
{
+_active = true;
platform->gic->sendInt(intNum);
}
void
ArmSPI::clear()
{
+_active = false;
platform->gic->clearInt(intNum);
}
@@ -170,12 +184,14 @@
void
ArmPPI::raise()
{
+_active = true;
platform->gic->sendPPInt(intNum, targetContext());
}
void
ArmPPI::clear()
{
+_active = false;
platform->gic->clearPPInt(intNum, targetContext());
}
diff --git a/src/dev/arm/base_gic.hh b/src/dev/arm/base_gic.hh
index 2f4a1f6..f8fd814 100644
--- a/src/dev/arm/base_gic.hh
+++ b/src/dev/arm/base_gic.hh
@@ -173,7 +173,7 @@
/**
* Generic representation of an Arm interrupt pin.
*/
-class ArmInterruptPin
+class ArmInterruptPin : public Serializable
{
friend class ArmInterruptPinGen;
protected:
@@ -193,11 +193,18 @@
/** Get interrupt number */
uint32_t num() const { return intNum; }
+/** True if interrupt pin is active, false otherwise */
+bool active() const { return _active; }
+
/** Signal an interrupt */
virtual void raise() = 0;
/** Clear a signalled interrupt */
virtual void clear() = 0;
+ public: /* Serializable interface */
+void serialize(CheckpointOut &cp) const override;
+void unserialize(CheckpointIn &cp) override;
+
protected:
/**
* Get the target context ID of this interrupt.
@@ -218,6 +225,9 @@
/** Interrupt number to generate */
const uint32_t intNum;
+
+/** True if interrupt pin is active, false otherwise */
+bool _active;
};
class ArmSPI : public ArmInterruptPin
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31934
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I18445b891a75767c8a72e9a7044d6d75fdb7e224
Gerrit-Change-Number: 31934
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Make Pl011 UART use the ArmInterruptPin
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31935 )
Change subject: dev-arm: Make Pl011 UART use the ArmInterruptPin
..
dev-arm: Make Pl011 UART use the ArmInterruptPin
Change-Id: I995a424491f087b70b72d2558d96c7a472d4abaa
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31935
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/dev/arm/RealView.py
M src/dev/arm/pl011.cc
M src/dev/arm/pl011.hh
3 files changed, 15 insertions(+), 16 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index a22ac4a..b0e8a8e 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -369,14 +369,13 @@
class Pl011(Uart):
type = 'Pl011'
cxx_header = "dev/arm/pl011.hh"
-gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
-int_num = Param.UInt32("Interrupt number that connects to GIC")
+interrupt = Param.ArmInterruptPin("Interrupt that connects to GIC")
end_on_eot = Param.Bool(False, "End the simulation when a EOT is
received on the UART")
int_delay = Param.Latency("100ns", "Time between action and interrupt
generation by UART")
def generateDeviceTree(self, state):
node = self.generateBasicPioDeviceNode(state, 'uart',
self.pio_addr,
- 0x1000, [int(self.int_num)])
+0x1000, [int(self.interrupt.num)])
node.appendCompatible(["arm,pl011", "arm,primecell"])
# Hardcoded reference to the realview platform clocks, because the
@@ -700,7 +699,7 @@
return memories
### Off-chip devices ###
-uart = Pl011(pio_addr=0x1c09, int_num=37)
+uart = Pl011(pio_addr=0x1c09, interrupt=ArmSPI(num=37))
pci_host = GenericPciHost(
conf_base=0x3000, conf_size='256MB', conf_device_bits=16,
pci_pio_base=0)
@@ -1012,10 +1011,14 @@
clock24MHz = SrcClockDomain(clock="24MHz")
uart = [
-Pl011(pio_addr=0x1c09, int_num=37),
-Pl011(pio_addr=0x1c0a, int_num=38, device=Terminal()),
-Pl011(pio_addr=0x1c0b, int_num=39, device=Terminal()),
-Pl011(pio_addr=0x1c0c, int_num=40, device=Terminal())
+Pl011(pio_addr=0x1c09,
+interrupt=ArmSPI(num=37)),
+Pl011(pio_addr=0x1c0a,
+interrupt=ArmSPI(num=38), device=Terminal()),
+Pl011(pio_addr=0x1c0b,
+interrupt=ArmSPI(num=39), device=Terminal()),
+Pl011(pio_addr=0x1c0c,
+interrupt=ArmSPI(num=40), device=Terminal())
]
kmi0 = Pl050(pio_addr=0x1c06, int_num=44, ps2=PS2Keyboard())
diff --git a/src/dev/arm/pl011.cc b/src/dev/arm/pl011.cc
index f24cb61..11485b5 100755
--- a/src/dev/arm/pl011.cc
+++ b/src/dev/arm/pl011.cc
@@ -55,7 +55,7 @@
intEvent([this]{ generateInterrupt(); }, name()),
control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12),
imsc(0), rawInt(0),
- gic(p->gic), endOnEOT(p->end_on_eot), intNum(p->int_num),
+ endOnEOT(p->end_on_eot), interrupt(p->interrupt->get()),
intDelay(p->int_delay)
{
}
@@ -272,7 +272,7 @@
imsc, rawInt, maskInt());
if (maskInt()) {
-gic->sendInt(intNum);
+interrupt->raise();
DPRINTF(Uart, " -- Generated\n");
}
}
@@ -289,7 +289,7 @@
if (!intEvent.scheduled())
schedule(intEvent, curTick() + intDelay);
} else if (old_ints && !maskInt()) {
-gic->clearInt(intNum);
+interrupt->clear();
}
}
diff --git a/src/dev/arm/pl011.hh b/src/dev/arm/pl011.hh
index 81181b7..0ecbe13 100755
--- a/src/dev/arm/pl011.hh
+++ b/src/dev/arm/pl011.hh
@@ -171,14 +171,10 @@
uint16_t rawInt;
protected: // Configuration
-/** Gic to use for interrupting */
-BaseGic * const gic;
-
/** Should the simulation end on an EOT */
const bool endOnEOT;
-/** Interrupt number to generate */
-const int intNum;
+ArmInterruptPin* const interrupt;
/** Delay before interrupting */
const Tick intDelay;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I995a424491f087b70b72d2558d96c7a472d4abaa
Gerrit-Change-Number: 31935
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Make AmbaInt/DmaDevice use the ArmInterruptPin
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31936 )
Change subject: dev-arm: Make AmbaInt/DmaDevice use the ArmInterruptPin
..
dev-arm: Make AmbaInt/DmaDevice use the ArmInterruptPin
Change-Id: I7318b9186cd81f948211e8a955dab7eea6d2a2f5
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31936
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/dev/arm/RealView.py
M src/dev/arm/amba_device.cc
M src/dev/arm/amba_device.hh
M src/dev/arm/hdlcd.cc
M src/dev/arm/kmi.cc
M src/dev/arm/pl111.cc
M src/dev/arm/rtc_pl031.cc
M src/dev/arm/watchdog_sp805.cc
8 files changed, 36 insertions(+), 36 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index b0e8a8e..b3d7305 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -85,8 +85,7 @@
type = 'AmbaIntDevice'
abstract = True
cxx_header = "dev/arm/amba_device.hh"
-gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
-int_num = Param.UInt32("Interrupt number that connects to GIC")
+interrupt = Param.ArmInterruptPin("Interrupt that connects to GIC")
int_delay = Param.Latency("100ns",
"Time between action and interrupt generation by device")
@@ -96,8 +95,7 @@
cxx_header = "dev/arm/amba_device.hh"
pio_addr = Param.Addr("Address for AMBA slave interface")
pio_latency = Param.Latency("10ns", "Time between action and
write/read result by AMBA DMA Device")
-gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
-int_num = Param.UInt32("Interrupt number that connects to GIC")
+interrupt = Param.ArmInterruptPin("Interrupt that connects to GIC")
amba_id = Param.UInt32("ID of AMBA device for kernel detection")
class A9SCU(BasicPioDevice):
@@ -412,7 +410,7 @@
def generateDeviceTree(self, state):
node = self.generateBasicPioDeviceNode(state, 'watchdog',
-self.pio_addr, 0x1000, [int(self.int_num)])
+self.pio_addr, 0x1000, [int(self.interrupt.num)])
node.appendCompatible(['arm,sp805', 'arm,primecell'])
clocks = [state.phandle(self.clk_domain.unproxy(self))]
clock_names = ['wdogclk']
@@ -445,7 +443,7 @@
def generateDeviceTree(self, state):
node = self.generateBasicPioDeviceNode(state, 'rtc', self.pio_addr,
- 0x1000, [int(self.int_num)])
+0x1000, [int(self.interrupt.num)])
node.appendCompatible(["arm,pl031", "arm,primecell"])
clock = state.phandle(self.clk_domain.unproxy(self))
@@ -463,7 +461,7 @@
def generateDeviceTree(self, state):
node = self.generateBasicPioDeviceNode(state, 'kmi', self.pio_addr,
- 0x1000, [int(self.int_num)])
+0x1000, [int(self.interrupt.num)])
node.appendCompatible(["arm,pl050", "arm,primecell"])
clock = state.phandle(self.clk_domain.unproxy(self))
@@ -679,7 +677,7 @@
pio_addr=0x2C08)
hdlcd = HDLcd(pxl_clk=dcc.osc_pxl,
- pio_addr=0x2b00, int_num=117,
+ pio_addr=0x2b00, interrupt=ArmSPI(num=117),
workaround_swap_rb=True)
def _on_chip_devices(self):
@@ -712,9 +710,11 @@
timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C11,
clock0='1MHz', clock1='1MHz')
timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C12,
clock0='1MHz', clock1='1MHz')
-clcd = Pl111(pio_addr=0x1c1f, int_num=46)
-kmi0 = Pl050(pio_addr=0x1c06, int_num=44, ps2=PS2Keyboard())
-kmi1 = Pl050(pio_addr=0x1c07, int_num=45, ps2=PS2TouchKit())
+clcd = Pl111(pio_addr=0x1c1f, interrupt=ArmSPI(num=46))
+kmi0 = Pl050(pio_addr=0x1c06, interrupt=ArmSPI(num=44),
+ ps2=PS2Keyboard())
+kmi1 = Pl050(pio_addr=0x1c07, interrupt=ArmSPI(num=45),
+ ps2=PS2TouchKit())
cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
io_shift = 2, ctrl_offset = 2, Command = 0x1,
BAR0 = 0x1C1A, BAR0Size = '256B',
@@ -725,7 +725,7 @@
conf_table_reported = False)
vram = SimpleMemory(range = AddrRange(0x1800,
size='32MB'),
conf_table_reported = False)
-rtc= PL031(pio_addr=0x1C17, int_num=36)
+rtc= PL031(pio_addr=0x1C17, interrupt=ArmSPI(num=36))
l2x0_fake = IsaFake(pio_addr=0x2C10, pio_size=0xfff)
uart1_fake = AmbaFake(pio_addr=0x1C0A)
@@ -971,7 +971,7 @@
[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Fix DTB autogen for HDLcd
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31940 )
Change subject: dev-arm: Fix DTB autogen for HDLcd
..
dev-arm: Fix DTB autogen for HDLcd
The HDLcd was wrongly reporting the hardcoded IRQ=63 as the interrupt
number during DTB autogeneration. This is because the DTS is using 63.
However that corresponds to the SPI offset; the gem5 helper is
instead expecting the global IRQ number = 32 + SPI offset
Change-Id: I9e82360843eacb13cef5ddd2e28d2f3ef3147335
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31940
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/dev/arm/RealView.py
1 file changed, 1 insertion(+), 2 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index b206a3f..5bfc12e 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -522,9 +522,8 @@
port_node = FdtNode("port")
port_node.append(endpoint_node)
-# Interrupt number is hardcoded; it is not a property of this class
node = self.generateBasicPioDeviceNode(state, 'hdlcd',
- self.pio_addr, 0x1000, [63])
+self.pio_addr, 0x1000, [ self.interrupt.num ])
node.appendCompatible(["arm,hdlcd"])
node.append(FdtPropertyWords("clocks",
state.phandle(self.pxl_clk)))
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31940
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9e82360843eacb13cef5ddd2e28d2f3ef3147335
Gerrit-Change-Number: 31940
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: generateBasicPioDeviceNode requiring an ArmInterruptPin
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31941 )
Change subject: dev-arm: generateBasicPioDeviceNode requiring an
ArmInterruptPin
..
dev-arm: generateBasicPioDeviceNode requiring an ArmInterruptPin
Change-Id: I16ed3b689158defe2a43cccfa053d48dec4a1e41
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31941
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/dev/Device.py
M src/dev/arm/RealView.py
M src/dev/arm/VirtIOMMIO.py
3 files changed, 8 insertions(+), 10 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/Device.py b/src/dev/Device.py
index d42541d..8950763 100644
--- a/src/dev/Device.py
+++ b/src/dev/Device.py
@@ -57,14 +57,14 @@
state.sizeCells(size) ))
if interrupts:
-if any([i < 32 for i in interrupts]):
+if any([i.num < 32 for i in interrupts]):
raise(("Interrupt number smaller than 32 "+
" in PioDevice %s") % name)
# subtracting 32 because Linux assumes that SPIs start at 0,
while
# gem5 uses the internal GIC numbering (SPIs start at 32)
node.append(FdtPropertyWords("interrupts", sum(
-[[0, i - 32, 4] for i in interrupts], []) ))
+[[0, i.num - 32, 4] for i in interrupts], []) ))
return node
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 5bfc12e..684567f 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -373,7 +373,7 @@
def generateDeviceTree(self, state):
node = self.generateBasicPioDeviceNode(state, 'uart',
self.pio_addr,
-0x1000, [int(self.interrupt.num)])
+0x1000, [ self.interrupt ])
node.appendCompatible(["arm,pl011", "arm,primecell"])
# Hardcoded reference to the realview platform clocks, because the
@@ -409,7 +409,7 @@
def generateDeviceTree(self, state):
node = self.generateBasicPioDeviceNode(state, 'watchdog',
-self.pio_addr, 0x1000, [int(self.interrupt.num)])
+self.pio_addr, 0x1000, [ self.interrupt ])
node.appendCompatible(['arm,sp805', 'arm,primecell'])
clocks = [state.phandle(self.clk_domain.unproxy(self))]
clock_names = ['wdogclk']
@@ -442,7 +442,7 @@
def generateDeviceTree(self, state):
node = self.generateBasicPioDeviceNode(state, 'rtc', self.pio_addr,
-0x1000, [int(self.interrupt.num)])
+0x1000, [ self.interrupt ])
node.appendCompatible(["arm,pl031", "arm,primecell"])
clock = state.phandle(self.clk_domain.unproxy(self))
@@ -460,7 +460,7 @@
def generateDeviceTree(self, state):
node = self.generateBasicPioDeviceNode(state, 'kmi', self.pio_addr,
-0x1000, [int(self.interrupt.num)])
+0x1000, [ self.interrupt ])
node.appendCompatible(["arm,pl050", "arm,primecell"])
clock = state.phandle(self.clk_domain.unproxy(self))
@@ -523,7 +523,7 @@
port_node.append(endpoint_node)
node = self.generateBasicPioDeviceNode(state, 'hdlcd',
-self.pio_addr, 0x1000, [ self.interrupt.num ])
+self.pio_addr, 0x1000, [ self.interrupt ])
node.appendCompatible(["arm,hdlcd"])
node.append(FdtPropertyWords("clocks",
state.phandle(self.pxl_clk)))
diff --git a/src/dev/arm/VirtIOMMIO.py b/src/dev/arm/VirtIOMMIO.py
index 919755b..60aee16 100644
--- a/src/dev/arm/VirtIOMMIO.py
+++ b/src/dev/arm/VirtIOMMIO.py
@@ -54,8 +54,6 @@
def generateDeviceTree(self, state):
node = self.generateBasicPioDeviceNode(state, 'virtio',
self.pio_addr,
- int(self.pio_size), [
- int(self.interrupt.num),
- ])
+int(self.pio_size), [ self.interrupt ])
node.appendCompatible(["virtio,mmio"])
yield node
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I16ed3b689158defe2a43cccfa053d48dec4a1e41
Gerrit-Change-Number: 31941
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Make Sp804 use the ArmInterruptPin
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31938 )
Change subject: dev-arm: Make Sp804 use the ArmInterruptPin
..
dev-arm: Make Sp804 use the ArmInterruptPin
Change-Id: I2d71c7e874ba1ec798e2314d7d282cb853b3f360
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31938
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/dev/arm/RealView.py
M src/dev/arm/timer_sp804.cc
M src/dev/arm/timer_sp804.hh
3 files changed, 19 insertions(+), 18 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index b3d7305..b206a3f 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -388,10 +388,9 @@
class Sp804(AmbaPioDevice):
type = 'Sp804'
cxx_header = "dev/arm/timer_sp804.hh"
-gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
-int_num0 = Param.UInt32("Interrupt number that connects to GIC")
+int0 = Param.ArmSPI("Interrupt that connects to GIC")
clock0 = Param.Clock('1MHz', "Clock speed of the input")
-int_num1 = Param.UInt32("Interrupt number that connects to GIC")
+int1 = Param.ArmSPI("Interrupt that connects to GIC")
clock1 = Param.Clock('1MHz', "Clock speed of the input")
amba_id = 0x00141804
@@ -708,8 +707,10 @@
int_virt=ArmPPI(num=27),
int_hyp=ArmPPI(num=26))
-timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C11,
clock0='1MHz', clock1='1MHz')
-timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C12,
clock0='1MHz', clock1='1MHz')
+timer0 = Sp804(int0=ArmSPI(num=34), int1=ArmSPI(num=34),
+ pio_addr=0x1C11, clock0='1MHz', clock1='1MHz')
+timer1 = Sp804(int0=ArmSPI(num=35), int1=ArmSPI(num=35),
+ pio_addr=0x1C12, clock0='1MHz', clock1='1MHz')
clcd = Pl111(pio_addr=0x1c1f, interrupt=ArmSPI(num=46))
kmi0 = Pl050(pio_addr=0x1c06, interrupt=ArmSPI(num=44),
ps2=PS2Keyboard())
diff --git a/src/dev/arm/timer_sp804.cc b/src/dev/arm/timer_sp804.cc
index bf47e6d..dbfa7ff 100644
--- a/src/dev/arm/timer_sp804.cc
+++ b/src/dev/arm/timer_sp804.cc
@@ -46,14 +46,16 @@
#include "mem/packet_access.hh"
Sp804::Sp804(Params *p)
-: AmbaPioDevice(p, 0x1000), gic(p->gic),
- timer0(name() + ".timer0", this, p->int_num0, p->clock0),
- timer1(name() + ".timer1", this, p->int_num1, p->clock1)
+: AmbaPioDevice(p, 0x1000),
+ timer0(name() + ".timer0", this, p->int0->get(), p->clock0),
+ timer1(name() + ".timer1", this, p->int1->get(), p->clock1)
{
}
-Sp804::Timer::Timer(std::string __name, Sp804 *_parent, int int_num, Tick
_clock)
-: _name(__name), parent(_parent), intNum(int_num), clock(_clock),
control(0x20),
+Sp804::Timer::Timer(std::string __name, Sp804 *_parent,
+ArmInterruptPin *_interrupt, Tick _clock)
+: _name(__name), parent(_parent), interrupt(_interrupt),
+ clock(_clock), control(0x20),
rawInt(false), pendingInt(false), loadValue(0x),
zeroEvent([this]{ counterAtZero(); }, name())
{
@@ -158,7 +160,7 @@
if (pendingInt) {
pendingInt = false;
DPRINTF(Timer, "Clearing interrupt\n");
-parent->gic->clearInt(intNum);
+interrupt->clear();
}
break;
case BGLoad:
@@ -205,7 +207,7 @@
pendingInt = true;
if (pendingInt && !old_pending) {
DPRINTF(Timer, "-- Causing interrupt\n");
-parent->gic->sendInt(intNum);
+interrupt->raise();
}
if (control.oneShot)
diff --git a/src/dev/arm/timer_sp804.hh b/src/dev/arm/timer_sp804.hh
index ef586fc..1054b6a 100644
--- a/src/dev/arm/timer_sp804.hh
+++ b/src/dev/arm/timer_sp804.hh
@@ -80,8 +80,8 @@
/** Pointer to parent class */
Sp804 *parent;
-/** Number of interrupt to cause/clear */
-const uint32_t intNum;
+/** Pointer to the interrupt pin */
+ArmInterruptPin * const interrupt;
/** Number of ticks in a clock input */
const Tick clock;
@@ -109,7 +109,8 @@
* @param val the value to start at (pre-16 bit masking if en) */
void restartCounter(uint32_t val);
-Timer(std::string __name, Sp804 *parent, int int_num, Tick clock);
+Timer(std::string __name, Sp804 *parent, ArmInterruptPin
*_interrupt,
+ Tick clock);
std::string name() const { return _name; }
@@ -123,9 +124,6 @@
void unserialize(CheckpointIn &cp) override;
};
-/** Pointer to the GIC for causing an interrupt */
-BaseGic *gic;
-
/** Timers that do the actual work */
Time
[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Make the Sp805 use the new ArmInterruptPin::active
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31939 )
Change subject: dev-arm: Make the Sp805 use the new ArmInterruptPin::active
..
dev-arm: Make the Sp805 use the new ArmInterruptPin::active
Change-Id: I65b53b33e13345eca93a76e82efac7f8c0b97755
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31939
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/dev/arm/watchdog_sp805.cc
M src/dev/arm/watchdog_sp805.hh
2 files changed, 3 insertions(+), 11 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/watchdog_sp805.cc b/src/dev/arm/watchdog_sp805.cc
index bed6258..3fd7006 100644
--- a/src/dev/arm/watchdog_sp805.cc
+++ b/src/dev/arm/watchdog_sp805.cc
@@ -49,7 +49,6 @@
persistedValue(timeoutInterval),
enabled(false),
resetEnabled(false),
- intRaised(false),
writeAccessEnabled(true),
integrationTestEnabled(false),
timeoutEvent([this] { timeoutExpired(); }, name())
@@ -78,10 +77,10 @@
warn("Sp805::read: WO reg (0x%x) [WDOGINTCLR]\n", addr);
break;
case WDOGRIS:
-resp = intRaised;
+resp = interrupt->active();
break;
case WDOGMIS:
-resp = intRaised & enabled;
+resp = interrupt->active() && enabled;
break;
case WDOGLOCK:
resp = writeAccessEnabled;
@@ -210,11 +209,10 @@
{
// If the previously sent interrupt has not been served,
// assert system reset if enabled
-if (intRaised & enabled) {
+if (interrupt->active() && enabled) {
if (resetEnabled)
warn("Watchdog timed out, system reset asserted\n");
} else {
-intRaised = true;
interrupt->raise();
}
}
@@ -222,7 +220,6 @@
void
Sp805::clearInt()
{
-intRaised = false;
interrupt->clear();
}
@@ -234,7 +231,6 @@
SERIALIZE_SCALAR(persistedValue);
SERIALIZE_SCALAR(enabled);
SERIALIZE_SCALAR(resetEnabled);
-SERIALIZE_SCALAR(intRaised);
SERIALIZE_SCALAR(writeAccessEnabled);
SERIALIZE_SCALAR(integrationTestEnabled);
@@ -252,7 +248,6 @@
UNSERIALIZE_SCALAR(persistedValue);
UNSERIALIZE_SCALAR(enabled);
UNSERIALIZE_SCALAR(resetEnabled);
-UNSERIALIZE_SCALAR(intRaised);
UNSERIALIZE_SCALAR(writeAccessEnabled);
UNSERIALIZE_SCALAR(integrationTestEnabled);
diff --git a/src/dev/arm/watchdog_sp805.hh b/src/dev/arm/watchdog_sp805.hh
index c2e99cd..4d9094d 100644
--- a/src/dev/arm/watchdog_sp805.hh
+++ b/src/dev/arm/watchdog_sp805.hh
@@ -93,9 +93,6 @@
/** Indicates if reset behaviour is enabled when counter reaches 0 */
bool resetEnabled;
-/** Indicates if an interrupt has been raised by the counter reaching
0 */
-bool intRaised;
-
/** Indicates if write access to registers is enabled */
bool writeAccessEnabled;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31939
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I65b53b33e13345eca93a76e82efac7f8c0b97755
Gerrit-Change-Number: 31939
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Relax size constraint on AMBA ID registers
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31175 )
Change subject: dev-arm: Relax size constraint on AMBA ID registers
..
dev-arm: Relax size constraint on AMBA ID registers
This patch is allowing non word sized accesses to the AMBA ID
registers.
Change-Id: I61a7163a3b4120e8dbcdbd6d9b83d33a7996f979
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31175
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/dev/arm/amba_device.cc
M src/dev/arm/kmi.cc
M src/dev/arm/pl011.cc
M src/dev/arm/pl111.cc
M src/dev/arm/rtc_pl031.cc
5 files changed, 6 insertions(+), 6 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/amba_device.cc b/src/dev/arm/amba_device.cc
index 2ab2743..76872b1 100644
--- a/src/dev/arm/amba_device.cc
+++ b/src/dev/arm/amba_device.cc
@@ -80,7 +80,7 @@
DPRINTF(AMBA, "Returning %#x for offset %#x(%d)\n",
(amba_id >> byte) & 0xFF,
pkt->getAddr() - pio_addr, byte);
-assert(pkt->getSize() == 4);
-pkt->setLE((amba_id >> byte) & 0xFF);
+
+pkt->setUintX((amba_id >> byte) & 0xFF, LittleEndianByteOrder);
return true;
}
diff --git a/src/dev/arm/kmi.cc b/src/dev/arm/kmi.cc
index 9d991c3..246fedb 100644
--- a/src/dev/arm/kmi.cc
+++ b/src/dev/arm/kmi.cc
@@ -95,7 +95,7 @@
default:
if (readId(pkt, ambaId, pioAddr)) {
// Hack for variable size accesses
-data = pkt->getLE();
+data = pkt->getUintX(LittleEndianByteOrder);
break;
}
diff --git a/src/dev/arm/pl011.cc b/src/dev/arm/pl011.cc
index 11485b5..a60276d 100755
--- a/src/dev/arm/pl011.cc
+++ b/src/dev/arm/pl011.cc
@@ -137,7 +137,7 @@
default:
if (readId(pkt, AMBA_ID, pioAddr)) {
// Hack for variable size accesses
-data = pkt->getLE();
+data = pkt->getUintX(LittleEndianByteOrder);
break;
}
diff --git a/src/dev/arm/pl111.cc b/src/dev/arm/pl111.cc
index f2b8e50..27606e1 100644
--- a/src/dev/arm/pl111.cc
+++ b/src/dev/arm/pl111.cc
@@ -182,7 +182,7 @@
default:
if (readId(pkt, AMBA_ID, pioAddr)) {
// Hack for variable size accesses
-data = pkt->getLE();
+data = pkt->getUintX(LittleEndianByteOrder);
break;
} else if (daddr >= CrsrImage && daddr <= 0xBFC) {
// CURSOR IMAGE
diff --git a/src/dev/arm/rtc_pl031.cc b/src/dev/arm/rtc_pl031.cc
index 713d3f7..b2b2322 100644
--- a/src/dev/arm/rtc_pl031.cc
+++ b/src/dev/arm/rtc_pl031.cc
@@ -90,7 +90,7 @@
default:
if (readId(pkt, ambaId, pioAddr)) {
// Hack for variable sized access
-data = pkt->getLE();
+data = pkt->getUintX(LittleEndianByteOrder);
break;
}
panic("Tried to read PL031 at offset %#x that doesn't exist\n",
daddr);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31175
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I61a7163a3b4120e8dbcdbd6d9b83d33a7996f979
Gerrit-Change-Number: 31175
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Avoid code duplication in Pl111
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31176 )
Change subject: dev-arm: Avoid code duplication in Pl111
..
dev-arm: Avoid code duplication in Pl111
Change-Id: I17af93459ace0e4ef82693622a4135c3e831aaf5
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31176
Reviewed-by: Bobby R. Bruce
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/dev/arm/pl111.cc
1 file changed, 2 insertions(+), 31 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/pl111.cc b/src/dev/arm/pl111.cc
index 27606e1..111de03 100644
--- a/src/dev/arm/pl111.cc
+++ b/src/dev/arm/pl111.cc
@@ -203,21 +203,7 @@
}
}
-switch(pkt->getSize()) {
- case 1:
-pkt->setLE(data);
-break;
- case 2:
-pkt->setLE(data);
-break;
- case 4:
-pkt->setLE(data);
-break;
- default:
-panic("CLCD controller read size too big?\n");
-break;
-}
-
+pkt->setUintX(data, LittleEndianByteOrder);
pkt->makeAtomicResponse();
return pioDelay;
}
@@ -229,22 +215,7 @@
// use a temporary data since the LCD registers are read/written with
// different size operations
//
-uint32_t data = 0;
-
-switch(pkt->getSize()) {
- case 1:
-data = pkt->getLE();
-break;
- case 2:
-data = pkt->getLE();
-break;
- case 4:
-data = pkt->getLE();
-break;
- default:
-panic("PL111 CLCD controller write size too big?\n");
-break;
-}
+const uint32_t data = pkt->getUintX(LittleEndianByteOrder);
assert(pkt->getAddr() >= pioAddr &&
pkt->getAddr() < pioAddr + pioSize);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31176
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I17af93459ace0e4ef82693622a4135c3e831aaf5
Gerrit-Change-Number: 31176
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Re: testlib question
For those interested in the outcome of this. Hoa opened a Jira ticket,
https://gem5.atlassian.net/browse/GEM5-709, and found a fix for this issue,
currently under review here:
https://gem5-review.googlesource.com/c/public/gem5/+/31994
--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616
web: https://www.bobbybruce.net
On Wed, Jul 29, 2020 at 10:43 AM mike upton via gem5-dev
wrote:
> My Jenkins setup is getting errors in testlib.
>
>
> The test is failing, and trying to call test.fail
>
> from the results.pickle file:
>
>
> File "/var/lib/jenkins/workspace/stress/tests/../ext/testlib/runner.py", line
> 146, in test
> test_params.test.test(test_params)
> File "/var/lib/jenkins/workspace/stress/tests/../ext/testlib/wrappers.py",
> line 147, in test
> self.obj.test(*args, **kwargs)
> File "/var/lib/jenkins/workspace/stress/tests/../ext/testlib/test_util.py",
> line 69, in test
> self.test_function(*args, **kwargs)
> File "/var/lib/jenkins/workspace/stress/tests/gem5/verifier.py", line 43,
> in _test
> self.test(*args, **kwargs)
> File "/var/lib/jenkins/workspace/stress/tests/gem5/verifier.py", line 83,
> in test
> test.fail('Stdout did not match:\n%s\nSee %s for full results'
> AttributeError: module 'testlib.test_util' has no attribute 'fail'
>
>
> Any ideas about how to fix? I am not familiar with testlib.
>
> I would like to see the error message it is trying to print.
>
>
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[gem5-dev] Change in gem5/gem5[develop]: tests: fix name collisions in verifier.py
Hoa Nguyen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31994 )
Change subject: tests: fix name collisions in verifier.py
..
tests: fix name collisions in verifier.py
In verifier.py, testlib.test_util is imported and renamed to 'test',
while several functions in the file have a subfunction named 'test()',
which causes test.fail() to fail as 'test' points to the
subfunction instead of the module.
This commit addresses the above issue by keeping the imported module
as test_util instead of renaming it to test.
Signed-off-by: Hoa Nguyen
Change-Id: I0ab7b52619f2fa9495e9a6ff8d469c022eea98bc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31994
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M tests/gem5/verifier.py
1 file changed, 4 insertions(+), 4 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/tests/gem5/verifier.py b/tests/gem5/verifier.py
index 815b9bb..ba4bd4f 100644
--- a/tests/gem5/verifier.py
+++ b/tests/gem5/verifier.py
@@ -29,7 +29,7 @@
'''
import re
-from testlib import test_util as test
+from testlib import test_util
from testlib.configuration import constants
from testlib.helper import joinpath, diff_out_file
@@ -44,7 +44,7 @@
def instantiate_test(self, name_pfx):
name = '-'.join([name_pfx, self.__class__.__name__])
-return test.TestFunction(self._test,
+return test_util.TestFunction(self._test,
name=name, fixtures=self.fixtures)
class MatchGoldStandard(Verifier):
@@ -80,7 +80,7 @@
ignore_regexes=self.ignore_regex,
logger=params.log)
if diff is not None:
-test.fail('Stdout did not match:\n%s\nSee %s for full results'
+test_util.fail('Stdout did not match:\n%s\nSee %s for full
results'
% (diff, tempdir))
def _generic_instance_warning(self, kwargs):
@@ -184,7 +184,7 @@
if parse_file(joinpath(tempdir,
constants.gem5_simulation_stderr)):
return # Success
-test.fail('Could not match regex.')
+test_util.fail('Could not match regex.')
_re_type = type(re.compile(''))
def _iterable_regex(regex):
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0ab7b52619f2fa9495e9a6ff8d469c022eea98bc
Gerrit-Change-Number: 31994
Gerrit-PatchSet: 4
Gerrit-Owner: Hoa Nguyen
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Hoa Nguyen
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-Reviewer: mike upton
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3: add support for flat atomic adds, subs, incs, decs
Matt Sinclair has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31974 )
Change subject: arch-gcn3: add support for flat atomic adds, subs, incs,
decs
..
arch-gcn3: add support for flat atomic adds, subs, incs, decs
Add support for all missing flat atomic adds, subtracts, increments,
and decrements, including their x2 variants.
Change-Id: I37a67fcacca91a09a82be6597facaa366105d2dc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31974
Reviewed-by: Anthony Gutierrez
Maintainer: Anthony Gutierrez
Tested-by: kokoro
---
M src/arch/gcn3/insts/instructions.cc
M src/arch/gcn3/insts/instructions.hh
2 files changed, 410 insertions(+), 6 deletions(-)
Approvals:
Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/gcn3/insts/instructions.cc
b/src/arch/gcn3/insts/instructions.cc
index 426f991..6e81e2c 100644
--- a/src/arch/gcn3/insts/instructions.cc
+++ b/src/arch/gcn3/insts/instructions.cc
@@ -40643,8 +40643,72 @@
void
Inst_FLAT__FLAT_ATOMIC_SUB::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+Wavefront *wf = gpuDynInst->wavefront();
+
+if (wf->execMask().none()) {
+wf->decVMemInstsIssued();
+wf->decLGKMInstsIssued();
+wf->wrGmReqsInPipe--;
+wf->rdGmReqsInPipe--;
+return;
+}
+
+gpuDynInst->execUnitId = wf->execUnitId;
+gpuDynInst->exec_mask = wf->execMask();
+gpuDynInst->latency.init(gpuDynInst->computeUnit());
+gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
+ConstVecOperandU32 data(gpuDynInst, extData.DATA);
+
+addr.read();
+data.read();
+
+calcAddr(gpuDynInst, addr);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+(reinterpret_cast(gpuDynInst->a_data))[lane]
+= data[lane];
+}
+}
+
+if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
+gpuDynInst->computeUnit()->globalMemoryPipe.
+issueRequest(gpuDynInst);
+wf->wrGmReqsInPipe--;
+wf->outstandingReqsWrGm++;
+wf->rdGmReqsInPipe--;
+wf->outstandingReqsRdGm++;
+} else {
+fatal("Non global flat instructions not implemented yet.\n");
+}
+
+gpuDynInst->wavefront()->outstandingReqs++;
+gpuDynInst->wavefront()->validateRequestCounters();
}
+void
+Inst_FLAT__FLAT_ATOMIC_SUB::initiateAcc(GPUDynInstPtr gpuDynInst)
+{
+initAtomicAccess(gpuDynInst);
+} // initiateAcc
+
+void
+Inst_FLAT__FLAT_ATOMIC_SUB::completeAcc(GPUDynInstPtr gpuDynInst)
+{
+if (isAtomicRet()) {
+VecOperandU32 vdst(gpuDynInst, extData.VDST);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+vdst[lane] = (reinterpret_cast(
+gpuDynInst->d_data))[lane];
+}
+}
+
+vdst.write();
+}
+} // completeAcc
Inst_FLAT__FLAT_ATOMIC_SMIN::Inst_FLAT__FLAT_ATOMIC_SMIN(InFmt_FLAT
*iFmt)
: Inst_FLAT(iFmt, "flat_atomic_smin")
@@ -40843,9 +40907,74 @@
void
Inst_FLAT__FLAT_ATOMIC_INC::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+Wavefront *wf = gpuDynInst->wavefront();
+
+if (wf->execMask().none()) {
+wf->decVMemInstsIssued();
+wf->decLGKMInstsIssued();
+wf->wrGmReqsInPipe--;
+wf->rdGmReqsInPipe--;
+return;
+}
+
+gpuDynInst->execUnitId = wf->execUnitId;
+gpuDynInst->exec_mask = wf->execMask();
+gpuDynInst->latency.init(gpuDynInst->computeUnit());
+gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
+ConstVecOperandU32 data(gpuDynInst, extData.DATA);
+
+addr.read();
+data.read();
+
+calcAddr(gpuDynInst, addr);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+(reinterpret_cast(gpuDynInst->a_data))[lane]
+= data[lane];
+}
+}
+
+if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
+gpuDynInst->computeUnit()->globalMemoryPipe.
+issueRequest(gpuDynInst);
+wf->wrGmReqsInPipe--;
+wf->outstandingReqsWrGm++;
+wf->rdGmReqsInPipe--;
+wf->outstandingReqsRdGm++;
+} else {
+fatal("Non global flat instructions not
