[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Fix switch storage in SimpleNetwork
Meatboy 106 has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/55723 )
Change subject: mem-ruby: Fix switch storage in SimpleNetwork
..
mem-ruby: Fix switch storage in SimpleNetwork
In SimpleNetwork, switches were assigned an index depending on their
position in params().routers. But switches are also referenced by their
router_id parameter in other locations of the ruby network system (e.g.,
src and dst node parameter in links). If the router_id does not match the
position in SimpleNetwork::m_switches, the network initialization might
fail or implement a different topology from what the user intended. This
patch fixes this issue by storing switches in a map instead of a vector.
Change-Id: I398f950ad404efbf9516ea9bbced598970a2bc24
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55723
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/network/simple/SimpleNetwork.cc
M src/mem/ruby/network/simple/SimpleNetwork.hh
2 files changed, 35 insertions(+), 14 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc
b/src/mem/ruby/network/simple/SimpleNetwork.cc
index 8e10081..ce7bf2c 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.cc
+++ b/src/mem/ruby/network/simple/SimpleNetwork.cc
@@ -66,9 +66,10 @@
// record the routers
for (std::vector::const_iterator i = p.routers.begin();
i != p.routers.end(); ++i) {
-Switch* s = safe_cast(*i);
-m_switches.push_back(s);
+auto* s = safe_cast(*i);
s->init_net_ptr(this);
+auto id = static_cast(s->params().router_id);
+m_switches[id] = s;
}
const std::vector _vnets_channels =
@@ -108,7 +109,6 @@
{
NodeID local_dest = getLocalNodeID(global_dest);
assert(local_dest < m_nodes);
-assert(src < m_switches.size());
assert(m_switches[src] != NULL);
SimpleExtLink *simple_link = safe_cast(link);
@@ -179,9 +179,9 @@
;
// Now state what the formula is.
-for (int i = 0; i < m_switches.size(); i++) {
+for (auto& [id, sw]: m_switches) {
*(networkStats.m_msg_counts[(unsigned int) type]) +=
-sum(m_switches[i]->getMsgCount(type));
+sum(sw->getMsgCount(type));
}
*(networkStats.m_msg_bytes[(unsigned int) type]) =
@@ -193,8 +193,8 @@
void
SimpleNetwork::collateStats()
{
-for (int i = 0; i < m_switches.size(); i++) {
-m_switches[i]->collateStats();
+for (auto& [id, sw]: m_switches) {
+sw->collateStats();
}
}
@@ -212,8 +212,8 @@
bool
SimpleNetwork::functionalRead(Packet *pkt)
{
-for (unsigned int i = 0; i < m_switches.size(); i++) {
-if (m_switches[i]->functionalRead(pkt))
+for (auto& [id, sw]: m_switches) {
+if (sw->functionalRead(pkt))
return true;
}
for (unsigned int i = 0; i < m_int_link_buffers.size(); ++i) {
@@ -228,8 +228,8 @@
SimpleNetwork::functionalRead(Packet *pkt, WriteMask )
{
bool read = false;
-for (unsigned int i = 0; i < m_switches.size(); i++) {
-if (m_switches[i]->functionalRead(pkt, mask))
+for (auto& [id, sw]: m_switches) {
+if (sw->functionalRead(pkt, mask))
read = true;
}
for (unsigned int i = 0; i < m_int_link_buffers.size(); ++i) {
@@ -244,8 +244,8 @@
{
uint32_t num_functional_writes = 0;
-for (unsigned int i = 0; i < m_switches.size(); i++) {
-num_functional_writes += m_switches[i]->functionalWrite(pkt);
+for (auto& [id, sw]: m_switches) {
+num_functional_writes += sw->functionalWrite(pkt);
}
for (unsigned int i = 0; i < m_int_link_buffers.size(); ++i) {
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.hh
b/src/mem/ruby/network/simple/SimpleNetwork.hh
index e336492..b90ee33 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.hh
+++ b/src/mem/ruby/network/simple/SimpleNetwork.hh
@@ -102,7 +102,7 @@
SimpleNetwork(const SimpleNetwork& obj);
SimpleNetwork& operator=(const SimpleNetwork& obj);
-std::vector m_switches;
+std::unordered_map m_switches;
std::vector m_int_link_buffers;
const int m_buffer_size;
const int m_endpoint_bandwidth;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/55723
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I398f950ad404efbf9516ea9bbced598970a2bc24
Gerrit-Change-Number: 55723
Gerrit-PatchSet: 6
Gerrit-Owner: Meatboy 106
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Meatboy 106
Gerrit-Reviewer:
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: refactor SimpleNetwork buffers
Tiago Muck has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41859 )
(
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: mem-ruby: refactor SimpleNetwork buffers
..
mem-ruby: refactor SimpleNetwork buffers
This removes the int_link_buffers param from SimpleNetwork. Internal
link buffers are now created as children of SimpleIntLink objects.
This results in a cleaner configuration and simplifies some code in
SimpleNetwork.cc.
setup_buffers is also split between Switch.setup_buffers and
SimpleIntLink.setup_buffers for clarity.
JIRA: https://gem5.atlassian.net/browse/GEM5-920
Change-Id: I68ad36ec0e682b8d5600c2950bcb56debe186af3
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41859
Reviewed-by: Meatboy 106
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/network/BasicLink.py
M src/mem/ruby/network/simple/SimpleLink.cc
M src/mem/ruby/network/simple/SimpleLink.hh
M src/mem/ruby/network/simple/SimpleLink.py
M src/mem/ruby/network/simple/SimpleNetwork.cc
M src/mem/ruby/network/simple/SimpleNetwork.hh
M src/mem/ruby/network/simple/SimpleNetwork.py
7 files changed, 136 insertions(+), 58 deletions(-)
Approvals:
Meatboy 106: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/network/BasicLink.py
b/src/mem/ruby/network/BasicLink.py
index 39f2282..5c5fcca 100644
--- a/src/mem/ruby/network/BasicLink.py
+++ b/src/mem/ruby/network/BasicLink.py
@@ -37,6 +37,10 @@
# Width of the link in bytes
# Only used by simple network.
# Garnet models this by flit size
+# For the simple links, the bandwidth factor translates to the
+# bandwidth multiplier. The multipiler, in combination with the
+# endpoint bandwidth multiplier - message size multiplier ratio,
+# determines the link bandwidth in bytes
bandwidth_factor = Param.Int("generic bandwidth factor, usually in
bytes")
weight = Param.Int(1, "used to restrict routing in shortest path
analysis")
supported_vnets = VectorParam.Int([], "Vnets supported
Default:All([])")
diff --git a/src/mem/ruby/network/simple/SimpleLink.cc
b/src/mem/ruby/network/simple/SimpleLink.cc
index 0f55545..8aea3f3 100644
--- a/src/mem/ruby/network/simple/SimpleLink.cc
+++ b/src/mem/ruby/network/simple/SimpleLink.cc
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2021 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2011 Advanced Micro Devices, Inc.
* All rights reserved.
*
@@ -51,13 +63,11 @@
}
SimpleIntLink::SimpleIntLink(const Params )
-: BasicIntLink(p)
+: BasicIntLink(p),
+ m_bw_multiplier(p.bandwidth_factor),
+ m_buffers(p.buffers)
{
-// For the simple links, the bandwidth factor translates to the
-// bandwidth multiplier. The multipiler, in combination with the
-// endpoint bandwidth multiplier - message size multiplier ratio,
-// determines the link bandwidth in bytes
-m_bw_multiplier = p.bandwidth_factor;
+
}
void
diff --git a/src/mem/ruby/network/simple/SimpleLink.hh
b/src/mem/ruby/network/simple/SimpleLink.hh
index 2f2582c..a311392 100644
--- a/src/mem/ruby/network/simple/SimpleLink.hh
+++ b/src/mem/ruby/network/simple/SimpleLink.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2021 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2011 Advanced Micro Devices, Inc.
* All rights reserved.
*
@@ -73,6 +85,7 @@
void print(std::ostream& out) const;
int m_bw_multiplier;
+const std::vector m_buffers;
};
inline std::ostream&
diff --git a/src/mem/ruby/network/simple/SimpleLink.py
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: int/ext SimpleNetwork routing latency
Tiago Muck has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41861 )
(
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: mem-ruby: int/ext SimpleNetwork routing latency
..
mem-ruby: int/ext SimpleNetwork routing latency
One now may specify separate routing latencies for internal and
external links using the router's int_routing_latency and
ext_routing_latency, respectively.
JIRA: https://gem5.atlassian.net/browse/GEM5-920
Change-Id: I5532668bf23fc61d02b978bfd9479023a6ce2b16
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41861
Reviewed-by: Meatboy 106
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/network/simple/PerfectSwitch.cc
M src/mem/ruby/network/simple/PerfectSwitch.hh
M src/mem/ruby/network/simple/SimpleNetwork.cc
M src/mem/ruby/network/simple/SimpleNetwork.py
M src/mem/ruby/network/simple/Switch.cc
M src/mem/ruby/network/simple/Switch.hh
6 files changed, 54 insertions(+), 14 deletions(-)
Approvals:
Meatboy 106: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/network/simple/PerfectSwitch.cc
b/src/mem/ruby/network/simple/PerfectSwitch.cc
index 19e1523..665fd0f 100644
--- a/src/mem/ruby/network/simple/PerfectSwitch.cc
+++ b/src/mem/ruby/network/simple/PerfectSwitch.cc
@@ -96,6 +96,7 @@
PerfectSwitch::addOutPort(const std::vector& out,
const NetDest& routing_table_entry,
const PortDirection _inport,
+ Tick routing_latency,
int link_weight)
{
// Add to routing unit
@@ -104,7 +105,7 @@
routing_table_entry,
dst_inport,
link_weight);
-m_out.push_back(out);
+m_out.push_back({routing_latency, out});
}
PerfectSwitch::~PerfectSwitch()
@@ -182,8 +183,9 @@
bool enough = true;
for (int i = 0; i < output_links.size(); i++) {
int outgoing = output_links[i].m_link_id;
+OutputPort _port = m_out[outgoing];
-if (!m_out[outgoing][vnet]->areNSlotsAvailable(1,
current_time))
+if (!out_port.buffers[vnet]->areNSlotsAvailable(1,
current_time))
enough = false;
DPRINTF(RubyNetwork, "Checking if node is blocked ..."
@@ -220,6 +222,7 @@
// Enqueue it - for all outgoing queues
for (int i=0; i 0) {
// create a private copy of the unmodified message
@@ -236,8 +239,8 @@
"inport[%d][%d] to outport [%d][%d].\n",
incoming, vnet, outgoing, vnet);
-m_out[outgoing][vnet]->enqueue(msg_ptr, current_time,
- m_switch->latencyTicks());
+out_port.buffers[vnet]->enqueue(msg_ptr, current_time,
+ out_port.latency);
}
}
}
diff --git a/src/mem/ruby/network/simple/PerfectSwitch.hh
b/src/mem/ruby/network/simple/PerfectSwitch.hh
index 41e9448..446ae83 100644
--- a/src/mem/ruby/network/simple/PerfectSwitch.hh
+++ b/src/mem/ruby/network/simple/PerfectSwitch.hh
@@ -80,6 +80,7 @@
void addOutPort(const std::vector& out,
const NetDest& routing_table_entry,
const PortDirection _inport,
+Tick routing_latency,
int link_weight);
int getInLinks() const { return m_in.size(); }
@@ -103,9 +104,16 @@
const SwitchID m_switch_id;
Switch * const m_switch;
-// vector of queues from the components
+// Vector of queues associated to each port.
std::vector > m_in;
-std::vector > m_out;
+
+// Each output port also has a latency for routing to that port
+struct OutputPort
+{
+Tick latency;
+std::vector buffers;
+};
+std::vector m_out;
uint32_t m_virtual_networks;
int m_wakeups_wo_switch;
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc
b/src/mem/ruby/network/simple/SimpleNetwork.cc
index ec3a25e..8e10081 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.cc
+++ b/src/mem/ruby/network/simple/SimpleNetwork.cc
@@ -122,7 +122,7 @@
m_switches[src]->addOutPort(m_fromNetQueues[local_dest],
routing_table_entry[0],
simple_link->m_latency, 0,
-simple_link->m_bw_multiplier);
+simple_link->m_bw_multiplier, true);
}
// From an endpoint node to a switch
@@ -150,6 +150,7 @@
simple_link->m_latency,
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: add priorities in SimpleNetwork routing
Tiago Muck has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41864 )
(
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: mem-ruby: add priorities in SimpleNetwork routing
..
mem-ruby: add priorities in SimpleNetwork routing
Configurations can specify a routing priority for message buffers.
This priority is used by SimpleNetwork when checking for messages
in the routers' input ports. Higher priority ports are always checked
first.
JIRA: https://gem5.atlassian.net/browse/GEM5-920
Change-Id: I7e2b35e2cae63086a76def1145f9b4b56220a2ba
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41864
Reviewed-by: Meatboy 106
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/network/MessageBuffer.cc
M src/mem/ruby/network/MessageBuffer.hh
M src/mem/ruby/network/MessageBuffer.py
M src/mem/ruby/network/simple/PerfectSwitch.cc
M src/mem/ruby/network/simple/PerfectSwitch.hh
5 files changed, 80 insertions(+), 13 deletions(-)
Approvals:
Meatboy 106: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/network/MessageBuffer.cc
b/src/mem/ruby/network/MessageBuffer.cc
index a891d5a..9a65009 100644
--- a/src/mem/ruby/network/MessageBuffer.cc
+++ b/src/mem/ruby/network/MessageBuffer.cc
@@ -65,6 +65,7 @@
m_last_arrival_time(0), m_strict_fifo(p.ordered),
m_randomization(p.randomization),
m_allow_zero_latency(p.allow_zero_latency),
+m_routing_priority(p.routing_priority),
ADD_STAT(m_not_avail_count, statistics::units::Count::get(),
"Number of times this buffer did not have N slots available"),
ADD_STAT(m_msg_count, statistics::units::Count::get(),
diff --git a/src/mem/ruby/network/MessageBuffer.hh
b/src/mem/ruby/network/MessageBuffer.hh
index 9cabbaf..2795993 100644
--- a/src/mem/ruby/network/MessageBuffer.hh
+++ b/src/mem/ruby/network/MessageBuffer.hh
@@ -158,6 +158,9 @@
void setIncomingLink(int link_id) { m_input_link_id = link_id; }
void setVnet(int net) { m_vnet_id = net; }
+int getIncomingLink() const { return m_input_link_id; }
+int getVnet() const { return m_vnet_id; }
+
Port &
getPort(const std::string &, PortID idx=InvalidPortID) override
{
@@ -187,6 +190,8 @@
return functionalAccess(pkt, true, ) == 1;
}
+int routingPriority() const { return m_routing_priority; }
+
private:
void reanalyzeList(std::list &, Tick);
@@ -270,6 +275,8 @@
const MessageRandomization m_randomization;
const bool m_allow_zero_latency;
+const int m_routing_priority;
+
int m_input_link_id;
int m_vnet_id;
diff --git a/src/mem/ruby/network/MessageBuffer.py
b/src/mem/ruby/network/MessageBuffer.py
index 80dc872..b776196 100644
--- a/src/mem/ruby/network/MessageBuffer.py
+++ b/src/mem/ruby/network/MessageBuffer.py
@@ -70,3 +70,6 @@
max_dequeue_rate = Param.Unsigned(0, "Maximum number of messages that
can \
be dequeued per cycle \
(0 allows dequeueing all ready
messages)")
+routing_priority = Param.Int(0, "Buffer priority when messages are \
+ consumed by the network. Smaller
value \
+ means higher priority")
diff --git a/src/mem/ruby/network/simple/PerfectSwitch.cc
b/src/mem/ruby/network/simple/PerfectSwitch.cc
index 665fd0f..74d78e3 100644
--- a/src/mem/ruby/network/simple/PerfectSwitch.cc
+++ b/src/mem/ruby/network/simple/PerfectSwitch.cc
@@ -88,11 +88,37 @@
in[i]->setConsumer(this);
in[i]->setIncomingLink(port);
in[i]->setVnet(i);
+updatePriorityGroups(i, in[i]);
}
}
}
void
+PerfectSwitch::updatePriorityGroups(int vnet, MessageBuffer* in_buf)
+{
+while (m_in_prio.size() <= vnet) {
+m_in_prio.emplace_back();
+m_in_prio_groups.emplace_back();
+}
+
+m_in_prio[vnet].push_back(in_buf);
+
+std::sort(m_in_prio[vnet].begin(), m_in_prio[vnet].end(),
+[](const MessageBuffer* i, const MessageBuffer* j)
+{ return i->routingPriority() < j->routingPriority(); });
+
+// reset groups
+m_in_prio_groups[vnet].clear();
+int cur_prio = m_in_prio[vnet].front()->routingPriority();
+m_in_prio_groups[vnet].emplace_back();
+for (auto buf : m_in_prio[vnet]) {
+if (buf->routingPriority() != cur_prio)
+m_in_prio_groups[vnet].emplace_back();
+m_in_prio_groups[vnet].back().push_back(buf);
+}
+}
+
+void
PerfectSwitch::addOutPort(const std::vector& out,
const NetDest& routing_table_entry,
const PortDirection _inport,
@@ -126,12
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix SimpleNetwork WeightBased routing
Tiago Muck has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41860 )
Change subject: mem-ruby: fix SimpleNetwork WeightBased routing
..
mem-ruby: fix SimpleNetwork WeightBased routing
Individual link weights are propagated to the routing algorithms and
WeightBased routing now uses this information to select the output
link when multiple routing options exist.
JIRA: https://gem5.atlassian.net/browse/GEM5-920
Change-Id: I86a4deb610a1b94abf745e9ef249961fb52e9800
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41860
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/network/simple/PerfectSwitch.cc
M src/mem/ruby/network/simple/PerfectSwitch.hh
M src/mem/ruby/network/simple/SimpleNetwork.cc
M src/mem/ruby/network/simple/Switch.cc
M src/mem/ruby/network/simple/Switch.hh
M src/mem/ruby/network/simple/routing/BaseRoutingUnit.hh
M src/mem/ruby/network/simple/routing/WeightBased.cc
M src/mem/ruby/network/simple/routing/WeightBased.hh
8 files changed, 53 insertions(+), 18 deletions(-)
Approvals:
Tiago Muck: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/network/simple/PerfectSwitch.cc
b/src/mem/ruby/network/simple/PerfectSwitch.cc
index 154e491..19e1523 100644
--- a/src/mem/ruby/network/simple/PerfectSwitch.cc
+++ b/src/mem/ruby/network/simple/PerfectSwitch.cc
@@ -95,13 +95,15 @@
void
PerfectSwitch::addOutPort(const std::vector& out,
const NetDest& routing_table_entry,
- const PortDirection _inport)
+ const PortDirection _inport,
+ int link_weight)
{
// Add to routing unit
m_switch->getRoutingUnit().addOutPort(m_out.size(),
out,
routing_table_entry,
- dst_inport);
+ dst_inport,
+ link_weight);
m_out.push_back(out);
}
diff --git a/src/mem/ruby/network/simple/PerfectSwitch.hh
b/src/mem/ruby/network/simple/PerfectSwitch.hh
index d6c836b..41e9448 100644
--- a/src/mem/ruby/network/simple/PerfectSwitch.hh
+++ b/src/mem/ruby/network/simple/PerfectSwitch.hh
@@ -79,7 +79,8 @@
void addInPort(const std::vector& in);
void addOutPort(const std::vector& out,
const NetDest& routing_table_entry,
-const PortDirection _inport);
+const PortDirection _inport,
+int link_weight);
int getInLinks() const { return m_in.size(); }
int getOutLinks() const { return m_out.size(); }
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc
b/src/mem/ruby/network/simple/SimpleNetwork.cc
index c30bd79..ec3a25e 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.cc
+++ b/src/mem/ruby/network/simple/SimpleNetwork.cc
@@ -120,7 +120,8 @@
m_fromNetQueues[local_dest].resize(num_vnets, nullptr);
m_switches[src]->addOutPort(m_fromNetQueues[local_dest],
-routing_table_entry[0],
simple_link->m_latency,
+routing_table_entry[0],
+simple_link->m_latency, 0,
simple_link->m_bw_multiplier);
}
@@ -147,6 +148,7 @@
m_switches[dest]->addInPort(simple_link->m_buffers);
m_switches[src]->addOutPort(simple_link->m_buffers,
routing_table_entry[0],
simple_link->m_latency,
+simple_link->m_weight,
simple_link->m_bw_multiplier,
dst_inport);
// Maitain a global list of buffers (used for functional accesses only)
diff --git a/src/mem/ruby/network/simple/Switch.cc
b/src/mem/ruby/network/simple/Switch.cc
index 8c0b229..fd43910 100644
--- a/src/mem/ruby/network/simple/Switch.cc
+++ b/src/mem/ruby/network/simple/Switch.cc
@@ -85,7 +85,8 @@
void
Switch::addOutPort(const std::vector& out,
const NetDest& routing_table_entry,
- Cycles link_latency, int bw_multiplier,
+ Cycles link_latency, int link_weight,
+ int bw_multiplier,
PortDirection dst_inport)
{
const std::vector _vnets_channels =
@@ -122,7 +123,7 @@
// Hook the queues to the PerfectSwitch
perfectSwitch.addOutPort(intermediateBuffers, routing_table_entry,
-dst_inport);
+ dst_inport, link_weight);
// Hook the queues to the Throttle
throttles.back().addLinks(intermediateBuffers, out);
diff --git a/src/mem/ruby/network/simple/Switch.hh
b/src/mem/ruby/network/simple/Switch.hh
index
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: additional SimpleNetwork stats
Tiago Muck has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41865 )
(
4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: mem-ruby: additional SimpleNetwork stats
..
mem-ruby: additional SimpleNetwork stats
Additional stats allow more detailed monitoring of switch bandwidth
and stalls.
Also cleaned up previous Throttle stats to match new stat API.
JIRA: https://gem5.atlassian.net/browse/GEM5-920
Change-Id: I56604f315024f19df5f89c6f6ea1e3aa0ea185ea
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41865
Reviewed-by: Meatboy 106
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/network/simple/Switch.cc
M src/mem/ruby/network/simple/Throttle.cc
M src/mem/ruby/network/simple/Throttle.hh
3 files changed, 126 insertions(+), 79 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Meatboy 106: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/network/simple/Switch.cc
b/src/mem/ruby/network/simple/Switch.cc
index a5fc6ed..c74246e 100644
--- a/src/mem/ruby/network/simple/Switch.cc
+++ b/src/mem/ruby/network/simple/Switch.cc
@@ -139,10 +139,6 @@
{
BasicRouter::regStats();
-for (auto& throttle : throttles) {
-throttle.regStats();
-}
-
for (const auto& throttle : throttles) {
switchStats.m_avg_utilization += throttle.getUtilization();
}
@@ -177,18 +173,12 @@
Switch::resetStats()
{
perfectSwitch.clearStats();
-for (auto& throttle : throttles) {
-throttle.clearStats();
-}
}
void
Switch::collateStats()
{
perfectSwitch.collateStats();
-for (auto& throttle : throttles) {
-throttle.collateStats();
-}
}
void
diff --git a/src/mem/ruby/network/simple/Throttle.cc
b/src/mem/ruby/network/simple/Throttle.cc
index 1e530df..20cebcc 100644
--- a/src/mem/ruby/network/simple/Throttle.cc
+++ b/src/mem/ruby/network/simple/Throttle.cc
@@ -50,6 +50,7 @@
#include "mem/ruby/network/simple/Switch.hh"
#include "mem/ruby/slicc_interface/Message.hh"
#include "mem/ruby/system/RubySystem.hh"
+#include "sim/stats.hh"
namespace gem5
{
@@ -77,7 +78,6 @@
m_endpoint_bandwidth = endpoint_bandwidth;
m_wakeups_wo_switch = 0;
-m_link_utilization_proxy = 0;
}
Throttle::Throttle(int sID, RubySystem *rs, NodeID node, Cycles
link_latency,
@@ -163,7 +163,7 @@
void
Throttle::operateVnet(int vnet, int channel, int _bw_remaining,
- bool _wakeup,
+ bool _saturated, bool _blocked,
MessageBuffer *in, MessageBuffer *out)
{
if (out == nullptr || in == nullptr) {
@@ -188,6 +188,7 @@
// Find the size of the message we are moving
MsgPtr msg_ptr = in->peekMsgPtr();
Message *net_msg_ptr = msg_ptr.get();
+Tick msg_enqueue_time = msg_ptr->getLastEnqueueTime();
units_remaining = network_message_to_size(net_msg_ptr);
DPRINTF(RubyNetwork, "throttle: %d my bw %d bw spent "
@@ -202,7 +203,16 @@
// Count the message
(*(throttleStats.
-m_msg_counts[net_msg_ptr->getMessageSize()]))[vnet]++;
+msg_counts[net_msg_ptr->getMessageSize()]))[vnet]++;
+throttleStats.total_msg_count += 1;
+uint32_t total_size =
+
Network::MessageSizeType_to_int(net_msg_ptr->getMessageSize());
+throttleStats.total_msg_bytes += total_size;
+total_size -=
+Network::MessageSizeType_to_int(MessageSizeType_Control);
+throttleStats.total_data_msg_bytes += total_size;
+throttleStats.total_msg_wait_time +=
+current_time - msg_enqueue_time;
DPRINTF(RubyNetwork, "%s\n", *out);
}
@@ -217,14 +227,15 @@
gem5_assert(bw_remaining >= 0);
gem5_assert(total_bw_remaining >= 0);
-// Make sure to continue work next cycle if
+// Notify caller if
// - we ran out of bandwith and still have stuff to do
// - we had something to do but output queue was unavailable
if (hasPendingWork()) {
gem5_assert((bw_remaining == 0) ||
!out->areNSlotsAvailable(1, current_time));
-DPRINTF(RubyNetwork, "vnet: %d set schedule_wakeup\n", vnet);
-schedule_wakeup = true;
+bw_saturated = bw_saturated || (bw_remaining == 0);
+output_blocked = output_blocked ||
+!out->areNSlotsAvailable(1, current_time);
}
}
@@ -236,7 +247,8 @@
int bw_remaining = getTotalLinkBandwidth();
m_wakeups_wo_switch++;
-bool schedule_wakeup = false;
+bool bw_saturated = false;
+
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fine tunning SimpleNetwork buffers
Tiago Muck has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41863 )
(
4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: mem-ruby: fine tunning SimpleNetwork buffers
..
mem-ruby: fine tunning SimpleNetwork buffers
If physical_vnets_channels is set we adjust the link buffer sizes and
the max_dequeue_rate in order to achieve the expected maximum throughput
assuming a fully pipelined link, i.e., throughput of 1 msg per cycle
per channel (assuming the channels width matches the protocol
logical message size, otherwise maximum throughput may be smaller).
JIRA: https://gem5.atlassian.net/browse/GEM5-920
Change-Id: Id99ab745ed54686d8ffcc630d622fb07ac0fc352
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41863
Reviewed-by: Meatboy 106
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/network/simple/SimpleLink.py
M src/mem/ruby/network/simple/SimpleNetwork.py
2 files changed, 58 insertions(+), 17 deletions(-)
Approvals:
Meatboy 106: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/network/simple/SimpleLink.py
b/src/mem/ruby/network/simple/SimpleLink.py
index ccf6b92..0497594 100644
--- a/src/mem/ruby/network/simple/SimpleLink.py
+++ b/src/mem/ruby/network/simple/SimpleLink.py
@@ -63,12 +63,29 @@
if len(self.buffers) > 0:
fatal("User should not manually set links' \
in_buffers or out_buffers")
-# Note that all SimpleNetwork MessageBuffers are currently ordered
# The network needs number_of_virtual_networks buffers per
# in and out port
buffers = []
for i in range(int(network.number_of_virtual_networks)):
-buffers.append(MessageBuffer(ordered = True,
-buffer_size =
network.vnet_buffer_size(i)))
+buffers.append(MessageBuffer(ordered = True))
+
+# If physical_vnets_channels is set we adjust the buffer sizes and
+# the max_dequeue_rate in order to achieve the expected thoughput
+# assuming a fully pipelined link, i.e., throughput of 1 msg per
cycle
+# per channel (assuming the channels width matches the protocol
+# logical message size, otherwise maximum thoughput may be
smaller).
+# In MessageBuffer, an entry occupied by a dequeued message at
cycle
+# X will available for enqueuing another message at cycle X+1. So
+# for a 1 cy enqueue latency, 2 entries are needed. For any
latency,
+# the size should be at least latency+1.
+if len(network.physical_vnets_channels) != 0:
+assert(len(network.physical_vnets_channels) == \
+ int(network.number_of_virtual_networks))
+for i in range(int(network.number_of_virtual_networks)):
+buffers[i].buffer_size = \
+network.physical_vnets_channels[i] * (self.latency + 1)
+buffers[i].max_dequeue_rate = \
+network.physical_vnets_channels[i]
+
self.buffers = buffers
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.py
b/src/mem/ruby/network/simple/SimpleNetwork.py
index 1d4772d..42484a1 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.py
+++ b/src/mem/ruby/network/simple/SimpleNetwork.py
@@ -63,18 +63,6 @@
"Only valid when physical_vnets_channels is set. This overrides
the"
"bandwidth_factor parameter set for the individual links.")
-def vnet_buffer_size(self, vnet):
-"""
-Gets the size of the message buffers associated to a vnet
-If physical_vnets_channels is set we just multiply the size of the
-buffers as SimpleNetwork does not actually creates multiple
physical
-channels per vnet.
-"""
-if len(self.physical_vnets_channels) == 0:
-return self.buffer_size
-else:
-return self.buffer_size * self.physical_vnets_channels[vnet]
-
def setup_buffers(self):
# Setup internal buffers for links and routers
for link in self.int_links:
@@ -128,8 +116,22 @@
"Routing strategy to be used")
def setup_buffers(self, network):
+def vnet_buffer_size(vnet):
+"""
+Gets the size of the message buffers associated to a vnet
+If physical_vnets_channels is set we just multiply the size of
the
+buffers as SimpleNetwork does not actually creates multiple phy
+channels per vnet.
+"""
+if len(network.physical_vnets_channels) == 0:
+return network.buffer_size
+else:
+return network.buffer_size * \
+
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Generate a decode map for AArch64 MiscRegs
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/55604 )
Change subject: arch-arm: Generate a decode map for AArch64 MiscRegs
..
arch-arm: Generate a decode map for AArch64 MiscRegs
The map is translating AArch64 system register numbers
(op0, op1, crn, crm, op2) into a MiscRegIndex
Signed-off-by: Giacomo Travaglini
Change-Id: I359f5d97b248ffafa9cf461d98339175fdf9688f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55604
Reviewed-by: Richard Cooper
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/arch/arm/regs/misc.cc
1 file changed, 495 insertions(+), 1 deletion(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Richard Cooper: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index d586e0f..212a4ff 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2013, 2015-2020 ARM Limited
+ * Copyright (c) 2010-2013, 2015-2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -3398,6 +3398,482 @@
std::bitset miscRegInfo[NUM_MISCREGS]; // initialized
below
+namespace {
+
+// The map is translating AArch64 system register numbers
+// (op0, op1, crn, crm, op2) into a MiscRegIndex
+std::unordered_map miscRegNumToIdx{
+{ MiscRegNum64(1, 0, 7, 1, 0), MISCREG_IC_IALLUIS },
+{ MiscRegNum64(1, 0, 7, 5, 0), MISCREG_IC_IALLU },
+{ MiscRegNum64(1, 0, 7, 6, 1), MISCREG_DC_IVAC_Xt },
+{ MiscRegNum64(1, 0, 7, 6, 2), MISCREG_DC_ISW_Xt },
+{ MiscRegNum64(1, 0, 7, 8, 0), MISCREG_AT_S1E1R_Xt },
+{ MiscRegNum64(1, 0, 7, 8, 1), MISCREG_AT_S1E1W_Xt },
+{ MiscRegNum64(1, 0, 7, 8, 2), MISCREG_AT_S1E0R_Xt },
+{ MiscRegNum64(1, 0, 7, 8, 3), MISCREG_AT_S1E0W_Xt },
+{ MiscRegNum64(1, 0, 7, 10, 2), MISCREG_DC_CSW_Xt },
+{ MiscRegNum64(1, 0, 7, 14, 2), MISCREG_DC_CISW_Xt },
+{ MiscRegNum64(1, 0, 8, 3, 0), MISCREG_TLBI_VMALLE1IS },
+{ MiscRegNum64(1, 0, 8, 3, 1), MISCREG_TLBI_VAE1IS_Xt },
+{ MiscRegNum64(1, 0, 8, 3, 2), MISCREG_TLBI_ASIDE1IS_Xt },
+{ MiscRegNum64(1, 0, 8, 3, 3), MISCREG_TLBI_VAAE1IS_Xt },
+{ MiscRegNum64(1, 0, 8, 3, 5), MISCREG_TLBI_VALE1IS_Xt },
+{ MiscRegNum64(1, 0, 8, 3, 7), MISCREG_TLBI_VAALE1IS_Xt },
+{ MiscRegNum64(1, 0, 8, 7, 0), MISCREG_TLBI_VMALLE1 },
+{ MiscRegNum64(1, 0, 8, 7, 1), MISCREG_TLBI_VAE1_Xt },
+{ MiscRegNum64(1, 0, 8, 7, 2), MISCREG_TLBI_ASIDE1_Xt },
+{ MiscRegNum64(1, 0, 8, 7, 3), MISCREG_TLBI_VAAE1_Xt },
+{ MiscRegNum64(1, 0, 8, 7, 5), MISCREG_TLBI_VALE1_Xt },
+{ MiscRegNum64(1, 0, 8, 7, 7), MISCREG_TLBI_VAALE1_Xt },
+{ MiscRegNum64(1, 3, 7, 4, 1), MISCREG_DC_ZVA_Xt },
+{ MiscRegNum64(1, 3, 7, 5, 1), MISCREG_IC_IVAU_Xt },
+{ MiscRegNum64(1, 3, 7, 10, 1), MISCREG_DC_CVAC_Xt },
+{ MiscRegNum64(1, 3, 7, 11, 1), MISCREG_DC_CVAU_Xt },
+{ MiscRegNum64(1, 3, 7, 14, 1), MISCREG_DC_CIVAC_Xt },
+{ MiscRegNum64(1, 4, 7, 8, 0), MISCREG_AT_S1E2R_Xt },
+{ MiscRegNum64(1, 4, 7, 8, 1), MISCREG_AT_S1E2W_Xt },
+{ MiscRegNum64(1, 4, 7, 8, 4), MISCREG_AT_S12E1R_Xt },
+{ MiscRegNum64(1, 4, 7, 8, 5), MISCREG_AT_S12E1W_Xt },
+{ MiscRegNum64(1, 4, 7, 8, 6), MISCREG_AT_S12E0R_Xt },
+{ MiscRegNum64(1, 4, 7, 8, 7), MISCREG_AT_S12E0W_Xt },
+{ MiscRegNum64(1, 4, 8, 0, 1), MISCREG_TLBI_IPAS2E1IS_Xt },
+{ MiscRegNum64(1, 4, 8, 0, 5), MISCREG_TLBI_IPAS2LE1IS_Xt },
+{ MiscRegNum64(1, 4, 8, 3, 0), MISCREG_TLBI_ALLE2IS },
+{ MiscRegNum64(1, 4, 8, 3, 1), MISCREG_TLBI_VAE2IS_Xt },
+{ MiscRegNum64(1, 4, 8, 3, 4), MISCREG_TLBI_ALLE1IS },
+{ MiscRegNum64(1, 4, 8, 3, 5), MISCREG_TLBI_VALE2IS_Xt },
+{ MiscRegNum64(1, 4, 8, 3, 6), MISCREG_TLBI_VMALLS12E1IS },
+{ MiscRegNum64(1, 4, 8, 4, 1), MISCREG_TLBI_IPAS2E1_Xt },
+{ MiscRegNum64(1, 4, 8, 4, 5), MISCREG_TLBI_IPAS2LE1_Xt },
+{ MiscRegNum64(1, 4, 8, 7, 0), MISCREG_TLBI_ALLE2 },
+{ MiscRegNum64(1, 4, 8, 7, 1), MISCREG_TLBI_VAE2_Xt },
+{ MiscRegNum64(1, 4, 8, 7, 4), MISCREG_TLBI_ALLE1 },
+{ MiscRegNum64(1, 4, 8, 7, 5), MISCREG_TLBI_VALE2_Xt },
+{ MiscRegNum64(1, 4, 8, 7, 6), MISCREG_TLBI_VMALLS12E1 },
+{ MiscRegNum64(1, 6, 7, 8, 0), MISCREG_AT_S1E3R_Xt },
+{ MiscRegNum64(1, 6, 7, 8, 1), MISCREG_AT_S1E3W_Xt },
+{ MiscRegNum64(1, 6, 8, 3, 0), MISCREG_TLBI_ALLE3IS },
+{ MiscRegNum64(1, 6, 8, 3, 1), MISCREG_TLBI_VAE3IS_Xt },
+{ MiscRegNum64(1, 6, 8, 3, 5), MISCREG_TLBI_VALE3IS_Xt },
+{ MiscRegNum64(1, 6, 8, 7, 0), MISCREG_TLBI_ALLE3 },
+{ MiscRegNum64(1, 6, 8, 7, 1), MISCREG_TLBI_VAE3_Xt },
+{ MiscRegNum64(1, 6, 8, 7, 5), MISCREG_TLBI_VALE3_Xt },
+{ MiscRegNum64(2, 0, 0, 0, 2), MISCREG_OSDTRRX_EL1 },
+
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Define MiscRegNum64 data structure
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/55603 )
Change subject: arch-arm: Define MiscRegNum64 data structure
..
arch-arm: Define MiscRegNum64 data structure
Signed-off-by: Giacomo Travaglini
Change-Id: Ia635bc068751edd9305a6e493e38e1a49aa64c4d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55603
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Reviewed-by: Richard Cooper
Tested-by: kokoro
---
M src/arch/arm/regs/misc.hh
1 file changed, 69 insertions(+), 1 deletion(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Richard Cooper: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index 1a2f137..5b8d75b 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2020 ARM Limited
+ * Copyright (c) 2010-2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -1153,6 +1153,46 @@
extern std::bitset miscRegInfo[NUM_MISCREGS];
+struct MiscRegNum64
+{
+MiscRegNum64(unsigned _op0, unsigned _op1,
+ unsigned _crn, unsigned _crm,
+ unsigned _op2)
+ : op0(_op0), op1(_op1), crn(_crn),
+crm(_crm), op2(_op2)
+{
+assert(op0 < 4 && op1 < 8 && crn < 16 && crm < 16 && op2 < 8);
+}
+
+MiscRegNum64(const MiscRegNum64& rhs) = default;
+
+bool
+operator==(const MiscRegNum64 ) const
+{
+return op0 == other.op0 &&
+op1 == other.op1 &&
+crn == other.crn &&
+crm == other.crm &&
+op2 == other.op2;
+}
+
+uint32_t
+packed() const
+{
+return op0 << 14 |
+ op1 << 11 |
+ crn << 7 |
+ crm << 3 |
+ op2;
+}
+
+unsigned op0;
+unsigned op1;
+unsigned crn;
+unsigned crm;
+unsigned op2;
+};
+
// Decodes 32-bit CP14 registers accessible through MCR/MRC
instructions
MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
unsigned crm, unsigned opc2);
@@ -2286,4 +2326,17 @@
} // namespace ArmISA
} // namespace gem5
+namespace std
+{
+template<>
+struct hash
+{
+size_t
+operator()(const gem5::ArmISA::MiscRegNum64& reg) const
+{
+return reg.packed();
+}
+};
+} // namespace std
+
#endif // __ARCH_ARM_REGS_MISC_HH__
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/55603
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia635bc068751edd9305a6e493e38e1a49aa64c4d
Gerrit-Change-Number: 55603
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Richard Cooper
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add a reverse map MiscRegIndex -> MiscRegNum64
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/55606 )
Change subject: arch-arm: Add a reverse map MiscRegIndex -> MiscRegNum64
..
arch-arm: Add a reverse map MiscRegIndex -> MiscRegNum64
Signed-off-by: Giacomo Travaglini
Change-Id: I63cdcdfca610cfd37a03769e077388a193510bc7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55606
Reviewed-by: Richard Cooper
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/arch/arm/regs/misc.cc
M src/arch/arm/regs/misc.hh
2 files changed, 38 insertions(+), 0 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Richard Cooper: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 99ea64b..0e58d93 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -1454,6 +1454,10 @@
namespace {
+// The map is translating a MiscRegIndex into AArch64 system register
+// numbers (op0, op1, crn, crm, op2)
+std::unordered_map idxToMiscRegNum;
+
// The map is translating AArch64 system register numbers
// (op0, op1, crn, crm, op2) into a MiscRegIndex
std::unordered_map miscRegNumToIdx{
@@ -1947,6 +1951,17 @@
}
}
+MiscRegNum64
+encodeAArch64SysReg(MiscRegIndex misc_reg)
+{
+if (auto it = idxToMiscRegNum.find(misc_reg);
+it != idxToMiscRegNum.end()) {
+return it->second;
+} else {
+panic("Invalid MiscRegIndex: %n\n", misc_reg);
+}
+}
+
void
ISA::initializeMiscRegMetadata()
{
@@ -4585,6 +4600,12 @@
// DBGDTRTX_EL0 -> DBGDTRRXint
// MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
+// Populate the idxToMiscRegNum map
+assert(idxToMiscRegNum.empty());
+for (const auto& [key, val] : miscRegNumToIdx) {
+idxToMiscRegNum.insert({val, key});
+}
+
completed = true;
}
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index 5b8d75b..ea58ad2 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -1199,6 +1199,8 @@
MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,
unsigned crn, unsigned crm,
unsigned op2);
+MiscRegNum64 encodeAArch64SysReg(MiscRegIndex misc_reg);
+
// Whether a particular AArch64 system register is -always- read only.
bool aarch64SysRegReadOnly(MiscRegIndex miscReg);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/55606
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I63cdcdfca610cfd37a03769e077388a193510bc7
Gerrit-Change-Number: 55606
Gerrit-PatchSet: 5
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Richard Cooper
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-arm, kvm: Handle vcpu2 if more than 256 vCPUs are in use
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55964 )
Change subject: arch-arm, kvm: Handle vcpu2 if more than 256 vCPUs are in
use
..
arch-arm, kvm: Handle vcpu2 if more than 256 vCPUs are in use
According to KVM Docs [1]:
"When KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 is supported, the target vcpu is
identified as (256 * vcpu2_index + vcpu_index). Otherwise, vcpu2_index
must be zero."
The vcpu parameter from the setIntState method is populated with
the gem5 context identifier (ContextID) of a specific PE.
It is not contrained by the 256 vcpu limit, so it can already specify
more than 256 vcpus. We therefore just need to translate/unpack the
value in two indices (vcpu and vcpu2) which will be forwarded to KVM
when raising an IRQ from userspace.
We guard the vcpu2 retrieval with a hash define as this is a late
addition and some older kernels do not define this capability (4.15 as
an example).
[1]: https://www.kernel.org/doc/html/latest/virt/kvm/api.html
Signed-off-by: Giacomo Travaglini
Change-Id: If0c475dc4a573337edd053020920e9b109d13991
---
M src/arch/arm/kvm/gic.cc
1 file changed, 47 insertions(+), 2 deletions(-)
diff --git a/src/arch/arm/kvm/gic.cc b/src/arch/arm/kvm/gic.cc
index efd8e54..3ceb814 100644
--- a/src/arch/arm/kvm/gic.cc
+++ b/src/arch/arm/kvm/gic.cc
@@ -91,12 +91,28 @@
KvmKernelGic::setIntState(unsigned type, unsigned vcpu, unsigned irq,
bool high)
{
+#ifdef KVM_CAP_ARM_IRQ_LINE_LAYOUT_2
+static const bool vcpu2_enabled = vm.checkExtension(
+KVM_CAP_ARM_IRQ_LINE_LAYOUT_2);
+
+const unsigned vcpu2_mask = vcpu2_enabled ? KVM_ARM_IRQ_VCPU2_MASK : 0;
+const unsigned vcpu2_shift = vcpu2_enabled ? KVM_ARM_IRQ_VCPU2_SHIFT :
0;
+#else
+const unsigned vcpu2_mask = 0;
+const unsigned vcpu2_shift = 0;
+#endif
+
+const unsigned vcpu_index = vcpu % 256;
+const unsigned vcpu2_index = vcpu / 256;
+
+assert(vcpu2_index <= vcpu2_mask);
assert(type <= KVM_ARM_IRQ_TYPE_MASK);
-assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
+assert(vcpu_index <= KVM_ARM_IRQ_VCPU_MASK);
assert(irq <= KVM_ARM_IRQ_NUM_MASK);
const uint32_t line(
+(vcpu2_index << vcpu2_shift) |
(type << KVM_ARM_IRQ_TYPE_SHIFT) |
-(vcpu << KVM_ARM_IRQ_VCPU_SHIFT) |
+(vcpu_index << KVM_ARM_IRQ_VCPU_SHIFT) |
(irq << KVM_ARM_IRQ_NUM_SHIFT));
vm.setIRQLine(line, high);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/55964
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If0c475dc4a573337edd053020920e9b109d13991
Gerrit-Change-Number: 55964
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: scons: protobuf builder, support source paths
Adrian Herrera has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55963 )
Change subject: scons: protobuf builder, support source paths
..
scons: protobuf builder, support source paths
Before this patch, the protobuf builder would search for dependencies
only at the build directory. This works if the importing .proto file
imports paths relative to the build directory, but it results in a build
failure if imports are done relative to the source directory of the
importing file.
This patch adds the source directory of the importing file to the set of
paths searched for dependencies, which solves this issue.
Change-Id: I7debd467485a5087276ac005ac08ab01b32cb02e
Signed-off-by: Adrián Herrera Arcila
---
M src/SConscript
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/src/SConscript b/src/SConscript
index e5b032c..6c8ccaf 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -240,7 +240,8 @@
return [root + '.pb.cc', root + '.pb.h'], source
protoc_action = MakeAction('${PROTOC} --cpp_out ${BUILDDIR} '
-'--proto_path ${BUILDDIR} ${SOURCE.get_abspath()}',
+'--proto_path ${BUILDDIR} --proto_path ${SOURCE.dir} '
+'${SOURCE.get_abspath()}',
Transform("PROTOC"))
protobuf_builder = Builder(action=protoc_action, emitter=protoc_emitter,
src_suffix='.proto')
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/55963
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7debd467485a5087276ac005ac08ab01b32cb02e
Gerrit-Change-Number: 55963
Gerrit-PatchSet: 1
Gerrit-Owner: Adrian Herrera
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: stdlib: Remove final decorator from abstract board
Hoa Nguyen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/55863 ) Change subject: stdlib: Remove final decorator from abstract board .. stdlib: Remove final decorator from abstract board @typing.final was not introduced until python3.8. Change-Id: I65a5f4b5655d2ad80f7b566f9cea8e2371b3be62 Signed-off-by: Hoa Nguyen Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55863 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/python/gem5/components/boards/abstract_board.py 1 file changed, 17 insertions(+), 2 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/python/gem5/components/boards/abstract_board.py b/src/python/gem5/components/boards/abstract_board.py index a27cecd..30fbfca 100644 --- a/src/python/gem5/components/boards/abstract_board.py +++ b/src/python/gem5/components/boards/abstract_board.py @@ -37,7 +37,7 @@ VoltageDomain, ) -from typing import List, final +from typing import List class AbstractBoard(System): @@ -236,7 +236,6 @@ """ raise NotImplementedError -@final def _connect_things(self) -> None: """Connects all the components to the board. -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/55863 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I65a5f4b5655d2ad80f7b566f9cea8e2371b3be62 Gerrit-Change-Number: 55863 Gerrit-PatchSet: 2 Gerrit-Owner: Hoa Nguyen Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Hoa Nguyen Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: systemc: Fixed ctor ordering for sc_fifo.hh
Franklin He has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/55664 )
Change subject: systemc: Fixed ctor ordering for sc_fifo.hh
..
systemc: Fixed ctor ordering for sc_fifo.hh
This fixes a constructor ordering issue and lets the
headers compile with `-Wreorder` enabled
Test: Compiled SystemC headers with `-Wreorder`
Change-Id: I88703b464f8940dd973c2102f1cd0da757b17985
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55664
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Reviewed-by: Matthias Jung
Tested-by: kokoro
---
M src/systemc/ext/channel/sc_fifo.hh
1 file changed, 24 insertions(+), 5 deletions(-)
Approvals:
Matthias Jung: Looks good to me, approved
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/systemc/ext/channel/sc_fifo.hh
b/src/systemc/ext/channel/sc_fifo.hh
index 5d3dab4..2f0a4f4 100644
--- a/src/systemc/ext/channel/sc_fifo.hh
+++ b/src/systemc/ext/channel/sc_fifo.hh
@@ -53,15 +53,16 @@
explicit sc_fifo(int size=16) :
sc_fifo_in_if(), sc_fifo_out_if(),
sc_prim_channel(sc_gen_unique_name("fifo")),
+_reader(NULL), _writer(NULL),
_size(size), _num_free(size), _num_available(0),
-_readsHappened(false), _writesHappened(false),
-_reader(NULL), _writer(NULL)
+_readsHappened(false), _writesHappened(false)
{}
explicit sc_fifo(const char *name, int size=16) :
sc_fifo_in_if(), sc_fifo_out_if(),
-sc_prim_channel(name), _size(size), _num_free(size),
-_num_available(0), _readsHappened(false),
_writesHappened(false),
-_reader(NULL), _writer(NULL)
+sc_prim_channel(name),
+_reader(NULL), _writer(NULL),
+_size(size), _num_free(size), _num_available(0),
+_readsHappened(false), _writesHappened(false)
{}
virtual ~sc_fifo() {}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/55664
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I88703b464f8940dd973c2102f1cd0da757b17985
Gerrit-Change-Number: 55664
Gerrit-PatchSet: 3
Gerrit-Owner: Franklin He
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Franklin He
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthias Jung
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
