date:20221101

[gem5-dev] [M] Change in gem5/gem5[develop]: tests: Remove long/nightly X86 Boot tests

2022-11-01 Thread Bobby Bruce (Gerrit) via gem5-dev

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65192?usp=email )


Change subject: tests: Remove long/nightly X86 Boot tests
..

tests: Remove long/nightly X86 Boot tests

The long/nightly tests are failing due to timeout (e.g.,:
https://jenkins.gem5.org/job/nightly/398/). We must therefore be more
careful about what we test on a nightly basis.

Each of these X86 boot tests takes an hour and, generally, are largely
the same (just with different CPU cores, cache hierarchy, and memory
system). Given this is largely redundant, some of these tests have been
remove dto save on testing time.

Change-Id: I761fca1aa5e111a03183f83d4e326aaea1bdbc3a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65192
Reviewed-by: Jason Lowe-Power 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
M tests/gem5/x86-boot-tests/test_linux_boot.py
1 file changed, 23 insertions(+), 35 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved




diff --git a/tests/gem5/x86-boot-tests/test_linux_boot.py  
b/tests/gem5/x86-boot-tests/test_linux_boot.py

index ecda2ff..76d593b 100644
--- a/tests/gem5/x86-boot-tests/test_linux_boot.py
+++ b/tests/gem5/x86-boot-tests/test_linux_boot.py
@@ -150,39 +150,13 @@

  The long (Nightly) tests 

-test_boot(
-cpu="atomic",
-num_cpus=1,
-mem_system="classic",
-memory_class="SingleChannelHBM",
-boot_type="init",
-length=constants.long_tag,
-)

 test_boot(
 cpu="timing",
 num_cpus=1,
 mem_system="mesi_two_level",
 memory_class="DualChannelDDR3_1600",
-boot_type="init",
-length=constants.long_tag,
-)
-
-test_boot(
-cpu="timing",
-num_cpus=1,
-mem_system="mi_example",
-memory_class="DualChannelDDR3_2133",
-boot_type="init",
-length=constants.long_tag,
-)
-
-test_boot(
-cpu="timing",
-num_cpus=4,
-mem_system="classic",
-memory_class="DualChannelDDR3_2133",
-boot_type="init",
+boot_type="systemd",
 length=constants.long_tag,
 )

@@ -209,14 +183,6 @@
 #length=constants.long_tag,
 # )

-test_boot(
-cpu="atomic",
-num_cpus=4,
-mem_system="classic",
-memory_class="HBM2Stack",
-boot_type="systemd",
-length=constants.long_tag,
-)

  The very-long (Weekly) tests 


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I761fca1aa5e111a03183f83d4e326aaea1bdbc3a
Gerrit-Change-Number: 65192
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: tests: Remove long/nightly ARM Boot tests

2022-11-01 Thread Bobby Bruce (Gerrit) via gem5-dev

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65191?usp=email )


Change subject: tests: Remove long/nightly ARM Boot tests
..

tests: Remove long/nightly ARM Boot tests

The long/nightly tests are failing due to timeout (e.g.:
https://jenkins.gem5.org/job/nightly/398/). We must therefore be more
careful about what we test on a nightly basis.

Each of these ARM boot tests takes an hour and, generally, are largely
the same (just with different CPU cores, cache hierarchy, and memory
system). Given this is largely redundant, some of these tests have been
removed to save on testing time.

Change-Id: I8d80d3e0869aca67aa7279a164bdce85d20f3682
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65191
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M tests/gem5/arm-boot-tests/test_linux_boot.py
1 file changed, 23 insertions(+), 57 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/gem5/arm-boot-tests/test_linux_boot.py  
b/tests/gem5/arm-boot-tests/test_linux_boot.py

index 9a6f671..6115bb2 100644
--- a/tests/gem5/arm-boot-tests/test_linux_boot.py
+++ b/tests/gem5/arm-boot-tests/test_linux_boot.py
@@ -185,32 +185,8 @@

 test_boot(
 cpu="atomic",
-num_cpus=1,
-mem_system="classic",
-memory_class="SingleChannelDDR3_1600",
-length=constants.long_tag,
-)
-
-test_boot(
-cpu="timing",
-num_cpus=1,
-mem_system="classic",
-memory_class="SingleChannelDDR3_2133",
-length=constants.long_tag,
-)
-
-test_boot(
-cpu="o3",
-num_cpus=1,
-mem_system="classic",
-memory_class="DualChannelDDR3_1600",
-length=constants.long_tag,
-)
-
-test_boot(
-cpu="timing",
 num_cpus=4,
-mem_system="classic",
+mem_system="no_cache",
 memory_class="HBM2Stack",
 length=constants.long_tag,
 )
@@ -218,39 +194,7 @@
 test_boot(
 cpu="timing",
 num_cpus=2,
-mem_system="classic",
-memory_class="DualChannelDDR4_2400",
-length=constants.long_tag,
-)
-
-test_boot(
-cpu="timing",
-num_cpus=2,
-mem_system="no_cache",
-memory_class="DualChannelDDR4_2400",
-length=constants.long_tag,
-)
-
-test_boot(
-cpu="timing",
-num_cpus=2,
 mem_system="chi",
 memory_class="DualChannelDDR4_2400",
 length=constants.long_tag,
 )
-
-test_boot(
-cpu="timing",
-num_cpus=2,
-mem_system="mesi_two_level",
-memory_class="DualChannelDDR4_2400",
-length=constants.long_tag,
-)
-
-test_boot(
-cpu="timing",
-num_cpus=2,
-mem_system="mi_example",
-memory_class="DualChannelDDR4_2400",
-length=constants.long_tag,
-)

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8d80d3e0869aca67aa7279a164bdce85d20f3682
Gerrit-Change-Number: 65191
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Remove ARM compilation requirement for quick/Kokoro

2022-11-01 Thread Bobby Bruce (Gerrit) via gem5-dev

Bobby Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65195?usp=email )



Change subject: tests: Remove ARM compilation requirement for quick/Kokoro
..

tests: Remove ARM compilation requirement for quick/Kokoro

The ARM Boot Tests required the compilation of ARM/gem5.opt to run a
quick test that the CHI protocol was functioning correctly with ARM and
the ArmBoard. This test has been removed and the test refactored
slightly to use the ALL/gem5.opt.

The CHI protocol is already tested nightly.

Change-Id: Ibe406348caefa2493860036eb89a20681478ea66
---
M tests/gem5/arm-boot-tests/test_linux_boot.py
1 file changed, 17 insertions(+), 21 deletions(-)



diff --git a/tests/gem5/arm-boot-tests/test_linux_boot.py  
b/tests/gem5/arm-boot-tests/test_linux_boot.py

index 6115bb2..3641256 100644
--- a/tests/gem5/arm-boot-tests/test_linux_boot.py
+++ b/tests/gem5/arm-boot-tests/test_linux_boot.py
@@ -77,16 +77,12 @@

 if mem_system == "chi":
 protocol_to_use = "CHI"
-isa_to_use = constants.arm_tag
 elif mem_system == "mesi_two_level":
 protocol_to_use = None
-isa_to_use = constants.all_compiled_tag
 elif mem_system == "mi_example":
 protocol_to_use = "MI_example"
-isa_to_use = constants.arm_tag
 else:
 protocol_to_use = None
-isa_to_use = constants.all_compiled_tag

 gem5_verify_config(
 name=name,
@@ -100,7 +96,7 @@
 "arm_boot_exit_run.py",
 ),
 config_args=config_args,
-valid_isas=(isa_to_use,),
+valid_isas=(constants.all_compiled,),
 valid_hosts=constants.supported_hosts,
 length=length,
 protocol=protocol_to_use,
@@ -154,14 +150,6 @@
 to_tick=100,
 )

-test_boot(
-cpu="timing",
-num_cpus=2,
-mem_system="chi",
-memory_class="DualChannelDDR4_2400",
-length=constants.quick_tag,
-to_tick=100,
-)

 test_boot(
 cpu="timing",
@@ -172,14 +160,6 @@
 to_tick=100,
 )

-test_boot(
-cpu="timing",
-num_cpus=2,
-mem_system="mi_example",
-memory_class="DualChannelDDR4_2400",
-length=constants.quick_tag,
-to_tick=100,
-)

  The long (nightly) tests 


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibe406348caefa2493860036eb89a20681478ea66
Gerrit-Change-Number: 65195
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby Bruce 
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Change the default kernel boot param from "ro" to "rw"

2022-11-01 Thread Hoa Nguyen (Gerrit) via gem5-dev

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65194?usp=email )



Change subject: stdlib: Change the default kernel boot param from "ro"  
to "rw"

..

stdlib: Change the default kernel boot param from "ro" to "rw"

Running workloads likely causes some content to be written to
the disk image, e.g., `m5 readfile`. However, on riscv boards,
the default kernel param specifies the disk image to be read-only.

This change changes this param so that the disk image is
read-write by default.

Change-Id: I414e483ad11d747f34433560e32a8f91a425ce7e
Signed-off-by: Hoa Nguyen 
---
M src/python/gem5/components/boards/experimental/lupv_board.py
M src/python/gem5/components/boards/riscv_board.py
M src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
3 files changed, 20 insertions(+), 3 deletions(-)



diff --git a/src/python/gem5/components/boards/experimental/lupv_board.py  
b/src/python/gem5/components/boards/experimental/lupv_board.py

index ba65ccb..5624712 100644
--- a/src/python/gem5/components/boards/experimental/lupv_board.py
+++ b/src/python/gem5/components/boards/experimental/lupv_board.py
@@ -536,7 +536,7 @@

 @overrides(KernelDiskWorkload)
 def get_default_kernel_args(self) -> List[str]:
-return ["console=ttyLIO0", "root={root_value}", "ro"]
+return ["console=ttyLIO0", "root={root_value}", "rw"]

 @overrides(KernelDiskWorkload)
 def get_disk_device(self) -> str:
diff --git a/src/python/gem5/components/boards/riscv_board.py  
b/src/python/gem5/components/boards/riscv_board.py

index d83b85e..15ec57a 100644
--- a/src/python/gem5/components/boards/riscv_board.py
+++ b/src/python/gem5/components/boards/riscv_board.py
@@ -494,4 +494,4 @@

 @overrides(KernelDiskWorkload)
 def get_default_kernel_args(self) -> List[str]:
-return ["console=ttyS0", "root={root_value}", "ro"]
+return ["console=ttyS0", "root={root_value}", "rw"]
diff --git a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py  
b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py

index 469010c..4148c0a 100644
--- a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
+++ b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
@@ -566,7 +566,7 @@

 @overrides(KernelDiskWorkload)
 def get_default_kernel_args(self) -> List[str]:
-return ["console=ttyS0", "root={root_value}", "ro"]
+return ["console=ttyS0", "root={root_value}", "rw"]

 @overrides(KernelDiskWorkload)
 def set_kernel_disk_workload(

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[gem5-dev] Re: Build failed in Jenkins: nightly #403

2022-11-01 Thread Bobby Bruce via gem5-dev

At least one problem here is the Nightly tests are failing due to it
reaching timeout. I've submitted some patches here to remove some of the
Boot tests (we have a lot of these, they take a while to run, and are
largely doing the same thing),  remove a couple of tests that require
compilation of SPARC, POWER, and MIPS (these tests were very small and I
didn't think they justify the additional compilation), and get rid of some
redundant compilations in the nightly.sh script :
https://gem5-review.googlesource.com/c/public/gem5/+/65175

As a general note, we should probably try to be more careful in how we
test. Particularly, we do full OS boots to test some rather minor features.
We should try to find ways to break these down into more unit-like tests.
Though that's probably on me :).

--
Dr. Bobby R. Bruce
Room 3050,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Tue, Nov 1, 2022 at 1:11 AM jenkins-no-reply--- via gem5-dev <
gem5-dev@gem5.org> wrote:

> See <
> https://jenkins.gem5.org/job/nightly/403/display/redirect?page=changes>
>
> Changes:
>
> [matthew.poremba] arch-vega: Improve non-native page size support
>
> [matthew.poremba] dev-amdgpu: Chunkify SDMA copies that use device memory
>
> [matthew.poremba] dev-amdgpu: Fix GART PTE size
>
> [yuhsingw] mem: introduce bad command error to packet commands
>
> [yuhsingw] systemc: sync the response error between gem5 packet and tlm
> payload
>
>
> --
> [...truncated 1.29 MB...]
>  [ CXX] ALL_MSI/arch/power/insts/mem.cc -> .o
>  [ CXX] ALL_MSI/arch/power/insts/integer.cc -> .o
>  [ CXX] ALL_MSI/arch/power/insts/floating.cc -> .o
>  [ CXX] ALL_MSI/arch/power/insts/condition.cc -> .o
>  [ CXX] ALL_MSI/arch/power/insts/static_inst.cc -> .o
>  [ CXX] ALL_MSI/arch/power/linux/se_workload.cc -> .o
>  [ CXX] ALL_MSI/arch/power/isa.cc -> .o
>  [ CXX] ALL_MSI/arch/power/process.cc -> .o
>  [ CXX] ALL_MSI/arch/power/remote_gdb.cc -> .o
>  [ CXX] ALL_MSI/arch/power/se_workload.cc -> .o
>  [ CXX] ALL_MSI/arch/power/tlb.cc -> .o
>  [ CXX] ALL_MSI/python/_m5/param_PowerISA.cc -> .o
>  [ CXX] ALL_MSI/python/_m5/param_PowerSEWorkload.cc -> .o
>  [ CXX] ALL_MSI/python/_m5/param_PowerEmuLinux.cc -> .o
>  [ CXX] ALL_MSI/arch/power/generated/decoder.cc -> .o
>  [ CXX] ALL_MSI/arch/power/generated/inst-constrs.cc -> .o
>  [ CXX] ALL_MSI/arch/power/generated/generic_cpu_exec.cc -> .o
>  [ CXX] ALL_MSI/arch/riscv/faults.cc -> .o
>  [ CXX] ALL_MSI/arch/riscv/isa.cc -> .o
>  [ CXX] ALL_MSI/arch/riscv/process.cc -> .o
>  [ CXX] ALL_MSI/arch/riscv/pagetable_walker.cc -> .o
>  [ CXX] ALL_MSI/arch/riscv/pma_checker.cc -> .o
>  [ CXX] ALL_MSI/arch/riscv/pmp.cc -> .o
>  [ CXX] ALL_MSI/arch/riscv/reg_abi.cc -> .o
>  [ CXX] ALL_MSI/arch/riscv/remote_gdb.cc -> .o
>  [ CXX] ALL_MSI/arch/riscv/tlb.cc -> .o
>  [ CXX] ALL_MSI/arch/riscv/linux/se_workload.cc -> .o
>  [ CXX] ALL_MSI/arch/riscv/linux/fs_workload.cc -> .o
>  [ CXX] ALL_MSI/arch/riscv/bare_metal/fs_workload.cc -> .o
>  [ CXX] ALL_MSI/python/_m5/param_PMAChecker.cc -> .o
>  [ CXX] ALL_MSI/python/_m5/param_PMP.cc -> .o
>  [ CXX] ALL_MSI/python/_m5/param_RiscvInterrupts.cc -> .o
>  [ CXX] ALL_MSI/python/_m5/param_RiscvISA.cc -> .o
>  [ CXX] ALL_MSI/python/_m5/param_RiscvMMU.cc -> .o
>  [ CXX] ALL_MSI/python/_m5/param_RiscvSEWorkload.cc -> .o
>  [ CXX] ALL_MSI/python/_m5/param_RiscvEmuLinux.cc -> .o
>  [ CXX] ALL_MSI/python/_m5/param_RiscvPagetableWalker.cc -> .o
>  [ CXX] ALL_MSI/python/_m5/param_RiscvTLB.cc -> .o
>  [ CXX] ALL_MSI/arch/riscv/generated/decoder.cc -> .o
>  [ CXX] ALL_MSI/arch/riscv/generated/inst-constrs.cc -> .o
>  [ CXX] ALL_MSI/arch/riscv/generated/generic_cpu_exec.cc -> .o
>  [ CXX] ALL_MSI/arch/riscv/insts/amo.cc -> .o
>  [ CXX] ALL_MSI/arch/riscv/insts/compressed.cc -> .o
>  [ CXX] ALL_MSI/arch/riscv/insts/mem.cc -> .o
>  [ CXX] ALL_MSI/arch/riscv/insts/standard.cc -> .o
>  [ CXX] ALL_MSI/arch/riscv/insts/static_inst.cc -> .o
>  [ CXX] ALL_MSI/arch/mips/faults.cc -> .o
>  [ CXX] ALL_MSI/arch/mips/interrupts.cc -> .o
>  [ CXX] ALL_MSI/arch/mips/isa.cc -> .o
>  [ CXX] ALL_MSI/arch/mips/linux/se_workload.cc -> .o
>  [ CXX] ALL_MSI/arch/mips/process.cc -> .o
>  [ CXX] ALL_MSI/arch/mips/remote_gdb.cc -> .o
>  [ CXX] ALL_MSI/arch/mips/se_workload.cc -> .o
>  [ CXX] ALL_MSI/arch/mips/tlb.cc -> .o
>  [ CXX] ALL_MSI/arch/mips/utility.cc -> .o
>  [ CXX] ALL_MSI/python/_m5/param_MipsInterrupts.cc -> .o
>  [ CXX] ALL_MSI/python/_m5/param_MipsISA.cc -> .o
>  [ CXX] ALL_MSI/python/_m5/param_MipsSEWorkload.cc -> .o
>  [ CXX] ALL_MSI/python/_m5/param_MipsEmuLinux.cc -> .o
>  [ CXX] ALL_MSI/python/_m5/param_MipsTLB.cc -> .o
>  [ CXX] ALL_MSI/arch/mips/generated/decoder.cc -> .o
>  [ CXX]

[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Remove unneeded build step from nightly.sh

2022-11-01 Thread Bobby Bruce (Gerrit) via gem5-dev

Bobby Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65175?usp=email )



Change subject: tests: Remove unneeded build step from nightly.sh
..

tests: Remove unneeded build step from nightly.sh

The `main.py` script will build the ISAs required to run tests. Our
compiler tests (see "tests/compiler-tests.sh") are run nightly and
already test to ensure these ISAs are compiled correctly. Compiling
these ISAs as part of this script is therefore redundant. This patch
removes this step to save testing time.

Change-Id: I58636acfd5512886ac11ca84ee96cbdc9e344c68
---
M tests/nightly.sh
1 file changed, 15 insertions(+), 23 deletions(-)



diff --git a/tests/nightly.sh b/tests/nightly.sh
index bd42d4b..a082158 100755
--- a/tests/nightly.sh
+++ b/tests/nightly.sh
@@ -61,20 +61,6 @@
 exit 1
 fi

-build_target () {
-isa=$1
-
-# Try to build. If not, delete the build directory and try again.
-# SCons is not perfect, and occasionally does not catch a necessary
-# compilation: https://gem5.atlassian.net/browse/GEM5-753
-docker run -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \
-"${gem5_root}" --memory="${docker_mem_limit}" --rm \
-gcr.io/gem5-test/ubuntu-22.04_all-dependencies:latest \
-bash -c "scons build/${isa}/gem5.opt -j${compile_threads} \
---ignore-style || (rm -rf build && scons build/${isa}/gem5.opt  
\

--j${compile_threads} --ignore-style)"
-}
-
 unit_test () {
 build=$1

@@ -88,15 +74,6 @@
 # Ensure we have the latest docker images.
 docker pull gcr.io/gem5-test/ubuntu-22.04_all-dependencies:latest

-# Try to build the ISA targets.
-build_target NULL
-build_target RISCV
-build_target X86
-build_target ARM
-build_target SPARC
-build_target MIPS
-build_target POWER
-
 # Run the unit tests.
 unit_test opt
 unit_test debug

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I58636acfd5512886ac11ca84ee96cbdc9e344c68
Gerrit-Change-Number: 65175
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby Bruce 
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: tests: Remove long/nightly ARM Boot tests

2022-11-01 Thread Bobby Bruce (Gerrit) via gem5-dev

Bobby Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65191?usp=email )



Change subject: tests: Remove long/nightly ARM Boot tests
..

tests: Remove long/nightly ARM Boot tests

The long/nightly tests are failing due to timeout (e.g.:
https://jenkins.gem5.org/job/nightly/398/). We must therefore be more
careful about what we test on a nightly basis.

Each of these ARM boot tests takes an hour and, generally, are largely
the same (just with different CPU cores, cache hierarchy, and memory
system). Given this is largely redundant, some of these tests have been
removed to save on testing time.

Change-Id: I8d80d3e0869aca67aa7279a164bdce85d20f3682
---
M tests/gem5/arm-boot-tests/test_linux_boot.py
1 file changed, 19 insertions(+), 57 deletions(-)



diff --git a/tests/gem5/arm-boot-tests/test_linux_boot.py  
b/tests/gem5/arm-boot-tests/test_linux_boot.py

index 9a6f671..6115bb2 100644
--- a/tests/gem5/arm-boot-tests/test_linux_boot.py
+++ b/tests/gem5/arm-boot-tests/test_linux_boot.py
@@ -185,32 +185,8 @@

 test_boot(
 cpu="atomic",
-num_cpus=1,
-mem_system="classic",
-memory_class="SingleChannelDDR3_1600",
-length=constants.long_tag,
-)
-
-test_boot(
-cpu="timing",
-num_cpus=1,
-mem_system="classic",
-memory_class="SingleChannelDDR3_2133",
-length=constants.long_tag,
-)
-
-test_boot(
-cpu="o3",
-num_cpus=1,
-mem_system="classic",
-memory_class="DualChannelDDR3_1600",
-length=constants.long_tag,
-)
-
-test_boot(
-cpu="timing",
 num_cpus=4,
-mem_system="classic",
+mem_system="no_cache",
 memory_class="HBM2Stack",
 length=constants.long_tag,
 )
@@ -218,39 +194,7 @@
 test_boot(
 cpu="timing",
 num_cpus=2,
-mem_system="classic",
-memory_class="DualChannelDDR4_2400",
-length=constants.long_tag,
-)
-
-test_boot(
-cpu="timing",
-num_cpus=2,
-mem_system="no_cache",
-memory_class="DualChannelDDR4_2400",
-length=constants.long_tag,
-)
-
-test_boot(
-cpu="timing",
-num_cpus=2,
 mem_system="chi",
 memory_class="DualChannelDDR4_2400",
 length=constants.long_tag,
 )
-
-test_boot(
-cpu="timing",
-num_cpus=2,
-mem_system="mesi_two_level",
-memory_class="DualChannelDDR4_2400",
-length=constants.long_tag,
-)
-
-test_boot(
-cpu="timing",
-num_cpus=2,
-mem_system="mi_example",
-memory_class="DualChannelDDR4_2400",
-length=constants.long_tag,
-)

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[gem5-dev] [M] Change in gem5/gem5[develop]: tests: Remove tests requiring comp of novel ISAs in long

2022-11-01 Thread Bobby Bruce (Gerrit) via gem5-dev

Bobby Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65193?usp=email )



Change subject: tests: Remove tests requiring comp of novel ISAs in long
..

tests: Remove tests requiring comp of novel ISAs in long

The only tests requiring the the compilation of SPARC, MIPS, and POWER
for the long/nightly suite were
"tests/gem5/multi_isa/test_multi_isa.py" and
"gem5/stdlib/test_requires.py". As compilation of gem5 is quite costly,
it'd best we simply remove these tests. They are minor and not very
important.

Compilation of these ISAs will continue to be tested via the compilation
tests.

Change-Id: I98b33eec5d0adb144109d32851033380f1641ad4
---
M tests/gem5/multi_isa/test_multi_isa.py
M tests/gem5/stdlib/test_requires.py
2 files changed, 72 insertions(+), 39 deletions(-)



diff --git a/tests/gem5/multi_isa/test_multi_isa.py  
b/tests/gem5/multi_isa/test_multi_isa.py

index 2c6a96c..7d278b7 100644
--- a/tests/gem5/multi_isa/test_multi_isa.py
+++ b/tests/gem5/multi_isa/test_multi_isa.py
@@ -38,35 +38,42 @@


 for isa in isa_map.keys():
-gem5_verify_config(
-name=f"runtime-isa-check_{isa}-compiled-alone",
-verifiers=(),
-fixtures=(),
-config=joinpath(
- 
config.base_dir, "tests", "gem5", "configs", "runtime_isa_check.py"

-),
-config_args=["-e", isa],
-valid_isas=(isa_map[isa],),
-valid_hosts=constants.supported_hosts,
-length=constants.long_tag,
-)
+if isa in ("x86", "arm", "riscv"):
+# We only do these checks for X86, ARM, and RISCV to save compiling
+# other ISAs.
+gem5_verify_config(
+name=f"runtime-isa-check_{isa}-compiled-alone",
+verifiers=(),
+fixtures=(),
+config=joinpath(
+config.base_dir,
+"tests",
+"gem5",
+"configs",
+"runtime_isa_check.py",
+),
+config_args=["-e", isa],
+valid_isas=(isa_map[isa],),
+valid_hosts=constants.supported_hosts,
+length=constants.long_tag,
+)

-gem5_verify_config(
-name=f"supported-isas-check_{isa}-compiled-alone",
-verifiers=(),
-fixtures=(),
-config=joinpath(
-config.base_dir,
-"tests",
-"gem5",
-"configs",
-"supported_isa_check.py",
-),
-config_args=["-e", isa],
-valid_isas=(isa_map[isa],),
-valid_hosts=constants.supported_hosts,
-length=constants.long_tag,
-)
+gem5_verify_config(
+name=f"supported-isas-check_{isa}-compiled-alone",
+verifiers=(),
+fixtures=(),
+config=joinpath(
+config.base_dir,
+"tests",
+"gem5",
+"configs",
+"supported_isa_check.py",
+),
+config_args=["-e", isa],
+valid_isas=(isa_map[isa],),
+valid_hosts=constants.supported_hosts,
+length=constants.long_tag,
+)

 if isa != "null":
 # The null isa is not "supported" in a case where other ISAs are
diff --git a/tests/gem5/stdlib/test_requires.py  
b/tests/gem5/stdlib/test_requires.py

index 293eb3d..b729050 100644
--- a/tests/gem5/stdlib/test_requires.py
+++ b/tests/gem5/stdlib/test_requires.py
@@ -47,17 +47,24 @@
 }

 for isa in isa_map.keys():
-gem5_verify_config(
-name=f"requires-isa-{isa}",
-verifiers=(),
-fixtures=(),
-config=joinpath(
- 
config.base_dir, "tests", "gem5", "configs", "requires_check.py"

-),
-config_args=["-i", isa],
-valid_isas=(isa_map[isa],),
-length=length_map[isa],
-)
+if isa in ("x86", "arm", "riscv"):
+# We only do these checks for X86, ARM, and RISCV to save compiling
+# other ISAs.
+gem5_verify_config(
+name=f"requires-isa-{isa}",
+verifiers=(),
+fixtures=(),
+config=joinpath(
+config.base_dir,
+"tests",
+"gem5",
+"configs",
+"requires_check.py",
+),
+config_args=["-i", isa],
+valid_isas=(isa_map[isa],),
+length=length_map[isa],
+)

 if isa != "null":
 gem5_verify_config(

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Gerrit-Change-Number: 65193
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Gerrit-Owner: Bobby Bruce 
Gerrit-MessageType: newchange

[gem5-dev] [M] Change in gem5/gem5[develop]: tests: Remove long/nightly X86 Boot tests

2022-11-01 Thread Bobby Bruce (Gerrit) via gem5-dev

Bobby Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65192?usp=email )



Change subject: tests: Remove long/nightly X86 Boot tests
..

tests: Remove long/nightly X86 Boot tests

The long/nightly tests are failing due to timeout (e.g.,:
https://jenkins.gem5.org/job/nightly/398/). We must therefore be more
careful about what we test on a nightly basis.

Each of these X86 boot tests takes an hour and, generally, are largely
the same (just with different CPU cores, cache hierarchy, and memory
system). Given this is largely redundant, some of these tests have been
remove dto save on testing time.

Change-Id: I761fca1aa5e111a03183f83d4e326aaea1bdbc3a
---
M tests/gem5/x86-boot-tests/test_linux_boot.py
1 file changed, 20 insertions(+), 36 deletions(-)



diff --git a/tests/gem5/x86-boot-tests/test_linux_boot.py  
b/tests/gem5/x86-boot-tests/test_linux_boot.py

index ecda2ff..7b4c181 100644
--- a/tests/gem5/x86-boot-tests/test_linux_boot.py
+++ b/tests/gem5/x86-boot-tests/test_linux_boot.py
@@ -150,39 +150,13 @@

  The long (Nightly) tests 

-test_boot(
-cpu="atomic",
-num_cpus=1,
-mem_system="classic",
-memory_class="SingleChannelHBM",
-boot_type="init",
-length=constants.long_tag,
-)

 test_boot(
 cpu="timing",
 num_cpus=1,
 mem_system="mesi_two_level",
 memory_class="DualChannelDDR3_1600",
-boot_type="init",
-length=constants.long_tag,
-)
-
-test_boot(
-cpu="timing",
-num_cpus=1,
-mem_system="mi_example",
-memory_class="DualChannelDDR3_2133",
-boot_type="init",
-length=constants.long_tag,
-)
-
-test_boot(
-cpu="timing",
-num_cpus=4,
-mem_system="classic",
-memory_class="DualChannelDDR3_2133",
-boot_type="init",
+boot_type="systemd",
 length=constants.long_tag,
 )

@@ -190,7 +164,7 @@
 cpu="atomic",
 num_cpus=4,
 mem_system="classic",
-memory_class="DualChannelDDR4_2400",
+memory_class="SingleChannelHBM",
 boot_type="systemd",
 length=constants.long_tag,
 )
@@ -209,14 +183,6 @@
 #length=constants.long_tag,
 # )

-test_boot(
-cpu="atomic",
-num_cpus=4,
-mem_system="classic",
-memory_class="HBM2Stack",
-boot_type="systemd",
-length=constants.long_tag,
-)

  The very-long (Weekly) tests 


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[gem5-dev] [L] Change in gem5/gem5[develop]: stdlib,arch-arm: Add ruby cache support to the ArmBoard

2022-11-01 Thread Bobby Bruce (Gerrit) via gem5-dev

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64011?usp=email )


Change subject: stdlib,arch-arm: Add ruby cache support to the ArmBoard
..

stdlib,arch-arm: Add ruby cache support to the ArmBoard

This change adds ruby cache support to the ArmBoard. Previously
only classic caches were supported by the ArmBoard. The ArmBoard
was tested with CHI, MESI_Two_Level and MI_example caches from
the gem5's stdlib.

Change-Id: I480fe6ae13e3bd8438a425548ed113d443fcee40
Signed-off-by: Kaustav Goswami 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64011
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Giacomo Travaglini 
Maintainer: Bobby Bruce 
---
M configs/example/gem5_library/arm-ubuntu-boot-exit.py
M src/python/gem5/components/boards/arm_board.py
M tests/gem5/arm-boot-tests/test_linux_boot.py
M tests/gem5/configs/arm_boot_exit_run.py
4 files changed, 337 insertions(+), 174 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, but someone else must approve




diff --git a/configs/example/gem5_library/arm-ubuntu-boot-exit.py  
b/configs/example/gem5_library/arm-ubuntu-boot-exit.py

index 201fb23..70608ec 100644
--- a/configs/example/gem5_library/arm-ubuntu-boot-exit.py
+++ b/configs/example/gem5_library/arm-ubuntu-boot-exit.py
@@ -25,11 +25,10 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 """
-This script shows an example of booting an ARM based full system Ubuntu
-disk image using the gem5's standard library. This simulation boots the  
disk

-image using 2 TIMING CPU cores. The simulation ends when the startup is
-completed successfully (i.e. when an `m5_exit instruction is reached on
-successful boot).
+This script further shows an example of booting an ARM based full system  
Ubuntu
+disk image. This simulation boots the disk image using 2 TIMING CPU cores.  
The

+simulation ends when the startup is completed successfully (i.e. when an
+`m5_exit instruction is reached on successful boot).

 Usage
 -
@@ -44,27 +43,26 @@
 from gem5.isas import ISA
 from m5.objects import ArmDefaultRelease
 from gem5.utils.requires import requires
+from gem5.resources.workload import Workload
 from gem5.simulate.simulator import Simulator
 from m5.objects import VExpress_GEM5_Foundation
+from gem5.coherence_protocol import CoherenceProtocol
 from gem5.components.boards.arm_board import ArmBoard
 from gem5.components.memory import DualChannelDDR4_2400
 from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.processors.simple_processor import SimpleProcessor
-from gem5.resources.workload import Workload

-# This runs a check to ensure the gem5 binary is compiled for ARM.
+
+# This runs a check to ensure the gem5 binary is compiled for ARM and the
+# protocol is CHI.

 requires(isa_required=ISA.ARM)

-# With ARM, we use simple caches.
-
 from  
gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy  
import (

 PrivateL1PrivateL2CacheHierarchy,
 )

-
 # Here we setup the parameters of the l1 and l2 caches.
-
 cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
 l1d_size="16kB", l1i_size="16kB", l2_size="256kB"
 )
diff --git a/src/python/gem5/components/boards/arm_board.py  
b/src/python/gem5/components/boards/arm_board.py

index c814810..eec9432 100644
--- a/src/python/gem5/components/boards/arm_board.py
+++ b/src/python/gem5/components/boards/arm_board.py
@@ -50,10 +50,9 @@
 import m5
 from abc import ABCMeta
 from ...isas import ISA
-from typing import List
-from m5.util import fatal
 from ...utils.requires import requires
 from ...utils.override import overrides
+from typing import List, Sequence, Tuple
 from .abstract_board import AbstractBoard
 from ...resources.resource import AbstractResource
 from .kernel_disk_workload import KernelDiskWorkload
@@ -74,9 +73,7 @@
 Versatile(TM) Express family of boards.

 **Limitations**
-* The board currently does not support ruby caches.
 * stage2 walker ports are ignored.
-* This version does not support SECURITY extension.
 """

 __metaclass__ = ABCMeta
@@ -90,6 +87,11 @@
 platform: VExpress_GEM5_Base = VExpress_GEM5_Foundation(),
 release: ArmRelease = ArmDefaultRelease(),
 ) -> None:
+
+# The platform and the clk has to be set before calling the super  
class

+self._platform = platform
+self._clk_freq = clk_freq
+
 super().__init__()
 AbstractBoard.__init__(
 self,
@@ -100,31 +102,14 @@
 )

 # This board requires ARM ISA to work.
-
 requires(isa_required=ISA.ARM)

-# Setting the voltage domain here.
-
-self.voltage_domain = self.clk_domain.voltage_domain
-
 # Setting up ARM

[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib,configs,tests: Rename config to arm-ubuntu-run.py

2022-11-01 Thread Bobby Bruce (Gerrit) via gem5-dev

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65132?usp=email )


Change subject: stdlib,configs,tests: Rename config to arm-ubuntu-run.py
..

stdlib,configs,tests: Rename config to arm-ubuntu-run.py

The "config/example/gem5_library/arm-ubuntu-boot-exit.py" script is
renamed to "config/example/gem5_library/arm-ubuntu-run.py". This makes
it more consistent with similar scripts in the
"config/example/gem5_library" directory: "x86-ubuntu-run.py" and
"riscv-ubuntu-run.py".

Change-Id: I9d96fd68e122f2841573b1717b0969cd44972771
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65132
Maintainer: Bobby Bruce 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
R configs/example/gem5_library/arm-ubuntu-run.py
M tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
2 files changed, 23 insertions(+), 3 deletions(-)

Approvals:
  kokoro: Regressions pass
  Bobby Bruce: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved




diff --git a/configs/example/gem5_library/arm-ubuntu-boot-exit.py  
b/configs/example/gem5_library/arm-ubuntu-run.py

similarity index 97%
rename from configs/example/gem5_library/arm-ubuntu-boot-exit.py
rename to configs/example/gem5_library/arm-ubuntu-run.py
index 70608ec..7f976f0 100644
--- a/configs/example/gem5_library/arm-ubuntu-boot-exit.py
+++ b/configs/example/gem5_library/arm-ubuntu-run.py
@@ -35,7 +35,7 @@

 ```
 scons build/ARM/gem5.opt -j
-./build/ARM/gem5.opt configs/example/gem5_library/arm-ubuntu-boot-exit.py
+./build/ARM/gem5.opt configs/example/gem5_library/arm-ubuntu-run.py
 ```

 """
diff --git  
a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py  
b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py

index 13aa877..28a10b5 100644
--- a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
+++ b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
@@ -275,7 +275,7 @@
 )

 gem5_verify_config(
-name="test-gem5-library-example-arm-ubuntu-boot-test",
+name="test-gem5-library-example-arm-ubuntu-run-test",
 fixtures=(),
 verifiers=(),
 config=joinpath(
@@ -283,7 +283,7 @@
 "configs",
 "example",
 "gem5_library",
-"arm-ubuntu-boot-exit.py",
+"arm-ubuntu-run.py",
 ),
 config_args=[],
 valid_isas=(constants.all_compiled_tag,),

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9d96fd68e122f2841573b1717b0969cd44972771
Gerrit-Change-Number: 65132
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Refactor the ArmBoard for _connect_things move

2022-11-01 Thread Bobby Bruce (Gerrit) via gem5-dev

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65052?usp=email )


Change subject: stdlib: Refactor the ArmBoard for _connect_things move
..

stdlib: Refactor the ArmBoard for _connect_things move

Since moving `_connect_things` to a pre-init step, the ArmBoard can now
be refactored to set up things in a more logical manner. In particular,
this patch moves activity out of the `_add_disk_to_board` function and
into the `_pre_initialization` function.

Change-Id: I5d40267f28ae87cd483a0396739c09b8b2b46383
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65052
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
---
M src/python/gem5/components/boards/arm_board.py
1 file changed, 68 insertions(+), 50 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/boards/arm_board.py  
b/src/python/gem5/components/boards/arm_board.py

index afb5cd6..7936c0c 100644
--- a/src/python/gem5/components/boards/arm_board.py
+++ b/src/python/gem5/components/boards/arm_board.py
@@ -153,9 +153,6 @@
 # We now need to setup the dma_ports.
 self._dma_ports = None

-# An else part is not required as for CHI protocol, the dma_ports  
has

-# to be set to []
-
 # RealView sets up most of the on-chip and off-chip devices and GIC
 # for the ARM board. These devices' information is also used to
 # generate the dtb file. We then connect the I/O devices to the
@@ -188,19 +185,9 @@
 else:
 raise ValueError("Memory size too big for platform  
capabilities")


-# the image is initially set to None as a sanity check. This is
-# overwritten in the method _setup_pci_devices.
-self._image = None
-
-# Calling _setup_pci_devices. DMA ports has to be setup  
beforehand. PCI
-# devices has to be setup before adding disk to board as the  
dma_ports
-# has to be correctly setup before incorporating ruby caches. The  
issue

-# is that the dma_controllers can only be created correctly when we
-# have the dma_ports for the PCI device. The current order of  
function

-# calls is:
-# ArmBoardAbstractBoard  KernelDiskWorkload
-# _setup_pci_devices() -> incorporate_cache() ->  
_add_disk_to_board()

-self._setup_pci_devices()
+# The PCI Devices. PCI devices can be added via the  
`_add_pci_device`

+# function.
+self._pci_devices = []

 def _setup_io_devices(self) -> None:
 """
@@ -323,52 +310,65 @@
 def connect_system_port(self, port: Port) -> None:
 self.system_port = port

-@overrides(KernelDiskWorkload)
-def get_disk_device(self):
-return "/dev/vda"
+@overrides(AbstractBoard)
+def _pre_instantiate(self):
+super()._pre_instantiate()

-def _setup_pci_devices(self):
+# Add the PCI devices.
+self.pci_devices = self._pci_devices

-# We define the image. The _image has to be None initially.
-assert self._image is None
-
-self._image = CowDiskImage(
-child=RawDiskImage(read_only=True), read_only=False
-)
-
-self.pci_devices = [PciVirtIO(vio=VirtIOBlock(image=self._image))]
-
-for device in self.pci_devices:
-self.realview.attachPciDevice(
-device, self.iobus, dma_ports=self.get_dma_ports()
-)
-
-@overrides(KernelDiskWorkload)
-def _add_disk_to_board(self, disk_image: AbstractResource):
-
-assert self._image is not None
-
-# Now that the disk and workload are set, we can generate the  
device

-# tree file. We will generate the dtb file everytime the board is
-# boot-up.
-self._image.child.image_file = disk_image.get_local_path()
-
-# Specifying the dtb file location to the workload.
-self.workload.dtb_filename = os.path.join(
-m5.options.outdir, "device.dtb"
-)
+# The workload needs to know the dtb_file.
+self.workload.dtb_filename = self._get_dtb_filename()

 # Calling generateDtb from class ArmSystem to add memory  
information to

 # the dtb file.
-self.generateDtb(self.workload.dtb_filename)
+self.generateDtb(self._get_dtb_filename())

 # Finally we need to setup the bootloader for the ArmBoard. An ARM
 # system requires three inputs to simulate a full system: a disk  
image,

 # the kernel file and the bootloader file(s).
 self.realview.setupBootLoader(
-self, self.workload.dtb_filename, self._bootloader
+self, self._get_dtb_filename(), self._bootloader
 )

+def _get_dtb_filename(self) -> str:
+"""Returns

[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Give board interface for mem ports

2022-11-01 Thread Bobby Bruce (Gerrit) via gem5-dev

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64631?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: stdlib: Give board interface for mem ports
..

stdlib: Give board interface for mem ports

It is possible that the board has more than just a "main" memory. For
instance, the ArmBoard has a boot memory which is separate from the
`get_memory` function.

This moves the `get_mem_ports` function to the board so that the board
can optionally override it.

Change-Id: I05e388cc93e691e9a4fa674023f158af447349f9
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64631
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
M src/python/gem5/components/boards/abstract_board.py
M  
src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py
M  
src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
M  
src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py

4 files changed, 34 insertions(+), 4 deletions(-)

Approvals:
  kokoro: Regressions pass
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved




diff --git a/src/python/gem5/components/boards/abstract_board.py  
b/src/python/gem5/components/boards/abstract_board.py

index e22c9ef..720aaca 100644
--- a/src/python/gem5/components/boards/abstract_board.py
+++ b/src/python/gem5/components/boards/abstract_board.py
@@ -31,6 +31,7 @@
 from ...resources.workload import AbstractWorkload

 from m5.objects import (
+AddrRange,
 System,
 Port,
 IOXBar,
@@ -39,7 +40,7 @@
 VoltageDomain,
 )

-from typing import List, Optional
+from typing import List, Optional, Sequence, Tuple


 class AbstractBoard:
@@ -128,6 +129,14 @@
 """
 return self.memory

+def get_mem_ports(self) -> Sequence[Tuple[AddrRange, Port]]:
+"""Get the memory ports exposed on this board
+
+Note: The ports should be returned such that the address ranges are
+in ascending order.
+"""
+return self.get_memory().get_mem_ports()
+
 def get_cache_hierarchy(self) -> Optional["AbstractCacheHierarchy"]:
 """Get the cache hierarchy connected to the board.

diff --git  
a/src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py  
b/src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py

index 2033903..9c91e05 100644
---  
a/src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py
+++  
b/src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py

@@ -202,7 +202,7 @@
 self, board: AbstractBoard
 ) -> List[MemoryController]:
 memory_controllers = []
-for rng, port in board.get_memory().get_mem_ports():
+for rng, port in board.get_mem_ports():
 mc = MemoryController(self.ruby_system.network, rng, port)
 mc.ruby_system = self.ruby_system
 memory_controllers.append(mc)
diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py  
b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py

index 96c7b70..82089a5 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py

@@ -147,7 +147,7 @@

 self._directory_controllers = [
 Directory(self.ruby_system.network, cache_line_size, range,  
port)

-for range, port in board.get_memory().get_mem_ports()
+for range, port in board.get_mem_ports()
 ]
 # TODO: Make this prettier: The problem is not being able to proxy
 # the ruby system correctly
diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py  
b/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py

index e3cf714..5955ad3 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py

@@ -118,7 +118,7 @@

 # Create the directory controllers
 self._directory_controllers = []
-for range, port in board.get_memory().get_mem_ports():
+for range, port in board.get_mem_ports():
 dir = Directory(
 self.ruby_system.network,
 board.get_cache_line_size(),

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id:

[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Move `_connect_things` to run as pre_instantiation

2022-11-01 Thread Bobby Bruce (Gerrit) via gem5-dev

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65051?usp=email )


 (

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: stdlib: Move `_connect_things` to run as pre_instantiation
..

stdlib: Move `_connect_things` to run as pre_instantiation

Through working with the gem5 stdlib there have been instances where
connecting the memory, processor, and cache hierarchy to the board (via
the AbstractBoard's `_connect_things` function) at the point of the
AbstractBoard's construction is problematic as the memory, processor,
and cache hierarchy may require information to connect correctly that is
only known to the AbstractBoard after construction. In particular this
can occur when a Workload contains information needed to configure
correctly.

To resolve this problem the `_connect_things` function has been moved to
run as a pre-initialization step. That is, run immediately before
`m5.instantiate`. This is done in the Simulator module.

This will break cases where a user utilizes the stdlib AbstractBoard but
does not use the stdlib Simulator module. As such, an Exception is
raised in these cases explaining the fix to the user. This is done via a
hack where the boards' `createCCObject` function (inheritted
from SimObject) is overriden with a check to ensure `_connect_things`
has been run. To fix the `_pre_instantiate` function must be executed
prior to `m5.instantiate` in the Python configuration script. Test and
config scripts in the gem5 repo have been updated accordingly.

Change-Id: Ibaef36eb7433ce104b861b1da80fc600f08f715a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65051
Maintainer: Bobby Bruce 
Reviewed-by: Giacomo Travaglini 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/example/gem5_library/x86-gapbs-benchmarks.py
M configs/example/gem5_library/x86-npb-benchmarks.py
M configs/example/gem5_library/x86-parsec-benchmarks.py
M configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
M configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
M src/python/gem5/components/boards/abstract_board.py
M src/python/gem5/components/boards/abstract_system_board.py
M src/python/gem5/components/boards/arm_board.py
M src/python/gem5/simulate/simulator.py
M tests/gem5/configs/boot_kvm_fork_run.py
M tests/gem5/traffic_gen/simple_traffic_run.py
11 files changed, 119 insertions(+), 4 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, but someone else must approve




diff --git a/configs/example/gem5_library/x86-gapbs-benchmarks.py  
b/configs/example/gem5_library/x86-gapbs-benchmarks.py

index 4078811..bdc0d94 100644
--- a/configs/example/gem5_library/x86-gapbs-benchmarks.py
+++ b/configs/example/gem5_library/x86-gapbs-benchmarks.py
@@ -216,6 +216,7 @@

 root.sim_quantum = int(1e9)

+board._pre_instantiate()
 m5.instantiate()

 # We maintain the wall clock time.
diff --git a/configs/example/gem5_library/x86-npb-benchmarks.py  
b/configs/example/gem5_library/x86-npb-benchmarks.py

index b3a78c2..385760c 100644
--- a/configs/example/gem5_library/x86-npb-benchmarks.py
+++ b/configs/example/gem5_library/x86-npb-benchmarks.py
@@ -218,6 +218,7 @@

 root.sim_quantum = int(1e9)

+board._pre_instantiate()
 m5.instantiate()

 # We maintain the wall clock time.
diff --git a/configs/example/gem5_library/x86-parsec-benchmarks.py  
b/configs/example/gem5_library/x86-parsec-benchmarks.py

index 08fa636..8218380 100644
--- a/configs/example/gem5_library/x86-parsec-benchmarks.py
+++ b/configs/example/gem5_library/x86-parsec-benchmarks.py
@@ -204,6 +204,7 @@

 root.sim_quantum = int(1e9)

+board._pre_instantiate()
 m5.instantiate()

 # We maintain the wall clock time.
diff --git a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py  
b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py

index 0bdc5ed..d656e61 100644
--- a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
+++ b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
@@ -274,6 +274,7 @@

 root.sim_quantum = int(1e9)

+board._pre_instantiate()
 m5.instantiate()

 # We maintain the wall clock time.
diff --git a/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py  
b/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py

index 6b0cc11..2bc948a 100644
--- a/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
+++ b/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
@@ -290,6 +290,7 @@

 root.sim_quantum = int(1e9)

+board._pre_instantiate()
 m5.instantiate()

 # We maintain the wall clock time.
diff --git a/src/python/gem5/components/boards/abstract_board.py  
b/src/python/gem5/components/boards/abstract_board.py

index 720aaca..4ea8866 100644
---

[gem5-dev] [S] Change in gem5/gem5[develop]: configs: GPUFS: use multiple event queues for >1 CPU

2022-11-01 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65131?usp=email )


Change subject: configs: GPUFS: use multiple event queues for >1 CPU
..

configs: GPUFS: use multiple event queues for >1 CPU

The KVM CPU hangs if there are not multiple event queues when more than
one CPU is created. Since GPUFS primarily relies on the KVM CPU, support
for multiple event queues is needed. Some GPU libraries, such as AMD
Research's ATMI library, assume more than one CPU.

This changeset adds support for multiple CPUs and was tested for up to
four CPUs.

Change-Id: Ia354e02209d0fa18195f3ad44f4fb1d58e93b5ca
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65131
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Maintainer: Matt Sinclair 
Reviewed-by: Matt Sinclair 
---
M configs/example/gpufs/runfs.py
M configs/example/gpufs/system/system.py
2 files changed, 39 insertions(+), 0 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/gpufs/runfs.py b/configs/example/gpufs/runfs.py
index 944a46a..781ce8e 100644
--- a/configs/example/gpufs/runfs.py
+++ b/configs/example/gpufs/runfs.py
@@ -133,6 +133,11 @@
 that should not be changed by the user.
 """

+# GPUFS is primarily designed to use the X86 KVM CPU. This model needs  
to
+# use multiple event queues when more than one CPU is simulated. Force  
it

+# on if that is the case.
+args.host_parallel = True if args.num_cpus > 1 else False
+
 # These are used by the protocols. They should not be set by the user.
 n_cu = args.num_compute_units
 args.num_sqc = int(math.ceil(float(n_cu) / args.cu_per_sqc))
@@ -149,6 +154,9 @@
 time_sync_period="1000us",
 )

+if args.host_parallel:
+root.sim_quantum = int(1e8)
+
 if args.script is not None:
 system.readfile = args.script

diff --git a/configs/example/gpufs/system/system.py  
b/configs/example/gpufs/system/system.py

index 46b023f..a1b59ef 100644
--- a/configs/example/gpufs/system/system.py
+++ b/configs/example/gpufs/system/system.py
@@ -204,6 +204,15 @@
 for j in range(len(system.cpu[i].isa)):
 system.cpu[i].isa[j].vendor_string = "AuthenticAMD"

+if args.host_parallel:
+# To get the KVM CPUs to run on different host CPUs, specify a
+# different event queue for each CPU.  The last CPU is a GPU
+# shader and should be skipped.
+for i, cpu in enumerate(system.cpu[:-1]):
+for obj in cpu.descendants():
+obj.eventq_index = 0
+cpu.eventq_index = i + 1
+
 gpu_port_idx = (
 len(system.ruby._cpu_ports)
 - args.num_compute_units

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia354e02209d0fa18195f3ad44f4fb1d58e93b5ca
Gerrit-Change-Number: 65131
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: dev-amdgpu: Fix issues with PM4 queue map, fences

2022-11-01 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65095?usp=email )


Change subject: dev-amdgpu: Fix issues with PM4 queue map, fences
..

dev-amdgpu: Fix issues with PM4 queue map, fences

The PM4 release_mem packet is used as a DMA fence in the driver. It
specifies which queue the interrupt came from by encoding the me, pipe,
and queue fields from the map_queue packet into the interrupt ring ID.
Currently these fields are incorrect because (1) the order in the
bitfield is backwards, (2) the queue constructor assigns a pointer to
the PM4MapQueue packet containing this data to the dmaBuffer which gets
deleted in short order, and (3) the order of the encoding of ring ID is
incorrect.

This change fixes these issues by (1) placing the struct vales in
correct order, (2) creating a const copy of the dmaBuffer on
construction, and (3) using the ring ID encoding expected by the driver:
https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/roc-4.3.x/
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c#L5989

Change-Id: I72c382980e57573f8a8a6879912c4139c7e2f505
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65095
Tested-by: kokoro 
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
---
M src/dev/amdgpu/pm4_defines.hh
M src/dev/amdgpu/pm4_packet_processor.cc
M src/dev/amdgpu/pm4_packet_processor.hh
M src/dev/amdgpu/pm4_queues.hh
4 files changed, 54 insertions(+), 21 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/amdgpu/pm4_defines.hh b/src/dev/amdgpu/pm4_defines.hh
index b690e54..42832d5 100644
--- a/src/dev/amdgpu/pm4_defines.hh
+++ b/src/dev/amdgpu/pm4_defines.hh
@@ -124,9 +124,9 @@
 uint32_t reserved2 : 2;
 uint32_t vmid : 4;
 uint32_t reserved3 : 1;
-uint32_t me : 1;
-uint32_t pipe : 2;
 uint32_t queueSlot : 3;
+uint32_t pipe : 2;
+uint32_t me : 1;
 uint32_t reserved6 : 2;
 uint32_t queueType : 3;
 uint32_t allocFormat : 2;
diff --git a/src/dev/amdgpu/pm4_packet_processor.cc  
b/src/dev/amdgpu/pm4_packet_processor.cc

index 48496f6..404beab 100644
--- a/src/dev/amdgpu/pm4_packet_processor.cc
+++ b/src/dev/amdgpu/pm4_packet_processor.cc
@@ -116,14 +116,14 @@
 PM4PacketProcessor::mapKiq(Addr offset)
 {
 DPRINTF(PM4PacketProcessor, "Mapping KIQ\n");
-newQueue((QueueDesc *), offset);
+newQueue((QueueDesc *), offset, _pkt);
 }

 void
 PM4PacketProcessor::mapPq(Addr offset)
 {
 DPRINTF(PM4PacketProcessor, "Mapping PQ\n");
-newQueue((QueueDesc *), offset);
+newQueue((QueueDesc *), offset, _pkt);
 }

 void
@@ -146,8 +146,9 @@
   : QueueType::Compute;
 gpuDevice->setDoorbellType(offset, qt);

-DPRINTF(PM4PacketProcessor, "New PM4 queue %d, base: %p offset: %p\n",
-id, q->base(), q->offset());
+DPRINTF(PM4PacketProcessor, "New PM4 queue %d, base: %p offset: %p,  
me: "

+"%d, pipe %d queue: %d\n", id, q->base(), q->offset(), q->me(),
+q->pipe(), q->queue());
 }

 void
@@ -490,14 +491,16 @@
 DPRINTF(PM4PacketProcessor, "PM4 release_mem wrote %d to %p\n",
 pkt->dataLo, addr);
 if (pkt->intSelect == 2) {
-DPRINTF(PM4PacketProcessor, "PM4 interrupt, ctx: %d, me: %d,  
pipe: "

-"%d, queueSlot:%d\n", pkt->intCtxId, q->me(), q->pipe(),
-q->queue());
-// Rearranging the queue field of PM4MapQueues as the interrupt  
RingId

-// format specified in PM4ReleaseMem pkt.
-uint32_t ringId = (q->me() << 6) | (q->pipe() << 4) | q->queue();
+DPRINTF(PM4PacketProcessor, "PM4 interrupt, id: %d ctx: %d,  
me: %d, "
+"pipe: %d, queueSlot:%d\n", q->id(), pkt->intCtxId,  
q->me(),

+q->pipe(), q->queue());
+
+uint8_t ringId = 0;
+if (q->id() != 0) {
+ringId = (q->queue() << 4) | (q->me() << 2) | q->pipe();
+}
 gpuDevice->getIH()->prepareInterruptCookie(pkt->intCtxId, ringId,
-SOC15_IH_CLIENTID_GRBM_CP, CP_EOP);
+SOC15_IH_CLIENTID_GRBM_CP,  
CP_EOP);

 gpuDevice->getIH()->submitInterruptCookie();
 }

diff --git a/src/dev/amdgpu/pm4_packet_processor.hh  
b/src/dev/amdgpu/pm4_packet_processor.hh

index c77edd2..4806671 100644
--- a/src/dev/amdgpu/pm4_packet_processor.hh
+++ b/src/dev/amdgpu/pm4_packet_processor.hh
@@ -54,8 +54,10 @@
 AMDGPUDevice *gpuDevice;
 /* First graphics queue */
 PrimaryQueue pq;
+PM4MapQueues pq_pkt;
 /* First compute queue */
 QueueDesc kiq;
+PM4MapQueues kiq_pkt;

 /* All PM4 queues, indexed by VMID */
 std::unordered_map queues;
diff --git a/src/dev/amdgpu/pm4_queues.hh b/src/dev/amdgpu/pm4_queues.hh
index 4e8638b..19973b1 100644
--- a/src/dev/amdgpu/pm4_queues.hh
+++

[gem5-dev] [S] Change in gem5/gem5[develop]: dev-amdgpu: Fix SDMA trap ring ID, context

2022-11-01 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65093?usp=email )


Change subject: dev-amdgpu: Fix SDMA trap ring ID, context
..

dev-amdgpu: Fix SDMA trap ring ID, context

SDMA traps are used in the driver as a DMA fence. To pass a fence, the
SDMA sends the driver the interrupt context from a trap packet and the
ring ID which specifies which queue in the SDMA engine is passing a
fence. Currently the interrupt context is using the wrong value in the
packet and the ring ID is hard-coded to always be the gfx queue.

This changeset uses the correct interrupt context from the SDMA packet
and sets the ring ID to either 0 if the gfx queue is currently being
processed or 3 if the page queue is being processed.

The relevant interrupt service routine in the driver can be found at:
https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/roc-4.3.x/
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c#L2129

Change-Id: Ie4a4a9d6ab1d3bf83bf76bb57a02a91100217b51
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65093
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/dev/amdgpu/sdma_engine.cc
1 file changed, 36 insertions(+), 4 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/amdgpu/sdma_engine.cc b/src/dev/amdgpu/sdma_engine.cc
index 1cd6ff2..e9a4c17 100644
--- a/src/dev/amdgpu/sdma_engine.cc
+++ b/src/dev/amdgpu/sdma_engine.cc
@@ -713,11 +713,16 @@
 {
 q->incRptr(sizeof(sdmaTrap));

-DPRINTF(SDMAEngine, "Trap contextId: %p rbRptr: %p ibOffset: %p\n",
-pkt->contextId, pkt->rbRptr, pkt->ibOffset);
+DPRINTF(SDMAEngine, "Trap contextId: %p\n", pkt->intrContext);

-gpuDevice->getIH()->prepareInterruptCookie(pkt->contextId, 0,
-getIHClientId(), TRAP_ID);
+uint32_t ring_id = 0;
+assert(page.processing() ^ gfx.processing());
+if (page.processing()) {
+ring_id = 3;
+}
+
+gpuDevice->getIH()->prepareInterruptCookie(pkt->intrContext, ring_id,
+   getIHClientId(), TRAP_ID);
 gpuDevice->getIH()->submitInterruptCookie();

 delete pkt;

--
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Gerrit-Change-Number: 65093
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[gem5-dev] [S] Change in gem5/gem5[develop]: dev-amdgpu: Fix interrupt handler address assignment

2022-11-01 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65092?usp=email )


Change subject: dev-amdgpu: Fix interrupt handler address assignment
..

dev-amdgpu: Fix interrupt handler address assignment

The interrupt handler's base address is sent via MMIO and must be
shifted by 8 bits to convert to a byte address. The current code is
shifting the MMIO dword first then assigning, resulting in the top 8
bits being shifted out.

This changeset fixes the issue by assigning the dword to the 64-bit
address first then shifting after. Similarly, the upper dword is cast to
a 64-bit value first before shifting.

This fixes some "fence fallback timeout" errors in the m5term output.
These timeouts become a problem because the driver will reset after a
few hundred of them, killing any running GPU applications as part of the
process.

Change-Id: I0beec313f533765c94063bcf4de8c65aacf2986b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65092
Tested-by: kokoro 
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
---
M src/dev/amdgpu/interrupt_handler.cc
1 file changed, 30 insertions(+), 4 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/amdgpu/interrupt_handler.cc  
b/src/dev/amdgpu/interrupt_handler.cc

index 585c1cf..a771976 100644
--- a/src/dev/amdgpu/interrupt_handler.cc
+++ b/src/dev/amdgpu/interrupt_handler.cc
@@ -202,15 +202,14 @@
 void
 AMDGPUInterruptHandler::setBase(const uint32_t )
 {
-regs.IH_Base = data << 8;
-regs.baseAddr |= regs.IH_Base;
+regs.baseAddr = data;
+regs.baseAddr <<= 8;
 }

 void
 AMDGPUInterruptHandler::setBaseHi(const uint32_t )
 {
-regs.IH_Base_Hi = data;
-regs.baseAddr |= ((uint64_t)regs.IH_Base_Hi) << 32;
+regs.baseAddr |= static_cast(data) << 40;
 }

 void

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Gerrit-Change-Number: 65092
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Alexandru Duțu (Alex) 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] [S] Change in gem5/gem5[develop]: dev-amdgpu: Rework PM4 NOP packet

2022-11-01 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65094?usp=email )


Change subject: dev-amdgpu: Rework PM4 NOP packet
..

dev-amdgpu: Rework PM4 NOP packet

The PM4 NOP header is used to insert spaces in the PM4 ring and can
therefore be any size. This includes zero. A size of zero is denoted by
a value of 0x3fff in the NOP packet header. Currently we assume this
means the remainder of the PM4 queue up to the wptr is empty/NOPs. This
is not always true.

This changeset reworks the PM4 NOP packet to handle the value of 0x3fff
as a special value and advances the rptr by 0 bytes. This fixes issues
where there were additional packets in the queue which were being
skipped over by fast forwarding. Since those packets could be anything,
that leads to undefined behavior afterwards.

Change-Id: I3f5c3f4b7dd50f93ba503fea97454a9d41771e30
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65094
Maintainer: Matt Sinclair 
Tested-by: kokoro 
Reviewed-by: Matt Sinclair 
---
M src/dev/amdgpu/pm4_packet_processor.cc
1 file changed, 26 insertions(+), 3 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/amdgpu/pm4_packet_processor.cc  
b/src/dev/amdgpu/pm4_packet_processor.cc

index 67c150a..48496f6 100644
--- a/src/dev/amdgpu/pm4_packet_processor.cc
+++ b/src/dev/amdgpu/pm4_packet_processor.cc
@@ -202,9 +202,7 @@
   case IT_NOP: {
 DPRINTF(PM4PacketProcessor, "PM4 nop, count %p\n", header.count);
 DPRINTF(PM4PacketProcessor, "rptr %p wptr %p\n", q->rptr(),  
q->wptr());

-if (header.count == 0x3fff) {
-q->fastforwardRptr();
-} else {
+if (header.count != 0x3fff) {
 q->incRptr((header.count + 1) * sizeof(uint32_t));
 }
 decodeNext(q);

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Gerrit-Change-Number: 65094
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba 
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Gerrit-Reviewer: Matt Sinclair 
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove ISA::haveGICv3CpuIfc method

2022-11-01 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65173?usp=email )



Change subject: arch-arm: Remove ISA::haveGICv3CpuIfc method
..

arch-arm: Remove ISA::haveGICv3CpuIfc method

The method is really not needed as we do not implement
GICv3 in legacy mode... Therefore when we want to check if
the GICv3 cpu interface is present, we can just check for
GICv3 being present

Change-Id: I264f887392d188a515480c2e31a4a4da3e67c498
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/regs/misc.cc
M src/arch/arm/utility.cc
4 files changed, 36 insertions(+), 33 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 8813082..a30fd94 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -79,8 +79,7 @@
 } // anonymous namespace

 ISA::ISA(const Params ) : BaseISA(p), system(NULL),
-_decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop),
-afterStartup(false)
+_decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop)
 {
 _regClasses.push_back();
 _regClasses.push_back();
@@ -513,8 +512,6 @@
 tc->setHtmCheckpointPtr(std::move(cpt));
 }
 }
-
-afterStartup = true;
 }

 void
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 218cf9c..1f7a756 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -104,8 +104,6 @@
  */
 bool impdefAsNop;

-bool afterStartup;
-
 SelfDebug * selfDebug;

 const MiscRegLUTEntryInitializer
@@ -394,17 +392,6 @@

 enums::DecoderFlavor decoderFlavor() const { return  
_decoderFlavor; }


-/** Returns true if the ISA has a GICv3 cpu interface */
-bool
-haveGICv3CpuIfc() const
-{
-// gicv3CpuInterface is initialized at startup time, hence
-// trying to read its value before the startup stage will lead
-// to an error
-assert(afterStartup);
-return gicv3CpuInterface != nullptr;
-}
-
 PARAMS(ArmISA);

 ISA(const Params );
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index b6f8aac..155da19 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -1619,12 +1619,24 @@
 }

 Fault
+faultGicv3(const MiscRegLUTEntry ,
+ThreadContext *tc, const MiscRegOp64 )
+{
+auto gic = static_cast(tc->getSystemPtr())->getGIC();
+if (!gic->supportsVersion(BaseGic::GicVersion::GIC_V3)) {
+return inst.undefined();
+} else {
+return NoFault;
+}
+}
+
+Fault
 faultIccSgiEL1(const MiscRegLUTEntry ,
 ThreadContext *tc, const MiscRegOp64 )
 {
-auto *isa = static_cast(tc->getIsaPtr());
-if (!isa->haveGICv3CpuIfc())
-return inst.undefined();
+if (auto fault = faultGicv3(entry, tc, inst); fault != NoFault) {
+return fault;
+}

 const Gicv3CPUInterface::ICH_HCR_EL2 ich_hcr =
 tc->readMiscReg(MISCREG_ICH_HCR_EL2);
@@ -1643,9 +1655,9 @@
 faultIccSgiEL2(const MiscRegLUTEntry ,
 ThreadContext *tc, const MiscRegOp64 )
 {
-auto *isa = static_cast(tc->getIsaPtr());
-if (!isa->haveGICv3CpuIfc())
-return inst.undefined();
+if (auto fault = faultGicv3(entry, tc, inst); fault != NoFault) {
+return fault;
+}

 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
 if (ArmSystem::haveEL(tc, EL3) && scr.irq && scr.fiq) {
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index d7185f2..6764569 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -626,19 +626,11 @@
 break;
   // GICv3 regs
   case MISCREG_ICC_SGI0R:
-{
-auto *isa = static_cast*>(tc->getIsaPtr());

-if (isa->haveGICv3CpuIfc())
-trap_to_hyp = hcr.fmo;
-}
+trap_to_hyp = hcr.fmo;
 break;
   case MISCREG_ICC_SGI1R:
   case MISCREG_ICC_ASGI1R:
-{
-auto *isa = static_cast*>(tc->getIsaPtr());

-if (isa->haveGICv3CpuIfc())
-trap_to_hyp = hcr.imo;
-}
+trap_to_hyp = hcr.imo;
 break;
   case MISCREG_CNTFRQ ... MISCREG_CNTV_TVAL:
 // CNTFRQ may be trapped only on reads

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Gerrit-Change-Id: I264f887392d188a515480c2e31a4a4da3e67c498
Gerrit-Change-Number: 65173
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Fix GICv3 List register mapping

2022-11-01 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65172?usp=email )



Change subject: arch-arm: Fix GICv3 List register mapping
..

arch-arm: Fix GICv3 List register mapping

Change-Id: I870104cf27cc9ba28763adc5b43ff850c1ea279f
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/regs/misc.cc
1 file changed, 42 insertions(+), 32 deletions(-)



diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 349ebb2..b6f8aac 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -4664,37 +4664,53 @@
 .hyp().mon()
 .mapsTo(MISCREG_ICH_VMCR);
 InitReg(MISCREG_ICH_LR0_EL2)
-.hyp().mon();
+.hyp().mon()
+.mapsTo(MISCREG_ICH_LR0, MISCREG_ICH_LRC0);
 InitReg(MISCREG_ICH_LR1_EL2)
-.hyp().mon();
+.hyp().mon()
+.mapsTo(MISCREG_ICH_LR1, MISCREG_ICH_LRC1);
 InitReg(MISCREG_ICH_LR2_EL2)
-.hyp().mon();
+.hyp().mon()
+.mapsTo(MISCREG_ICH_LR2, MISCREG_ICH_LRC2);
 InitReg(MISCREG_ICH_LR3_EL2)
-.hyp().mon();
+.hyp().mon()
+.mapsTo(MISCREG_ICH_LR3, MISCREG_ICH_LRC3);
 InitReg(MISCREG_ICH_LR4_EL2)
-.hyp().mon();
+.hyp().mon()
+.mapsTo(MISCREG_ICH_LR4, MISCREG_ICH_LRC4);
 InitReg(MISCREG_ICH_LR5_EL2)
-.hyp().mon();
+.hyp().mon()
+.mapsTo(MISCREG_ICH_LR5, MISCREG_ICH_LRC5);
 InitReg(MISCREG_ICH_LR6_EL2)
-.hyp().mon();
+.hyp().mon()
+.mapsTo(MISCREG_ICH_LR6, MISCREG_ICH_LRC6);
 InitReg(MISCREG_ICH_LR7_EL2)
-.hyp().mon();
+.hyp().mon()
+.mapsTo(MISCREG_ICH_LR7, MISCREG_ICH_LRC7);
 InitReg(MISCREG_ICH_LR8_EL2)
-.hyp().mon();
+.hyp().mon()
+.mapsTo(MISCREG_ICH_LR8, MISCREG_ICH_LRC8);
 InitReg(MISCREG_ICH_LR9_EL2)
-.hyp().mon();
+.hyp().mon()
+.mapsTo(MISCREG_ICH_LR9, MISCREG_ICH_LRC9);
 InitReg(MISCREG_ICH_LR10_EL2)
-.hyp().mon();
+.hyp().mon()
+.mapsTo(MISCREG_ICH_LR10, MISCREG_ICH_LRC10);
 InitReg(MISCREG_ICH_LR11_EL2)
-.hyp().mon();
+.hyp().mon()
+.mapsTo(MISCREG_ICH_LR11, MISCREG_ICH_LRC11);
 InitReg(MISCREG_ICH_LR12_EL2)
-.hyp().mon();
+.hyp().mon()
+.mapsTo(MISCREG_ICH_LR12, MISCREG_ICH_LRC12);
 InitReg(MISCREG_ICH_LR13_EL2)
-.hyp().mon();
+.hyp().mon()
+.mapsTo(MISCREG_ICH_LR13, MISCREG_ICH_LRC13);
 InitReg(MISCREG_ICH_LR14_EL2)
-.hyp().mon();
+.hyp().mon()
+.mapsTo(MISCREG_ICH_LR14, MISCREG_ICH_LRC14);
 InitReg(MISCREG_ICH_LR15_EL2)
-.hyp().mon();
+.hyp().mon()
+.mapsTo(MISCREG_ICH_LR15, MISCREG_ICH_LRC15);

 // GICv3 AArch32
 InitReg(MISCREG_ICC_AP0R0)
@@ -4851,52 +4867,36 @@
 InitReg(MISCREG_ICH_LR15)
 .hyp().mon();
 InitReg(MISCREG_ICH_LRC0)
-.mapsTo(MISCREG_ICH_LR0)
 .hyp().mon();
 InitReg(MISCREG_ICH_LRC1)
-.mapsTo(MISCREG_ICH_LR1)
 .hyp().mon();
 InitReg(MISCREG_ICH_LRC2)
-.mapsTo(MISCREG_ICH_LR2)
 .hyp().mon();
 InitReg(MISCREG_ICH_LRC3)
-.mapsTo(MISCREG_ICH_LR3)
 .hyp().mon();
 InitReg(MISCREG_ICH_LRC4)
-.mapsTo(MISCREG_ICH_LR4)
 .hyp().mon();
 InitReg(MISCREG_ICH_LRC5)
-.mapsTo(MISCREG_ICH_LR5)
 .hyp().mon();
 InitReg(MISCREG_ICH_LRC6)
-.mapsTo(MISCREG_ICH_LR6)
 .hyp().mon();
 InitReg(MISCREG_ICH_LRC7)
-.mapsTo(MISCREG_ICH_LR7)
 .hyp().mon();
 InitReg(MISCREG_ICH_LRC8)
-.mapsTo(MISCREG_ICH_LR8)
 .hyp().mon();
 InitReg(MISCREG_ICH_LRC9)
-.mapsTo(MISCREG_ICH_LR9)
 .hyp().mon();
 InitReg(MISCREG_ICH_LRC10)
-.mapsTo(MISCREG_ICH_LR10)
 .hyp().mon();
 InitReg(MISCREG_ICH_LRC11)
-.mapsTo(MISCREG_ICH_LR11)
 .hyp().mon();
 InitReg(MISCREG_ICH_LRC12)
-.mapsTo(MISCREG_ICH_LR12)
 .hyp().mon();
 InitReg(MISCREG_ICH_LRC13)
-.mapsTo(MISCREG_ICH_LR13)
 .hyp().mon();
 InitReg(MISCREG_ICH_LRC14)
-.mapsTo(MISCREG_ICH_LR14)
 .hyp().mon();
 InitReg(MISCREG_ICH_LRC15)
-.mapsTo(MISCREG_ICH_LR15)
 .hyp().mon();

 // SVE

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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Fix access permissions for GICv3 cpu registers

2022-11-01 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65171?usp=email )



Change subject: arch-arm: Fix access permissions for GICv3 cpu registers
..

arch-arm: Fix access permissions for GICv3 cpu registers

* ICC_SRE_EL3/ICC_CTLR_EL3/MISCREG_ICC_IGRPEN1_EL3 are accessible at EL3
only

* ICH_LR_EL2 are accessible at EL2 and EL3 only

Change-Id: Idcd9656abafc3014d2715cd6f138a6d786bc6c34
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/regs/misc.cc
1 file changed, 40 insertions(+), 35 deletions(-)



diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index a534c65..349ebb2 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -4612,32 +4612,38 @@
 .hyp().mon()
 .mapsTo(MISCREG_ICC_HSRE);
 InitReg(MISCREG_ICC_CTLR_EL3)
-.allPrivileges().exceptUserMode()
+.mon()
 .mapsTo(MISCREG_ICC_MCTLR);
 InitReg(MISCREG_ICC_SRE_EL3)
-.allPrivileges().exceptUserMode()
+.mon()
 .mapsTo(MISCREG_ICC_MSRE);
 InitReg(MISCREG_ICC_IGRPEN1_EL3)
-.allPrivileges().exceptUserMode()
+.mon()
 .mapsTo(MISCREG_ICC_MGRPEN1);

 InitReg(MISCREG_ICH_AP0R0_EL2)
 .hyp().mon()
 .mapsTo(MISCREG_ICH_AP0R0);
 InitReg(MISCREG_ICH_AP0R1_EL2)
+.hyp().mon()
 .mapsTo(MISCREG_ICH_AP0R1);
 InitReg(MISCREG_ICH_AP0R2_EL2)
+.hyp().mon()
 .mapsTo(MISCREG_ICH_AP0R2);
 InitReg(MISCREG_ICH_AP0R3_EL2)
+.hyp().mon()
 .mapsTo(MISCREG_ICH_AP0R3);
 InitReg(MISCREG_ICH_AP1R0_EL2)
 .hyp().mon()
 .mapsTo(MISCREG_ICH_AP1R0);
 InitReg(MISCREG_ICH_AP1R1_EL2)
+.hyp().mon()
 .mapsTo(MISCREG_ICH_AP1R1);
 InitReg(MISCREG_ICH_AP1R2_EL2)
+.hyp().mon()
 .mapsTo(MISCREG_ICH_AP1R2);
 InitReg(MISCREG_ICH_AP1R3_EL2)
+.hyp().mon()
 .mapsTo(MISCREG_ICH_AP1R3);
 InitReg(MISCREG_ICH_HCR_EL2)
 .hyp().mon()
@@ -4658,53 +4664,37 @@
 .hyp().mon()
 .mapsTo(MISCREG_ICH_VMCR);
 InitReg(MISCREG_ICH_LR0_EL2)
-.hyp().mon()
-.allPrivileges().exceptUserMode();
+.hyp().mon();
 InitReg(MISCREG_ICH_LR1_EL2)
-.hyp().mon()
-.allPrivileges().exceptUserMode();
+.hyp().mon();
 InitReg(MISCREG_ICH_LR2_EL2)
-.hyp().mon()
-.allPrivileges().exceptUserMode();
+.hyp().mon();
 InitReg(MISCREG_ICH_LR3_EL2)
-.hyp().mon()
-.allPrivileges().exceptUserMode();
+.hyp().mon();
 InitReg(MISCREG_ICH_LR4_EL2)
-.hyp().mon()
-.allPrivileges().exceptUserMode();
+.hyp().mon();
 InitReg(MISCREG_ICH_LR5_EL2)
-.hyp().mon()
-.allPrivileges().exceptUserMode();
+.hyp().mon();
 InitReg(MISCREG_ICH_LR6_EL2)
-.hyp().mon()
-.allPrivileges().exceptUserMode();
+.hyp().mon();
 InitReg(MISCREG_ICH_LR7_EL2)
-.hyp().mon()
-.allPrivileges().exceptUserMode();
+.hyp().mon();
 InitReg(MISCREG_ICH_LR8_EL2)
-.hyp().mon()
-.allPrivileges().exceptUserMode();
+.hyp().mon();
 InitReg(MISCREG_ICH_LR9_EL2)
-.hyp().mon()
-.allPrivileges().exceptUserMode();
+.hyp().mon();
 InitReg(MISCREG_ICH_LR10_EL2)
-.hyp().mon()
-.allPrivileges().exceptUserMode();
+.hyp().mon();
 InitReg(MISCREG_ICH_LR11_EL2)
-.hyp().mon()
-.allPrivileges().exceptUserMode();
+.hyp().mon();
 InitReg(MISCREG_ICH_LR12_EL2)
-.hyp().mon()
-.allPrivileges().exceptUserMode();
+.hyp().mon();
 InitReg(MISCREG_ICH_LR13_EL2)
-.hyp().mon()
-.allPrivileges().exceptUserMode();
+.hyp().mon();
 InitReg(MISCREG_ICH_LR14_EL2)
-.hyp().mon()
-.allPrivileges().exceptUserMode();
+.hyp().mon();
 InitReg(MISCREG_ICH_LR15_EL2)
-.hyp().mon()
-.allPrivileges().exceptUserMode();
+.hyp().mon();

 // GICv3 AArch32
 InitReg(MISCREG_ICC_AP0R0)

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Gerrit-Change-Number: 65171
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Setup ISA::gicv3CpuInterface on demand only

2022-11-01 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65174?usp=email )



Change subject: arch-arm: Setup ISA::gicv3CpuInterface on demand only
..

arch-arm: Setup ISA::gicv3CpuInterface on demand only

This is aligning with what we are already doing with the CoreTimers:
rather than setting up the interface at ISA::startup, we set it
up on the first time the GIC cpu interface is actually required
by the ISA

Change-Id: Iec29b2098ea29ca2886a69c5db8a2bc8d2f6f71e
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/isa.cc
1 file changed, 26 insertions(+), 11 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index a30fd94..50c88ac 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -523,16 +523,6 @@
 return;

 selfDebug->init(tc);
-
-Gicv3 *gicv3 = dynamic_cast(system->getGIC());
-if (!gicv3)
-return;
-
-if (!gicv3CpuInterface)
-gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
-
-gicv3CpuInterface->setISA(this);
-gicv3CpuInterface->setThreadContext(tc);
 }

 void
@@ -2008,7 +1998,17 @@
 BaseISADevice &
 ISA::getGICv3CPUInterface()
 {
-panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!");
+if (gicv3CpuInterface)
+return *gicv3CpuInterface.get();
+
+assert(system);
+Gicv3 *gicv3 = dynamic_cast(system->getGIC());
+assert(gicv3);
+
+gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
+gicv3CpuInterface->setISA(this);
+gicv3CpuInterface->setThreadContext(tc);
+
 return *gicv3CpuInterface.get();
 }


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iec29b2098ea29ca2886a69c5db8a2bc8d2f6f71e
Gerrit-Change-Number: 65174
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
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[gem5-dev] Build failed in Jenkins: nightly #403

2022-11-01 Thread jenkins-no-reply--- via gem5-dev

See 

Changes:

[matthew.poremba] arch-vega: Improve non-native page size support

[matthew.poremba] dev-amdgpu: Chunkify SDMA copies that use device memory

[matthew.poremba] dev-amdgpu: Fix GART PTE size

[yuhsingw] mem: introduce bad command error to packet commands

[yuhsingw] systemc: sync the response error between gem5 packet and tlm payload


--
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 [ CXX] ALL_MSI/arch/power/insts/static_inst.cc -> .o
 [ CXX] ALL_MSI/arch/power/linux/se_workload.cc -> .o
 [ CXX] ALL_MSI/arch/power/isa.cc -> .o
 [ CXX] ALL_MSI/arch/power/process.cc -> .o
 [ CXX] ALL_MSI/arch/power/remote_gdb.cc -> .o
 [ CXX] ALL_MSI/arch/power/se_workload.cc -> .o
 [ CXX] ALL_MSI/arch/power/tlb.cc -> .o
 [ CXX] ALL_MSI/python/_m5/param_PowerISA.cc -> .o
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[gem5-dev] [S] Change in gem5/gem5[develop]: util: update termios to replace nl with cr-nl

2022-11-01 Thread Earl Ou (Gerrit) via gem5-dev

Earl Ou has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65152?usp=email )



Change subject: util: update termios to replace nl with cr-nl
..

util: update termios to replace nl with cr-nl

This change enables OPOST to enable output post-processing. It then
enables ONLCR to prepend newline characters with carriage return so
that start of each line is always left aligned. Note that on some
terminals this might display a redundant ^M.

Change-Id: Ia0b4c61725ab7478e7341273a8279b96e53d9f26
---
M util/term/term.c
1 file changed, 16 insertions(+), 2 deletions(-)



diff --git a/util/term/term.c b/util/term/term.c
index ca88ad4..529712c 100644
--- a/util/term/term.c
+++ b/util/term/term.c
@@ -302,8 +302,8 @@
 memcpy(_ios, , sizeof(struct termios));

 ios.c_iflag &= ~(ISTRIP|ICRNL|IGNCR|ICRNL|IXOFF|IXON);
-ios.c_oflag &= ~(OPOST);
-ios.c_oflag &= (ONLCR);
+ios.c_oflag |= OPOST;
+ios.c_oflag |= ONLCR;
 ios.c_lflag &= ~(ISIG|ICANON|ECHO);
 ios.c_cc[VMIN] = 1;
 ios.c_cc[VTIME] = 0;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia0b4c61725ab7478e7341273a8279b96e53d9f26
Gerrit-Change-Number: 65152
Gerrit-PatchSet: 1
Gerrit-Owner: Earl Ou 
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: sim: allow specifying remote gdb port for each workload

2022-11-01 Thread Earl Ou (Gerrit) via gem5-dev

Earl Ou has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65151?usp=email )



Change subject: sim: allow specifying remote gdb port for each workload
..

sim: allow specifying remote gdb port for each workload

In a platform with multiple systems, we may want to specify the
remote gdb port for each system. This change makes it
possible to specify the port number at each Workload instance.

Change-Id: I755b3960ee920ae5289819aa05d98902614a5615
---
M src/arch/arm/fs_workload.hh
M src/arch/arm/se_workload.hh
M src/arch/mips/se_workload.hh
M src/arch/power/se_workload.hh
M src/arch/riscv/bare_metal/fs_workload.hh
M src/arch/riscv/linux/fs_workload.hh
M src/arch/riscv/se_workload.hh
M src/arch/sparc/fs_workload.hh
M src/arch/sparc/se_workload.hh
M src/arch/x86/fs_workload.hh
M src/arch/x86/linux/se_workload.hh
M src/base/remote_gdb.hh
M src/python/m5/debug.py
M src/python/m5/main.py
M src/python/pybind11/debug.cc
M src/sim/Workload.py
M src/sim/debug.cc
M src/sim/debug.hh
M util/systemc/gem5_within_systemc/sc_gem5_control.cc
M util/systemc/gem5_within_systemc/sc_gem5_control.hh
20 files changed, 48 insertions(+), 53 deletions(-)



diff --git a/src/arch/arm/fs_workload.hh b/src/arch/arm/fs_workload.hh
index 547bbf1..0811f3d 100644
--- a/src/arch/arm/fs_workload.hh
+++ b/src/arch/arm/fs_workload.hh
@@ -153,7 +153,8 @@
 setSystem(System *sys) override
 {
 KernelWorkload::setSystem(sys);
-gdb = BaseRemoteGDB::build(system);
+gdb = BaseRemoteGDB::build(
+params().remote_gdb_port, system);
 }

 Addr
diff --git a/src/arch/arm/se_workload.hh b/src/arch/arm/se_workload.hh
index deb5d3b..f0bf0eb 100644
--- a/src/arch/arm/se_workload.hh
+++ b/src/arch/arm/se_workload.hh
@@ -42,7 +42,7 @@
 class SEWorkload : public gem5::SEWorkload
 {
   public:
-using Params = ArmSEWorkloadParams;
+PARAMS(ArmSEWorkload);

 SEWorkload(const Params , Addr page_shift) :
 gem5::SEWorkload(p, page_shift)
@@ -52,7 +52,8 @@
 setSystem(System *sys) override
 {
 gem5::SEWorkload::setSystem(sys);
-gdb = BaseRemoteGDB::build(system);
+gdb = BaseRemoteGDB::build(
+params().remote_gdb_port, system);
 }

 loader::Arch getArch() const override { return loader::Arm64; }
diff --git a/src/arch/mips/se_workload.hh b/src/arch/mips/se_workload.hh
index d5184dd..dc6f1dd 100644
--- a/src/arch/mips/se_workload.hh
+++ b/src/arch/mips/se_workload.hh
@@ -44,7 +44,7 @@
 class SEWorkload : public gem5::SEWorkload
 {
   public:
-using Params = MipsSEWorkloadParams;
+PARAMS(MipsSEWorkload);

 SEWorkload(const Params , Addr page_shift) :
 gem5::SEWorkload(p, page_shift)
@@ -54,7 +54,8 @@
 setSystem(System *sys) override
 {
 gem5::SEWorkload::setSystem(sys);
-gdb = BaseRemoteGDB::build(system);
+gdb = BaseRemoteGDB::build(
+params().remote_gdb_port, system);
 }

 loader::Arch getArch() const override { return loader::Mips; }
diff --git a/src/arch/power/se_workload.hh b/src/arch/power/se_workload.hh
index f3c7b35..d041c45 100644
--- a/src/arch/power/se_workload.hh
+++ b/src/arch/power/se_workload.hh
@@ -45,7 +45,7 @@
 class SEWorkload : public gem5::SEWorkload
 {
   public:
-using Params = PowerSEWorkloadParams;
+PARAMS(PowerSEWorkload);
 SEWorkload(const Params , Addr page_shift) :
 gem5::SEWorkload(p, page_shift)
 {}
@@ -54,7 +54,8 @@
 setSystem(System *sys) override
 {
 gem5::SEWorkload::setSystem(sys);
-gdb = BaseRemoteGDB::build(system);
+gdb = BaseRemoteGDB::build(
+params().remote_gdb_port, system);
 }

 loader::Arch getArch() const override { return loader::Power; }
diff --git a/src/arch/riscv/bare_metal/fs_workload.hh  
b/src/arch/riscv/bare_metal/fs_workload.hh

index e10c0a0..35f4255 100644
--- a/src/arch/riscv/bare_metal/fs_workload.hh
+++ b/src/arch/riscv/bare_metal/fs_workload.hh
@@ -60,7 +60,8 @@
 setSystem(System *sys) override
 {
 Workload::setSystem(sys);
-gdb = BaseRemoteGDB::build(system);
+gdb = BaseRemoteGDB::build(
+params().remote_gdb_port, system);
 }

 loader::Arch getArch() const override { return bootloader->getArch(); }
diff --git a/src/arch/riscv/linux/fs_workload.hh  
b/src/arch/riscv/linux/fs_workload.hh

index cb29bee..1dc704d 100644
--- a/src/arch/riscv/linux/fs_workload.hh
+++ b/src/arch/riscv/linux/fs_workload.hh
@@ -51,7 +51,8 @@
 setSystem(System *sys) override
 {
 KernelWorkload::setSystem(sys);
-gdb = BaseRemoteGDB::build(system);
+gdb = BaseRemoteGDB::build(
+params().remote_gdb_port, system);
 }

 ByteOrder byteOrder() const override { return ByteOrder::little; }
diff --git a/src/arch/riscv/se_workload.hh

[gem5-dev] Build failed in Jenkins: nightly #402

2022-11-01 Thread jenkins-no-reply--- via gem5-dev

See 

Changes:

[shunhsingou] mem: implement ThreadBridge


--
[...truncated 2.41 MB...]
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--max-ticks 10
Starting Test Suite: test-lupv-example-ALL-x86_64-opt 
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 /nobackup/jenkins/workspace/nightly/tests/gem5/resources/arm 
/nobackup/jenkins/workspace/nightly
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/nobackup/jenkins/workspace/nightly
Starting Test Suite: realview-switcheroo-full-ALL-x86_64-opt 
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--test-length 5 --num-dmas 0
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Starting Test Case: ruby-gpu-random-test-perCheckin-VEGA_X86-x86_64-opt
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--test-length 500 --num-dmas 0
Starting Test Suite: ruby-gpu-random-test-nightly-VEGA_X86-x86_64-opt 
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Test: realview64-o3-dual-ruby-ARM-x86_64-opt Passed
Test: realview64-o3-dual-ruby-ARM-x86_64-opt-MatchFileRegex Passed
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Logging call to command: /nobackup/jenkins/workspace/nightly/build/ALL/gem5.opt 
-d /tmp/gem5out18m8ci8o -re --silent-redirect 
/nobackup/jenkins/workspace/nightly/configs/example/gem5_library/x86-ubuntu-run.py
Starting Test Suite: test-gem5-library-example-x86-ubuntu-run-ALL-x86_64-opt 
Starting Test Case: test-gem5-library-example-x86-ubuntu-run-ALL-x86_64-opt
Test:

[gem5-dev] [M] Change in gem5/gem5[develop]: tests: Remove long/nightly X86 Boot tests

[gem5-dev] [M] Change in gem5/gem5[develop]: tests: Remove long/nightly ARM Boot tests

[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Remove ARM compilation requirement for quick/Kokoro

[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Change the default kernel boot param from "ro" to "rw"

[gem5-dev] Re: Build failed in Jenkins: nightly #403

[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Remove unneeded build step from nightly.sh

[gem5-dev] [M] Change in gem5/gem5[develop]: tests: Remove long/nightly ARM Boot tests

[gem5-dev] [M] Change in gem5/gem5[develop]: tests: Remove tests requiring comp of novel ISAs in long

[gem5-dev] [M] Change in gem5/gem5[develop]: tests: Remove long/nightly X86 Boot tests

[gem5-dev] [L] Change in gem5/gem5[develop]: stdlib,arch-arm: Add ruby cache support to the ArmBoard

[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib,configs,tests: Rename config to arm-ubuntu-run.py

[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Refactor the ArmBoard for _connect_things move

[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Give board interface for mem ports

[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Move `_connect_things` to run as pre_instantiation

[gem5-dev] [S] Change in gem5/gem5[develop]: configs: GPUFS: use multiple event queues for >1 CPU

[gem5-dev] [M] Change in gem5/gem5[develop]: dev-amdgpu: Fix issues with PM4 queue map, fences

[gem5-dev] [S] Change in gem5/gem5[develop]: dev-amdgpu: Fix SDMA trap ring ID, context

[gem5-dev] [S] Change in gem5/gem5[develop]: dev-amdgpu: Fix interrupt handler address assignment

[gem5-dev] [S] Change in gem5/gem5[develop]: dev-amdgpu: Rework PM4 NOP packet

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove ISA::haveGICv3CpuIfc method

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Fix GICv3 List register mapping

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Fix access permissions for GICv3 cpu registers

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Setup ISA::gicv3CpuInterface on demand only

[gem5-dev] Build failed in Jenkins: nightly #403

[gem5-dev] [S] Change in gem5/gem5[develop]: util: update termios to replace nl with cr-nl

[gem5-dev] [M] Change in gem5/gem5[develop]: sim: allow specifying remote gdb port for each workload

[gem5-dev] Build failed in Jenkins: nightly #402

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