[gem5-dev] [S] Change in gem5/gem5[develop]: dev-arm: Setup TC/ISA at construction time of Gicv3CPUInterface

2022-11-04 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65291?usp=email )


Change subject: dev-arm: Setup TC/ISA at construction time of  
Gicv3CPUInterface

..

dev-arm: Setup TC/ISA at construction time of Gicv3CPUInterface

We should initialize them as soon as possible to make sure
any Gicv3CPUInterface method uses a valid reference

Change-Id: I8fffebdab9136a9027c4f61bb9413e97031e1969
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65291
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/arch/arm/isa.cc
M src/dev/arm/gic_v3.cc
M src/dev/arm/gic_v3_cpu_interface.cc
M src/dev/arm/gic_v3_cpu_interface.hh
4 files changed, 29 insertions(+), 19 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index a30fd94..3aabb56 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -530,9 +530,6 @@

 if (!gicv3CpuInterface)
 gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
-
-gicv3CpuInterface->setISA(this);
-gicv3CpuInterface->setThreadContext(tc);
 }

 void
diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc
index dde3818..e14d1f2 100644
--- a/src/dev/arm/gic_v3.cc
+++ b/src/dev/arm/gic_v3.cc
@@ -147,7 +147,7 @@

 for (int i = 0; i < threads; i++) {
 redistributors[i] = new Gicv3Redistributor(this, i);
-cpuInterfaces[i] = new Gicv3CPUInterface(this, i);
+cpuInterfaces[i] = new Gicv3CPUInterface(this, sys->threads[i]);
 }

 distRange = RangeSize(params().dist_addr,
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc  
b/src/dev/arm/gic_v3_cpu_interface.cc

index 0e1dbaa..a11dd9b 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -55,15 +55,19 @@
 const uint8_t Gicv3CPUInterface::GIC_MIN_BPR;
 const uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS;

-Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id)
+Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, ThreadContext *_tc)
 : BaseISADevice(),
   gic(gic),
   redistributor(nullptr),
   distributor(nullptr),
-  cpuId(cpu_id)
+  tc(_tc),
+  maintenanceInterrupt(gic->params().maint_int->get(tc)),
+  cpuId(tc->contextId())
 {
 hppi.prio = 0xff;
 hppi.intid = Gicv3::INTID_SPURIOUS;
+
+setISA(static_cast(tc->getIsaPtr()));
 }

 void
@@ -80,15 +84,6 @@
 hppi.prio = 0xff;
 }

-void
-Gicv3CPUInterface::setThreadContext(ThreadContext *_tc)
-{
-tc = _tc;
-maintenanceInterrupt = gic->params().maint_int->get(tc);
-fatal_if(maintenanceInterrupt->num() >=  
redistributor->irqPending.size(),

-"Invalid maintenance interrupt number\n");
-}
-
 bool
 Gicv3CPUInterface::getHCREL2FMO() const
 {
diff --git a/src/dev/arm/gic_v3_cpu_interface.hh  
b/src/dev/arm/gic_v3_cpu_interface.hh

index e860373..c39fab7 100644
--- a/src/dev/arm/gic_v3_cpu_interface.hh
+++ b/src/dev/arm/gic_v3_cpu_interface.hh
@@ -68,10 +68,10 @@
 Gicv3 * gic;
 Gicv3Redistributor * redistributor;
 Gicv3Distributor * distributor;
-uint32_t cpuId;

-ArmInterruptPin *maintenanceInterrupt;
 ThreadContext *tc;
+ArmInterruptPin *maintenanceInterrupt;
+uint32_t cpuId;

 BitUnion64(ICC_CTLR_EL1)
 Bitfield<63, 20> res0_3;
@@ -359,7 +359,7 @@
 void setBankedMiscReg(ArmISA::MiscRegIndex misc_reg, RegVal val) const;
   public:

-Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id);
+Gicv3CPUInterface(Gicv3 * gic, ThreadContext *tc);

 void init();

@@ -369,7 +369,6 @@
   public: // BaseISADevice
 RegVal readMiscReg(int misc_reg) override;
 void setMiscReg(int misc_reg, RegVal val) override;
-void setThreadContext(ThreadContext *tc) override;
 };

 } // namespace gem5

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8fffebdab9136a9027c4f61bb9413e97031e1969
Gerrit-Change-Number: 65291
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Setup ISA::gicv3CpuInterface on demand only

2022-11-04 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65174?usp=email )


Change subject: arch-arm: Setup ISA::gicv3CpuInterface on demand only
..

arch-arm: Setup ISA::gicv3CpuInterface on demand only

This is aligning with what we are already doing with the CoreTimers:
rather than setting up the interface at ISA::startup, we set it
up on the first time the GIC cpu interface is actually required
by the ISA

Change-Id: Iec29b2098ea29ca2886a69c5db8a2bc8d2f6f71e
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65174
Reviewed-by: Jason Lowe-Power 
Maintainer: Andreas Sandberg 
Reviewed-by: Andreas Sandberg 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/isa.cc
1 file changed, 30 insertions(+), 8 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 3aabb56..fd19f72 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -523,13 +523,6 @@
 return;

 selfDebug->init(tc);
-
-Gicv3 *gicv3 = dynamic_cast(system->getGIC());
-if (!gicv3)
-return;
-
-if (!gicv3CpuInterface)
-gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
 }

 void
@@ -2005,7 +1998,15 @@
 BaseISADevice &
 ISA::getGICv3CPUInterface()
 {
-panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!");
+if (gicv3CpuInterface)
+return *gicv3CpuInterface.get();
+
+assert(system);
+Gicv3 *gicv3 = dynamic_cast(system->getGIC());
+panic_if(!gicv3, "The system does not have a GICv3 irq controller\n");
+
+gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
+
 return *gicv3CpuInterface.get();
 }


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iec29b2098ea29ca2886a69c5db8a2bc8d2f6f71e
Gerrit-Change-Number: 65174
Gerrit-PatchSet: 7
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Update FS field of mstatus register where approriate.

2022-11-04 Thread Hoa Nguyen (Gerrit) via gem5-dev 
Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65272?usp=email )


 (

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: arch-riscv: Update FS field of mstatus register where  
approriate.

..

arch-riscv: Update FS field of mstatus register where approriate.

Per RISC-V ISA Manual, vol II, section 3.1.6.6, page 25, the
FS field of the mstatus register encodes the status of the floating
point unit, including the floating point registers. Per page 27,
microarchitecture can choose to set the FS field to Dirty even if
the floating point unit has not been modified.

Per section 3.1.6, page 20, the FS field is located at bits 14..13
of the mstatus register.

Per section 3.1.6.6, page 27, the FS field is used for saving
context.

Upon a system call, the Linux kernel relies on mstatus for
choosing registers to save for switching to kernel code.
In particular, if the SD bit (updating this bit is also a bug
in gem5 and will be explained in the next commit) is not set
properly due to the FS field being incorrect, the process of saving
the context and restoring the context result in the floating
point registers being zeroed out. I.e., upon the saving context
function call, the floating point registers are not saved, while
in restore context function call, the floating point registers
are overwritten with zero bits.

Previously, in gem5 RISC-V ISA, the FS field is not updated upon
floating point instruction execution. This caused issue on context
saving described above.

This change conservatively updates the FS field to Dirty on
the execution of any floating point instruction.

Change-Id: I8b3b4922e8da483cff3a2210ee80c163cace182a
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65272
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/isa/formats/fp.isa
1 file changed, 47 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/riscv/isa/formats/fp.isa  
b/src/arch/riscv/isa/formats/fp.isa

index 65e81cd..d0bd245 100644
--- a/src/arch/riscv/isa/formats/fp.isa
+++ b/src/arch/riscv/isa/formats/fp.isa
@@ -40,6 +40,9 @@
 if (status.fs == FPUStatus::OFF)
 return std::make_shared("FPU is off",  
machInst);


+status.fs = FPUStatus::DIRTY;
+xc->setMiscReg(MISCREG_STATUS, status);
+
 %(op_decl)s;
 %(op_rd)s;


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8b3b4922e8da483cff3a2210ee80c163cace182a
Gerrit-Change-Number: 65272
Gerrit-PatchSet: 4
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Add VS field to the STATUS CSR

2022-11-04 Thread Hoa Nguyen (Gerrit) via gem5-dev 
Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65274?usp=email )


Change subject: arch-riscv: Add VS field to the STATUS CSR
..

arch-riscv: Add VS field to the STATUS CSR

Per RISC-V ISA Manual, vol II, section 3.1.6, page 20, the VS field
is located at bits 10..9 of mstatus. Per section 4.1.1, page 63,
the VS field is located at the same bits of sstatus.

Change-Id: Ifda1c551a23ed892fb8ac7ef31fa98f0b6db
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65274
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/regs/misc.hh
1 file changed, 30 insertions(+), 10 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved




diff --git a/src/arch/riscv/regs/misc.hh b/src/arch/riscv/regs/misc.hh
index cb8c907..5f07447 100644
--- a/src/arch/riscv/regs/misc.hh
+++ b/src/arch/riscv/regs/misc.hh
@@ -562,6 +562,7 @@
 Bitfield<16, 15> xs;
 Bitfield<14, 13> fs;
 Bitfield<12, 11> mpp;
+Bitfield<10, 9> vs;
 Bitfield<8> spp;
 Bitfield<7> mpie;
 Bitfield<5> spie;
@@ -612,6 +613,7 @@
 const RegVal STATUS_XS_MASK = 3ULL << 15;
 const RegVal STATUS_FS_MASK = 3ULL << FS_OFFSET;
 const RegVal STATUS_MPP_MASK = 3ULL << 11;
+const RegVal STATUS_VS_MASK = 3ULL << 9;
 const RegVal STATUS_SPP_MASK = 1ULL << 8;
 const RegVal STATUS_MPIE_MASK = 1ULL << 7;
 const RegVal STATUS_SPIE_MASK = 1ULL << 5;
@@ -624,21 +626,21 @@
 STATUS_TW_MASK | STATUS_TVM_MASK |
 STATUS_MXR_MASK | STATUS_SUM_MASK |
 STATUS_MPRV_MASK | STATUS_XS_MASK |
-STATUS_FS_MASK | STATUS_MPP_MASK |
-STATUS_SPP_MASK | STATUS_MPIE_MASK |
-STATUS_SPIE_MASK | STATUS_UPIE_MASK |
-STATUS_MIE_MASK | STATUS_SIE_MASK |
-STATUS_UIE_MASK;
+STATUS_FS_MASK | STATUS_VS_MASK |
+STATUS_MPP_MASK | STATUS_SPP_MASK |
+STATUS_MPIE_MASK | STATUS_SPIE_MASK |
+STATUS_UPIE_MASK | STATUS_MIE_MASK |
+STATUS_SIE_MASK | STATUS_UIE_MASK;
 const RegVal SSTATUS_MASK = STATUS_SD_MASK | STATUS_UXL_MASK |
 STATUS_MXR_MASK | STATUS_SUM_MASK |
 STATUS_XS_MASK | STATUS_FS_MASK |
-STATUS_SPP_MASK | STATUS_SPIE_MASK |
-STATUS_UPIE_MASK | STATUS_SIE_MASK |
-STATUS_UIE_MASK;
+STATUS_VS_MASK | STATUS_SPP_MASK |
+STATUS_SPIE_MASK | STATUS_UPIE_MASK |
+STATUS_SIE_MASK | STATUS_UIE_MASK;
 const RegVal USTATUS_MASK = STATUS_SD_MASK | STATUS_MXR_MASK |
 STATUS_SUM_MASK | STATUS_XS_MASK |
-STATUS_FS_MASK | STATUS_UPIE_MASK |
-STATUS_UIE_MASK;
+STATUS_FS_MASK | STATUS_VS_MASK |
+STATUS_UPIE_MASK | STATUS_UIE_MASK;

 const RegVal MEI_MASK = 1ULL << 11;
 const RegVal SEI_MASK = 1ULL << 9;

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Gerrit-Change-Number: 65274
Gerrit-PatchSet: 2
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Change the default kernel boot param from "ro" to "rw"

2022-11-04 Thread Hoa Nguyen (Gerrit) via gem5-dev 
Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65194?usp=email )


Change subject: stdlib: Change the default kernel boot param from "ro"  
to "rw"

..

stdlib: Change the default kernel boot param from "ro" to "rw"

Running workloads likely causes some content to be written to
the disk image, e.g., `m5 readfile`. However, on riscv boards,
the default kernel param specifies the disk image to be read-only.

This change changes this param so that the disk image is
read-write by default.

Change-Id: I414e483ad11d747f34433560e32a8f91a425ce7e
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65194
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/python/gem5/components/boards/experimental/lupv_board.py
M src/python/gem5/components/boards/riscv_board.py
M src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
3 files changed, 24 insertions(+), 3 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved




diff --git a/src/python/gem5/components/boards/experimental/lupv_board.py  
b/src/python/gem5/components/boards/experimental/lupv_board.py

index ba65ccb..5624712 100644
--- a/src/python/gem5/components/boards/experimental/lupv_board.py
+++ b/src/python/gem5/components/boards/experimental/lupv_board.py
@@ -536,7 +536,7 @@

 @overrides(KernelDiskWorkload)
 def get_default_kernel_args(self) -> List[str]:
-return ["console=ttyLIO0", "root={root_value}", "ro"]
+return ["console=ttyLIO0", "root={root_value}", "rw"]

 @overrides(KernelDiskWorkload)
 def get_disk_device(self) -> str:
diff --git a/src/python/gem5/components/boards/riscv_board.py  
b/src/python/gem5/components/boards/riscv_board.py

index d83b85e..15ec57a 100644
--- a/src/python/gem5/components/boards/riscv_board.py
+++ b/src/python/gem5/components/boards/riscv_board.py
@@ -494,4 +494,4 @@

 @overrides(KernelDiskWorkload)
 def get_default_kernel_args(self) -> List[str]:
-return ["console=ttyS0", "root={root_value}", "ro"]
+return ["console=ttyS0", "root={root_value}", "rw"]
diff --git a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py  
b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py

index 469010c..4148c0a 100644
--- a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
+++ b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
@@ -566,7 +566,7 @@

 @overrides(KernelDiskWorkload)
 def get_default_kernel_args(self) -> List[str]:
-return ["console=ttyS0", "root={root_value}", "ro"]
+return ["console=ttyS0", "root={root_value}", "rw"]

 @overrides(KernelDiskWorkload)
 def set_kernel_disk_workload(

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Gerrit-Change-Id: I414e483ad11d747f34433560e32a8f91a425ce7e
Gerrit-Change-Number: 65194
Gerrit-PatchSet: 2
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Fixing erroneous typing in Simulator __init__

2022-11-04 Thread Bobby Bruce (Gerrit) via gem5-dev 
Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64773?usp=email )


Change subject: stdlib: Fixing erroneous typing in Simulator __init__
..

stdlib: Fixing erroneous typing in Simulator __init__

The key in the `on_exit_event` dictionary can only be an ExitEvent. The
typing information here suggested a string could be passed. This is not
the case. This patch fixes the issue.

Change-Id: Iaa4b66417c15e31f6aafe9e550a7552461a15be1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64773
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
---
M src/python/gem5/simulate/simulator.py
1 file changed, 18 insertions(+), 1 deletion(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/simulate/simulator.py  
b/src/python/gem5/simulate/simulator.py

index b32e54a..1d0d3ec 100644
--- a/src/python/gem5/simulate/simulator.py
+++ b/src/python/gem5/simulate/simulator.py
@@ -87,7 +87,7 @@
 board: AbstractBoard,
 full_system: Optional[bool] = None,
 on_exit_event: Optional[
-Dict[Union[str, ExitEvent], Generator[Optional[bool], None,  
None]]

+Dict[ExitEvent, Generator[Optional[bool], None, None]]
 ] = None,
 expected_execution_order: Optional[List[ExitEvent]] = None,
 checkpoint_path: Optional[Path] = None,

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Gerrit-Change-Id: Iaa4b66417c15e31f6aafe9e550a7552461a15be1
Gerrit-Change-Number: 64773
Gerrit-PatchSet: 14
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Melissa Jost 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Update AbstractCore's 'set_inst_stop_any_thread'

2022-11-04 Thread Bobby Bruce (Gerrit) via gem5-dev 
Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64833?usp=email )


Change subject: stdlib: Update AbstractCore's 'set_inst_stop_any_thread'
..

stdlib: Update AbstractCore's 'set_inst_stop_any_thread'

This patch:
- Makes this function private.
- Updates the function's documentation.
- Changes the 'init' parameter to 'board_initialized'.

It doesn't make much sense for this function to be exposed directly to
the user as it requires knowing whether the board is initialized or not.

In addition to this I believe it makes more sense for the 'init' logic
to be flipped and renamed "board_initialized' so that this value is True
if the board has been initialized.

The documentation for this function has been updated.

Change-Id: I016c65bde88357111d3e648d7aa99aeb6e31f410
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64833
Maintainer: Bobby Bruce 
Reviewed-by: Bobby Bruce 
Tested-by: kokoro 
---
M configs/example/gem5_library/checkpoints/simpoints-se-restore.py
M src/python/gem5/components/processors/abstract_core.py
M src/python/gem5/components/processors/base_cpu_core.py
M src/python/gem5/simulate/simulator.py
4 files changed, 48 insertions(+), 21 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git  
a/configs/example/gem5_library/checkpoints/simpoints-se-restore.py  
b/configs/example/gem5_library/checkpoints/simpoints-se-restore.py

index b529672..f8f48d0 100644
--- a/configs/example/gem5_library/checkpoints/simpoints-se-restore.py
+++ b/configs/example/gem5_library/checkpoints/simpoints-se-restore.py
@@ -132,5 +132,5 @@
 # is greater than 0.
 # In here, it schedules an exit event for the first SimPoint's warmup
 # instructions
-simulator.schedule_max_insts(board.get_simpoint().get_warmup_list()[0],  
True)

+simulator.schedule_max_insts(board.get_simpoint().get_warmup_list()[0])
 simulator.run()
diff --git a/src/python/gem5/components/processors/abstract_core.py  
b/src/python/gem5/components/processors/abstract_core.py

index ea2875e..58296bc 100644
--- a/src/python/gem5/components/processors/abstract_core.py
+++ b/src/python/gem5/components/processors/abstract_core.py
@@ -140,15 +140,18 @@
 raise NotImplementedError("This core type does not support  
simpoints")


 @abstractmethod
-def set_inst_stop_any_thread(self, inst: int, init: bool) -> None:
+def _set_inst_stop_any_thread(
+self, inst: int, board_initialized: bool
+) -> None:
 """Schedule an exit event when any thread in this core reaches the
-given number of instructions.
+given number of instructions. This is called through the simulator
+module and should not be called directly.

 This is used to raise MAX_INSTS exit event in the gem5 standard  
library


 :param inst: a number of instructions
-:param init: if it is True, the exit event will be scheduled at the
-init stage of the core, else, it will be scheduled during the
-simulation
+:param board_initialized: True if the board has already been
+initialized, otherwise False. This parameter is necessary as the
+instruction stop is setup differently dependent on this.
 """
 raise NotImplementedError("This core type does not support  
MAX_INSTS")
diff --git a/src/python/gem5/components/processors/base_cpu_core.py  
b/src/python/gem5/components/processors/base_cpu_core.py

index 535a800..631fd0a 100644
--- a/src/python/gem5/components/processors/base_cpu_core.py
+++ b/src/python/gem5/components/processors/base_cpu_core.py
@@ -162,8 +162,10 @@
 self.core.simpoint_start_insts = sorted(set(inst_starts))

 @overrides(AbstractCore)
-def set_inst_stop_any_thread(self, inst: int, init: bool) -> None:
-if init:
-self.core.max_insts_any_thread = inst
-else:
+def _set_inst_stop_any_thread(
+self, inst: int, board_initialized: bool
+) -> None:
+if board_initialized:
 self.core.scheduleInstStopAnyThread(inst)
+else:
+self.core.max_insts_any_thread = inst
diff --git a/src/python/gem5/simulate/simulator.py  
b/src/python/gem5/simulate/simulator.py

index d7e2141..0d2917d 100644
--- a/src/python/gem5/simulate/simulator.py
+++ b/src/python/gem5/simulate/simulator.py
@@ -251,20 +251,15 @@
 simpoint_start_insts, self._instantiated
 )

-def schedule_max_insts(
-self, inst: int, schedule_at_init: bool = False
-) -> None:
+def schedule_max_insts(self, inst: int) -> None:
 """
-Schedule a MAX_INSTS exit event when any thread in the current core
-reaches the given number of instructions
+Schedule a MAX_INSTS exit event when any thread in any core  
reaches the

+given number of

[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Update AbstractCore `set_simpoint` func

2022-11-04 Thread Bobby Bruce (Gerrit) via gem5-dev 
Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64832?usp=email )


Change subject: stdlib: Update AbstractCore `set_simpoint` func
..

stdlib: Update AbstractCore `set_simpoint` func

This change:
- Makes this function private.
- Adds better documentation describing the usage.
- Changes the 'init' param to 'board_initialized'

This function really doesn't make much sense to set directly by an
stdlib user. It requires knowing whether or not the the board has been
initialized which is an annoying detail and will cause error if set
incorrectly.

The logic of the `init` parameter has been flipped to be
`board_initialized`. This makes it clearer what the parameter is
doing and what it's for.

The documentation for this function has been updated to make it clearer
on how the `board_initialized` parameter should be used correctly.

Change-Id: I567a48df06e6327b38673a2c510065d4334657e2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64832
Reviewed-by: Melissa Jost 
Reviewed-by: Jason Lowe-Power 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
M src/python/gem5/components/boards/se_binary_workload.py
M src/python/gem5/components/processors/abstract_core.py
M src/python/gem5/components/processors/base_cpu_core.py
M src/python/gem5/simulate/simulator.py
4 files changed, 49 insertions(+), 17 deletions(-)

Approvals:
  Melissa Jost: Looks good to me, approved
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved




diff --git a/src/python/gem5/components/boards/se_binary_workload.py  
b/src/python/gem5/components/boards/se_binary_workload.py

index b9ecc7f..8ec112e 100644
--- a/src/python/gem5/components/boards/se_binary_workload.py
+++ b/src/python/gem5/components/boards/se_binary_workload.py
@@ -149,9 +149,9 @@

 if self.get_processor().get_num_cores() > 1:
 warn("SimPoints only works with one core")
-self.get_processor().get_cores()[0].set_simpoint(
+self.get_processor().get_cores()[0]._set_simpoint(
 inst_starts=self._simpoint_object.get_simpoint_start_insts(),
-init=True,
+board_initialized=False,
 )

 # Call set_se_binary_workload after SimPoint setup is complete
diff --git a/src/python/gem5/components/processors/abstract_core.py  
b/src/python/gem5/components/processors/abstract_core.py

index 2f4cb79..ea2875e 100644
--- a/src/python/gem5/components/processors/abstract_core.py
+++ b/src/python/gem5/components/processors/abstract_core.py
@@ -122,17 +122,20 @@
 raise NotImplementedError

 @abstractmethod
-def set_simpoint(self, inst_starts: List[int], init: bool) -> None:
+def _set_simpoint(
+self, inst_starts: List[int], board_initialized: bool
+) -> None:
 """Schedule simpoint exit events for the core.

 This is used to raise SIMPOINT_BEGIN exit events in the gem5  
standard
-library. Duplicate instruction counts in the inst_starts list will  
not
+library. This is called through the set_workload functions and  
should
+not be called directly. Duplicate instruction counts in the  
inst_starts list will not

 be scheduled.

 :param inst_starts: a list of SimPoints starting instructions
-:param init: if it is True, the starting instructions will be  
scheduled
-at the init stage of the core, else, the starting insructions will  
be

-scheduled during the simulation
+:param board_initialized: True if the board has already been
+initialized, otherwise False. This parameter is necessary as  
simpoints

+are setup differently dependent on this.
 """
 raise NotImplementedError("This core type does not support  
simpoints")


diff --git a/src/python/gem5/components/processors/base_cpu_core.py  
b/src/python/gem5/components/processors/base_cpu_core.py

index db9a1a2..535a800 100644
--- a/src/python/gem5/components/processors/base_cpu_core.py
+++ b/src/python/gem5/components/processors/base_cpu_core.py
@@ -153,11 +153,13 @@
 return self.core.mmu

 @overrides(AbstractCore)
-def set_simpoint(self, inst_starts: List[int], init: bool) -> None:
-if init:
-self.core.simpoint_start_insts = sorted(set(inst_starts))
-else:
+def _set_simpoint(
+self, inst_starts: List[int], board_initialized: bool
+) -> None:
+if board_initialized:
 self.core.scheduleSimpointsInstStop(sorted(set(inst_starts)))
+else:
+self.core.simpoint_start_insts = sorted(set(inst_starts))

 @overrides(AbstractCore)
 def set_inst_stop_any_thread(self, inst: int, init: bool) -> None:
diff --git a/src/python/gem5/simulate/simulator.py  
b/src/python/gem5/simulate/simulator.py

index 8be915e..d7e2141 100644
---

[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Fix typos and remove unneeded import in Simulator

2022-11-04 Thread Bobby Bruce (Gerrit) via gem5-dev 
Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/62931?usp=email )


Change subject: stdlib: Fix typos and remove unneeded import in Simulator
..

stdlib: Fix typos and remove unneeded import in Simulator

Change-Id: I6faa63959d09444b8e931e14846fb1af98866ade
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62931
Tested-by: kokoro 
Maintainer: Bobby Bruce 
Reviewed-by: Bobby Bruce 
---
M src/python/gem5/simulate/simulator.py
1 file changed, 15 insertions(+), 3 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/simulate/simulator.py  
b/src/python/gem5/simulate/simulator.py

index 0d2917d..b32e54a 100644
--- a/src/python/gem5/simulate/simulator.py
+++ b/src/python/gem5/simulate/simulator.py
@@ -47,7 +47,6 @@
 from .exit_event import ExitEvent
 from ..components.boards.abstract_board import AbstractBoard
 from ..components.processors.switchable_processor import  
SwitchableProcessor

-from ..components.processors.cpu_types import CPUTypes


 class Simulator:
@@ -284,7 +283,7 @@

 if not self._instantiated:
 raise Exception(
-"Cannot obtain simulation statistics prior to  
inialization."
+"Cannot obtain simulation statistics prior to  
initialization."

 )

 return m5.stats.gem5stats.get_simstat(self._root)
@@ -440,7 +439,7 @@
 :param max_ticks: The maximum number of ticks to execute per  
simulation

 run. If this max_ticks value is met, a MAX_TICK exit event is
 received, if another simulation exit event is met the tick count is
-reset. This is the **maximum number of ticks per simululation  
run**.

+reset. This is the **maximum number of ticks per simulation run**.
 """

 # Check to ensure no banned module has been imported.

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/62931?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6faa63959d09444b8e931e14846fb1af98866ade
Gerrit-Change-Number: 62931
Gerrit-PatchSet: 15
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Melissa Jost 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] Build failed in Jenkins: nightly #409

2022-11-04 Thread jenkins-no-reply--- via gem5-dev 
See 

Changes:

[Bobby R. Bruce] tests, resources: CVE-2007-4559 Patch

[Bobby R. Bruce] tests,stdlib: Add a test for JsonSerializable

[Bobby R. Bruce] stdlib: Rename JsonSerializable to SerializableStat

[Bobby R. Bruce] misc: Update black to process src/python/m5/ext/pystats

[Bobby R. Bruce] stdlib: Add __repr__ to pystats

[Bobby R. Bruce] stdlib: Add 'get_simstats' function to simulator

[Bobby R. Bruce] python: Add AbstractStat for PyStats

[Bobby R. Bruce] python: Move find from group to AbstractStat


--
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generated/exec-g.cc.inc, generated/exec-ns.cc.inc, generated/decoder.cc, 
generated/inst-constrs.cc, generated/generic_cpu_exec.cc
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[gem5-dev] Build failed in Jenkins: nightly #408

2022-11-04 Thread jenkins-no-reply--- via gem5-dev 
See 

Changes:


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 [SHCC] NULL/ext/softfloat/s_propagateNaNF16UI.c -> .os
 [SHCC] NULL/ext/softfloat/s_propagateNaNF32UI.c -> .os
 [SHCC] NULL/ext/softfloat/s_propagateNaNF64UI.c -> .os
 [SHCC] NULL/ext/softfloat/s_remStepMBy32.c -> .os
 [SHCC] NULL/ext/softfloat/s_roundMToI64.c

[gem5-dev] [S] Change in gem5/gem5[develop]: dev-arm: Setup TC/ISA at construction time of Gicv3CPUInterface

2022-11-04 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65291?usp=email )



Change subject: dev-arm: Setup TC/ISA at construction time of  
Gicv3CPUInterface

..

dev-arm: Setup TC/ISA at construction time of Gicv3CPUInterface

We should initialize them as soon as possible to make sure
any Gicv3CPUInterface method uses a valid reference

Change-Id: I8fffebdab9136a9027c4f61bb9413e97031e1969
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/isa.cc
M src/dev/arm/gic_v3.cc
M src/dev/arm/gic_v3_cpu_interface.cc
M src/dev/arm/gic_v3_cpu_interface.hh
4 files changed, 23 insertions(+), 19 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index a30fd94..3aabb56 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -530,9 +530,6 @@

 if (!gicv3CpuInterface)
 gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
-
-gicv3CpuInterface->setISA(this);
-gicv3CpuInterface->setThreadContext(tc);
 }

 void
diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc
index dde3818..e14d1f2 100644
--- a/src/dev/arm/gic_v3.cc
+++ b/src/dev/arm/gic_v3.cc
@@ -147,7 +147,7 @@

 for (int i = 0; i < threads; i++) {
 redistributors[i] = new Gicv3Redistributor(this, i);
-cpuInterfaces[i] = new Gicv3CPUInterface(this, i);
+cpuInterfaces[i] = new Gicv3CPUInterface(this, sys->threads[i]);
 }

 distRange = RangeSize(params().dist_addr,
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc  
b/src/dev/arm/gic_v3_cpu_interface.cc

index 0e1dbaa..a11dd9b 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -55,15 +55,19 @@
 const uint8_t Gicv3CPUInterface::GIC_MIN_BPR;
 const uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS;

-Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id)
+Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, ThreadContext *_tc)
 : BaseISADevice(),
   gic(gic),
   redistributor(nullptr),
   distributor(nullptr),
-  cpuId(cpu_id)
+  tc(_tc),
+  maintenanceInterrupt(gic->params().maint_int->get(tc)),
+  cpuId(tc->contextId())
 {
 hppi.prio = 0xff;
 hppi.intid = Gicv3::INTID_SPURIOUS;
+
+setISA(static_cast(tc->getIsaPtr()));
 }

 void
@@ -80,15 +84,6 @@
 hppi.prio = 0xff;
 }

-void
-Gicv3CPUInterface::setThreadContext(ThreadContext *_tc)
-{
-tc = _tc;
-maintenanceInterrupt = gic->params().maint_int->get(tc);
-fatal_if(maintenanceInterrupt->num() >=  
redistributor->irqPending.size(),

-"Invalid maintenance interrupt number\n");
-}
-
 bool
 Gicv3CPUInterface::getHCREL2FMO() const
 {
diff --git a/src/dev/arm/gic_v3_cpu_interface.hh  
b/src/dev/arm/gic_v3_cpu_interface.hh

index e860373..c39fab7 100644
--- a/src/dev/arm/gic_v3_cpu_interface.hh
+++ b/src/dev/arm/gic_v3_cpu_interface.hh
@@ -68,10 +68,10 @@
 Gicv3 * gic;
 Gicv3Redistributor * redistributor;
 Gicv3Distributor * distributor;
-uint32_t cpuId;

-ArmInterruptPin *maintenanceInterrupt;
 ThreadContext *tc;
+ArmInterruptPin *maintenanceInterrupt;
+uint32_t cpuId;

 BitUnion64(ICC_CTLR_EL1)
 Bitfield<63, 20> res0_3;
@@ -359,7 +359,7 @@
 void setBankedMiscReg(ArmISA::MiscRegIndex misc_reg, RegVal val) const;
   public:

-Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id);
+Gicv3CPUInterface(Gicv3 * gic, ThreadContext *tc);

 void init();

@@ -369,7 +369,6 @@
   public: // BaseISADevice
 RegVal readMiscReg(int misc_reg) override;
 void setMiscReg(int misc_reg, RegVal val) override;
-void setThreadContext(ThreadContext *tc) override;
 };

 } // namespace gem5

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8fffebdab9136a9027c4f61bb9413e97031e1969
Gerrit-Change-Number: 65291
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
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