[gem5-dev] Change in gem5/gem5[develop]: base: Add XOR and modulo operator to ChannelAddr

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39235 )


Change subject: base: Add XOR and modulo operator to ChannelAddr
..

base: Add XOR and modulo operator to ChannelAddr

Channel address class did not offer bitwise
XOR and modulo operation. These two functions
where now added to the ChannelAddr class.

Change-Id: I02a5e49e9700cc5283415c921a25989a130e5d07
Reviewed-by: Andreas Sandberg 
Reviewed-by: Ciro Santilli 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39235
Reviewed-by: Daniel Carvalho 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Bobby R. Bruce 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/base/channel_addr.hh
1 file changed, 9 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Daniel Carvalho: Looks good to me, but someone else must approve
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/channel_addr.hh b/src/base/channel_addr.hh
index 2cfe380..55d227b 100644
--- a/src/base/channel_addr.hh
+++ b/src/base/channel_addr.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019 ARM Limited
+ * Copyright (c) 2019, 2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -93,6 +93,14 @@
 return ChannelAddr(a << b);
 }

+constexpr ChannelAddr operator^(const int b) const {
+return ChannelAddr(a ^ b);
+}
+
+constexpr ChannelAddr operator%(const int b) const {
+return ChannelAddr(a % b);
+}
+
 constexpr ChannelAddr operator*(const Type ) const {
 return ChannelAddr(a * b);
 }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I02a5e49e9700cc5283415c921a25989a130e5d07
Gerrit-Change-Number: 39235
Gerrit-PatchSet: 2
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim,base: make checkpointMapIn warn if an unknown key is found

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37575 )


Change subject: sim,base: make checkpointMapIn warn if an unknown key is  
found

..

sim,base: make checkpointMapIn warn if an unknown key is found

The warning happens when a key is present in the checkpoint but not in the
values that gem5 source code knows about.

To do this, we must expose iteration over IniFile section keys. To not
have to make those classes public, a visitor method is implemented.

Change-Id: I23340a953f3e604642b97690a7328b10fdd740a8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37575
Reviewed-by: Daniel Carvalho 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/base/inifile.cc
M src/base/inifile.hh
M src/sim/serialize.cc
M src/sim/serialize.hh
4 files changed, 54 insertions(+), 1 deletion(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/inifile.cc b/src/base/inifile.cc
index 1fbebb4..b2eeafc 100644
--- a/src/base/inifile.cc
+++ b/src/base/inifile.cc
@@ -345,3 +345,25 @@
 i->second->dump(i->first);
 }
 }
+
+IniFile::Section::EntryTable::const_iterator
+IniFile::Section::begin() const
+{
+return table.begin();
+}
+
+IniFile::Section::EntryTable::const_iterator
+IniFile::Section::end() const
+{
+return table.end();
+}
+
+void
+IniFile::visitSection(const std::string ,
+IniFile::VisitSectionCallback cb)
+{
+const auto& section = *table.at(sectionName);
+for (const auto& pair : section) {
+cb(pair.first, pair.second->getValue());
+}
+}
diff --git a/src/base/inifile.hh b/src/base/inifile.hh
index 095d132..ae6dc45 100644
--- a/src/base/inifile.hh
+++ b/src/base/inifile.hh
@@ -30,6 +30,7 @@
 #define __INIFILE_HH__

 #include 
+#include 
 #include 
 #include 
 #include 
@@ -132,6 +133,9 @@

 /// Print the contents of this section to cout (for debugging).
 void dump(const std::string );
+
+EntryTable::const_iterator begin() const;
+EntryTable::const_iterator end() const;
 };

 /// SectionTable type.  Map of strings to Section object pointers.
@@ -203,6 +207,13 @@

 /// Dump contents to cout.  For debugging.
 void dump();
+
+/// Visitor callback that receives key/value pairs.
+using VisitSectionCallback = std::function;
+
+/// Iterate over key/value pairs of the given section.
+void visitSection(const std::string , VisitSectionCallback  
cb);

 };

 #endif // __INIFILE_HH__
diff --git a/src/sim/serialize.cc b/src/sim/serialize.cc
index e502d9a..a563332 100644
--- a/src/sim/serialize.cc
+++ b/src/sim/serialize.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2015, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -338,6 +338,13 @@
 }

 void
+CheckpointIn::visitSection(const std::string ,
+IniFile::VisitSectionCallback cb)
+{
+db->visitSection(section, cb);
+}
+
+void
 objParamIn(CheckpointIn , const string , SimObject * )
 {
 const string (Serializable::currentSection());
diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh
index 9e25d09..80fac66 100644
--- a/src/sim/serialize.hh
+++ b/src/sim/serialize.hh
@@ -55,6 +55,7 @@
 #include 
 #include 

+#include "base/inifile.hh"
 #include "base/logging.hh"
 #include "sim/serialize_handlers.hh"

@@ -94,6 +95,8 @@

 bool entryExists(const std::string , const std::string );
 bool sectionExists(const std::string );
+void visitSection(const std::string ,
+IniFile::VisitSectionCallback cb);
 /** @}*/ //end of api_checkout group

 // The following static functions have to do with checkpoint
@@ -555,6 +558,16 @@
 param[name_to_index[key]] = value;
 }
 }
+cp.visitSection(
+Serializable::currentSection(),
+[name_to_index](const std::string& key, const std::string& val)
+{
+if (!name_to_index.count(key)) {
+warn("unknown entry found in checkpoint: %s %s %s\n",
+Serializable::currentSection(), key, val);
+}
+}
+);
 }

 //

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I23340a953f3e604642b97690a7328b10fdd740a8
Gerrit-Change-Number: 37575
Gerrit-PatchSet: 10
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 

[gem5-dev] Change in gem5/gem5[develop]: base: Add XOR and modulo operator to ChannelAddr

[Ciro Santilli (Gerrit) via gem5-dev]

Attention is currently required from: Andreas Sandberg.
Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/39235

to review the following change.


Change subject: base: Add XOR and modulo operator to ChannelAddr
..

base: Add XOR and modulo operator to ChannelAddr

Channel address class did not offer bitwise
XOR and modulo operation. These two functions
where now added to the ChannelAddr class.

Change-Id: I02a5e49e9700cc5283415c921a25989a130e5d07
Reviewed-by: Andreas Sandberg 
Reviewed-by: Ciro Santilli 
---
M src/base/channel_addr.hh
1 file changed, 9 insertions(+), 1 deletion(-)



diff --git a/src/base/channel_addr.hh b/src/base/channel_addr.hh
index 2cfe380..55d227b 100644
--- a/src/base/channel_addr.hh
+++ b/src/base/channel_addr.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019 ARM Limited
+ * Copyright (c) 2019, 2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -93,6 +93,14 @@
 return ChannelAddr(a << b);
 }

+constexpr ChannelAddr operator^(const int b) const {
+return ChannelAddr(a ^ b);
+}
+
+constexpr ChannelAddr operator%(const int b) const {
+return ChannelAddr(a % b);
+}
+
 constexpr ChannelAddr operator*(const Type ) const {
 return ChannelAddr(a * b);
 }

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I02a5e49e9700cc5283415c921a25989a130e5d07
Gerrit-Change-Number: 39235
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Attention: Andreas Sandberg 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: inform bootloader of kernel position with a register

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35076 )


Change subject: arch-arm: inform bootloader of kernel position with a  
register

..

arch-arm: inform bootloader of kernel position with a register

Before the commit, the bootloader had a hardcoded entry point that it
would jump to.

However, the Linux kernel arm64 v5.8 forced us to change the kernel
entry point because the required memory alignment has changed at:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
commit/?h=v5.8=cfa7ede20f133cc81cef01dc3a516dda3a9721ee

Therefore the only way to have a single bootloader that boots both
pre-v5.8 and post-v5.8 kernels is to pass that information from gem5
to the bootloader, which we do in this patch via registers.

This approach was already used by the 32-bit bootloader, which passed
that value via r3, and we try to use the same register x3 in 64-bit.

Since we are now passing this information, the this patch also removes
the hardcoding of DTB and cpu-release-addr, and also passes those
values via registers.

We store the cpu-release-addr in x5 as that value appears to have a
function similar to flags_addr, which is used only in 32-bit arm and
gets stored in r5.

This commit renames atags_addr to dtb_addr, since both are mutually
exclusive, and serve a similar purpose, DTB being the newer recommended
approach.

Similarly, flags_addr is renamed to cpu_release_addr, and it is moved
from ArmSystem into ArmFsWorkload, since it is not an intrinsic system
property, and should be together with dtb_addr instead.

Before this commit, flags_addr was being set from FSConfig.py and
configs/example/arm/devices.py to self.realview.realview_io.pio_addr
+ 0x30. This commit moves that logic into RealView.py instead, and
sets the flags address 8 bytes before the start of the DTB address.

JIRA: https://gem5.atlassian.net/browse/GEM5-787
Change-Id: If70bea9690be04b84e6040e256a9b03e46710e10
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35076
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M configs/common/FSConfig.py
M configs/example/arm/devices.py
M configs/example/arm/workloads.py
M src/arch/arm/ArmFsWorkload.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/freebsd/fs_workload.cc
M src/arch/arm/fs_workload.cc
M src/arch/arm/linux/fs_workload.cc
M src/dev/arm/RealView.py
M system/arm/bootloader/arm64/boot.S
M system/arm/bootloader/arm64/makefile
11 files changed, 73 insertions(+), 45 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 710ee4d..6fd39a5 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -250,7 +250,7 @@
 if bare_metal:
 # EOT character on UART will end the simulation
 self.realview.uart[0].end_on_eot = True
-self.workload = ArmFsWorkload(atags_addr=0)
+self.workload = ArmFsWorkload(dtb_addr=0)
 else:
 workload = ArmFsLinux()

@@ -269,8 +269,6 @@
 if hasattr(self.realview.gic, 'cpu_addr'):
 self.gic_cpu_addr = self.realview.gic.cpu_addr

-self.flags_addr = self.realview.realview_io.pio_addr + 0x30
-
 # This check is for users who have previously put 'android' in
 # the disk image filename to tell the config scripts to
 # prepare the kernel with android-specific boot options. That
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index 971782d..e3cee1e 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -308,7 +308,6 @@

 if hasattr(self.realview.gic, 'cpu_addr'):
 self.gic_cpu_addr = self.realview.gic.cpu_addr
-self.flags_addr = self.realview.realview_io.pio_addr + 0x30

 self.membus = MemBus()

diff --git a/configs/example/arm/workloads.py  
b/configs/example/arm/workloads.py

index 6952a4a..ce48cdd 100644
--- a/configs/example/arm/workloads.py
+++ b/configs/example/arm/workloads.py
@@ -47,7 +47,7 @@

 class ArmBaremetal(ArmFsWorkload):
 """ Baremetal workload """
-atags_addr = 0
+dtb_addr = 0

 def __init__(self, obj, system, **kwargs):
 super(ArmBaremetal, self).__init__(**kwargs)
@@ -72,7 +72,7 @@
 https://github.com/ARM-software/arm-trusted-firmware

 """
-atags_addr = 0
+dtb_addr = 0

 def __init__(self, obj, system, **kwargs):
 super(ArmTrustedFirmware, self).__init__(**kwargs)
diff --git a/src/arch/arm/ArmFsWorkload.py b/src/arch/arm/ArmFsWorkload.py
index bc27c6d..b57b1f0 100644
--- a/src/arch/arm/ArmFsWorkload.py
+++ b/src/arch/arm/ArmFsWorkload.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2009, 2012-2013, 2015-2019 ARM Limited
+# Copyright (c) 2009, 2012-2013, 2015-2020 ARM Limited
 

[gem5-dev] Change in gem5/gem5[develop]: sim: make ProbeListener satisfy the rule of five with deleted

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37977 )


Change subject: sim: make ProbeListener satisfy the rule of five with  
deleted

..

sim: make ProbeListener satisfy the rule of five with deleted

Since this class has a custom destructor ~ProbeListener(), it should
also generally have the 4 other methods defined, otherwise calling
those methods lead to subtle failures.

In this specific case, the ProbeManager *const manager; field stores a
pointer back to the ProbeListener object at:

ProbeListener::ProbeListener {
manager->addListener(name, *this);

which gets unregistered by the destructor:

ProbeListener::~ProbeListener()
manager->removeListener(name, *this);

and because the default copy does not re-register anything, it leads to
unregistration.

Therefore, a copy constructor would need the manager to support multiple
identical listeners, or at least refcount them, which would be overkill.

The two move operations would be more feasible, as we could make them
unregister the old ProbeListener address and then re-register the new one,
but that is not very efficient, so we just delete them as well.

A consequence of not implementing the move methods is that it is
impossible to store ProbeListener inside an std::vector. since objects
inside std::vector may need to be moved in memory when the vector resizes,
and therefore need to be movable. The alternative is to use an std::vector
of std::unique_ptr instead.

Change-Id: I8dc0157665391f86e2ca81d144bc6a42e9312d6c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37977
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/sim/probe/probe.hh
1 file changed, 4 insertions(+), 0 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/probe/probe.hh b/src/sim/probe/probe.hh
index 97edf0b..57132fc 100644
--- a/src/sim/probe/probe.hh
+++ b/src/sim/probe/probe.hh
@@ -119,6 +119,10 @@
   public:
 ProbeListener(ProbeManager *manager, const std::string );
 virtual ~ProbeListener();
+ProbeListener(const ProbeListener& other) = delete;
+ProbeListener& operator=(const ProbeListener& other) = delete;
+ProbeListener(ProbeListener&& other) noexcept = delete;
+ProbeListener& operator=(ProbeListener&& other) noexcept = delete;

   protected:
 ProbeManager *const manager;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8dc0157665391f86e2ca81d144bc6a42e9312d6c
Gerrit-Change-Number: 37977
Gerrit-PatchSet: 2
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: add official names to all PMU events

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37976 )


Change subject: arch-arm: add official names to all PMU events
..

arch-arm: add official names to all PMU events

Change-Id: I1d44ffa540b0cf175f279c6509839ad2dd69017a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37976
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/arch/arm/ArmPMU.py
1 file changed, 11 insertions(+), 0 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/ArmPMU.py b/src/arch/arm/ArmPMU.py
index c712a97..1839010 100644
--- a/src/arch/arm/ArmPMU.py
+++ b/src/arch/arm/ArmPMU.py
@@ -117,14 +117,20 @@
 if bpred is not None and isNullPointer(bpred):
 bpred = None

+# 0x00: SW_INCR
 self.addEvent(SoftwareIncrement(self,0x00))
 # 0x01: L1I_CACHE_REFILL
+# 0x02: L1I_TLB_REFILL,
 self.addEvent(ProbeEvent(self,0x02, itb, "Refills"))
 # 0x03: L1D_CACHE_REFILL
 # 0x04: L1D_CACHE
+# 0x05: L1D_TLB_REFILL
 self.addEvent(ProbeEvent(self,0x05, dtb, "Refills"))
+# 0x06: LD_RETIRED
 self.addEvent(ProbeEvent(self,0x06, cpu, "RetiredLoads"))
+# 0x07: ST_RETIRED
 self.addEvent(ProbeEvent(self,0x07, cpu, "RetiredStores"))
+# 0x08: INST_RETIRED
 self.addEvent(ProbeEvent(self,0x08, cpu, "RetiredInsts"))
 # 0x09: EXC_TAKEN
 # 0x0A: EXC_RETURN
@@ -133,10 +139,14 @@
 # 0x0D: BR_IMMED_RETIRED
 # 0x0E: BR_RETURN_RETIRED
 # 0x0F: UNALIGEND_LDST_RETIRED
+# 0x10: BR_MIS_PRED
 self.addEvent(ProbeEvent(self,0x10, bpred, "Misses"))
+# 0x11: CPU_CYCLES
 self.addEvent(ProbeEvent(self, ARCH_EVENT_CORE_CYCLES, cpu,
  "ActiveCycles"))
+# 0x12: BR_PRED
 self.addEvent(ProbeEvent(self,0x12, bpred, "Branches"))
+# 0x13: MEM_ACCESS
 self.addEvent(ProbeEvent(self,0x13, cpu, "RetiredLoads",
  "RetiredStores"))
 # 0x14: L1I_CACHE
@@ -152,6 +162,7 @@
 # 0x1E: CHAIN
 # 0x1F: L1D_CACHE_ALLOCATE
 # 0x20: L2D_CACHE_ALLOCATE
+# 0x21: BR_RETIRED
 self.addEvent(ProbeEvent(self,0x21, cpu, "RetiredBranches"))
 # 0x22: BR_MIS_PRED_RETIRED
 # 0x23: STALL_FRONTEND

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1d44ffa540b0cf175f279c6509839ad2dd69017a
Gerrit-Change-Number: 37976
Gerrit-PatchSet: 2
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add ID_MMFR4{,EL1} system registers

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34876 )


Change subject: arch-arm: Add ID_MMFR4{,EL1} system registers
..

arch-arm: Add ID_MMFR4{,EL1} system registers

Change-Id: Id50ebd2ef2e69ecbd3b7f64a4e9eafe00e283806
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34876
Reviewed-by: Ciro Santilli 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/arch/arm/ArmISA.py
M src/arch/arm/fastmodel/CortexA76/thread_context.cc
M src/arch/arm/insts/misc64.cc
M src/arch/arm/isa.cc
M src/arch/arm/kvm/arm_cpu.cc
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/utility.cc
9 files changed, 22 insertions(+), 2 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Ciro Santilli: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 0cb973a..bc5f823 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -72,6 +72,7 @@
 # SuperSec | Coherent TLB | Bcast Maint |
 # BP Maint | Cache Maint Set/way | Cache Maint MVA
 id_mmfr3 = Param.UInt32(0x02102211, "Memory Model Feature Register 3")
+id_mmfr4 = Param.UInt32(0x, "Memory Model Feature Register 4")

 # See section B4.1.84 of ARM ARM
 # All values are latest for ARMv7-A profile
diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc  
b/src/arch/arm/fastmodel/CortexA76/thread_context.cc

index d2aca9b..44becd3 100644
--- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
@@ -300,6 +300,7 @@
 { ArmISA::MISCREG_ID_MMFR1, "ID_MMFR1" },
 { ArmISA::MISCREG_ID_MMFR2, "ID_MMFR2" },
 { ArmISA::MISCREG_ID_MMFR3, "ID_MMFR3" },
+{ ArmISA::MISCREG_ID_MMFR4, "ID_MMFR4" },
 { ArmISA::MISCREG_ID_ISAR0, "ID_ISAR0" },
 { ArmISA::MISCREG_ID_ISAR1, "ID_ISAR1" },
 { ArmISA::MISCREG_ID_ISAR2, "ID_ISAR2" },
@@ -582,6 +583,7 @@
 { ArmISA::MISCREG_ID_MMFR1_EL1, "ID_MMFR1_EL1" },
 { ArmISA::MISCREG_ID_MMFR2_EL1, "ID_MMFR2_EL1" },
 { ArmISA::MISCREG_ID_MMFR3_EL1, "ID_MMFR3_EL1" },
+{ ArmISA::MISCREG_ID_MMFR4_EL1, "ID_MMFR4_EL1" },
 { ArmISA::MISCREG_ID_ISAR0_EL1, "ID_ISAR0_EL1" },
 { ArmISA::MISCREG_ID_ISAR1_EL1, "ID_ISAR1_EL1" },
 { ArmISA::MISCREG_ID_ISAR2_EL1, "ID_ISAR2_EL1" },
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 4d6a95b..40126cf 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -365,7 +365,7 @@
   case MISCREG_ID_MMFR1_EL1:
   case MISCREG_ID_MMFR2_EL1:
   case MISCREG_ID_MMFR3_EL1:
-  //case MISCREG_ID_MMFR4_EL1:
+  case MISCREG_ID_MMFR4_EL1:
   case MISCREG_ID_ISAR0_EL1:
   case MISCREG_ID_ISAR1_EL1:
   case MISCREG_ID_ISAR2_EL1:
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index dd6a680..f4fabc1 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -350,6 +350,7 @@
 miscRegs[MISCREG_ID_MMFR1] = p.id_mmfr1;
 miscRegs[MISCREG_ID_MMFR2] = p.id_mmfr2;
 miscRegs[MISCREG_ID_MMFR3] = p.id_mmfr3;
+miscRegs[MISCREG_ID_MMFR4] = p.id_mmfr4;

 miscRegs[MISCREG_ID_ISAR5] = insertBits(
 miscRegs[MISCREG_ID_ISAR5], 19, 4,
@@ -1391,6 +1392,7 @@
   case MISCREG_ID_MMFR1:
   case MISCREG_ID_MMFR2:
   case MISCREG_ID_MMFR3:
+  case MISCREG_ID_MMFR4:
   case MISCREG_ID_ISAR0:
   case MISCREG_ID_ISAR1:
   case MISCREG_ID_ISAR2:
diff --git a/src/arch/arm/kvm/arm_cpu.cc b/src/arch/arm/kvm/arm_cpu.cc
index a52b506..f674c7e 100644
--- a/src/arch/arm/kvm/arm_cpu.cc
+++ b/src/arch/arm/kvm/arm_cpu.cc
@@ -157,6 +157,7 @@
 REG_CP32(15, 0, 0, 2, 3), // ID_ISAR3
 REG_CP32(15, 0, 0, 2, 4), // ID_ISAR4
 REG_CP32(15, 0, 0, 2, 5), // ID_ISAR5
+REG_CP32(15, 0, 0, 2, 6), // ID_MMFR4
 REG_CP32(15, 0, 0, 2, 7), // ID_ISAR6

 REG_CP32(15, 0, 1, 0, 0), // CSSIDR
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 825811f..b5af9b6 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -394,7 +394,7 @@
   case 5:
 return MISCREG_ID_ISAR5;
   case 6:
-return MISCREG_RAZ; // read as zero
+return MISCREG_ID_MMFR4;
   case 7:
 return MISCREG_ID_ISAR6;
 }
@@ -2070,6 +2070,8 @@
 return MISCREG_ID_ISAR4_EL1;
   case 5:
 return MISCREG_ID_ISAR5_EL1;
+  case 6:
+return MISCREG_ID_MMFR4_EL1;
   case 7:
 return 

[gem5-dev] Change in gem5/gem5[develop]: configs: hack PMU in fs.py

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37978 )



Change subject: configs: hack PMU in fs.py
..

configs: hack PMU in fs.py

Change-Id: I13b705183eb7c2e810594e9092325f0f2fee9485
---
M configs/example/fs.py
A src/arch/arm/PmuListener.py
M src/arch/arm/SConscript
A src/arch/arm/pmu_listener.cc
A src/arch/arm/pmu_listener.hh
5 files changed, 194 insertions(+), 0 deletions(-)



diff --git a/configs/example/fs.py b/configs/example/fs.py
index 229c50e..c0c50cf 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -233,6 +233,27 @@

 MemConfig.config_mem(options, test_sys)

+pmu_listeners = []
+for  cpu in test_sys.cpu:
+if buildEnv['TARGET_ISA'] in "arm":
+for isa in cpu.isa:
+isa.pmu = ArmPMU(interrupt=ArmPPI(num=20))
+isa.pmu.addArchEvents(
+cpu=cpu, dtb=cpu.mmu.dtb, itb=cpu.mmu.itb,
+icache=getattr(cpu, "icache", None),
+dcache=getattr(cpu, "dcache", None),
+l2cache=getattr(test_sys, "l2", None))
+pmu_listeners.append(PmuListener(
+cpu=cpu,
+dtb=cpu.mmu.dtb,
+itb=cpu.mmu.itb,
+icache=getattr(cpu, "icache", None),
+dcache=getattr(cpu, "dcache", None),
+l2cache=getattr(test_sys, "l2", None),
+bpred=getattr(cpu, "branchPred", None),
+))
+test_sys.pmu_listeners = pmu_listeners
+
 return test_sys

 def build_drive_system(np):
diff --git a/src/arch/arm/PmuListener.py b/src/arch/arm/PmuListener.py
new file mode 100644
index 000..31c95fc
--- /dev/null
+++ b/src/arch/arm/PmuListener.py
@@ -0,0 +1,48 @@
+# Copyright (c) 2020 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+
+from m5.SimObject import *
+from m5.params import *
+
+class PmuListener(SimObject):
+type = 'PmuListener'
+cxx_class = 'ArmISA::PmuListener'
+cxx_header = 'arch/arm/pmu_listener.hh'
+cpu = Param.SimObject(NULL)
+dtb = Param.SimObject(NULL)
+itb = Param.SimObject(NULL)
+icache = Param.SimObject(NULL)
+dcache = Param.SimObject(NULL)
+l2cache = Param.SimObject(NULL)
+bpred = Param.SimObject(NULL)
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 31e83a7..6cf250f 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -88,6 +88,7 @@
 Source('pmu.cc')
 Source('process.cc')
 Source('qarma.cc')
+Source('pmu_listener.cc')
 Source('remote_gdb.cc')
 Source('semihosting.cc')
 Source('system.cc')
@@ -110,6 +111,7 @@
 SimObject('ArmSystem.py')
 SimObject('ArmTLB.py')
 SimObject('ArmPMU.py')
+SimObject('PmuListener.py')

 DebugFlag('Arm')
 DebugFlag('ArmTme', 'Transactional Memory Extension')
diff --git a/src/arch/arm/pmu_listener.cc b/src/arch/arm/pmu_listener.cc
new file mode 

[gem5-dev] Change in gem5/gem5[develop]: sim: make ProbeListener satisfy the rule of five with deleted

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37977 )



Change subject: sim: make ProbeListener satisfy the rule of five with  
deleted

..

sim: make ProbeListener satisfy the rule of five with deleted

Since this class has a custom destructor ~ProbeListener(), it should
also generally have the 4 other methods defined, otherwise calling
those methods lead to subtle failures.

In this specific case, the ProbeManager *const manager; field stores a
pointer back to the ProbeListener object at:

ProbeListener::ProbeListener {
manager->addListener(name, *this);

which gets unregistered by the destructor:

ProbeListener::~ProbeListener()
manager->removeListener(name, *this);

and because the default copy does not re-register anything, it leads to
unregistration.

Therefore, a copy constructor would need the manager to support multiple
identical listeners, or at least refcount them, which would be overkill.

The two move operations would be more feasible, as we could make them
unregister the old ProbeListener address and then re-register the new one,
but that is not very efficient, so we just delete them as well.

A consequence of not implementing the move methods is that it is
impossible to store ProbeListener inside an std::vector. since objects
inside std::vector may need to be moved in memory when the vector resizes,
and therefore need to be movable. The alternative is to use an std::vector
of std::unique_ptr instead.

Change-Id: I8dc0157665391f86e2ca81d144bc6a42e9312d6c
---
M src/sim/probe/probe.hh
1 file changed, 4 insertions(+), 0 deletions(-)



diff --git a/src/sim/probe/probe.hh b/src/sim/probe/probe.hh
index 97edf0b..57132fc 100644
--- a/src/sim/probe/probe.hh
+++ b/src/sim/probe/probe.hh
@@ -119,6 +119,10 @@
   public:
 ProbeListener(ProbeManager *manager, const std::string );
 virtual ~ProbeListener();
+ProbeListener(const ProbeListener& other) = delete;
+ProbeListener& operator=(const ProbeListener& other) = delete;
+ProbeListener(ProbeListener&& other) noexcept = delete;
+ProbeListener& operator=(ProbeListener&& other) noexcept = delete;

   protected:
 ProbeManager *const manager;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8dc0157665391f86e2ca81d144bc6a42e9312d6c
Gerrit-Change-Number: 37977
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: add official names to all PMU events

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37976 )



Change subject: arch-arm: add official names to all PMU events
..

arch-arm: add official names to all PMU events

Change-Id: I1d44ffa540b0cf175f279c6509839ad2dd69017a
---
M src/arch/arm/ArmPMU.py
1 file changed, 11 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/ArmPMU.py b/src/arch/arm/ArmPMU.py
index c712a97..1839010 100644
--- a/src/arch/arm/ArmPMU.py
+++ b/src/arch/arm/ArmPMU.py
@@ -117,14 +117,20 @@
 if bpred is not None and isNullPointer(bpred):
 bpred = None

+# 0x00: SW_INCR
 self.addEvent(SoftwareIncrement(self,0x00))
 # 0x01: L1I_CACHE_REFILL
+# 0x02: L1I_TLB_REFILL,
 self.addEvent(ProbeEvent(self,0x02, itb, "Refills"))
 # 0x03: L1D_CACHE_REFILL
 # 0x04: L1D_CACHE
+# 0x05: L1D_TLB_REFILL
 self.addEvent(ProbeEvent(self,0x05, dtb, "Refills"))
+# 0x06: LD_RETIRED
 self.addEvent(ProbeEvent(self,0x06, cpu, "RetiredLoads"))
+# 0x07: ST_RETIRED
 self.addEvent(ProbeEvent(self,0x07, cpu, "RetiredStores"))
+# 0x08: INST_RETIRED
 self.addEvent(ProbeEvent(self,0x08, cpu, "RetiredInsts"))
 # 0x09: EXC_TAKEN
 # 0x0A: EXC_RETURN
@@ -133,10 +139,14 @@
 # 0x0D: BR_IMMED_RETIRED
 # 0x0E: BR_RETURN_RETIRED
 # 0x0F: UNALIGEND_LDST_RETIRED
+# 0x10: BR_MIS_PRED
 self.addEvent(ProbeEvent(self,0x10, bpred, "Misses"))
+# 0x11: CPU_CYCLES
 self.addEvent(ProbeEvent(self, ARCH_EVENT_CORE_CYCLES, cpu,
  "ActiveCycles"))
+# 0x12: BR_PRED
 self.addEvent(ProbeEvent(self,0x12, bpred, "Branches"))
+# 0x13: MEM_ACCESS
 self.addEvent(ProbeEvent(self,0x13, cpu, "RetiredLoads",
  "RetiredStores"))
 # 0x14: L1I_CACHE
@@ -152,6 +162,7 @@
 # 0x1E: CHAIN
 # 0x1F: L1D_CACHE_ALLOCATE
 # 0x20: L2D_CACHE_ALLOCATE
+# 0x21: BR_RETIRED
 self.addEvent(ProbeEvent(self,0x21, cpu, "RetiredBranches"))
 # 0x22: BR_MIS_PRED_RETIRED
 # 0x23: STALL_FRONTEND

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I1d44ffa540b0cf175f279c6509839ad2dd69017a
Gerrit-Change-Number: 37976
Gerrit-PatchSet: 1
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[gem5-dev] Change in gem5/gem5[develop]: sim: add test for IniFile::visitSection

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37975 )



Change subject: sim: add test for IniFile::visitSection
..

sim: add test for IniFile::visitSection

iniFile was used as a global variable, and thee tests were relying on
MatchNotFound running after MatchFound, which would first empty the
istringstream.

Therefore, the only way to reuse that test file was to rewind
istringstream. Since this is a bit ugly, and it is better practice not to
rely on a specific test order, this commit instead creates a separate
istringstream per test.

Change-Id: If3cf5ef74ba7dfaf2f90b55acd1c3a8bdda04947
---
M src/base/inifile.test.cc
1 file changed, 31 insertions(+), 7 deletions(-)



diff --git a/src/base/inifile.test.cc b/src/base/inifile.test.cc
index 0d1600e..0cabb55 100644
--- a/src/base/inifile.test.cc
+++ b/src/base/inifile.test.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018 ARM Limited
+ * Copyright (c) 2018, 2020 ARM Limited
  * All rights reserved
  *
  * Copyright (c) 2002-2005 The Regents of The University of Michigan
@@ -29,20 +29,27 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */

+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wdeprecated-copy"
+#include 
 #include 
+#pragma GCC diagnostic pop

 #include 
 #include 
 #include 
+#include 
 #include 

 #include "base/inifile.hh"

 using namespace std;
+using testing::ElementsAre;
+using testing::Pair;

 namespace {

-std::istringstream iniFile(R"ini_file(
+const char *iniFileString = R"ini_file(
 [General]
Test1=BARasdf
Test2=bar
@@ -60,14 +67,13 @@

 [Junk]
 Test4+=mia
-)ini_file");
-
-};
+)ini_file";

 TEST(Initest, MatchFound)
 {
 IniFile simConfigDB;
-simConfigDB.load(iniFile);
+std::istringstream is{iniFileString};
+simConfigDB.load(is);

 std::string value;

@@ -95,7 +101,8 @@
 TEST(Initest, MatchNotFound)
 {
 IniFile simConfigDB;
-simConfigDB.load(iniFile);
+std::istringstream is;
+simConfigDB.load(is);

 std::string value;

@@ -105,3 +112,20 @@
 ret = simConfigDB.find("Junk", "test4", value);
 ASSERT_FALSE(ret);
 }
+
+TEST(Initest, visitSection)
+{
+IniFile simConfigDB;
+std::istringstream is{iniFileString};
+simConfigDB.load(is);
+std::vector> keys_values;
+simConfigDB.visitSection("Junk", [&](std::string key, std::string  
value)

+{
+keys_values.emplace_back(key, value);
+});
+ASSERT_THAT(keys_values, ElementsAre(
+Pair("Test4", "mama mia"),
+Pair("Test3", "yo")
+));
+}
+}

--
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: implement the aarch64 ID_ISAR6_EL1 miscregister

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30935 )


Change subject: arch-arm: implement the aarch64 ID_ISAR6_EL1 miscregister
..

arch-arm: implement the aarch64 ID_ISAR6_EL1 miscregister

This register is used since the Linux kernel 5.6 aarch64 boot.

This register indicates CPU capabilities in aarch32 mode, and it has the
same value as the aarch32 ID_ISAR6 miscregister, which is also added.

The capability values of those registers are analogous to those present in
aarch64 accessible ID_AA64ISAR0_EL1 and ID_AA64ISAR1_EL1, which refer to
aarch64 capabilities however, and were already implemented before this
commit.

The arm architecture document clarifies that reads to this system register
location before it had been defined should return 0, but we were faulting
instead:


Prior to the introduction of the features described by this register,

this register was unnamed and reserved, RES0 from EL1, EL2, and EL3.

Change-Id: I70e99536dc98925e88233fd4c6887bbcdd5d87dc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30935
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/ArmISA.py
M src/arch/arm/fastmodel/CortexA76/thread_context.cc
M src/arch/arm/insts/misc64.cc
M src/arch/arm/isa.cc
M src/arch/arm/kvm/arm_cpu.cc
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/utility.cc
9 files changed, 27 insertions(+), 4 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 3e18665..0cb973a 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -81,6 +81,8 @@
 id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute  
Register 3")
 id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute  
Register 4")
 id_isar5 = Param.UInt32(0x1100, "Instruction Set Attribute  
Register 5")

+# !I8MM | !BF16 | SPECRES = 0 | !SB | !FHM | DP | JSCVT
+id_isar6 = Param.UInt32(0x0001, "Instruction Set Attribute  
Register 6")


 fpsid = Param.UInt32(0x410430a0, "Floating-point System ID Register")

@@ -98,10 +100,11 @@
 id_aa64dfr1_el1 = Param.UInt64(0x,
 "AArch64 Debug Feature Register 1")

-# !TME | !Atomic | !CRC32 | !SHA2 | RDM | !SHA1 | !AES
+# !FHM | !TME | !Atomic | !CRC32 | !SHA2 | RDM | !SHA1 | !AES
 id_aa64isar0_el1 = Param.UInt64(0x1000,
 "AArch64 Instruction Set Attribute Register 0")

+# !I8MM | !BF16 | SPECRES = 0 | !SB |
 # GPI = 0x0 | GPA = 0x1 | API=0x0 | FCMA | JSCVT | APA=0x1
 id_aa64isar1_el1 = Param.UInt64(0x01011010,
 "AArch64 Instruction Set Attribute Register 1")
diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc  
b/src/arch/arm/fastmodel/CortexA76/thread_context.cc

index 9c9b933..d2aca9b 100644
--- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
@@ -306,6 +306,7 @@
 { ArmISA::MISCREG_ID_ISAR3, "ID_ISAR3" },
 { ArmISA::MISCREG_ID_ISAR4, "ID_ISAR4" },
 { ArmISA::MISCREG_ID_ISAR5, "ID_ISAR5" },
+{ ArmISA::MISCREG_ID_ISAR6, "ID_ISAR6" },
 { ArmISA::MISCREG_CCSIDR, "CCSIDR" },
 { ArmISA::MISCREG_CLIDR, "CLIDR" },
 { ArmISA::MISCREG_AIDR, "AIDR" },
@@ -587,6 +588,7 @@
 { ArmISA::MISCREG_ID_ISAR3_EL1, "ID_ISAR3_EL1" },
 { ArmISA::MISCREG_ID_ISAR4_EL1, "ID_ISAR4_EL1" },
 { ArmISA::MISCREG_ID_ISAR5_EL1, "ID_ISAR5_EL1" },
+{ ArmISA::MISCREG_ID_ISAR6_EL1, "ID_ISAR6_EL1" },
 { ArmISA::MISCREG_MVFR0_EL1, "MVFR0_EL1" },
 { ArmISA::MISCREG_MVFR1_EL1, "MVFR1_EL1" },
 { ArmISA::MISCREG_MVFR2_EL1, "MVFR2_EL1" },
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 47a8ad9..4d6a95b 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -372,6 +372,7 @@
   case MISCREG_ID_ISAR3_EL1:
   case MISCREG_ID_ISAR4_EL1:
   case MISCREG_ID_ISAR5_EL1:
+  case MISCREG_ID_ISAR6_EL1:
   case MISCREG_MVFR0_EL1:
   case MISCREG_MVFR1_EL1:
   case MISCREG_MVFR2_EL1:
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 9b0b957..dd6a680 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -344,6 +344,7 @@
 miscRegs[MISCREG_ID_ISAR3] = p.id_isar3;
 miscRegs[MISCREG_ID_ISAR4] = p.id_isar4;
 miscRegs[MISCREG_ID_ISAR5] = p.id_isar5;
+miscRegs[MISCREG_ID_ISAR6] = p.id_isar6;

 miscRegs[MISCREG_ID_MMFR0] = p.id_mmfr0;
 miscRegs[MISCREG_ID_MMFR1] = p.id_mmfr1;
diff --git a/src/arch/arm/kvm/arm_cpu.cc b/src/arch/arm/kvm/arm_cpu.cc
index 4fbb78e..a52b506 100644
--- a/src/arch/arm/kvm/arm_cpu.cc
+++ 

[gem5-dev] Change in gem5/gem5[develop]: sim: create SERIALIZE_MAPPING and UNSERIALIZE_MAPPING

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/36135 )


Change subject: sim: create SERIALIZE_MAPPING and UNSERIALIZE_MAPPING
..

sim: create SERIALIZE_MAPPING and UNSERIALIZE_MAPPING

The motivation for those new methods is to prevent checkpoints from
breaking when new map entries are added.

Change-Id: I0ff8681498bcf669492e6b876ad385fda4673d77
JIRA: https://gem5.atlassian.net/browse/GEM5-661
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36135
Reviewed-by: Richard Cooper 
Reviewed-by: Daniel Carvalho 
Reviewed-by: Andreas Sandberg 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/sim/serialize.hh
1 file changed, 56 insertions(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  Richard Cooper: Looks good to me, but someone else must approve
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh
index 51313a4..987bee2 100644
--- a/src/sim/serialize.hh
+++ b/src/sim/serialize.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, 2018 ARM Limited
+ * Copyright (c) 2015, 2018, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -50,7 +50,9 @@
 #include 
 #include 
 #include 
+#include 
 #include 
+#include 
 #include 

 #include "base/logging.hh"
@@ -515,6 +517,47 @@
 void
 objParamIn(CheckpointIn , const std::string , SimObject * );

+/**
+ * Serialize a mapping represented as two arrays: one containing names
+ * and the other containing values.
+ *
+ * @param names array of keys
+ * @param param array of values
+ * @param size size of the names and param arrays
+ */
+template 
+void
+mappingParamOut(CheckpointOut , const char* sectionName,
+const char* const names[], const T *param, unsigned size)
+{
+Serializable::ScopedCheckpointSection sec(os, sectionName);
+for (unsigned i = 0; i < size; ++i) {
+paramOut(os, names[i], param[i]);
+}
+}
+
+/**
+ * Restore mappingParamOut. Keys missing from the checkpoint are ignored.
+ */
+template 
+void
+mappingParamIn(CheckpointIn , const char* sectionName,
+const char* const names[], T *param, unsigned size)
+{
+Serializable::ScopedCheckpointSection sec(cp, sectionName);
+std::unordered_map name_to_index;
+for (size_t i = 0; i < size; i++) {
+name_to_index[names[i]] = i;
+}
+for (size_t i = 0; i < size; i++) {
+auto& key = names[i];
+T value;
+if (optParamIn(cp, key, value)) {
+param[name_to_index[key]] = value;
+}
+}
+}
+
 //
 // These macros are streamlined to use in serialize/unserialize
 // functions.  It's assumed that serialize() has a parameter 'os' for
@@ -646,4 +689,16 @@
 objptr = dynamic_cast(sptr);  \
 } while (0)

+/**
+ * \def SERIALIZE_MAPPING(member, names, size)
+ */
+#define SERIALIZE_MAPPING(member, names, size) \
+mappingParamOut(cp, #member, names, member, size)
+
+/**
+ * \def UNSERIALIZE_MAPPING(member, names, size)
+ */
+#define UNSERIALIZE_MAPPING(member, names, size) \
+mappingParamIn(cp, #member, names, member, size)
+
 #endif // __SERIALIZE_HH__

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0ff8681498bcf669492e6b876ad385fda4673d77
Gerrit-Change-Number: 36135
Gerrit-PatchSet: 8
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: serialize miscregs as a map

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/36116 )


Change subject: arch-arm: serialize miscregs as a map
..

arch-arm: serialize miscregs as a map

This will prevent checkpoints from breaking on every miscreg addition.

Before this commit, miscregs were stored as an array:

[system.cpu.isa]
miscRegs=965 0 0 0 0 0 0 0 0 0 0 0 17895697 ...

and after this commit they are stored as a map:

[system.cpu.isa]

[system.cpu.isa.miscRegs]
cpsr=965
spsr=0
spsr_fiq=0
spsr_irq=0
spsr_svc=0
spsr_mon=0
spsr_abt=0
spsr_hyp=0
spsr_und=0
elr_hyp=0
fpsid=0
fpscr=0
mvfr1=17895697

JIRA: https://gem5.atlassian.net/browse/GEM5-661
Change-Id: I4c7206bd9ac1cfb81297d45c8117ff8ae675
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36116
Reviewed-by: Andreas Sandberg 
Reviewed-by: Richard Cooper 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/arch/arm/isa.cc
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Richard Cooper: Looks good to me, but someone else must approve
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 9b1cde3..9b0b957 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -2354,14 +2354,14 @@
 ISA::serialize(CheckpointOut ) const
 {
 DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
-SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
+SERIALIZE_MAPPING(miscRegs, miscRegName, NUM_PHYS_MISCREGS);
 }

 void
 ISA::unserialize(CheckpointIn )
 {
 DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
-UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
+UNSERIALIZE_MAPPING(miscRegs, miscRegName, NUM_PHYS_MISCREGS);
 CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
 updateRegMap(tmp_cpsr);
 }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4c7206bd9ac1cfb81297d45c8117ff8ae675
Gerrit-Change-Number: 36116
Gerrit-PatchSet: 11
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: move serialize and unserialize definition to cpp file

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/36115 )


Change subject: arch-arm: move serialize and unserialize definition to cpp  
file

..

arch-arm: move serialize and unserialize definition to cpp file

Change-Id: I9ac64184d3fe36617f474a714b228b55b9a90976
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36115
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
2 files changed, 18 insertions(+), 15 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 217f432..9b1cde3 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -2351,6 +2351,22 @@
 }

 void
+ISA::serialize(CheckpointOut ) const
+{
+DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
+SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
+}
+
+void
+ISA::unserialize(CheckpointIn )
+{
+DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
+UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
+CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
+updateRegMap(tmp_cpsr);
+}
+
+void
 ISA::addressTranslation64(TLB::ArmTranslationType tran_type,
 BaseTLB::Mode mode, Request::Flags flags, RegVal val)
 {
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 4a824ed..6b9dd3c 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -810,21 +810,8 @@
 static void zeroSveVecRegUpperPart(VecRegContainer ,
unsigned eCount);

-void
-serialize(CheckpointOut ) const override
-{
-DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
-SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
-}
-
-void
-unserialize(CheckpointIn ) override
-{
-DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
-UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
-CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
-updateRegMap(tmp_cpsr);
-}
+void serialize(CheckpointOut ) const override;
+void unserialize(CheckpointIn ) override;

 void startup() override;


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9ac64184d3fe36617f474a714b228b55b9a90976
Gerrit-Change-Number: 36115
Gerrit-PatchSet: 3
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim,base: make checkpointMapIn warn if an unknown key is found

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37575 )



Change subject: sim,base: make checkpointMapIn warn if an unknown key is  
found

..

sim,base: make checkpointMapIn warn if an unknown key is found

The warning happens when a key is present in the checkpoint but not in the
values that gem5 source code knows about.

Change-Id: I23340a953f3e604642b97690a7328b10fdd740a8
---
M src/base/inifile.cc
M src/base/inifile.hh
M src/sim/serialize.cc
M src/sim/serialize.hh
4 files changed, 75 insertions(+), 0 deletions(-)



diff --git a/src/base/inifile.cc b/src/base/inifile.cc
index 1fbebb4..acbe422 100644
--- a/src/base/inifile.cc
+++ b/src/base/inifile.cc
@@ -345,3 +345,26 @@
 i->second->dump(i->first);
 }
 }
+
+/// Iterate key values of a given section.
+IniFile::Section::EntryTable::const_iterator
+IniFile::Section::cbegin() const
+{
+return table.cbegin();
+}
+
+IniFile::Section::EntryTable::const_iterator
+IniFile::Section::cend() const
+{
+return table.cend();
+}
+
+std::pair
+IniFile::iterSection(const std::string )
+{
+const auto& section = table.at(sectionName);
+return std::make_pair(
+SectionIterator(section->cbegin()),
+SectionIterator(section->cend())
+);
+}
diff --git a/src/base/inifile.hh b/src/base/inifile.hh
index 095d132..f1101cf 100644
--- a/src/base/inifile.hh
+++ b/src/base/inifile.hh
@@ -84,11 +84,17 @@
 void appendValue(const std::string ) { value += " "; value += v;  
}

 };

+  public:
+class SectionIterator;
+
+  protected:
 ///
 /// A section.
 ///
 class Section
 {
+friend class SectionIterator;
+
 /// EntryTable type.  Map of strings to Entry object pointers.
 typedef std::unordered_map EntryTable;

@@ -132,6 +138,9 @@

 /// Print the contents of this section to cout (for debugging).
 void dump(const std::string );
+
+EntryTable::const_iterator cbegin() const;
+EntryTable::const_iterator cend() const;
 };

 /// SectionTable type.  Map of strings to Section object pointers.
@@ -151,6 +160,25 @@
 Section *findSection(const std::string ) const;

   public:
+class SectionIterator {
+  private:
+using It = Section::EntryTable::const_iterator;
+It it;
+  public:
+using value_type = std::pair;
+SectionIterator(It it) : it(it) {}
+SectionIterator& operator++() {it++; return *this;}
+SectionIterator operator++(int) {auto retval = *this;
+++(*this); return retval;}
+bool operator==(SectionIterator other) const { return it ==  
other.it; }

+bool operator!=(SectionIterator other) const {
+return !(*this == other); }
+value_type operator*() {
+auto pair = *it;
+return std::make_pair(pair.first, pair.second->getValue());
+}
+};
+
 /// Constructor.
 IniFile();

@@ -203,6 +231,10 @@

 /// Dump contents to cout.  For debugging.
 void dump();
+
+/// Iterate key values of a given section.
+std::pair
+iterSection(const std::string );
 };

 #endif // __INIFILE_HH__
diff --git a/src/sim/serialize.cc b/src/sim/serialize.cc
index e502d9a..3732a28 100644
--- a/src/sim/serialize.cc
+++ b/src/sim/serialize.cc
@@ -337,6 +337,12 @@
 return db->sectionExists(section);
 }

+std::pair
+CheckpointIn::iterSection(const string )
+{
+return db->iterSection(section);
+}
+
 void
 objParamIn(CheckpointIn , const string , SimObject * )
 {
diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh
index c774eab..74567a6 100644
--- a/src/sim/serialize.hh
+++ b/src/sim/serialize.hh
@@ -55,6 +55,7 @@
 #include 
 #include 

+#include "base/inifile.hh"
 #include "base/logging.hh"
 #include "sim/serialize_handlers.hh"

@@ -94,6 +95,8 @@

 bool entryExists(const std::string , const std::string );
 bool sectionExists(const std::string );
+std::pair
+iterSection(const std::string );
 /** @}*/ //end of api_checkout group

 // The following static functions have to do with checkpoint
@@ -557,6 +560,17 @@
 param[name_to_index[key]] = value;
 }
 }
+auto start_end = os.iterSection(Serializable::currentSection());
+auto start = start_end.first;
+const auto end = start_end.second;
+while (start != end) {
+const auto& key = (*start).first;
+if (!name_to_index.count(key)) {
+warn("unknown entry found in checkpoint: %s %s\n",
+Serializable::currentSection(), key);
+}
+start++;
+}
 }

 //

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Gerrit-Change-Id: 

[gem5-dev] Change in gem5/gem5[develop]: misc: create C declarations for the _addr and _semi m5ops

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/36896 )


Change subject: misc: create C declarations for the _addr and _semi m5ops
..

misc: create C declarations for the _addr and _semi m5ops

Symbols such as m5_exit_addr are already present in the libm5.a, but were
not previously exposed in a header. This commit allows external C programs
to use those versions of the functions as well.

Change-Id: I925e3af7bd6cb23e06fb744d453153323afb9310
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36896
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M include/gem5/m5ops.h
1 file changed, 16 insertions(+), 0 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/include/gem5/m5ops.h b/include/gem5/m5ops.h
index 315b1dc..7e12c70 100644
--- a/include/gem5/m5ops.h
+++ b/include/gem5/m5ops.h
@@ -35,6 +35,8 @@

 #include 

+#include 
+
 void m5_arm(uint64_t address);
 void m5_quiesce(void);
 void m5_quiesce_ns(uint64_t ns);
@@ -73,6 +75,20 @@
  */
 void m5_workload();

+/*
+ * Create _addr and _semi versions all declarations, e.g. m5_exit_addr and
+ * m5_exit_semi. These expose the the memory and semihosting variants of  
the

+ * ops.
+ *
+ * Some of those declarations are not defined for certain ISAs, e.g. X86
+ * does not have _semi, but we felt that ifdefing them out could cause more
+ * trouble tham leaving them in.
+ */
+#define M5OP(name, func) __typeof__(name) M5OP_MERGE_TOKENS(name, _addr); \
+ __typeof__(name) M5OP_MERGE_TOKENS(name, _semi);
+M5OP_FOREACH
+#undef M5OP
+
 #ifdef __cplusplus
 }
 #endif

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I925e3af7bd6cb23e06fb744d453153323afb9310
Gerrit-Change-Number: 36896
Gerrit-PatchSet: 5
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Jason Lowe-Power 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: util: add update-copyright utility to update copyright on commits

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35535 )


Change subject: util: add update-copyright utility to update copyright on  
commits

..

util: add update-copyright utility to update copyright on commits

The utility can automatically update copyright for the chosen
organization on all files touched in the selected range of git commits.

Change-Id: I4e1803e53f4530f88fb344f56e08ea29fbfcd41d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35535
Reviewed-by: Daniel Carvalho 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M CONTRIBUTING.md
A util/update-copyright.py
A util/update_copyright/__init__.py
A util/update_copyright/requirements.txt
A util/update_copyright/test/__init__.py
A util/update_copyright/test/test_copyright.py
6 files changed, 319 insertions(+), 1 deletion(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
index 10a026e..bdbcc2d 100644
--- a/CONTRIBUTING.md
+++ b/CONTRIBUTING.md
@@ -203,7 +203,10 @@
 For significant changes, authors are encouraged to add copyright  
information
 and their names at the beginning of the file. The main purpose of the  
author
 names on the file is to track who is most knowledgeable about the file  
(e.g.,

-who has contributed a significant amount of code to the file).
+who has contributed a significant amount of code to the file). The
+`util/update-copyright.py` helper script can help to keep your copyright  
dates

+up-to-date when you make further changes to files which already have your
+copyright but with older dates.

 Note: If you do not follow these guidelines, the gerrit review site will
 automatically reject your patch.
diff --git a/util/update-copyright.py b/util/update-copyright.py
new file mode 100755
index 000..7cb0a75
--- /dev/null
+++ b/util/update-copyright.py
@@ -0,0 +1,141 @@
+#!/usr/bin/env python
+
+# Copyright (c) 2020 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import argparse
+import datetime
+import subprocess
+import sys
+
+import git_filter_repo
+
+import update_copyright
+
+parser = argparse.ArgumentParser(description=
+"""Update copyright headers on files of a range of commits.
+
+This can be used to easily update copyright headers at once on an entire
+patchset before submitting.
+
+Only files touched by the selected commits are updated.
+
+Only existing copyrights for the selected holder are updated, new
+notices are never automatically added if not already present.
+
+The size of the changes is not taken into account, every touched file gets
+updated. If you want to undo that for a certain file because the change to
+it is trivial, you need to manually rebase and undo the copyright change
+for that file.
+
+Example usage with an organization alias such as 

[gem5-dev] Change in gem5/gem5[develop]: misc: create C declarations for the _addr and _semi m5ops

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/36896 )



Change subject: misc: create C declarations for the _addr and _semi m5ops
..

misc: create C declarations for the _addr and _semi m5ops

Symbols such as m5_exit_addr are already present in the libm5.a, but were
not previously exposed in a header. This commit allows external C programs
to use those versions of the functions as well.

Change-Id: I925e3af7bd6cb23e06fb744d453153323afb9310
---
M include/gem5/m5ops.h
1 file changed, 7 insertions(+), 0 deletions(-)



diff --git a/include/gem5/m5ops.h b/include/gem5/m5ops.h
index fddbf53..377d648 100644
--- a/include/gem5/m5ops.h
+++ b/include/gem5/m5ops.h
@@ -35,6 +35,8 @@

 #include 

+#include 
+
 void m5_arm(uint64_t address);
 void m5_quiesce(void);
 void m5_quiesce_ns(uint64_t ns);
@@ -68,6 +70,11 @@
 void m5_se_syscall();
 void m5_se_page_fault();

+#define M5OP(name, func) __typeof__(name) name ## _addr; \
+ __typeof__(name) name ## _semi;
+M5OP_FOREACH
+#undef M5OP
+
 #ifdef __cplusplus
 }
 #endif

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[gem5-dev] Change in gem5/gem5[develop]: sim: create SERIALIZE_MAP and UNSERIALIZE_MAP

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/36135 )



Change subject: sim: create SERIALIZE_MAP and UNSERIALIZE_MAP
..

sim: create SERIALIZE_MAP and UNSERIALIZE_MAP

The motivation for those new methods is to prevent checkpoints from
breaking when new map entries are added.

Change-Id: I0ff8681498bcf669492e6b876ad385fda4673d77
JIRA: https://gem5.atlassian.net/browse/GEM5-661
---
M src/sim/serialize.hh
1 file changed, 57 insertions(+), 0 deletions(-)



diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh
index bbc91d7..6a78e05 100644
--- a/src/sim/serialize.hh
+++ b/src/sim/serialize.hh
@@ -52,6 +52,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 

 #include "base/bitunion.hh"
@@ -776,6 +777,46 @@
 void
 objParamIn(CheckpointIn , const std::string , SimObject * );

+/**
+ * @param names array of keys
+ * @param param array of values
+ * @param size size o fthe names and param arrays
+ *
+ * @ingroup api_serialize
+ */
+template 
+void
+mapParamOut(CheckpointOut , const char* base,
+const char* const names[], const T *param, unsigned size)
+{
+for (unsigned i = 0; i < size; ++i) {
+paramOut(os, csprintf("%s.%d", base, names[i]), param[i]);
+}
+}
+
+/**
+ * Restore a map structure. Keys missing from the checkpoint are ignored.
+ *
+ * @ingroup api_serialize
+ */
+template 
+void
+mapParamIn(CheckpointIn , const char* base,
+const char* const names[], T *param, unsigned size)
+{
+std::unordered_map name_to_index;
+for (size_t i = 0; i < size; i++) {
+name_to_index[names[i]] = i;
+}
+for (size_t i = 0; i < size; i++) {
+auto& key = names[i];
+T value;
+if (optParamIn(os, csprintf("%s.%s", base, key), value)) {
+param[name_to_index[key]] = value;
+}
+}
+}
+
 //
 // These macros are streamlined to use in serialize/unserialize
 // functions.  It's assumed that serialize() has a parameter 'os' for
@@ -907,4 +948,20 @@
 objptr = dynamic_cast(sptr);  \
 } while (0)

+/**
+ * \def SERIALIZE_MAP(member, names, size)
+ *
+ * @ingroup api_serialize
+ */
+#define SERIALIZE_MAP(member, names, size) \
+mapParamOut(cp, #member, names, member, size)
+
+/**
+ * \def UNSERIALIZE_MAP(member, names, size)
+ *
+ * @ingroup api_serialize
+ */
+#define UNSERIALIZE_MAP(member, names, size) \
+mapParamIn(cp, #member, names, member, size)
+
 #endif // __SERIALIZE_HH__

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: serialize miscregs as a map

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/36116 )



Change subject: arch-arm: serialize miscregs as a map
..

arch-arm: serialize miscregs as a map

This will prevent checkpoints from breaking on every miscreg addition.

Before this commit, miscregs were stored as an array:

[system.cpu.isa]
miscRegs=965 0 0 0 0 0 0 0 0 0 0 0 17895697 ...

and after this commit they are stored as a map:

[system.cpu.isa]
miscRegs.cpsr=965
miscRegs.spsr=0
miscRegs.spsr_fiq=0
miscRegs.spsr_irq=0
miscRegs.spsr_svc=0
miscRegs.spsr_mon=0
miscRegs.spsr_abt=0
miscRegs.spsr_hyp=0
miscRegs.spsr_und=0
miscRegs.elr_hyp=0
miscRegs.fpsid=0
miscRegs.fpscr=0
miscRegs.mvfr1=17895697

This follows a similar pattern to what was in use for the symbol table:

[system.workload]
symtab.size=10
symtab.addr_0=0
symtab.symbol_0=/tmp/ccPFSHJm.o
symtab.binding_0=1

Change-Id: I4c7206bd9ac1cfb81297d45c8117ff8ae675
---
M src/arch/arm/isa.cc
M src/sim/serialize.hh
2 files changed, 60 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 4e90dc8..788c549 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -2352,14 +2352,15 @@
 ISA::serialize(CheckpointOut ) const
 {
 DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
-SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
+SERIALIZE_MAP(miscRegs, miscRegName, NUM_PHYS_MISCREGS);
+mapParamOut(cp, "miscRegs", miscRegName, miscRegs, NUM_PHYS_MISCREGS);
 }

 void
 ISA::unserialize(CheckpointIn )
 {
 DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
-UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
+UNSERIALIZE_MAP(miscRegs, miscRegName, NUM_PHYS_MISCREGS);
 CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
 updateRegMap(tmp_cpsr);
 }
diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh
index bbc91d7..6a78e05 100644
--- a/src/sim/serialize.hh
+++ b/src/sim/serialize.hh
@@ -52,6 +52,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 

 #include "base/bitunion.hh"
@@ -776,6 +777,46 @@
 void
 objParamIn(CheckpointIn , const std::string , SimObject * );

+/**
+ * @param names array of keys
+ * @param param array of values
+ * @param size size o fthe names and param arrays
+ *
+ * @ingroup api_serialize
+ */
+template 
+void
+mapParamOut(CheckpointOut , const char* base,
+const char* const names[], const T *param, unsigned size)
+{
+for (unsigned i = 0; i < size; ++i) {
+paramOut(os, csprintf("%s.%d", base, names[i]), param[i]);
+}
+}
+
+/**
+ * Restore a map structure. Keys missing from the checkpoint are ignored.
+ *
+ * @ingroup api_serialize
+ */
+template 
+void
+mapParamIn(CheckpointIn , const char* base,
+const char* const names[], T *param, unsigned size)
+{
+std::unordered_map name_to_index;
+for (size_t i = 0; i < size; i++) {
+name_to_index[names[i]] = i;
+}
+for (size_t i = 0; i < size; i++) {
+auto& key = names[i];
+T value;
+if (optParamIn(os, csprintf("%s.%s", base, key), value)) {
+param[name_to_index[key]] = value;
+}
+}
+}
+
 //
 // These macros are streamlined to use in serialize/unserialize
 // functions.  It's assumed that serialize() has a parameter 'os' for
@@ -907,4 +948,20 @@
 objptr = dynamic_cast(sptr);  \
 } while (0)

+/**
+ * \def SERIALIZE_MAP(member, names, size)
+ *
+ * @ingroup api_serialize
+ */
+#define SERIALIZE_MAP(member, names, size) \
+mapParamOut(cp, #member, names, member, size)
+
+/**
+ * \def UNSERIALIZE_MAP(member, names, size)
+ *
+ * @ingroup api_serialize
+ */
+#define UNSERIALIZE_MAP(member, names, size) \
+mapParamIn(cp, #member, names, member, size)
+
 #endif // __SERIALIZE_HH__

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: move serialize and unserialize definition to cpp file

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/36115 )



Change subject: arch-arm: move serialize and unserialize definition to cpp  
file

..

arch-arm: move serialize and unserialize definition to cpp file

Change-Id: I9ac64184d3fe36617f474a714b228b55b9a90976
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
2 files changed, 18 insertions(+), 15 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 8ec2dc6..4e90dc8 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -2349,6 +2349,22 @@
 }

 void
+ISA::serialize(CheckpointOut ) const
+{
+DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
+SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
+}
+
+void
+ISA::unserialize(CheckpointIn )
+{
+DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
+UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
+CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
+updateRegMap(tmp_cpsr);
+}
+
+void
 ISA::addressTranslation64(TLB::ArmTranslationType tran_type,
 BaseTLB::Mode mode, Request::Flags flags, RegVal val)
 {
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 910dc2c..43ba8b3 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -810,21 +810,8 @@
 static void zeroSveVecRegUpperPart(VecRegContainer ,
unsigned eCount);

-void
-serialize(CheckpointOut ) const override
-{
-DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
-SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
-}
-
-void
-unserialize(CheckpointIn ) override
-{
-DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
-UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
-CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
-updateRegMap(tmp_cpsr);
-}
+void serialize(CheckpointOut ) const override;
+void unserialize(CheckpointIn ) override;

 void startup() override;


--
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[gem5-dev] Change in gem5/gem5[develop]: scons: make LDFLAGS_EXTRA take effect on partial links as well

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35995 )



Change subject: scons: make LDFLAGS_EXTRA take effect on partial links as  
well

..

scons: make LDFLAGS_EXTRA take effect on partial links as well

Before this patch, it would only be added to the final link, but this is
not what I would expect from the option.

After this change this for example, the --gold-linker option could have
been implemented with LDFLAGS_EXTRA, since gold fails if the partial links
are done with ld and the final link with gold.

Change-Id: I8bbebf65afbff83b512defc879b518e87c64c348
---
M SConstruct
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/SConstruct b/SConstruct
index 8e7ec34..81fdac0 100755
--- a/SConstruct
+++ b/SConstruct
@@ -332,6 +332,7 @@
 main['PSHLINKFLAGS'] =  
main.subst('${FILTER_PSHLINKFLAGS(SHLINKFLAGS)}')

 if GetOption('gold_linker'):
 main.Append(LINKFLAGS='-fuse-ld=gold')
+main.Append(LINKFLAGS='$LDFLAGS_EXTRA')
 main['PLINKFLAGS'] = main.get('LINKFLAGS')
 shared_partial_flags = ['-r', '-nostdlib']
 main.Append(PSHLINKFLAGS=shared_partial_flags)
@@ -1241,7 +1242,6 @@
 env.Append(CCFLAGS=['-msse2'])

 env.Append(CCFLAGS='$CCFLAGS_EXTRA')
-env.Append(LINKFLAGS='$LDFLAGS_EXTRA')

 # The src/SConscript file sets up the build rules in 'env' according
 # to the configured variables.  It returns a list of environments,

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[gem5-dev] Change in gem5/gem5[develop]: util: add update-copyright utility

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35535 )



Change subject: util: add update-copyright utility
..

util: add update-copyright utility

Only ARM copyright headers are implemented now, but the script is designed
to be easily generalizable by other organizations.

Change-Id: I4e1803e53f4530f88fb344f56e08ea29fbfcd41d
---
A util/update-copyright
1 file changed, 177 insertions(+), 0 deletions(-)



diff --git a/util/update-copyright b/util/update-copyright
new file mode 100755
index 000..7851646
--- /dev/null
+++ b/util/update-copyright
@@ -0,0 +1,177 @@
+#!/usr/bin/env python
+
+# Copyright (c) 2020 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import argparse
+import datetime
+import re
+
+import git_filter_repo
+
+parser = argparse.ArgumentParser(description=
+"""Update copyright headers on files of a range of commits.
+
+This can be used to easily update copyright headers at once on an entire
+patchset before submitting.
+
+Only files touched by the selected commits are updated.
+
+Example usage:
+
+```
+python3 -m pip install --user git-filter-repo
+./update-copyright HEAD~3 arm
+```
+
+The above would act on the 3 last commits (HEAD~2, HEAD~ and HEAD),
+leaving HEAD~3 unchanged.
+""",
+formatter_class=argparse.RawTextHelpFormatter,
+)
+parser.add_argument('--test',
+action='store_true',
+default=False,
+help="Run unit tests instead of running.")
+parser.add_argument('start',
+default=None,
+nargs='?',
+help="The commit before the last commit to be modified")
+parser.add_argument('org', default='arm', nargs='?', choices=('arm',),
+help="Organization to update the copyright for")
+args = parser.parse_args()
+
+update_arm_copyright_regexp = re.compile(
+b' Copyright \\(c\\) ([0-9,\- ]+) ARM Limited',
+re.IGNORECASE
+)
+
+update_arm_copyright_year_regexp = re.compile(b'(.*?)([0-9]+)$')
+
+def update_copyright_years(m, cur_year):
+'''
+Does e.g.: b'2016, 2018-2019' -> b'2016, 2018-2020'.
+
+:param m: match containing only the years part of the string
+:type m: re.Match
+:return: the new years part of the string
+:rtype: bytes
+'''
+cur_year_bytes = str(cur_year).encode()
+m = update_arm_copyright_year_regexp.match(m.group(1))
+years_prefix = m.group(1)
+old_year_bytes = m.group(2)
+old_year = int(old_year_bytes.decode())
+if old_year == cur_year:
+new_years_string = old_year_bytes
+elif old_year == cur_year - 1:
+if len(years_prefix) > 0 and years_prefix[-1:] == b'-':
+new_years_string = cur_year_bytes
+else:
+new_years_string = old_year_bytes + b'-' + cur_year_bytes
+else:
+new_years_string = old_year_bytes + b', ' + cur_year_bytes
+new_years_string = years_prefix + new_years_string

[gem5-dev] Change in gem5/gem5[develop]: sim: factor fs_workload address relocation

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35335 )



Change subject: sim: factor fs_workload address relocation
..

sim: factor fs_workload address relocation

The same operation was being done from three different places, this commit
factors them out with KernelWorkload::relocateAddr.

Also always call the function instead of using the member in case the
getter starts doing some extra logic later on.

Change-Id: Idc06ac9fd361c62dec3ef3d7db4d912068a28a88
---
M src/arch/arm/freebsd/fs_workload.cc
M src/arch/arm/fs_workload.cc
M src/arch/arm/linux/fs_workload.cc
M src/sim/kernel_workload.cc
M src/sim/kernel_workload.hh
5 files changed, 29 insertions(+), 23 deletions(-)



diff --git a/src/arch/arm/freebsd/fs_workload.cc  
b/src/arch/arm/freebsd/fs_workload.cc

index 080dc35..79bc5e6 100644
--- a/src/arch/arm/freebsd/fs_workload.cc
+++ b/src/arch/arm/freebsd/fs_workload.cc
@@ -81,7 +81,8 @@
 // to do this permanently, for but early bootup work
 // it is helpful.
 if (params()->early_kernel_symbols) {
-auto phys_globals =  
kernelObj->symtab().globals()->mask(_loadAddrMask);

+auto phys_globals = kernelObj->symtab().globals()->mask(
+loadAddrMask());
 kernelSymtab.insert(*phys_globals);
 Loader::debugSymbolTable.insert(*phys_globals);
 }
@@ -95,7 +96,7 @@
 // Kernel supports flattened device tree and dtb file specified.
 // Using Device Tree Blob to describe system configuration.
 inform("Loading DTB file: %s at address %#x\n", params()->dtb_filename,
-params()->atags_addr + _loadAddrOffset);
+params()->atags_addr + loadAddrOffset());

 auto *dtb_file = new ::Loader::DtbFile(params()->dtb_filename);

@@ -108,7 +109,7 @@
 bootReleaseAddr = ra & ~ULL(0x7F);

 dtb_file->buildImage().
-offset(params()->atags_addr + _loadAddrOffset).
+offset(params()->atags_addr + loadAddrOffset()).
 write(system->physProxy);
 delete dtb_file;

@@ -116,7 +117,7 @@
 for (auto *tc: system->threads) {
 tc->setIntReg(0, 0);
 tc->setIntReg(1, params()->machine_type);
-tc->setIntReg(2, params()->atags_addr + _loadAddrOffset);
+tc->setIntReg(2, params()->atags_addr + loadAddrOffset());
 }
 }

diff --git a/src/arch/arm/fs_workload.cc b/src/arch/arm/fs_workload.cc
index 0cafb1b..1fae3ab 100644
--- a/src/arch/arm/fs_workload.cc
+++ b/src/arch/arm/fs_workload.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013, 2015,2017-2019 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2015,2017-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -72,8 +72,7 @@
 FsWorkload::FsWorkload(Params *p) : KernelWorkload(*p)
 {
 if (kernelObj) {
-kernelEntry = (kernelObj->entryPoint() & loadAddrMask()) +
-loadAddrOffset();
+kernelEntry = relocateAddr(kernelObj->entryPoint());
 }

 bootLoaders.reserve(p->boot_loader.size());
diff --git a/src/arch/arm/linux/fs_workload.cc  
b/src/arch/arm/linux/fs_workload.cc

index 8aba285..dc36195 100644
--- a/src/arch/arm/linux/fs_workload.cc
+++ b/src/arch/arm/linux/fs_workload.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, 2016 ARM Limited
+ * Copyright (c) 2010-2013, 2016, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -76,7 +76,8 @@
 // to do this permanently, for but early bootup work
 // it is helpful.
 if (params()->early_kernel_symbols) {
-auto phys_globals =  
kernelObj->symtab().globals()->mask(_loadAddrMask);

+auto phys_globals = kernelObj->symtab().globals()->mask(
+loadAddrMask());
 kernelSymtab.insert(*phys_globals);
 Loader::debugSymbolTable.insert(*phys_globals);
 }
@@ -92,7 +93,7 @@
 // Kernel supports flattened device tree and dtb file specified.
 // Using Device Tree Blob to describe system configuration.
 inform("Loading DTB file: %s at address %#x\n",  
params()->dtb_filename,

-params()->atags_addr + _loadAddrOffset);
+params()->atags_addr + loadAddrOffset());

 auto *dtb_file = new ::Loader::DtbFile(params()->dtb_filename);

@@ -103,7 +104,7 @@
 }

 dtb_file->buildImage().
-offset(params()->atags_addr + _loadAddrOffset).
+offset(params()->atags_addr + loadAddrOffset()).
 write(system->physProxy);
 delete dtb_file;
 } else {
@@ -152,7 +153,7 @@
 DPRINTF(Loader, "Boot atags was %d bytes in total\n", size << 2);
 DDUMP(Loader, boot_data, size << 2);

-system->physProxy.writeBlob(params()->atags_addr + _loadAddrOffset,
+system->physProxy.writeBlob(params()->atags_addr +  

[gem5-dev] Change in gem5/gem5[develop]: cpu: make ExecSymbol show the symbol in addition to address

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35077 )


Change subject: cpu: make ExecSymbol show the symbol in addition to address
..

cpu: make ExecSymbol show the symbol in addition to address

Before this commit, ExecSymbol would show only the symbol and no address:

0: system.cpu: A0 T0 : @_kernel_flags_le_lo32+6:   mrs   x0, currentel

After this commit, it shows the symbol in addition to the address:

0: system.cpu: A0 T0 : 0x10 @_kernel_flags_le_lo32+6:   mrs   x0,  
currentel


Change-Id: I665802f50ce9aeac6bb9e174b5dd06196e757c60
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35077
Reviewed-by: Richard Cooper 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/exetrace.cc
1 file changed, 3 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Richard Cooper: Looks good to me, but someone else must approve
  kokoro: Regressions pass



diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index ca05041..69ee5cc 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -77,16 +77,15 @@

 Addr cur_pc = pc.instAddr();
 Loader::SymbolTable::const_iterator it;
+ccprintf(outs, "%#x", cur_pc);
 if (Debug::ExecSymbol && (!FullSystem || !inUserMode(thread)) &&
 (it = Loader::debugSymbolTable.findNearest(cur_pc)) !=
 Loader::debugSymbolTable.end()) {
 Addr delta = cur_pc - it->address;
 if (delta)
-ccprintf(outs, "@%s+%d", it->name, delta);
+ccprintf(outs, " @%s+%d", it->name, delta);
 else
-ccprintf(outs, "@%s", it->name);
-} else {
-ccprintf(outs, "%#x", cur_pc);
+ccprintf(outs, " @%s", it->name);
 }

 if (inst->isMicroop()) {

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I665802f50ce9aeac6bb9e174b5dd06196e757c60
Gerrit-Change-Number: 35077
Gerrit-PatchSet: 2
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: arm64 kernel offset into bootloader

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35078 )



Change subject: arch-arm: arm64 kernel offset into bootloader
..

arch-arm: arm64 kernel offset into bootloader

This gets Linux 5.8 booting, accounting for its TEXT_OFFSET change
in cfa7ede20f13.

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
commit/?h=v5.8=cfa7ede20f133cc81cef01dc3a516dda3a9721ee
https://lore.kernel.org/r/20200415082922.32709-1-a...@kernel.org

Change-Id: Ie22f7c44d5454249e73a0bae718b1b9cab3c
---
M src/dev/arm/RealView.py
M src/sim/kernel_workload.cc
M system/arm/bootloader/arm64/boot.S
M system/arm/bootloader/arm64/makefile
4 files changed, 26 insertions(+), 6 deletions(-)



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 9ab0472..4768724 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -646,8 +646,11 @@
 cpu.append(FdtPropertyStrings('enable-method', 'psci'))
 else:
 cpu.append(FdtPropertyStrings("enable-method", "spin-table"))
+# The kernel writes the entry addres of secondary CPUs to this
+# address before waking up secondary CPUs.
+# The gem5 bootloader then makes secondary CPUs jump to it.
 cpu.append(FdtPropertyWords("cpu-release-addr", \
-state.addrCells(0x8000fff8)))
+state.addrCells(0x87f8)))

 class VExpress_EMM(RealView):
 _mem_regions = [ AddrRange('2GB', size='2GB') ]
diff --git a/src/sim/kernel_workload.cc b/src/sim/kernel_workload.cc
index d144872..ef3e4ca 100644
--- a/src/sim/kernel_workload.cc
+++ b/src/sim/kernel_workload.cc
@@ -53,8 +53,11 @@
 // If load_addr_mask is set to 0x0, then calculate the smallest  
mask to
 // cover all kernel addresses so gem5 can relocate the kernel to a  
new

 // offset.
-if (_loadAddrMask == 0)
+if (_loadAddrMask == 0) {
 _loadAddrMask = mask(findMsbSet(_end - _start) + 1);
+// Make the very first address map exactly to our address  
offset.

+_loadAddrOffset -= (_start & _loadAddrMask);
+}

 image.move([this](Addr a) {
 return (a & _loadAddrMask) + _loadAddrOffset;
diff --git a/system/arm/bootloader/arm64/boot.S  
b/system/arm/bootloader/arm64/boot.S

index b3baa71..2b3e68f 100644
--- a/system/arm/bootloader/arm64/boot.S
+++ b/system/arm/bootloader/arm64/boot.S
@@ -153,7 +153,19 @@
  * Secondary CPUs
  */
 1: wfe
-ldrx4, =PHYS_OFFSET + 0xfff8
+/* The Linux kernel v5.8 and older writes the entry point address
+ * of the secondary CPU to this address, and does a SEV, waking up
+ * the secondary CPUs.
+ *
+ * gem5 informs the kernel the desired address via cpu-release-addr
+ * of the DTB.
+ *
+ * When this is first reached immediately after the bootloader  
starts,

+ * the value at that address must be 0, which is the default memory
+ * value set by gem5 for otherwise uninitialized memory, leading to
+ # WFE.
+ */
+ldrx4, =PHYS_OFFSET + DTB_OFFSET - 8
 ldr x4, [x4]
 cbzx4, 1b
 br x4  // branch to the given address
@@ -180,9 +192,10 @@
 /*
  * Primary CPU
  */
-ldrx0, =PHYS_OFFSET + 0x800 // device tree blob
-ldr x6, =PHYS_OFFSET + 0x8   // kernel start address
-br x6
+ldrx0, =PHYS_OFFSET + DTB_OFFSET// device tree blob
+ldr x6, =PHYS_OFFSET // kernel start address
+br x6
+.long  0x8  // default TEXT_OFFSET

 .ltorg

diff --git a/system/arm/bootloader/arm64/makefile  
b/system/arm/bootloader/arm64/makefile

index 2112b6e..2c59ea0 100644
--- a/system/arm/bootloader/arm64/makefile
+++ b/system/arm/bootloader/arm64/makefile
@@ -35,6 +35,7 @@

 CFLAGS = -march=armv8-a
 CPPFLAGS = -DPHYS_OFFSET=0x8000 \
+   -DDTB_OFFSET=0x800 \
   -DUART_BASE=0x1c09 -DSYSREGS_BASE=0x1c01 \
   -Dkernel=0x8008 \
   -Dmbox=0x8000fff8 -Ddtb=0x8100

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie22f7c44d5454249e73a0bae718b1b9cab3c
Gerrit-Change-Number: 35078
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: cpu: make ExecSymbol show the symbol in addition to address

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35077 )



Change subject: cpu: make ExecSymbol show the symbol in addition to address
..

cpu: make ExecSymbol show the symbol in addition to address

Before this commit, ExecSymbol would show only the symbol and no address:

0: system.cpu: A0 T0 : @_kernel_flags_le_lo32+6:   mrs   x0, currentel

After this commit, it shows the symbol in addition to the address:

0: system.cpu: A0 T0 : 0x10 @_kernel_flags_le_lo32+6:   mrs   x0,  
currentel


Change-Id: I665802f50ce9aeac6bb9e174b5dd06196e757c60
---
M src/cpu/exetrace.cc
1 file changed, 3 insertions(+), 4 deletions(-)



diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index ca05041..69ee5cc 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -77,16 +77,15 @@

 Addr cur_pc = pc.instAddr();
 Loader::SymbolTable::const_iterator it;
+ccprintf(outs, "%#x", cur_pc);
 if (Debug::ExecSymbol && (!FullSystem || !inUserMode(thread)) &&
 (it = Loader::debugSymbolTable.findNearest(cur_pc)) !=
 Loader::debugSymbolTable.end()) {
 Addr delta = cur_pc - it->address;
 if (delta)
-ccprintf(outs, "@%s+%d", it->name, delta);
+ccprintf(outs, " @%s+%d", it->name, delta);
 else
-ccprintf(outs, "@%s", it->name);
-} else {
-ccprintf(outs, "%#x", cur_pc);
+ccprintf(outs, " @%s", it->name);
 }

 if (inst->isMicroop()) {

--
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: arm64 kernel offset into bootloader

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35076 )



Change subject: arch-arm: arm64 kernel offset into bootloader
..

arch-arm: arm64 kernel offset into bootloader

This gets Linux 5.8 booting, accounting for its TEXT_OFFSET change
in cfa7ede20f13.

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
commit/?h=v5.8=cfa7ede20f133cc81cef01dc3a516dda3a9721ee
https://lore.kernel.org/r/20200415082922.32709-1-a...@kernel.org

Change-Id: If70bea9690be04b84e6040e256a9b03e46710e10
---
M src/dev/arm/RealView.py
M src/sim/kernel_workload.cc
M system/arm/bootloader/arm64/boot.S
M system/arm/bootloader/arm64/makefile
4 files changed, 26 insertions(+), 6 deletions(-)



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 9ab0472..4768724 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -646,8 +646,11 @@
 cpu.append(FdtPropertyStrings('enable-method', 'psci'))
 else:
 cpu.append(FdtPropertyStrings("enable-method", "spin-table"))
+# The kernel writes the entry addres of secondary CPUs to this
+# address before waking up secondary CPUs.
+# The gem5 bootloader then makes secondary CPUs jump to it.
 cpu.append(FdtPropertyWords("cpu-release-addr", \
-state.addrCells(0x8000fff8)))
+state.addrCells(0x87f8)))

 class VExpress_EMM(RealView):
 _mem_regions = [ AddrRange('2GB', size='2GB') ]
diff --git a/src/sim/kernel_workload.cc b/src/sim/kernel_workload.cc
index d144872..ef3e4ca 100644
--- a/src/sim/kernel_workload.cc
+++ b/src/sim/kernel_workload.cc
@@ -53,8 +53,11 @@
 // If load_addr_mask is set to 0x0, then calculate the smallest  
mask to
 // cover all kernel addresses so gem5 can relocate the kernel to a  
new

 // offset.
-if (_loadAddrMask == 0)
+if (_loadAddrMask == 0) {
 _loadAddrMask = mask(findMsbSet(_end - _start) + 1);
+// Make the very first address map exactly to our address  
offset.

+_loadAddrOffset -= (_start & _loadAddrMask);
+}

 image.move([this](Addr a) {
 return (a & _loadAddrMask) + _loadAddrOffset;
diff --git a/system/arm/bootloader/arm64/boot.S  
b/system/arm/bootloader/arm64/boot.S

index b3baa71..2b3e68f 100644
--- a/system/arm/bootloader/arm64/boot.S
+++ b/system/arm/bootloader/arm64/boot.S
@@ -153,7 +153,19 @@
  * Secondary CPUs
  */
 1: wfe
-ldrx4, =PHYS_OFFSET + 0xfff8
+/* The Linux kernel v5.8 and older writes the entry point address
+ * of the secondary CPU to this address, and does a SEV, waking up
+ * the secondary CPUs.
+ *
+ * gem5 informs the kernel the desired address via cpu-release-addr
+ * of the DTB.
+ *
+ * When this is first reached immediately after the bootloader  
starts,

+ * the value at that address must be 0, which is the default memory
+ * value set by gem5 for otherwise uninitialized memory, leading to
+ # WFE.
+ */
+ldrx4, =PHYS_OFFSET + DTB_OFFSET - 8
 ldr x4, [x4]
 cbzx4, 1b
 br x4  // branch to the given address
@@ -180,9 +192,10 @@
 /*
  * Primary CPU
  */
-ldrx0, =PHYS_OFFSET + 0x800 // device tree blob
-ldr x6, =PHYS_OFFSET + 0x8   // kernel start address
-br x6
+ldrx0, =PHYS_OFFSET + DTB_OFFSET// device tree blob
+ldr x6, =PHYS_OFFSET // kernel start address
+br x6
+.long  0x8  // default TEXT_OFFSET

 .ltorg

diff --git a/system/arm/bootloader/arm64/makefile  
b/system/arm/bootloader/arm64/makefile

index 2112b6e..2c59ea0 100644
--- a/system/arm/bootloader/arm64/makefile
+++ b/system/arm/bootloader/arm64/makefile
@@ -35,6 +35,7 @@

 CFLAGS = -march=armv8-a
 CPPFLAGS = -DPHYS_OFFSET=0x8000 \
+   -DDTB_OFFSET=0x800 \
   -DUART_BASE=0x1c09 -DSYSREGS_BASE=0x1c01 \
   -Dkernel=0x8008 \
   -Dmbox=0x8000fff8 -Ddtb=0x8100

--
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Gerrit-Branch: develop
Gerrit-Change-Id: If70bea9690be04b84e6040e256a9b03e46710e10
Gerrit-Change-Number: 35076
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: util: add pkg-config to ubuntu all-dependencies Dockerfiles

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34777 )


Change subject: util: add pkg-config to ubuntu all-dependencies Dockerfiles
..

util: add pkg-config to ubuntu all-dependencies Dockerfiles

Without this, HDF5 is not built, e.g. a run such as
http://jenkins.gem5.org/job/Nightly/68/console contains:

Checking for hdf5-serial using pkg-config... pkg-config not found
Checking for hdf5 using pkg-config... pkg-config not found
Checking for H5Fcreate("", 0, 0, 0) in C library hdf5... (cached) no
Warning: Couldn't find any HDF5 C++ libraries. Disabling
 HDF5 support.

This is done to increase coverage a bit, and serve as dependency
documentation to users.

Change-Id: Ibf820a3aa76c291201646924ee181615a162
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34777
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile
M util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile
2 files changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile  
b/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile

index 282805d..1259f2e 100644
--- a/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile
+++ b/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile
@@ -31,4 +31,4 @@
 RUN apt -y install build-essential git m4 scons zlib1g zlib1g-dev \
 libprotobuf-dev protobuf-compiler libprotoc-dev  
libgoogle-perftools-dev \
 python-dev python python-six doxygen libboost-all-dev  
libhdf5-serial-dev \

-python-pydot libpng-dev libelf-dev
+python-pydot libpng-dev libelf-dev pkg-config
diff --git a/util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile  
b/util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile

index 283d356..3facf7e 100644
--- a/util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile
+++ b/util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile
@@ -32,4 +32,4 @@
 RUN apt -y install build-essential git m4 scons zlib1g zlib1g-dev \
 libprotobuf-dev protobuf-compiler libprotoc-dev  
libgoogle-perftools-dev \

 python3-dev python3-six python-is-python3 doxygen libboost-all-dev \
-libhdf5-serial-dev python3-pydot libpng-dev libelf-dev
+libhdf5-serial-dev python3-pydot libpng-dev libelf-dev pkg-config

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibf820a3aa76c291201646924ee181615a162
Gerrit-Change-Number: 34777
Gerrit-PatchSet: 3
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: util: add pkg-config to ubuntu-20.04_all-dependencies/Dockerfile

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34777 )



Change subject: util: add pkg-config to  
ubuntu-20.04_all-dependencies/Dockerfile

..

util: add pkg-config to ubuntu-20.04_all-dependencies/Dockerfile

Without this, HDF5 is not built, e.g. a run such as
http://jenkins.gem5.org/job/Nightly/68/console contains:

Checking for hdf5-serial using pkg-config... pkg-config not found
Checking for hdf5 using pkg-config... pkg-config not found
Checking for H5Fcreate("", 0, 0, 0) in C library hdf5... (cached) no
Warning: Couldn't find any HDF5 C++ libraries. Disabling
 HDF5 support.

This is done to increase coverage a bit, and serve as dependency
documentation to users.

Change-Id: Ibf820a3aa76c291201646924ee181615a162
---
M util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile  
b/util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile

index 283d356..3facf7e 100644
--- a/util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile
+++ b/util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile
@@ -32,4 +32,4 @@
 RUN apt -y install build-essential git m4 scons zlib1g zlib1g-dev \
 libprotobuf-dev protobuf-compiler libprotoc-dev  
libgoogle-perftools-dev \

 python3-dev python3-six python-is-python3 doxygen libboost-all-dev \
-libhdf5-serial-dev python3-pydot libpng-dev libelf-dev
+libhdf5-serial-dev python3-pydot libpng-dev libelf-dev pkg-config

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibf820a3aa76c291201646924ee181615a162
Gerrit-Change-Number: 34777
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: tests: cleanup all SE tests previously moved to gem5-resources

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34476 )


Change subject: tests: cleanup all SE tests previously moved to  
gem5-resources

..

tests: cleanup all SE tests previously moved to gem5-resources

The move was done at:
https://gem5-review.googlesource.com/c/public/gem5-resources/+/32074

All files keep exact same name, or are obvious renames like underscore to
-. threads/ is the only non obvious and remaps to src/simple/std_thread.cpp

Only m5-exit is left because it does squashfs generation which wasn't yet
moved.

Change-Id: I72ad104c9311c2f81af49458bdd44e24a6bafc0a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34476
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
D tests/test-progs/chdir-print/Makefile
D tests/test-progs/chdir-print/README.txt
D tests/test-progs/chdir-print/chdir-print.c
D tests/test-progs/mwait/Makefile
D tests/test-progs/mwait/mwait.c
D tests/test-progs/page-access-wrap/Makefile
D tests/test-progs/page-access-wrap/page-access-wrap.cpp
D tests/test-progs/stack-print/bin/x86/linux/stack-print
D tests/test-progs/stack-print/src/stack-print.c
9 files changed, 0 insertions(+), 507 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/test-progs/chdir-print/Makefile  
b/tests/test-progs/chdir-print/Makefile

deleted file mode 100644
index 6a357d5..000
--- a/tests/test-progs/chdir-print/Makefile
+++ /dev/null
@@ -1,20 +0,0 @@
-
-CPP := g++
-
-TEST_OBJS := chdir-print.o
-TEST_PROGS := $(TEST_OBJS:.o=)
-
-#  Rules  
==

-
-.PHONY: default clean
-
-default: $(TEST_PROGS)
-
-clean:
-   $(RM)  $(TEST_OBJS) $(TEST_PROGS)
-
-$(TEST_PROGS): $(TEST_OBJS)
-   $(CPP)  -static -o $@  $@.o
-
-%.o: %.c Makefile
-   $(CPP) -c -o $@ $*.c -msse3
diff --git a/tests/test-progs/chdir-print/README.txt  
b/tests/test-progs/chdir-print/README.txt

deleted file mode 100644
index b1e9213..000
--- a/tests/test-progs/chdir-print/README.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-# example test compile and run parameters
-# Note: the absolute path to the chdir-print binary should be specified
-# in the run command even if running from the same folder. This is needed
-# because chdir is executed before triggering a clone for the file read,
-# and the cloned process won't be able to find the executable if a relative
-# path is provided.
-
-# compile examples
-scons --default=X86 ./build/X86/gem5.opt PROTOCOL=MOESI_hammer
-scons --default=X86 ./build/X86/gem5.opt PROTOCOL=MESI_Three_Level
-
-# run parameters
-/build/X86/gem5.opt /configs/example/se.py -c  
/tests/test-progs/chdir-print/chdir-print -n2 --ruby

-
-
-# example successful output for MESI_Three_Level:
-
-<...>
-
- REAL SIMULATION 
-info: Entering event queue @ 0.  Starting simulation...
-warn: Replacement policy updates recently became the responsibility of  
SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
-cwd:  
/proj/research_simu/users/jalsop/gem5-mem_dif_debug/tests/test-progs/chdir-print/

-cwd: /proc
-
-<...>
-
-processor   : 0
-vendor_id   : Generic
-cpu family  : 0
-model   : 0
-model name  : Generic
-stepping: 0
-cpu MHz : 2000
-cache size: : 2048K
-physical id : 0
-siblings: 2
-core id : 0
-cpu cores   : 2
-fpu : yes
-fpu exception   : yes
-cpuid level : 1
-wp  : yes
-flags   : fpu
-cache alignment : 64
-
-processor   : 1
-vendor_id   : Generic
-cpu family  : 0
-model   : 0
-model name  : Generic
-stepping: 0
-cpu MHz : 2000
-cache size: : 2048K
-physical id : 0
-siblings: 2
-core id : 1
-cpu cores   : 2
-fpu : yes
-fpu exception   : yes
-cpuid level : 1
-wp  : yes
-flags   : fpu
-cache alignment : 64
-
-SUCCESS
-Exiting @ tick 2694923000 because exiting with last active thread context
diff --git a/tests/test-progs/chdir-print/chdir-print.c  
b/tests/test-progs/chdir-print/chdir-print.c

deleted file mode 100644
index 71747b6..000
--- a/tests/test-progs/chdir-print/chdir-print.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * For use for simulation and test purposes only
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are  
met:

- *
- * 1. Redistributions of source code must retain the above copyright  
notice,

- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright  
notice,
- * this list of conditions and 

[gem5-dev] Change in gem5/gem5[develop]: tests: cleanup all SE tests previously moved to gem5-resources

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34476 )



Change subject: tests: cleanup all SE tests previously moved to  
gem5-resources

..

tests: cleanup all SE tests previously moved to gem5-resources

The move was done at:
https://gem5-review.googlesource.com/c/public/gem5-resources/+/32074

All files keep exact same name, or are obvious renames like underscore to
-. threads/ is the only non obvious and remaps to src/simple/std_thread.cpp

Only m5-exit is left because it does squashfs generation which wasn't yet
moved.

Change-Id: I72ad104c9311c2f81af49458bdd44e24a6bafc0a
---
D tests/test-progs/chdir-print/Makefile
D tests/test-progs/chdir-print/README.txt
D tests/test-progs/chdir-print/chdir-print.c
D tests/test-progs/hello/.gitignore
D tests/test-progs/hello/bin/arm/linux/hello
D tests/test-progs/hello/bin/riscv/linux/hello
D tests/test-progs/hello/bin/x86/linux/hello
D tests/test-progs/hello/bin/x86/linux/hello32
D tests/test-progs/hello/src/Makefile.arm
D tests/test-progs/hello/src/Makefile.mips
D tests/test-progs/hello/src/Makefile.x86
D tests/test-progs/hello/src/hello.c
D tests/test-progs/mwait/Makefile
D tests/test-progs/mwait/mwait.c
D tests/test-progs/page-access-wrap/Makefile
D tests/test-progs/page-access-wrap/page-access-wrap.cpp
D tests/test-progs/stack-print/bin/x86/linux/stack-print
D tests/test-progs/stack-print/src/stack-print.c
D tests/test-progs/threads/bin/x86/linux/threads
D tests/test-progs/threads/src/Makefile
D tests/test-progs/threads/src/threads.cpp
21 files changed, 0 insertions(+), 724 deletions(-)



diff --git a/tests/test-progs/chdir-print/Makefile  
b/tests/test-progs/chdir-print/Makefile

deleted file mode 100644
index 6a357d5..000
--- a/tests/test-progs/chdir-print/Makefile
+++ /dev/null
@@ -1,20 +0,0 @@
-
-CPP := g++
-
-TEST_OBJS := chdir-print.o
-TEST_PROGS := $(TEST_OBJS:.o=)
-
-#  Rules  
==

-
-.PHONY: default clean
-
-default: $(TEST_PROGS)
-
-clean:
-   $(RM)  $(TEST_OBJS) $(TEST_PROGS)
-
-$(TEST_PROGS): $(TEST_OBJS)
-   $(CPP)  -static -o $@  $@.o
-
-%.o: %.c Makefile
-   $(CPP) -c -o $@ $*.c -msse3
diff --git a/tests/test-progs/chdir-print/README.txt  
b/tests/test-progs/chdir-print/README.txt

deleted file mode 100644
index b1e9213..000
--- a/tests/test-progs/chdir-print/README.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-# example test compile and run parameters
-# Note: the absolute path to the chdir-print binary should be specified
-# in the run command even if running from the same folder. This is needed
-# because chdir is executed before triggering a clone for the file read,
-# and the cloned process won't be able to find the executable if a relative
-# path is provided.
-
-# compile examples
-scons --default=X86 ./build/X86/gem5.opt PROTOCOL=MOESI_hammer
-scons --default=X86 ./build/X86/gem5.opt PROTOCOL=MESI_Three_Level
-
-# run parameters
-/build/X86/gem5.opt /configs/example/se.py -c  
/tests/test-progs/chdir-print/chdir-print -n2 --ruby

-
-
-# example successful output for MESI_Three_Level:
-
-<...>
-
- REAL SIMULATION 
-info: Entering event queue @ 0.  Starting simulation...
-warn: Replacement policy updates recently became the responsibility of  
SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
-cwd:  
/proj/research_simu/users/jalsop/gem5-mem_dif_debug/tests/test-progs/chdir-print/

-cwd: /proc
-
-<...>
-
-processor   : 0
-vendor_id   : Generic
-cpu family  : 0
-model   : 0
-model name  : Generic
-stepping: 0
-cpu MHz : 2000
-cache size: : 2048K
-physical id : 0
-siblings: 2
-core id : 0
-cpu cores   : 2
-fpu : yes
-fpu exception   : yes
-cpuid level : 1
-wp  : yes
-flags   : fpu
-cache alignment : 64
-
-processor   : 1
-vendor_id   : Generic
-cpu family  : 0
-model   : 0
-model name  : Generic
-stepping: 0
-cpu MHz : 2000
-cache size: : 2048K
-physical id : 0
-siblings: 2
-core id : 1
-cpu cores   : 2
-fpu : yes
-fpu exception   : yes
-cpuid level : 1
-wp  : yes
-flags   : fpu
-cache alignment : 64
-
-SUCCESS
-Exiting @ tick 2694923000 because exiting with last active thread context
diff --git a/tests/test-progs/chdir-print/chdir-print.c  
b/tests/test-progs/chdir-print/chdir-print.c

deleted file mode 100644
index 71747b6..000
--- a/tests/test-progs/chdir-print/chdir-print.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * For use for simulation and test purposes only
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are  

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: fix KVM build due to missing ArmISA namespace

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34475 )



Change subject: arch-arm: fix KVM build due to missing ArmISA namespace
..

arch-arm: fix KVM build due to missing ArmISA namespace

The build was failing with:

arch/arm/kvm/armv8_cpu.hh:96:35: error: 'IntRegIndex' has not been declared

and other similar errors.

Change-Id: I15ebf0beb17a499585b409a431700e551a61a9ee
---
M src/arch/arm/kvm/armv8_cpu.hh
M src/arch/arm/kvm/base_cpu.cc
2 files changed, 5 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/kvm/armv8_cpu.hh b/src/arch/arm/kvm/armv8_cpu.hh
index 9870510..62ee5d6 100644
--- a/src/arch/arm/kvm/armv8_cpu.hh
+++ b/src/arch/arm/kvm/armv8_cpu.hh
@@ -45,6 +45,8 @@
 #include "arch/arm/kvm/base_cpu.hh"
 #include "arch/arm/miscregs.hh"

+using namespace ArmISA;
+
 struct ArmV8KvmCPUParams;

 /**
@@ -93,7 +95,7 @@
   protected:
 /** Mapping between integer registers in gem5 and KVM */
 struct IntRegInfo {
-IntRegInfo(uint64_t _kvm, IntRegIndex _idx, const char *_name)
+IntRegInfo(uint64_t _kvm, ArmISA::IntRegIndex _idx, const char  
*_name)

 : kvm(_kvm), idx(_idx), name(_name) {}

 /** Register index in KVM */
diff --git a/src/arch/arm/kvm/base_cpu.cc b/src/arch/arm/kvm/base_cpu.cc
index 04c5d0f..6fd2651 100644
--- a/src/arch/arm/kvm/base_cpu.cc
+++ b/src/arch/arm/kvm/base_cpu.cc
@@ -45,6 +45,8 @@
 #include "params/BaseArmKvmCPU.hh"
 #include "params/GenericTimer.hh"

+using namespace ArmISA;
+
 #define INTERRUPT_ID(type, vcpu, irq) (\
 ((type) << KVM_ARM_IRQ_TYPE_SHIFT) |   \
 ((vcpu) << KVM_ARM_IRQ_VCPU_SHIFT) |   \

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I15ebf0beb17a499585b409a431700e551a61a9ee
Gerrit-Change-Number: 34475
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: tests: ignore 32-bit arm dual linux boot tests

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33015 )


Change subject: tests: ignore 32-bit arm dual linux boot tests
..

tests: ignore 32-bit arm dual linux boot tests

As mentioned on the JIRA issue, uncacheable requests done after
cacheable requests had been done to the address make the cache writeback
and write trash data to memory.

We believe that the kernel must be doing earlier invalidation by set and
way earlier on to prevent this, but that is not implemented in gem5 yet.

The problem can be worked around by booting in atomic without caches and
checkpointing after init, because uncacheable accesses are only done on
early stages of CPU bringup, which is the more common use case anyways.

The aarch64 Linux kernel developers have stated that set and way
invalidates are not going to be used in aarch64, which further reduces the
importance of implementing this immediatly

JIRA: https://gem5.atlassian.net/browse/GEM5-640
Change-Id: Ieba31e707dcc09693d7a87ed9d51c3d1ffa3abe0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33015
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Giacomo Travaglini 
Maintainer: Jason Lowe-Power 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M tests/gem5/fs/linux/arm/test.py
1 file changed, 7 insertions(+), 5 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/gem5/fs/linux/arm/test.py  
b/tests/gem5/fs/linux/arm/test.py

index 39cb011..d68e434 100644
--- a/tests/gem5/fs/linux/arm/test.py
+++ b/tests/gem5/fs/linux/arm/test.py
@@ -53,17 +53,13 @@

 arm_fs_long_tests = [
 'realview-simple-atomic',
-'realview-simple-atomic-dual',
 'realview-simple-atomic-checkpoint',
 'realview-simple-timing',
-'realview-simple-timing-dual',
 'realview-switcheroo-atomic',
 'realview-switcheroo-timing',
 'realview-o3',
 'realview-o3-checker',
-'realview-o3-dual',
 'realview-minor',
-'realview-minor-dual',
 'realview-switcheroo-noncaching-timing',
 'realview-switcheroo-o3',
 'realview-switcheroo-full',
@@ -75,9 +71,15 @@
 'realview64-switcheroo-o3',
 'realview64-switcheroo-full',
 'realview-simple-timing-ruby',
-'realview-simple-timing-dual-ruby',
 'realview64-simple-timing-ruby',
 'realview64-simple-timing-dual-ruby',
+
+# https://gem5.atlassian.net/browse/GEM5-640
+#'realview-simple-atomic-dual',
+#'realview-simple-timing-dual',
+#'realview-o3-dual',
+#'realview-minor-dual',
+#'realview-simple-timing-dual-ruby',
 ]

 tarball = 'aarch-system-201901106.tar.bz2'

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ieba31e707dcc09693d7a87ed9d51c3d1ffa3abe0
Gerrit-Change-Number: 33015
Gerrit-PatchSet: 4
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests: ignore 32-bit arm dual linux boot tests

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33015 )



Change subject: tests: ignore 32-bit arm dual linux boot tests
..

tests: ignore 32-bit arm dual linux boot tests

As mentioned on the JIRA issue, uncacheable requests done after
cacheable requests had been done to the address make the cache writeback
and write trash data to memory.

We believe that the kernel must be doing earlier invalidation by set and
way earlier on to prevent this, but that is not implemented in gem5 yet.

The problem can be worked around by booting in atomic without caches and
checkpointing after init, because uncacheable accesses are only done on
early stages of CPU bringup, which is the more common use case anyways.

The aarch64 Linux kernel developers have stated that set and way
invalidates are not going to be used in aarch64, which further reduces the
importance of implementing this immediatly

JIRA: https://gem5.atlassian.net/browse/GEM5-640
Change-Id: Ieba31e707dcc09693d7a87ed9d51c3d1ffa3abe0
---
M tests/gem5/.testignore
1 file changed, 5 insertions(+), 0 deletions(-)



diff --git a/tests/gem5/.testignore b/tests/gem5/.testignore
index 08afde7..6228ad2 100644
--- a/tests/gem5/.testignore
+++ b/tests/gem5/.testignore
@@ -1,4 +1,9 @@
+realview-minor-dual-ARM-x86_64-opt
 realview-o3-checker-ARM-x86_64-opt
+realview-o3-dual-ARM-x86_64-opt
+realview-simple-atomic-dual-ARM-x86_64-opt
+realview-simple-timing-dual-ARM-x86_64-opt
+realview-simple-timing-dual-ruby-ARM-x86_64-opt
 realview64-o3-checker-ARM-x86_64-opt
 test-atomic-DerivO3CPU-SPARC-aarch64-debug
 test-atomic-DerivO3CPU-SPARC-aarch64-fast

--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ieba31e707dcc09693d7a87ed9d51c3d1ffa3abe0
Gerrit-Change-Number: 33015
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: tests: sort testignore

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33014 )



Change subject: tests: sort testignore
..

tests: sort testignore

It makes it easier to spot if you are adding duplicates or not.

Change-Id: I8381fd6e1535e978eeb2a19597f5f716f2aec906
---
M tests/gem5/.testignore
1 file changed, 109 insertions(+), 109 deletions(-)



diff --git a/tests/gem5/.testignore b/tests/gem5/.testignore
index dfca4e9..08afde7 100644
--- a/tests/gem5/.testignore
+++ b/tests/gem5/.testignore
@@ -1,111 +1,111 @@
-test-insttest-rv64a-linux-MinorCPU-RISCV-x86_64-opt
-test-insttest-rv64c-linux-MinorCPU-RISCV-x86_64-opt
-test-insttest-rv64d-linux-MinorCPU-RISCV-x86_64-opt
-test-insttest-rv64f-linux-MinorCPU-RISCV-x86_64-opt
-test-insttest-rv64i-linux-MinorCPU-RISCV-x86_64-opt
-test-insttest-rv64m-linux-MinorCPU-RISCV-x86_64-opt
-test-insttest-rv64i-linux-AtomicSimpleCPU-RISCV-x86_64-opt
-test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-x86_64-opt
-test-insttest-rv64i-linux-DerivO3CPU-RISCV-x86_64-opt
-test-insttest-linux-AtomicSimpleCPU-SPARC-x86_64-opt
-test-insttest-linux-TimingSimpleCPU-SPARC-x86_64-opt
-test-insttest-rv64a-linux-MinorCPU-RISCV-x86_64-debug
-test-insttest-rv64c-linux-MinorCPU-RISCV-x86_64-debug
-test-insttest-rv64d-linux-MinorCPU-RISCV-x86_64-debug
-test-insttest-rv64f-linux-MinorCPU-RISCV-x86_64-debug
-test-insttest-rv64i-linux-MinorCPU-RISCV-x86_64-debug
-test-insttest-rv64m-linux-MinorCPU-RISCV-x86_64-debug
-test-insttest-rv64i-linux-AtomicSimpleCPU-RISCV-x86_64-debug
-test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-x86_64-debug
-test-insttest-rv64i-linux-DerivO3CPU-RISCV-x86_64-debug
-test-insttest-linux-AtomicSimpleCPU-SPARC-x86_64-debug
-test-insttest-linux-TimingSimpleCPU-SPARC-x86_64-debug
-test-insttest-rv64i-linux-MinorCPU-RISCV-x86_64-fast
-test-insttest-rv64i-linux-AtomicSimpleCPU-RISCV-x86_64-fast
-test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-x86_64-fast
-test-insttest-rv64i-linux-DerivO3CPU-RISCV-x86_64-fast
-test-insttest-linux-AtomicSimpleCPU-SPARC-x86_64-fast
-test-insttest-linux-TimingSimpleCPU-SPARC-x86_64-fast
-test-insttest-rv64a-linux-MinorCPU-RISCV-aarch64-opt
-test-insttest-rv64c-linux-MinorCPU-RISCV-aarch64-opt
-test-insttest-rv64d-linux-MinorCPU-RISCV-aarch64-opt
-test-insttest-rv64f-linux-MinorCPU-RISCV-aarch64-opt
-test-insttest-rv64i-linux-MinorCPU-RISCV-aarch64-opt
-test-insttest-rv64m-linux-MinorCPU-RISCV-aarch64-opt
-test-insttest-rv64i-linux-AtomicSimpleCPU-RISCV-aarch64-opt
-test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-aarch64-opt
-test-insttest-rv64i-linux-DerivO3CPU-RISCV-aarch64-opt
-test-insttest-linux-AtomicSimpleCPU-SPARC-aarch64-opt
-test-insttest-linux-TimingSimpleCPU-SPARC-aarch64-opt
-test-insttest-rv64a-linux-MinorCPU-RISCV-aarch64-debug
-test-insttest-rv64c-linux-MinorCPU-RISCV-aarch64-debug
-test-insttest-rv64d-linux-MinorCPU-RISCV-aarch64-debug
-test-insttest-rv64f-linux-MinorCPU-RISCV-aarch64-debug
-test-insttest-rv64i-linux-MinorCPU-RISCV-aarch64-debug
-test-insttest-rv64m-linux-MinorCPU-RISCV-aarch64-debug
-test-insttest-rv64i-linux-AtomicSimpleCPU-RISCV-aarch64-debug
-test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-aarch64-debug
-test-insttest-rv64i-linux-DerivO3CPU-RISCV-aarch64-debug
-test-insttest-linux-AtomicSimpleCPU-SPARC-aarch64-debug
-test-insttest-linux-TimingSimpleCPU-SPARC-aarch64-debug
-test-insttest-rv64a-linux-MinorCPU-RISCV-aarch64-fast
-test-insttest-rv64c-linux-MinorCPU-RISCV-aarch64-fast
-test-insttest-rv64d-linux-MinorCPU-RISCV-aarch64-fast
-test-insttest-rv64f-linux-MinorCPU-RISCV-aarch64-fast
-test-insttest-rv64i-linux-MinorCPU-RISCV-aarch64-fast
-test-insttest-rv64m-linux-MinorCPU-RISCV-aarch64-fast
-test-insttest-rv64i-linux-AtomicSimpleCPU-RISCV-aarch64-fast
-test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-aarch64-fast
-test-insttest-rv64i-linux-DerivO3CPU-RISCV-aarch64-fast
-test-insttest-linux-AtomicSimpleCPU-SPARC-aarch64-fast
-test-insttest-linux-TimingSimpleCPU-SPARC-aarch64-fast
-test-hello-linux-MinorCPU-RISCV-x86_64-debug
-test-hello-linux-TimingSimpleCPU-SPARC-x86_64-debug
-test-hello-linux-AtomicSimpleCPU-SPARC-x86_64-debug
-test-hello-linux-TimingSimpleCPU-MIPS-x86_64-debug
-test-hello-linux-AtomicSimpleCPU-MIPS-x86_64-debug
-test-hello-linux-DerivO3CPU-MIPS-x86_64-debug
-test-hello-linux-MinorCPU-RISCV-x86_64-fast
-test-hello-linux-TimingSimpleCPU-SPARC-x86_64-fast
-test-hello-linux-AtomicSimpleCPU-SPARC-x86_64-fast
-test-hello-linux-TimingSimpleCPU-MIPS-x86_64-fast
-test-hello-linux-AtomicSimpleCPU-MIPS-x86_64-fast
-test-hello-linux-DerivO3CPU-MIPS-x86_64-fast
-test-hello-linux-MinorCPU-RISCV-x86_64-opt
-test-hello-linux-TimingSimpleCPU-SPARC-x86_64-opt
-test-hello-linux-AtomicSimpleCPU-SPARC-x86_64-opt
-test-hello-linux-TimingSimpleCPU-MIPS-x86_64-opt
-test-hello-linux-AtomicSimpleCPU-MIPS-x86_64-opt
-test-hello-linux-DerivO3CPU-MIPS-x86_64-opt
-test-hello-linux-MinorCPU-RISCV-aarch64-debug

[gem5-dev] Change in gem5/gem5[develop]: sim-se: don't wake up SE futex syscalls on ARM events

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29777 )


Change subject: sim-se: don't wake up SE futex syscalls on ARM events
..

sim-se: don't wake up SE futex syscalls on ARM events

Before this commit:

* SEV events were not waking neither WFE (wrong) nor futex WAIT (correct)
* locked memory events (LLSC) due to LDXR and STXR were waking up both
  WFE (correct) and futex WAIT (wrong)

This commit fixes all wrong behaviours mentioned above.

The fact that LLSC events were waking up futexes leads to deadlocks,
as shown in the test case described at:
https://gem5.atlassian.net/browse/GEM5-537
because threads woken up by SVE are not removed from the waiter list
for the futex address they are sleeping on.

A previous fix atttempt was done at:
1531b56d605d47252dc0620bb3e755b7cf84df97
in which only sleeping threads are woken up. But that is not sufficient,
because the futex sleeping thread that was being wrongly woken up on SEV
can start to sleep on a second futex.

As an example, consider the case where 4 threads are fighting over two
critical sections protected by futex1 and futex2 addresses. In this case,
one thread wakes up the other thread after it is done with the section.

Suppose the following sequence of events:

* thread1 is awake and all others are suspended on futex1

* thread1 SEV wakes thread2 from the futex1 while in the critical region 1.

  This is the wrong behaviour that this patch prevents, because
  now thread2 is still in the sleeper list for futex1

* thread1 then futex wakes tread3, then proceeds to critical region 2.

* thread3 wakes up, but because thread2 has critical region, it sleeps
  again.

* thread2 finishes its work, futex wakes thread3, and then proceeds to
  futex2

  When it reaches futex2, thread1 is still working there, so it sleeps on
  futex2.

* thread3 futex wakes thread2, because it is still wrongly on the sleeper
  list of futex1. But thread2 is in futex2 now.

  If it weren't for this mistake, it should have awaken the final thread4
  instead.

Outcome: thread4 sleeps forever, no other thread ever wakes it, because all
other threads have woken from futex1 and awoken another thread.

The problem is fixed by adding the waitingTcs unordered_set FutexMap,
which is basically an inverse map to FutexMap, which tracks (addr,
tgid) -> ThreadContext. This allows us allow to quickly check
if a given ThreadContext is waiting on a futex in any address.

Then the SEV wakeup code path
now checks if the thread is k

Change-Id: Icec5e30b041f53e5aa3b6e0d291e77bc0e865984
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29777
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Brandon Potter 
Maintainer: Jason Lowe-Power 
Maintainer: Brandon Potter 
Tested-by: kokoro 
---
M src/arch/arm/locked_mem.hh
M src/cpu/base.cc
M src/cpu/base.hh
M src/sim/futex_map.cc
M src/sim/futex_map.hh
5 files changed, 39 insertions(+), 14 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Brandon Potter: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/locked_mem.hh b/src/arch/arm/locked_mem.hh
index ad52da4..a01b838 100644
--- a/src/arch/arm/locked_mem.hh
+++ b/src/arch/arm/locked_mem.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013,2017 ARM Limited
+ * Copyright (c) 2012-2013,2017, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -50,6 +50,7 @@

 #include "arch/arm/miscregs.hh"
 #include "arch/arm/isa_traits.hh"
+#include "arch/arm/utility.hh"
 #include "debug/LLSC.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"
@@ -80,8 +81,8 @@
 xc->getCpuPtr()->name());
 xc->setMiscReg(MISCREG_LOCKFLAG, false);
 // Implement ARMv8 WFE/SEV semantics
+sendEvent(xc);
 xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
-xc->getCpuPtr()->wakeup(xc->threadId());
 }
 }

@@ -155,8 +156,8 @@
 DPRINTF(LLSC,"Clearing lock and signaling sev\n");
 xc->setMiscReg(MISCREG_LOCKFLAG, false);
 // Implement ARMv8 WFE/SEV semantics
+sendEvent(xc);
 xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
-xc->getCpuPtr()->wakeup(xc->threadId());
 }

 } // namespace ArmISA
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 084c1e5..fb99712 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -186,6 +186,17 @@
 }

 void
+BaseCPU::postInterrupt(ThreadID tid, int int_num, int index)
+{
+interrupts[tid]->post(int_num, index);
+// Only wake up syscall emulation if it is not waiting on a futex.
+// This is to model the fact that instructions such as ARM SEV
+// should wake up a WFE sleep, but not a futex syscall WAIT. */
+if (FullSystem || !system->futexMap.is_waiting(threadContexts[tid]))
+wakeup(tid);
+}
+

[gem5-dev] Change in gem5/gem5[develop]: sim-se: factor out FutexMap::suspend and FutexMap::suspend_bitset

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29776 )


Change subject: sim-se: factor out FutexMap::suspend and  
FutexMap::suspend_bitset

..

sim-se: factor out FutexMap::suspend and FutexMap::suspend_bitset

Both methods do basically the same, especially since they don't handle the
timeout which is basically the only difference between both modes of the
syscall (one uses absolute and the other relative time).

Remove the WaiterState::WaiterState(ThreadContext* _tc) constructor,
since the only calls were from FutexMap::suspend which does not use them
anymore. Instead, set the magic 0x constant as a parameter to
suspend_bitset.

Change-Id: I69d86bad31d63604657a3c71cf07e5623f0ea639
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29776
Reviewed-by: Brandon Potter 
Maintainer: Brandon Potter 
Tested-by: kokoro 
---
M src/sim/futex_map.cc
M src/sim/futex_map.hh
2 files changed, 1 insertion(+), 21 deletions(-)

Approvals:
  Brandon Potter: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/futex_map.cc b/src/sim/futex_map.cc
index e2880aa..f7dde9c 100644
--- a/src/sim/futex_map.cc
+++ b/src/sim/futex_map.cc
@@ -26,7 +26,6 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */

-#include 
 #include 

 FutexKey::FutexKey(uint64_t addr_in, uint64_t tgid_in)
@@ -53,9 +52,6 @@
 WaiterState::WaiterState(ThreadContext* _tc, int _bitmask)
   : tc(_tc), bitmask(_bitmask) { }

-WaiterState::WaiterState(ThreadContext* _tc)
-  : tc(_tc), bitmask(0x) { }
-
 bool
 WaiterState::checkMask(int wakeup_bitmask) const
 {
@@ -65,18 +61,7 @@
 void
 FutexMap::suspend(Addr addr, uint64_t tgid, ThreadContext *tc)
 {
-FutexKey key(addr, tgid);
-auto it = find(key);
-
-if (it == end()) {
-WaiterList waiterList {WaiterState(tc)};
-insert({key, waiterList});
-} else {
-it->second.push_back(WaiterState(tc));
-}
-
-/** Suspend the thread context */
-tc->suspend();
+suspend_bitset(addr, tgid, tc, 0x);
 }

 int
diff --git a/src/sim/futex_map.hh b/src/sim/futex_map.hh
index 025d324..13caa12 100644
--- a/src/sim/futex_map.hh
+++ b/src/sim/futex_map.hh
@@ -75,11 +75,6 @@
 WaiterState(ThreadContext* _tc, int _bitmask);

 /**
- * if bitset is not defined, just set bitmask to 0x
- */
-WaiterState(ThreadContext* _tc);
-
-/**
  * return true if the bit-wise AND of the wakeup_bitmask given by
  * a waking thread and this thread's internal bitmask is non-zero
  */

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I69d86bad31d63604657a3c71cf07e5623f0ea639
Gerrit-Change-Number: 29776
Gerrit-PatchSet: 6
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim-se: split futex_map.cc into header and source files

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29775 )


Change subject: sim-se: split futex_map.cc into header and source files
..

sim-se: split futex_map.cc into header and source files

To speed up development when modifying the implementation.

Change-Id: I1b3c67c86f8faa38ed81a538521b08e256d21a5a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29775
Reviewed-by: Brandon Potter 
Maintainer: Brandon Potter 
Tested-by: kokoro 
---
M src/sim/SConscript
A src/sim/futex_map.cc
M src/sim/futex_map.hh
3 files changed, 218 insertions(+), 174 deletions(-)

Approvals:
  Brandon Potter: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/SConscript b/src/sim/SConscript
index 961d89e..307c45b 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -51,6 +51,7 @@
 Source('debug.cc')
 Source('py_interact.cc', add_tags='python')
 Source('eventq.cc')
+Source('futex_map.cc')
 Source('global_event.cc')
 Source('init.cc', add_tags='python')
 Source('init_signals.cc')
diff --git a/src/sim/futex_map.cc b/src/sim/futex_map.cc
new file mode 100644
index 000..e2880aa
--- /dev/null
+++ b/src/sim/futex_map.cc
@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2017 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+FutexKey::FutexKey(uint64_t addr_in, uint64_t tgid_in)
+: addr(addr_in), tgid(tgid_in) {}
+
+bool
+FutexKey::operator==(const FutexKey ) const
+{
+return addr == in.addr && tgid == in.tgid;
+}
+
+namespace std {
+size_t hash::operator()(const FutexKey& in) const
+{
+size_t hash = 65521;
+for (int i = 0; i < sizeof(uint64_t) / sizeof(size_t); i++) {
+hash ^= (size_t)(in.addr >> sizeof(size_t) * i) ^
+(size_t)(in.tgid >> sizeof(size_t) * i);
+}
+return hash;
+}
+}
+
+WaiterState::WaiterState(ThreadContext* _tc, int _bitmask)
+  : tc(_tc), bitmask(_bitmask) { }
+
+WaiterState::WaiterState(ThreadContext* _tc)
+  : tc(_tc), bitmask(0x) { }
+
+bool
+WaiterState::checkMask(int wakeup_bitmask) const
+{
+return bitmask & wakeup_bitmask;
+}
+
+void
+FutexMap::suspend(Addr addr, uint64_t tgid, ThreadContext *tc)
+{
+FutexKey key(addr, tgid);
+auto it = find(key);
+
+if (it == end()) {
+WaiterList waiterList {WaiterState(tc)};
+insert({key, waiterList});
+} else {
+it->second.push_back(WaiterState(tc));
+}
+
+/** Suspend the thread context */
+tc->suspend();
+}
+
+int
+FutexMap::wakeup(Addr addr, uint64_t tgid, int count)
+{
+FutexKey key(addr, tgid);
+auto it = find(key);
+
+if (it == end())
+return 0;
+
+int woken_up = 0;
+auto  = it->second;
+
+while (!waiterList.empty() && woken_up < count) {
+// Threads may be woken up by access to locked
+// memory addresses outside of syscalls, so we
+// must only count threads that were actually
+// woken up by this syscall.
+auto& tc = waiterList.front().tc;
+if (tc->status() == ThreadContext::Suspended) {
+tc->activate();
+woken_up++;
+}
+waiterList.pop_front();
+}
+
+if (waiterList.empty())
+erase(it);
+
+return woken_up;
+}
+
+void
+FutexMap::suspend_bitset(Addr addr, uint64_t tgid, 

[gem5-dev] Change in gem5/gem5[develop]: dev-arm: relax GenericTimer check for CPU count

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31894 )


Change subject: dev-arm: relax GenericTimer check for CPU count
..

dev-arm: relax GenericTimer check for CPU count

At Iff9ad68d64e67b3df51682b7e4e272e5f355bcd6 a check was added to prevent
segfaults when unserializing the GenericTimer in case the new number of
thread contexts was smaller than the old one pre-checkpoint.

However, GenericTimer objects are only created dynamically as needed after
timer miscreg accesses. Therefore, if we take the checkpoint before
touching those registers, e.g. from a simple baremetal example, then the
checkpoint saves zero timers, and upon restore the assert would fail
because we have one thread context and not zero:


fatal: The simulated system has been initialized with 1 CPUs, but the

Generic Timer checkpoint expects 0 CPUs. Consider restoring the checkpoint
specifying 0 CPUs.

This commit solves that by ensuring only that the new thread context count
larger than, but not necessarily equal to the number of cores.

Change-Id: I8bcb05a6faecd4b4845f7fd4d71df95041bf6c99
JIRA: https://gem5.atlassian.net/browse/GEM5-703
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31894
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/dev/arm/generic_timer.cc
1 file changed, 5 insertions(+), 1 deletion(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc
index bf6cd4e..7bb2def 100644
--- a/src/dev/arm/generic_timer.cc
+++ b/src/dev/arm/generic_timer.cc
@@ -426,7 +426,11 @@
 cpu_count = OLD_CPU_MAX;
 }

-if (cpu_count != system.threads.size()) {
+// We cannot assert for equality here because CPU timers are  
dynamically
+// created on the first miscreg access. Therefore, if we take the  
checkpoint
+// before any timer registers have been accessed, the number of  
counters

+// is actually smaller than the total number of CPUs.
+if (cpu_count > system.threads.size()) {
 fatal("The simulated system has been initialized with %d CPUs, "
   "but the Generic Timer checkpoint expects %d CPUs. Consider "
   "restoring the checkpoint specifying %d CPUs.",

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31894
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8bcb05a6faecd4b4845f7fd4d71df95041bf6c99
Gerrit-Change-Number: 31894
Gerrit-PatchSet: 4
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: relax GenericTimer check for CPU count

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31894 )



Change subject: dev-arm: relax GenericTimer check for CPU count
..

dev-arm: relax GenericTimer check for CPU count

At Iff9ad68d64e67b3df51682b7e4e272e5f355bcd6 a check was added to prevent
segfaults when unserializing the GenericTimer in case the new number of
thread contexts was smaller than the old one pre-checkpoint.

However, GenericTimer objects are only created dynamically as needed after
timer miscreg accesses. Therefore, if we take the checkpoint before
touching those registers, e.g. from a simple baremetal example, then the
checkpoint saves zero timers, and upon restore the assert would fail
because we have one thread context and not zero:


fatal: The simulated system has been initialized with 1 CPUs, but the

Generic Timer checkpoint expects 0 CPUs. Consider restoring the checkpoint
specifying 0 CPUs.

This commit solves that by ensuring only that the new thread context count
larger than, but not necessarily equal to the number of cores.

Change-Id: I8bcb05a6faecd4b4845f7fd4d71df95041bf6c99
JIRA: https://gem5.atlassian.net/browse/GEM5-703
---
M src/dev/arm/generic_timer.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc
index bf6cd4e..0a44adf 100644
--- a/src/dev/arm/generic_timer.cc
+++ b/src/dev/arm/generic_timer.cc
@@ -426,7 +426,7 @@
 cpu_count = OLD_CPU_MAX;
 }

-if (cpu_count != system.threads.size()) {
+if (cpu_count > system.threads.size()) {
 fatal("The simulated system has been initialized with %d CPUs, "
   "but the Generic Timer checkpoint expects %d CPUs. Consider "
   "restoring the checkpoint specifying %d CPUs.",

--
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Gerrit-Change-Id: I8bcb05a6faecd4b4845f7fd4d71df95041bf6c99
Gerrit-Change-Number: 31894
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[gem5-dev] Change in gem5/gem5[develop]: sim: add UNSERIALIZE_ARRAY_INCOMPLETE

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31895 )



Change subject: sim: add UNSERIALIZE_ARRAY_INCOMPLETE
..

sim: add UNSERIALIZE_ARRAY_INCOMPLETE

This new serialization method allows the number of unserialized array
elements to be smaller than the new number of elements.

This allows new entries to be added to the end of arrays without breaking
checkpoints.

Change-Id: Ia9588dde24d1eb988d34789fca2883a1c9e7b39d
---
M src/sim/serialize.hh
1 file changed, 22 insertions(+), 5 deletions(-)



diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh
index 1f31dd2..b8c0c8c 100644
--- a/src/sim/serialize.hh
+++ b/src/sim/serialize.hh
@@ -586,7 +586,7 @@
 template 
 void
 arrayParamIn(CheckpointIn , const std::string ,
- T *param, unsigned size)
+ T *param, unsigned size, bool exact_size = true)
 {
 const std::string (Serializable::currentSection());
 std::string str;
@@ -604,9 +604,15 @@
 // Need this if we were doing a vector
 // value.resize(tokens.size());

-fatal_if(tokens.size() != size,
- "Array size mismatch on %s:%s (Got %u, expected %u)'\n",
- section, name, tokens.size(), size);
+if (exact_size) {
+fatal_if(tokens.size() != size,
+ "Array size mismatch on %s:%s (Got %u, expected %u)'\n",
+ section, name, tokens.size(), size);
+} else {
+fatal_if(tokens.size() > size,
+ "Array size smaller on %s:%s (Got %u, expected %u)'\n",
+ section, name, tokens.size(), size);
+}

 for (std::vector::size_type i = 0; i < tokens.size();  
i++) {

 // need to parse into local variable to handle vector,
@@ -717,8 +723,8 @@
 std::string str;
 if (!cp.find(section, name, str)) {
 fatal("Can't unserialize '%s:%s'\n", section, name);
-}
 param.clear();
+}

 std::vector tokens;
 tokenize(tokens, str, ' ');
@@ -814,6 +820,17 @@
 arrayParamIn(cp, #member, member, size)

 /**
+ * \def UNSERIALIZE_ARRAY_INCOMPLETE(member, size)
+ *
+ * Unserialize an array, and allow the serialization data to be
+ * smaller than the container size.
+ *
+ * @ingroup api_serialize
+ */
+#define UNSERIALIZE_ARRAY_INCOMPLETE(member, size) \
+arrayParamIn(cp, #member, member, size, false)
+
+/**
  * \def SERIALIZE_CONTAINER(member)
  *
  * @ingroup api_serialize

--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ia9588dde24d1eb988d34789fca2883a1c9e7b39d
Gerrit-Change-Number: 31895
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[gem5-dev] Change in gem5/gem5[develop]: cpu: differentiate snoop DPRINTF messages for AtomicSimpleCPU

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30694 )


Change subject: cpu: differentiate snoop DPRINTF messages for  
AtomicSimpleCPU

..

cpu: differentiate snoop DPRINTF messages for AtomicSimpleCPU

Those three snoop messages were the same, which made interpreting logs
harder.

Change-Id: Ibff092932bc6d2ef0c5f15bf5f7ce031d1f1956b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30694
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/simple/atomic.cc
1 file changed, 6 insertions(+), 6 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index c57fe14..d7a914a 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -125,8 +125,8 @@
 void
 AtomicSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender)
 {
-DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n",  
pkt->getAddr(),

-pkt->cmdString());
+DPRINTF(SimpleCPU, "%s received snoop pkt for addr:%#x %s\n",
+__func__, pkt->getAddr(), pkt->cmdString());

 for (ThreadID tid = 0; tid < numThreads; tid++) {
 if (tid != sender) {
@@ -280,8 +280,8 @@
 Tick
 AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt)
 {
-DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n",  
pkt->getAddr(),

-pkt->cmdString());
+DPRINTF(SimpleCPU, "%s received atomic snoop pkt for addr:%#x %s\n",
+__func__, pkt->getAddr(), pkt->cmdString());

 // X86 ISA: Snooping an invalidation for monitor/mwait
 AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)();
@@ -310,8 +310,8 @@
 void
 AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt)
 {
-DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n",  
pkt->getAddr(),

-pkt->cmdString());
+DPRINTF(SimpleCPU, "%s received functional snoop pkt for  
addr:%#x %s\n",

+__func__, pkt->getAddr(), pkt->cmdString());

 // X86 ISA: Snooping an invalidation for monitor/mwait
 AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)();

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibff092932bc6d2ef0c5f15bf5f7ce031d1f1956b
Gerrit-Change-Number: 30694
Gerrit-PatchSet: 2
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: mark ID_AA64ISAR1_EL1.JSCVT implemented

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30934 )


Change subject: arch-arm: mark ID_AA64ISAR1_EL1.JSCVT implemented
..

arch-arm: mark ID_AA64ISAR1_EL1.JSCVT implemented

The feature was implemented at: I1b24839daef775bbb1eb9da5f32c4bb3843e0b28

Change-Id: I0c0f55e55a1ca3ca6bf40206a989ef0bb353ee84
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30934
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/ArmISA.py
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index f701f7d..b2513f7 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2013, 2015-2019 ARM Limited
+# Copyright (c) 2012-2013, 2015-2020 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -101,8 +101,8 @@
 id_aa64isar0_el1 = Param.UInt64(0x,
 "AArch64 Instruction Set Attribute Register 0")

-# GPI = 0x0 | GPA = 0x1| API=0x0 | APA=0x1 | FCMA
-id_aa64isar1_el1 = Param.UInt64(0x01010010,
+# GPI = 0x0 | GPA = 0x1 | API=0x0 | FCMA | JSCVT | APA=0x1
+id_aa64isar1_el1 = Param.UInt64(0x01011010,
 "AArch64 Instruction Set Attribute Register 1")

 # 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I0c0f55e55a1ca3ca6bf40206a989ef0bb353ee84
Gerrit-Change-Number: 30934
Gerrit-PatchSet: 2
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: implement the ID_ISAR6_EL1 miscregister

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30935 )



Change subject: arch-arm: implement the ID_ISAR6_EL1 miscregister
..

arch-arm: implement the ID_ISAR6_EL1 miscregister

This register is used since the Linux kernel 5.6 aarch64 boot.

Its capability values are analogous to those present in
ID_AA64ISAR0_EL1 and ID_AA64ISAR1_EL1.

The arm architecture document clarifies that reads to this system register
location before it had defined should return 0, but we were faulting
instead:


Prior to the introduction of the features described by this register,

this register was unnamed and reserved, RES0 from EL1, EL2, and EL3.

Change-Id: I70e99536dc98925e88233fd4c6887bbcdd5d87dc
---
M src/arch/arm/ArmISA.py
M src/arch/arm/fastmodel/CortexA76/thread_context.cc
M src/arch/arm/insts/misc64.cc
M src/arch/arm/isa.cc
M src/arch/arm/kvm/arm_cpu.cc
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/utility.cc
9 files changed, 27 insertions(+), 4 deletions(-)



diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 47ba5c8..702c110 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -80,6 +80,8 @@
 id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute  
Register 3")
 id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute  
Register 4")
 id_isar5 = Param.UInt32(0x1000, "Instruction Set Attribute  
Register 5")

+# !I8MM | !BF16 | SPECRES = 0 | !SB | !FHM | DP | JSCVT
+id_isar6 = Param.UInt32(0x0001, "Instruction Set Attribute  
Register 6")


 fpsid = Param.UInt32(0x410430a0, "Floating-point System ID Register")

@@ -97,10 +99,11 @@
 id_aa64dfr1_el1 = Param.UInt64(0x,
 "AArch64 Debug Feature Register 1")

-# !CRC32 | !SHA2 | !SHA1 | !AES
+# !FHM | !CRC32 | !SHA2 | !SHA1 | !AES
 id_aa64isar0_el1 = Param.UInt64(0x,
 "AArch64 Instruction Set Attribute Register 0")

+# !I8MM | !BF16 | SPECRES = 0 | !SB |
 # GPI = 0x0 | GPA = 0x1 | API=0x0 | FCMA | JSCVT | APA=0x1
 id_aa64isar1_el1 = Param.UInt64(0x01011010,
 "AArch64 Instruction Set Attribute Register 1")
diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc  
b/src/arch/arm/fastmodel/CortexA76/thread_context.cc

index 4016d2b..825934b 100644
--- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
@@ -306,6 +306,7 @@
 { ArmISA::MISCREG_ID_ISAR3, "ID_ISAR3" },
 { ArmISA::MISCREG_ID_ISAR4, "ID_ISAR4" },
 { ArmISA::MISCREG_ID_ISAR5, "ID_ISAR5" },
+{ ArmISA::MISCREG_ID_ISAR6, "ID_ISAR6" },
 { ArmISA::MISCREG_CCSIDR, "CCSIDR" },
 { ArmISA::MISCREG_CLIDR, "CLIDR" },
 { ArmISA::MISCREG_AIDR, "AIDR" },
@@ -587,6 +588,7 @@
 { ArmISA::MISCREG_ID_ISAR3_EL1, "ID_ISAR3_EL1" },
 { ArmISA::MISCREG_ID_ISAR4_EL1, "ID_ISAR4_EL1" },
 { ArmISA::MISCREG_ID_ISAR5_EL1, "ID_ISAR5_EL1" },
+{ ArmISA::MISCREG_ID_ISAR6_EL1, "ID_ISAR6_EL1" },
 { ArmISA::MISCREG_MVFR0_EL1, "MVFR0_EL1" },
 { ArmISA::MISCREG_MVFR1_EL1, "MVFR1_EL1" },
 { ArmISA::MISCREG_MVFR2_EL1, "MVFR2_EL1" },
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 51e6028..e1310c4 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -250,6 +250,7 @@
   case MISCREG_ID_ISAR3_EL1:
   case MISCREG_ID_ISAR4_EL1:
   case MISCREG_ID_ISAR5_EL1:
+  case MISCREG_ID_ISAR6_EL1:
   case MISCREG_MVFR0_EL1:
   case MISCREG_MVFR1_EL1:
   case MISCREG_MVFR2_EL1:
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 29c5538..9cac0cf 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -338,6 +338,7 @@
 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
+miscRegs[MISCREG_ID_ISAR6] = p->id_isar6;

 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
diff --git a/src/arch/arm/kvm/arm_cpu.cc b/src/arch/arm/kvm/arm_cpu.cc
index a8b07b9..5dd1725 100644
--- a/src/arch/arm/kvm/arm_cpu.cc
+++ b/src/arch/arm/kvm/arm_cpu.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -157,6 +157,7 @@
 REG_CP32(15, 0, 0, 2, 3), // ID_ISAR3
 REG_CP32(15, 0, 0, 2, 4), // ID_ISAR4
 REG_CP32(15, 0, 0, 2, 5), // ID_ISAR5
+REG_CP32(15, 0, 0, 2, 7), // ID_ISAR6

 REG_CP32(15, 0, 1, 0, 0), // CSSIDR
 REG_CP32(15, 0, 1, 0, 1), // CLIDR
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 3c80de4..0b74629 100644

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: mark ID_AA64ISAR1_EL1.JSCVT implemented

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30934 )



Change subject: arch-arm: mark ID_AA64ISAR1_EL1.JSCVT implemented
..

arch-arm: mark ID_AA64ISAR1_EL1.JSCVT implemented

The feature was implemented at: I1b24839daef775bbb1eb9da5f32c4bb3843e0b28

Change-Id: I0c0f55e55a1ca3ca6bf40206a989ef0bb353ee84
---
M src/arch/arm/ArmISA.py
1 file changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 2641ec3..47ba5c8 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2013, 2015-2019 ARM Limited
+# Copyright (c) 2012-2013, 2015-2020 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -101,8 +101,8 @@
 id_aa64isar0_el1 = Param.UInt64(0x,
 "AArch64 Instruction Set Attribute Register 0")

-# GPI = 0x0 | GPA = 0x1| API=0x0 | APA=0x1 | FCMA
-id_aa64isar1_el1 = Param.UInt64(0x01010010,
+# GPI = 0x0 | GPA = 0x1 | API=0x0 | FCMA | JSCVT | APA=0x1
+id_aa64isar1_el1 = Param.UInt64(0x01011010,
 "AArch64 Instruction Set Attribute Register 1")

 # 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA

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Gerrit-Change-Id: I0c0f55e55a1ca3ca6bf40206a989ef0bb353ee84
Gerrit-Change-Number: 30934
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[gem5-dev] Change in gem5/gem5[develop]: stats: add --stats-root option to dump only under some SimObjects

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28628 )


Change subject: stats: add --stats-root option to dump only under some  
SimObjects

..

stats: add --stats-root option to dump only under some SimObjects

This commit makes it possible to make invocations such as:

gem5.opt se.py --stats-root 'system.cpu[:].dtb' --stats-root 'system.membus'

When --stats-root is given, only stats that are under any of the root
SimObjects get dumped. E.g. the above invocation would dump stats such as:

system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED
system.membus.pwrStateResidencyTicks::UNDEFINED
system.membus.trans_dist::ReadReq

but not for example `system.clk_domain.clock`.

If the --stats-root is given, only new stats as defined at:
Idc8ff448b9f70a796427b4a5231e7371485130b4 get dumped, and old ones are
ignored. The commits following that one have done some initial conversion
work, but many stats are still in the old format.

Change-Id: Iadaef26edf9a678b39f774515600884fbaeec497
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28628
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M RELEASE-NOTES.md
M configs/common/Options.py
M configs/common/Simulation.py
M src/python/m5/SimObject.py
M src/python/m5/stats/__init__.py
5 files changed, 61 insertions(+), 18 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/RELEASE-NOTES.md b/RELEASE-NOTES.md
index 3542de9..adf33b2 100644
--- a/RELEASE-NOTES.md
+++ b/RELEASE-NOTES.md
@@ -1,3 +1,7 @@
+# Version 20.1.0.0
+
+* m5.stats.dump() root argument renamed to roots to reflect the fact that  
it now takes a list of SimObjects

+
 # Version 20.0.0.2

 **[HOTFIX]** A patch was applied to fix the RubyPrefetcher with  
MESI_Three_Level. Prior to this fix a segfault occurred.

diff --git a/configs/common/Options.py b/configs/common/Options.py
index 3eff04b..0409fb8 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -361,6 +361,14 @@
 parser.add_option("--arm-iset", default="arm", type="choice",
   choices=["arm", "thumb", "aarch64"],
   help="ARM instruction set.")
+parser.add_option("--stats-root", action="append", default=[], help=
+"If given, dump only stats of objects under the given SimObject. "
+"SimObjects are identified with Python notation as in: "
+"system.cpu[0].dtb. All elements of an array can be selected at "
+"once with: system.cpu[:].dtb. If given multiple times, dump  
stats "

+"that are present under any of the roots. If not given, dump all "
+"stats. "
+)


 def addSEOptions(parser):
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index e53c755..e7fb878 100644
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -451,6 +451,12 @@
 if options.repeat_switch and options.take_checkpoints:
 fatal("Can't specify both --repeat-switch and --take-checkpoints")

+# Setup global stat filtering.
+stat_root_simobjs = []
+for stat_root_str in options.stats_root:
+stat_root_simobjs.extend(root.get_simobj(stat_root_str))
+m5.stats.global_dump_roots = stat_root_simobjs
+
 np = options.num_cpus
 switch_cpus = None

diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index a045fb7..7f12856 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2017-2019 ARM Limited
+# Copyright (c) 2017-2020 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -1071,6 +1071,9 @@
 out.extend(sim_object[i] for i in _range)
 return SimObjectCliWrapper(out)

+def __iter__(self):
+return iter(self._sim_objects)
+
 # The SimObject class is the root of the special hierarchy.  Most of
 # the code in this class deals with the configuration hierarchy itself
 # (parent/child node relationships).
@@ -1695,6 +1698,18 @@
 for param in params:
 exec(param, d)

+def get_simobj(self, simobj_path):
+"""
+Get all sim objects that match a given string.
+
+The format is the same as that supported by SimObjectCliWrapper.
+
+:param simobj_path: Current state to be in.
+:type simobj_path: str
+"""
+d = self._apply_config_get_dict()
+return eval(simobj_path, d)
+
 # Function to provide to C++ so it can look up instances based on paths
 def resolveSimObject(name):
 obj = instanceDict[name]
diff --git a/src/python/m5/stats/__init__.py  
b/src/python/m5/stats/__init__.py

index 1e37a14..6c4a42c 100644
--- a/src/python/m5/stats/__init__.py
+++ 

[gem5-dev] Change in gem5/gem5[develop]: cpu: differentiate snoop DPRINTF messages for AtomicSimpleCPU

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30694 )



Change subject: cpu: differentiate snoop DPRINTF messages for  
AtomicSimpleCPU

..

cpu: differentiate snoop DPRINTF messages for AtomicSimpleCPU

Those three snoop messages were the same, which made interpreting logs
harder.

Change-Id: Ibff092932bc6d2ef0c5f15bf5f7ce031d1f1956b
---
M src/cpu/simple/atomic.cc
1 file changed, 6 insertions(+), 6 deletions(-)



diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 4671402..8c918e6 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -125,8 +125,8 @@
 void
 AtomicSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender)
 {
-DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n",  
pkt->getAddr(),

-pkt->cmdString());
+DPRINTF(SimpleCPU, "%s received snoop pkt for addr:%#x %s\n",
+__func__, pkt->getAddr(), pkt->cmdString());

 for (ThreadID tid = 0; tid < numThreads; tid++) {
 if (tid != sender) {
@@ -280,8 +280,8 @@
 Tick
 AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt)
 {
-DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n",  
pkt->getAddr(),

-pkt->cmdString());
+DPRINTF(SimpleCPU, "%s received atomic snoop pkt for addr:%#x %s\n",
+__func__, pkt->getAddr(), pkt->cmdString());

 // X86 ISA: Snooping an invalidation for monitor/mwait
 AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)();
@@ -310,8 +310,8 @@
 void
 AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt)
 {
-DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n",  
pkt->getAddr(),

-pkt->cmdString());
+DPRINTF(SimpleCPU, "%s received functional snoop pkt for  
addr:%#x %s\n",

+__func__, pkt->getAddr(), pkt->cmdString());

 // X86 ISA: Snooping an invalidation for monitor/mwait
 AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)();

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30694
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibff092932bc6d2ef0c5f15bf5f7ce031d1f1956b
Gerrit-Change-Number: 30694
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: stats: add option to disable alignment spaces in stats.txt file

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28627 )


Change subject: stats: add option to disable alignment spaces in stats.txt  
file

..

stats: add option to disable alignment spaces in stats.txt file

The alignment spaces in stats.txt takes up a lot of space and increases
simulation time, this commit adds the option to disable them with:

--stats-file stats.txt?spaces=False

Sample old lines with ?desc=False:

system.cpu.op_class::FloatMultAcc   0  0.00% 65.92%
system.cpu.op_class::FloatDiv   0  0.00% 65.92%

Sample new lines with ?desc=False;spaces=False:

system.cpu.op_class::FloatMultAcc 0 0.00% 65.92%
system.cpu.op_class::FloatDiv 0 0.00% 65.92%

On a 1000 dumpstats m5op loop spaces=False reduces:

* size: from 38MB to 20MB
* time: from 4.5s to 3.5s

Change-Id: Ib738b996b5646c329094cf61aaa1d977e844e759
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28627
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/base/stats/text.cc
M src/base/stats/text.hh
M src/python/m5/stats/__init__.py
3 files changed, 71 insertions(+), 28 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/stats/text.cc b/src/base/stats/text.cc
index 96cbe34..fa342a2 100644
--- a/src/base/stats/text.cc
+++ b/src/base/stats/text.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019 Arm Limited
+ * Copyright (c) 2019-2020 Arm Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -95,18 +95,16 @@
 std::list ();

 Text::Text()
-: mystream(false), stream(NULL), descriptions(false)
+: mystream(false), stream(NULL), descriptions(false), spaces(false)
 {
 }

-Text::Text(std::ostream )
-: mystream(false), stream(NULL), descriptions(false)
+Text::Text(std::ostream ) : Text()
 {
 open(stream);
 }

-Text::Text(const std::string )
-: mystream(false), stream(NULL), descriptions(false)
+Text::Text(const std::string ) : Text()
 {
 open(file);
 }
@@ -229,10 +227,28 @@
 string desc;
 Flags flags;
 bool descriptions;
+bool spaces;
 int precision;
 Result pdf;
 Result cdf;
+int nameSpaces;
+int valueSpaces;
+int pdfstrSpaces;
+int cdfstrSpaces;

+ScalarPrint(bool spaces) : spaces(spaces) {
+if (spaces) {
+nameSpaces = 40;
+valueSpaces = 12;
+pdfstrSpaces = 10;
+cdfstrSpaces = 10;
+} else {
+nameSpaces = 0;
+valueSpaces = 0;
+pdfstrSpaces = 0;
+cdfstrSpaces = 0;
+}
+}
 void update(Result val, Result total);
 void operator()(ostream , bool oneLine = false) const;
 };
@@ -263,12 +279,16 @@
 ccprintf(cdfstr, "%.2f%%", cdf * 100.0);

 if (oneLine) {
-ccprintf(stream, " |%12s %10s %10s",
- ValueToString(value, precision), pdfstr.str(),  
cdfstr.str());

+ccprintf(stream, " |");
 } else {
-ccprintf(stream, "%-40s %12s %10s %10s", name,
- ValueToString(value, precision), pdfstr.str(),  
cdfstr.str());

-
+ccprintf(stream, "%-*s ", nameSpaces, name);
+}
+ccprintf(stream, "%*s", valueSpaces, ValueToString(value, precision));
+if (spaces || pdfstr.rdbuf()->in_avail())
+ccprintf(stream, " %*s", pdfstrSpaces, pdfstr.str());
+if (spaces || cdfstr.rdbuf()->in_avail())
+ccprintf(stream, " %*s", cdfstrSpaces, cdfstr.str());
+if (!oneLine) {
 if (descriptions) {
 if (!desc.empty())
 ccprintf(stream, " # %s", desc);
@@ -286,11 +306,21 @@
 vector subdescs;
 Flags flags;
 bool descriptions;
+bool spaces;
 int precision;
 VResult vec;
 Result total;
 bool forceSubnames;
+int nameSpaces;

+VectorPrint() = delete;
+VectorPrint(bool spaces) : spaces(spaces) {
+if (spaces) {
+nameSpaces = 40;
+} else {
+nameSpaces = 0;
+}
+}
 void operator()(ostream ) const;
 };

@@ -308,7 +338,7 @@

 string base = name + separatorString;

-ScalarPrint print;
+ScalarPrint print(spaces);
 print.name = name;
 print.desc = desc;
 print.precision = precision;
@@ -332,7 +362,7 @@

 if ((!flags.isSet(nozero)) || (total != 0)) {
 if (flags.isSet(oneline)) {
-ccprintf(stream, "%-40s", name);
+ccprintf(stream, "%-*s", nameSpaces, name);
 print.flags = print.flags & (~nozero);
 }

@@ -373,7 +403,9 @@
 string desc;
 Flags flags;
 bool descriptions;
+bool spaces;
 int precision;
+int nameSpaces;

 const DistData 

@@ -389,8 +421,8 @@
 init(text, info);
 }

[gem5-dev] Change in gem5/gem5[develop]: tests: add arm64/futex_ldxr_stxr.c

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30634 )



Change subject: tests: add arm64/futex_ldxr_stxr.c
..

tests: add arm64/futex_ldxr_stxr.c

For: https://gem5.atlassian.net/browse/GEM5-537

Change-Id: I943d78f797685f253b7095847a254767c79a2421
---
A tests/test-progs/arm64/futex_ldxr_stxr.c
1 file changed, 126 insertions(+), 0 deletions(-)



diff --git a/tests/test-progs/arm64/futex_ldxr_stxr.c  
b/tests/test-progs/arm64/futex_ldxr_stxr.c

new file mode 100644
index 000..b044494
--- /dev/null
+++ b/tests/test-progs/arm64/futex_ldxr_stxr.c
@@ -0,0 +1,126 @@
+/* Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Correct outcome:
+ * Exiting @ tick 18446744073709551615 because simulate() limit reached
+ * Incorrect behaviour due to: https://gem5.atlassian.net/browse/GEM5-537
+ * Exits successfully. */
+
+#define _GNU_SOURCE
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define LDXR_OPS_SIZE 1024
+static int futex1 = 1;
+static int futex2 = 1;
+/* We do this to ensure that those two varibles are well separated.
+ * If they are too close (same cache line?), then the str to ldxr_done
+ * can make CPU1 lose the lock. */
+static uint64_t ldxr_ops[LDXR_OPS_SIZE];
+static uint64_t *ldxr_done = ldxr_ops;
+static uint64_t *ldxr_var = ldxr_ops + LDXR_OPS_SIZE - 1;
+
+void __attribute__ ((noinline)) busy_loop(
+unsigned long long max,
+unsigned long long max2
+) {
+for (unsigned long long i = 0; i < max2; i++) {
+for (unsigned long long j = 0; j < max; j++) {
+__asm__ __volatile__ ("" : "+g" (i), "+g" (j) : :);
+}
+}
+}
+
+static int
+futex(int *uaddr, int futex_op, int val,
+const struct timespec *timeout, int *uaddr2, int val3)
+{
+register uint64_t x0 __asm__ ("x0") = (uint64_t)uaddr;
+register uint64_t x1 __asm__ ("x1") = futex_op;
+register uint64_t x2 __asm__ ("x2") = val;
+register const struct timespec *x3 __asm__ ("x3") = timeout;
+register int *x4 __asm__ ("x4") = uaddr2;
+register uint64_t x5 __asm__ ("x5") = val3;
+register uint64_t x8 __asm__ ("x8") = SYS_futex; /* syscall number */
+__asm__ __volatile__ (
+"svc 0;"
+: "+r" (x0)
+: "r" (x1), "r" (x2), "r" (x3), "r" (x4), "r" (x5), "r" (x8)
+: "memory"
+);
+return x0;
+}
+
+void* thread_main(void *arg) {
+(void)arg;
+__asm__ __volatile__ (
+"ldxr x0, [%[ldxr_var]];mov %[ldxr_done], 1"
+: [ldxr_done] "=r" (*ldxr_done)
+: [ldxr_var] "r" (ldxr_var)
+: "x0", "memory"
+);
+futex(, FUTEX_WAIT, futex1, NULL, NULL, 0);
+futex(, FUTEX_WAIT, futex2, NULL, NULL, 0);
+return NULL;
+}
+
+int main(void) {
+pthread_t thread;
+pthread_create(, 

[gem5-dev] Change in gem5/gem5[develop]: sim-se: don't wake up SE futex syscalls on ARM events

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29777 )



Change subject: sim-se: don't wake up SE futex syscalls on ARM events
..

sim-se: don't wake up SE futex syscalls on ARM events

Before this commit:

* SEV events were not waking neither WFE (wrong) nor futex WAIT (correct)
* locked memory events (LLSC) due to LDXR and STXR were waking up both
  WFE (correct) and futex WAIT (wrong)

This commit fixes all wrong behaviours mentioned above.

The fact that LLSC events were waking up futexes leads to deadlocks,
as shown in the test case described at:
https://gem5.atlassian.net/browse/GEM5-537
because threads woken up by SVE are not removed from the waiter list
for the futex address they are sleeping on.

A previous fix atttempt was done at:
1531b56d605d47252dc0620bb3e755b7cf84df97
in which only sleeping threads are woken up. But that is not sufficient,
because the futex sleeping thread that was being wrongly woken up on SEV
can start to sleep on a second futex. The deadlock chain of events looks
like this for thread1:

- sleep on futex1, waiter list for futex1 now contains thread1
- woken up by SEV from another thread, not removed from waiter list
  (wrong behaviour made impossible by this patch)
- sleep on futex2
- another thread wakes up thread1 via futex1, since it was still found in
  that waiter list and is in sleeping state

As a result, some other thread that was sleeping on futex1 misses the
wakeup which thread1 received instead, and we have deadlock.

JIRA: https://gem5.atlassian.net/browse/GEM5-622
Change-Id: Icec5e30b041f53e5aa3b6e0d291e77bc0e865984
---
M src/arch/arm/locked_mem.hh
M src/cpu/base.hh
M src/sim/futex_map.cc
M src/sim/futex_map.hh
4 files changed, 31 insertions(+), 9 deletions(-)



diff --git a/src/arch/arm/locked_mem.hh b/src/arch/arm/locked_mem.hh
index ad52da4..a01b838 100644
--- a/src/arch/arm/locked_mem.hh
+++ b/src/arch/arm/locked_mem.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013,2017 ARM Limited
+ * Copyright (c) 2012-2013,2017, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -50,6 +50,7 @@

 #include "arch/arm/miscregs.hh"
 #include "arch/arm/isa_traits.hh"
+#include "arch/arm/utility.hh"
 #include "debug/LLSC.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"
@@ -80,8 +81,8 @@
 xc->getCpuPtr()->name());
 xc->setMiscReg(MISCREG_LOCKFLAG, false);
 // Implement ARMv8 WFE/SEV semantics
+sendEvent(xc);
 xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
-xc->getCpuPtr()->wakeup(xc->threadId());
 }
 }

@@ -155,8 +156,8 @@
 DPRINTF(LLSC,"Clearing lock and signaling sev\n");
 xc->setMiscReg(MISCREG_LOCKFLAG, false);
 // Implement ARMv8 WFE/SEV semantics
+sendEvent(xc);
 xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
-xc->getCpuPtr()->wakeup(xc->threadId());
 }

 } // namespace ArmISA
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index a33d1bd..0ad8cad 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2013, 2017 ARM Limited
+ * Copyright (c) 2011-2013, 2017, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -234,7 +234,10 @@
 postInterrupt(ThreadID tid, int int_num, int index)
 {
 interrupts[tid]->post(int_num, index);
-if (FullSystem)
+// Only wake up syscall emulation if it is not waiting on a futex.
+// This is to model the fact that instructions such as ARM SEV
+// should wake up a WFE sleep, but not a futex syscall WAIT.
+if (FullSystem | 
| !system->futexMap.is_waiting(threadContexts[tid]))

 wakeup(tid);
 }

diff --git a/src/sim/futex_map.cc b/src/sim/futex_map.cc
index f7dde9c..7dabaf2 100644
--- a/src/sim/futex_map.cc
+++ b/src/sim/futex_map.cc
@@ -82,11 +82,10 @@
 // must only count threads that were actually
 // woken up by this syscall.
 auto& tc = waiterList.front().tc;
-if (tc->status() == ThreadContext::Suspended) {
-tc->activate();
-woken_up++;
-}
+tc->activate();
+woken_up++;
 waiterList.pop_front();
+waitingTcs.erase(tc);
 }

 if (waiterList.empty())
@@ -108,6 +107,7 @@
 } else {
 it->second.push_back(WaiterState(tc, bitmask));
 }
+waitingTcs.emplace(tc);

 /** Suspend the thread context */
 tc->suspend();
@@ -133,6 +133,7 @@
 if (waiter.checkMask(bitmask)) {
 waiter.tc->activate();
 iter = waiterList.erase(iter);
+waitingTcs.erase(waiter.tc);
 woken_up++;
 } else {
 ++iter;
@@ -188,3 +189,9 @@

 return woken_up + requeued;
 }
+
+bool
+FutexMap::is_waiting(ThreadContext *tc)
+{
+

[gem5-dev] Change in gem5/gem5[develop]: sim-se: split futex_map.cc into header and source files

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29775 )



Change subject: sim-se: split futex_map.cc into header and source files
..

sim-se: split futex_map.cc into header and source files

To speed up development when modifying the implementation.

Change-Id: I1b3c67c86f8faa38ed81a538521b08e256d21a5a
---
M src/sim/SConscript
A src/sim/futex_map.cc
M src/sim/futex_map.hh
3 files changed, 218 insertions(+), 174 deletions(-)



diff --git a/src/sim/SConscript b/src/sim/SConscript
index bf8cbf5..86c0271 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -51,6 +51,7 @@
 Source('debug.cc')
 Source('py_interact.cc', add_tags='python')
 Source('eventq.cc')
+Source('futex_map.cc')
 Source('global_event.cc')
 Source('init.cc', add_tags='python')
 Source('init_signals.cc')
diff --git a/src/sim/futex_map.cc b/src/sim/futex_map.cc
new file mode 100644
index 000..e2880aa
--- /dev/null
+++ b/src/sim/futex_map.cc
@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2017 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+FutexKey::FutexKey(uint64_t addr_in, uint64_t tgid_in)
+: addr(addr_in), tgid(tgid_in) {}
+
+bool
+FutexKey::operator==(const FutexKey ) const
+{
+return addr == in.addr && tgid == in.tgid;
+}
+
+namespace std {
+size_t hash::operator()(const FutexKey& in) const
+{
+size_t hash = 65521;
+for (int i = 0; i < sizeof(uint64_t) / sizeof(size_t); i++) {
+hash ^= (size_t)(in.addr >> sizeof(size_t) * i) ^
+(size_t)(in.tgid >> sizeof(size_t) * i);
+}
+return hash;
+}
+}
+
+WaiterState::WaiterState(ThreadContext* _tc, int _bitmask)
+  : tc(_tc), bitmask(_bitmask) { }
+
+WaiterState::WaiterState(ThreadContext* _tc)
+  : tc(_tc), bitmask(0x) { }
+
+bool
+WaiterState::checkMask(int wakeup_bitmask) const
+{
+return bitmask & wakeup_bitmask;
+}
+
+void
+FutexMap::suspend(Addr addr, uint64_t tgid, ThreadContext *tc)
+{
+FutexKey key(addr, tgid);
+auto it = find(key);
+
+if (it == end()) {
+WaiterList waiterList {WaiterState(tc)};
+insert({key, waiterList});
+} else {
+it->second.push_back(WaiterState(tc));
+}
+
+/** Suspend the thread context */
+tc->suspend();
+}
+
+int
+FutexMap::wakeup(Addr addr, uint64_t tgid, int count)
+{
+FutexKey key(addr, tgid);
+auto it = find(key);
+
+if (it == end())
+return 0;
+
+int woken_up = 0;
+auto  = it->second;
+
+while (!waiterList.empty() && woken_up < count) {
+// Threads may be woken up by access to locked
+// memory addresses outside of syscalls, so we
+// must only count threads that were actually
+// woken up by this syscall.
+auto& tc = waiterList.front().tc;
+if (tc->status() == ThreadContext::Suspended) {
+tc->activate();
+woken_up++;
+}
+waiterList.pop_front();
+}
+
+if (waiterList.empty())
+erase(it);
+
+return woken_up;
+}
+
+void
+FutexMap::suspend_bitset(Addr addr, uint64_t tgid, ThreadContext *tc,
+   int bitmask)
+{
+FutexKey key(addr, tgid);
+auto it = find(key);
+
+if (it == end()) {
+WaiterList waiterList {WaiterState(tc, bitmask)};
+insert({key, waiterList});
+} else {
+

[gem5-dev] Change in gem5/gem5[develop]: sim-se: factor out FutexMap::suspend and FutexMap::suspend_bitset

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29776 )



Change subject: sim-se: factor out FutexMap::suspend and  
FutexMap::suspend_bitset

..

sim-se: factor out FutexMap::suspend and FutexMap::suspend_bitset

Both methods do basically the same, especially since they don't handle the
timeout which is basically the only difference between both modes of the
syscall (one uses absolute and the other relative time).

Remove the WaiterState::WaiterState(ThreadContext* _tc) constructor,
since the only calls were from FutexMap::suspend which does not use them
anymore. Instead, set the magic 0x constant as a parameter to
suspend_bitset.

Change-Id: I69d86bad31d63604657a3c71cf07e5623f0ea639
---
M src/sim/futex_map.cc
1 file changed, 1 insertion(+), 16 deletions(-)



diff --git a/src/sim/futex_map.cc b/src/sim/futex_map.cc
index e2880aa..f7dde9c 100644
--- a/src/sim/futex_map.cc
+++ b/src/sim/futex_map.cc
@@ -26,7 +26,6 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */

-#include 
 #include 

 FutexKey::FutexKey(uint64_t addr_in, uint64_t tgid_in)
@@ -53,9 +52,6 @@
 WaiterState::WaiterState(ThreadContext* _tc, int _bitmask)
   : tc(_tc), bitmask(_bitmask) { }

-WaiterState::WaiterState(ThreadContext* _tc)
-  : tc(_tc), bitmask(0x) { }
-
 bool
 WaiterState::checkMask(int wakeup_bitmask) const
 {
@@ -65,18 +61,7 @@
 void
 FutexMap::suspend(Addr addr, uint64_t tgid, ThreadContext *tc)
 {
-FutexKey key(addr, tgid);
-auto it = find(key);
-
-if (it == end()) {
-WaiterList waiterList {WaiterState(tc)};
-insert({key, waiterList});
-} else {
-it->second.push_back(WaiterState(tc));
-}
-
-/** Suspend the thread context */
-tc->suspend();
+suspend_bitset(addr, tgid, tc, 0x);
 }

 int

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I69d86bad31d63604657a3c71cf07e5623f0ea639
Gerrit-Change-Number: 29776
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: tests: add ruby_mem_test.py to the tests

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26805 )


Change subject: tests: add ruby_mem_test.py to the tests
..

tests: add ruby_mem_test.py to the tests

This catches ruby functional memory errors we have observed, and ensures
that ruby_mem_test.py itself won't be broken.

The test duration is about 10 seconds, and it can be run as:

./main.py run --uid SuiteUID:tests/gem5/test_ruby_mem_test.py:test-ruby\
_mem_test-NULL-x86_64-opt

Change-Id: I39bc559aaea3ebb41217a96cd4e8dae46271ea1f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26805
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M tests/gem5/memory/test.py
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/gem5/memory/test.py b/tests/gem5/memory/test.py
index 2a4eeb3..5b6294e 100644
--- a/tests/gem5/memory/test.py
+++ b/tests/gem5/memory/test.py
@@ -69,6 +69,8 @@
 null_tests = [
 ('garnet_synth_traffic', ['--sim-cycles', '500']),
 ('memcheck', ['--maxtick', '20', '--prefetchers']),
+('ruby_mem_test', ['--abs-max-tick', '2000',
+'--functional', '10']),
 ('ruby_random_test', ['--maxloads', '5000']),
 ('ruby_direct_test', ['--requests', '5']),
 ]

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I39bc559aaea3ebb41217a96cd4e8dae46271ea1f
Gerrit-Change-Number: 26805
Gerrit-PatchSet: 5
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim-se: implement the getcpu syscall

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28590 )


Change subject: sim-se: implement the getcpu syscall
..

sim-se: implement the getcpu syscall

Change-Id: I63a1384646829b8cf68453c42aed6a7d12172787
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28590
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/linux/process.cc
M src/arch/x86/linux/process.cc
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
4 files changed, 32 insertions(+), 6 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc
index b5b6553..55141ba 100644
--- a/src/arch/arm/linux/process.cc
+++ b/src/arch/arm/linux/process.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, 2015 ARM Limited
+ * Copyright (c) 2010-2013, 2015, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -476,7 +476,7 @@
 { base + 342, "tee" },
 { base + 343, "vmsplice" },
 { base + 344, "move_pages" },
-{ base + 345, "getcpu" },
+{ base + 345, "getcpu", getcpuFunc },
 { base + 346, "epoll_pwait" },
 { base + 347, "sys_kexec_load" },
 { base + 348, "sys_utimensat" },
@@ -681,7 +681,7 @@
 {  base + 165, "getrusage", getrusageFunc },
 {  base + 166, "umask" },
 {  base + 167, "prctl" },
-{  base + 168, "getcpu" },
+{  base + 168, "getcpu", getcpuFunc },
 {  base + 169, "gettimeofday", gettimeofdayFunc },
 {  base + 170, "settimeofday" },
 {  base + 171, "adjtimex" },
diff --git a/src/arch/x86/linux/process.cc b/src/arch/x86/linux/process.cc
index 6b50dbf..2c594e7 100644
--- a/src/arch/x86/linux/process.cc
+++ b/src/arch/x86/linux/process.cc
@@ -566,7 +566,7 @@
 { 306, "syncfs" },
 { 307, "sendmmsg" },
 { 308, "setns" },
-{ 309, "getcpu" },
+{ 309, "getcpu", getcpuFunc },
 { 310, "proess_vm_readv" },
 { 311, "proess_vm_writev" },
 { 312, "kcmp" },
@@ -914,7 +914,7 @@
 { 315, "tee" },
 { 316, "vmsplice" },
 { 317, "move_pages" },
-{ 318, "getcpu" },
+{ 318, "getcpu", getcpuFunc },
 { 319, "epoll_pwait" },
 { 320, "utimensat" },
 { 321, "signalfd" },
diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc
index bffedfd..6d39823 100644
--- a/src/sim/syscall_emul.cc
+++ b/src/sim/syscall_emul.cc
@@ -1633,3 +1633,26 @@
 return (status == -1) ? -errno : status;
 }

+SyscallReturn
+getcpuFunc(SyscallDesc *desc, ThreadContext *tc,
+   Addr cpu_ptr, Addr node_ptr, Addr tcache_ptr)
+{
+bool error = false;
+
+// unsigned is the same size (4) on all Linux supported ISAs.
+if (cpu_ptr != 0) {
+TypedBufferArg result(cpu_ptr);
+*result = htog(tc->contextId(),
+tc->getSystemPtr()->getGuestByteOrder());
+error |= !result.copyOut(tc->getVirtProxy());
+}
+
+// Set a fixed NUMA node 0.
+if (node_ptr != 0) {
+TypedBufferArg result(node_ptr);
+*result = 0;
+error |= !result.copyOut(tc->getVirtProxy());
+}
+
+return error ? -EFAULT : 0;
+}
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 4a37e99..55d30f3 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013, 2015, 2019 ARM Limited
+ * Copyright (c) 2012-2013, 2015, 2019-2020 ARM Limited
  * Copyright (c) 2015 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -354,6 +354,9 @@
  int tgt_fd, int level, int optname,
  Addr valPtr, socklen_t len);

+SyscallReturn getcpuFunc(SyscallDesc *desc, ThreadContext *tc,
+ Addr cpu_ptr, Addr node_ptr, Addr tcache_ptr);
+
 // Target getsockname() handler.
 SyscallReturn getsocknameFunc(SyscallDesc *desc, ThreadContext *tc,
   int tgt_fd, Addr addrPtr, Addr lenPtr);

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I63a1384646829b8cf68453c42aed6a7d12172787
Gerrit-Change-Number: 28590
Gerrit-PatchSet: 4
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim-se: ignore all scheduler related syscalls for arm

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28591 )


Change subject: sim-se: ignore all scheduler related syscalls for arm
..

sim-se: ignore all scheduler related syscalls for arm

With the simplistic syscall emulation fork algorithm that we currently have
of running one thread per call, those calls simply cannot be reasonably
implemented.

However, content can often still work without them.

Change-Id: Iac88dfd055564c47b7a7b6898b7582cf4087f708
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28591
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M src/arch/arm/linux/process.cc
1 file changed, 18 insertions(+), 18 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc
index 55141ba..4c679b3 100644
--- a/src/arch/arm/linux/process.cc
+++ b/src/arch/arm/linux/process.cc
@@ -290,14 +290,14 @@
 { base + 151, "munlock" },
 { base + 152, "mlockall" },
 { base + 153, "munlockall" },
-{ base + 154, "sched_setparam" },
-{ base + 155, "sched_getparam" },
-{ base + 156, "sched_setscheduler" },
-{ base + 157, "sched_getscheduler" },
-{ base + 158, "sched_yield" },
-{ base + 159, "sched_get_priority_max" },
-{ base + 160, "sched_get_priority_min" },
-{ base + 161, "sched_rr_get_interval" },
+{ base + 154, "sched_setparam", ignoreWarnOnceFunc },
+{ base + 155, "sched_getparam", ignoreWarnOnceFunc },
+{ base + 156, "sched_setscheduler", ignoreWarnOnceFunc },
+{ base + 157, "sched_getscheduler", ignoreWarnOnceFunc },
+{ base + 158, "sched_yield", ignoreWarnOnceFunc },
+{ base + 159, "sched_get_priority_max", ignoreWarnOnceFunc },
+{ base + 160, "sched_get_priority_min", ignoreWarnOnceFunc },
+{ base + 161, "sched_rr_get_interval", ignoreWarnOnceFunc },
 { base + 162, "nanosleep", ignoreWarnOnceFunc },
 { base + 163, "mremap", mremapFunc }, // ARM-specific
 { base + 164, "setresuid" },
@@ -375,7 +375,7 @@
 { base + 238, "tkill" },
 { base + 239, "sendfile64" },
 { base + 240, "futex", futexFunc },
-{ base + 241, "sched_setaffinity" },
+{ base + 241, "sched_setaffinity", ignoreWarnOnceFunc },
 { base + 242, "sched_getaffinity", ignoreFunc },
 { base + 243, "io_setup" },
 { base + 244, "io_destroy" },
@@ -631,16 +631,16 @@
 {  base + 115, "clock_nanosleep" },
 {  base + 116, "syslog" },
 {  base + 117, "ptrace" },
-{  base + 118, "sched_setparam" },
-{  base + 119, "sched_setscheduler" },
-{  base + 120, "sched_getscheduler" },
-{  base + 121, "sched_getparam" },
-{  base + 122, "sched_setaffinity" },
+{  base + 118, "sched_setparam", ignoreWarnOnceFunc },
+{  base + 119, "sched_setscheduler", ignoreWarnOnceFunc },
+{  base + 120, "sched_getscheduler", ignoreWarnOnceFunc },
+{  base + 121, "sched_getparam", ignoreWarnOnceFunc },
+{  base + 122, "sched_setaffinity", ignoreWarnOnceFunc },
 {  base + 123, "sched_getaffinity", ignoreFunc },
-{  base + 124, "sched_yield" },
-{  base + 125, "sched_get_priority_max" },
-{  base + 126, "sched_get_priority_min" },
-{  base + 127, "sched_rr_get_interval" },
+{  base + 124, "sched_yield", ignoreWarnOnceFunc },
+{  base + 125, "sched_get_priority_max", ignoreWarnOnceFunc },
+{  base + 126, "sched_get_priority_min", ignoreWarnOnceFunc },
+{  base + 127, "sched_rr_get_interval", ignoreWarnOnceFunc },
 {  base + 128, "restart_syscall" },
 {  base + 129, "kill", ignoreFunc },
 {  base + 130, "tkill" },

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iac88dfd055564c47b7a7b6898b7582cf4087f708
Gerrit-Change-Number: 28591
Gerrit-PatchSet: 4
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: lololo

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29153 )



Change subject: scons: lololo
..

scons: lololo

Change-Id: I43d030dc1db4f371290a15fde175e5feff6274b9
---
M ext/pybind11/include/pybind11/detail/class.h
M ext/pybind11/include/pybind11/detail/internals.h
M ext/pybind11/include/pybind11/detail/typeid.h
3 files changed, 48 insertions(+), 650 deletions(-)



diff --git a/ext/pybind11/include/pybind11/detail/class.h  
b/ext/pybind11/include/pybind11/detail/class.h

index ffdfefe..4dc109b 100644
--- a/ext/pybind11/include/pybind11/detail/class.h
+++ b/ext/pybind11/include/pybind11/detail/class.h
@@ -24,82 +24,27 @@
 #  define PYBIND11_SET_OLDPY_QUALNAME(obj, nameobj) setattr((PyObject *)  
obj, "__qualname__", nameobj)

 #endif

-inline PyTypeObject *type_incref(PyTypeObject *type) {
-Py_INCREF(type);
-return type;
-}
+PyTypeObject *type_incref(PyTypeObject *type);

 #if !defined(PYPY_VERSION)

 /// `pybind11_static_property.__get__()`: Always pass the class instead of  
the instance.
-extern "C" inline PyObject *pybind11_static_get(PyObject *self, PyObject *  
/*ob*/, PyObject *cls) {

-return PyProperty_Type.tp_descr_get(self, cls, cls);
-}
+extern "C" PyObject *pybind11_static_get(PyObject *self, PyObject *  
/*ob*/, PyObject *cls);


 /// `pybind11_static_property.__set__()`: Just like the above `__get__()`.
-extern "C" inline int pybind11_static_set(PyObject *self, PyObject *obj,  
PyObject *value) {

-PyObject *cls = PyType_Check(obj) ? obj : (PyObject *) Py_TYPE(obj);
-return PyProperty_Type.tp_descr_set(self, cls, value);
-}
+extern "C" int pybind11_static_set(PyObject *self, PyObject *obj, PyObject  
*value);


 /** A `static_property` is the same as a `property` but the `__get__()`  
and `__set__()`
 methods are modified to always use the object type instead of a  
concrete instance.

 Return value: New reference. */
-inline PyTypeObject *make_static_property_type() {
-constexpr auto *name = "pybind11_static_property";
-auto name_obj = reinterpret_steal(PYBIND11_FROM_STRING(name));
-
-/* Danger zone: from now (and until PyType_Ready), make sure to
-   issue no Python C API calls which could potentially invoke the
-   garbage collector (the GC will call type_traverse(), which will in
-   turn find the newly constructed type in an invalid state) */
-auto heap_type = (PyHeapTypeObject *)  
PyType_Type.tp_alloc(_Type, 0);

-if (!heap_type)
-pybind11_fail("make_static_property_type(): error allocating  
type!");

-
-heap_type->ht_name = name_obj.inc_ref().ptr();
-#ifdef PYBIND11_BUILTIN_QUALNAME
-heap_type->ht_qualname = name_obj.inc_ref().ptr();
-#endif
-
-auto type = _type->ht_type;
-type->tp_name = name;
-type->tp_base = type_incref(_Type);
-type->tp_flags = Py_TPFLAGS_DEFAULT | Py_TPFLAGS_BASETYPE |  
Py_TPFLAGS_HEAPTYPE;

-type->tp_descr_get = pybind11_static_get;
-type->tp_descr_set = pybind11_static_set;
-
-if (PyType_Ready(type) < 0)
-pybind11_fail("make_static_property_type(): failure in  
PyType_Ready()!");

-
-setattr((PyObject *) type, "__module__", str("pybind11_builtins"));
-PYBIND11_SET_OLDPY_QUALNAME(type, name_obj);
-
-return type;
-}
+PyTypeObject *make_static_property_type();

 #else // PYPY

 /** PyPy has some issues with the above C API, so we evaluate Python code  
instead.
 This function will only be called once so performance isn't really a  
concern.

 Return value: New reference. */
-inline PyTypeObject *make_static_property_type() {
-auto d = dict();
-PyObject *result = PyRun_String(R"(\
-class pybind11_static_property(property):
-def __get__(self, obj, cls):
-return property.__get__(self, cls, cls)
-
-def __set__(self, obj, value):
-cls = obj if isinstance(obj, type) else type(obj)
-property.__set__(self, cls, value)
-)", Py_file_input, d.ptr(), d.ptr()
-);
-if (result == nullptr)
-throw error_already_set();
-Py_DECREF(result);
-return (PyTypeObject *)  
d["pybind11_static_property"].cast().release().ptr();

-}
+PyTypeObject *make_static_property_type();

 #endif // PYPY

@@ -107,35 +52,7 @@
 By default, Python replaces the `static_property` itself, but for  
wrapped C++ types
 we need to call `static_property.__set__()` in order to propagate the  
new value to

 the underlying C++ data structure. */
-extern "C" inline int pybind11_meta_setattro(PyObject* obj, PyObject*  
name, PyObject* value) {
-// Use `_PyType_Lookup()` instead of `PyObject_GetAttr()` in order to  
get the raw
-// descriptor (`property`) instead of calling `tp_descr_get`  
(`property.__get__()`).

-PyObject *descr = _PyType_Lookup((PyTypeObject *) obj, name);
-
-// The following assignment 

[gem5-dev] Change in gem5/gem5[develop]: scons: split pybind11 headers into cpp files -40% build time

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29152 )



Change subject: scons: split pybind11 headers into cpp files -40% build time
..

scons: split pybind11 headers into cpp files -40% build time

This is a proof of concept for now: the build integration might be
improved, and the split can be done more carefully.

This commit splits everything form pybind11 that can go into a cpp files
(i.e. everything except templates) into cpp files.

A related upstream discussion about this can be found at:
https://github.com/pybind/pybind11/issues/708

This reduces the from scratch scons build/ARM/gem5.opt -j8 time by 40%
from 25 minutes to 15 minutes on a Lenovo ThinkPad P51.

Change-Id: I8e61b80031f82b288e64b397ed541f6cbc7be029
---
M ext/pybind11/include/pybind11/attr.h
A ext/pybind11/include/pybind11/cast.cpp
M ext/pybind11/include/pybind11/cast.h
A ext/pybind11/include/pybind11/embed.cpp
M ext/pybind11/include/pybind11/embed.h
A ext/pybind11/include/pybind11/eval.cpp
M ext/pybind11/include/pybind11/eval.h
A ext/pybind11/include/pybind11/iostream.cpp
M ext/pybind11/include/pybind11/iostream.h
A ext/pybind11/include/pybind11/options.cpp
M ext/pybind11/include/pybind11/options.h
A ext/pybind11/include/pybind11/pybind11.cpp
M ext/pybind11/include/pybind11/pybind11.h
A ext/pybind11/include/pybind11/pytypes.cpp
M ext/pybind11/include/pybind11/pytypes.h
15 files changed, 3,271 insertions(+), 2,245 deletions(-)




--
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Gerrit-Branch: develop
Gerrit-Change-Id: I8e61b80031f82b288e64b397ed541f6cbc7be029
Gerrit-Change-Number: 29152
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: scons: quick test la la la la la

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29132 )



Change subject: scons: quick test la la la la la
..

scons: quick test la la la la la

Change-Id: Ieabc268e0ac66dd4469e5586519470b661bee0ec
---
M src/SConscript
1 file changed, 11 insertions(+), 1 deletion(-)



diff --git a/src/SConscript b/src/SConscript
index 134e2a5..e2eed55 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -60,6 +60,14 @@

 Import('*')

+pybind11objs = []
+for path, dirnames, filenames in
+os.walk(Dir('#/ext/pybind11/include/pybind11').get_abspath()):
+for filename in filenames:
+if os.path.splitext(filename)[1] == '.cpp':
+pybind11objs.append(
+base_py_env.Object(os.path.join(path, filename)))
+
 # Children need to see the environment
 Export('env')

@@ -454,6 +462,7 @@
 def declare(self, env, objs=None):
 if objs is None:
 objs = self.srcs_to_objs(env, self.sources)
+objs.extend(pybind11objs)

 env = env.Clone()
 env['BIN_RPATH_PREFIX'] = os.path.relpath(
@@ -1140,7 +1149,8 @@
 # Build a small helper that marshals the Python code using the same
 # version of Python as gem5. This is in an unorthodox location to
 # avoid building it for every variant.
-py_marshal = base_py_env.Program('marshal', 'python/marshal.cc')[0]
+py_marshal = base_py_env.Program('marshal', ['python/marshal.cc'] +
+pybind11objs)[0]

 # Embed python files.  All .py files that have been indicated by a
 # PySource() call in a SConscript need to be embedded into the M5

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[gem5-dev] Change in gem5/gem5[develop]: stats: refactor ScalarPrint and VectorPrint constructors

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28630 )



Change subject: stats: refactor ScalarPrint and VectorPrint constructors
..

stats: refactor ScalarPrint and VectorPrint constructors

This commit is only a refactoring to improve code quality after the need
was felt in the previous commits.

It creates constructors for those classes, and define the parameters that
don't change often across calls in the constructors.

Parameters that change often across calls such as value and name are now
passed to the operator() call directly.

Change-Id: Ibc12ed354e8e949d5a8b9ca23c6958c713f58800
---
M src/base/stats/text.cc
1 file changed, 148 insertions(+), 152 deletions(-)



diff --git a/src/base/stats/text.cc b/src/base/stats/text.cc
index aabcc0c..0ae7953 100644
--- a/src/base/stats/text.cc
+++ b/src/base/stats/text.cc
@@ -223,8 +223,6 @@

 struct ScalarPrint
 {
-Result value;
-string name;
 string desc;
 Flags flags;
 bool descriptions;
@@ -238,7 +236,24 @@
 int pdfstrSpaces;
 int cdfstrSpaces;

-ScalarPrint(bool spaces) : spaces(spaces) {
+ScalarPrint(
+const string ,
+const Flags ,
+bool descriptions,
+bool spaces,
+bool names,
+int precision,
+const Result ,
+const Result 
+) : desc(desc),
+flags(flags),
+descriptions(descriptions),
+spaces(spaces),
+names(names),
+precision(precision),
+pdf(pdf),
+cdf(cdf)
+{
 if (spaces) {
 nameSpaces = 40;
 valueSpaces = 12;
@@ -251,24 +266,34 @@
 cdfstrSpaces = 0;
 }
 }
-void update(Result val, Result total);
-void operator()(ostream , bool oneLine = false,
-bool firstBegin = false) const;
+void update(const Result , const Result );
+void operator()(
+ostream ,
+const string ,
+const Result ,
+bool oneLine = false,
+bool firstBegin = false) const;
 };

 void
-ScalarPrint::update(Result val, Result total)
-{
-value = val;
+ScalarPrint::update(
+const Result ,
+const Result 
+) {
 if (total) {
-pdf = val / total;
+pdf = value / total;
 cdf += pdf;
 }
 }

 void
-ScalarPrint::operator()(ostream , bool oneLine, bool firstBegin)  
const

-{
+ScalarPrint::operator()(
+ostream ,
+const string ,
+const Result ,
+bool oneLine,
+bool firstBegin
+) const {
 if (names && (
 (flags.isSet(nozero) && (!oneLine) && value == 0.0) ||
 (flags.isSet(nonan) && std::isnan(value))
@@ -306,7 +331,6 @@

 struct VectorPrint
 {
-string name;
 string separatorString;
 string desc;
 vector subnames;
@@ -316,24 +340,50 @@
 bool spaces;
 bool names;
 int precision;
-VResult vec;
-Result total;
 bool forceSubnames;
 int nameSpaces;

-VectorPrint() = delete;
-VectorPrint(bool spaces) : spaces(spaces) {
+VectorPrint(
+const string ,
+const string ,
+const Flags ,
+bool descriptions,
+bool spaces,
+bool names,
+int precision,
+bool forceSubnames
+) : separatorString(separatorString),
+desc(desc),
+flags(flags),
+descriptions(descriptions),
+spaces(spaces),
+names(names),
+precision(precision),
+forceSubnames(forceSubnames)
+{
 if (spaces) {
 nameSpaces = 40;
 } else {
 nameSpaces = 0;
 }
 }
-void operator()(ostream , bool firstBegin) const;
+void operator()(
+ostream ,
+const string ,
+const VResult ,
+const Result ,
+bool firstBegin
+) const;
 };

 void
-VectorPrint::operator()(std::ostream , bool firstBegin) const
+VectorPrint::operator()(
+ostream ,
+const string ,
+const VResult ,
+const Result ,
+bool firstBegin
+) const
 {
 size_type _size = vec.size();
 Result _total = 0.0;
@@ -346,15 +396,16 @@

 string base = name + separatorString;

-ScalarPrint print(spaces);
-print.name = name;
-print.names = names;
-print.desc = desc;
-print.precision = precision;
-print.descriptions = descriptions;
-print.flags = flags;
-print.pdf = _total ? 0.0 : NAN;
-print.cdf = _total ? 0.0 : NAN;
+ScalarPrint print(
+desc,
+flags,
+descriptions,
+spaces,
+names,
+precision,
+_total ? 0.0 : NAN,
+_total ? 0.0 : NAN
+);

 bool havesub = !subnames.empty();

@@ -362,10 +413,14 @@
 // If forceSubnames is set, get the first subname (or index in
 // the case where there are no subnames) and append it to the
 // base name.
-if (forceSubnames)
-print.name = base + 

[gem5-dev] Change in gem5/gem5[develop]: stats: add --stats-root option to dump only under some SimObjects

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28628 )



Change subject: stats: add --stats-root option to dump only under some  
SimObjects

..

stats: add --stats-root option to dump only under some SimObjects

This commit makes it possible to make invocations such as:

gem5.opt --stats-root 'system.cpu[:].dtb' --stats-root 'system.membus'

When --stats-root is given, only stats that are under any of the root
SimObjects get dumped. E.g. the above invocation would dump stats such as:

system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED
system.membus.pwrStateResidencyTicks::UNDEFINED
system.membus.trans_dist::ReadReq

but not for example `system.clk_domain.clock`.

If the --stats-root is given, only new stats as defined at:
Idc8ff448b9f70a796427b4a5231e7371485130b4 get dumped, and old ones are
ignored. The commits following that one have done some initial conversion
work, but many stats are still in the old format.

Change-Id: Iadaef26edf9a678b39f774515600884fbaeec497
---
M src/python/m5/SimObject.py
M src/python/m5/main.py
M src/python/m5/simulate.py
M src/python/m5/stats/__init__.py
4 files changed, 52 insertions(+), 20 deletions(-)



diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index a045fb7..561e4b8 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2017-2019 ARM Limited
+# Copyright (c) 2017-2020 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -1071,6 +1071,9 @@
 out.extend(sim_object[i] for i in _range)
 return SimObjectCliWrapper(out)

+def getSimObjects(self):
+return self._sim_objects
+
 # The SimObject class is the root of the special hierarchy.  Most of
 # the code in this class deals with the configuration hierarchy itself
 # (parent/child node relationships).
@@ -1695,6 +1698,10 @@
 for param in params:
 exec(param, d)

+def get_simobj(self, simobj_path):
+d = self._apply_config_get_dict()
+return eval(simobj_path, d).getSimObjects()
+
 # Function to provide to C++ so it can look up instances based on paths
 def resolveSimObject(name):
 obj = instanceDict[name]
diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index 6fe9218..781f3a9 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016, 2019 Arm Limited
+# Copyright (c) 2016, 2019-2020 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -118,6 +118,14 @@
 option("--stats-help",
action="callback", callback=_stats_help,
help="Display documentation for available stat visitors")
+option("--stats-root", action="append", default=[], help=
+"If given, dump only stats of objects under the given SimObject. "
+"SimObjects are identified with Python notation as in: "
+"system.cpu[0].dtb. All elements of an array can be selected at "
+"once with: system.cpu[:].dtb. If given multiple times, dump  
stats "

+"that are present under any of the roots. If not given, dump all "
+"stats. "
+)

 # Configuration Options
 group("Configuration Options")
diff --git a/src/python/m5/simulate.py b/src/python/m5/simulate.py
index 3317ae8..629c054 100644
--- a/src/python/m5/simulate.py
+++ b/src/python/m5/simulate.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012,2019 ARM Limited
+# Copyright (c) 2012,2019-2020 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -52,6 +52,7 @@
 from . import SimObject
 from . import ticks
 from . import objects
+import m5
 from m5.util.dot_writer import do_dot, do_dvfs_dot
 from m5.util.dot_writer_ruby import do_ruby_dot

@@ -139,6 +140,12 @@
 # We're done registering statistics.  Enable the stats package now.
 stats.enable()

+# Setup global stat filtering.
+stat_root_simobjs = []
+for stat_root_str in m5.options.stats_root:
+stat_root_simobjs.extend(root.get_simobj(stat_root_str))
+m5.stats.global_dump_roots = stat_root_simobjs
+
 # Restore checkpoint (if any)
 if ckpt_dir:
 _drain_manager.preCheckpointRestore()
diff --git a/src/python/m5/stats/__init__.py  
b/src/python/m5/stats/__init__.py

index 1e37a14..6c4a42c 100644
--- a/src/python/m5/stats/__init__.py
+++ b/src/python/m5/stats/__init__.py
@@ -326,35 +326,45 @@
 # New stats
 _visit_stats(lambda g, s: s.prepare())

-def _dump_to_visitor(visitor, root=None):
-# Legacy stats
-if root is None:
-for stat in stats_list:
-stat.visit(visitor)
-
+def _dump_to_visitor(visitor, roots=None):
 # New stats
 def dump_group(group):
  

[gem5-dev] Change in gem5/gem5[develop]: stats: add option to remove names from all stats but first dump

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28629 )



Change subject: stats: add option to remove names from all stats but first  
dump

..

stats: add option to remove names from all stats but first dump

With:

--stats-file stats.txt?names=False

names are only printed on the first dump of the run, e.g.:

-- Begin Simulation Statistics --
system.cpu0.Branches 21667
system.cpu0.committedInsts 105034
-- End Simulation Statistics   --

-- Begin Simulation Statistics --
21673
105054
-- End Simulation Statistics   --

-- Begin Simulation Statistics --
21683
105094
-- End Simulation Statistics   --

For this to work, stats that were omitted due to the nozero and nonan must
always be printed however to have the same number of lines per dump, but I
have observed a 5x reduction in dump sizes in a simple se.py loop setup, so
it is still highly worth it in that setup.

The use case is for users that are already post-processing the dumps after
the run is over to datamine it, so they don't need the names every time
for visual inspection.

Change-Id: Ibe589997511536bdc9f510e78b5e99bd09fff0bc
---
M src/base/stats/hdf5.cc
M src/base/stats/hdf5.hh
M src/base/stats/output.hh
M src/base/stats/text.cc
M src/base/stats/text.hh
M src/python/m5/stats/__init__.py
6 files changed, 85 insertions(+), 51 deletions(-)



diff --git a/src/base/stats/hdf5.cc b/src/base/stats/hdf5.cc
index 963be6e..ca1ce22 100644
--- a/src/base/stats/hdf5.cc
+++ b/src/base/stats/hdf5.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019 Arm Limited
+ * Copyright (c) 2016-2020 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -83,7 +83,7 @@
 }

 void
-Hdf5::end()
+Hdf5::doEnd()
 {
 assert(valid());

diff --git a/src/base/stats/hdf5.hh b/src/base/stats/hdf5.hh
index 8944a55..89be2c9 100644
--- a/src/base/stats/hdf5.hh
+++ b/src/base/stats/hdf5.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019 Arm Limited
+ * Copyright (c) 2016-2020 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -63,7 +63,7 @@

   public: // Output interface
 void begin() override;
-void end() override;
+void doEnd() override;
 bool valid() const override;

 void beginGroup(const char *name) override;
diff --git a/src/base/stats/output.hh b/src/base/stats/output.hh
index 6ff4a5d..df70f27 100644
--- a/src/base/stats/output.hh
+++ b/src/base/stats/output.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019 Arm Limited
+ * Copyright (c) 2019-2020 Arm Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -57,10 +57,19 @@

 struct Output
 {
+  protected:
+bool firstBegin;
+
+  public:
+Output() : firstBegin(true) {}
 virtual ~Output() {}

 virtual void begin() = 0;
-virtual void end() = 0;
+void end() {
+doEnd();
+firstBegin = false;
+}
+virtual void doEnd() = 0;
 virtual bool valid() const = 0;

 virtual void beginGroup(const char *name) = 0;
diff --git a/src/base/stats/text.cc b/src/base/stats/text.cc
index fa342a2..aabcc0c 100644
--- a/src/base/stats/text.cc
+++ b/src/base/stats/text.cc
@@ -95,7 +95,8 @@
 std::list ();

 Text::Text()
-: mystream(false), stream(NULL), descriptions(false), spaces(false)
+: mystream(false), stream(NULL), descriptions(false), spaces(false),
+  names(false)
 {
 }

@@ -155,7 +156,7 @@
 }

 void
-Text::end()
+Text::doEnd()
 {
 ccprintf(*stream, "\n-- End Simulation Statistics
--\n");

 stream->flush();
@@ -228,6 +229,7 @@
 Flags flags;
 bool descriptions;
 bool spaces;
+bool names;
 int precision;
 Result pdf;
 Result cdf;
@@ -250,7 +252,8 @@
 }
 }
 void update(Result val, Result total);
-void operator()(ostream , bool oneLine = false) const;
+void operator()(ostream , bool oneLine = false,
+bool firstBegin = false) const;
 };

 void
@@ -264,10 +267,12 @@
 }

 void
-ScalarPrint::operator()(ostream , bool oneLine) const
+ScalarPrint::operator()(ostream , bool oneLine, bool firstBegin)  
const

 {
-if ((flags.isSet(nozero) && (!oneLine) && value == 0.0) ||
-(flags.isSet(nonan) && std::isnan(value)))
+if (names && (
+(flags.isSet(nozero) && (!oneLine) && value == 0.0) ||
+(flags.isSet(nonan) && std::isnan(value))
+))
 return;

 stringstream pdfstr, cdfstr;
@@ -281,7 +286,9 @@
 if (oneLine) {
 ccprintf(stream, " |");
 } else {
-ccprintf(stream, "%-*s ", nameSpaces, name);
+if (names || firstBegin) {
+ccprintf(stream, "%-*s ", nameSpaces, name);
+}
 }
 ccprintf(stream, 

[gem5-dev] Change in gem5/gem5[develop]: stats: add option to disable alignment spaces in stats.txt file

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28627 )



Change subject: stats: add option to disable alignment spaces in stats.txt  
file

..

stats: add option to disable alignment spaces in stats.txt file

The alignment spaces in stats.txt takes up a lot of space and increases
simulation time, this commit adds the option to disable them with:

--stats-file stats.txt?spaces=False

Sample old lines with ?desc=False:

system.cpu.op_class::FloatMultAcc   0  0.00% 65.92%
system.cpu.op_class::FloatDiv   0  0.00% 65.92%

Sample new lines with ?desc=False;spaces=False:

system.cpu.op_class::FloatMultAcc 0 0.00% 65.92%
system.cpu.op_class::FloatDiv 0 0.00% 65.92%

On a 1000 dumpstats m5op loop spaces=False reduces:

* size: from 38MB to 20MB
* time: from 4.5s to 3.5s

Change-Id: Ib738b996b5646c329094cf61aaa1d977e844e759
---
M src/base/stats/text.cc
M src/base/stats/text.hh
M src/python/m5/stats/__init__.py
3 files changed, 71 insertions(+), 28 deletions(-)



diff --git a/src/base/stats/text.cc b/src/base/stats/text.cc
index 96cbe34..fa342a2 100644
--- a/src/base/stats/text.cc
+++ b/src/base/stats/text.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019 Arm Limited
+ * Copyright (c) 2019-2020 Arm Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -95,18 +95,16 @@
 std::list ();

 Text::Text()
-: mystream(false), stream(NULL), descriptions(false)
+: mystream(false), stream(NULL), descriptions(false), spaces(false)
 {
 }

-Text::Text(std::ostream )
-: mystream(false), stream(NULL), descriptions(false)
+Text::Text(std::ostream ) : Text()
 {
 open(stream);
 }

-Text::Text(const std::string )
-: mystream(false), stream(NULL), descriptions(false)
+Text::Text(const std::string ) : Text()
 {
 open(file);
 }
@@ -229,10 +227,28 @@
 string desc;
 Flags flags;
 bool descriptions;
+bool spaces;
 int precision;
 Result pdf;
 Result cdf;
+int nameSpaces;
+int valueSpaces;
+int pdfstrSpaces;
+int cdfstrSpaces;

+ScalarPrint(bool spaces) : spaces(spaces) {
+if (spaces) {
+nameSpaces = 40;
+valueSpaces = 12;
+pdfstrSpaces = 10;
+cdfstrSpaces = 10;
+} else {
+nameSpaces = 0;
+valueSpaces = 0;
+pdfstrSpaces = 0;
+cdfstrSpaces = 0;
+}
+}
 void update(Result val, Result total);
 void operator()(ostream , bool oneLine = false) const;
 };
@@ -263,12 +279,16 @@
 ccprintf(cdfstr, "%.2f%%", cdf * 100.0);

 if (oneLine) {
-ccprintf(stream, " |%12s %10s %10s",
- ValueToString(value, precision), pdfstr.str(),  
cdfstr.str());

+ccprintf(stream, " |");
 } else {
-ccprintf(stream, "%-40s %12s %10s %10s", name,
- ValueToString(value, precision), pdfstr.str(),  
cdfstr.str());

-
+ccprintf(stream, "%-*s ", nameSpaces, name);
+}
+ccprintf(stream, "%*s", valueSpaces, ValueToString(value, precision));
+if (spaces || pdfstr.rdbuf()->in_avail())
+ccprintf(stream, " %*s", pdfstrSpaces, pdfstr.str());
+if (spaces || cdfstr.rdbuf()->in_avail())
+ccprintf(stream, " %*s", cdfstrSpaces, cdfstr.str());
+if (!oneLine) {
 if (descriptions) {
 if (!desc.empty())
 ccprintf(stream, " # %s", desc);
@@ -286,11 +306,21 @@
 vector subdescs;
 Flags flags;
 bool descriptions;
+bool spaces;
 int precision;
 VResult vec;
 Result total;
 bool forceSubnames;
+int nameSpaces;

+VectorPrint() = delete;
+VectorPrint(bool spaces) : spaces(spaces) {
+if (spaces) {
+nameSpaces = 40;
+} else {
+nameSpaces = 0;
+}
+}
 void operator()(ostream ) const;
 };

@@ -308,7 +338,7 @@

 string base = name + separatorString;

-ScalarPrint print;
+ScalarPrint print(spaces);
 print.name = name;
 print.desc = desc;
 print.precision = precision;
@@ -332,7 +362,7 @@

 if ((!flags.isSet(nozero)) || (total != 0)) {
 if (flags.isSet(oneline)) {
-ccprintf(stream, "%-40s", name);
+ccprintf(stream, "%-*s", nameSpaces, name);
 print.flags = print.flags & (~nozero);
 }

@@ -373,7 +403,9 @@
 string desc;
 Flags flags;
 bool descriptions;
+bool spaces;
 int precision;
+int nameSpaces;

 const DistData 

@@ -389,8 +421,8 @@
 init(text, info);
 }

-DistPrint::DistPrint(const Text *text, const VectorDistInfo , int i)
-: data(info.data[i])
+DistPrint::DistPrint(const Text *text, const VectorDistInfo ,
+int i) : data(info.data[i])
 {
 init(text, info);

@@ -411,6 +443,12 @@
 flags = info.flags;
 

[gem5-dev] Change in gem5/gem5[develop]: sim-se: ignore all scheduler related syscalls for arm

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28591 )



Change subject: sim-se: ignore all scheduler related syscalls for arm
..

sim-se: ignore all scheduler related syscalls for arm

With the simplistic syscall emulation fork algorithm that we currently have
of running one thread per call, those calls simply cannot be reasonably
implemented.

However, content can often still work without them.

Change-Id: Iac88dfd055564c47b7a7b6898b7582cf4087f708
---
M src/arch/arm/linux/process.cc
1 file changed, 18 insertions(+), 18 deletions(-)



diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc
index 55141ba..4c679b3 100644
--- a/src/arch/arm/linux/process.cc
+++ b/src/arch/arm/linux/process.cc
@@ -290,14 +290,14 @@
 { base + 151, "munlock" },
 { base + 152, "mlockall" },
 { base + 153, "munlockall" },
-{ base + 154, "sched_setparam" },
-{ base + 155, "sched_getparam" },
-{ base + 156, "sched_setscheduler" },
-{ base + 157, "sched_getscheduler" },
-{ base + 158, "sched_yield" },
-{ base + 159, "sched_get_priority_max" },
-{ base + 160, "sched_get_priority_min" },
-{ base + 161, "sched_rr_get_interval" },
+{ base + 154, "sched_setparam", ignoreWarnOnceFunc },
+{ base + 155, "sched_getparam", ignoreWarnOnceFunc },
+{ base + 156, "sched_setscheduler", ignoreWarnOnceFunc },
+{ base + 157, "sched_getscheduler", ignoreWarnOnceFunc },
+{ base + 158, "sched_yield", ignoreWarnOnceFunc },
+{ base + 159, "sched_get_priority_max", ignoreWarnOnceFunc },
+{ base + 160, "sched_get_priority_min", ignoreWarnOnceFunc },
+{ base + 161, "sched_rr_get_interval", ignoreWarnOnceFunc },
 { base + 162, "nanosleep", ignoreWarnOnceFunc },
 { base + 163, "mremap", mremapFunc }, // ARM-specific
 { base + 164, "setresuid" },
@@ -375,7 +375,7 @@
 { base + 238, "tkill" },
 { base + 239, "sendfile64" },
 { base + 240, "futex", futexFunc },
-{ base + 241, "sched_setaffinity" },
+{ base + 241, "sched_setaffinity", ignoreWarnOnceFunc },
 { base + 242, "sched_getaffinity", ignoreFunc },
 { base + 243, "io_setup" },
 { base + 244, "io_destroy" },
@@ -631,16 +631,16 @@
 {  base + 115, "clock_nanosleep" },
 {  base + 116, "syslog" },
 {  base + 117, "ptrace" },
-{  base + 118, "sched_setparam" },
-{  base + 119, "sched_setscheduler" },
-{  base + 120, "sched_getscheduler" },
-{  base + 121, "sched_getparam" },
-{  base + 122, "sched_setaffinity" },
+{  base + 118, "sched_setparam", ignoreWarnOnceFunc },
+{  base + 119, "sched_setscheduler", ignoreWarnOnceFunc },
+{  base + 120, "sched_getscheduler", ignoreWarnOnceFunc },
+{  base + 121, "sched_getparam", ignoreWarnOnceFunc },
+{  base + 122, "sched_setaffinity", ignoreWarnOnceFunc },
 {  base + 123, "sched_getaffinity", ignoreFunc },
-{  base + 124, "sched_yield" },
-{  base + 125, "sched_get_priority_max" },
-{  base + 126, "sched_get_priority_min" },
-{  base + 127, "sched_rr_get_interval" },
+{  base + 124, "sched_yield", ignoreWarnOnceFunc },
+{  base + 125, "sched_get_priority_max", ignoreWarnOnceFunc },
+{  base + 126, "sched_get_priority_min", ignoreWarnOnceFunc },
+{  base + 127, "sched_rr_get_interval", ignoreWarnOnceFunc },
 {  base + 128, "restart_syscall" },
 {  base + 129, "kill", ignoreFunc },
 {  base + 130, "tkill" },

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Gerrit-Branch: develop
Gerrit-Change-Id: Iac88dfd055564c47b7a7b6898b7582cf4087f708
Gerrit-Change-Number: 28591
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli 
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[gem5-dev] Change in gem5/gem5[develop]: sim-se: implement the getcpu syscall

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28590 )



Change subject: sim-se: implement the getcpu syscall
..

sim-se: implement the getcpu syscall

Change-Id: I63a1384646829b8cf68453c42aed6a7d12172787
---
M src/arch/arm/linux/process.cc
M src/arch/x86/linux/process.cc
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
4 files changed, 21 insertions(+), 6 deletions(-)



diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc
index b5b6553..55141ba 100644
--- a/src/arch/arm/linux/process.cc
+++ b/src/arch/arm/linux/process.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, 2015 ARM Limited
+ * Copyright (c) 2010-2013, 2015, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -476,7 +476,7 @@
 { base + 342, "tee" },
 { base + 343, "vmsplice" },
 { base + 344, "move_pages" },
-{ base + 345, "getcpu" },
+{ base + 345, "getcpu", getcpuFunc },
 { base + 346, "epoll_pwait" },
 { base + 347, "sys_kexec_load" },
 { base + 348, "sys_utimensat" },
@@ -681,7 +681,7 @@
 {  base + 165, "getrusage", getrusageFunc },
 {  base + 166, "umask" },
 {  base + 167, "prctl" },
-{  base + 168, "getcpu" },
+{  base + 168, "getcpu", getcpuFunc },
 {  base + 169, "gettimeofday", gettimeofdayFunc },
 {  base + 170, "settimeofday" },
 {  base + 171, "adjtimex" },
diff --git a/src/arch/x86/linux/process.cc b/src/arch/x86/linux/process.cc
index 6b50dbf..2c594e7 100644
--- a/src/arch/x86/linux/process.cc
+++ b/src/arch/x86/linux/process.cc
@@ -566,7 +566,7 @@
 { 306, "syncfs" },
 { 307, "sendmmsg" },
 { 308, "setns" },
-{ 309, "getcpu" },
+{ 309, "getcpu", getcpuFunc },
 { 310, "proess_vm_readv" },
 { 311, "proess_vm_writev" },
 { 312, "kcmp" },
@@ -914,7 +914,7 @@
 { 315, "tee" },
 { 316, "vmsplice" },
 { 317, "move_pages" },
-{ 318, "getcpu" },
+{ 318, "getcpu", getcpuFunc },
 { 319, "epoll_pwait" },
 { 320, "utimensat" },
 { 321, "signalfd" },
diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc
index bffedfd..918a7bd 100644
--- a/src/sim/syscall_emul.cc
+++ b/src/sim/syscall_emul.cc
@@ -1633,3 +1633,15 @@
 return (status == -1) ? -errno : status;
 }

+SyscallReturn
+getcpuFunc(SyscallDesc *desc, ThreadContext *tc,
+   Addr cpu_ptr, Addr node_ptr, Addr tcache_ptr)
+{
+// unsigned is the same size (4) on all Linux supported ISAs.
+uint32_t result = htog(tc->contextId(),
+tc->getSystemPtr()->getGuestByteOrder());
+BufferArg result_buf(cpu_ptr, sizeof(result));
+memcpy(result_buf.bufferPtr(), , sizeof(result));
+result_buf.copyOut(tc->getVirtProxy());
+return 0;
+}
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 5bd9f54..bb3b418 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013, 2015, 2019 ARM Limited
+ * Copyright (c) 2012-2013, 2015, 2019-2020 ARM Limited
  * Copyright (c) 2015 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -354,6 +354,9 @@
  int tgt_fd, int level, int optname,
  Addr valPtr, socklen_t len);

+SyscallReturn getcpuFunc(SyscallDesc *desc, ThreadContext *tc,
+Addr cpu_ptr, Addr node_ptr, Addr tcache_ptr);
+
 // Target getsockname() handler.
 SyscallReturn getsocknameFunc(SyscallDesc *desc, ThreadContext *tc,
   int tgt_fd, Addr addrPtr, Addr lenPtr);

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Gerrit-Change-Id: I63a1384646829b8cf68453c42aed6a7d12172787
Gerrit-Change-Number: 28590
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Gerrit-Owner: Ciro Santilli 
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: show names on --debug-flags MiscRegs write:

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28467 )


Change subject: arch-arm: show names on --debug-flags MiscRegs write:
..

arch-arm: show names on --debug-flags MiscRegs write:

Before this commit it would show only numbers:

Writing to misc reg 19 (19) : 0x74178

and now it also shows the name:

Writing MiscReg lockaddr (19 19) : 0x74178

MiscReg reads were already showing names and are unchanged, e.g.:

Reading MiscReg sctlr_el1 with clear res1 bits: 0x18100800

Change-Id: If46da88359ce4a549a6a50080a2b13077d41e373
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28467
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/isa.cc
1 file changed, 4 insertions(+), 4 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b3d6726..b18bbb0 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -787,12 +787,12 @@
 if (upper > 0) {
 miscRegs[lower] = bits(v, 31, 0);
 miscRegs[upper] = bits(v, 63, 32);
-DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
-misc_reg, lower, upper, v);
+DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d:%d) : %#x\n",
+miscRegName[misc_reg], misc_reg, lower, upper, v);
 } else {
 miscRegs[lower] = v;
-DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
-misc_reg, lower, v);
+DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d) : %#x\n",
+miscRegName[misc_reg], misc_reg, lower, v);
 }
 }


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Gerrit-Branch: develop
Gerrit-Change-Id: If46da88359ce4a549a6a50080a2b13077d41e373
Gerrit-Change-Number: 28467
Gerrit-PatchSet: 2
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: show names on --debug-flags MiscRegs write:

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28467 )



Change subject: arch-arm: show names on --debug-flags MiscRegs write:
..

arch-arm: show names on --debug-flags MiscRegs write:

Before this commit it would show only numbers:

Writing to misc reg 19 (19) : 0x74178

and now it also shows the name:

Writing MiscReg lockaddr (19 19) : 0x74178

MiscReg reads were already showing names and are unchanged, e.g.:

Reading MiscReg sctlr_el1 with clear res1 bits: 0x18100800

Change-Id: If46da88359ce4a549a6a50080a2b13077d41e373
---
M src/arch/arm/isa.cc
1 file changed, 4 insertions(+), 4 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b3d6726..b18bbb0 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -787,12 +787,12 @@
 if (upper > 0) {
 miscRegs[lower] = bits(v, 31, 0);
 miscRegs[upper] = bits(v, 63, 32);
-DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
-misc_reg, lower, upper, v);
+DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d:%d) : %#x\n",
+miscRegName[misc_reg], misc_reg, lower, upper, v);
 } else {
 miscRegs[lower] = v;
-DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
-misc_reg, lower, v);
+DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d) : %#x\n",
+miscRegName[misc_reg], misc_reg, lower, v);
 }
 }


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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: fix Exec trace decode of ARM atomic instructions

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28449 )



Change subject: arch-arm: fix Exec trace decode of ARM atomic instructions
..

arch-arm: fix Exec trace decode of ARM atomic instructions

For example an STXR:

stxr w2, x1, [x0]

was decoding as:

stxr   x1, x2, [x0]

and now it decodes as:

stxr   x2, x1, [x0]

The w vs x part is still wrong and is not fixed by this patch.

MemoryEx64 seems to be the base class of all atomic instructions,
and I've verified that e.g. LDADD was also wrong and is now fixed.

Change-Id: Ic3bcb6a1d9b18f33dde5db369ac3903b443e53ae
JIRA: https://gem5.atlassian.net/browse/GEM5-484
---
M src/arch/arm/insts/mem64.cc
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/insts/mem64.cc b/src/arch/arm/insts/mem64.cc
index 0ddda95..9d4c391 100644
--- a/src/arch/arm/insts/mem64.cc
+++ b/src/arch/arm/insts/mem64.cc
@@ -182,9 +182,9 @@
 {
 std::stringstream ss;
 printMnemonic(ss, "", false);
-printIntReg(ss, dest);
-ccprintf(ss, ", ");
 printIntReg(ss, result);
+ccprintf(ss, ", ");
+printIntReg(ss, dest);
 ccprintf(ss, ", [");
 printIntReg(ss, base);
 ccprintf(ss, "]");

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Gerrit-Change-Id: Ic3bcb6a1d9b18f33dde5db369ac3903b443e53ae
Gerrit-Change-Number: 28449
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Gerrit-Owner: Ciro Santilli 
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[gem5-dev] Change in gem5/gem5[develop]: mem: make MemTest panic on a packet error

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26804 )


Change subject: mem: make MemTest panic on a packet error
..

mem: make MemTest panic on a packet error

Before this change, running:

./build/NULL/gem5.opt configs/example/ruby_mem_test.py -m 2000 \
  --functional 10

would only print warning for memory errors such as:

warn: Read access failed at 0x107a00

and there was no way to make the simulation fail.

This commit makes those warnings into errors such as:

panic: Read access failed at 0x107a00

unless --suppress-func-errors is given.

This will be used to automate MemTest testing in later commits.

Change-Id: I1840c1ed1853f1a71ec73bd50cadaac095794f91
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26804
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/example/ruby_mem_test.py
M src/cpu/testers/memtest/MemTest.py
M src/cpu/testers/memtest/memtest.cc
M src/cpu/testers/memtest/memtest.hh
M tests/configs/memtest-ruby.py
5 files changed, 12 insertions(+), 13 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/example/ruby_mem_test.py  
b/configs/example/ruby_mem_test.py

index 5325c50..310ee3c 100644
--- a/configs/example/ruby_mem_test.py
+++ b/configs/example/ruby_mem_test.py
@@ -55,8 +55,8 @@
 parser.add_option("--num-dmas", type="int", default=0, help="# of dma  
testers")

 parser.add_option("--functional", type="int", default=0,
   help="percentage of accesses that should be functional")
-parser.add_option("--suppress-func-warnings", action="store_true",
-  help="suppress warnings when functional accesses fail")
+parser.add_option("--suppress-func-errors", action="store_true",
+  help="suppress panic when functional accesses fail")

 #
 # Add the ruby specific and protocol specific options
@@ -96,7 +96,7 @@
  percent_functional = options.functional,
  percent_uncacheable = 0,
  progress_interval = options.progress,
- suppress_func_warnings = options.suppress_func_warnings) \
+ suppress_func_errors = options.suppress_func_errors) \
  for i in range(options.num_cpus) ]

 system = System(cpu = cpus,
@@ -108,8 +108,8 @@
  percent_functional = 0,
  percent_uncacheable = 0,
  progress_interval = options.progress,
- suppress_func_warnings =
-not  
options.suppress_func_warnings) \

+ suppress_func_errors =
+not options.suppress_func_errors) \
  for i in range(options.num_dmas) ]
 system.dma_devices = dmas
 else:
diff --git a/src/cpu/testers/memtest/MemTest.py  
b/src/cpu/testers/memtest/MemTest.py

index 463c553..36bc929 100644
--- a/src/cpu/testers/memtest/MemTest.py
+++ b/src/cpu/testers/memtest/MemTest.py
@@ -69,5 +69,5 @@

 # Add the ability to supress error responses on functional
 # accesses as Ruby needs this
-suppress_func_warnings = Param.Bool(False, "Suppress warnings when "\
+suppress_func_errors = Param.Bool(False, "Suppress panic when "\
 "functional accesses fail.")
diff --git a/src/cpu/testers/memtest/memtest.cc  
b/src/cpu/testers/memtest/memtest.cc

index 262f1a9..720b273 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -99,7 +99,7 @@
   nextProgressMessage(p->progress_interval),
   maxLoads(p->max_loads),
   atomic(p->system->isAtomicMode()),
-  suppressFuncWarnings(p->suppress_func_warnings)
+  suppressFuncErrors(p->suppress_func_errors)
 {
 id = TESTER_ALLOCATOR++;
 fatal_if(id >= blockSize, "Too many testers, only %d allowed\n",
@@ -146,10 +146,9 @@
 const uint8_t *pkt_data = pkt->getConstPtr();

 if (pkt->isError()) {
-if (!functional || !suppressFuncWarnings) {
-warn("%s access failed at %#x\n",
- pkt->isWrite() ? "Write" : "Read", req->getPaddr());
-}
+if (!functional || !suppressFuncErrors)
+panic( "%s access failed at %#x\n",
+pkt->isWrite() ? "Write" : "Read", req->getPaddr());
 } else {
 if (pkt->isRead()) {
 uint8_t ref_data = referenceData[req->getPaddr()];
diff --git a/src/cpu/testers/memtest/memtest.hh  
b/src/cpu/testers/memtest/memtest.hh

index 86ac6e4..fa13c0a 100644
--- a/src/cpu/testers/memtest/memtest.hh
+++ b/src/cpu/testers/memtest/memtest.hh
@@ -165,7 +165,7 @@

 const bool atomic;

-const bool suppressFuncWarnings;
+const bool suppressFuncErrors;

 Stats::Scalar numReadsStat;
 Stats::Scalar 

[gem5-dev] Change in gem5/gem5[develop]: configs: remove exec of Options.py from ruby_mem_test.py

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26803 )


Change subject: configs: remove exec of Options.py from ruby_mem_test.py
..

configs: remove exec of Options.py from ruby_mem_test.py

The removed exec statement does not appear to be needed however,
since Options is already imported above with:

from common import Options

Change-Id: I934a65d21fa5099a786224a5476d609e4d707205
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26803
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/example/ruby_mem_test.py
1 file changed, 0 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/example/ruby_mem_test.py  
b/configs/example/ruby_mem_test.py

index 070cb37..5325c50 100644
--- a/configs/example/ruby_mem_test.py
+++ b/configs/example/ruby_mem_test.py
@@ -63,10 +63,6 @@
 #
 Ruby.define_options(parser)

-exec(compile( \
-open(os.path.join(config_root, "common", "Options.py")).read(), \
-os.path.join(config_root, "common", "Options.py"), 'exec'))
-
 (options, args) = parser.parse_args()

 #

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I934a65d21fa5099a786224a5476d609e4d707205
Gerrit-Change-Number: 26803
Gerrit-PatchSet: 3
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Daniel Carvalho 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests: create tests for various traffic generators on NULL

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26808 )


Change subject: tests: create tests for various traffic generators on NULL
..

tests: create tests for various traffic generators on NULL

New tests were added for:

- garnet_synth_traffic.py
- ruby_random_test.py
- ruby_direct_test.py

These tests are factored out with the tests for:

- memcheck.py
- ruby_mem_test.py

Each new test was calibrated to last about 5 seconds on a Lenovo ThinkPad
P51.

Change-Id: Ie13d3963e1163cffae5dce329b623fbebbf2b983
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26808
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M tests/gem5/memory/test.py
1 file changed, 18 insertions(+), 9 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/gem5/memory/test.py b/tests/gem5/memory/test.py
index af3af5c..2a4eeb3 100644
--- a/tests/gem5/memory/test.py
+++ b/tests/gem5/memory/test.py
@@ -66,12 +66,21 @@
 valid_isas=(constants.null_tag,),
 )

-gem5_verify_config(
-name='test-memcheck',
-fixtures=(),
-verifiers=(),
-config=joinpath(config.base_dir, 'configs', 'example','memcheck.py'),
-config_args=['--maxtick', '20', '--prefetchers'],
-valid_isas=('NULL',),
-valid_hosts=constants.supported_hosts,
-)
+null_tests = [
+('garnet_synth_traffic', ['--sim-cycles', '500']),
+('memcheck', ['--maxtick', '20', '--prefetchers']),
+('ruby_random_test', ['--maxloads', '5000']),
+('ruby_direct_test', ['--requests', '5']),
+]
+
+for basename_noext, args in null_tests:
+gem5_verify_config(
+name=basename_noext,
+fixtures=(),
+verifiers=(),
+config=joinpath(config.base_dir, 'configs',
+'example', basename_noext + '.py'),
+config_args=args,
+valid_isas=('NULL',),
+valid_hosts=constants.supported_hosts,
+)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie13d3963e1163cffae5dce329b623fbebbf2b983
Gerrit-Change-Number: 26808
Gerrit-PatchSet: 4
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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