[gem5-dev] Change in gem5/gem5[develop]: sim: Fix Mempool overrides during checkpoint
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/56969 )
Change subject: sim: Fix Mempool overrides during checkpoint
..
sim: Fix Mempool overrides during checkpoint
This patch fixes the problem during checkpoing where the mempool is not
restored, but using only the one specified in the config file as a new
execution.
In order to fix that this changes modifyies the serialize/unserialize
functions for mempools and create new funcionts on se_workload to make
sure mempools ends up in the m5.cpt.
We change as well the unserialize mempool function to update
according the checkpoint file so the execution starts with the same
free pages and free pointers.
JIRA: https://gem5.atlassian.net/browse/GEM5-1191
Change-Id: I289bf91eb4f01d9c01a31a39b968e30f8b8d2bdc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56969
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/sim/mem_pool.cc
M src/sim/process.cc
M src/sim/se_workload.cc
M src/sim/se_workload.hh
4 files changed, 46 insertions(+), 0 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/mem_pool.cc b/src/sim/mem_pool.cc
index 20b6eda..d58399d 100644
--- a/src/sim/mem_pool.cc
+++ b/src/sim/mem_pool.cc
@@ -169,6 +169,7 @@
void
MemPools::serialize(CheckpointOut ) const
{
+ScopedCheckpointSection sec(cp, "mempools");
int num_pools = pools.size();
SERIALIZE_SCALAR(num_pools);
@@ -179,6 +180,10 @@
void
MemPools::unserialize(CheckpointIn )
{
+// Delete previous mem_pools
+pools.clear();
+
+ScopedCheckpointSection sec(cp, "mempools");
int num_pools = 0;
UNSERIALIZE_SCALAR(num_pools);
diff --git a/src/sim/process.cc b/src/sim/process.cc
index 3a631a5..97130bd 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -388,6 +388,7 @@
memState->unserialize(cp);
pTable->unserialize(cp);
fds->unserialize(cp);
+
/**
* Checkpoints for pipes, device drivers or sockets currently
* do not work. Need to come back and fix them at a later date.
diff --git a/src/sim/se_workload.cc b/src/sim/se_workload.cc
index d3c8570..4d2bd54 100644
--- a/src/sim/se_workload.cc
+++ b/src/sim/se_workload.cc
@@ -54,6 +54,18 @@
}
void
+SEWorkload::serialize(CheckpointOut ) const
+{
+memPools.serialize(cp);
+}
+
+void
+SEWorkload::unserialize(CheckpointIn )
+{
+memPools.unserialize(cp);
+}
+
+void
SEWorkload::syscall(ThreadContext *tc)
{
tc->getProcessPtr()->syscall(tc);
diff --git a/src/sim/se_workload.hh b/src/sim/se_workload.hh
index 5bc597f..e212ad6 100644
--- a/src/sim/se_workload.hh
+++ b/src/sim/se_workload.hh
@@ -81,6 +81,9 @@
panic("No workload symbol table for syscall emulation mode.");
}
+void serialize(CheckpointOut ) const override;
+void unserialize(CheckpointIn ) override;
+
void syscall(ThreadContext *tc) override;
// For now, assume the only type of events are system calls.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I289bf91eb4f01d9c01a31a39b968e30f8b8d2bdc
Gerrit-Change-Number: 56969
Gerrit-PatchSet: 6
Gerrit-Owner: Jordi Vaquero
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jordi Vaquero
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Fix Mempool overrides during checkpoint
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56969 )
Change subject: sim: Fix Mempool overrides during checkpoint
..
sim: Fix Mempool overrides during checkpoint
This patch fixes the problem during checkpoing where the mempool is not
restored, but using only the one specified in the config file as a new
execution.
In order to fix that this changes modifyies the serialize/unserialize
functions for mempools and create new funcionts on se_workload to make
sure mempools ends up in the m5.cpt.
We change as well the unserialize mempool function to update the values for
and already createt pool, so the execution picks up right in the same place
for the checkpoint.
JIRA: https://gem5.atlassian.net/browse/GEM5-1191
Change-Id: I289bf91eb4f01d9c01a31a39b968e30f8b8d2bdc
---
M src/sim/mem_pool.cc
M src/sim/mem_pool.hh
M src/sim/process.cc
M src/sim/se_workload.hh
4 files changed, 78 insertions(+), 4 deletions(-)
diff --git a/src/sim/mem_pool.cc b/src/sim/mem_pool.cc
index 20b6eda..26190a6 100644
--- a/src/sim/mem_pool.cc
+++ b/src/sim/mem_pool.cc
@@ -123,6 +123,26 @@
return return_addr;
}
+bool
+MemPool::overlaps(MemPool& other)
+{
+Addr end_page_num = startPageNum + totalPages();
+if (startPageNum <= other.startPageNum &&
+end_page_num > other.startPageNum)
+return true;
+else
+return false;
+}
+
+void
+MemPool::update(MemPool & other)
+{
+pageShift = other.pageShift;
+startPageNum = other.startPageNum;
+freePageNum = other.freePageNum;
+_totalPages = other._totalPages;
+}
+
void
MemPool::serialize(CheckpointOut ) const
{
@@ -166,26 +186,42 @@
return pools[pool_id].freeBytes();
}
+bool
+MemPools::checkDuplicate(MemPool& pool)
+{
+for (auto : pools) {
+if (p.overlaps(pool)) {
+p.update(pool);
+return true;
+}
+}
+return false;
+}
+
void
MemPools::serialize(CheckpointOut ) const
{
+ScopedCheckpointSection sec(cp, "mempools");
int num_pools = pools.size();
SERIALIZE_SCALAR(num_pools);
for (int i = 0; i < num_pools; i++)
-pools[i].serializeSection(cp, csprintf("pool%d", i));
+pools[i].serializeSection(cp, csprintf("mempools.pool%d", i));
}
void
MemPools::unserialize(CheckpointIn )
{
+ScopedCheckpointSection sec(cp, "mempools");
int num_pools = 0;
UNSERIALIZE_SCALAR(num_pools);
for (int i = 0; i < num_pools; i++) {
MemPool pool;
-pool.unserializeSection(cp, csprintf("pool%d", i));
-pools.push_back(pool);
+pool.unserializeSection(cp, csprintf("mempools.pool%d", i));
+if (!checkDuplicate(pool)) {
+pools.push_back(pool);
+}
}
}
diff --git a/src/sim/mem_pool.hh b/src/sim/mem_pool.hh
index f35fdbc..452507a 100644
--- a/src/sim/mem_pool.hh
+++ b/src/sim/mem_pool.hh
@@ -79,6 +79,9 @@
Addr allocate(Addr npages);
+bool overlaps(MemPool& other);
+void update(MemPool& other);
+
void serialize(CheckpointOut ) const override;
void unserialize(CheckpointIn ) override;
};
@@ -105,6 +108,8 @@
/** Amount of physical memory that is still free in a pool. */
Addr freeMemSize(int pool_id=0) const;
+bool checkDuplicate(MemPool& pool);
+
void serialize(CheckpointOut ) const override;
void unserialize(CheckpointIn ) override;
};
diff --git a/src/sim/process.cc b/src/sim/process.cc
index 3a631a5..64fdca4 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -373,7 +373,7 @@
memState->serialize(cp);
pTable->serialize(cp);
fds->serialize(cp);
-
+seWorkload->serialize(cp);
/**
* Checkpoints for pipes, device drivers or sockets currently
* do not work. Need to come back and fix them at a later date.
@@ -388,6 +388,7 @@
memState->unserialize(cp);
pTable->unserialize(cp);
fds->unserialize(cp);
+seWorkload->unserialize(cp);
/**
* Checkpoints for pipes, device drivers or sockets currently
* do not work. Need to come back and fix them at a later date.
diff --git a/src/sim/se_workload.hh b/src/sim/se_workload.hh
index 5bc597f..117fbe0 100644
--- a/src/sim/se_workload.hh
+++ b/src/sim/se_workload.hh
@@ -81,6 +81,17 @@
panic("No workload symbol table for syscall emulation mode.");
}
+void
+serialize(CheckpointOut ) const override
+{
+memPools.serialize(cp);
+}
+void
+unserialize(CheckpointIn ) override
+{
+memPools.unserialize(cp);
+}
+
void syscall(ThreadContext *tc) override;
// For now, assume the only type of events are system calls.
--
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementation ARMv8.1 RDMA
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/36015 )
Change subject: arch-arm: Implementation ARMv8.1 RDMA
..
arch-arm: Implementation ARMv8.1 RDMA
Adding RDMA implementation for ARMv8.1
+ isa/formats/*: Adding decoding of Aarch64 and aarch32 instructions
+ isa/insts/neon.isa\neon64.isa: Adding function instructions
Change-Id: I430e8880723f373a50079a87fd4ecc634d86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36015
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/ArmISA.py
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/fp.isa
M src/arch/arm/isa/formats/neon64.isa
M src/arch/arm/isa/insts/neon.isa
M src/arch/arm/isa/insts/neon64.isa
6 files changed, 268 insertions(+), 23 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 02f24d3..3e18665 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -80,7 +80,7 @@
id_isar2 = Param.UInt32(0x21232141, "Instruction Set Attribute
Register 2")
id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute
Register 3")
id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute
Register 4")
-id_isar5 = Param.UInt32(0x1000, "Instruction Set Attribute
Register 5")
+id_isar5 = Param.UInt32(0x1100, "Instruction Set Attribute
Register 5")
fpsid = Param.UInt32(0x410430a0, "Floating-point System ID Register")
@@ -98,8 +98,8 @@
id_aa64dfr1_el1 = Param.UInt64(0x,
"AArch64 Debug Feature Register 1")
-# !TME | !Atomic | !CRC32 | !SHA2 | !SHA1 | !AES
-id_aa64isar0_el1 = Param.UInt64(0x,
+# !TME | !Atomic | !CRC32 | !SHA2 | RDM | !SHA1 | !AES
+id_aa64isar0_el1 = Param.UInt64(0x1000,
"AArch64 Instruction Set Attribute Register 0")
# GPI = 0x0 | GPA = 0x1 | API=0x0 | FCMA | JSCVT | APA=0x1
diff --git a/src/arch/arm/isa/formats/aarch64.isa
b/src/arch/arm/isa/formats/aarch64.isa
index f1a0cdb..9a487ea 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -2975,6 +2975,8 @@
} else {
return new Unknown64(machInst);
}
+} else if (bits(machInst, 15) && bits(machInst, 10) == 1) {
+return decodeNeonSc3SameExtra(machInst);
} else if (bits(machInst, 23, 22) == 0 &&
bits(machInst, 15) == 0) {
if (bits(machInst, 10) == 1) {
diff --git a/src/arch/arm/isa/formats/fp.isa
b/src/arch/arm/isa/formats/fp.isa
index f1b387e..5e7880e 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -652,7 +652,10 @@
}
case 0xb:
if (o1) {
-if (u || q) {
+if (u) {
+return decodeNeonSThreeSReg(
+q, size, machInst, vd, vn, vm);
+} else if (q) {
return new Unknown(machInst);
} else {
return decodeNeonUThreeUSReg(
@@ -669,7 +672,10 @@
}
case 0xc:
if (o1) {
-if (!u) {
+if (u) {
+return decodeNeonSThreeSReg(
+q, size, machInst, vd, vn, vm);
+} else {
if (bits(size, 1) == 0) {
if (q) {
return new NVfmaQFp(machInst, vd, vn,
vm);
@@ -1504,6 +1510,54 @@
return new Unknown(machInst);
}
}
+ case 0xe:
+if (u) {
+switch (size) {
+ case 1:
+return new VqrdmlahsQ(
+machInst, vd, vn, vm, index);
+ case 2:
+return new VqrdmlahsQ(
+machInst, vd, vn, vm, index);
+ default:
+return new Unknown(machInst);
+}
+} else {
+switch (size) {
+ case 1:
+return new VqrdmlahsD(
+machInst, vd, vn, vm, index);
+ case 2:
+return new VqrdmlahsD(
+machInst, vd, vn, vm, index);
+ default:
+return new Unknown(machInst);
+}
+}
+ case 0xf:
+if (u) {
+switch (size) {
+ case 1:
+return new VqrdmlshsQ(
+machInst, vd, vn, vm, index);
+ case 2:
+
[gem5-dev] Change in gem5/gem5[develop]: cpu: Adding connector post Timing access
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37416 )
Change subject: cpu: Adding connector post Timing access
..
cpu: Adding connector post Timing access
This patch adds a new connector to architecture dependent code
in completeDataAccess. This is used for address based memory
barrier to release the block after that access. The address based
barrier is implemented on architecture dependent code. Its implementation
for ARM arch can be accessed in dependent commits.
Change-Id: I8c75cd77dc6c9f9ae5e416608ce3d8ddb7b2ecf9
---
M src/arch/generic/tlb.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/simple/timing.cc
3 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh
index 59b3a01..21d80c1 100644
--- a/src/arch/generic/tlb.hh
+++ b/src/arch/generic/tlb.hh
@@ -98,6 +98,8 @@
panic("Not implemented.\n");
}
+virtual void handleOrdering(ThreadContext *tc, RequestPtr ) = 0;
+
/**
* Do post-translation physical address finalization.
*
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index b67edc4..519e288 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -970,6 +970,7 @@
state->outstanding--;
assert(pkt == _packets.front());
_port.completeDataAccess(pkt);
+_port.getMMUPtr()->dtb->handleOrdering(_inst->thread->getTC(),
pkt->req);
return true;
}
@@ -996,6 +997,8 @@
resp->dataStatic(_data);
resp->senderState = _senderState;
_port.completeDataAccess(resp);
+_port.getMMUPtr()->dtb->handleOrdering(_inst->thread->getTC(),
+ pkt->req);
delete resp;
}
return true;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 9c529b4..06212c7 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -1046,8 +1046,10 @@
panic("HTM - unhandled rc %s", htmFailureToStr(htm_rc));
}
} else {
+SimpleThread* thread = t_info->thread;
fault = curStaticInst->completeAcc(pkt, t_info,
traceData);
+thread->mmu->dtb->handleOrdering(thread->getTC(), pkt->req);
}
// hardware transactional memory
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I8c75cd77dc6c9f9ae5e416608ce3d8ddb7b2ecf9
Gerrit-Change-Number: 37416
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem: Added a new atribute for Address based mem barrier
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37415 )
Change subject: mem: Added a new atribute for Address based mem barrier
..
mem: Added a new atribute for Address based mem barrier
This small patch adds a new attribute and the set/get functions
to implement an address based mem barrier. The details of its use an
implementation are architecture dependent and it is described in
child-commits.
Change-Id: I2bf95b0b9ba848e35b58e545db311b8f09cb9cc7
---
M src/mem/request.hh
1 file changed, 15 insertions(+), 0 deletions(-)
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 73c823b..2898a33 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -407,6 +407,9 @@
LocalAccessor _localAccessor;
+/** Extra data used for ARM LOR subsistem to identify memory region **/
+int orderIndex = 0;
+
/** The instruction count at the time this request is created */
Counter _instCount = 0;
@@ -860,6 +863,18 @@
void setAccessLatency() { accessDelta = curTick() - _time -
translateDelta; }
Tick getAccessLatency() const { return accessDelta; }
+void
+setOrderingIndex(int idx)
+{
+orderIndex = idx;
+}
+
+int
+getOrderingIndex()
+{
+return orderIndex;
+}
+
/**
* Accessor for the sequence number of instruction that creates the
* request.
--
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Gerrit-Change-Id: I2bf95b0b9ba848e35b58e545db311b8f09cb9cc7
Gerrit-Change-Number: 37415
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementing Arm8 LOR feature
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/36835 )
Change subject: arch-arm: Implementing Arm8 LOR feature
..
arch-arm: Implementing Arm8 LOR feature
This patch implementents Limited ordering feature for Armv8.
This consist in addiung memory barrier regions to block ld/st
depending on the region their PA falls in.
This required some minor modification in the path for timing and o3
cpu types. In this case on completeDataAccess we refer to the LOR_helper
functions to free the barrier for the operation that has been waiting.
Change-Id: I2e0d4962f8672856185054917482204d2f220cbe
---
M src/arch/arm/ArmISA.py
M src/arch/arm/SConscript
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/insts/str64.isa
M src/arch/arm/isa/templates/mem64.isa
A src/arch/arm/lor_helper.cc
A src/arch/arm/lor_helper.hh
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
M src/arch/generic/tlb.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/simple/timing.cc
M src/mem/request.hh
21 files changed, 477 insertions(+), 14 deletions(-)
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 02f24d3..1e645d3 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -109,13 +109,17 @@
# 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA
id_aa64mmfr0_el1 = Param.UInt64(0x00f2,
"AArch64 Memory Model Feature Register 0")
-# PAN | HPDS | VHE
-id_aa64mmfr1_el1 = Param.UInt64(0x00101100,
-"AArch64 Memory Model Feature Register 1")
+# PAN | LO | HPDS | VHE
+id_aa64mmfr1_el1 = Param.UInt64(0x0000,
+ "AArch64 Memory Model Feature Register 1")
# |VARANGE
id_aa64mmfr2_el1 = Param.UInt64(0x0001,
"AArch64 Memory Model Feature Register 2")
+# Select number of regions and region descriptors
+lorid_el1 = Param.UInt64(0x00FF00FF,
+"LORegion ID Register")
+
# Any access (read/write) to an unimplemented
# Implementation Defined registers is not causing an Undefined
Instruction.
# It is rather executed as a NOP.
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 31e83a7..3faff7d 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -77,6 +77,7 @@
Source('linux/process.cc')
Source('linux/se_workload.cc')
Source('linux/fs_workload.cc')
+Source('lor_helper.cc')
Source('freebsd/freebsd.cc')
Source('freebsd/fs_workload.cc')
Source('freebsd/se_workload.cc')
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 3607c29..4292b70 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -112,6 +112,7 @@
highestELIs64 ? Enums::Full : Enums::Elem;
selfDebug = new SelfDebug();
+lorHelper = new LORHelper();
initializeMiscRegMetadata();
preUnflattenMiscReg();
@@ -372,6 +373,8 @@
miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p.id_aa64mmfr1_el1;
miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p.id_aa64mmfr2_el1;
+miscRegs[MISCREG_LORID_EL1] = p.lorid_el1;
+
miscRegs[MISCREG_ID_DFR0_EL1] =
(p.pmu ? 0x0300ULL : 0); // Enable PMUv3
@@ -460,6 +463,7 @@
return;
selfDebug->init(tc);
+lorHelper->init(tc);
Gicv3 *gicv3 = dynamic_cast(system->getGIC());
if (!gicv3)
@@ -1336,6 +1340,10 @@
case MISCREG_DBGWCR15_EL1:
selfDebug->updateDBGWCR(15, val);
break;
+ case MISCREG_LORC_EL1:
+if (val & 0x1)
+lorHelper->updateDescriptor(tc, val);
+break;
case MISCREG_IFSR:
{
// ARM ARM (ARM DDI 0406C.b) B4.1.96
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 4a824ed..92ced40 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -110,6 +110,7 @@
bool afterStartup;
SelfDebug * selfDebug;
+LORHelper * lorHelper;
/** MiscReg metadata **/
struct MiscRegLUTEntry {
@@ -485,6 +486,19 @@
return arm_isa->getSelfDebug();
}
+LORHelper*
+getLorHelper() const
+{
+return lorHelper;
+}
+
+static LORHelper*
+getLorHelper(ThreadContext *tc)
+{
+auto *arm_isa = static_cast(tc->getIsaPtr());
+return arm_isa->getLorHelper();
+}
+
RegVal readMiscRegNoEffect(int misc_reg) const;
RegVal readMiscReg(int misc_reg);
void setMiscRegNoEffect(int misc_reg, RegVal val);
diff --git a/src/arch/arm/isa/formats/aarch64.isa
b/src/arch/arm/isa/formats/aarch64.isa
index f1a0cdb..44f6333 100644
---
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementation ARMv8.1 RDMA
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/36015 )
Change subject: arch-arm: Implementation ARMv8.1 RDMA
..
arch-arm: Implementation ARMv8.1 RDMA
Adding RDMA implementation for ARMv8.1
+ isa/formats/*: Adding decoding of Aarch64 and aarch32 instructions
+ isa/insts/neon.isa\neon64.isa: Adding function instructions
Change-Id: I430e8880723f373a50079a87fd4ecc634d86
---
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/fp.isa
M src/arch/arm/isa/formats/neon64.isa
M src/arch/arm/isa/insts/neon.isa
M src/arch/arm/isa/insts/neon64.isa
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
7 files changed, 258 insertions(+), 17 deletions(-)
diff --git a/src/arch/arm/isa/formats/aarch64.isa
b/src/arch/arm/isa/formats/aarch64.isa
index f1a0cdb..4815f4e 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -2961,7 +2961,8 @@
} else if (bits(machInst, 23) == 0) {
return decodeNeonScShiftByImm(machInst);
}
-} else if (bits(machInst, 21) == 1) {
+} else if (bits(machInst, 21) == 1 || (!bits(machInst, 21) &&
+bits(machInst, 15))) {
if (bits(machInst, 10) == 1) {
return decodeNeonSc3Same(machInst);
} else if (bits(machInst, 11) == 0) {
diff --git a/src/arch/arm/isa/formats/fp.isa
b/src/arch/arm/isa/formats/fp.isa
index f1b387e..ac9ce81 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -652,7 +652,10 @@
}
case 0xb:
if (o1) {
-if (u || q) {
+if (u) {
+return decodeNeonSThreeSReg(
+q, size, machInst, vd, vn, vm);
+} else if (q) {
return new Unknown(machInst);
} else {
return decodeNeonUThreeUSReg(
@@ -1504,6 +1507,30 @@
return new Unknown(machInst);
}
}
+ case 0xe:
+if (u) {
+switch (size) {
+ case 1:
+return new VqrdmlahsQ(
+machInst, vd, vn, vm, index);
+ case 2:
+return new VqrdmlahsQ(
+machInst, vd, vn, vm, index);
+ default:
+return new Unknown(machInst);
+}
+} else {
+switch (size) {
+ case 1:
+return new VqrdmlahsD(
+machInst, vd, vn, vm, index);
+ case 2:
+return new VqrdmlahsD(
+machInst, vd, vn, vm, index);
+ default:
+return new Unknown(machInst);
+}
+}
}
return new Unknown(machInst);
}
diff --git a/src/arch/arm/isa/formats/neon64.isa
b/src/arch/arm/isa/formats/neon64.isa
index 6c2b2e0..7275ed7 100644
--- a/src/arch/arm/isa/formats/neon64.isa
+++ b/src/arch/arm/isa/formats/neon64.isa
@@ -516,6 +516,24 @@
IntRegIndex vm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
switch (opcode) {
+ case 0x10:
+if (size == 0x3 || size == 0x0)
+return new Unknown64(machInst);
+if (q)
+return decodeNeonSThreeHAndWReg(
+size, machInst, vd, vn, vm);
+else
+return decodeNeonSThreeHAndWReg(
+size, machInst, vd, vn, vm);
+ case 0x11:
+if (size == 0x3 || size == 0x0)
+return new Unknown64(machInst);
+if (q)
+return decodeNeonSThreeHAndWReg(
+size, machInst, vd, vn, vm);
+else
+return decodeNeonSThreeHAndWReg(
+size, machInst, vd, vn, vm);
case 0x18:
case 0x19:
case 0x1a:
@@ -1531,10 +1549,20 @@
return decodeNeonSThreeImmHAndWRegSqdmulhElemQX>(
q, size, machInst, vd, vn, vm, index);
case 0xd:
-if (u || (size == 0x0 || size == 0x3))
+if (size == 0x0 || size == 0x3)
return new Unknown64(machInst);
+else if (u)
+return decodeNeonSThreeImmHAndWReg(
+q, size, machInst, vd, vn, vm, index);
else
-return decodeNeonSThreeImmHAndWRegSqrdmulhElemQX>(
+return decodeNeonSThreeImmHAndWReg(
+q, size, machInst, vd, vn, vm, index);
+ case 0xf:
+if (size == 0x0 || size == 0x3)
+return new Unknown64(machInst);
+
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implement Armv8.2-LPA
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/35956 )
Change subject: arch-arm: Implement Armv8.2-LPA
..
arch-arm: Implement Armv8.2-LPA
This is enabled by setting the ArmSystem.phys_addr_range64 to 52.
This will automatically set the ID_AA64MMFR0_EL1.PARange to 0b0110
which encodes the presence of Armv8.2-LPA
Change-Id: If9b36e26cd2a72e55c8e929a632b7b50d909b282
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35956
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/pagetable.hh
M src/arch/arm/system.cc
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
M src/arch/arm/utility.cc
7 files changed, 105 insertions(+), 57 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/pagetable.hh b/src/arch/arm/pagetable.hh
index 9d1df1f..84e1967 100644
--- a/src/arch/arm/pagetable.hh
+++ b/src/arch/arm/pagetable.hh
@@ -51,7 +51,7 @@
{
// Max. physical address range in bits supported by the architecture
-const unsigned MaxPhysAddrRange = 48;
+const unsigned MaxPhysAddrRange = 52;
// ITB/DTB page table entry
struct PTE
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 7009b31..20ebee2 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -95,7 +95,7 @@
if (_highestELIs64 && (
_physAddrRange64 < 32 ||
-_physAddrRange64 > 48 ||
+_physAddrRange64 > MaxPhysAddrRange ||
(_physAddrRange64 % 4 != 0 && _physAddrRange64 != 42))) {
fatal("Invalid physical address range (%d)\n", _physAddrRange64);
}
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index d5027cf..26e20b2 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -81,12 +81,12 @@
haveSecurity = armSys->haveSecurity();
_haveLPAE = armSys->haveLPAE();
_haveVirtualization = armSys->haveVirtualization();
-physAddrRange = armSys->physAddrRange();
+_physAddrRange = armSys->physAddrRange();
_haveLargeAsid64 = armSys->haveLargeAsid64();
} else {
haveSecurity = _haveLPAE = _haveVirtualization = false;
_haveLargeAsid64 = false;
-physAddrRange = 32;
+_physAddrRange = 48;
}
}
@@ -252,7 +252,7 @@
currState->mode = _mode;
currState->tranType = tranType;
currState->isSecure = secure;
-currState->physAddrRange = physAddrRange;
+currState->physAddrRange = _physAddrRange;
/** @todo These should be cached or grabbed from cached copies in
the TLB, all these miscreg reads are expensive */
@@ -764,10 +764,10 @@
}
bool
-TableWalker::checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange)
+TableWalker::checkAddrSizeFaultAArch64(Addr addr, int pa_range)
{
-return (currPhysAddrRange != MaxPhysAddrRange &&
-bits(addr, MaxPhysAddrRange - 1, currPhysAddrRange));
+return (pa_range != _physAddrRange &&
+bits(addr, _physAddrRange - 1, pa_range));
}
Fault
@@ -1041,20 +1041,29 @@
"Table walker couldn't find lookup level\n");
}
-int stride = tg - 3;
+// Clamp to lower limit
+int pa_range = decodePhysAddrRange64(ps);
+if (pa_range > _physAddrRange) {
+currState->physAddrRange = _physAddrRange;
+} else {
+currState->physAddrRange = pa_range;
+}
// Determine table base address
+int stride = tg - 3;
int base_addr_lo = 3 + tsz - stride * (3 - start_lookup_level) - tg;
-Addr base_addr = mbits(ttbr, 47, base_addr_lo);
+Addr base_addr = 0;
+
+if (pa_range == 52) {
+int z = (base_addr_lo < 6) ? 6 : base_addr_lo;
+base_addr = mbits(ttbr, 47, z);
+base_addr |= (bits(ttbr, 5, 2) << 48);
+} else {
+base_addr = mbits(ttbr, 47, base_addr_lo);
+}
// Determine physical address size and raise an Address Size Fault if
// necessary
-int pa_range = decodePhysAddrRange64(ps);
-// Clamp to lower limit
-if (pa_range > physAddrRange)
-currState->physAddrRange = physAddrRange;
-else
-currState->physAddrRange = pa_range;
if (checkAddrSizeFaultAArch64(base_addr, currState->physAddrRange)) {
DPRINTF(TLB, "Address size fault before any lookup\n");
Fault f;
@@ -1084,7 +1093,7 @@
}
return f;
- }
+}
// Determine descriptor address
Addr desc_addr = base_addr |
@@ -1119,6 +1128,7 @@
currState->longDesc.lookupLevel = start_lookup_level;
currState->longDesc.aarch64 = true;
currState->longDesc.grainSize = tg;
+currState->longDesc.physAddrRange = _physAddrRange;
if (currState->timing) {
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implement Armv8.2-LVA
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/35955 )
Change subject: arch-arm: Implement Armv8.2-LVA
..
arch-arm: Implement Armv8.2-LVA
Change-Id: I1b489a3629b2376e03e79b158631cb1d0cacc17e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35955
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/ArmISA.py
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
5 files changed, 93 insertions(+), 48 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index a709894..02f24d3 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -112,7 +112,8 @@
# PAN | HPDS | VHE
id_aa64mmfr1_el1 = Param.UInt64(0x00101100,
"AArch64 Memory Model Feature Register 1")
-id_aa64mmfr2_el1 = Param.UInt64(0x,
+# |VARANGE
+id_aa64mmfr2_el1 = Param.UInt64(0x0001,
"AArch64 Memory Model Feature Register 2")
# Any access (read/write) to an unimplemented
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 9462e27..d5027cf 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -746,14 +746,21 @@
return f;
}
-unsigned
-TableWalker::adjustTableSizeAArch64(unsigned tsz)
+bool
+TableWalker::checkVAddrSizeFaultAArch64(Addr addr, int top_bit,
+GrainSize tg, int tsz, bool low_range)
{
-if (tsz < 25)
-return 25;
-if (tsz > 48)
-return 48;
-return tsz;
+// The effective maximum input size is 48 if ARMv8.2-LVA is not
+// supported or if the translation granule that is in use is 4KB or
+// 16KB in size. When ARMv8.2-LVA is supported, for the 64KB
+// translation granule size only, the effective minimum value of
+// 52.
+int in_max = (HaveLVA(currState->tc) && tg == Grain64KB) ? 52 : 48;
+int in_min = 64 - (tg == Grain64KB ? 47 : 48);
+
+return tsz > in_max || tsz < in_min || (low_range ?
+bits(currState->vaddr, top_bit, tsz) != 0x0 :
+bits(currState->vaddr, top_bit, tsz) != mask(top_bit - tsz + 1));
}
bool
@@ -784,8 +791,14 @@
GrainSize tg = Grain4KB; // grain size computed from tg* field
bool fault = false;
-LookupLevel start_lookup_level = MAX_LOOKUP_LEVELS;
+int top_bit = computeAddrTop(currState->tc,
+bits(currState->vaddr, 55),
+currState->mode==TLB::Execute,
+currState->tcr,
+currState->el);
+LookupLevel start_lookup_level = MAX_LOOKUP_LEVELS;
+bool vaddr_fault = false;
switch (currState->el) {
case EL0:
{
@@ -804,24 +817,28 @@
case 0:
DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
ttbr = ttbr0;
-tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
+tsz = 64 - currState->tcr.t0sz;
tg = GrainMap_tg0[currState->tcr.tg0];
currState->hpd = currState->tcr.hpd0;
currState->isUncacheable = currState->tcr.irgn0 == 0;
-if (bits(currState->vaddr, 63, tsz) != 0x0 ||
-currState->tcr.epd0)
- fault = true;
+vaddr_fault = checkVAddrSizeFaultAArch64(currState->vaddr,
+top_bit, tg, tsz, true);
+
+if (vaddr_fault || currState->tcr.epd0)
+fault = true;
break;
case 0x:
DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n");
ttbr = ttbr1;
-tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz);
+tsz = 64 - currState->tcr.t1sz;
tg = GrainMap_tg1[currState->tcr.tg1];
currState->hpd = currState->tcr.hpd1;
currState->isUncacheable = currState->tcr.irgn1 == 0;
-if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) ||
-currState->tcr.epd1)
- fault = true;
+vaddr_fault = checkVAddrSizeFaultAArch64(currState->vaddr,
+top_bit, tg, tsz, false);
+
+if (vaddr_fault || currState->tcr.epd1)
+fault = true;
break;
default:
// top two bytes must be all 0s or all 1s, else invalid
addr
@@ -858,28 +875,32 @@
ps = currState->vtcr.ps;
currState->isUncacheable = currState->vtcr.irgn0 == 0;
} else {
-switch (bits(currState->vaddr, 63,48)) {
+switch (bits(currState->vaddr, top_bit)) {
case 0:
-DPRINTF(TLB, " - Selecting TTBR0
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implement Armv8.2-LPA
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/35956 )
Change subject: arch-arm: Implement Armv8.2-LPA
..
arch-arm: Implement Armv8.2-LPA
This is enabled by setting the ArmSystem.phys_addr_range64 to 52.
This will automatically set the ID_AA64MMFR0_EL1.PARange to 0b0110
which encodes the presence of Armv8.2-LPA
Change-Id: If9b36e26cd2a72e55c8e929a632b7b50d909b282
---
M src/arch/arm/pagetable.hh
M src/arch/arm/system.cc
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
M src/arch/arm/utility.cc
7 files changed, 105 insertions(+), 57 deletions(-)
diff --git a/src/arch/arm/pagetable.hh b/src/arch/arm/pagetable.hh
index 9d1df1f..84e1967 100644
--- a/src/arch/arm/pagetable.hh
+++ b/src/arch/arm/pagetable.hh
@@ -51,7 +51,7 @@
{
// Max. physical address range in bits supported by the architecture
-const unsigned MaxPhysAddrRange = 48;
+const unsigned MaxPhysAddrRange = 52;
// ITB/DTB page table entry
struct PTE
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 7009b31..20ebee2 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -95,7 +95,7 @@
if (_highestELIs64 && (
_physAddrRange64 < 32 ||
-_physAddrRange64 > 48 ||
+_physAddrRange64 > MaxPhysAddrRange ||
(_physAddrRange64 % 4 != 0 && _physAddrRange64 != 42))) {
fatal("Invalid physical address range (%d)\n", _physAddrRange64);
}
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index d5027cf..26e20b2 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -81,12 +81,12 @@
haveSecurity = armSys->haveSecurity();
_haveLPAE = armSys->haveLPAE();
_haveVirtualization = armSys->haveVirtualization();
-physAddrRange = armSys->physAddrRange();
+_physAddrRange = armSys->physAddrRange();
_haveLargeAsid64 = armSys->haveLargeAsid64();
} else {
haveSecurity = _haveLPAE = _haveVirtualization = false;
_haveLargeAsid64 = false;
-physAddrRange = 32;
+_physAddrRange = 48;
}
}
@@ -252,7 +252,7 @@
currState->mode = _mode;
currState->tranType = tranType;
currState->isSecure = secure;
-currState->physAddrRange = physAddrRange;
+currState->physAddrRange = _physAddrRange;
/** @todo These should be cached or grabbed from cached copies in
the TLB, all these miscreg reads are expensive */
@@ -764,10 +764,10 @@
}
bool
-TableWalker::checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange)
+TableWalker::checkAddrSizeFaultAArch64(Addr addr, int pa_range)
{
-return (currPhysAddrRange != MaxPhysAddrRange &&
-bits(addr, MaxPhysAddrRange - 1, currPhysAddrRange));
+return (pa_range != _physAddrRange &&
+bits(addr, _physAddrRange - 1, pa_range));
}
Fault
@@ -1041,20 +1041,29 @@
"Table walker couldn't find lookup level\n");
}
-int stride = tg - 3;
+// Clamp to lower limit
+int pa_range = decodePhysAddrRange64(ps);
+if (pa_range > _physAddrRange) {
+currState->physAddrRange = _physAddrRange;
+} else {
+currState->physAddrRange = pa_range;
+}
// Determine table base address
+int stride = tg - 3;
int base_addr_lo = 3 + tsz - stride * (3 - start_lookup_level) - tg;
-Addr base_addr = mbits(ttbr, 47, base_addr_lo);
+Addr base_addr = 0;
+
+if (pa_range == 52) {
+int z = (base_addr_lo < 6) ? 6 : base_addr_lo;
+base_addr = mbits(ttbr, 47, z);
+base_addr |= (bits(ttbr, 5, 2) << 48);
+} else {
+base_addr = mbits(ttbr, 47, base_addr_lo);
+}
// Determine physical address size and raise an Address Size Fault if
// necessary
-int pa_range = decodePhysAddrRange64(ps);
-// Clamp to lower limit
-if (pa_range > physAddrRange)
-currState->physAddrRange = physAddrRange;
-else
-currState->physAddrRange = pa_range;
if (checkAddrSizeFaultAArch64(base_addr, currState->physAddrRange)) {
DPRINTF(TLB, "Address size fault before any lookup\n");
Fault f;
@@ -1084,7 +1093,7 @@
}
return f;
- }
+}
// Determine descriptor address
Addr desc_addr = base_addr |
@@ -1119,6 +1128,7 @@
currState->longDesc.lookupLevel = start_lookup_level;
currState->longDesc.aarch64 = true;
currState->longDesc.grainSize = tg;
+currState->longDesc.physAddrRange = _physAddrRange;
if (currState->timing) {
fetchDescriptor(desc_addr, (uint8_t*) >longDesc.data,
@@ -1745,10 +1755,8 @@
{
auto fault_source = ArmFault::FaultSourceInvalid;
// Check for address size fault
-if (checkAddrSizeFaultAArch64(
-
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implement Armv8.2-LVA
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/35955 )
Change subject: arch-arm: Implement Armv8.2-LVA
..
arch-arm: Implement Armv8.2-LVA
Change-Id: I1b489a3629b2376e03e79b158631cb1d0cacc17e
---
M src/arch/arm/ArmISA.py
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
5 files changed, 93 insertions(+), 48 deletions(-)
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index a709894..02f24d3 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -112,7 +112,8 @@
# PAN | HPDS | VHE
id_aa64mmfr1_el1 = Param.UInt64(0x00101100,
"AArch64 Memory Model Feature Register 1")
-id_aa64mmfr2_el1 = Param.UInt64(0x,
+# |VARANGE
+id_aa64mmfr2_el1 = Param.UInt64(0x0001,
"AArch64 Memory Model Feature Register 2")
# Any access (read/write) to an unimplemented
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 9462e27..d5027cf 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -746,14 +746,21 @@
return f;
}
-unsigned
-TableWalker::adjustTableSizeAArch64(unsigned tsz)
+bool
+TableWalker::checkVAddrSizeFaultAArch64(Addr addr, int top_bit,
+GrainSize tg, int tsz, bool low_range)
{
-if (tsz < 25)
-return 25;
-if (tsz > 48)
-return 48;
-return tsz;
+// The effective maximum input size is 48 if ARMv8.2-LVA is not
+// supported or if the translation granule that is in use is 4KB or
+// 16KB in size. When ARMv8.2-LVA is supported, for the 64KB
+// translation granule size only, the effective minimum value of
+// 52.
+int in_max = (HaveLVA(currState->tc) && tg == Grain64KB) ? 52 : 48;
+int in_min = 64 - (tg == Grain64KB ? 47 : 48);
+
+return tsz > in_max || tsz < in_min || (low_range ?
+bits(currState->vaddr, top_bit, tsz) != 0x0 :
+bits(currState->vaddr, top_bit, tsz) != mask(top_bit - tsz + 1));
}
bool
@@ -784,8 +791,14 @@
GrainSize tg = Grain4KB; // grain size computed from tg* field
bool fault = false;
-LookupLevel start_lookup_level = MAX_LOOKUP_LEVELS;
+int top_bit = computeAddrTop(currState->tc,
+bits(currState->vaddr, 55),
+currState->mode==TLB::Execute,
+currState->tcr,
+currState->el);
+LookupLevel start_lookup_level = MAX_LOOKUP_LEVELS;
+bool vaddr_fault = false;
switch (currState->el) {
case EL0:
{
@@ -804,24 +817,28 @@
case 0:
DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
ttbr = ttbr0;
-tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
+tsz = 64 - currState->tcr.t0sz;
tg = GrainMap_tg0[currState->tcr.tg0];
currState->hpd = currState->tcr.hpd0;
currState->isUncacheable = currState->tcr.irgn0 == 0;
-if (bits(currState->vaddr, 63, tsz) != 0x0 ||
-currState->tcr.epd0)
- fault = true;
+vaddr_fault = checkVAddrSizeFaultAArch64(currState->vaddr,
+top_bit, tg, tsz, true);
+
+if (vaddr_fault || currState->tcr.epd0)
+fault = true;
break;
case 0x:
DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n");
ttbr = ttbr1;
-tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz);
+tsz = 64 - currState->tcr.t1sz;
tg = GrainMap_tg1[currState->tcr.tg1];
currState->hpd = currState->tcr.hpd1;
currState->isUncacheable = currState->tcr.irgn1 == 0;
-if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) ||
-currState->tcr.epd1)
- fault = true;
+vaddr_fault = checkVAddrSizeFaultAArch64(currState->vaddr,
+top_bit, tg, tsz, false);
+
+if (vaddr_fault || currState->tcr.epd1)
+fault = true;
break;
default:
// top two bytes must be all 0s or all 1s, else invalid
addr
@@ -858,28 +875,32 @@
ps = currState->vtcr.ps;
currState->isUncacheable = currState->vtcr.irgn0 == 0;
} else {
-switch (bits(currState->vaddr, 63,48)) {
+switch (bits(currState->vaddr, top_bit)) {
case 0:
-DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
+DPRINTF(TLB, " - Selecting TTBR0_EL1 (AArch64)\n");
ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1);
-tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
+tsz = 64 -
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementing SecureEL2 feature for Armv8
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31394 )
Change subject: arch-arm: Implementing SecureEL2 feature for Armv8
..
arch-arm: Implementing SecureEL2 feature for Armv8
This patch adds Secure EL2 feature. This allows stage1
EL2/EL&0 and stage2 secure translation.
The changes are organized as follow:
+ insts/static_inst.cc: Modify checks for illegalInstruction on eret
+ isa.cc/hh: Enabling contorl bits
+ isa/insts/misc.hh/64.hh: Smc fault trigger.
+ miscregs.cc/hh: Declaration and initialization of new registers
+ self_debug.cc/hh: Add secureEL2 types for breakpoints
+ stage2_lookup.cc/hh: Allow stage2 in secure state.
+ tlb.cc/table_walker.cc: Allow secure state for stage2 and stage 1 EL2&0
translation regime
+ utility.cc/hh: New function InSecure and refactor of other helpers
to enable secure state
JIRA: https://gem5.atlassian.net/browse/GEM5-686
Change-Id: Ie59438b1828508e944334420da1d8f4745649056
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31394
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/fastmodel/CortexA76/thread_context.cc
M src/arch/arm/faults.cc
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/static_inst.hh
M src/arch/arm/interrupts.cc
M src/arch/arm/interrupts.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa/insts/branch.isa
M src/arch/arm/isa/insts/fp.isa
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/isa/insts/misc64.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
M src/arch/arm/semihosting.cc
M src/arch/arm/stage2_lookup.cc
M src/arch/arm/stage2_lookup.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/tlb.cc
M src/arch/arm/tracers/tarmac_record.cc
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
27 files changed, 211 insertions(+), 139 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index c4cc51f..333ae5f 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -75,6 +75,8 @@
"True if LSE is implemented (ARMv8.1)")
have_pan = Param.Bool(True,
"True if Priviledge Access Never is implemented (ARMv8.1)")
+have_secel2 = Param.Bool(True,
+"True if Secure EL2 is implemented (ARMv8)")
semihosting = Param.ArmSemihosting(NULL,
"Enable support for the Arm semihosting by settings this
parameter")
diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
index 4016d2b..4e2bfd2 100644
--- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
@@ -59,7 +59,7 @@
break;
}
-Iris::CanonicalMsn out_msn = inSecureState(this) ?
+Iris::CanonicalMsn out_msn = isSecure(this) ?
Iris::PhysicalMemorySecureMsn : Iris::PhysicalMemoryNonSecureMsn;
// Figure out what memory spaces match the canonical numbers we need.
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 40cf634..300c82c 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -977,10 +977,12 @@
} else {
bool lower_32 = false;
if (toEL == EL3) {
-if (!inSecureState(tc) && ArmSystem::haveEL(tc, EL2))
+if (EL2Enabled(tc))
lower_32 = ELIs32(tc, EL2);
else
lower_32 = ELIs32(tc, EL1);
+} else if (ELIsInHost(tc, fromEL) && fromEL == EL0 && toEL == EL2)
{
+lower_32 = ELIs32(tc, EL0);
} else {
lower_32 = ELIs32(tc, static_cast(toEL - 1));
}
@@ -1310,7 +1312,7 @@
HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
toHyp = fromEL == EL2;
-toHyp |= ArmSystem::haveEL(tc, EL2) && !inSecureState(tc) &&
+toHyp |= ArmSystem::haveEL(tc, EL2) && !isSecure(tc) &&
currEL(tc) <= EL1 && (hcr.tge || stage2 ||
(source == DebugEvent && hdcr.tde));
return toHyp;
diff --git a/src/arch/arm/insts/static_inst.cc
b/src/arch/arm/insts/static_inst.cc
index 0cbd776..12586c7 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -634,9 +634,8 @@
const auto tc = xc->tcBase();
const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
-if ((ArmSystem::haveEL(tc, EL2) && !inSecureState(tc) &&
- !ELIs32(tc, EL2) && (hcr.tge == 1 || mdcr.tde == 1)) ||
- !ELIs32(tc, EL1)) {
+if ((EL2Enabled(tc) && !ELIs32(tc, EL2) &&
+
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix Trap to EL1 on register DC CVAU
Jordi Vaquero has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/31774 ) Change subject: arch-arm: Fix Trap to EL1 on register DC CVAU .. arch-arm: Fix Trap to EL1 on register DC CVAU Change-Id: I8add9fc8595bb1ac0a7de9778bd4544a01b94ee4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31774 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- M src/arch/arm/insts/misc64.cc 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index 49cc6b0..f9f00f0 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -146,7 +146,7 @@ break; case MISCREG_DC_CVAU_Xt: trap_to_sup = !sctlr.uci && (!hcr.tge || (!scr.ns && !scr.eel2)) && -el == EL1; +el == EL0; break; case MISCREG_CTR_EL0: trap_to_sup = el == EL0 && !sctlr.uct && -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31774 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I8add9fc8595bb1ac0a7de9778bd4544a01b94ee4 Gerrit-Change-Number: 31774 Gerrit-PatchSet: 2 Gerrit-Owner: Jordi Vaquero Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jordi Vaquero Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix Trap to EL1 on register DC CVAU
Jordi Vaquero has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/31774 ) Change subject: arch-arm: Fix Trap to EL1 on register DC CVAU .. arch-arm: Fix Trap to EL1 on register DC CVAU Change-Id: I8add9fc8595bb1ac0a7de9778bd4544a01b94ee4 --- M src/arch/arm/insts/misc64.cc 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index 49cc6b0..f9f00f0 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -146,7 +146,7 @@ break; case MISCREG_DC_CVAU_Xt: trap_to_sup = !sctlr.uci && (!hcr.tge || (!scr.ns && !scr.eel2)) && -el == EL1; +el == EL0; break; case MISCREG_CTR_EL0: trap_to_sup = el == EL0 && !sctlr.uct && -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31774 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I8add9fc8595bb1ac0a7de9778bd4544a01b94ee4 Gerrit-Change-Number: 31774 Gerrit-PatchSet: 1 Gerrit-Owner: Jordi Vaquero Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add System register trap check for EL1
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31694 )
Change subject: arch-arm: Add System register trap check for EL1
..
arch-arm: Add System register trap check for EL1
This change adds and refactors the register trap checks
for EL1 in the same function, unifying the registry trapping
Change-Id: Ief3e0a9f70cc8cd44c1c8215515f36168927362d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31694
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/insts/misc64.cc
M src/arch/arm/isa/insts/data64.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs_types.hh
4 files changed, 36 insertions(+), 25 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 51e6028..49cc6b0 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -114,9 +114,26 @@
uint32_t ) const
{
const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
+const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
+const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
+const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
bool trap_to_sup = false;
switch (misc_reg) {
+ case MISCREG_DAIF:
+trap_to_sup = !scr.ns && !scr.eel2 && !sctlr.uma && el == EL0;
+trap_to_sup = trap_to_sup ||
+(el == EL0 && (scr.ns || scr.eel2) && !hcr.tge && !sctlr.uma);
+break;
+ case MISCREG_DC_ZVA_Xt:
+// In syscall-emulation mode, this test is skipped and DCZVA is
always
+// allowed at EL0
+trap_to_sup = el == EL0 && !sctlr.dze && FullSystem;
+break;
+ case MISCREG_DC_CIVAC_Xt:
+ case MISCREG_DC_CVAC_Xt:
+trap_to_sup = el == EL0 && !sctlr.uci;
+break;
case MISCREG_FPCR:
case MISCREG_FPSR:
case MISCREG_FPEXC32_EL2:
@@ -127,6 +144,24 @@
immediate = 0x1E0;
}
break;
+ case MISCREG_DC_CVAU_Xt:
+trap_to_sup = !sctlr.uci && (!hcr.tge || (!scr.ns && !scr.eel2)) &&
+el == EL1;
+break;
+ case MISCREG_CTR_EL0:
+trap_to_sup = el == EL0 && !sctlr.uct &&
+(!hcr.tge || (!scr.ns && !scr.eel2));
+break;
+ case MISCREG_MDCCSR_EL0:
+ {
+ DBGDS32 mdscr = tc->readMiscReg(MISCREG_MDSCR_EL1);
+ trap_to_sup = el == EL0 && mdscr.tdcc &&
+ (hcr.tge == 0x0 || ( scr.ns == 0x0));
+ }
+ break;
+ case MISCREG_ZCR_EL1:
+trap_to_sup = el == EL1 && ((cpacr.zen & 0x1) == 0x0);
+break;
// Generic Timer
case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
trap_to_sup = el == EL0 &&
diff --git a/src/arch/arm/isa/insts/data64.isa
b/src/arch/arm/isa/insts/data64.isa
index 3c1e941..1b099bf 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -312,14 +312,6 @@
msrMrs64EnabledCheckCode = '''
// Check for read/write access right
if (!can%sAArch64SysReg(flat_idx, Hcr64, Scr64, cpsr,
xc->tcBase())) {
-if (flat_idx == MISCREG_DAIF ||
-flat_idx == MISCREG_DC_ZVA_Xt ||
-flat_idx == MISCREG_DC_CVAC_Xt ||
-flat_idx == MISCREG_DC_CIVAC_Xt
-)
-return std::make_shared(
-machInst, 0, EC_TRAPPED_MSR_MRS_64,
-mnemonic);
return std::make_shared(machInst, false,
mnemonic);
}
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index cc451c6..525fbcd 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -1415,23 +1415,6 @@
if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
return false;
ExceptionLevel el = currEL(cpsr);
-if (reg == MISCREG_DAIF) {
-SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
-if (el == EL0 && !sctlr.uma)
-return false;
-}
-if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
-// In syscall-emulation mode, this test is skipped and DCZVA is
always
-// allowed at EL0
-SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
-if (el == EL0 && !sctlr.dze)
-return false;
-}
-if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
-SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
-if (el == EL0 && !sctlr.uci)
-return false;
-}
bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
bool el2_host = EL2Enabled(tc) && hcr.e2h;
diff --git a/src/arch/arm/miscregs_types.hh
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add System register trap check for EL1
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31694 )
Change subject: arch-arm: Add System register trap check for EL1
..
arch-arm: Add System register trap check for EL1
Change-Id: Ief3e0a9f70cc8cd44c1c8215515f36168927362d
---
M src/arch/arm/insts/misc64.cc
M src/arch/arm/miscregs_types.hh
2 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 51e6028..cd6386a 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -114,9 +114,17 @@
uint32_t ) const
{
const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
+const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
+const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
+const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
bool trap_to_sup = false;
switch (misc_reg) {
+ case MISCREG_DAIF:
+trap_to_sup = !scr.ns && !scr.eel2 && !sctlr.uma && el == EL0;
+trap_to_sup = trap_to_sup ||
+(el == EL0 && (scr.ns || scr.eel2) && !hcr.tge && !sctlr.uma);
+break;
case MISCREG_FPCR:
case MISCREG_FPSR:
case MISCREG_FPEXC32_EL2:
@@ -127,6 +135,24 @@
immediate = 0x1E0;
}
break;
+ case MISCREG_DC_CVAU_Xt:
+trap_to_sup = !sctlr.uci && (!hcr.tge || (!scr.ns && !scr.eel2)) &&
+el == EL1;
+break;
+ case MISCREG_CTR_EL0:
+trap_to_sup = el == EL0 && !sctlr.uct &&
+(!hcr.tge || (!scr.ns && !scr.eel2));
+break;
+ case MISCREG_MDCCSR_EL0:
+ {
+ DBGDS32 mdscr = tc->readMiscReg(MISCREG_MDSCR_EL1);
+ trap_to_sup = el == EL0 && mdscr.tdcc &&
+ (hcr.tge == 0x0 || ( scr.ns == 0x0));
+ }
+ break;
+ case MISCREG_ZCR_EL1:
+trap_to_sup = el == EL1 && ((cpacr.zen & 0x1) == 0x0);
+break;
// Generic Timer
case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
trap_to_sup = el == EL0 &&
diff --git a/src/arch/arm/miscregs_types.hh b/src/arch/arm/miscregs_types.hh
index d3787ff..3578f58 100644
--- a/src/arch/arm/miscregs_types.hh
+++ b/src/arch/arm/miscregs_types.hh
@@ -730,6 +730,7 @@
Bitfield<14> hde;
Bitfield<13> res0_;
Bitfield<12> udccdis;
+Bitfield<12> tdcc;
Bitfield<11, 7> res0_2;
Bitfield<6> err;
Bitfield<5, 2> moe;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31694
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ief3e0a9f70cc8cd44c1c8215515f36168927362d
Gerrit-Change-Number: 31694
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix Fault subsystem adding EL2Enable func
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31374 )
Change subject: arch-arm: Fix Fault subsystem adding EL2Enable func
..
arch-arm: Fix Fault subsystem adding EL2Enable func
Change-Id: I7a4f0c22ac31fd56a8976ee8a1d9760cf6055d63
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31374
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
2 files changed, 58 insertions(+), 57 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 743e08d..40cf634 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -819,17 +819,9 @@
bool
UndefinedInstruction::routeToHyp(ThreadContext *tc) const
{
-bool toHyp;
-
-SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
-// if in Hyp mode then stay in Hyp mode
-toHyp = scr.ns && (currEL(tc) == EL2);
-// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
-toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
-return toHyp;
+return fromEL == EL2 ||
+ (EL2Enabled(tc) && (fromEL == EL0) && hcr.tge);
}
uint32_t
@@ -885,7 +877,8 @@
SupervisorCall::routeToHyp(ThreadContext *tc) const
{
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
-return EL2Enabled(tc) && currEL(tc) == EL0 && hcr.tge == 1;
+return fromEL == EL2 ||
+ (EL2Enabled(tc) && fromEL == EL0 && hcr.tge);
}
ExceptionClass
@@ -929,6 +922,18 @@
bStep = true;
}
+bool
+HypervisorCall::routeToMonitor(ThreadContext *tc) const
+{
+return from64 && fromEL == EL3;
+}
+
+bool
+HypervisorCall::routeToHyp(ThreadContext *tc) const
+{
+return !from64 || fromEL != EL3;
+}
+
ExceptionClass
HypervisorCall::ec(ThreadContext *tc) const
{
@@ -1301,20 +1306,14 @@
{
bool toHyp;
-SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
-// if in Hyp mode then stay in Hyp mode
-toHyp = scr.ns && (currEL(tc) == EL2);
-toHyp |= (currEL(tc) <= EL1) && hcr.tge;
-// otherwise, check whether to take to Hyp mode through Hyp Trap vector
-toHyp |= (stage2 ||
- ((source == DebugEvent) && (hdcr.tde || hcr.tge) &&
- (currEL(tc) != EL2)) ||
- ((source == SynchronousExternalAbort) && hcr.tge &&
- (currEL(tc) == EL0))) && !inSecureState(tc);
-return toHyp;
+toHyp = fromEL == EL2;
+toHyp |= ArmSystem::haveEL(tc, EL2) && !inSecureState(tc) &&
+currEL(tc) <= EL1 && (hcr.tge || stage2 ||
+ (source == DebugEvent && hdcr.tde));
+ return toHyp;
}
ExceptionClass
@@ -1363,21 +1362,22 @@
{
bool toHyp;
-SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
+bool amo = hcr.amo;
+if (hcr.tge == 1)
+amo = (!HaveVirtHostExt(tc) || hcr.e2h == 0);
+
// if in Hyp mode then stay in Hyp mode
-toHyp = scr.ns && (currEL(tc) == EL2);
-toHyp |= (currEL(tc) <= EL1 && hcr.tge==1);
-// otherwise, check whether to take to Hyp mode through Hyp Trap vector
-toHyp |= (stage2 ||
- ((currEL(tc) != EL2) &&
- (((source == AsynchronousExternalAbort) && hcr.amo) ||
-((source == DebugEvent) && (hdcr.tde || hcr.tge ||
- ((currEL(tc) == EL0) && hcr.tge &&
- ((source == AlignmentFault) ||
-(source == SynchronousExternalAbort
&& !inSecureState(tc);
+toHyp = fromEL == EL2 ||
+(EL2Enabled(tc) && fromEL <= EL1
+&& (hcr.tge || stage2 ||
+((source == AsynchronousExternalAbort) && amo) ||
+((fromEL == EL0) && hcr.tge &&
+ ((source == AlignmentFault) ||
+ (source == SynchronousExternalAbort))) ||
+((source == DebugEvent) && (hdcr.tde || hcr.tge;
return toHyp;
}
@@ -1472,7 +1472,7 @@
{
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
return fromEL == EL2 ||
- (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge == 1 || hcr.imo));
+ (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || hcr.imo));
}
bool
@@ -1505,7 +1505,7 @@
{
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
return fromEL == EL2 ||
- (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge == 1 || hcr.fmo));
+ (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge ||
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementing SecureEL2 feature for Armv8
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31394 )
Change subject: arch-arm: Implementing SecureEL2 feature for Armv8
..
arch-arm: Implementing SecureEL2 feature for Armv8
This patch adds Secure EL2 feature. This allows stage1
EL2/EL&0 and stage2 secure translation.
The changes are organized as follow:
+ insts/static_inst.cc: Modify checks for illegalInstruction on eret
+ isa.cc/hh: Enabling contorl bits
+ isa/insts/misc.hh/64.hh: Smc fault trigger.
+ miscregs.cc/hh: Declaration and initialization of new registers
+ self_debug.cc/hh: Add secureEL2 types for breakpoints
+ stage2_lookup.cc/hh: Allow stage2 in secure state.
+ tlb.cc/table_walker.cc: Allow secure state for stage2 and stage 1 EL2&0
translation regime
+ utility.cc/hh: New function InSecure and refactor of other helpers
to enable secure state
Change-Id: Ie59438b1828508e944334420da1d8f4745649056
---
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/isa/insts/misc64.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
M src/arch/arm/stage2_lookup.cc
M src/arch/arm/stage2_lookup.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/tlb.cc
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
15 files changed, 177 insertions(+), 96 deletions(-)
diff --git a/src/arch/arm/insts/static_inst.cc
b/src/arch/arm/insts/static_inst.cc
index c7f3c27..cb89def 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -634,9 +634,8 @@
const auto tc = xc->tcBase();
const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
-if ((ArmSystem::haveEL(tc, EL2) && !inSecureState(tc) &&
- !ELIs32(tc, EL2) && (hcr.tge == 1 || mdcr.tde == 1)) ||
- !ELIs32(tc, EL1)) {
+if ((EL2Enabled(tc) && !ELIs32(tc, EL2)
+ && (hcr.tge || mdcr.tde)) || !ELIs32(tc, EL1)) {
// Route to AArch64 Software Breakpoint
return std::make_shared(machInst, imm);
} else {
@@ -1094,22 +1093,33 @@
if (unknownMode(mode))
return true;
-const OperatingMode cur_mode = (OperatingMode) (uint8_t)cpsr.mode;
-const ExceptionLevel target_el = opModeToEL(mode);
+SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
+HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
-HCR hcr = ((HCR)tc->readMiscReg(MISCREG_HCR_EL2));
-SCR scr = ((SCR)tc->readMiscReg(MISCREG_SCR_EL3));
-
-if (target_el > opModeToEL(cur_mode))
+//ELFromSPSR
+bool valid;
+ExceptionLevel target_el = opModeToEL(mode);
+if (!spsr.width) {
+if (!ArmSystem::highestELIs64(tc)) {
+valid = false;
+} else if (!ArmSystem::haveEL(tc, target_el)) {
+valid = false;
+} else if (spsr & 0x2) {
+valid = false;
+} else if (target_el == EL0 && spsr.sp) {
+valid = false;
+} else if (target_el == EL2 && ArmSystem::haveEL(tc, EL3)
&& !scr.ns
+&& !IsSecureEL2Enabled(tc)){
+valid = false;
+} else
+valid = true;
+} else {
+valid = !unknownMode32(mode);
+}
+if (!valid)
return true;
-if (!ArmSystem::haveEL(tc, target_el))
-return true;
-
-if (target_el == EL1 && ArmSystem::haveEL(tc, EL2) && scr.ns &&
hcr.tge)
-return true;
-
-if (target_el == EL2 && ArmSystem::haveEL(tc, EL3) && !scr.ns)
+if (target_el > currEL(tc))
return true;
bool spsr_mode_is_aarch32 = (spsr.width == 1);
@@ -1120,17 +1130,9 @@
if (known && (spsr_mode_is_aarch32 != target_el_is_aarch32))
return true;
-if (!spsr.width) {
-// aarch64
-if (!ArmSystem::highestELIs64(tc))
-return true;
-if (spsr & 0x2)
-return true;
-if (target_el == EL0 && spsr.sp)
-return true;
-} else {
-// aarch32
-return unknownMode32(mode);
+if (target_el == EL1 && ArmSystem::haveEL(tc, EL2) && hcr.tge &&
+(IsSecureEL2Enabled(tc) || !isSecureBelowEL3(tc))) {
+return true;
}
return false;
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 9cb8c2b..40c589a 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -397,6 +397,11 @@
miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32,
haveSVE ? 0x1 : 0x0);
+// SecEL2
+miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
+miscRegs[MISCREG_ID_AA64PFR0_EL1], 39, 36, 0x1);
+miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
+miscRegs[MISCREG_ID_AA64ISAR0_EL1], 39, 36, 0x1);
// Large ASID support
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix Fault subsystem adding EL2Enable func
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31374 )
Change subject: arch-arm: Fix Fault subsystem adding EL2Enable func
..
arch-arm: Fix Fault subsystem adding EL2Enable func
Change-Id: I7a4f0c22ac31fd56a8976ee8a1d9760cf6055d63
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
2 files changed, 55 insertions(+), 53 deletions(-)
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 743e08d..151be20 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -819,17 +819,8 @@
bool
UndefinedInstruction::routeToHyp(ThreadContext *tc) const
{
-bool toHyp;
-
-SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
-// if in Hyp mode then stay in Hyp mode
-toHyp = scr.ns && (currEL(tc) == EL2);
-// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
-toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
-return toHyp;
+return hcr.tge && (currEL(tc) == EL0) && EL2Enabled(tc);
}
uint32_t
@@ -885,7 +876,8 @@
SupervisorCall::routeToHyp(ThreadContext *tc) const
{
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
-return EL2Enabled(tc) && currEL(tc) == EL0 && hcr.tge == 1;
+return fromEL <= EL1 &&
+ (EL2Enabled(tc) && currEL(tc) == EL0 && hcr.tge == 1);
}
ExceptionClass
@@ -929,6 +921,20 @@
bStep = true;
}
+bool
+HypervisorCall::routeToMonitor(ThreadContext *tc) const
+{
+bool toMon = from64 && fromEL == EL3;
+return toMon;
+}
+
+bool
+HypervisorCall::routeToHyp(ThreadContext *tc) const
+{
+bool toHyp = !from64 || fromEL != EL3;
+return toHyp;
+}
+
ExceptionClass
HypervisorCall::ec(ThreadContext *tc) const
{
@@ -1301,20 +1307,13 @@
{
bool toHyp;
-SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
-// if in Hyp mode then stay in Hyp mode
-toHyp = scr.ns && (currEL(tc) == EL2);
-toHyp |= (currEL(tc) <= EL1) && hcr.tge;
-// otherwise, check whether to take to Hyp mode through Hyp Trap vector
-toHyp |= (stage2 ||
- ((source == DebugEvent) && (hdcr.tde || hcr.tge) &&
- (currEL(tc) != EL2)) ||
- ((source == SynchronousExternalAbort) && hcr.tge &&
- (currEL(tc) == EL0))) && !inSecureState(tc);
-return toHyp;
+toHyp = fromEL == EL2;
+toHyp |= ArmSystem::haveEL(tc, EL2) && !isSecure(tc) &&
currEL(tc)<=EL1
+&& (hcr.tge || stage2 || (source == DebugEvent && hdcr.tde));
+ return toHyp;
}
ExceptionClass
@@ -1363,21 +1362,22 @@
{
bool toHyp;
-SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
+bool amo = hcr.amo;
+if (hcr.tge == 1)
+amo = (!HaveVirtHostExt(tc) || hcr.e2h == 0);
+
// if in Hyp mode then stay in Hyp mode
-toHyp = scr.ns && (currEL(tc) == EL2);
-toHyp |= (currEL(tc) <= EL1 && hcr.tge==1);
-// otherwise, check whether to take to Hyp mode through Hyp Trap vector
-toHyp |= (stage2 ||
- ((currEL(tc) != EL2) &&
- (((source == AsynchronousExternalAbort) && hcr.amo) ||
-((source == DebugEvent) && (hdcr.tde || hcr.tge ||
- ((currEL(tc) == EL0) && hcr.tge &&
- ((source == AlignmentFault) ||
-(source == SynchronousExternalAbort
&& !inSecureState(tc);
+toHyp = fromEL == EL2
+|| (EL2Enabled(tc) && fromEL<=EL1
+&& (hcr.tge || stage2
+|| ((source == AsynchronousExternalAbort) && amo)
+|| ((fromEL == EL0) && hcr.tge &&
+((source == AlignmentFault)
+ || (source == SynchronousExternalAbort)))
+|| ((source == DebugEvent) && (hdcr.tde || hcr.tge;
return toHyp;
}
@@ -1472,7 +1472,7 @@
{
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
return fromEL == EL2 ||
- (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge == 1 || hcr.imo));
+ (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || hcr.imo));
}
bool
@@ -1505,7 +1505,7 @@
{
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
return fromEL == EL2 ||
- (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge == 1 || hcr.fmo));
+ (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || hcr.fmo));
}
bool
@@ -1546,7 +1546,7 @@
PCAlignmentFault::routeToHyp(ThreadContext *tc) const
{
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
-return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge == 1;
+return EL2Enabled(tc) && fromEL <= EL1 && hcr.tge;
}
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix routeToHyp conditions for Excp Type
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30620 )
Change subject: arch-arm: Fix routeToHyp conditions for Excp Type
..
arch-arm: Fix routeToHyp conditions for Excp Type
Change-Id: I8eadd8e1f8c53d5e61969b492d9f2cbd12110188
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30620
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/faults.cc
1 file changed, 10 insertions(+), 43 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index ecc9e4d..743e08d 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -884,17 +884,8 @@
bool
SupervisorCall::routeToHyp(ThreadContext *tc) const
{
-bool toHyp;
-
-SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
-// if in Hyp mode then stay in Hyp mode
-toHyp = scr.ns && (cpsr.mode == MODE_HYP);
-// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
-toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
-return toHyp;
+return EL2Enabled(tc) && currEL(tc) == EL0 && hcr.tge == 1;
}
ExceptionClass
@@ -1028,15 +1019,8 @@
bool
SupervisorTrap::routeToHyp(ThreadContext *tc) const
{
-bool toHyp = false;
-
-SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
-// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
-toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
-return toHyp;
+return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge;
}
uint32_t
@@ -1323,6 +1307,7 @@
// if in Hyp mode then stay in Hyp mode
toHyp = scr.ns && (currEL(tc) == EL2);
+toHyp |= (currEL(tc) <= EL1) && hcr.tge;
// otherwise, check whether to take to Hyp mode through Hyp Trap vector
toHyp |= (stage2 ||
((source == DebugEvent) && (hdcr.tde || hcr.tge) &&
@@ -1384,6 +1369,7 @@
// if in Hyp mode then stay in Hyp mode
toHyp = scr.ns && (currEL(tc) == EL2);
+toHyp |= (currEL(tc) <= EL1 && hcr.tge==1);
// otherwise, check whether to take to Hyp mode through Hyp Trap vector
toHyp |= (stage2 ||
((currEL(tc) != EL2) &&
@@ -1484,15 +1470,9 @@
bool
Interrupt::routeToHyp(ThreadContext *tc) const
{
-bool toHyp;
-
-SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-// Determine whether IRQs are routed to Hyp mode.
-toHyp = (!scr.irq && hcr.imo && !inSecureState(tc)) ||
-(cpsr.mode == MODE_HYP);
-return toHyp;
+return fromEL == EL2 ||
+ (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge == 1 || hcr.imo));
}
bool
@@ -1523,15 +1503,9 @@
bool
FastInterrupt::routeToHyp(ThreadContext *tc) const
{
-bool toHyp;
-
-SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-// Determine whether IRQs are routed to Hyp mode.
-toHyp = (!scr.fiq && hcr.fmo && !inSecureState(tc)) ||
-(cpsr.mode == MODE_HYP);
-return toHyp;
+return fromEL == EL2 ||
+ (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge == 1 || hcr.fmo));
}
bool
@@ -1571,15 +1545,8 @@
bool
PCAlignmentFault::routeToHyp(ThreadContext *tc) const
{
-bool toHyp = false;
-
-SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
-// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
-toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
-return toHyp;
+return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge == 1;
}
SPAlignmentFault::SPAlignmentFault()
@@ -1590,7 +1557,7 @@
{
assert(from64);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
-return EL2Enabled(tc) && hcr.tge==1;
+return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge == 1;
}
SystemError::SystemError()
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30620
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8eadd8e1f8c53d5e61969b492d9f2cbd12110188
Gerrit-Change-Number: 30620
Gerrit-PatchSet: 4
Gerrit-Owner: Jordi Vaquero
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jordi Vaquero
Gerrit-Reviewer:
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add Check for AddressSize Fault
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30619 )
Change subject: arch-arm: Add Check for AddressSize Fault
..
arch-arm: Add Check for AddressSize Fault
This patch add a check for AddressSize Fault during translation when
MMU is disabled.
Change-Id: Iff3a1543df010b086813869b4b6c4fe776e74499
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30619
Maintainer: Giacomo Travaglini
Tested-by: kokoro
Reviewed-by: Giacomo Travaglini
---
M src/arch/arm/tlb.cc
M src/arch/arm/utility.hh
2 files changed, 19 insertions(+), 1 deletion(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index f92f8e0..f007f93 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1011,12 +1011,30 @@
TLB::ArmTranslationType tranType, Addr vaddr, bool
long_desc_format)
{
bool is_fetch = (mode == Execute);
+bool is_atomic = req->isAtomic();
req->setPaddr(vaddr);
// When the MMU is off the security attribute corresponds to the
// security state of the processor
if (isSecure)
req->setFlags(Request::SECURE);
+bool selbit = bits(vaddr, 55);
+TCR tcr1 = tc->readMiscReg(MISCREG_TCR_EL1);
+int topbit = computeAddrTop(tc, selbit, is_fetch, tcr1, currEL(tc));
+int addr_sz = bits(vaddr, topbit, MaxPhysAddrRange);
+if (addr_sz != 0){
+Fault f;
+if (is_fetch)
+f = std::make_shared(vaddr,
+ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
+else
+f = std::make_shared( vaddr,
+TlbEntry::DomainType::NoAccess,
+is_atomic ? false : mode==Write,
+ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
+return f;
+}
+
// @todo: double check this (ARM ARM issue C B3.2.1)
if (long_desc_format || sctlr.tre == 0 || nmrr.ir0 == 0 ||
nmrr.or0 == 0 || prrr.tr0 != 0x2) {
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 04403fc..b61fc20 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -237,7 +237,7 @@
Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
bool isInstr);
int computeAddrTop(ThreadContext *tc, bool selbit, bool isInstr,
- TTBCR tcr, ExceptionLevel el);
+ TCR tcr, ExceptionLevel el);
static inline bool
inSecureState(SCR scr, CPSR cpsr)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iff3a1543df010b086813869b4b6c4fe776e74499
Gerrit-Change-Number: 30619
Gerrit-PatchSet: 5
Gerrit-Owner: Jordi Vaquero
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jordi Vaquero
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementation of Vector Catch debug exception
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30618 )
Change subject: arch-arm: Implementation of Vector Catch debug exception
..
arch-arm: Implementation of Vector Catch debug exception
This commit implements Vector Catch exception as they are described
in Armv8 reference manual chapter G2. This exception is just for AArch32.
+ tlb.cc: Implements the entry point for vector catch in addres mode
+ faults.hh/cc: Implements the entry point for vector catch in exception
trap mode.
+ miscregs.cc: enables the use of vector catch releated registers
+ miscregs_types.hh: New bitwise type for vector catch control registers.
+ types.hh: declaration of EC for vector catch exception
+ self_debug.hh/cc: Main implementation of the vector catch functions to
match address and exceptions type.
Change-Id: Idbef26b16eff059e94ff16fac13bf5708dfe647f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30618
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs_types.hh
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
M src/arch/arm/tlb.cc
M src/arch/arm/types.hh
8 files changed, 259 insertions(+), 9 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 6a3ee18..ecc9e4d 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -42,6 +42,8 @@
#include "arch/arm/faults.hh"
#include "arch/arm/insts/static_inst.hh"
+#include "arch/arm/isa.hh"
+#include "arch/arm/self_debug.hh"
#include "arch/arm/system.hh"
#include "arch/arm/utility.hh"
#include "base/compiler.hh"
@@ -480,7 +482,6 @@
void
ArmFault::invoke(ThreadContext *tc, const StaticInstPtr )
{
-
// Update fault state informations, like the starting mode (aarch32)
// or EL (aarch64) and the ending mode or EL.
// From the update function we are also evaluating if the fault must
@@ -493,6 +494,9 @@
return;
}
+if (vectorCatch(tc, inst))
+return;
+
// ARMv7 (ARM ARM issue C B1.9)
bool have_security = ArmSystem::haveSecurity(tc);
@@ -716,6 +720,21 @@
setSyndrome(tc, getSyndromeReg64());
}
+bool
+ArmFault::vectorCatch(ThreadContext *tc, const StaticInstPtr )
+{
+auto *isa = static_cast(tc->getIsaPtr());
+SelfDebug * sd = isa->getSelfDebug();
+VectorCatch* vc = sd->getVectorCatch(tc);
+if (!vc->isVCMatch()) {
+Fault fault = sd->testVectorCatch(tc, 0x0, this);
+if (fault != NoFault)
+fault->invoke(tc, inst);
+return true;
+}
+return false;
+}
+
ArmStaticInst *
ArmFault::instrAnnotate(const StaticInstPtr )
{
@@ -1094,7 +1113,9 @@
tc->setMiscReg(T::FarIndex, faultAddr);
if (debug == ArmFault::BRKPOINT){
Rext.moe = 0x1;
-} else if (debug > ArmFault::BRKPOINT) {
+} else if (debug == ArmFault::VECTORCATCH){
+Rext.moe = 0x5;
+} else if (debug > ArmFault::VECTORCATCH) {
Rext.moe = 0xa;
fsr.cm = (debug == ArmFault::WPOINT_CM)? 1 : 0;
}
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 8a127ff..a552757 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -154,6 +154,7 @@
{
NODEBUG = 0,
BRKPOINT,
+VECTORCATCH,
WPOINT_CM,
WPOINT_NOCM
};
@@ -226,6 +227,8 @@
void update(ThreadContext *tc);
bool isResetSPSR(){ return bStep; }
+bool vectorCatch(ThreadContext *tc, const StaticInstPtr );
+
ArmStaticInst *instrAnnotate(const StaticInstPtr );
virtual void annotate(AnnotationIDs id, uint64_t val) {}
virtual FaultStat& countStat() = 0;
@@ -241,12 +244,13 @@
virtual bool abortDisable(ThreadContext *tc) = 0;
virtual bool fiqDisable(ThreadContext *tc) = 0;
virtual ExceptionClass ec(ThreadContext *tc) const = 0;
+virtual uint32_t vectorCatchFlag() const { return 0x0; }
virtual uint32_t iss() const = 0;
virtual bool isStage2() const { return false; }
virtual FSR getFsr(ThreadContext *tc) const { return 0; }
virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg);
virtual bool getFaultVAddr(Addr ) const { return false; }
-
+OperatingMode getToMode() const { return toMode; }
};
template
@@ -323,6 +327,7 @@
bool routeToHyp(ThreadContext *tc) const override;
ExceptionClass ec(ThreadContext *tc) const override;
uint32_t iss() const override;
+uint32_t vectorCatchFlag() const override { return 0x0202; }
};
class SupervisorCall : public ArmFaultVals
@@ -343,6 +348,7 @@
bool
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementation of SelfHosted Debug Software step
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30617 )
Change subject: arch-arm: Implementation of SelfHosted Debug Software step
..
arch-arm: Implementation of SelfHosted Debug Software step
This commit implements SelfHosted Debug Software step as is defined in
Armv8 Reference manual chapter D2.
+ decoder.hh/cc/isa: Checks the software step bit in order to skip the
instruction
before its decode.
+ faults.hh/cc: implemented SoftwareStep exception and proper modification
of spsr during the invoke of other exceptions
+ isa.cc: Set debug mask if needed during cpsr modification
+ tlb.cc: Checks if software step is in ACTIVE state to avoid trigger
breakpoint or watchpoint exception
+ self_debug.hh/cc: Implementation of State change and ss bit based during
eret.
+ types.hh: Define sofware step flags like step, load or stepped to check
the different flags
that triggering software step should use for the ISS code.
+ pseudo.hh/isa: Triggers the sofware step esception after decode.
+ static_inst.cc: Call debugExceptionReturnsSS durint eret routine.
Change-Id: I3a64507c64842c34c76ad7f6daa5f4306bd55d2c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30617
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/decoder.cc
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
M src/arch/arm/insts/pseudo.cc
M src/arch/arm/insts/pseudo.hh
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/isa.cc
M src/arch/arm/isa/bitfields.isa
M src/arch/arm/isa/decoder/decoder.isa
M src/arch/arm/isa/formats/pseudo.isa
M src/arch/arm/isa/insts/ldr.isa
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
M src/arch/arm/tlb.cc
M src/arch/arm/types.hh
16 files changed, 364 insertions(+), 36 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/decoder.cc b/src/arch/arm/decoder.cc
index 8f37e63..d7de6a2 100644
--- a/src/arch/arm/decoder.cc
+++ b/src/arch/arm/decoder.cc
@@ -53,7 +53,8 @@
GenericISA::BasicDecodeCache Decoder::defaultCache;
Decoder::Decoder(ISA* isa)
-: data(0), fpscrLen(0), fpscrStride(0),
decoderFlavor(isa->decoderFlavor())
+: data(0), fpscrLen(0), fpscrStride(0),
+ decoderFlavor(isa->decoderFlavor())
{
reset();
@@ -181,7 +182,7 @@
pc.nextItstate(itBits);
this_emi.itstate = pc.itstate();
this_emi.illegalExecution = pc.illegalExec() ? 1 : 0;
-
+this_emi.debugStep = pc.debugStep() ? 1 : 0;
pc.size(inst_size);
emi = 0;
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index ce9675a..6a3ee18 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -289,6 +289,10 @@
"Watchpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
0, 0, 0, 0, true, false, false, EC_WATCHPOINT
);
+template<> ArmFault::FaultVals ArmFaultVals::vals(
+"SoftwareStep", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
+0, 0, 0, 0, true, false, false, EC_SOFTWARE_STEP
+);
template<> ArmFault::FaultVals ArmFaultVals::vals(
// Some dummy values
"ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
@@ -649,6 +653,7 @@
spsr.nz = tc->readCCReg(CCREG_NZ);
spsr.c = tc->readCCReg(CCREG_C);
spsr.v = tc->readCCReg(CCREG_V);
+spsr.ss = isResetSPSR() ? 0: cpsr.ss;
if (from64) {
// Force some bitfields to 0
spsr.q = 0;
@@ -662,8 +667,6 @@
ITSTATE it = tc->pcState().itstate();
spsr.it2 = it.top6;
spsr.it1 = it.bottom2;
-// Force some bitfields to 0
-spsr.ss = 0;
}
tc->setMiscReg(spsr_idx, spsr);
@@ -705,6 +708,7 @@
pc.aarch64(!cpsr.width);
pc.nextAArch64(!cpsr.width);
pc.illegalExec(false);
+pc.stepped(false);
tc->pcState(pc);
// Save exception syndrome
@@ -911,7 +915,9 @@
HypervisorCall::HypervisorCall(ExtMachInst _machInst, uint32_t _imm) :
ArmFaultVals(_machInst, _imm)
-{}
+{
+bStep = true;
+}
ExceptionClass
HypervisorCall::ec(ThreadContext *tc) const
@@ -1739,6 +1745,52 @@
return EC_WATCHPOINT_LOWER_EL;
}
+SoftwareStepFault::SoftwareStepFault(ExtMachInst _mach_inst, bool is_ldx,
+ bool _stepped)
+: ArmFaultVals(_mach_inst), isldx(is_ldx),
+ stepped(_stepped)
+{
+bStep = true;
+}
+
+bool
+SoftwareStepFault::routeToHyp(ThreadContext *tc) const
+{
+const bool have_el2 = ArmSystem::haveVirtualization(tc);
+
+const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
+
+return have_el2 && !inSecureState(tc) && fromEL <= EL1 &&
+(hcr.tge ||
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix minor bug PAUTH comparision with 0
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30615 )
Change subject: arch-arm: Fix minor bug PAUTH comparision with 0
..
arch-arm: Fix minor bug PAUTH comparision with 0
Change-Id: I887e5fa256a8c9cc24f7b9ef1fc0353dea555e82
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30615
Tested-by: kokoro
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
---
M src/arch/arm/pauth_helpers.cc
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/pauth_helpers.cc b/src/arch/arm/pauth_helpers.cc
index 1c83d77..c88795f 100644
--- a/src/arch/arm/pauth_helpers.cc
+++ b/src/arch/arm/pauth_helpers.cc
@@ -706,7 +706,7 @@
{
case EL0:
trapEL2 = (EL2Enabled(tc) && hcr.api == 0 &&
- (hcr.tge == '0' || hcr.e2h == 0));
+ (hcr.tge == 0 || hcr.e2h == 0));
trapEL3 = have_el3 && sc3.api == 0;
break;
case EL1:
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30615
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I887e5fa256a8c9cc24f7b9ef1fc0353dea555e82
Gerrit-Change-Number: 30615
Gerrit-PatchSet: 4
Gerrit-Owner: Jordi Vaquero
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jordi Vaquero
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix SCR.NS compare to 0
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30614 )
Change subject: arch-arm: Fix SCR.NS compare to 0
..
arch-arm: Fix SCR.NS compare to 0
Change-Id: Iba7628640bb222fd21fd067ff60dbe4d34f4b196
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30614
Tested-by: kokoro
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
---
M src/arch/arm/insts/static_inst.hh
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/insts/static_inst.hh
b/src/arch/arm/insts/static_inst.hh
index 82bf61d..8610f99 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -257,7 +257,7 @@
validModeChange = false;
// There is no Hyp mode ('11010') in Secure state, so
that
// is UNPREDICTABLE
-if (scr.ns == '0' && newMode == MODE_HYP)
+if (scr.ns == 0 && newMode == MODE_HYP)
validModeChange = false;
// Cannot move into Hyp mode directly from a Non-secure
// PL1 mode
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iba7628640bb222fd21fd067ff60dbe4d34f4b196
Gerrit-Change-Number: 30614
Gerrit-PatchSet: 4
Gerrit-Owner: Jordi Vaquero
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jordi Vaquero
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix routeToHyp conditions for Excp Type
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30620 )
Change subject: arch-arm: Fix routeToHyp conditions for Excp Type
..
arch-arm: Fix routeToHyp conditions for Excp Type
Change-Id: I8eadd8e1f8c53d5e61969b492d9f2cbd12110188
---
M src/arch/arm/faults.cc
1 file changed, 8 insertions(+), 43 deletions(-)
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index ba8369a..00a70ed 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -857,17 +857,8 @@
bool
SupervisorCall::routeToHyp(ThreadContext *tc) const
{
-bool toHyp;
-
-SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
-// if in Hyp mode then stay in Hyp mode
-toHyp = scr.ns && (cpsr.mode == MODE_HYP);
-// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
-toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
-return toHyp;
+return EL2Enabled(tc) && currEL(tc) == EL0 && hcr.tge == 1;
}
ExceptionClass
@@ -999,15 +990,8 @@
bool
SupervisorTrap::routeToHyp(ThreadContext *tc) const
{
-bool toHyp = false;
-
-SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
-// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
-toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
-return toHyp;
+return hcr.tge && (currEL(tc) <= EL1) && EL2Enabled(tc);
}
uint32_t
@@ -1289,6 +1273,7 @@
// if in Hyp mode then stay in Hyp mode
toHyp = scr.ns && (currEL(tc) == EL2);
+toHyp |= (currEL(tc) <= EL1) && hcr.tge;
// otherwise, check whether to take to Hyp mode through Hyp Trap vector
toHyp |= (stage2 ||
((source == DebugEvent) && (hdcr.tde || hcr.tge) &&
@@ -1350,6 +1335,7 @@
// if in Hyp mode then stay in Hyp mode
toHyp = scr.ns && (currEL(tc) == EL2);
+toHyp |= (currEL(tc) <= EL1 && hcr.tge==1);
// otherwise, check whether to take to Hyp mode through Hyp Trap vector
toHyp |= (stage2 ||
((currEL(tc) != EL2) &&
@@ -1450,15 +1436,8 @@
bool
Interrupt::routeToHyp(ThreadContext *tc) const
{
-bool toHyp;
-
-SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-// Determine whether IRQs are routed to Hyp mode.
-toHyp = (!scr.irq && hcr.imo && !inSecureState(tc)) ||
-(cpsr.mode == MODE_HYP);
-return toHyp;
+return EL2Enabled(tc) &(tc) <= EL1 && (hcr.tge==1 || hcr.fmo);
}
bool
@@ -1489,15 +1468,8 @@
bool
FastInterrupt::routeToHyp(ThreadContext *tc) const
{
-bool toHyp;
-
-SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-// Determine whether IRQs are routed to Hyp mode.
-toHyp = (!scr.fiq && hcr.fmo && !inSecureState(tc)) ||
-(cpsr.mode == MODE_HYP);
-return toHyp;
+return EL2Enabled(tc) &(tc) <= EL1 && (hcr.tge == 1 || hcr.fmo);
}
bool
@@ -1537,15 +1509,8 @@
bool
PCAlignmentFault::routeToHyp(ThreadContext *tc) const
{
-bool toHyp = false;
-
-SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
-// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
-toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
-return toHyp;
+return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge == 1;
}
SPAlignmentFault::SPAlignmentFault()
@@ -1556,7 +1521,7 @@
{
assert(from64);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
-return EL2Enabled(tc) && hcr.tge==1;
+return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge == 1;
}
SystemError::SystemError()
--
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Gerrit-Change-Id: I8eadd8e1f8c53d5e61969b492d9f2cbd12110188
Gerrit-Change-Number: 30620
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add Check for AddressSize Fault
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30619 )
Change subject: arch-arm: Add Check for AddressSize Fault
..
arch-arm: Add Check for AddressSize Fault
This patch add a check for AddressSize Fault during translation when
MMU is disabled.
Change-Id: Iff3a1543df010b086813869b4b6c4fe776e74499
---
M src/arch/arm/tlb.cc
1 file changed, 18 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index a00cba8..8a6e684 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1011,12 +1011,30 @@
TLB::ArmTranslationType tranType, Addr vaddr, bool
long_desc_format)
{
bool is_fetch = (mode == Execute);
+bool is_atomic = req->isAtomic();
req->setPaddr(vaddr);
// When the MMU is off the security attribute corresponds to the
// security state of the processor
if (isSecure)
req->setFlags(Request::SECURE);
+bool selbit = bits(vaddr, 55);
+TCR tcr1 = tc->readMiscReg(MISCREG_TCR_EL1);
+int topbit = computeAddrTop(tc, selbit, is_fetch, tcr1, currEL(tc));
+int addr_sz = bits(vaddr, topbit, MaxPhysAddrRange);
+if (addr_sz != 0){
+Fault f;
+if (is_fetch)
+f = std::make_shared(vaddr,
+ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
+else
+f = std::make_shared( vaddr,
+TlbEntry::DomainType::NoAccess,
+is_atomic ? false : mode==Write,
+ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
+return f;
+}
+
// @todo: double check this (ARM ARM issue C B3.2.1)
if (long_desc_format || sctlr.tre == 0 || nmrr.ir0 == 0 ||
nmrr.or0 == 0 || prrr.tr0 != 0x2) {
--
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Gerrit-Change-Id: Iff3a1543df010b086813869b4b6c4fe776e74499
Gerrit-Change-Number: 30619
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementation of Vector Catch debug exception
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30618 )
Change subject: arch-arm: Implementation of Vector Catch debug exception
..
arch-arm: Implementation of Vector Catch debug exception
This commit implements Vector Catch exception as they are described
in Armv8 reference manual chapter G2. This exception is just for AArch32.
+ tlb.cc: Implements the entry point for vector catch in addres mode
+ faults.hh/cc: Implements the entry point for vector catch in exception
trap mode.
+ miscregs.cc: enables the use of vector catch releated registers
+ miscregs_types.hh: New bitwise type for vector catch control registers.
+ types.hh: declaration of EC for vector catch exception
+ self_debug.hh/cc: Main implementation of the vector catch functions to
match address and exceptions type.
Change-Id: Idbef26b16eff059e94ff16fac13bf5708dfe647f
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs_types.hh
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
M src/arch/arm/tlb.cc
M src/arch/arm/types.hh
8 files changed, 321 insertions(+), 7 deletions(-)
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index fde28d6..422e801 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -42,6 +42,8 @@
#include "arch/arm/faults.hh"
#include "arch/arm/insts/static_inst.hh"
+#include "arch/arm/isa.hh"
+#include "arch/arm/self_debug.hh"
#include "arch/arm/system.hh"
#include "arch/arm/utility.hh"
#include "base/compiler.hh"
@@ -481,6 +483,16 @@
ArmFault::invoke(ThreadContext *tc, const StaticInstPtr )
{
+auto *isa = static_cast(tc->getIsaPtr());
+SelfDebug * sd = isa->getSelfDebug();
+VectorCatch* vc = sd->getVectorCatch(tc);
+if (!vc->isVCMatch()){
+Fault flt = sd->testVectorCatch(tc, 0x0, this);
+if (flt != NoFault)
+flt->invoke(tc, inst);
+return;
+}
+
// Update fault state informations, like the starting mode (aarch32)
// or EL (aarch64) and the ending mode or EL.
// From the update function we are also evaluating if the fault must
@@ -1094,7 +1106,9 @@
tc->setMiscReg(T::FarIndex, faultAddr);
if (debug == ArmFault::BRKPOINT){
Rext.moe = 0x1;
-} else if (debug > ArmFault::BRKPOINT) {
+} else if (debug == ArmFault::VECTORCATCH){
+Rext.moe = 0x5;
+} else if (debug > ArmFault::VECTORCATCH) {
Rext.moe = 0xa;
fsr.cm = (debug == ArmFault::WPOINT_CM)? 1 : 0;
}
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 703d6bb..a7bda4f 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -154,6 +154,7 @@
{
NODEBUG = 0,
BRKPOINT,
+VECTORCATCH,
WPOINT_CM,
WPOINT_NOCM
};
@@ -246,7 +247,7 @@
virtual FSR getFsr(ThreadContext *tc) const { return 0; }
virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg);
virtual bool getFaultVAddr(Addr ) const { return false; }
-
+OperatingMode getToMode() const { return toMode; }
};
template
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index aae12d5..d5eb757 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -61,6 +61,8 @@
return MISCREG_DBGDIDR;
case 1:
return MISCREG_DBGDSCRint;
+ case 7:
+return MISCREG_DBGVCR;
}
break;
case 2:
@@ -564,6 +566,12 @@
return MISCREG_BPIALLIS;
}
break;
+ case 2:
+switch (opc2){
+ case 7:
+return MISCREG_DBGDEVID0;
+}
+break;
case 4:
if (opc2 == 0) {
return MISCREG_PAR;
@@ -3418,8 +3426,7 @@
.unimplemented()
.allPrivileges();
InitReg(MISCREG_DBGVCR)
- .unimplemented()
- .allPrivileges();
+ .allPrivileges().exceptUserMode();
InitReg(MISCREG_DBGDTRRXext)
.unimplemented()
.allPrivileges();
@@ -3625,7 +3632,6 @@
.unimplemented()
.allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
InitReg(MISCREG_DBGDEVID0)
- .unimplemented()
.allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
InitReg(MISCREG_TEECR)
.unimplemented()
@@ -4532,7 +4538,7 @@
InitReg(MISCREG_MDDTRRX_EL0)
.allPrivileges();
InitReg(MISCREG_DBGVCR32_EL2)
- .allPrivileges()
+ .allPrivileges().exceptUserMode()
.mapsTo(MISCREG_DBGVCR);
InitReg(MISCREG_MDRAR_EL1)
.allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
diff
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementation of SelfHosted Debug Software step
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30617 )
Change subject: arch-arm: Implementation of SelfHosted Debug Software step
..
arch-arm: Implementation of SelfHosted Debug Software step
This commit implements SelfHosted Debug Software step as is defined in
Armv8 Reference manual chapter D2.
+ decoder.hh/cc/isa: Checks the software step bit in order to skip the
instruction
before its decode.
+ faults.hh/cc: implemented SoftwareStep exception and proper modification
of spsr during the invoke of other exceptions
+ isa.cc: Set debug mask if needed during cpsr modification
+ tlb.cc: Checks if software step is in ACTIVE state to avoid trigger
breakpoint or watchpoint exception
+ self_debug.hh/cc: Implementation of State change and ss bit based during
eret.
+ types.hh: Define sofware step flags like step, load or stepped to check
the different flags
that triggering software step should use for the ISS code.
+ pseudo.hh/isa: Triggers the sofware step esception after decode.
+ static_inst.cc: Call debugExceptionReturnsSS durint eret routine.
Change-Id: I3a64507c64842c34c76ad7f6daa5f4306bd55d2c
---
M src/arch/arm/decoder.cc
M src/arch/arm/decoder.hh
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
M src/arch/arm/insts/pseudo.cc
M src/arch/arm/insts/pseudo.hh
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/isa.cc
M src/arch/arm/isa/bitfields.isa
M src/arch/arm/isa/decoder/decoder.isa
M src/arch/arm/isa/formats/pseudo.isa
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
M src/arch/arm/tlb.cc
M src/arch/arm/types.hh
15 files changed, 384 insertions(+), 31 deletions(-)
diff --git a/src/arch/arm/decoder.cc b/src/arch/arm/decoder.cc
index 8f37e63..5b2dd1e 100644
--- a/src/arch/arm/decoder.cc
+++ b/src/arch/arm/decoder.cc
@@ -53,7 +53,9 @@
GenericISA::BasicDecodeCache Decoder::defaultCache;
Decoder::Decoder(ISA* isa)
-: data(0), fpscrLen(0), fpscrStride(0),
decoderFlavor(isa->decoderFlavor())
+: data(0), fpscrLen(0), fpscrStride(0),
+ softStep(isa->getSelfDebug()->get_Sstep()),
+ decoderFlavor(isa->decoderFlavor())
{
reset();
@@ -181,13 +183,34 @@
pc.nextItstate(itBits);
this_emi.itstate = pc.itstate();
this_emi.illegalExecution = pc.illegalExec() ? 1 : 0;
-
+this_emi.debugStep = pc.debugStep() ? 1 : 0;
pc.size(inst_size);
emi = 0;
instDone = false;
foundIt = false;
+bool ldx = false;
+if (pc.aarch64()){
+unsigned b1 = bits(this_emi, 29, 16);
+ldx = (b1 == 0x087F) || (b1 == 0x085F);
+} else {
+if (pc.thumb()){
+unsigned b1 = bits(this_emi, 31, 20); //bits high 15, 4
+unsigned b2 = bits(this_emi, 6);
+ldx = (b1 == 0xE85 || (b1 == 0xE8B && b2 == 0x1));
+
+} else {
+unsigned b1 = bits(this_emi, 31, 28);
+unsigned b2 = bits(this_emi, 27, 23);
+unsigned L = bits(this_emi, 20);
+unsigned ex = bits(this_emi, 11, 9);
+ldx = (b1 != 0xF && b2 == 0x3 && L == 0x1 && ex == 0x7);
+}
+
+}
+
+pc.ldx(ldx);
return decode(this_emi, pc.instAddr());
}
diff --git a/src/arch/arm/decoder.hh b/src/arch/arm/decoder.hh
index 774aedd..b714fe4 100644
--- a/src/arch/arm/decoder.hh
+++ b/src/arch/arm/decoder.hh
@@ -44,6 +44,7 @@
#include
#include "arch/arm/miscregs.hh"
+#include "arch/arm/self_debug.hh"
#include "arch/arm/types.hh"
#include "arch/generic/decode_cache.hh"
#include "base/types.hh"
@@ -70,6 +71,8 @@
int fpscrLen;
int fpscrStride;
+SoftwareStep * softStep;
+
/**
* SVE vector length, encoded in the same format as the ZCR_EL.LEN
* bitfields.
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index ce9675a..fde28d6 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -289,6 +289,10 @@
"Watchpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
0, 0, 0, 0, true, false, false, EC_WATCHPOINT
);
+template<> ArmFault::FaultVals ArmFaultVals::vals(
+"SoftwareStep", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
+0, 0, 0, 0, true, false, false, EC_SOFTWARE_STEP
+);
template<> ArmFault::FaultVals ArmFaultVals::vals(
// Some dummy values
"ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
@@ -649,6 +653,7 @@
spsr.nz = tc->readCCReg(CCREG_NZ);
spsr.c = tc->readCCReg(CCREG_C);
spsr.v = tc->readCCReg(CCREG_V);
+spsr.ss = isResetSPSR() ? 0: cpsr.ss;
if (from64) {
// Force some bitfields to 0
spsr.q = 0;
@@ -662,8 +667,6 @@
ITSTATE it = tc->pcState().itstate();
spsr.it2 = it.top6;
spsr.it1 = it.bottom2;
-// Force some bitfields to 0
-spsr.ss = 0;
}
tc->setMiscReg(spsr_idx, spsr);
@@ -705,6 +708,7 @@
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix minor bug PAUTH comparision with 0
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30615 )
Change subject: arch-arm: Fix minor bug PAUTH comparision with 0
..
arch-arm: Fix minor bug PAUTH comparision with 0
Change-Id: I887e5fa256a8c9cc24f7b9ef1fc0353dea555e82
---
M src/arch/arm/pauth_helpers.cc
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/arch/arm/pauth_helpers.cc b/src/arch/arm/pauth_helpers.cc
index 1c83d77..c88795f 100644
--- a/src/arch/arm/pauth_helpers.cc
+++ b/src/arch/arm/pauth_helpers.cc
@@ -706,7 +706,7 @@
{
case EL0:
trapEL2 = (EL2Enabled(tc) && hcr.api == 0 &&
- (hcr.tge == '0' || hcr.e2h == 0));
+ (hcr.tge == 0 || hcr.e2h == 0));
trapEL3 = have_el3 && sc3.api == 0;
break;
case EL1:
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I887e5fa256a8c9cc24f7b9ef1fc0353dea555e82
Gerrit-Change-Number: 30615
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix SCR.NS compare to 0
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30614 )
Change subject: arch-arm: Fix SCR.NS compare to 0
..
arch-arm: Fix SCR.NS compare to 0
Change-Id: Iba7628640bb222fd21fd067ff60dbe4d34f4b196
---
M src/arch/arm/insts/static_inst.hh
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/arch/arm/insts/static_inst.hh
b/src/arch/arm/insts/static_inst.hh
index 82bf61d..8610f99 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -257,7 +257,7 @@
validModeChange = false;
// There is no Hyp mode ('11010') in Secure state, so
that
// is UNPREDICTABLE
-if (scr.ns == '0' && newMode == MODE_HYP)
+if (scr.ns == 0 && newMode == MODE_HYP)
validModeChange = false;
// Cannot move into Hyp mode directly from a Non-secure
// PL1 mode
--
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Gerrit-Change-Id: Iba7628640bb222fd21fd067ff60dbe4d34f4b196
Gerrit-Change-Number: 30614
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Gerrit-Owner: Jordi Vaquero
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix SVE indx inst by sizeof error and dest overwrite
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28228 )
Change subject: arch-arm: Fix SVE indx inst by sizeof error and dest
overwrite
..
arch-arm: Fix SVE indx inst by sizeof error and dest overwrite
This patch includes two fixes for SVE FMUL; FMLA FMLS AND FCMLA instructions
+ Fixes indexed functions like FMUL, FMLA, FMLS, FCMLA due to its
destination register overwrite with temporary values, wince the imm
can make changes in vector positions that will be read in the future.
+ sizeof return bytes not bits so division of 128 shouild be of 16 instead
Change-Id: I304d1b254a299069c85bbc3319e5a6d4119436d0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28228
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/isa/insts/sve.isa
1 file changed, 33 insertions(+), 21 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index 16597d6..9314ba9 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -1835,26 +1835,25 @@
xc->tcBase());
// Number of elements in a 128 bit segment
-constexpr unsigned ePerSegment = 128 / sizeof(Element);
+constexpr unsigned ePerSegment = 16 / sizeof(Element);
-'''
-
-code += '''
+ArmISA::VecRegContainer tmpC;
+auto auxDest = tmpC.as();
for (unsigned i = 0; i < eCount; i++) {
-const auto segmentBase = i - i % ePerSegment;
-const auto segmentIdx = segmentBase + index;
+const auto segmentBase = i - i %% ePerSegment;
+const auto segmentIdx = segmentBase + index;
-const Element& srcElem1 = AA64FpOp1_x[i];
-const Element& srcElem2 = AA64FpOp2_x[segmentIdx];
-Element destElem = 0;
+const Element& srcElem1 = AA64FpOp1_x[i];
+const Element& srcElem2 = AA64FpOp2_x[segmentIdx];
+Element destElem = 0;
-'''
-
-code += '''
-%(op)s
-AA64FpDest_x[i] = destElem;
+%(op)s
+auxDest[i] = destElem;
}
-''' % {'op': op}
+
+for (unsigned i = 0; i < eCount; i++) {
+AA64FpDest_x[i] = auxDest[i];
+}''' % {'op':op}
baseClass = 'SveBinIdxUnpredOp'
@@ -2067,8 +2066,10 @@
xc->tcBase());
// Number of elements in a 128 bit segment
-constexpr unsigned ePerSegment = 128 / sizeof(Element);
+constexpr unsigned ePerSegment = 16 / sizeof(Element);
+ArmISA::VecRegContainer tmpC;
+auto auxDest = tmpC.as();
for (unsigned i = 0; i < eCount; i++) {
const auto segmentBase = i - i % ePerSegment;
const auto segmentIdx = segmentBase + index;
@@ -2077,10 +2078,13 @@
const Element& srcElem2 = AA64FpOp2_x[segmentIdx];
Element destElem = AA64FpDestMerge_x[i];
'''
-
code += '''
%(op)s
-AA64FpDest_x[i] = destElem;
+auxDest[i] = destElem;
+}
+
+for (unsigned i = 0; i < eCount; i++) {
+AA64FpDest_x[i] = auxDest[i];
}''' % {'op': op}
iop = InstObjParams(name, 'Sve' + Name, 'SveBinIdxUnpredOp',
@@ -3024,6 +3028,9 @@
code += '''
uint32_t eltspersegment = 16 / (2 * sizeof(Element));'''
code += '''
+ArmISA::VecRegContainer tmpC;
+auto auxDest = tmpC.as();
+
for (int i = 0; i < eCount / 2; ++i) {'''
if predType == PredType.NONE:
code += '''
@@ -3067,9 +3074,14 @@
code += '''
}'''
code += '''
-AA64FpDest_x[2 * i] = addend_r;
-AA64FpDest_x[2 * i + 1] = addend_i;
-}'''
+auxDest[2 * i] = addend_r;
+auxDest[2 * i + 1] = addend_i;
+}
+
+for (unsigned i = 0; i < eCount; i++) {
+AA64FpDest_x[i] = auxDest[i];
+}
+'''
iop = InstObjParams(name, 'Sve' + Name,
'SveComplexIdxOp' if predType == PredType.NONE
else 'SveComplexOp',
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I304d1b254a299069c85bbc3319e5a6d4119436d0
Gerrit-Change-Number: 28228
Gerrit-PatchSet: 4
Gerrit-Owner: Jordi Vaquero
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jordi Vaquero
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: FCVTZS instruction returns sign extension
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28229 )
Change subject: arch-arm: FCVTZS instruction returns sign extension
..
arch-arm: FCVTZS instruction returns sign extension
This patch fix Fcvtzs instruction adding sign extension instead of
zero extension
Change-Id: I28cdca432fa6baa8a524de4c431f492f23f0e9a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28229
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/isa/insts/sve.isa
1 file changed, 29 insertions(+), 6 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index aa4f194..16597d6 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -1516,27 +1516,49 @@
# Generates definitions for SVE floating-point conversions (always
# unary, constructive, merging
def sveCvtInst(name, Name, opClass, types, op, direction=CvtDir.Narrow,
- decoder='Generic'):
+ decoder='Generic', signed=False):
global header_output, exec_output, decoders
+
+if signed:
+mask = "SElement msk = mask(sizeof(DElement)*8);"
+assign_code = '''
+int sign_bit = bits(destElem, sizeof(DElement)*8 -1);
+AA64FpDest_x%(bigElemSuffix)s[i] =
+sign_bit? (destElem|~msk): destElem;
+ ''' % {
+ 'bigElemSuffix': 's' if direction == CvtDir.Narrow else 'd'
+ }
+else:
+mask = "";
+assign_code = '''
+AA64FpDest_x%(bigElemSuffix)s[i] = destElem;
+''' % {
+ 'bigElemSuffix': 's' if direction == CvtDir.Narrow else 'd'
+ }
+
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<%(bigElemType)s>(
xc->tcBase());
+%(mask)s
for (unsigned i = 0; i < eCount; i++) {
SElement srcElem1 = AA64FpOp1_x%(bigElemSuffix)s[i] &
mask(sizeof(SElement) * 8);
DElement destElem = 0;
if (GpOp_x%(bigElemSuffix)s[i]) {
%(op)s
-AA64FpDest_x%(bigElemSuffix)s[i] = destElem;
+%(assign)s;
} else {
AA64FpDest_x%(bigElemSuffix)s[i] =
AA64FpDestMerge_x%(bigElemSuffix)s[i];
}
}
-''' % {'op': op,
- 'bigElemType': 'SElement' if direction == CvtDir.Narrow
+''' % {'bigElemType': 'SElement' if direction == CvtDir.Narrow
else 'DElement',
- 'bigElemSuffix': 's' if direction == CvtDir.Narrow else 'd'}
+ 'op': op, 'mask': mask,
+ 'bigElemSuffix': 's' if direction == CvtDir.Narrow else 'd',
+ 'assign': assign_code
+ }
+
iop = InstObjParams(name, 'Sve' + Name, 'SveUnaryPredOp',
{'code': code, 'op_class': opClass}, [])
header_output += SveWideningUnaryPredOpDeclare.subst(iop)
@@ -2743,6 +2765,7 @@
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen(
xc->tcBase());
+
ArmISA::VecRegContainer tmpVecC;
auto auxDest = tmpVecC.as();
int firstelem = -1, lastelem = -2;
@@ -3596,7 +3619,7 @@
'uint32_t, uint32_t',
'uint64_t, uint32_t',
'uint64_t, uint64_t'),
- fcvtzsCode, CvtDir.Narrow)
+ fcvtzsCode, CvtDir.Narrow, signed=True)
sveCvtInst('fcvtzs', 'FcvtzsWiden', 'SimdCvtOp',
('uint16_t, uint32_t',
'uint16_t, uint64_t',
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I28cdca432fa6baa8a524de4c431f492f23f0e9a6
Gerrit-Change-Number: 28229
Gerrit-PatchSet: 3
Gerrit-Owner: Jordi Vaquero
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jordi Vaquero
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementation of ARMv8 SelfDebug Watchpoints
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28589 )
Change subject: arch-arm: Implementation of ARMv8 SelfDebug Watchpoints
..
arch-arm: Implementation of ARMv8 SelfDebug Watchpoints
This change includes ArmV8 SelfDebug Watchpoint implementation
as is described in Armv8 Reference manual D2/G2
The changes specific descriptions are as follow:
+ ArmISA.py: Enable up to 16 DBGWn registers
+ isa.cc: Include in setMiscReg specific cases for DBGWCn registers enable
bit
+ miscregs_types.hh: Define DBGWC bitwise types
+ miscregs.hh/cc: Definition of watchpoint registers and its initialization
+ tlb.cc: Call for watchpoint entry point on tlb translation for dtlb.
+ fault.cc/hh: Definition/implementation of Watchpoint exception and
modification on DataAbort Exception accordingly to handle
AArch32 Watchpoint exceptions.
+ types.hh: Exception Code for watchpoint.
+ self_debug.cc/hh: Watchpoint check and comparison. Definition and
implementation of all the watchpoint auxiliar functions.
Change-Id: If275e4df0d28918dd887ab78166e653da875310a
---
M src/arch/arm/ArmISA.py
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
M src/arch/arm/isa.cc
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/miscregs_types.hh
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/types.hh
12 files changed, 862 insertions(+), 32 deletions(-)
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index b030e6c..f701f7d 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -90,8 +90,8 @@
id_aa64afr1_el1 = Param.UInt64(0x,
"AArch64 Auxiliary Feature Register 1")
-# 1 CTX CMPs | 2 WRPs | 16 BRPs | !PMU | !Trace | Debug v8-A
-id_aa64dfr0_el1 = Param.UInt64(0x0010F006,
+# 1 CTX CMPs | 16 WRPs | 16 BRPs | !PMU | !Trace | Debug v8-A
+id_aa64dfr0_el1 = Param.UInt64(0x00F0F006,
"AArch64 Debug Feature Register 0")
# Reserved for future expansion
id_aa64dfr1_el1 = Param.UInt64(0x,
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index ba8369a..28719c0 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -285,6 +285,10 @@
"Hardware Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
0, 0, 0, 0, true, false, false, EC_HW_BREAKPOINT
);
+template<> ArmFault::FaultVals ArmFaultVals::vals(
+"Watchpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
+0, 0, 0, 0, true, false, false, EC_WATCHPOINT
+);
template<> ArmFault::FaultVals ArmFaultVals::vals(
// Some dummy values
"ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
@@ -1084,6 +1088,9 @@
tc->setMiscReg(T::FarIndex, faultAddr);
if (debug == ArmFault::BRKPOINT){
Rext.moe = 0x1;
+} else if (debug > ArmFault::BRKPOINT) {
+Rext.moe = 0xa;
+fsr.cm = (debug == ArmFault::WPOINT_CM)? 1 : 0;
}
tc->setMiscReg(T::FsrIndex, fsr);
@@ -1354,10 +1361,10 @@
toHyp |= (stage2 ||
((currEL(tc) != EL2) &&
(((source == AsynchronousExternalAbort) && hcr.amo) ||
-((source == DebugEvent) && hdcr.tde))) ||
- ((currEL(tc) == EL0) && hcr.tge &&
-((source == AlignmentFault) ||
- (source == SynchronousExternalAbort
&& !inSecureState(tc);
+((source == DebugEvent) && (hdcr.tde || hcr.tge ||
+ ((currEL(tc) == EL0) && hcr.tge &&
+ ((source == AlignmentFault) ||
+(source == SynchronousExternalAbort
&& !inSecureState(tc);
return toHyp;
}
@@ -1668,6 +1675,70 @@
}
+Watchpoint::Watchpoint(ExtMachInst _mach_inst, Addr _vaddr,
+ bool _write, bool _cm)
+: ArmFaultVals(_mach_inst), vAddr(_vaddr),
+ write(_write), cm(_cm)
+{}
+
+uint32_t
+Watchpoint::iss() const
+{
+uint32_t iss = 0x0022;
+if (toEL == EL2)
+iss |= 0x02000;
+if (cm)
+iss |= 0x00100;
+if (write)
+iss |= 0x00040;
+return iss;
+}
+
+void
+Watchpoint::invoke(ThreadContext *tc, const StaticInstPtr )
+{
+ArmFaultVals::invoke(tc, inst);
+// Set the FAR
+tc->setMiscReg(getFaultAddrReg64(), vAddr);
+
+}
+bool
+Watchpoint::routeToHyp(ThreadContext *tc) const
+{
+const bool have_el2 = ArmSystem::haveVirtualization(tc);
+
+const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
+
+return have_el2 && !inSecureState(tc) && fromEL <= EL1 &&
+(hcr.tge || mdcr.tde);
+}
+
+void
+Watchpoint::annotate(AnnotationIDs id, uint64_t val)
+{
+
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix clasta/b and lasta/b simd instructions
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28247 )
Change subject: arch-arm: Fix clasta/b and lasta/b simd instructions
..
arch-arm: Fix clasta/b and lasta/b simd instructions
The simd version of this instructions required zeroing the result
vector except for the first element, that contains the result.
Change-Id: I231ad3c44d89f34acae26d299ab676e2ed09acdc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28247
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/isa/insts/sve.isa
1 file changed, 10 insertions(+), 1 deletion(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index 06ff728..aa4f194 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -2432,7 +2432,16 @@
elif destType == DstRegType.SimdFpScalar:
code += ''' else {
AA64FpDest_x[0] = AA64FpDestMerge_x[0];
-}'''
+}
+'''
+if destType == DstRegType.SimdFpScalar:
+# This section will extend zeros to the simdFP scalar
+# intructions for lasta/b and Clasta/b
+code += '''
+for (int i = 1; i < eCount; ++i) {
+AA64FpDest_x[i] = (Element)0x0;
+}
+'''
iop = InstObjParams(name, 'Sve' + Name, 'SveSelectOp',
{'code': code, 'op_class': opClass,
'isCond': 'true' if isCond else 'false',
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I231ad3c44d89f34acae26d299ab676e2ed09acdc
Gerrit-Change-Number: 28247
Gerrit-PatchSet: 2
Gerrit-Owner: Jordi Vaquero
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jordi Vaquero
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix clasta/b and lasta/b simd instructions
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28247 )
Change subject: arch-arm: Fix clasta/b and lasta/b simd instructions
..
arch-arm: Fix clasta/b and lasta/b simd instructions
The simd version of this instructions required zeroing the result
vector except for the first element, that contains the result.
Change-Id: I231ad3c44d89f34acae26d299ab676e2ed09acdc
---
M src/arch/arm/isa/insts/sve.isa
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index 612e3c7..2d4d60a 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -2434,7 +2434,16 @@
elif destType == DstRegType.SimdFpScalar:
code += ''' else {
AA64FpDest_x[0] = AA64FpDestMerge_x[0];
-}'''
+}
+'''
+if destType == DstRegType.SimdFpScalar:
+# This section will extend zeros to the simdFP scalar
+# intructions for lasta/b and Clasta/b
+code += '''
+for (int i = 1; i < eCount; ++i) {
+AA64FpDest_x[i] = (Element)0x0;
+}
+'''
iop = InstObjParams(name, 'Sve' + Name, 'SveSelectOp',
{'code': code, 'op_class': opClass,
'isCond': 'true' if isCond else 'false',
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I231ad3c44d89f34acae26d299ab676e2ed09acdc
Gerrit-Change-Number: 28247
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix Sve Fcmla indexed instruction
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28227 )
Change subject: arch-arm: Fix Sve Fcmla indexed instruction
..
arch-arm: Fix Sve Fcmla indexed instruction
Sve implementation of FCMLA indexed instruction was
incorrectly typed. This instruction is design to be used for
half-precision and single precision.
Change-Id: Ie529e21140ce5b26a8e72ac869a5422d32eba864
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28227
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/insts/sve.isa
2 files changed, 3 insertions(+), 3 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa
b/src/arch/arm/isa/formats/sve_2nd_level.isa
index b6f8340..53fd80d 100644
--- a/src/arch/arm/isa/formats/sve_2nd_level.isa
+++ b/src/arch/arm/isa/formats/sve_2nd_level.isa
@@ -2799,12 +2799,12 @@
case 2:
zm = (IntRegIndex) (uint8_t) bits(machInst, 18, 16);
imm = bits(machInst, 20, 19);
-return new SveFcmlai(machInst,
+return new SveFcmlai(machInst,
zda, zn, zm, rot, imm);
case 3:
zm = (IntRegIndex) (uint8_t) bits(machInst, 19, 16);
imm = bits(machInst, 20);
-return new SveFcmlai(machInst,
+return new SveFcmlai(machInst,
zda, zn, zm, rot, imm);
}
return new Unknown64(machInst);
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index deb12bc..06ff728 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -3558,7 +3558,7 @@
sveCmpInst('fcmuo', 'Fcmuo', 'SimdFloatCmpOp', fpTypes, fcmuoCode)
# FCMLA (indexed)
sveComplexMulAddInst('fcmla', 'Fcmlai', 'SimdFloatMultAccOp',
-fpTypes[1:], predType = PredType.NONE)
+fpTypes[:2], predType = PredType.NONE)
# FCMLA (vectors)
sveComplexMulAddInst('fcmla', 'Fcmlav', 'SimdFloatMultAccOp',
fpTypes, predType = PredType.MERGE)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie529e21140ce5b26a8e72ac869a5422d32eba864
Gerrit-Change-Number: 28227
Gerrit-PatchSet: 2
Gerrit-Owner: Jordi Vaquero
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jordi Vaquero
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: FCVTZS instruction returns sign extension
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28229 )
Change subject: arch-arm: FCVTZS instruction returns sign extension
..
arch-arm: FCVTZS instruction returns sign extension
This patch fix Fcvtzs instruction adding sign extension instead of
zero extension
Change-Id: I28cdca432fa6baa8a524de4c431f492f23f0e9a6
---
M src/arch/arm/isa/insts/sve.isa
1 file changed, 28 insertions(+), 6 deletions(-)
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index 612e3c7..01abe49 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -1518,27 +1518,48 @@
# Generates definitions for SVE floating-point conversions (always
# unary, constructive, merging
def sveCvtInst(name, Name, opClass, types, op, direction=CvtDir.Narrow,
- decoder='Generic'):
+ decoder='Generic', signed=False):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<%(bigElemType)s>(
xc->tcBase());
+''' % {'bigElemType': 'SElement' if direction == CvtDir.Narrow
+ else 'DElement'}
+if signed:
+code += '''
+SElement msk = mask(sizeof(DElement)*8);
+ '''
+assign_code = '''
+int sign_bit = bits(destElem, sizeof(DElement)*8 -1);
+AA64FpDest_x%(bigElemSuffix)s[i] =
+sign_bit? (destElem|~msk): destElem;
+ ''' % {
+ 'bigElemSuffix': 's' if direction == CvtDir.Narrow else 'd'
+ }
+else:
+assign_code = '''
+AA64FpDest_x%(bigElemSuffix)s[i] = destElem;
+''' % {
+ 'bigElemSuffix': 's' if direction == CvtDir.Narrow else 'd'
+ }
+
+code += '''
for (unsigned i = 0; i < eCount; i++) {
SElement srcElem1 = AA64FpOp1_x%(bigElemSuffix)s[i] &
mask(sizeof(SElement) * 8);
DElement destElem = 0;
if (GpOp_x%(bigElemSuffix)s[i]) {
%(op)s
-AA64FpDest_x%(bigElemSuffix)s[i] = destElem;
+%(assign)s;
} else {
AA64FpDest_x%(bigElemSuffix)s[i] =
AA64FpDestMerge_x%(bigElemSuffix)s[i];
}
}
''' % {'op': op,
- 'bigElemType': 'SElement' if direction == CvtDir.Narrow
- else 'DElement',
- 'bigElemSuffix': 's' if direction == CvtDir.Narrow else 'd'}
+ 'bigElemSuffix': 's' if direction == CvtDir.Narrow else 'd',
+ 'assign': assign_code
+ }
iop = InstObjParams(name, 'Sve' + Name, 'SveUnaryPredOp',
{'code': code, 'op_class': opClass}, [])
header_output += SveWideningUnaryPredOpDeclare.subst(iop)
@@ -2736,6 +2757,7 @@
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen(
xc->tcBase());
+
ArmISA::VecRegContainer tmpVecC;
auto auxDest = tmpVecC.as();
int firstelem = -1, lastelem = -2;
@@ -3589,7 +3611,7 @@
'uint32_t, uint32_t',
'uint64_t, uint32_t',
'uint64_t, uint64_t'),
- fcvtzsCode, CvtDir.Narrow)
+ fcvtzsCode, CvtDir.Narrow, signed=True)
sveCvtInst('fcvtzs', 'FcvtzsWiden', 'SimdCvtOp',
('uint16_t, uint32_t',
'uint16_t, uint64_t',
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28229
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I28cdca432fa6baa8a524de4c431f492f23f0e9a6
Gerrit-Change-Number: 28229
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix SVE indx inst by sizeof error and dest overwrite
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28228 )
Change subject: arch-arm: Fix SVE indx inst by sizeof error and dest
overwrite
..
arch-arm: Fix SVE indx inst by sizeof error and dest overwrite
This patch includes two fixes for SVE FMUL; FMLA FMLS AND FCMLA instructions
+ Fixes indexed functions like FMUL, FMLA, FMLS, FCMLA due to its
destination register overwrite with temporary values, wince the imm
can make changes in vector positions that will be read in the future.
+ sizeof return bytes not bits so division of 128 shouild be of 16 instead
Change-Id: I304d1b254a299069c85bbc3319e5a6d4119436d0
---
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/insts/sve.isa
2 files changed, 30 insertions(+), 12 deletions(-)
diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa
b/src/arch/arm/isa/formats/sve_2nd_level.isa
index b6f8340..53fd80d 100644
--- a/src/arch/arm/isa/formats/sve_2nd_level.isa
+++ b/src/arch/arm/isa/formats/sve_2nd_level.isa
@@ -2799,12 +2799,12 @@
case 2:
zm = (IntRegIndex) (uint8_t) bits(machInst, 18, 16);
imm = bits(machInst, 20, 19);
-return new SveFcmlai(machInst,
+return new SveFcmlai(machInst,
zda, zn, zm, rot, imm);
case 3:
zm = (IntRegIndex) (uint8_t) bits(machInst, 19, 16);
imm = bits(machInst, 20);
-return new SveFcmlai(machInst,
+return new SveFcmlai(machInst,
zda, zn, zm, rot, imm);
}
return new Unknown64(machInst);
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index b4c7fe5..870ecfd 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -1813,11 +1813,13 @@
xc->tcBase());
// Number of elements in a 128 bit segment
-constexpr unsigned ePerSegment = 128 / sizeof(Element);
+constexpr unsigned ePerSegment = 16 / sizeof(Element);
'''
code += '''
+ArmISA::VecRegContainer tmpC;
+auto auxDest = tmpC.as();
for (unsigned i = 0; i < eCount; i++) {
const auto segmentBase = i - i % ePerSegment;
const auto segmentIdx = segmentBase + index;
@@ -1830,9 +1832,12 @@
code += '''
%(op)s
-AA64FpDest_x[i] = destElem;
+auxDest[i] = destElem;
}
-''' % {'op': op}
+
+for (unsigned i = 0; i < eCount; i++) {
+AA64FpDest_x[i] = auxDest[i];
+}''' % {'op': op}
baseClass = 'SveBinIdxUnpredOp'
@@ -2045,8 +2050,10 @@
xc->tcBase());
// Number of elements in a 128 bit segment
-constexpr unsigned ePerSegment = 128 / sizeof(Element);
+constexpr unsigned ePerSegment = 16 / sizeof(Element);
+ArmISA::VecRegContainer tmpC;
+auto auxDest = tmpC.as();
for (unsigned i = 0; i < eCount; i++) {
const auto segmentBase = i - i % ePerSegment;
const auto segmentIdx = segmentBase + index;
@@ -2055,10 +2062,13 @@
const Element& srcElem2 = AA64FpOp2_x[segmentIdx];
Element destElem = AA64FpDestMerge_x[i];
'''
-
code += '''
%(op)s
-AA64FpDest_x[i] = destElem;
+auxDest[i] = destElem;
+}
+
+for (unsigned i = 0; i < eCount; i++) {
+AA64FpDest_x[i] = auxDest[i];
}''' % {'op': op}
iop = InstObjParams(name, 'Sve' + Name, 'SveBinIdxUnpredOp',
@@ -2992,6 +3002,9 @@
code += '''
uint32_t eltspersegment = 16 / (2 * sizeof(Element));'''
code += '''
+ArmISA::VecRegContainer tmpC;
+auto auxDest = tmpC.as();
+
for (int i = 0; i < eCount / 2; ++i) {'''
if predType == PredType.NONE:
code += '''
@@ -3035,9 +3048,14 @@
code += '''
}'''
code += '''
-AA64FpDest_x[2 * i] = addend_r;
-AA64FpDest_x[2 * i + 1] = addend_i;
-}'''
+auxDest[2 * i] = addend_r;
+auxDest[2 * i + 1] = addend_i;
+}
+
+for (unsigned i = 0; i < eCount; i++) {
+AA64FpDest_x[i] = auxDest[i];
+}
+'''
iop = InstObjParams(name, 'Sve' + Name,
'SveComplexIdxOp' if predType == PredType.NONE
else 'SveComplexOp',
@@ -3558,7 +3576,7 @@
sveCmpInst('fcmuo', 'Fcmuo', 'SimdFloatCmpOp', fpTypes, fcmuoCode)
# FCMLA (indexed)
sveComplexMulAddInst('fcmla', 'Fcmlai', 'SimdFloatMultAccOp',
-fpTypes[1:], predType = PredType.NONE)
+fpTypes[:2], predType = PredType.NONE)
# FCMLA (vectors)
sveComplexMulAddInst('fcmla',
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix Sve Fcmla indexed instruction
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28227 )
Change subject: arch-arm: Fix Sve Fcmla indexed instruction
..
arch-arm: Fix Sve Fcmla indexed instruction
Sve implementation of FCMLA indexed instruction was
incorrectly typed. This instruction is design to be used for
half-precision and single precision.
Change-Id: Ie529e21140ce5b26a8e72ac869a5422d32eba864
---
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/insts/sve.isa
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa
b/src/arch/arm/isa/formats/sve_2nd_level.isa
index b6f8340..53fd80d 100644
--- a/src/arch/arm/isa/formats/sve_2nd_level.isa
+++ b/src/arch/arm/isa/formats/sve_2nd_level.isa
@@ -2799,12 +2799,12 @@
case 2:
zm = (IntRegIndex) (uint8_t) bits(machInst, 18, 16);
imm = bits(machInst, 20, 19);
-return new SveFcmlai(machInst,
+return new SveFcmlai(machInst,
zda, zn, zm, rot, imm);
case 3:
zm = (IntRegIndex) (uint8_t) bits(machInst, 19, 16);
imm = bits(machInst, 20);
-return new SveFcmlai(machInst,
+return new SveFcmlai(machInst,
zda, zn, zm, rot, imm);
}
return new Unknown64(machInst);
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index b4c7fe5..19c3a0f 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -3558,7 +3558,7 @@
sveCmpInst('fcmuo', 'Fcmuo', 'SimdFloatCmpOp', fpTypes, fcmuoCode)
# FCMLA (indexed)
sveComplexMulAddInst('fcmla', 'Fcmlai', 'SimdFloatMultAccOp',
-fpTypes[1:], predType = PredType.NONE)
+fpTypes[:2], predType = PredType.NONE)
# FCMLA (vectors)
sveComplexMulAddInst('fcmla', 'Fcmlav', 'SimdFloatMultAccOp',
fpTypes, predType = PredType.MERGE)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28227
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie529e21140ce5b26a8e72ac869a5422d32eba864
Gerrit-Change-Number: 28227
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch: Fix VecReg container alignement to 128bits view
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27968 )
Change subject: arch: Fix VecReg container alignement to 128bits view
..
arch: Fix VecReg container alignement to 128bits view
This Patch will fix the alignment problem that appears sometimes
when we try to create a view of 128 bits over the VecRegContainer
object.
That container is initially created as std::array, so
there is no obligation to be aligned to 16 bytes. This patches forces
all containers to be aligned to 16 bytes.
The problem has been observed in the Jira Issue:
https://gem5.atlassian.net/browse/GEM5-320
Change-Id: Id9fdd427bd7a4dc904edd519f31cc29c5b29c5e6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27968
Reviewed-by: Jason Lowe-Power
Reviewed-by: Ciro Santilli
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/generic/vec_reg.hh
1 file changed, 2 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Ciro Santilli: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/arch/generic/vec_reg.hh b/src/arch/generic/vec_reg.hh
index 4156ac5..e26cf8b 100644
--- a/src/arch/generic/vec_reg.hh
+++ b/src/arch/generic/vec_reg.hh
@@ -279,7 +279,8 @@
static constexpr inline size_t size() { return SIZE; };
using Container = std::array;
private:
-Container container;
+// 16-byte aligned to support 128bit element view
+alignas(16) Container container;
using MyClass = VecRegContainer;
public:
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27968
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id9fdd427bd7a4dc904edd519f31cc29c5b29c5e6
Gerrit-Change-Number: 27968
Gerrit-PatchSet: 2
Gerrit-Owner: Jordi Vaquero
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jordi Vaquero
Gerrit-Reviewer: Victor Soria
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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