[m5-dev] Undelivered Mail Returned to Sender
This is the mail system at host daystrom.m5sim.org. I'm sorry to have to inform you that your message could not be delivered to one or more recipients. It's attached below. For further assistance, please send mail to postmaster. If you do so, please include this problem report. You can delete your own text from the attached returned message. The mail system dan...@ya.ru: host mx2.yandex.ru[93.158.134.89] said: 550 5.1.1 dan...@ya.ru user unknown (in reply to RCPT TO command) Reporting-MTA: dns; daystrom.m5sim.org X-Postfix-Queue-ID: 6D0CC158112 X-Postfix-Sender: rfc822; m5-dev@m5sim.org Arrival-Date: Wed, 4 Mar 2009 03:54:39 -0500 (EST) Final-Recipient: rfc822; Dan1oo@ya.ru Action: failed Status: 5.1.1 Remote-MTA: dns; mx2.yandex.ru Diagnostic-Code: smtp; 550 5.1.1 Dan1oo@ya.ru user unknown ---BeginMessage--- This address has been used to register a Flyspray account. If you were not expecting this message, please ignore and delete it. Go to the following URL to complete your registration: http://www.m5sim.org/flyspray/index.php?do=registermagic=8b285c8adef906b02283a62220824e66 Your confirmation code is: 7a1.DC0Yqj2Mg ---End Message--- ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] locked memory accesses
On Wed, Mar 4, 2009 at 7:03 AM, Steve Reinhardt ste...@gmail.com wrote: I think there are two possible solutions: 1. Add a retry response code for atomic requests (along the lines of the error codes we alrady have in packet.hh) and then make sure that all the places where we issue atomic requests can deal with them appropriately. Oddly enough it's reminiscent of the LL/SC solution, though this is different since it only applies in atomic mode. 2. Force any cpu or device that wants to do locked accesses in atomic mode to do both the lock and unlock accesses back-to-back within the same event (e.g., in the same call to tick()). Neither of these sound particularly attractive. I like #2 better [...] Another advantage of #2 is that atomic-mode atomicity comes for free without touching the memory system at all. This is nice since it gives you a baseline that will work on any memory system (e.g., Ruby). There's also some possibility that we could avoid implementing timing-mode locking in main memory with this approach, by making the reasonable restriction that if you want to run in timing mode then you have to use caches. That may not hold if we have to deal with locked uncached accesses... I know these exist in real life, but I'm hoping that that's one of the features we can avoid by only running modern 64-bit software. Gabe, do you know off hand if there are locked uncached accesses in any of the code you've run so far? Steve ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] [m5-users] Using the pin command to bin programs to cores
The m5 binary on the disk image that we distribute doesn't support the pin command. You'll need to compile it yourself. Additionally, I don't believe libc on the disk image supports sched_setaffinity (needed by pin). This is something we need to fix, but it unfortunately involves distributing a new disk image to everyone and updating a bunch of regressions. You can easily make a new disk image by starting with a gentoo image or you can copy the libc* and libstdc++* from one of the cross compilers on the m5sim.org website onto the disk image (you might need to make the actual image bigger to do this). Maybe we should just bite the bullet and do this. If we do, I think we should probably deprecate any stuff we don't like in the m5ops stuff. My inclination is to just generate a new disk image with gentoo 2008.0, recompile the binaries and move them over. Does anyone have a problem if we do this? Does anyone know if/when a 2009.0 is supposed to come out? Should we wait for it? I will probably be a many weeks before I could have time to do this, but it may at least be good to have a plan of attack so we can do the right thing when the time comes. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: use numCycles instead of simTicks to determine ...
changeset 2a2c2403ee5b in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=2a2c2403ee5b description: use numCycles instead of simTicks to determine CPI stat in InOrder diffstat: 1 file changed, 2 insertions(+), 2 deletions(-) src/cpu/inorder/cpu.cc |4 ++-- diffs (21 lines): diff -r de47df436ace -r 2a2c2403ee5b src/cpu/inorder/cpu.cc --- a/src/cpu/inorder/cpu.ccWed Mar 04 09:25:53 2009 -0500 +++ b/src/cpu/inorder/cpu.ccWed Mar 04 13:16:48 2009 -0500 @@ -355,7 +355,7 @@ .name(name() + .cpi_total) .desc(CPI: Total CPI of All Threads) .precision(6); -totalCpi = simTicks / totalCommittedInsts; +totalCpi = numCycles / totalCommittedInsts; ipc .name(name() + .ipc) @@ -373,7 +373,7 @@ .name(name() + .ipc_total) .desc(IPC: Total IPC of All Threads) .precision(6); -totalIpc = totalCommittedInsts / simTicks; +totalIpc = totalCommittedInsts / numCycles; BaseCPU::regStats(); } ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: Give TimeBuffer an ID that can be set. Necessar...
changeset 4842a7d78634 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4842a7d78634
description:
Give TimeBuffer an ID that can be set. Necessary because InOrder uses
generic stages so w/o an ID there is no way to differentiate buffers when
debugging
diffstat:
3 files changed, 19 insertions(+), 7 deletions(-)
src/base/timebuf.hh | 13 +
src/cpu/inorder/cpu.cc|4 +---
src/cpu/inorder/pipeline_stage.cc |9 +
diffs (79 lines):
diff -r 2a2c2403ee5b -r 4842a7d78634 src/base/timebuf.hh
--- a/src/base/timebuf.hh Wed Mar 04 13:16:48 2009 -0500
+++ b/src/base/timebuf.hh Wed Mar 04 13:16:49 2009 -0500
@@ -43,6 +43,7 @@
int past;
int future;
int size;
+int _id;
char *data;
std::vectorchar * index;
@@ -148,6 +149,8 @@
new (ptr) T;
ptr += sizeof(T);
}
+
+_id = -1;
}
TimeBuffer()
@@ -162,6 +165,16 @@
delete [] data;
}
+void id(int id)
+{
+_id = id;
+}
+
+int id()
+{
+return _id;
+}
+
void
advance()
{
diff -r 2a2c2403ee5b -r 4842a7d78634 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.ccWed Mar 04 13:16:48 2009 -0500
+++ b/src/cpu/inorder/cpu.ccWed Mar 04 13:16:49 2009 -0500
@@ -230,11 +230,9 @@
}
// Initialize TimeBuffer Stage Queues
-// For now just have these time buffers be pretty big.
-// @note: This could be statically allocated but changes
-// would have to be made to the standard time buffer class.
for (int stNum=0; stNum NumStages - 1; stNum++) {
stageQueue[stNum] = new StageQueue(NumStages, NumStages);
+stageQueue[stNum]-id(stNum);
}
diff -r 2a2c2403ee5b -r 4842a7d78634 src/cpu/inorder/pipeline_stage.cc
--- a/src/cpu/inorder/pipeline_stage.cc Wed Mar 04 13:16:48 2009 -0500
+++ b/src/cpu/inorder/pipeline_stage.cc Wed Mar 04 13:16:49 2009 -0500
@@ -556,8 +556,8 @@
if (prevStageValid) {
int insts_from_prev_stage = prevStage-size;
-DPRINTF(InOrderStage, %i insts available from previous stage.\n,
-insts_from_prev_stage);
+DPRINTF(InOrderStage, %i insts available from stage buffer %i.\n,
+insts_from_prev_stage, prevStageQueue-id());
for (int i = 0; i insts_from_prev_stage; ++i) {
@@ -985,8 +985,9 @@
tid, cpu-pipelineStage[next_stage]-stageBufferAvail());
DPRINTF(InOrderStage, [tid:%u]: [sn:%i]: being placed into
-index %i stage %i queue.\n,
-tid, inst-seqNum, toNextStageIndex, inst-nextStage);
+index %i of stage buffer %i queue.\n,
+tid, inst-seqNum, toNextStageIndex,
+cpu-pipelineStage[prev_stage]-nextStageQueue-id());
int next_stage_idx =
cpu-pipelineStage[prev_stage]-nextStage-size;
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: InOrder didnt have all it's params set to a def...
changeset b4e30b30f695 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b4e30b30f695
description:
InOrder didnt have all it's params set to a default value, which is now
required for M5 objects; Also, a # of values need to be reset to 0 (or the
appropriate value) before we assume they are OK for use.
diffstat:
5 files changed, 24 insertions(+), 31 deletions(-)
src/cpu/inorder/InOrderCPU.py |5 +---
src/cpu/inorder/comm.hh|8 +++
src/cpu/inorder/inorder_dyn_inst.cc|5 +++-
src/cpu/inorder/pipeline_stage.cc | 32
src/cpu/inorder/resources/mult_div_unit.cc |5
diffs (137 lines):
diff -r 4842a7d78634 -r b4e30b30f695 src/cpu/inorder/InOrderCPU.py
--- a/src/cpu/inorder/InOrderCPU.py Wed Mar 04 13:16:49 2009 -0500
+++ b/src/cpu/inorder/InOrderCPU.py Wed Mar 04 13:17:05 2009 -0500
@@ -34,9 +34,8 @@
class InOrderCPU(BaseCPU):
type = 'InOrderCPU'
activity = Param.Unsigned(0, Initial count)
-numThreads = Param.Unsigned(1, number of HW thread contexts)
-cachePorts = Param.Unsigned(Cache Ports)
+cachePorts = Param.Unsigned(2, Cache Ports)
stageWidth = Param.Unsigned(1, Stage width)
fetchMemPort = Param.String(icache_port , Name of Memory Port to get
instructions from)
@@ -66,7 +65,7 @@
functionTraceStart = Param.Tick(0, Cycle to start function trace)
stageTracing = Param.Bool(False, Enable tracing of each stage in CPU)
-memBlockSize = Param.Unsigned(Memory Block Size)
+memBlockSize = Param.Unsigned(64, Memory Block Size)
multLatency = Param.Unsigned(1, Latency for Multiply Operations)
multRepeatRate = Param.Unsigned(1, Repeat Rate for Multiply Operations)
diff -r 4842a7d78634 -r b4e30b30f695 src/cpu/inorder/comm.hh
--- a/src/cpu/inorder/comm.hh Wed Mar 04 13:16:49 2009 -0500
+++ b/src/cpu/inorder/comm.hh Wed Mar 04 13:17:05 2009 -0500
@@ -53,6 +53,14 @@
uint64_t nextPC;
InstSeqNum squashedSeqNum;
bool includeSquashInst;
+
+InterStageStruct()
+:size(0), squash(false),
+ branchMispredict(false), branchTaken(false),
+ mispredPC(0), nextPC(0),
+ squashedSeqNum(0), includeSquashInst(false)
+{ }
+
};
/** Turn This into a Class */
diff -r 4842a7d78634 -r b4e30b30f695 src/cpu/inorder/inorder_dyn_inst.cc
--- a/src/cpu/inorder/inorder_dyn_inst.cc Wed Mar 04 13:16:49 2009 -0500
+++ b/src/cpu/inorder/inorder_dyn_inst.cc Wed Mar 04 13:17:05 2009 -0500
@@ -84,7 +84,10 @@
InOrderDynInst::InOrderDynInst()
: traceData(NULL), cpu(cpu)
-{ initVars(); }
+{
+seqNum = 0;
+initVars();
+}
int InOrderDynInst::instcount = 0;
diff -r 4842a7d78634 -r b4e30b30f695 src/cpu/inorder/pipeline_stage.cc
--- a/src/cpu/inorder/pipeline_stage.cc Wed Mar 04 13:16:49 2009 -0500
+++ b/src/cpu/inorder/pipeline_stage.cc Wed Mar 04 13:17:05 2009 -0500
@@ -38,35 +38,10 @@
using namespace ThePipeline;
PipelineStage::PipelineStage(Params *params, unsigned stage_num)
-: numThreads(ThePipeline::MaxThreads)
{
-stageNum = stage_num;
-stageWidth = ThePipeline::StageWidth;
-
-_status = Inactive;
-
-prevStageValid = false;
-nextStageValid = false;
-
-// Init. structures
-for(int tid=0; tid numThreads; tid++) {
-stageStatus[tid] = Idle;
-
-for (int stNum = 0; stNum NumStages; stNum++) {
-stalls[tid].stage[stNum] = false;
-}
-stalls[tid].resources.clear();
-
-if (stageNum BackEndStartStage)
-lastStallingStage[tid] = BackEndStartStage - 1;
-else
-lastStallingStage[tid] = NumStages - 1;
-}
-
-stageBufferMax = ThePipeline::interStageBuffSize[stage_num];
+init(params, stage_num);
}
-
void
PipelineStage::init(Params *params, unsigned stage_num)
{
@@ -189,7 +164,7 @@
// Setup wire to write information to proper place in stage queue.
nextStage = nextStageQueue-getWire(0);
-
+nextStage-size = 0;
nextStageValid = true;
}
@@ -682,6 +657,9 @@
bool status_change = false;
+if (nextStageValid)
+nextStage-size = 0;
+
toNextStageIndex = 0;
sortInsts();
diff -r 4842a7d78634 -r b4e30b30f695 src/cpu/inorder/resources/mult_div_unit.cc
--- a/src/cpu/inorder/resources/mult_div_unit.ccWed Mar 04 13:16:49
2009 -0500
+++ b/src/cpu/inorder/resources/mult_div_unit.ccWed Mar 04 13:17:05
2009 -0500
@@ -57,6 +57,8 @@
div32RepeatRate = params-div32RepeatRate;
div32Latency = params-div32Latency;
+
+lastMDUCycle = 0;
}
void
@@ -150,6 +152,9 @@
rval);
if (rval != -1) {
+lastMDUCycle = curTick;
+lastOpType = inst-opClass();
+lastInstName = inst-staticInst-getName();
}
return rval;
___
m5-dev mailing list
m5-dev@m5sim.org
[m5-dev] changeset in m5: make handling of interstage buffers (i.e. Stage...
changeset a6d07755d34f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a6d07755d34f
description:
make handling of interstage buffers (i.e. StageQueues) more consistent:
(1)number from 0-n, not 1-n+1, (2) always check nextStageValid before a
stageNum+1 and prevStageValid for a stageNum-1 reference (3) add skidSize() to
get StageQueue size for all threads
diffstat:
4 files changed, 63 insertions(+), 35 deletions(-)
src/cpu/inorder/cpu.cc|4 -
src/cpu/inorder/first_stage.cc|2
src/cpu/inorder/pipeline_stage.cc | 87 +++--
src/cpu/inorder/pipeline_stage.hh |5 +-
diffs (228 lines):
diff -r b4e30b30f695 -r a6d07755d34f src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.ccWed Mar 04 13:17:05 2009 -0500
+++ b/src/cpu/inorder/cpu.ccWed Mar 04 13:17:07 2009 -0500
@@ -250,8 +250,8 @@
// Take Care of 1st/Nth stages
if (stNum 0)
pipelineStage[stNum]-setPrevStageQueue(stageQueue[stNum - 1]);
-if (stNum NumStages - 2)
-pipelineStage[stNum]-setNextStageQueue(stageQueue[stNum + 1]);
+if (stNum NumStages - 1)
+pipelineStage[stNum]-setNextStageQueue(stageQueue[stNum]);
}
// Initialize thread specific variables
diff -r b4e30b30f695 -r a6d07755d34f src/cpu/inorder/first_stage.cc
--- a/src/cpu/inorder/first_stage.ccWed Mar 04 13:17:05 2009 -0500
+++ b/src/cpu/inorder/first_stage.ccWed Mar 04 13:17:07 2009 -0500
@@ -127,7 +127,7 @@
{
bool all_reqs_completed = true;
-for (int insts_fetched = 0; insts_fetched stageWidth
canSendInstToNextStage(); insts_fetched++) {
+for (int insts_fetched = 0; insts_fetched stageWidth
canSendInstToStage(1); insts_fetched++) {
DynInstPtr inst;
bool new_inst = false;
diff -r b4e30b30f695 -r a6d07755d34f src/cpu/inorder/pipeline_stage.cc
--- a/src/cpu/inorder/pipeline_stage.cc Wed Mar 04 13:17:05 2009 -0500
+++ b/src/cpu/inorder/pipeline_stage.cc Wed Mar 04 13:17:07 2009 -0500
@@ -229,7 +229,7 @@
bool ret_val = false;
// Only check pipeline stall from stage directly following this stage
-if (stalls[tid].stage[stageNum + 1]) {
+if (nextStageValid stalls[tid].stage[stageNum + 1]) {
DPRINTF(InOrderStage,[tid:%i]: Stall fom Stage %i detected.\n,
tid, stageNum + 1);
ret_val = true;
@@ -422,26 +422,28 @@
}
int incoming_insts = (prevStageValid) ?
-cpu-pipelineStage[stageNum-1]-nextStage-size :
+cpu-pipelineStage[stageNum]-prevStage-size :
0;
-int avail = stageBufferMax - total - incoming_insts;
+int avail = stageBufferMax - total -0;// incoming_insts;
-assert(avail = 0);
+if (avail 0)
+fatal(stageNum %i:stageBufferAvail()
0...stBMax=%i,total=%i,incoming=%i=%i,
+ stageNum, stageBufferMax, total, incoming_insts, avail);
return avail;
}
bool
-PipelineStage::canSendInstToNextStage()
+PipelineStage::canSendInstToStage(unsigned stage_num)
{
bool buffer_avail = false;
-if (nextStageValid) {
-buffer_avail = (cpu-pipelineStage[stageNum+1]-stageBufferAvail() =
1);
+if (cpu-pipelineStage[stage_num]-prevStageValid) {
+buffer_avail = cpu-pipelineStage[stage_num]-stageBufferAvail() = 1;
}
-if (!buffer_avail nextStageValid) {
+if (!buffer_avail nextStageQueueValid(stage_num)) {
DPRINTF(InOrderStall, STALL: No room in stage %i buffer.\n, stageNum
+ 1);
}
@@ -468,6 +470,17 @@
}
+int
+PipelineStage::skidSize()
+{
+int total = 0;
+
+for (int i=0; i ThePipeline::MaxThreads; i++) {
+total += skidBuffer[i].size();
+}
+
+return total;
+}
bool
PipelineStage::skidsEmpty()
@@ -743,8 +756,11 @@
nextStage-size, stageNum + 1);
}
-DPRINTF(InOrderStage, %i insts left in stage buffer.\n, stageBufferMax -
stageBufferAvail());
+DPRINTF(InOrderStage, %i left in stage %i incoming buffer.\n, skidSize(),
+stageNum);
+DPRINTF(InOrderStage, %i available in stage %i incoming buffer.\n,
stageBufferAvail(),
+stageNum);
}
void
@@ -814,14 +830,10 @@
int insts_processed = 0;
-DPRINTF(InOrderStage, [tid:%u]: Sending instructions to stage %u.\n, tid,
-stageNum+1);
-
-//Keep processing instructions while ... these ?s are true:
-while (insts_available 0 //1. are there
instructions to process
- insts_processed stageWidth//2. can the
stage still process this
- (canSendInstToNextStage() || !nextStageValid) //3. is there
room in next stage
- last_req_completed) { //4. was the last
instruction completed
+while (insts_available 0
+ insts_processed stageWidth
+ (!nextStageValid || canSendInstToStage(stageNum+1))
+ last_req_completed) {
[m5-dev] changeset in m5: Remove unused functions/comments cluttering up ...
changeset a87880065b42 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a87880065b42
description:
Remove unused functions/comments cluttering up the code.
diffstat:
13 files changed, 14 insertions(+), 159 deletions(-)
src/cpu/inorder/SConscript |2 -
src/cpu/inorder/cpu.cc | 45 +--
src/cpu/inorder/cpu.hh | 25 +
src/cpu/inorder/inorder_cpu_builder.cc |1
src/cpu/inorder/inorder_dyn_inst.cc | 59 +--
src/cpu/inorder/inorder_dyn_inst.hh |4 --
src/cpu/inorder/params.hh |2 -
src/cpu/inorder/pipeline_stage.cc | 13 +-
src/cpu/inorder/pipeline_stage.hh |3 -
src/cpu/inorder/pipeline_traits.hh |7 ---
src/cpu/inorder/resource.hh |3 -
src/cpu/inorder/resources/cache_unit.cc |6 +--
src/cpu/inorder/thread_context.hh |3 -
diffs (truncated from 454 to 300 lines):
diff -r a6d07755d34f -r a87880065b42 src/cpu/inorder/SConscript
--- a/src/cpu/inorder/SConscriptWed Mar 04 13:17:07 2009 -0500
+++ b/src/cpu/inorder/SConscriptWed Mar 04 13:17:08 2009 -0500
@@ -47,7 +47,7 @@
TraceFlag('RefCount')
CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall',
'InOrderCPU',
- 'InOrderMDU', 'RegDepMap', 'Resource'])
+ 'InOrderMDU', 'InOrderCachePort', 'RegDepMap', 'Resource'])
Source('pipeline_traits.cc')
Source('inorder_dyn_inst.cc')
diff -r a6d07755d34f -r a87880065b42 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.ccWed Mar 04 13:17:07 2009 -0500
+++ b/src/cpu/inorder/cpu.ccWed Mar 04 13:17:08 2009 -0500
@@ -46,7 +46,6 @@
#include cpu/inorder/resource_pool.hh
#include mem/translating_port.hh
#include sim/process.hh
-//#include sim/root.hh
#include sim/stat_control.hh
#include algorithm
@@ -162,7 +161,6 @@
cpu_params = params;
resPool = new ResourcePool(this, params);
-//resPool-init();
coreType = default; // eventually get this from params
@@ -191,13 +189,9 @@
}
-/* Use this port to for syscall emulation writes to memory. */
-//Port *mem_port = NULL;
-//TranslatingPort *trans_port = NULL;
-
for (int i = 0; i numThreads; ++i) {
if (i params-workload.size()) {
-DPRINTF(InOrderCPU, Workload[%i] process is %#x,
+DPRINTF(InOrderCPU, Workload[%i] process is %#x\n,
i, this-thread[i]);
this-thread[i] = new Thread(this, i, params-workload[i],
i);
@@ -208,11 +202,8 @@
} else {
//Allocate Empty thread so M5 can use later
//when scheduling threads to CPU
-Process* dummy_proc = params-workload[0];
//LiveProcess::createDummy();
+Process* dummy_proc = params-workload[0];
this-thread[i] = new Thread(this, i, dummy_proc, i);
-
-// Set Up Syscall Emulation Port
-//this-thread[i]-setMemPort(trans_port);
}
// Setup the TC that will serve as the interface to the threads/CPU.
@@ -790,8 +781,6 @@
{
DPRINTF(InOrderCPU,[tid:%i]: Deallocating ..., tid);
-//removeThread(tid);
-
removeFromCurrentThreads(tid);
deactivateThread(tid);
@@ -840,19 +829,6 @@
}
-void
-InOrderCPU::signalSwitched()
-{
-panic(Unimplemented Function\n.);
-}
-
-
-void
-InOrderCPU::takeOverFrom(BaseCPU *oldCPU)
-{
-panic(Take Over From Another CPU\n.);
-}
-
uint64_t
InOrderCPU::readPC(unsigned tid)
{
@@ -1205,14 +1181,6 @@
}
}
-/*
-
-void
-InOrderCPU::removeAllInsts()
-{
-instList.clear();
-}
-*/
void
InOrderCPU::dumpInsts()
@@ -1233,14 +1201,6 @@
++num;
}
}
-/*
-
-void
-InOrderCPU::wakeDependents(DynInstPtr inst)
-{
-iew.wakeDependents(inst);
-}
-*/
void
InOrderCPU::wakeCPU()
@@ -1252,6 +1212,7 @@
DPRINTF(Activity, Waking up CPU\n);
+//@todo: figure out how to count idleCycles correctly
//idleCycles += (curTick - 1) - lastRunningCycle;
mainEventQueue.schedule(tickEvent, curTick);
diff -r a6d07755d34f -r a87880065b42 src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hhWed Mar 04 13:17:07 2009 -0500
+++ b/src/cpu/inorder/cpu.hhWed Mar 04 13:17:08 2009 -0500
@@ -249,9 +249,6 @@
TheISA::IntReg nextNPC[ThePipeline::MaxThreads];
/** The Register File for the CPU */
-/** @TODO: This regFile wont be a sufficient solution for out-of-order,
add register
- * files as a resource in order to handle ths problem
- */
TheISA::IntRegFile intRegFile[ThePipeline::MaxThreads];;
TheISA::FloatRegFile floatRegFile[ThePipeline::MaxThreads];;
TheISA::MiscRegFile miscRegFile;
@@ -362,15 +359,6 @@
void switchToActive(int stage_idx)
{ /*pipelineStage[stage_idx]-switchToActive();*/ }
-/** Switches out this CPU. (Unused currently) */
-
[m5-dev] changeset in m5: Give each resource in InOrder it's own TraceFla...
changeset 38e32429b739 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=38e32429b739
description:
Give each resource in InOrder it's own TraceFlag instead of just
standard 'Resource' flag
diffstat:
11 files changed, 87 insertions(+), 77 deletions(-)
src/cpu/inorder/SConscript| 17 --
src/cpu/inorder/resources/agen_unit.cc|8 ++--
src/cpu/inorder/resources/branch_predictor.cc | 10 ++---
src/cpu/inorder/resources/branch_predictor.hh |1
src/cpu/inorder/resources/decode_unit.cc |4 +-
src/cpu/inorder/resources/execution_unit.cc | 16 -
src/cpu/inorder/resources/fetch_seq_unit.cc | 28
src/cpu/inorder/resources/graduation_unit.cc |6 +--
src/cpu/inorder/resources/inst_buffer.cc | 20 +--
src/cpu/inorder/resources/tlb_unit.cc | 12 +++
src/cpu/inorder/resources/use_def.cc | 42 -
diffs (truncated from 670 to 300 lines):
diff -r a87880065b42 -r 38e32429b739 src/cpu/inorder/SConscript
--- a/src/cpu/inorder/SConscriptWed Mar 04 13:17:08 2009 -0500
+++ b/src/cpu/inorder/SConscriptWed Mar 04 13:17:09 2009 -0500
@@ -36,18 +36,29 @@
TraceFlag('ResReqCount')
TraceFlag('FreeList')
- TraceFlag('InOrderCachePort')
TraceFlag('InOrderStage')
TraceFlag('InOrderStall')
TraceFlag('InOrderCPU')
- TraceFlag('InOrderMDU')
TraceFlag('RegDepMap')
TraceFlag('InOrderDynInst')
TraceFlag('Resource')
+ TraceFlag('InOrderAGEN')
+ TraceFlag('InOrderFetchSeq')
+ TraceFlag('InOrderTLB')
+ TraceFlag('InOrderCachePort')
+ TraceFlag('InOrderBPred')
+ TraceFlag('InOrderDecode')
+ TraceFlag('InOrderExecute')
+ TraceFlag('InOrderInstBuffer')
+ TraceFlag('InOrderUseDef')
+ TraceFlag('InOrderMDU')
+ TraceFlag('InOrderGraduation')
TraceFlag('RefCount')
CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall',
'InOrderCPU',
- 'InOrderMDU', 'InOrderCachePort', 'RegDepMap', 'Resource'])
+ 'InOrderMDU', 'InOrderAGEN', 'InOrderFetchSeq', 'InOrderTLB',
'InOrderBPred',
+ 'InOrderDecode', 'InOrderExecute', 'InOrderInstBuffer',
'InOrderUseDef',
+ 'InOrderGraduation', 'InOrderCachePort', 'RegDepMap',
'Resource'])
Source('pipeline_traits.cc')
Source('inorder_dyn_inst.cc')
diff -r a87880065b42 -r 38e32429b739 src/cpu/inorder/resources/agen_unit.cc
--- a/src/cpu/inorder/resources/agen_unit.ccWed Mar 04 13:17:08 2009 -0500
+++ b/src/cpu/inorder/resources/agen_unit.ccWed Mar 04 13:17:09 2009 -0500
@@ -54,7 +54,7 @@
{
// Load/Store Instruction
if (inst-isMemRef()) {
-DPRINTF(Resource, [tid:%i] Generating Address for [sn:%i]
(%s).\n,
+DPRINTF(InOrderAGEN, [tid:%i] Generating Address for [sn:%i]
(%s).\n,
tid, inst-seqNum, inst-staticInst-getName());
@@ -67,13 +67,13 @@
inst-setMemAddr(inst-getEA());
//inst-setExecuted();
-DPRINTF(Resource, [tid:%i] [sn:%i] Effective address
calculated to be:
+DPRINTF(InOrderAGEN, [tid:%i] [sn:%i] Effective
address calculated to be:
%#x.\n, tid, inst-seqNum, inst-getEA());
} else if (inst-isStore()) {
fault = inst-calcEA();
inst-setMemAddr(inst-getEA());
-DPRINTF(Resource, [tid:%i] [sn:%i] Effective address
calculated to be:
+DPRINTF(InOrderAGEN, [tid:%i] [sn:%i] Effective
address calculated to be:
%#x.\n, tid, inst-seqNum, inst-getEA());
} else {
panic(Unexpected memory type!\n);
@@ -86,7 +86,7 @@
}
}
} else {
-DPRINTF(Resource, [tid:] Ignoring non-memory instruction
[sn:%i].\n, tid, seq_num);
+DPRINTF(InOrderAGEN, [tid:] Ignoring non-memory instruction
[sn:%i].\n, tid, seq_num);
agen_req-done();
}
}
diff -r a87880065b42 -r 38e32429b739
src/cpu/inorder/resources/branch_predictor.cc
--- a/src/cpu/inorder/resources/branch_predictor.cc Wed Mar 04 13:17:08
2009 -0500
+++ b/src/cpu/inorder/resources/branch_predictor.cc Wed Mar 04 13:17:09
2009 -0500
@@ -90,7 +90,7 @@
predictedTaken++;
} else {
-DPRINTF(Resource, [tid:%i]: [sn:%i]: Branch predicted
false.\n,
+DPRINTF(InOrderBPred, [tid:%i]: [sn:%i]: Branch predicted
false.\n,
tid, seq_num);
if (inst-isCondDelaySlot())
@@ -105,11 +105,11 @@
Re: [m5-dev] changeset in m5: InOrder didnt have all it's params set to a def...
InOrderDynInst::InOrderDynInst()
: traceData(NULL), cpu(cpu)
-{ initVars(); }
+{
+seqNum = 0;
+initVars();
+}
Sorry guys, I'm aware of this... Constructor initialization will be updated
in next changeset. I want to go through all the InOrderCPU structures and
clean up any initialization issues...
--
--
Korey L Sewell
Graduate Student - PhD Candidate
Computer Science Engineering
University of Michigan
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Undelivered Mail Returned to Sender
This is the mail system at host daystrom.m5sim.org. I'm sorry to have to inform you that your message could not be delivered to one or more recipients. It's attached below. For further assistance, please send mail to postmaster. If you do so, please include this problem report. You can delete your own text from the attached returned message. The mail system rewa...@narod.ru: host mx2.yandex.ru[93.158.134.89] said: 550 5.1.1 rewa...@narod.ru user unknown (in reply to RCPT TO command) Reporting-MTA: dns; daystrom.m5sim.org X-Postfix-Queue-ID: 7E461158202 X-Postfix-Sender: rfc822; m5-dev@m5sim.org Arrival-Date: Wed, 4 Mar 2009 15:34:07 -0500 (EST) Final-Recipient: rfc822; Rewalk4@narod.ru Action: failed Status: 5.1.1 Remote-MTA: dns; mx2.yandex.ru Diagnostic-Code: smtp; 550 5.1.1 Rewalk4@narod.ru user unknown ---BeginMessage--- This address has been used to register a Flyspray account. If you were not expecting this message, please ignore and delete it. Go to the following URL to complete your registration: http://www.m5sim.org/flyspray/index.php?do=registermagic=435d2e56188e3530bedc89c16c90bd27 Your confirmation code is: 7aM8Cf2PrKH/U ---End Message--- ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset in m5: Give TimeBuffer an ID that can be set. Necessar...
+ int id()
+ {
+ return _id;
+ }
+
This one should be declared const. int id() const ...
Please try to use const properly.
Nate
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: InOrderCPU: Clean up Constructors to initialize...
changeset 4ed2100efa84 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4ed2100efa84
description:
InOrderCPU: Clean up Constructors to initialize variables correctly
(i.e. in a way for the compiler to play *nice*)
diffstat:
11 files changed, 33 insertions(+), 66 deletions(-)
src/cpu/inorder/cpu.cc |6 +
src/cpu/inorder/first_stage.cc |7 +-
src/cpu/inorder/inorder_dyn_inst.cc |6 +
src/cpu/inorder/pipeline_stage.cc| 21 +---
src/cpu/inorder/pipeline_stage.hh|2 -
src/cpu/inorder/resources/cache_unit.cc |7 --
src/cpu/inorder/resources/fetch_seq_unit.cc |5 +---
src/cpu/inorder/resources/graduation_unit.cc |7 ++
src/cpu/inorder/resources/mult_div_unit.cc | 27 +++---
src/cpu/inorder/resources/mult_div_unit.hh | 10 -
src/cpu/inorder/thread_context.hh|1
diffs (255 lines):
diff -r 38e32429b739 -r 4ed2100efa84 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.ccWed Mar 04 13:17:09 2009 -0500
+++ b/src/cpu/inorder/cpu.ccWed Mar 04 22:37:45 2009 -0500
@@ -147,6 +147,8 @@
InOrderCPU::InOrderCPU(Params *params)
: BaseCPU(params),
cpu_id(params-cpu_id),
+ coreType(default),
+ _status(Idle),
tickEvent(this),
miscRegFile(this),
timeBuffer(2 , 2),
@@ -162,10 +164,6 @@
resPool = new ResourcePool(this, params);
-coreType = default; // eventually get this from params
-
-_status = Idle;
-
// Resize for Multithreading CPUs
thread.resize(numThreads);
diff -r 38e32429b739 -r 4ed2100efa84 src/cpu/inorder/first_stage.cc
--- a/src/cpu/inorder/first_stage.ccWed Mar 04 13:17:09 2009 -0500
+++ b/src/cpu/inorder/first_stage.ccWed Mar 04 22:37:45 2009 -0500
@@ -40,15 +40,12 @@
using namespace ThePipeline;
FirstStage::FirstStage(Params *params, unsigned stage_num)
-: PipelineStage(params, stage_num)
+: PipelineStage(params, stage_num), numFetchingThreads(1),
+ fetchPolicy(FirstStage::RoundRobin)
{
for(int tid=0; tid this-numThreads; tid++) {
stageStatus[tid] = Running;
}
-
-numFetchingThreads = 1;
-
-fetchPolicy = RoundRobin;
}
void
diff -r 38e32429b739 -r 4ed2100efa84 src/cpu/inorder/inorder_dyn_inst.cc
--- a/src/cpu/inorder/inorder_dyn_inst.cc Wed Mar 04 13:17:09 2009 -0500
+++ b/src/cpu/inorder/inorder_dyn_inst.cc Wed Mar 04 22:37:45 2009 -0500
@@ -76,16 +76,14 @@
}
InOrderDynInst::InOrderDynInst(StaticInstPtr _staticInst)
-: staticInst(_staticInst), traceData(NULL)
+: seqNum(0), staticInst(_staticInst), traceData(NULL)
{
-seqNum = 0;
initVars();
}
InOrderDynInst::InOrderDynInst()
-: traceData(NULL), cpu(cpu)
+: seqNum(0), traceData(NULL), cpu(cpu)
{
-seqNum = 0;
initVars();
}
diff -r 38e32429b739 -r 4ed2100efa84 src/cpu/inorder/pipeline_stage.cc
--- a/src/cpu/inorder/pipeline_stage.cc Wed Mar 04 13:17:09 2009 -0500
+++ b/src/cpu/inorder/pipeline_stage.cc Wed Mar 04 22:37:45 2009 -0500
@@ -38,24 +38,17 @@
using namespace ThePipeline;
PipelineStage::PipelineStage(Params *params, unsigned stage_num)
+: stageNum(stage_num), stageWidth(ThePipeline::StageWidth),
+ numThreads(ThePipeline::MaxThreads), _status(Inactive),
+ stageBufferMax(ThePipeline::interStageBuffSize[stage_num]),
+ prevStageValid(false), nextStageValid(false)
{
-init(params, stage_num);
+init(params);
}
void
-PipelineStage::init(Params *params, unsigned stage_num)
+PipelineStage::init(Params *params)
{
-stageNum = stage_num;
-stageWidth = ThePipeline::StageWidth;
-
-_status = Inactive;
-
-numThreads = ThePipeline::MaxThreads;
-
-prevStageValid = false;
-nextStageValid = false;
-
-// Init. structures
for(int tid=0; tid numThreads; tid++) {
stageStatus[tid] = Idle;
@@ -69,8 +62,6 @@
else
lastStallingStage[tid] = NumStages - 1;
}
-
-stageBufferMax = ThePipeline::interStageBuffSize[stage_num];
}
diff -r 38e32429b739 -r 4ed2100efa84 src/cpu/inorder/pipeline_stage.hh
--- a/src/cpu/inorder/pipeline_stage.hh Wed Mar 04 13:17:09 2009 -0500
+++ b/src/cpu/inorder/pipeline_stage.hh Wed Mar 04 22:37:45 2009 -0500
@@ -97,7 +97,7 @@
virtual ~PipelineStage() { }
/** PipelineStage initialization. */
-void init(Params *params, unsigned stage_num);
+void init(Params *params);
/** Returns the name of stage. */
std::string name() const;
diff -r 38e32429b739 -r 4ed2100efa84 src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc Wed Mar 04 13:17:09 2009 -0500
+++ b/src/cpu/inorder/resources/cache_unit.cc Wed Mar 04 22:37:45 2009 -0500
@@ -81,14 +81,9 @@
CacheUnit::CacheUnit(string res_name, int res_id, int res_width,
int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
:
