[gem5-users] Alpha ROB, IQ, LSQ overflow, or something related to cpu->instcount <= 1500' failed

[Chao Chen]

Hi,

I am using the up-to-date gem5 version (repo.gem5.org/gem5). and run
the ALPHA arch with FS mode.
The system have many stalls due to lack of free ROB, IQ or LSQ,
although the simulation still procedes slowly.
I increase the ROB and IQ to 4048 entries each, but the stalls didn't
disappear. I increase the Load Queue to 4048 (I know it may be not
reasonable), but I cannot increase Store Queue to more than 128
entries, the simulation would halt.

I tried to debug with gem5.debug.
The simulation is aborted for "void BaseDynInst<
 >::initVars() [with Impl = O3CPUImpl]:
Assertion `cpu->instcount <= 1500' failed."
This was ignored when using gem5.fast earlier.

I see the other posts that it means the in flight instructions
increases beyond a reasonable limit

I have some questions I cannot understand.
1.  Is it reasonable that the in flight instructions increases while I
use large ROB and IQ size? I was expecting in-flight instructions
didn't increase and the stalled caused by lack of buffer would
disappear.
2. I tried to debug it myself, and find that some instructions are not
destroyed after committing. It seems they are never destroyed, and
kept somewhere in some queue (I don't know which queue).
For most (regular) instructions, when
"instList.erase(removeList.front())" is called in o3/cpu.cc, the
instruction would be destroyed.
For some instructions, they are not destroyed properly after
calling instList.erase. I debug to find the reason is the reference
counter of the instruction object does not reach zero, and the system
would destroy the instruction object while nobody is still referencing
(using) this instruction. According to my understanding, there must be
somewhere in the pipeline that didn't decrease the reference
correctly, or some special operations (like squash) didn't call
functions to remove the reference.
3. I am not sure how this would cause the ROB and IQ to overflow (no
matter how big I set the values of these buffers).

Is there anyone see this kind of issues before? Is it really a bug or
did I do something wrong? If it is a bug, can you give me some hint to
detect which part may not have decrement the reference counter of the
instruction object? Any suspect?

Thanks,
Chao
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[gem5-users] cannot add debug message to mshr_queue.cc

[ignacio charalabidis]

Hello,

I am trying to place that code inside mem/cache/mshr_queue.cc

  if (!freeList.empty()){
DPRINTF(Cache,"!freeList.empty() returns True\n");
} else {
DPRINTF(Cache,"!freeList.empty() returns False\n");
}

and I have included:

#include "debug/Cache.hh"

but gem5 cannot compile and I get this error:

build/ARM/mem/cache/mshr_queue.cc: In member function 'MSHR* 
MSHRQueue::allocate(Addr, int, Packet*&, Tick, Counter)':
build/ARM/mem/cache/mshr_queue.cc:171:17: error: 'Cache' was not declared in 
this scope
build/ARM/mem/cache/mshr_queue.cc:171:17: note: suggested alternative:
build/ARM/debug/Cache.hh:12:19: note:   'Debug::Cache'
build/ARM/mem/cache/mshr_queue.cc:171:57: error: 'DPRINTF' was not declared in 
this scope
build/ARM/mem/cache/mshr_queue.cc:173:17: error: 'Cache' was not declared in 
this scope
build/ARM/mem/cache/mshr_queue.cc:173:17: note: suggested alternative:
build/ARM/debug/Cache.hh:12:19: note:   'Debug::Cache'
build/ARM/mem/cache/mshr_queue.cc:173:58: error: 'DPRINTF' was not declared in 
this scope


In all other files I could add debug messages with the same way but not in 
here. Why is that?

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Re: [gem5-users] Question about SimpleMemory latency

[Amin Farmahini]

A latency of 3 means 3 ps, or 30 ns.

To change it, you may edit src/mem/SimpleMemory.py or may define a new
command option using the configs/common/Options.py file.

Thanks,
Amin



On Tue, May 7, 2013 at 12:21 PM, David Gloe  wrote:

> Hello,
>
> For a default memory configuration using SimpleMemory in SE mode,
> config.ini is showing a latency of 3. Is this latency in cycles (same
> question for cache latency values)? In addition, a professor has told me
> that typical DRAM latency is more like 300 cycles; can someone explain the
> factor of 100 difference?
>
> Finally, what's the easiest way to change the memory latency for our
> simulation?
>
> [system.physmem]
> type=SimpleMemory
> bandwidth=73.00
> clock=1000
> conf_table_reported=false
> in_addr_map=true
> latency=3
> latency_var=0
> null=false
> range=0:536870911
> zero=false
> port=system.membus.master[0]
>
> Thanks,
> David G.
>
> --
> David Gloe
> Masters Student, Computer Science
> University of Minnesota
>
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[gem5-users] Question about SimpleMemory latency

[David Gloe]

Hello,

For a default memory configuration using SimpleMemory in SE mode, 
config.ini is showing a latency of 3. Is this latency in cycles 
(same question for cache latency values)? In addition, a professor has 
told me that typical DRAM latency is more like 300 cycles; can someone 
explain the factor of 100 difference?


Finally, what's the easiest way to change the memory latency for our 
simulation?


[system.physmem]
type=SimpleMemory
bandwidth=73.00
clock=1000
conf_table_reported=false
in_addr_map=true
latency=3
latency_var=0
null=false
range=0:536870911
zero=false
port=system.membus.master[0]

Thanks,
David G.

--
David Gloe
Masters Student, Computer Science
University of Minnesota

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Re: [gem5-users] GHB prefetcher

[Xiangyang Guo]

Hi, Mahmood, Thanks for your information.


Xiangyang
On May 7, 2013 2:08 AM, "Mahmood Naderan"  wrote:

> This may be useful
> http://www.mail-archive.com/gem5-users@gem5.org/msg02490.html
>
> On 5/7/13, Xiangyang Guo  wrote:
> > Hi, gem5-user,
> >
> > I take a look at the GHB prefetcher provided by Gem5 , I'm wondering if
> > this part is finished or not? It seems that the code is like a stride
> based
> > GHB prefetcher, but I'm not sure because there is no a obvious index
> table
> > and buffer. So could anyone give me any hints?  Thanks in advance.
> >
> > Regards
> >
> > Xiangyang
> >
>
>
> --
> Regards,
> Mahmood
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Re: [gem5-users] Error when installing the full system image

[Amol]

Thank you for the valuable help
but i did not get it I read it but 

if it possible then can you provide any link for that

Thank you in advance



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