Re: [gem5-users] How to run PARSEC within GEM5 in FS mode?
Hi M.Y. You must change the disk image size with /gem5/util/gem5img.py as you want. I hope that help you. Best --- Babak Aghaei Ph.D candidate From: Matheus Alcântara Souza via gem5-users gem5-users@gem5.org To: n26001482 n26001...@mail.ncku.edu.tw; gem5 users mailing list gem5-users@gem5.org Sent: Wednesday, October 1, 2014 4:05 AM Subject: Re: [gem5-users] How to run PARSEC within GEM5 in FS mode? Hello, If you want to run PARSEC 3.0, you need to crosscompile it for the ISA you want, on your host (GCC crosscompilers are available at gem5 wiki, on Download section). After that, copy the binaries and inputs to the image. If PARSEC 2.1 is enough, you should take a look at http://www.cs.utexas.edu/~cart/parsec_m5/. 2014-09-30 21:31 GMT-03:00 n26001482 via gem5-users gem5-users@gem5.org: Hi, all. Referring to the website http://parsec.cs.princeton.edu/parsec3-doc.htm#start I've downloaded PARSEC 3.0 on my real machine, X86. Except one of them doesn't work the other work fine. Now I want to run them within GEM5 in FS mode, but the files included in the PARSEC suite seem too large so that I cannot put it in the GEM5 image using the commands below: $sudo mount -o loop,offset=32256 disks/arm.img tempdir $sudo umount tempdir I found the file system space is about 2.5GB. But all the files included in the PARSEC are 7GB. How to put the whole files in the suite? Was the way I walked wrong? Is there some specific-version PARSEC suite for simulators like GEM5 smaller than normal-version suite? I appreciate if anyone could give me some hints. BEST M.Y. ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Best regards, Matheus Alcântara Souza MSc candidate in Informatics at PUC Minas ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] I need help for running configuration script
Hi Naveed, Are you using the latest gem5 trunk? I was the one who changed Bus to XBar, so there was not much finding out to do. Good point though, I should update the Wiki. Andreas On 01/10/2014 06:05, Naveed Ul Mustafa naveed.must...@bilkent.edu.tr wrote: Hi Anderson, Thanks for the reply, however I still face the problem. Following is the new script. -- #import m5 #from m5.objects import * import m5 from m5.objects import * MyCache=BaseCache(assoc=2, mshrs = 10, tgts_per_mshr=5, hit_latency=1, response_latency=2) MyL1Cache=MyCache(is_top_level= True) mycpu = TimingSimpleCPU(cpu_id=0) mycpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), MyL1Cache(size = '256kB'), MyCache(size = '2MB', hit_latency=2, response_latency=4)#Level2 Cache ) mysystem = System( cpu=mycpu, cache_line_size = '64', physmem = SimpleMemory(), membus = CoherentXBar() ) # Create a source clock for the system and set the clock period mysystem.clk_domain = SrcClockDomain(clock='1GHz') root = Root(full_system=False,system = mysystem) root.system.cpu.workload=LiveProcess(cmd= 'hello', executable ='/home/naveed/Desktop/gem5/tests/test-progs/hello/bin/arm/linux') # instantiate configuration m5.instantiate() #exit_event = m5.simulate() print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() - and I get the following error gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. gem5 compiled Aug 28 2014 12:59:22 gem5 started Oct 1 2014 08:00:23 gem5 executing on naveed-desktop command line: build/ARM/gem5.opt configs/MyScripts/mySystem.py Traceback (most recent call last): File string, line 1, in module File /home/naveed/Desktop/gem5/src/python/m5/main.py, line 388, in main exec filecode in scope File configs/MyScripts/mySystem.py, line 26, in module membus = CoherentXBar() NameError: name 'CoherentXBar' is not defined Can you please let me know why I am having this error? By the way, how you figure out that they replaced the Bus() with CoherentXBar()? I mean, is there any reference guide for this purpose? Thanks in advance Hi Naveed, The Bus is renamed Xbar, and you need to specify either a coherent or non coherent one. In your case: membus = CoherentXBar() ...should do the trick. Concerning the power and clock domains, I suggest having a look at configs/examples/se.py and fs.py to see how it is done. If you do not want to use the DVFS functionality you can create a single system power and clock domain. Andreas On 30/09/2014 16:54, Naveed Ul Mustafa via gem5-users gem5-users@gem5.org wrote: Hi All, I am a new user of gem5. I am following the slides available on following link. I am running following configuration script. Lines whic prodcue error are marked by comments import m5 from m5.objects import * MyCache=BaseCache(assoc=2, mshrs = 10, tgts_per_mshr=5, hit_latency=1, response_latency=2) MyL1Cache=MyCache(is_top_level= True) mycpu = TimingSimpleCPU(cpu_id=0) mycpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), MyL1Cache(size = '256kB'), MyCache(size = '2MB', hit_latency=2, response_latency=4) ) mysystem = System(cpu=mycpu, cache_line_size = '64', physmem = SimpleMemory(), membus = Bus()# İt says in error that System has no attribute membus ) # create the interrupt controller mycpu.createInterruptController() mycpu.connectAllPorts(system.membus)# Again same error message that is System has no attribute membus mycpu.clock= '2GHz'#Error message: TimingSimple CPU has no attribute clock root = Root(full_system=False,system = mysystem) root.system.cpu.workload=LiveProcess(cmd= 'hello', executable ='/home/naveed/Desktop/gem5/tests/test-progs/hello/bin/arm/linux') # instantiate configuration m5.instantiate(root)#Error in unproxying param 'clk_domain' of system exit_event = m5.simulate() print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() -Wil l be thankful for any help Naveed Ul Mustafa ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered
[gem5-users] ThreadContext / takeOverFrom() function
Hello, My aim is to copy the context of a thread to another thread which runs on different cpu. According to the definition of takeOverFrom() in gem5/src/cpu/thread_context.cc, we can copy thread contexts: /** * Copy state between thread contexts in preparation for CPU handover. * * @note This method modifies the old thread contexts as well as the * new thread context. The old thread context will have its quiesce * event descheduled if it is scheduled and its status set to halted. * * @param new_tc Destination ThreadContext. * @param old_tc Source ThreadContext. */void takeOverFrom(ThreadContext new_tc, ThreadContext old_tc); However, after I used takeOverFrom() function, the newly copied thread (other_tc) cannot be activated and it gives an error in activateContext() function. tc-suspend(); tc-pcState(tc-nextInstAddr()); other_tc-takeOverFrom(tc); Am I doing something wrong? Can I copy the content of a thread to another one like that? ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Query regarding DRAM controller's FR-FCFC scheduler implementation.
Hi Users, I am going through the FR-FCFS implementaion of gem5 DRAM Controller. When the queue.size() is greater than 1 and memSchedPolicy == Enums::frfcfs, the ChooseNext function calls reorderQueue. The reorderQueue function searches for row hits first in the queue and if there is a row hit it selects that request as the next request to be processed. My question here is, what if there are multiple row hits? If there are multiple row hits, is it not suppose to choose the first come among multiple row hits? I think the current implementation doesn't arbitrate among multiple row hits. Is this correct or i am missing something. Thanks, Prathap ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Query regarding DRAM controller's FR-FCFS scheduler implementation.
On Wed, Oct 1, 2014 at 1:59 PM, Prathap Kolakkampadath kvprat...@gmail.com wrote: Hi Users, I am going through the FR-FCFS implementaion of gem5 DRAM Controller. When the queue.size() is greater than 1 and memSchedPolicy == Enums::frfcfs, the ChooseNext function calls reorderQueue. The reorderQueue function searches for row hits first in the queue and if there is a row hit it selects that request as the next request to be processed. My question here is, what if there are multiple row hits? If there are multiple row hits, is it not suppose to choose the first come among multiple row hits? I think the current implementation doesn't arbitrate among multiple row hits. Is this correct or i am missing something. Thanks, Prathap ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Query regarding DRAM controller's FR-FCFC scheduler implementation.
Prathap, As far as I remember, it choses the first request (oldest one) among hits. It starts from head of the queue and once there is a hit, you have got the first come among multiple row hits. Thanks, Amin On Wed, Oct 1, 2014 at 1:59 PM, Prathap Kolakkampadath via gem5-users gem5-users@gem5.org wrote: Hi Users, I am going through the FR-FCFS implementaion of gem5 DRAM Controller. When the queue.size() is greater than 1 and memSchedPolicy == Enums::frfcfs, the ChooseNext function calls reorderQueue. The reorderQueue function searches for row hits first in the queue and if there is a row hit it selects that request as the next request to be processed. My question here is, what if there are multiple row hits? If there are multiple row hits, is it not suppose to choose the first come among multiple row hits? I think the current implementation doesn't arbitrate among multiple row hits. Is this correct or i am missing something. Thanks, Prathap ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Query regarding DRAM controller's FR-FCFC scheduler implementation.
Yes. I got that. Thanks Amin. On Wed, Oct 1, 2014 at 2:56 PM, Amin Farmahini amin...@gmail.com wrote: Prathap, As far as I remember, it choses the first request (oldest one) among hits. It starts from head of the queue and once there is a hit, you have got the first come among multiple row hits. Thanks, Amin On Wed, Oct 1, 2014 at 1:59 PM, Prathap Kolakkampadath via gem5-users gem5-users@gem5.org wrote: Hi Users, I am going through the FR-FCFS implementaion of gem5 DRAM Controller. When the queue.size() is greater than 1 and memSchedPolicy == Enums::frfcfs, the ChooseNext function calls reorderQueue. The reorderQueue function searches for row hits first in the queue and if there is a row hit it selects that request as the next request to be processed. My question here is, what if there are multiple row hits? If there are multiple row hits, is it not suppose to choose the first come among multiple row hits? I think the current implementation doesn't arbitrate among multiple row hits. Is this correct or i am missing something. Thanks, Prathap ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] teymori...@yahoo.com has indicated you're a friend. Accept?
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