Re: [gem5-users] Full simulation take a long time
Hi Sahar, If I remember correctly, booting the aarch64 ubuntu image you are using in atomic takes around 10-12 min. Until we have got KVM working for aarch64 I’m afraid that is as fast as it will go. Rather than interacting with the simulation, try and script what you want to do, boot, take a checkpoint, and the iterate around what ever region of interest it is you want to capture. If you’re not using KVM, then interacting directly with the simulator can be rather painful. Andreas From: Sahar Pilevar via gem5-users gem5-users@gem5.orgmailto:gem5-users@gem5.org Reply-To: Sahar Pilevar saharpile...@yahoo.commailto:saharpile...@yahoo.com, gem5 users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org Date: Monday, 10 November 2014 06:52 To: Gem5 Users Mailing List gem5-users@gem5.orgmailto:gem5-users@gem5.org, Gem5 Developer List gem5-...@gem5.orgmailto:gem5-...@gem5.org Subject: [gem5-users] Full simulation take a long time Hi all, when I use this command for full simulation ./build/ARM/gem5.opt configs/example/fs.py --kernel=vmlinux.aarch64.20140821 --disk-image=/home/sahar/gem5/full_system_images/arch1/disks/aarch64-ubuntu-trusty-headless.img --mem-size=512MB after sahar@ubuntu:~/gem5$ m5term localhost 3456 in a new terminal , it does not proceed any more and it remains in: sahar@ubuntu:~/gem5$ ./build/ARM/gem5.opt configs/example/fs.py --kernel=vmlinux.aarch64.20140821 --disk-image=/home/sahar/gem5/full_system_images/arch1/disks/aarch64-ubuntu-trusty-headless.img --mem-size=512MB gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. gem5 compiled Nov 8 2014 07:29:04 gem5 started Nov 9 2014 12:05:34 gem5 executing on ubuntu command line: ./build/ARM/gem5.opt configs/example/fs.py --kernel=vmlinux.aarch64.20140821 --disk-image=/home/sahar/gem5/full_system_images/arch1/disks/aarch64-ubuntu-trusty-headless.img --mem-size=512MB Global frequency set at 1 ticks per second warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) info: kernel located at: /home/sahar/gem5/full_system_images/arch1/disks/binaries/vmlinux.aarch64.20140821 Listening for system connection on port 5900 Listening for system connection on port 3456 0: system.cpu.isa: ISA system set to: 0x39d2d00 0x39d2d00 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x8008 info: Loading DTB file: /home/sahar/gem5/full_system_images/arch1/disks/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x8800 warn: Kernel supports generic PCI host but PCI Config offsets configured for legacy. Set pci_cfg_gen_offsets to True warn: Kernel supports generic PCI host but PCI IO base is set to 0. Set pci_io_base to the start of PCI IO space REAL SIMULATION warn: Existing EnergyCtrl, but no enabled DVFSHandler found. info: Entering event queue @ 0. Starting simulation... 19229139000: system.terminal: attach terminal 0 and in new terminal I have: sahar@ubuntu:~/gem5$ m5term localhost 3456 m5 slave terminal: Terminal 0 Does anybody have suggestion about this problem? Thank you, Sahar. -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] X86 switch CPU
Hello, I would like to execute the following boot script: m5 switchcpu ./application m5 switchcpu So using the x86 simulator I would like to boot in atomic simple switch to o3 and after the execution of the application I would like to switch back to atomic simple in order to finish my simulation. I think I should make some changes in the Simulation.py file. Could anyone guide me through the procedure? Thank you, Konstantinos Parasyris ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] all the cores are not online when performing ARM full system simulation to test DVFS
Hi All, I am following the steps mentioned in the documentation to configure per-core dvfs. I am trying to simulate four cores by giving the following command M5_PATH=$(pwd)/.. ./build/ARM/gem5.opt --debug-flags=DVFS,EnergyCtrl \ --debug-file=dfvs_debug.log configs/example/fs.py --cpu-type=AtomicSimpleCPU \ *-n 4 *--machine-type=VExpress_EMM --kernel=../linux-linaro-tracking-gem5/vmlinux \ --dtb-filename=../linux-linaro-tracking-gem5/arch/arm/boot/dts/\ *vexpress-v2p-ca15-tc1-gem5_dvfs_per_core_4cpus.dts* \ --disk-image=../disks/arm-ubuntu-natty-headless.img \ --cpu-clock=\['1 GHz','750 MHz','500 MHz'\] I am using the above dtb to configure per core dvfs and start the simulation. However, when I check /sys/devices/system/cpu/cpu1,2,3/online, all the cores are offline except core0. When I try to write '1' to 'online' file for any core, it throws the following error *CPU1: failed to boot: -38* *-bash: echo: write error: Function not implemented * Could you please help me here. Regards Rahul ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] all the cores are not online when performing ARM full system simulation to test DVFS
Hi Rahul, On Monday 10 November 2014 09:08:46 rahul shrivastava via gem5-users wrote: I am following the steps mentioned in the documentation to configure per-core dvfs. I am trying to simulate four cores by giving the following command M5_PATH=$(pwd)/.. ./build/ARM/gem5.opt --debug-flags=DVFS,EnergyCtrl \ --debug-file=dfvs_debug.log configs/example/fs.py --cpu-type=AtomicSimpleCPU \ -n 4 --machine-type=VExpress_EMM --kernel=../linux-linaro-tracking-gem5/vmlinux \ --dtb-filename=../linux-linaro-tracking-gem5/arch/arm/boot/dts/\ vexpress-v2p-ca15-tc1-gem5_dvfs_per_core_4cpus.dts \ --disk-image=../disks/arm-ubuntu-natty-headless.img \ --cpu-clock=\['1 GHz','750 MHz','500 MHz'\] I am using the above dtb to configure per core dvfs and start the simulation. Could you try starting this with the actual dtB file, rather than the dtS? dtsc should help you getting this compiled. However, when I check /sys/devices/system/cpu/cpu1,2,3/online, all the cores are offline except core0. When I try to write '1' to 'online' file for any core, it throws the following error CPU1: failed to boot: -38 Yep, that happens when the kernel cannot initialise the other cores for one reason or another. Could you do cat /proc/cpuinfo and post that, in addition to the suggestion above, please? Thanks, Stephan -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] all the cores are not online when performing ARM full system simulation to test DVFS
On Monday 10 November 2014 11:43:39 Stephan Diestelhorst via gem5-users wrote: Hi Rahul, On Monday 10 November 2014 09:08:46 rahul shrivastava via gem5-users wrote: I am following the steps mentioned in the documentation to configure per-core dvfs. I am trying to simulate four cores by giving the following command M5_PATH=$(pwd)/.. ./build/ARM/gem5.opt --debug-flags=DVFS,EnergyCtrl \ --debug-file=dfvs_debug.log configs/example/fs.py --cpu-type=AtomicSimpleCPU \ -n 4 --machine-type=VExpress_EMM --kernel=../linux-linaro-tracking-gem5/vmlinux \ --dtb-filename=../linux-linaro-tracking-gem5/arch/arm/boot/dts/\ vexpress-v2p-ca15-tc1-gem5_dvfs_per_core_4cpus.dts \ --disk-image=../disks/arm-ubuntu-natty-headless.img \ --cpu-clock=\['1 GHz','750 MHz','500 MHz'\] I am using the above dtb to configure per core dvfs and start the simulation. Could you try starting this with the actual dtB file, rather than the dtS? dtsc should help you getting this compiled. However, when I check /sys/devices/system/cpu/cpu1,2,3/online, all the cores are offline except core0. When I try to write '1' to 'online' file for any core, it throws the following error CPU1: failed to boot: -38 Yep, that happens when the kernel cannot initialise the other cores for one reason or another. Could you do cat /proc/cpuinfo and post that, in addition to the suggestion above, please? Could you also please attach / dump your config.ini and config.json somewhere (email attachement or pastebin)? -- Thanks, Stephan -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] X86 atomic CPU error message
George Michelogiannakis mixelogj13 at yahoo.co.uk writes: Hi all, I'm using the latest stable version of Gem5 and I built X86_MESI_CMP_directory with the default settings and also AtomicSimpleCPU added to the options. I get the following error: Traceback (most recent call last): File string, line 1, in module File /home/parallels/gem5-stable/src/python/m5/main.py, line 387, in main exec filecode in scope File configs/example/fs.py, line 63, in module (options, args) = parser.parse_args() File /usr/lib/python2.7/optparse.py, line 1383, in parse_args values = self.get_default_values() File /usr/lib/python2.7/optparse.py, line 1328, in get_default_values defaults[option.dest] = option.check_value(opt_str, default) File /usr/lib/python2.7/optparse.py, line 769, in check_value return checker(self, opt, value) File /usr/lib/python2.7/optparse.py, line 438, in check_choice % (opt, value, choices)) optparse.OptionValueError: option --cpu-type: invalid choice: 'atomic' (choose from 'arm_detailed', 'DerivO3CPU', 'TimingSimpleC PU', 'timing', 'detailed') Did you ever get this figured out? I am having the exact same problem, except I built the ARM, O3CPU model. I see this problem even when I explicitly specify the cpu-type as detailed. I've been trying to follow this through the Python debugger but I can't pinpoint the problem. ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Deadlock threshold
Hi all, Currently, I'm trying to simulate some parsec benchmarks on a Ruby + Garnet system, using Mesh; 8 cpus, L1 and L2; X86_MESI_Two_Level protocol, for example. Unfortunatelly, the simulations have been stopped by an deadlock detection, after some minutes starting the workload (e.g. blackscholes). The deadlock_threshold is set up to be 500.000 cycles (default value). Questions: - What could happen if I remove this detection? - What do you suggest me to verify what is causing this long access time on the Sequencer? Thank you! -- Atenciosamente, Matheus Alcântara Souza ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] X86 atomic CPU error message
Eric W Mackay via gem5-users gem5-users at gem5.org writes: Did you ever get this figured out? I am having the exact same problem, except I built the ARM, O3CPU model. I see this problem even when I explicitly specify the cpu-type as detailed. I've been trying to follow this through the Python debugger but I can't pinpoint the problem. ___ gem5-users mailing list gem5-users at gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users I answered my own question. Turns out that optparse sets all the options to their default values and then goes in and replaces any options you've specified on the command line. Since atomic is incompatible with the O3CPU ARM model, it wouldn't even get to parsing the arguments I specified since it checks whether the default values are legal first. This should probably be seen as a bug. ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Deadlock threshold
My question is already answered. https://www.mail-archive.com/gem5-dev@m5sim.org/msg09340.html Sorry Atenciosamente, Matheus Alcântara Souza (Via iPhone) Em 10/11/2014, às 16:41, Matheus Alcântara Souza ticks...@gmail.com escreveu: Hi all, Currently, I'm trying to simulate some parsec benchmarks on a Ruby + Garnet system, using Mesh; 8 cpus, L1 and L2; X86_MESI_Two_Level protocol, for example. Unfortunatelly, the simulations have been stopped by an deadlock detection, after some minutes starting the workload (e.g. blackscholes). The deadlock_threshold is set up to be 500.000 cycles (default value). Questions: - What could happen if I remove this detection? - What do you suggest me to verify what is causing this long access time on the Sequencer? Thank you! -- Atenciosamente, Matheus Alcântara Souza ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Multiple Application run in FS mode in x86 for a CMPs .
Hello all, I want to simulate following thing on gem 5 in X86 architecture .I am using pre compiled disk image(from http://www.cs.utexas.edu/~parsec_m5) of parsec and binary kernel x86_64-vmlinux-2.6.28.4-smp.and run a Blackscholes benchmark.So i want to confirm some following things regarding to this simulation as i stuck on all these things for last 20 days: i)Is it working for chip multiprocessor means each cpu stats in stats.txt is for each core or something else? ii)How can I bind a application on each core. iii)I want that each application run concurrently on a core. iv) I used following command .rcS to run two application(application/core) .(uses MESI_Two_Level) **command* ./build/X86/gem5.opt configs/example/fs.py --script=./path/my.rcS -n 2 --l1i_size=32kB --l1d_size=32kB --l2_size=2MB --num-l2caches=2 --ruby --garnet-network=fixed --topology=Mesh --mesh-rows=2 --num-dirs=2 .rcS file*** #!/bin/sh # File to run the blackscholes benchmark export GOMP_CPU_AFFINITY=0 1 cd /parsec/install/bin #/sbin/m5 dumpstats /sbin/m5 dumpresetstats ./blackscholes 1 /parsec/install/inputs/blackscholes/in_4K.txt /parsec/install/inputs/blackscholes/prices.txt ./bodytrack /parsec/install/inputs/bodytrack/sequenceB_1 4 1 1000 5 0 1 echo Done :D /sbin/m5 exit /sbin/m5 exit Please tell me sequence to simulate above configuration.. Thank you in advance. ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DRAM memory access latency
Hello Andreas, waiting in the port until the crossbar can accept it Is this because of Bus Contention? In that case, is there a way to reduce this latency by changing any parameters in gem5? Thanks, Prathap On Thu, Nov 6, 2014 at 2:30 PM, Andreas Hansson andreas.hans...@arm.com wrote: Hi Prathap, I suspect the answer to the mysterious 50 ns is due to the responses being sent back using a so called “queued port” in gem5. Thus, from the memory controller’s point of view the packet is all done, but is now waiting in the port until the crossbar can accept it. This queue can hold a number of packets if there has been a burst of responses that are trickling through the crossbar on their way back. You can always run with some debug flags to verify this (XBar, DRAM, PacketQueue etc). Coincidentally I have been working on a patch to remove this “invisible” queue and should hopefully have this on the review board shortly. Andreas From: Prathap Kolakkampadath kvprat...@gmail.com Date: Thursday, November 6, 2014 at 5:47 PM To: Andreas Hansson andreas.hans...@arm.com Cc: gem5 users mailing list gem5-users@gem5.org Subject: Re: [gem5-users] DRAM memory access latency Hello Andreas, Thanks for your reply. Ok. I got that the memory access latency indeed includes the queueing latency. And for the read/write request that miss the buffer has a static latency of Static frontend latency + Static backend latency. To summarize, the test i run is a latency benchmark which is a pointer chasing test(only one request at a time) , generate reads to a specific DRAM bank (Bank partitioned).This test is running on cpu0 of 4 cpu arm_detailed running at 1GHZ frequency with 1MB shared L2 cache and single channel LPDDR3 x32 DRAM. The bank used by cpu0 is not shared between other cpu's. Test statistics: system.mem_ctrls.avgQLat 43816.35 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst system.mem_ctrls.avgMemAccLat 63816.35 # Average memory access latency per DRAM burst system.mem_ctrls.avgRdQLen 2.00 # Average read queue length when enqueuing system.mem_ctrls.avgGap 136814.25 # Average gap between requests system.l2.ReadReq_avg_miss_latency::switch_cpus0.data 114767.654811 # average ReadReq miss latency Based on above test statistics: avgMemAccLat is 63ns, which i presume the sum of tRP(15ns)+tRCD(15ns) +tCL(15ns)+static latency(20ns). Is this breakup correct? However the l2.ReadReq_avg_miss_atency is 114ns which is ~50 ns more than the avgMemAccLat. I couldn't figure out the components contributing to this 50ns latency. Your thoughts on this is much appreciated. Regards, Prathap On Thu, Nov 6, 2014 at 3:03 AM, Andreas Hansson andreas.hans...@arm.com wrote: Hi Prathap, The avgMemAccLat does indeed include any queueing latency. For the precise components included in the various latencies I would suggest checking the source code. Note that the controller is not just accounting for the static (and dynamic) DRAM latency, but also the static controller pipeline latency (and dynamic queueing latency). The controller static latency is two parameters that are by default also adding a few 10’s of nanoseconds. Let me know if you need more help breaking out the various components. Andreas From: Prathap Kolakkampadath via gem5-users gem5-users@gem5.org Reply-To: Prathap Kolakkampadath kvprat...@gmail.com, gem5 users mailing list gem5-users@gem5.org Date: Wednesday, 5 November 2014 05:36 To: Tao Zhang tao.zhang.0...@gmail.com, gem5 users mailing list gem5-users@gem5.org, Amin Farmahini amin...@gmail.com Subject: Re: [gem5-users] DRAM memory access latency Hi Tao,Amin, According to gem5 source, MemAccLat is the time difference between the packet enters in the controller and packet leaves the controller. I presume this added with BusLatency and static backend latency should match with system.l2.ReadReq_avg_miss_latency. However i see a difference of approx 50ns. As mentioned above if MemAccLat is the time a packet spends in memory controller, then it should include the queuing latency too. In that case the value of avgQLat looks suspicious. Is the avgQlat part of avgMemAccLat? Thanks, Prathap On Tue, Nov 4, 2014 at 3:11 PM, Tao Zhang tao.zhang.0...@gmail.com wrote: From the stats, I'd like to use system.mem_ctrls.avgMemAccLat as the overall average memory latency. It is 63.816ns, which is very close to 60ns as you calculated. I guess the extra 3.816ns is due to the refresh penalty. -Tao On Tue, Nov 4, 2014 at 12:10 PM, Prathap Kolakkampadath kvprat...@gmail.com wrote: Hi Toa, Amin, Thanks for your reply. To discard interbank interference and queueing delay, i have
[gem5-users] Help
Hi MatheusHow is it going. What I must be do for following case?I want to modify the router_d.cc code and change some line of it based on my purpose and then I want to see the result of changes in stats.txt. Best ---Babak Aghaei Ph.D candidate ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
