[gem5-users] profiling benchmarks with arm in full system mode
Hello everyone , Am i brainless to ask those questions ? or they have been processed ? Because since i'm asking for help there is no answers . This time i just want to know if it's possible to profile an application in full system with arm as architecture using gprof ? Thanks -- *Cordialement* ** * ASNGAR DJELAR ESPERANCE* Master 2 Génie Electrique Informatique Industrielle 56100 Lorient Tel:0664117963 esperance.asn...@gmail.com ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Cache Flushing in FS-ARM
Dear All, I am running a full-system ARM simulation (aarch-system-2014-10/vmlinux.aarch32.ll_20131205.0-gem5). I intend to flush the L1 and L2 caches in my device driver. For the L1 cache, I succeed without any problem, but for the L2 cache when I use *outer_clean_range()*, nothing happens, and when I use *outer_cache.flush_range()*, I get a kernel fault (null pointer). Also, I get in the messages that the following instructions are not implemented: warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented Can anybody help me with this issue? Thanks in advance, Best Regards, -- Erfan Azarkhish Micrel Lab - Viale Carlo Pepoli 3/2 - 40123, Bologna DEI - University of Bologna, Italy https://www.linkedin.com/in/erfanazarkhish ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Cache Flushing in FS-ARM
Hi Erfan, The cache management instructions are currently not implemented. It would be a great addition though. The only related instruction that is currently supported is dzcva. If you’re interested in filling in the blanks I’m sure there are plenty people willing to help out. All devices in gem5 are IO coherent, and for that reason we have a functionally correct system also without the cache flushes. There is quite a bunch of patches on RB that I’m about to push that also makes uncacheable accesses snoop into the caches properly. I hope that provides some clarity. Regarding your kernel panic I’d say the best way forward is to start digging in and debug what is happening. Andreas From: Erfan Azarkhish e.azarkh...@gmail.commailto:e.azarkh...@gmail.com Reply-To: gem5 users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org Date: Monday, 4 May 2015 14:29 To: gem5 users gem5-users@gem5.orgmailto:gem5-users@gem5.org Subject: [gem5-users] Cache Flushing in FS-ARM Dear All, I am running a full-system ARM simulation (aarch-system-2014-10/vmlinux.aarch32.ll_20131205.0-gem5). I intend to flush the L1 and L2 caches in my device driver. For the L1 cache, I succeed without any problem, but for the L2 cache when I use outer_clean_range(), nothing happens, and when I use outer_cache.flush_range(), I get a kernel fault (null pointer). Also, I get in the messages that the following instructions are not implemented: warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented Can anybody help me with this issue? Thanks in advance, Best Regards, -- Erfan Azarkhish Micrel Lab - Viale Carlo Pepoli 3/2 - 40123, Bologna DEI - University of Bologna, Italy https://www.linkedin.com/in/erfanazarkhish -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Cache Flushing in FS-ARM
Dear Andreas, Thank you very much for the info, Best, On Mon, May 4, 2015 at 3:43 PM, Andreas Hansson andreas.hans...@arm.com wrote: Hi Erfan, The cache management instructions are currently not implemented. It would be a great addition though. The only related instruction that is currently supported is dzcva. If you’re interested in filling in the blanks I’m sure there are plenty people willing to help out. All devices in gem5 are IO coherent, and for that reason we have a functionally correct system also without the cache flushes. There is quite a bunch of patches on RB that I’m about to push that also makes uncacheable accesses snoop into the caches properly. I hope that provides some clarity. Regarding your kernel panic I’d say the best way forward is to start digging in and debug what is happening. Andreas From: Erfan Azarkhish e.azarkh...@gmail.com Reply-To: gem5 users mailing list gem5-users@gem5.org Date: Monday, 4 May 2015 14:29 To: gem5 users gem5-users@gem5.org Subject: [gem5-users] Cache Flushing in FS-ARM Dear All, I am running a full-system ARM simulation (aarch-system-2014-10/vmlinux.aarch32.ll_20131205.0-gem5). I intend to flush the L1 and L2 caches in my device driver. For the L1 cache, I succeed without any problem, but for the L2 cache when I use *outer_clean_range()*, nothing happens, and when I use *outer_cache.flush_range()*, I get a kernel fault (null pointer). Also, I get in the messages that the following instructions are not implemented: warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented Can anybody help me with this issue? Thanks in advance, Best Regards, -- Erfan Azarkhish Micrel Lab - Viale Carlo Pepoli 3/2 - 40123, Bologna DEI - University of Bologna, Italy https://www.linkedin.com/in/erfanazarkhish -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Erfan Azarkhish Micrel Lab - Viale Carlo Pepoli 3/2 - 40123, Bologna DEI - University of Bologna, Italy https://www.linkedin.com/in/erfanazarkhish ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Query regarding blocking cache slave port
Hello All, I am simulating an ARM O3 multi-core system with private L1 cache and a Shared L2 cache. I am investigating the MSHR contention in the L2 cache. If cache has no free MSHRs, this Marks the access path of the cache as blocked and also sets the blocked flag in the slave interface.This means there won't be any further access to the L2 cache. Instead of blocking the L2 cache altogether, i would like to place a MSHR reservation to a selected core. So that requests from only selected core are blocked based on its respective MSHR utilization. I am not sure if this is feasible. Do L2 Bus has an arbitrator which can be modified to do this? Thanks, Prathap ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Query regarding blocking cache slave port
Thanks Andreas. On Mon, May 4, 2015 at 5:11 PM, Andreas Hansson andreas.hans...@arm.com wrote: Hi Prathap, Check retryWaiting in Xbar. There we choose the port to go next when one or more ports had to wait. If you want to implement what you suggest you also have to perform a check in recvTimingReq to not just see if the layer is busy, but also check if the port asking is within budget. Andreas From: Prathap Kolakkampadath kvprat...@gmail.com Reply-To: gem5 users mailing list gem5-users@gem5.org Date: Monday, 4 May 2015 22:56 To: gem5 users mailing list gem5-users@gem5.org Subject: Re: [gem5-users] Query regarding blocking cache slave port Hi Andreas, Thanks for your reply. I am trying to figure out how to implement this based on your inputs. Can you also please point out the data structures which maintains the queue in cross bar.? Thanks, Prathap On Mon, May 4, 2015 at 4:04 PM, Andreas Hansson andreas.hans...@arm.com wrote: Hi Prathap, The most sensible place to implement the arbitration is indeed in the crossbar which is conceptually part of the L2 cache. By default the crossbar uses First-Come First-Served, but you can change with not too much coding. The tricky bit in this case is to base the selection on MSHRs, since the crossbar has no such accounting. I would think the easiest is to add outstanding transaction counting per SlavePort in the crossbar, and then only let a port have X outstanding transactions. Overall this would be valuable functionality, so if you do code it up, please post a patch. It would be a great contribution. Andreas From: Prathap Kolakkampadath kvprat...@gmail.com Reply-To: gem5 users mailing list gem5-users@gem5.org Date: Monday, 4 May 2015 20:18 To: gem5 users mailing list gem5-users@gem5.org Subject: [gem5-users] Query regarding blocking cache slave port Hello All, I am simulating an ARM O3 multi-core system with private L1 cache and a Shared L2 cache. I am investigating the MSHR contention in the L2 cache. If cache has no free MSHRs, this Marks the access path of the cache as blocked and also sets the blocked flag in the slave interface.This means there won't be any further access to the L2 cache. Instead of blocking the L2 cache altogether, i would like to place a MSHR reservation to a selected core. So that requests from only selected core are blocked based on its respective MSHR utilization. I am not sure if this is feasible. Do L2 Bus has an arbitrator which can be modified to do this? Thanks, Prathap -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Query regarding blocking cache slave port
Hi Prathap, Check retryWaiting in Xbar. There we choose the port to go next when one or more ports had to wait. If you want to implement what you suggest you also have to perform a check in recvTimingReq to not just see if the layer is busy, but also check if the port asking is within budget. Andreas From: Prathap Kolakkampadath kvprat...@gmail.commailto:kvprat...@gmail.com Reply-To: gem5 users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org Date: Monday, 4 May 2015 22:56 To: gem5 users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org Subject: Re: [gem5-users] Query regarding blocking cache slave port Hi Andreas, Thanks for your reply. I am trying to figure out how to implement this based on your inputs. Can you also please point out the data structures which maintains the queue in cross bar.? Thanks, Prathap On Mon, May 4, 2015 at 4:04 PM, Andreas Hansson andreas.hans...@arm.commailto:andreas.hans...@arm.com wrote: Hi Prathap, The most sensible place to implement the arbitration is indeed in the crossbar which is conceptually part of the L2 cache. By default the crossbar uses First-Come First-Served, but you can change with not too much coding. The tricky bit in this case is to base the selection on MSHRs, since the crossbar has no such accounting. I would think the easiest is to add outstanding transaction counting per SlavePort in the crossbar, and then only let a port have X outstanding transactions. Overall this would be valuable functionality, so if you do code it up, please post a patch. It would be a great contribution. Andreas From: Prathap Kolakkampadath kvprat...@gmail.commailto:kvprat...@gmail.com Reply-To: gem5 users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org Date: Monday, 4 May 2015 20:18 To: gem5 users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org Subject: [gem5-users] Query regarding blocking cache slave port Hello All, I am simulating an ARM O3 multi-core system with private L1 cache and a Shared L2 cache. I am investigating the MSHR contention in the L2 cache. If cache has no free MSHRs, this Marks the access path of the cache as blocked and also sets the blocked flag in the slave interface.This means there won't be any further access to the L2 cache. Instead of blocking the L2 cache altogether, i would like to place a MSHR reservation to a selected core. So that requests from only selected core are blocked based on its respective MSHR utilization. I am not sure if this is feasible. Do L2 Bus has an arbitrator which can be modified to do this? Thanks, Prathap -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Query regarding blocking cache slave port
Hi Andreas, Thanks for your reply. I am trying to figure out how to implement this based on your inputs. Can you also please point out the data structures which maintains the queue in cross bar.? Thanks, Prathap On Mon, May 4, 2015 at 4:04 PM, Andreas Hansson andreas.hans...@arm.com wrote: Hi Prathap, The most sensible place to implement the arbitration is indeed in the crossbar which is conceptually part of the L2 cache. By default the crossbar uses First-Come First-Served, but you can change with not too much coding. The tricky bit in this case is to base the selection on MSHRs, since the crossbar has no such accounting. I would think the easiest is to add outstanding transaction counting per SlavePort in the crossbar, and then only let a port have X outstanding transactions. Overall this would be valuable functionality, so if you do code it up, please post a patch. It would be a great contribution. Andreas From: Prathap Kolakkampadath kvprat...@gmail.com Reply-To: gem5 users mailing list gem5-users@gem5.org Date: Monday, 4 May 2015 20:18 To: gem5 users mailing list gem5-users@gem5.org Subject: [gem5-users] Query regarding blocking cache slave port Hello All, I am simulating an ARM O3 multi-core system with private L1 cache and a Shared L2 cache. I am investigating the MSHR contention in the L2 cache. If cache has no free MSHRs, this Marks the access path of the cache as blocked and also sets the blocked flag in the slave interface.This means there won't be any further access to the L2 cache. Instead of blocking the L2 cache altogether, i would like to place a MSHR reservation to a selected core. So that requests from only selected core are blocked based on its respective MSHR utilization. I am not sure if this is feasible. Do L2 Bus has an arbitrator which can be modified to do this? Thanks, Prathap -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Query regarding blocking cache slave port
Hi Prathap, The most sensible place to implement the arbitration is indeed in the crossbar which is conceptually part of the L2 cache. By default the crossbar uses First-Come First-Served, but you can change with not too much coding. The tricky bit in this case is to base the selection on MSHRs, since the crossbar has no such accounting. I would think the easiest is to add outstanding transaction counting per SlavePort in the crossbar, and then only let a port have X outstanding transactions. Overall this would be valuable functionality, so if you do code it up, please post a patch. It would be a great contribution. Andreas From: Prathap Kolakkampadath kvprat...@gmail.commailto:kvprat...@gmail.com Reply-To: gem5 users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org Date: Monday, 4 May 2015 20:18 To: gem5 users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org Subject: [gem5-users] Query regarding blocking cache slave port Hello All, I am simulating an ARM O3 multi-core system with private L1 cache and a Shared L2 cache. I am investigating the MSHR contention in the L2 cache. If cache has no free MSHRs, this Marks the access path of the cache as blocked and also sets the blocked flag in the slave interface.This means there won't be any further access to the L2 cache. Instead of blocking the L2 cache altogether, i would like to place a MSHR reservation to a selected core. So that requests from only selected core are blocked based on its respective MSHR utilization. I am not sure if this is feasible. Do L2 Bus has an arbitrator which can be modified to do this? Thanks, Prathap -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
