[gem5-users] Getting error while simulating multi level cache for ARM FS simulation
Hi, I am using the following command to test multi level caches for ARM FS simulation M5_PATH=$(pwd)/.. ./build/ARM/gem5.fast configs/example/fs.py --script=./auto_scripts --cpu-type=DerivO3CPU -n 4* --caches --l1d_size=32kB --l1i_size=32kB --l2cache --l2_size=256kB --l3_size=20480kB* --machine-type=VExpress_EMM --kernel=../linux-linaro-tracking-gem5/vmlinux --dtb-filename=../linux-linaro-tracking-gem5/arch/arm/boot/dts/vexpress-v2p-ca15-tc1-gem5_dvfs_per_core_4cpus.dtb --disk-image=../disks/arm-ubuntu-natty-headless.img --cpu-clock=\['1 GHz','750 MHz','500 MHz'\] But it throws a following exception. Could you please let me know if I am missing some option? *TRACEBACK* File string, line 1, in module File /home/rahuls/gem5-stable-0e86fac7254c/gem5/src/python/m5/main.py, line 388, in main exec filecode in scope File configs/example/fs.py, line 335, in module test_sys = build_test_system(np) File configs/example/fs.py, line 231, in build_test_system CacheConfig.config_cache(options, test_sys) File /home/rahuls/gem5-stable-0e86fac7254c/gem5/configs/common/CacheConfig.py, line 72, in config_cache assoc=options.l2_assoc) File /home/rahuls/gem5-stable-0e86fac7254c/gem5/src/python/m5/SimObject.py, line 1044, in __init__ setattr(self, key, val) File /home/rahuls/gem5-stable-0e86fac7254c/gem5/src/python/m5/SimObject.py, line 1122, in __setattr__ value = param.convert(value) File /home/rahuls/gem5-stable-0e86fac7254c/gem5/src/python/m5/params.py, line 212, in convert return self.ptype(value) TypeError: __init__() takes exactly 1 argument (2 given) Error setting param L2Cache.clk_domain to [m5.objects.ClockDomain.SrcClockDomain object at 0x7f2b106ed1d0, m5.objects.ClockDomain.SrcClockDomain object at 0x7f2b106ed310, m5.objects.ClockDomain.SrcClockDomain object at 0x7f2b106ed4d0, m5.objects.ClockDomain.SrcClockDomain object at 0x7f2b106ed690] Regards Rahul ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Issue on setting cache line size using --cacheline_size
Hi All, I'm running my program on various possible configurations on gem5 . In one particular configuration , I have set --cacheline_size=32 . This throws the following error : fatal: fetch buffer size (64 bytes) is greater than the cache block size (32 bytes) @ tick 0 [DefaultFetch:build/ALPHA/cpu/o3/fetch_impl.hh, line 107] Memory Usage: 614136 KBytes Program aborted at cycle 0 Shouldn't the fetch buffer size be equal to the cache line size set ? Does it need to be explicitly set? Please help. Thanks Regards, Gnanambikai ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Issue on setting cache line size using --cacheline_size
Hi, I tried this option before and have similar issue. I think although the option is provided, the cache line size should still be set 64 bytes. If you want use various cache line size you need to modify the codes. On Mon, Jul 20, 2015 at 9:20 AM, gnanu krishna gnanukris...@gmail.com wrote: Hi All, I'm running my program on various possible configurations on gem5 . In one particular configuration , I have set --cacheline_size=32 . This throws the following error : fatal: fetch buffer size (64 bytes) is greater than the cache block size (32 bytes) @ tick 0 [DefaultFetch:build/ALPHA/cpu/o3/fetch_impl.hh, line 107] Memory Usage: 614136 KBytes Program aborted at cycle 0 Shouldn't the fetch buffer size be equal to the cache line size set ? Does it need to be explicitly set? Please help. Thanks Regards, Gnanambikai ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Qi Jia Graduate Student Department of Electrical and Computer Engineering North Carolina State University, Raleigh ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Handling write backs
Hello Users, I am running a test which generate write misses to LLC. I am looking at the cache implementation code. What i understood is, write are treated as write backs; on miss, write back commands allocate a new block in cache and write the data into it and marks this block as dirty. When the dirty blocks are replaced,these will be written in to write buffers. I have following questions on this: 1) When i run the test which generates write misses, i see same number of reads from memory as the number of writes. Does this mean, write backs also fetches the cache-line from main memory? 2) When the blocks in write buffers will be written to memory? Is it written when the write buffers are full? It would be great if someone can help me in understanding this. Thanks, Prathap ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Booting 64 processors causes Ruby deadlock
Hi all I compiled ALPHA_MOESI_CMP_directory/gem5.opt and downloaded the full system images from UT Austin website. When there are 4 processors, I can get the system up and running the blackscholes benchmark successfully using following command: ./build/ALPHA_MOESI_CMP_directory/gem5.opt ./configs/example/fs.py --ruby -n 4 --topology=Mesh --mesh-row=2 --num-dirs=4 --num-l2caches=4 --script=./run.rcS However if I increase the number of CPUs to 64 like this: ./build/ALPHA_MOESI_CMP_directory/gem5.opt ./configs/example/fs.py --ruby -n 64 --topology=Mesh --mesh-row=8 --num-dirs=64 --num-l2caches=64 --script=./run.rcS I got this error REAL SIMULATION info: Entering event queue @ 0. Starting simulation... panic: Possible Deadlock detected. Aborting! version: 0 request.paddr: 0x[0x4000, line 0x4000] m_readRequestTable: 1 current time: 25000 issue_time: 0 difference: 25000 @ tick 25000 [wakeup:build/ALPHA_MOESI_CMP_directory/mem/ruby/system/Sequencer.cc, line 101] I found that this 0x4000 address is the first cache block that all the processors try to access when they start. And after a L2 cache miss, this missing request is forwarded to its home directory, Directory 0. In my understanding Directory 0 should go to ask a memory controller to fetch this cache block. However, I don't observe the directory controller sending message to memory controller, and in ruby debug log I can see it invokes *qf_queueMemoryFetchRequest*. 4500: system.ruby.dir_cntrl0: [Directory_Controller 0], Time: 9, state: I, event: GETS, addr: [0x4000, line 0x4000] 4500: system.ruby.dir_cntrl0: executing qf_queueMemoryFetchRequest 4500: system.ruby.dir_cntrl0: executing i_popIncomingRequestQueue 4500: system.ruby.dir_cntrl0: next_state: IS Is my configuration causing this problem or other reasons? Many thanks Wen ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Tracking DRAM requests from a process
Hello Davesh,
You could probably use something like this:
To check the requests coming from cpus0
if (system()-getMasterName(pkt-req-masterId()) == switch_cpus0.data)
{}
Hope this helps.
Thanks,
Prathap
On Mon, Jul 20, 2015 at 6:09 PM, Davesh Shingari shingaridav...@gmail.com
wrote:
Polydoros Petrakis polpetras at gmail.com writes:
Maybe you can check the physical memory range allocated for each
process and track requests depending on the access address. (Check which
range it belongs to)
On 31 March 2015 at 00:30, Prathap Kolakkampadath kvprathap at
gmail.com wrote:
Hello Andreas,
I am trying to collect the per request memory access latency of a
specific linux process Read requests. I am running two memory intensive
linux processes in a single core.
In my understanding, the Thread id/Context id, Master id are the same
for the two process memory requests running in the same core. So I won't
be able to differentiate the requests of one process from the other
using that. Is it possible to differentiate the memory requests at DRAM
Controller layer based on linux process id?
Thanks,
Prathap
On Mon, Mar 30, 2015 at 12:35 PM, Andreas Hansson Andreas.Hansson
at arm.com wrote:
Hi Prathap,
Could you be a bit more specific about what you mean by “tracking
requests”. Each request that originates in the CPU has an ASID and
ThreadID associated with it, as well as a MasterID. You should be able
to access these at the DRAM controller if that’s
what you’re after. Note that you end up getting requests without this
information (write backs etc), so you cannot always rely on it.
Andreas
From: Prathap Kolakkampadath kvprathap at gmail.comReply-To: gem5
users mailing list gem5-users at gem5.orgDate: Monday, 30 March 2015
17:27To: gem5 users mailing list gem5-users at gem5.orgSubject:
[gem5-users] Tracking DRAM requests from a process
Hello Users,
I am running Gem5 on ARM FS mode using classic memory system. I am
running two process on a single core. I need to track the DRAM requests
(memory access latency) of a particular process. Is it possible to
identify the process id of a linux process in the DRAM
Controller layer?
Thanks,
Prathap Kumar Valsan
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are confidential and may also be privileged. If you are not the intended
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information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1
9NJ, Registered in England Wales, Company No: 2548782
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Hi
Did you find a way to know the core where the memory request originated?
If I use function to get threadId or asid, I get following error:
gem5.opt: build/ARM/mem/request.hh:533: int Request::getAsid() const:
Assertion `privateFlags.isSet(VALID_VADDR)' failed.
And for masterId, the number changes with simulation (I think it is
generated statically).
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[gem5-users] How to know master of memory request?
Hi I want to know the master of the memory request at the cache and main memory level. The packet is the one which is being send from the upper layers to lower layers i.e. cache - memory. I can see that packet (pkt) has a field requestPtr (req) which has functions masterId, threadId, and taskId. Thread Id is always coming 0 and Task Id is always coming 1024. MasterId is consistent with master during a simulation, but the number assigned gets generated dynamically, so can't be used. Can anyone provide any pointers about in-built functions to know the master? -- Have a great day! Thanks and Warm Regards Davesh Shingari Master's in Computer Engineering [EE] Arizona State University davesh.shing...@asu.edu ᐧ ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Tracking DRAM requests from a process
Hi Prathap
Thanks a lot. It works perfectly.
ᐧ
On Mon, Jul 20, 2015 at 4:35 PM, Prathap Kolakkampadath kvprat...@gmail.com
wrote:
Hello Davesh,
You could probably use something like this:
To check the requests coming from cpus0
if (system()-getMasterName(pkt-req-masterId()) == switch_cpus0.data)
{}
Hope this helps.
Thanks,
Prathap
On Mon, Jul 20, 2015 at 6:09 PM, Davesh Shingari shingaridav...@gmail.com
wrote:
Polydoros Petrakis polpetras at gmail.com writes:
Maybe you can check the physical memory range allocated for each
process and track requests depending on the access address. (Check which
range it belongs to)
On 31 March 2015 at 00:30, Prathap Kolakkampadath kvprathap at
gmail.com wrote:
Hello Andreas,
I am trying to collect the per request memory access latency of a
specific linux process Read requests. I am running two memory intensive
linux processes in a single core.
In my understanding, the Thread id/Context id, Master id are the same
for the two process memory requests running in the same core. So I won't
be able to differentiate the requests of one process from the other
using that. Is it possible to differentiate the memory requests at DRAM
Controller layer based on linux process id?
Thanks,
Prathap
On Mon, Mar 30, 2015 at 12:35 PM, Andreas Hansson Andreas.Hansson
at arm.com wrote:
Hi Prathap,
Could you be a bit more specific about what you mean by “tracking
requests”. Each request that originates in the CPU has an ASID and
ThreadID associated with it, as well as a MasterID. You should be able
to access these at the DRAM controller if that’s
what you’re after. Note that you end up getting requests without this
information (write backs etc), so you cannot always rely on it.
Andreas
From: Prathap Kolakkampadath kvprathap at gmail.comReply-To: gem5
users mailing list gem5-users at gem5.orgDate: Monday, 30 March 2015
17:27To: gem5 users mailing list gem5-users at gem5.orgSubject:
[gem5-users] Tracking DRAM requests from a process
Hello Users,
I am running Gem5 on ARM FS mode using classic memory system. I am
running two process on a single core. I need to track the DRAM requests
(memory access latency) of a particular process. Is it possible to
identify the process id of a linux process in the DRAM
Controller layer?
Thanks,
Prathap Kumar Valsan
-- IMPORTANT NOTICE: The contents of this email and any attachments
are confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents
to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1
9NJ, Registered in England Wales, Company No: 2548782
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Hi
Did you find a way to know the core where the memory request originated?
If I use function to get threadId or asid, I get following error:
gem5.opt: build/ARM/mem/request.hh:533: int Request::getAsid() const:
Assertion `privateFlags.isSet(VALID_VADDR)' failed.
And for masterId, the number changes with simulation (I think it is
generated statically).
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--
Have a great day!
Thanks and Warm Regards
Davesh Shingari
Master's in Computer Engineering [EE]
Arizona State University
davesh.shing...@asu.edu
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Re: [gem5-users] Tracking DRAM requests from a process
Polydoros Petrakis polpetras at gmail.com writes: Maybe you can check the physical memory range allocated for each process and track requests depending on the access address. (Check which range it belongs to) On 31 March 2015 at 00:30, Prathap Kolakkampadath kvprathap at gmail.com wrote: Hello Andreas, I am trying to collect the per request memory access latency of a specific linux process Read requests. I am running two memory intensive linux processes in a single core. In my understanding, the Thread id/Context id, Master id are the same for the two process memory requests running in the same core. So I won't be able to differentiate the requests of one process from the other using that. Is it possible to differentiate the memory requests at DRAM Controller layer based on linux process id? Thanks, Prathap On Mon, Mar 30, 2015 at 12:35 PM, Andreas Hansson Andreas.Hansson at arm.com wrote: Hi Prathap, Could you be a bit more specific about what you mean by “tracking requests”. Each request that originates in the CPU has an ASID and ThreadID associated with it, as well as a MasterID. You should be able to access these at the DRAM controller if that’s what you’re after. Note that you end up getting requests without this information (write backs etc), so you cannot always rely on it. Andreas From: Prathap Kolakkampadath kvprathap at gmail.comReply-To: gem5 users mailing list gem5-users at gem5.orgDate: Monday, 30 March 2015 17:27To: gem5 users mailing list gem5-users at gem5.orgSubject: [gem5-users] Tracking DRAM requests from a process Hello Users, I am running Gem5 on ARM FS mode using classic memory system. I am running two process on a single core. I need to track the DRAM requests (memory access latency) of a particular process. Is it possible to identify the process id of a linux process in the DRAM Controller layer? Thanks, Prathap Kumar Valsan -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing listgem5-users at gem5.orghttp://m5sim.org/cgi- bin/mailman/listinfo/gem5-users ___ gem5-users mailing listgem5-users at gem5.orghttp://m5sim.org/cgi- bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users at gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users Hi Did you find a way to know the core where the memory request originated? If I use function to get threadId or asid, I get following error: gem5.opt: build/ARM/mem/request.hh:533: int Request::getAsid() const: Assertion `privateFlags.isSet(VALID_VADDR)' failed. And for masterId, the number changes with simulation (I think it is generated statically). ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] MSHR Queue Full Handling
Hi Andreas Thanks a lot for pointer. I have been experimenting with your suggestion. I have few questions. *Question 1:* In configs/common/Caches.py. configuration is done as follows: class L1Cache(BaseCache): assoc = 2 hit_latency = 2 response_latency = 2 mshrs = 4 tgts_per_mshr = 20 is_top_level = True But when I print the values of variables used in isFull function (in src/mem/cache/mshr_queue.hh) , I see following 16338315506500: system.cpu0.icache: Packet: MasterId=cpu0.inst 16338315506500: global: Number of allocated 1 16338315506500: global: Number of numEntries 8 16338315506500: global: Number of numReserve 4 16338316046500: system.cpu0.dcache: Packet: MasterId=switch_cpus0.data 16338316046500: global: Number of allocated 1 16338316046500: global: Number of numEntries 9 16338316046500: global: Number of numReserve 4 How come these values are different from those values? Am I looking at wrong place? *Question 2:* As per your suggestion, I am trying to configure the MSHR per core in configuration file itself. The fs.py import from CacheConfig.py: for i in xrange(options.num_cpus): if options.caches: print i icache = icache_class(size=options.l1i_size, assoc=options.l1i_assoc, mshrs=5) dcache = dcache_class(size=options.l1d_size, assoc=options.l1d_assoc) So configuring mshrs over here will overwrite other values. Is this the correct place or were you referring to some other place? ᐧ On Thu, Jul 16, 2015 at 4:03 AM, Andreas Hansson andreas.hans...@arm.com wrote: Hi all, The best way to customise your L1 instances is in the config script itself. If you use fs.py, I’d suggest to do it there. Andreas From: gem5-users gem5-users-boun...@gem5.org on behalf of Prathap Kolakkampadath kvprat...@gmail.com Reply-To: gem5 users mailing list gem5-users@gem5.org Date: Thursday, 16 July 2015 00:00 To: gem5 users mailing list gem5-users@gem5.org Subject: Re: [gem5-users] MSHR Queue Full Handling Hello Davesh, I think it should be possible by passing the desired L1 MSHR setting for each core, while instantiating the dcache in CacheConfig.py Also look at the BaseCache constructor, to see how these parameters are being set. Thanks, Prathap -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Have a great day! Thanks and Warm Regards Davesh Shingari Master's in Computer Engineering [EE] Arizona State University davesh.shing...@asu.edu ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Getting error while simulating multi level cache for ARM FS simulation
Does anyone has some idea about this? I am stuck here for quite a while. Regards Rahul On Mon, Jul 20, 2015 at 6:35 PM, rahul shrivastava rshrivasta...@gmail.com wrote: Hi, I am using the following command to test multi level caches for ARM FS simulation M5_PATH=$(pwd)/.. ./build/ARM/gem5.fast configs/example/fs.py --script=./auto_scripts --cpu-type=DerivO3CPU -n 4* --caches --l1d_size=32kB --l1i_size=32kB --l2cache --l2_size=256kB --l3_size=20480kB* --machine-type=VExpress_EMM --kernel=../linux-linaro-tracking-gem5/vmlinux --dtb-filename=../linux-linaro-tracking-gem5/arch/arm/boot/dts/vexpress-v2p-ca15-tc1-gem5_dvfs_per_core_4cpus.dtb --disk-image=../disks/arm-ubuntu-natty-headless.img --cpu-clock=\['1 GHz','750 MHz','500 MHz'\] But it throws a following exception. Could you please let me know if I am missing some option? *TRACEBACK* File string, line 1, in module File /home/rahuls/gem5-stable-0e86fac7254c/gem5/src/python/m5/main.py, line 388, in main exec filecode in scope File configs/example/fs.py, line 335, in module test_sys = build_test_system(np) File configs/example/fs.py, line 231, in build_test_system CacheConfig.config_cache(options, test_sys) File /home/rahuls/gem5-stable-0e86fac7254c/gem5/configs/common/CacheConfig.py, line 72, in config_cache assoc=options.l2_assoc) File /home/rahuls/gem5-stable-0e86fac7254c/gem5/src/python/m5/SimObject.py, line 1044, in __init__ setattr(self, key, val) File /home/rahuls/gem5-stable-0e86fac7254c/gem5/src/python/m5/SimObject.py, line 1122, in __setattr__ value = param.convert(value) File /home/rahuls/gem5-stable-0e86fac7254c/gem5/src/python/m5/params.py, line 212, in convert return self.ptype(value) TypeError: __init__() takes exactly 1 argument (2 given) Error setting param L2Cache.clk_domain to [m5.objects.ClockDomain.SrcClockDomain object at 0x7f2b106ed1d0, m5.objects.ClockDomain.SrcClockDomain object at 0x7f2b106ed310, m5.objects.ClockDomain.SrcClockDomain object at 0x7f2b106ed4d0, m5.objects.ClockDomain.SrcClockDomain object at 0x7f2b106ed690] Regards Rahul ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Getting error while simulating multi level cache for ARM FS simulation
Hi I would suggest you to look at previous posts. Some of the related ones are: http://comments.gmane.org/gmane.comp.emulators.m5.users/16590 https://www.mail-archive.com/gem5-users@gem5.org/msg02781.html https://www.mail-archive.com/gem5-users@gem5.org/msg08121.html ᐧ On Mon, Jul 20, 2015 at 10:03 PM, rahul shrivastava rshrivasta...@gmail.com wrote: Does anyone has some idea about this? I am stuck here for quite a while. Regards Rahul On Mon, Jul 20, 2015 at 6:35 PM, rahul shrivastava rshrivasta...@gmail.com wrote: Hi, I am using the following command to test multi level caches for ARM FS simulation M5_PATH=$(pwd)/.. ./build/ARM/gem5.fast configs/example/fs.py --script=./auto_scripts --cpu-type=DerivO3CPU -n 4* --caches --l1d_size=32kB --l1i_size=32kB --l2cache --l2_size=256kB --l3_size=20480kB* --machine-type=VExpress_EMM --kernel=../linux-linaro-tracking-gem5/vmlinux --dtb-filename=../linux-linaro-tracking-gem5/arch/arm/boot/dts/vexpress-v2p-ca15-tc1-gem5_dvfs_per_core_4cpus.dtb --disk-image=../disks/arm-ubuntu-natty-headless.img --cpu-clock=\['1 GHz','750 MHz','500 MHz'\] But it throws a following exception. Could you please let me know if I am missing some option? *TRACEBACK* File string, line 1, in module File /home/rahuls/gem5-stable-0e86fac7254c/gem5/src/python/m5/main.py, line 388, in main exec filecode in scope File configs/example/fs.py, line 335, in module test_sys = build_test_system(np) File configs/example/fs.py, line 231, in build_test_system CacheConfig.config_cache(options, test_sys) File /home/rahuls/gem5-stable-0e86fac7254c/gem5/configs/common/CacheConfig.py, line 72, in config_cache assoc=options.l2_assoc) File /home/rahuls/gem5-stable-0e86fac7254c/gem5/src/python/m5/SimObject.py, line 1044, in __init__ setattr(self, key, val) File /home/rahuls/gem5-stable-0e86fac7254c/gem5/src/python/m5/SimObject.py, line 1122, in __setattr__ value = param.convert(value) File /home/rahuls/gem5-stable-0e86fac7254c/gem5/src/python/m5/params.py, line 212, in convert return self.ptype(value) TypeError: __init__() takes exactly 1 argument (2 given) Error setting param L2Cache.clk_domain to [m5.objects.ClockDomain.SrcClockDomain object at 0x7f2b106ed1d0, m5.objects.ClockDomain.SrcClockDomain object at 0x7f2b106ed310, m5.objects.ClockDomain.SrcClockDomain object at 0x7f2b106ed4d0, m5.objects.ClockDomain.SrcClockDomain object at 0x7f2b106ed690] Regards Rahul ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Have a great day! Thanks and Warm Regards Davesh Shingari Master's in Computer Engineering [EE] Arizona State University davesh.shing...@asu.edu ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
