Re: [gem5-users] Error in the process of running SPEC CPU2006 Benchmarks in the gem5 Simulator
Hi, As far as I remember, not all spec benchmarks run in the SE mode since it is probable that there exist unimplemented instructions. You can try other things such as bzip2, libquantum, ... Another less useful trick is to skip that instruction. However, if that instruction repeats so many times in the binary file, then you should think about something else. Regards, Mahmood On Wed, Jul 19, 2017 at 3:20 PM, Zeynab Mohseni wrote: > Dear Sir/Madam, > > As I am beginner and unfortunately I did not found a complete tutorial > about running SPEC benchmark in gem5 simulator in your web page, I followed > the tutorial in (https://markgottscho.wordpress.com/2014/09/20/ > tutorial-easily-running-spec-cpu2006-benchmarks-in-the- > gem5-simulator/comment-page-1/#comment-184) web page. I am using the > RISCV version of gem5, but before this, I tested the " > ./run_gem5_alpha_spec06_benchmark.sh perlbench > /home/ubuntu/GEM5_ALPHA/gem5/output_dir" command for ALPHA microprocessor > and I had the same error. after running the below command in the terminal, > there is an error related to instruction (panic: Unknown instruction > 0xa5378082 at pc 0x00010fa4). > > > ~/GEM5_RISCV/gem5$ ./run_gem5_riscv_spec06_benchmark.sh perlbench > /home/ubuntu/GEM5_RISCV/gem5/output_dir > > > As follow you can find the result of running the addressed command for > RISCV version of gem5. It should be note that the perlbech.out, > perlbench.err and the stats.txt which are created after running the command > are empty. > > > I look froward to hearing from you. > > Sincerely, > Artemis > > ~/GEM5_RISCV/gem5$ ./run_gem5_riscv_spec06_benchmark.sh perlbench > /home/ubuntu/GEM5_RISCV/gem5/output_dir > Command line: > ./run_gem5_riscv_spec06_benchmark.sh perlbench > /home/ubuntu/GEM5_RISCV/gem5/output_dir > = Hardcoded directories == > GEM5_DIR: /home/ubuntu/GEM5_RISCV/gem5 > SPEC_DIR: /home/ubuntu/cpu2006 > Script inputs === > BENCHMARK:perlbench > OUTPUT_DIR: > /home/ubuntu/GEM5_RISCV/gem5/output_dir > == > > Changing to SPEC benchmark runtime directory: /home/ubuntu/cpu2006/ > benchspec/CPU2006/400.perlbench/run/run_base_ref_riscv. > > > - Here goes nothing! Starting gem5! > > > warn: DRAM device capacity (8192 Mbytes) does not match the address range > assigned (512 Mbytes) > gem5 Simulator System. http://gem5.org > gem5 is copyrighted software; use the --copyright option for details. > > gem5 compiled Jul 17 2017 16:51:43 > gem5 started Jul 19 2017 12:00:55 > gem5 executing on ubuntu-VirtualBox, pid 7547 > command line: /home/ubuntu/GEM5_RISCV/gem5/build/RISCV/gem5.opt > --outdir=/home/ubuntu/GEM5_RISCV/gem5/output_dir > /home/ubuntu/GEM5_RISCV/gem5/configs/example/spec06_config.py > --benchmark=perlbench --benchmark_stdout=/home/ > ubuntu/GEM5_RISCV/gem5/output_dir/perlbench.out --benchmark_stderr=/home/ > ubuntu/GEM5_RISCV/gem5/output_dir/perlbench.err > > Selected SPEC_CPU2006 benchmark > --> perlbench > Process stdout file: /home/ubuntu/GEM5_RISCV/gem5/output_dir/perlbench.out > Process stderr file: /home/ubuntu/GEM5_RISCV/gem5/output_dir/perlbench.err > ['/home/ubuntu/cpu2006/benchspec/CPU2006/400.perlbench/run/run_base_ref_ > riscv./perlbench_base.riscv', '-I./lib', 'checkspam.pl', '2500', '5', > '25', '11', '150', '1', '1', '1', '1'] > Global frequency set at 1 ticks per second > 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 > info: Entering event queue @ 0. Starting simulation... > REAL SIMULATION > panic: Unknown instruction 0xa5378082 at pc 0x00010fa4 > Memory Usage: 636556 KBytes > Program aborted at tick 1500 > --- BEGIN LIBC BACKTRACE --- > /home/ubuntu/GEM5_RISCV/gem5/build/RISCV/gem5.opt(_ > Z15print_backtracev+0x28)[0x1040588] > /home/ubuntu/GEM5_RISCV/gem5/build/RISCV/gem5.opt(_Z12abortHandleri+0x46)[ > 0x1054586] > /lib/x86_64-linux-gnu/libpthread.so.0(+0x11390)[0x7f71fe6e3390] > /lib/x86_64-linux-gnu/libc.so.6(gsignal+0x38)[0x7f71fd0eb428] > /lib/x86_64-linux-gnu/libc.so.6(abort+0x16a)[0x7f71fd0ed02a] > /home/ubuntu/GEM5_RISCV/gem5/build/RISCV/gem5.opt(_ > ZN8RiscvISA16UnknownInstFault9invoke_seEP13ThreadContextRK14RefCoun > tingPtrI10StaticInstE+0x1a8)[0xcaba68] > /home/ubuntu/GEM5_RISCV/gem5/build/RISCV/gem5.opt(_ > ZN8RiscvISA10RiscvFault6invokeEP13ThreadContextRK14RefCounti > ngPtrI10StaticInstE+0x30)[0xcab7c0] > /home/ubuntu/GEM5_RISCV/gem5/build/RISCV/gem5.opt(_ > ZN13BaseSimpleCPU9advancePCERKSt10shared_ptrI9FaultBaseE+0xd9)[0xf021d9] > /home/ubuntu/GEM5_RISCV/gem5/build/RISCV/gem5.opt(_ > ZN15AtomicSimpleCPU4tickEv+0x448)[0xef9a38] > /home/ubuntu/GEM5_RISCV/gem5/build/RISCV/gem5.opt(_ > ZN10EventQueue10serviceOneEv+0x11d)[0x10471cd] > /home/ubuntu/GEM5_RISCV/gem5/build/RISCV/gem5.opt
Re: [gem5-users] add parameter in params
The idea is to add some params in .py file and then bind their names to the variables in the implementation file of of the class (foo.cc). I think you missed that step. Have a look at the constructor and add yours similar to the existing params. At least this is the way that we did. I don't know if that procedure has been changed in newer versions. Regards, Mahmood On Tue, Jul 11, 2017 at 11:01 PM, raziye deylamsalehi < raziye.deylamsal...@gmail.com> wrote: > Hi Mahmood > > Thank you for answering. for example I want to add parameter to > src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh. > GarnetNetworkInterface > class is in GarnetNetwork.py file. I added new parameter in .py file and > recompile but it said: > error: 'const Params' has no member named 'num_vcs' > I didn't add this parameter to build/x86/params/GarnetNetworkInterface.hh > for previous run. > then I added parameter to build/x86/params/GarnetNetworkInterface.hh and > recompiled again and it had no compile error. > then I give input in configs/ruby/Ruby.py but when I simulate my 8*8 > network it has this error: > > system.ruby.network.netifs000.num_vcs without default or user set value > > On Tue, Jul 11, 2017 at 7:37 PM, Mahmood Naderan > wrote: > >> Hi, >> You have to edit the .py file in the src/ and then recompile. For >> example, have a look at src/mem/cache/BaseCache.py and add your *cache* >> related params there and the recompile. The same can be applied to other >> components. >> >> Regards, >> Mahmood >> >> >> >> On Tue, Jul 11, 2017 at 7:31 PM, raziye deylamsalehi < >> raziye.deylamsal...@gmail.com> wrote: >> >>> Hi >>> >>> I want to add parameter in const params of class. I go to this >>> path build/x86/params and insert parameter there. that is correct? >>> >>> Thanks >>> >>> ___ >>> gem5-users mailing list >>> gem5-users@gem5.org >>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>> >> >> >> ___ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] add parameter in params
Hi, You have to edit the .py file in the src/ and then recompile. For example, have a look at src/mem/cache/BaseCache.py and add your *cache* related params there and the recompile. The same can be applied to other components. Regards, Mahmood On Tue, Jul 11, 2017 at 7:31 PM, raziye deylamsalehi < raziye.deylamsal...@gmail.com> wrote: > Hi > > I want to add parameter in const params of class. I go to this > path build/x86/params and insert parameter there. that is correct? > > Thanks > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] SimPoint with gem5
Hi, Have you read http://gem5.org/Simpoints ? Regards, Mahmood On Wed, Jul 5, 2017 at 4:00 PM, Mukherjee, Somnath wrote: > Friends, > > A rather short message – wanted to know if anyone has used SimPoint with > gem5? J > > https://www.spec.org/cpu2006/research/simpoint.html > > > > If yes, can you share any links, documents, code snippets etc.? > > > > Regards, > > Somnath Mukherjee > > Bangalore > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Error using runspec in SPEC2006 Benchmarks
Hi, Although it is not related to gem5, i recommecd you to directly go to the src folder of each benchmark and build that. Regards, Mahmood On 2 Feb 2017 22:57, "Muzamil Rafique" wrote: Hi All, I am trying to use runspec in an effort to compile and run SPEC2006 benchmarks and getting following erroe: */cpu2006$ runspec --config=example-simple.cfg --action=build --tune=base bzip2 -I* runspec v4662 - Copyright 1999-2006 Standard Performance Evaluation Corporation Using 'linux-suse101-AMD64' tools Reading MANIFEST... 17856 files Loading runspec modules... Locating benchmarks...found 31 benchmarks in 12 benchsets. Locating output formats: ASCII, config, CSV, flags, HTML, mail, PDF, PostScript, raw, Screen, Submission Check Reading config file '/home/*/cpu2006/config/example-simple.cfg' Benchmarks selected: 401.bzip2 Compiling Binaries Building 401.bzip2 ref base compsys default: (build_base_compsys.) Error with make 'specmake build': check file '/home/muhammad/cpu2006/ benchspec/CPU2006/401.bzip2/run/build_base_compsys./make.err' *Error with make!*** Error building 401.bzip2Build errors: 401.bzip2(base)Build CompleteThe log for this run is in /cpu2006/result/CPU2006.008.log* runspec finished at Thu Feb 2 13:13:55 2017; 36 total seconds elapsed Please help to fix this error!!! Thanks Muzamil ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] IDE For Gem5
Hi, What do you mean by Gem5 itself? it is c++ code which you can debug it like other codes. Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Error on gem5.debug but no error on gem5.fast
OK it seems I have to setup that. I thought the ICS bbench is a good place for tests. Lets move on then... Regards, Mahmood On Mon, Dec 28, 2015 at 7:28 PM, Andreas Hansson wrote: > Hi, > > gem5.fast does not have any assertions. > > As I already mentioned, I’d suggest to forget all about ICS and instead > follow the instructions here: http://www.gem5.org/Android_KitKat and > here: http://www.gem5.org/WA-gem5. > > That enables you to run a wide range of workloads, using Workload > Automation on Android KitKat. > > Andreas > > From: gem5-users on behalf of Mahmood > Naderan > Reply-To: gem5 users mailing list > Date: Monday, 28 December 2015 at 08:43 > To: gem5 users mailing list > Subject: [gem5-users] Error on gem5.debug but no error on gem5.fast > > Hi, > If I run bbench with gem5.debug, I immediately get an error in the code > however, gem5.fast doesn't fail at that point. In fact it will fail after > so many ticks. > > A bit strange... Any idea on that? I haven't modified the code yet. > > > gem5.debug > > warn: DTB file specified, but no device tree support in kernel > REAL SIMULATION > warn: Existing EnergyCtrl, but no enabled DVFSHandler found. > info: Entering event queue @ 0. Starting simulation... > warn: Device system.membus.badaddr_responder accessed by read to address > 0x10009018 size=4 > gem5.debug: build/ARM/cpu/simple/atomic.cc:378: virtual Fault > AtomicSimpleCPU::readMem(Addr, uint8_t*, unsigned int, unsigned int): > Assertion `!pkt.isError()' failed. > Program aborted at tick 3 > --- BEGIN LIBC BACKTRACE --- > build/ARM/gem5.debug(_Z15print_backtracev+0x23)[0x116b887] > build/ARM/gem5.debug(_Z12abortHandleri+0x5f)[0x1181581] > /lib/x86_64-linux-gnu/libpthread.so.0(+0xfcb0)[0x7f378047fcb0] > /lib/x86_64-linux-gnu/libc.so.6(gsignal+0x35)[0x7f377efac0d5] > /lib/x86_64-linux-gnu/libc.so.6(abort+0x17b)[0x7f377efaf83b] > /lib/x86_64-linux-gnu/libc.so.6(+0x2ed9e)[0x7f377efa4d9e] > /lib/x86_64-linux-gnu/libc.so.6(+0x2ee42)[0x7f377efa4e42] > build/ARM/gem5.debug(_ZN15AtomicSimpleCPU7readMemEmPhjj+0x449)[0x1509433] > build/ARM/gem5.debug(_ZN17SimpleExecContext7readMemEmPhjj+0x52)[0x1516e4e] > > build/ARM/gem5.debug(_Z13readMemTimingI11ExecContextjESt10shared_ptrI9FaultBaseEPT_PN5Trace10InstRecordEmRT0_j+0x4d)[0x222469b] > > build/ARM/gem5.debug(_Z13readMemAtomicI11ExecContextjESt10shared_ptrI9FaultBaseEPT_PN5Trace10InstRecordEmRT0_j+0x5d)[0x2224525] > > build/ARM/gem5.debug(_ZNK10ArmISAInst27LOAD_IMM_AY_PN_SN_UN_WN_SZ47executeEP11ExecContextPN5Trace10InstRecordE+0x1da)[0x21846ca] > build/ARM/gem5.debug(_ZN15AtomicSimpleCPU4tickEv+0x5c8)[0x150a41a] > > > > > > > > But gem5.fast passes that tick number. The command I use is: > > build/ARM/gem5.fast configs/example/fs.py -b bbench-ics > --kernel=vmlinux.smp.mouse.arm --frame-capture > > build/ARM/gem5.debugconfigs/example/fs.py -b bbench-ics > --kernel=vmlinux.smp.mouse.arm --frame-capture > > > Regards, > Mahmood > > > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Error on gem5.debug but no error on gem5.fast
Hi, If I run bbench with gem5.debug, I immediately get an error in the code however, gem5.fast doesn't fail at that point. In fact it will fail after so many ticks. A bit strange... Any idea on that? I haven't modified the code yet. gem5.debug warn: DTB file specified, but no device tree support in kernel REAL SIMULATION warn: Existing EnergyCtrl, but no enabled DVFSHandler found. info: Entering event queue @ 0. Starting simulation... warn: Device system.membus.badaddr_responder accessed by read to address 0x10009018 size=4 gem5.debug: build/ARM/cpu/simple/atomic.cc:378: virtual Fault AtomicSimpleCPU::readMem(Addr, uint8_t*, unsigned int, unsigned int): Assertion `!pkt.isError()' failed. Program aborted at tick 3 --- BEGIN LIBC BACKTRACE --- build/ARM/gem5.debug(_Z15print_backtracev+0x23)[0x116b887] build/ARM/gem5.debug(_Z12abortHandleri+0x5f)[0x1181581] /lib/x86_64-linux-gnu/libpthread.so.0(+0xfcb0)[0x7f378047fcb0] /lib/x86_64-linux-gnu/libc.so.6(gsignal+0x35)[0x7f377efac0d5] /lib/x86_64-linux-gnu/libc.so.6(abort+0x17b)[0x7f377efaf83b] /lib/x86_64-linux-gnu/libc.so.6(+0x2ed9e)[0x7f377efa4d9e] /lib/x86_64-linux-gnu/libc.so.6(+0x2ee42)[0x7f377efa4e42] build/ARM/gem5.debug(_ZN15AtomicSimpleCPU7readMemEmPhjj+0x449)[0x1509433] build/ARM/gem5.debug(_ZN17SimpleExecContext7readMemEmPhjj+0x52)[0x1516e4e] build/ARM/gem5.debug(_Z13readMemTimingI11ExecContextjESt10shared_ptrI9FaultBaseEPT_PN5Trace10InstRecordEmRT0_j+0x4d)[0x222469b] build/ARM/gem5.debug(_Z13readMemAtomicI11ExecContextjESt10shared_ptrI9FaultBaseEPT_PN5Trace10InstRecordEmRT0_j+0x5d)[0x2224525] build/ARM/gem5.debug(_ZNK10ArmISAInst27LOAD_IMM_AY_PN_SN_UN_WN_SZ47executeEP11ExecContextPN5Trace10InstRecordE+0x1da)[0x21846ca] build/ARM/gem5.debug(_ZN15AtomicSimpleCPU4tickEv+0x5c8)[0x150a41a] But gem5.fast passes that tick number. The command I use is: build/ARM/gem5.fast configs/example/fs.py -b bbench-ics --kernel=vmlinux.smp.mouse.arm --frame-capture build/ARM/gem5.debugconfigs/example/fs.py -b bbench-ics --kernel=vmlinux.smp.mouse.arm --frame-capture Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Yet another question on BBench
OK I think I got what you said. However, I have to say that after about two hours, the simulation aborted with a panic related to VNC. I have to say I didn't attach any vncviewer since the job was running in the background yesterday night. Have you seen that before? Global frequency set at 1 ticks per second warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) info: kernel located at: /home/mahmood/gem5/system/binaries/vmlinux.smp.mouse.arm Listening for system connection on port 5900 Listening for system connection on port 3456 0: system.remote_gdb.listener: listening for remote gdb on port 7000 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 warn: DTB file specified, but no device tree support in kernel REAL SIMULATION warn: Existing EnergyCtrl, but no enabled DVFSHandler found. info: Entering event queue @ 0. Starting simulation... warn: Device system.membus.badaddr_responder accessed by write to address 0x10009000 size=1 data=0xa warn: Device system.membus.badaddr_responder accessed by read to address 0x10009018 size=4 warn: Device system.membus.badaddr_responder accessed by read to address 0x10009018 size=4 warn: Device system.membus.badaddr_responder accessed by write to address 0x10009000 size=1 data=0xd warn: Device system.membus.badaddr_responder accessed by read to address 0x10009018 size=4 info: VNC client attached warn: Malformed protocol version GET / HTTP/1 info: VNC client detached warn: Unsupported VNC client version... disconnecting panic: Vnc client not properly attached. @ tick 13301657326000 [write:build/ARM/base/vnc/vncserver.cc, line 331] Memory Usage: 531056 KBytes Program aborted at tick 13301657326000 --- BEGIN LIBC BACKTRACE --- build/ARM/gem5.fast(_Z15print_backtracev+0x1f)[0x11b2f2f] build/ARM/gem5.fast(_Z12abortHandleri+0x34)[0x11b3054] /lib/x86_64-linux-gnu/libpthread.so.0(+0xfcb0)[0x7f5a188e4cb0] /lib/x86_64-linux-gnu/libc.so.6(gsignal+0x35)[0x7f5a174110d5] /lib/x86_64-linux-gnu/libc.so.6(abort+0x17b)[0x7f5a1741483b] build/ARM/gem5.fast(_Z15__exit_epilogueiPKcS0_iS0_+0x2aa)[0x1319eda] build/ARM/gem5.fast(_Z22MachineType_base_countRK11MachineType+0x0)[0x1335e70] build/ARM/gem5.fast[0xa1ee20] build/ARM/gem5.fast[0x1769aff] build/ARM/gem5.fast(_ZN9VncServer9DataEvent7processEi+0x154)[0x176b174] build/ARM/gem5.fast(_Z9doSimLoopP10EventQueue+0x220)[0xf876d0] build/ARM/gem5.fast(_Z8simulatem+0x23f)[0x1612f6f] build/ARM/gem5.fast[0x1613d65] /usr/lib/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x4f18)[0x7f5a184693b8] Regards, Mahmood On Sun, Dec 27, 2015 at 6:02 AM, Davesh Shingari wrote: > Hi > > Which script are you using - bbench-ics.rcS? > You can see whether the checkpoint was created by checking the cpt created > and looking at the frame output to know whether bbench has started or not. > If you are using bbench-ics then it automatically creates a checkpoint and > then starts the bbench. So best way is to start the simulation in atomic > mode and then after checkpoint is created run the simulation in detailed > mode using the checkpoint created, if this is what you are looking for. > ᐧ > -- > Have a great day! > > Thanks and Warm Regards > Davesh Shingari > Master's in Computer Engineering [EE] > Arizona State University > > davesh.shing...@asu.edu > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Yet another question on BBench
Hi, For the BBench, how can I be sure that the android is booted up in order to create a checkpoint? Also, how does it work? I mean does it automatically run the benchmark after the boot? Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] problem attaching vncviewer
Hi, As I run the bbench, the simulation window shows nothing. On another terminal running vncviewer, I get this error: mahmood@orca:~$ vncviewer 127.0.0.1:5900 Connected to RFB server, using protocol version 3.8 No authentication needed Authentication successful Desktop name "M5" VNC server default format: 32 bits per pixel. Least significant byte first in each pixel. True colour: max red 255 green 255 blue 255, shift red 16 green 8 blue 0 Using default colormap which is TrueColor. Pixel format: 32 bits per pixel. Least significant byte first in each pixel. True colour: max red 255 green 255 blue 255, shift red 16 green 8 blue 0 CleanupXtErrorHandler called Error: Shell widget vncviewer has zero width and/or height As you can see, desktop name is "M5" and is identified. In the other window, the gem5 simulation is running. Has anyone faced such an issue? Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] where to obtain 'vmlinux.aarch32.ll_20131205.0-gem5'?
Thanks. Found it... Regards, Mahmood On Thu, Dec 24, 2015 at 7:35 PM, Paul Rosenfeld (prosenfeld) < prosenf...@micron.com> wrote: > It should be in the ARM full system files: > http://www.gem5.org/dist/current/arm/aarch-system-2014-10.tar.xz > > > > tar --list -f aarch-system-2014-10.tar | grep aarch32 > > binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb > > *binaries/vmlinux.aarch32.ll_20131205.0-gem5* > > binaries/vexpress.aarch32.ll_20131205.0-gem5.4cpu.dtb > > binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb > > > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] where to obtain 'vmlinux.aarch32.ll_20131205.0-gem5'?
Hi, After some years, now getting back to gem5 for a test! I followed the instructions on how to run bbench, however got an error that relates to a missing file What is 'vmlinux.aarch32.ll_20131205.0-gem5' and where can I obtain that? seems that a step is missing in the manual. mahmood@orca:gem5$ echo $M5_PATH /home/mahmood/gem5/system/ mahmood@orca:gem5$ ls system/disks/ ARMv7a-ICS-Android.SMP.nolock.img mahmood@orca:gem5$ ls system/binaries/ android.m5.pbx.smp.mouse.config vmlinux.smp.mouse.arm mahmood@orca:gem5$ build/ARM/gem5.fast configs/example/fs.py -b bbench-ics --kernel=vmlinux.smp.mouse.arm --frame-capture Couldn't import dot_parser, loading of dot files will not be possible. gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. gem5 compiled Dec 24 2015 17:10:34 gem5 started Dec 24 2015 18:39:19 gem5 executing on orca, pid 5626 command line: build/ARM/gem5.fast configs/example/fs.py -b bbench-ics --kernel=vmlinux.smp.mouse.arm --frame-capture Traceback (most recent call last): File "", line 1, in File "/home/mahmood/gem5/src/python/m5/main.py", line 389, in main exec filecode in scope File "configs/example/fs.py", line 339, in test_sys = build_test_system(np) File "configs/example/fs.py", line 102, in build_test_system external_memory=options.external_memory_system) File "/home/mahmood/gem5/configs/common/FSConfig.py", line 294, in makeArmSystem self.kernel = binary(default_kernels[machine_type]) File "/home/mahmood/gem5/configs/common/SysPaths.py", line 49, in binary return searchpath(binary.path, filename) File "/home/mahmood/gem5/configs/common/SysPaths.py", line 41, in searchpath raise IOError, "Can't find file '%s' on path." % filename IOError: Can't find file 'vmlinux.aarch32.ll_20131205.0-gem5' on path. Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] List of SPEC 2000 runnable benchmarks on gem5
The instructions are available at http://www.m5sim.org/SPEC2000_benchmarks On 3/10/15, Vanchinathan Venkataramani wrote: > Hi Andreas > > I can find the list of SPEC2006 benchmarks that can successfully run on > gem5 from the following link: > > http://www.m5sim.org/SPEC_CPU2006_benchmarks > > I would like to know if I can find similar details for SPEC2000 benchmarks > also. > > Thanks > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] mshr miss rate
Hi What does "mshr miss rate" mean? Let's say MSHR contains [A B C D] and these are the misses waiting for service. Now assume, cpu requests B. This is called MSHR hit. If cpu requests E, then that is called MHSR miss. How MSHR_miss_rate is then calculated. Is that 1/(1+1)? Shouldn't we consider number of pending request in the MSHR queue? -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Why CPI is so big
>I get the CPI by dividing sim_insts(m5out/stats.txt) >from sim_ticks and the result is 9411 CPI has a dedicated stat name. Check that. >what are the default configs for cacheline size See Options.py On 4/26/14, luming wrote: > Dear gem5 users, > > I'm new to gem5 and I ran SPEC2006 to get some simulation results. > However, I found the CPI was so big and I'm wondering whether I > misunderstood something in the output. For example, I ran 410.bwaves > with > > ./build/X86/gem5.fast ./configs/example/se.py --ruby -c > ../spec2006/benchspec/CPU2006/410.bwaves/exe/bwaves_base.amd64-m64-gcc42-nn > > -o ../spec2006/benchspec/CPU2006/410.bwaves/data/test/input/bwaves.in > > and I get the CPI by dividing sim_insts(m5out/stats.txt) from sim_ticks > and the result is 9411. Similar situation applies to the other > benchmarks. Does sim_ticks mean number of cycles simulated? If so, why > the CPI is so big? > > And I'm new to python, what are the default configs for cacheline size > (or CPU model) if i didn't provide it in command? I checked > ./configs/example/se.py but failed to figure out. Is it defined in those > C++ source files of gem5? > > Any clarification is appreciated. Thanks in advance! > > Best regards, > > Luming > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Prefetcher / Cache Address
If there is a way to view the data of a particular address prior to its actual request, then what does prefetching mean here? With prefetching, you generate an address and issue later to bring the data. On 4/19/14, anonymous wrote: > Fernando Endo gmail.com> writes: > >> >> >> Hello, >> I'm not familiar with the prefetcher codes, > but there is a stride prefetcher implemented in gem5. > The code there may help. >> >> Regards, >> >> >> --Fernando A. Endo, PhD student > and researcherUniversité de Grenoble, UJFFrance >> >> 2014-04-19 1:04 GMT+02:00 anonymous gmail.com>: >> Hi, >> I am attempting to write a custom Prefetcher. >> However I am having some significant difficulties. >> Particuarlly during the development. >> I have added a new fetcher (right now a copy of Tagged.cc/.hh) >> recompiled gem5 and added it to CacheConfig.py and it links fine >> I can turn on HWPrefetch debug and see a custom message >> I added into the code so add good here. >> My problem is 2 fold. >> First I want to ensure I am printing the request data correctly, >> Addr blkAddr = pkt->getAddr() & ~(Addr)(blkSize-1); >> Addr data_addr = pkt->getAddr(); >> DPRINTF(HWPrefetch, "BlockAddr %x data_addr %x Data: %x %s\n", >> blkAddr, data_addr,*(pkt-> >> getPtr())) >> Secondly if I translate this address say data_addr+8 >> how can I view the data at this location? It >> doesn't seem possible to make sure I am accessing the correct data? >> Any help would be greatly appreciated thank you >> ___ >> gem5-users mailing listgem5-users gem5.orghttp://m5sim.org/cgi- > bin/mailman/listinfo/gem5-users >> >> >> >> >> >> >> ___ >> gem5-users mailing list >> gem5-users gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > Hey thank you very much for the reply. > Yes I have looked through the Stride Prefetcher, > and it is very interesting how they store > the strides in a table. But it doesn't seem > to help with my particular issue since from > what I can tell the Stride are still contiguous blocks. > I am prefetching specific blocks. > > Additionally I have a class member that is being fetched > and I would very much like to be able > to view individual properties of that class > (i.e I would like to be able to check the data > in particular properties to > ensure I'm working on the right items) > > > Any help on accessing or viewing data > in particular properties from within > the prefetcher class would be greatly appreciated > > just as a note, I can't even seem to print out the data in > newAddr from these pre fetchers. It seems the getPtr() > is the only way to get data, and that only points to current data > request. So I can't even work backward from that. > > Thank you again > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] cache stats
Hi What is the logic behind the definition of cache stats? For each stat, a loop is defined that assigns a subname it. -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] gem5 cache latency, impact on performance
That is a normal thing. sim_second is a workload related parameter while simulation execution on the host is related to your host, e.g wall time. Assume you are simulating single core at 2GHz frequency. As a result simulating 1 second of your workload takes 2*10^9 cycles. If you write a good code in gem5, it may takes 10 hours to complete and if you write a bad code by putting sleep() it takes 20 hours to complete. On 4/5/14, Sanem Arslan wrote: > Mahmood, > > I have comfirmed that sleep() function executes. Besides that, > simulation execution on host machine takes longer but execution time > value (sim_seconds) in stat file does not show a significant difference. > Alinti Mahmood Naderan > >> Sanem, >> maybe you put sleep() somewhere in the code that never executes! Can >> you confirm that by breakpoints? >> >> On 4/4/14, Sanem Arslan wrote: >>> Hi all, >>> >>> I am using classic memory system and I have added several codes to >>> the "cache_impl.hh" and "blk.hh" files. However I cannot see the >>> performance overhead of these added codes on the gem5 execution time. >>> I have increased cache latency parameters from "CacheConfig.py" file >>> and I can see the values are updated through out the simulation by >>> looking trace file, but there is no significant impact on execution >>> time (sim_seconds). There is a post >>> (http://thread.gmane.org/gmane.comp.emulators.m5.users/15517/focus=15526) >>> that >>> claims there is no significant impact of increasing latency because of >>> optimizations implemented in the cache protocol in Classic Memory. >>> >>> Moreover I have changed "blk->whenReady" parameter aggresively and I >>> have put some sleep() functions somewhere in cache structures again, >>> but there is no effect on the execution time. >>> >>> How can I observe the performance overhead of my added codes? If you >>> have any suggestions, please let me know. >>> >>> By the way, I am using gem5.opt and X86 with full system mode. >>> >>> Thanks for you time and help. >>> >>> Sanem. >>> ___ >>> gem5-users mailing list >>> gem5-users@gem5.org >>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>> >> >> >> -- >> Regards, >> Mahmood >> ___ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] modeling L3 last level cache in gem5
Prateek,
Don't know what is config.dot.py but with config.dot.pdf you can
easily verify the connections.
On 4/4/14, Prateek Gupta wrote:
> Hello Andreas,
>
>
> Thanks for your reply.
> Do I need to extend fs.py or se.py? I have tried making changes in
> CacheConfig.py, Caches.py and
> Options.py as follows:
>
>
> Options.py: I add this new option
> parser.add_option("--l3cache", action="store_true")
>
>
> Caches.py: I add the L3 cache
> class L1Cache(BaseCache):
> assoc = 8
> hit_latency = 2
> response_latency = 2
> mshrs = 4
> tgts_per_mshr = 20
> is_top_level = True
>
>
> class L2Cache(BaseCache):
> assoc = 8
> hit_latency = 8
> response_latency = 20
> mshrs = 20
> tgts_per_mshr = 16
> write_buffers = 8
>
>
> class L3Cache(BaseCache):
> assoc = 16
> hit_latency = 20
> response_latency = 20
> mshrs = 512
> tgts_per_mshr = 20
> write_buffers = 256
>
>
> class IOCache(BaseCache):
> assoc = 8
> hit_latency = 50
> response_latency = 50
> mshrs = 20
> size = '1kB'
> tgts_per_mshr = 12
> forward_snoops = False
> is_top_level = True
>
>
> class PageTableWalkerCache(BaseCache):
> assoc = 2
> hit_latency = 2
> response_latency = 2
> mshrs = 10
> size = '1kB'
> tgts_per_mshr = 12
> is_top_level = True
>
>
>
> CacheConfig.py: The main changes are as follows:
>
>
> import m5
> from m5.objects import *
> from Caches import *
> from O3_ARM_v7a import *
>
>
> def config_cache(options, system):
>
>
> if options.cpu_type == "arm_detailed":
> try:
> from O3_ARM_v7a import *
> except:
> print "arm_detailed is unavailable. Did you compile the O3
> model?"
> sys.exit(1)
>
>
> dcache_class, icache_class, l2_cache_class, l3_cache_class = \
> O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, O3_ARM_v7aL3
> else:
> dcache_class, icache_class, l2_cache_class, l3_cache_class = \
> L1Cache, L1Cache, L2Cache, L3Cache
>
>
> # Set the cache line size of the system
> system.cache_line_size = options.cacheline_size
>
>
> if options.l3cache:
> system.l3 = l3_cache_class(clk_domain=system.cpu_clk_domain,
> size=options.l3_size,
> assoc=options.l3_assoc)
>
>
> system.tol3bus = CoherentBus(clk_domain = system.cpu_clk_domain,
> width = 32)
> system.l3.cpu_side = system.tol3bus.master
> system.l3.mem_side = system.membus.slave
> else:
> if options.l2cache:
> # Provide a clock for the L2 and the L1-to-L2 bus here as they
> # are not connected using addTwoLevelCacheHierarchy. Use the
> # same clock as the CPUs, and set the L1-to-L2 bus width to 32
> # bytes (256 bits).
> system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
> size=options.l2_size,
> assoc=options.l2_assoc)
>
>
> system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain,
> width = 32)
> system.l2.cpu_side = system.tol2bus.master
> system.l2.mem_side = system.membus.slave
> for i in xrange(options.num_cpus):
> if options.caches:
> icache = icache_class(size=options.l1i_size,
> assoc=options.l1i_assoc)
> dcache = dcache_class(size=options.l1d_size,
> assoc=options.l1d_assoc)
> if options.l3cache:
> system.cpu[i].l2 = l2_cache_class(size=options.l2_size,
> assoc=options.l2_assoc)
> system.cpu[i].tol2bus = CoherentBus()
> system.cpu[i].l2.cpu_side = system.cpu[i].tol2bus.master
> system.cpu[i].l2.mem_side = system.tol3bus.slave
>
>
> # When connecting the caches, the clock is also inherited
> # from the CPU in question
> if buildEnv['TARGET_ISA'] == 'x86':
> system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
>
> PageTableWalkerCache(),
>
> PageTableWalkerCache())
> else:
> system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
> system.cpu[i].createInterruptController()
> if options.l3cache:
> system.cpu[i].connectAllPorts(system.cpu[i].tol3bus,
> system.membus)
> else:
> if options.l2cache:
> system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
> else:
> system.cpu[i].connectAllPorts(system.membus)
>
>
> return system
>
>
> I am not getting any changes in the results in config.dot.py and stats.txt
> from when I am simulating without making the changes for L3 caches, I am
> wondering whether I have missed something?
>
>
> Thanks,
> Prateek
>
> On 04/03/14, "Prateek Gupta"
> wrote:
>> Hi,
>> I am new to Gem-5 and I want to simulate and model L3 last level cache in
>> gem-5 and then want to implement this last level cache as e-DRAM, STT-RAM.
>> I have couple of questions as mentioned below:
>>
>>
>> 1. If I want to simulate the behavior of last level caches for different
>> memory technologies like e-DRAM, STT-RAM, 1T-SRAM for 8-core, 2GHz, OOO
>> processor with 32KB, 8-way set assoc., 64 byte line size, 1 bank private
>> L1 (I$ and D$), 256 KB, 8-way set assoc., 64 byte line size, 1 bank
>> private L2$ and 32MB, 16way set assoc., 64 byte line size, 16 banks, write
>> back shared L3 $. Should I go for ruby memory controller or classic memory
>> controller? I have modified the "CacheConfig.py" for adding L3 cache
>> hierarchy but now I am not sure whether there ar
Re: [gem5-users] gem5 cache latency, impact on performance
Sanem, maybe you put sleep() somewhere in the code that never executes! Can you confirm that by breakpoints? On 4/4/14, Sanem Arslan wrote: > Hi all, > > I am using classic memory system and I have added several codes to > the "cache_impl.hh" and "blk.hh" files. However I cannot see the > performance overhead of these added codes on the gem5 execution time. > I have increased cache latency parameters from "CacheConfig.py" file > and I can see the values are updated through out the simulation by > looking trace file, but there is no significant impact on execution > time (sim_seconds). There is a post > (http://thread.gmane.org/gmane.comp.emulators.m5.users/15517/focus=15526) > that > claims there is no significant impact of increasing latency because of > optimizations implemented in the cache protocol in Classic Memory. > > Moreover I have changed "blk->whenReady" parameter aggresively and I > have put some sleep() functions somewhere in cache structures again, > but there is no effect on the execution time. > > How can I observe the performance overhead of my added codes? If you > have any suggestions, please let me know. > > By the way, I am using gem5.opt and X86 with full system mode. > > Thanks for you time and help. > > Sanem. > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Question about IPC in the O3 CPU
Hi,
That depends on the definition of idle cycle. Some say that idle
cycles don't include cache misses because there exists some
instructions in the pipeline. With such definition, idle cycles are
related to thread stalls due to I/O, network, ...
You have to check how idle cycles is incremented in gem5
On 3/31/14, Fernando Endo wrote:
> Hello,
>
> On the other hand, if a system has two cores, and only one thread is
> executing, should the IPC of a core represent the busy portion of the app
> or the overall IPC including the idle cycles?
>
> Im my opinion, the current definition may be linked to what hardware perf
> counters do. Any expert among us to explain that?
>
> Thanks in advance,
>
> --
> Fernando A. Endo, PhD student and researcher
>
> Université de Grenoble, UJF
> France
>
>
>
> 2014-03-26 23:15 GMT+01:00 Tiago Mück :
>
>> Hi,
>>
>> At /src/cpu/o3/cpu.cc we can see that the IPC is defined like this:
>>
>> totalIpc
>>
>> .name(name() + ".ipc_total")
>>
>> .desc("IPC: Total IPC of All Threads")
>>
>> .precision(6);
>>
>> totalIpc = totalCommittedInsts / numCycles;
>>
>>
>> But, according to a previous post on the list (
>> http://comments.gmane.org/gmane.comp.emulators.m5.users/11513), "
>> *numCycles*" accounts for only busy CPU cycles, so shouldn't IPC be
>> either "*totalCommittedInsts / (numCycles+idleCycles)*" or
>> "*totalCommittedInsts
>> / (numCycles+idleCycles+quiescCycles)*" ?
>>
>> If my understanding is correct, using the current formula may lead to
>> similar IPCs for tasks with very different cache miss rates for instance.
>>
>> Thanks.
>>
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>
--
Regards,
Mahmood
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Syscall clock_gettime (#228) implemented
>fatal: syscall clock_gettime (#228) unimplemented Regrding the gettime call, if it is used to report the progress, then you can safely ignore that. Otherwise, you have to implement that. To ignore that you have to comment some lines in code! grep for the syscall and you will find that. -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] mmap error when I increase mem-size
Anju, First you have to find is it a system related problem or gem5 bug. What is your OS? G++? GLIBC? -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] config.dot.pdf file
Thanks Andreas, I worked with se.py on one system and fs.py on another. -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] config.dot.pdf file
Hi It seems that in the full system simulation, the *.dot.pdf is not created. Can someone confirm tht? -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Parsec checkpointing at ROI for X86
Hi, Has anyone been able to take a checkpoint at the beginning of ROI for PARSEC workloads on a X86 disk image? I used the hook binaries but they ignore the hooks. -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Finding cache type in cache_impl.hh
That is not applicable. In addition to compiler errors, there is no such hierarchy in c++ On 3/7/14, Hamid Motaman wrote: > Hello > you can use if(name()==system.cpu.dcache) for finding whether data cache is > accessed or not > > > > > Sent from Samsung Mobile > > Original message ---- > From: Mahmood Naderan > Date: > To: gem5 users mailing list > Subject: [gem5-users] Finding cache type in cache_impl.hh > > Hi, > Since cache_impl.hh is used for all cache levels and types, how is it > possible to check whether it is used for d-cache or something else? > > IsTopLevel is useful for L1/L2 but what about i-cache, d-cache and > page table walker? > I can not find any identifier for that. > > -- > Regards, > Mahmood > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Finding cache type in cache_impl.hh
Hi, Since cache_impl.hh is used for all cache levels and types, how is it possible to check whether it is used for d-cache or something else? IsTopLevel is useful for L1/L2 but what about i-cache, d-cache and page table walker? I can not find any identifier for that. -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Running SPECCPU2006 benchmarks in X86 SE mode
Add this line to Mybench.py from m5.objects import LiveProcess -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Maxticks option
Hi I have set -F 2,000,000,000 and -m 4,000,000,000,000 to simulate an eight core processor. However the final tick is not the same as what I specified Exiting @ tick 2291079562000 because target called exit() Do I need to specify something else? -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] instruction cache miss rate result for parsec benchmark
Hi You can try other workloads or reduce the i-cache size (8KB) to verify if it working properly. On 2/28/14, Fateme Movafagh wrote: > hi all, > I am running parsec on gem5 x86 full system with --caches --cachel2 option > . > in the stat.txt file , the result of total Icache miss rate is very small, > I'm wondering maybe I have made a mistake. > for example in blackscholes even for 512B instruction cache , the miss rate > is 0.0097 and for 1kB instruction cache , it is 0.0076 . > how should I interpret these results ? > any help? > > thanks in advance. > -- > Fateme Movafagh > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Question about McPAT
Is your i-cache bigger than d-cache (in terms of KB and not mm2)? On 2/20/14, Mahshid Sedghi wrote: > Hi, > > I was wondering if anyone have done area estimation for L1 caches using > McPAT. For some reason, L1 dcache or icache is the same for > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] cache latency unit
Hi, It seems that the latency unit has been changed from Tick (ns) to Cycle. Is that correct? For example I see class L1Cache(BaseCache): size= '32kB' assoc = 4 hit_latency = 2 response_latency = 2 is_top_level = True Using CACTI, at 45nm process technology and 2.5GHz cpu frequency, the L1 access latency is 1 cycle. So should I set hit_latency = 1 response_latency = 1 ? Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] error on 'cpu_voltage_domain'
Hi While porting an old simulation script, I added these lines (the same as se.py) system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, voltage_domain = system.cpu_voltage_domain) But I get this error Traceback (most recent call last): File "", line 1, in File "/home/mahmood/gem5-10083/src/python/m5/main.py", line 388, in main exec filecode in scope File "configs/example/cmp.py", line 108, in system.cpu_voltage_domain) File "/home/mahmood/gem5-10083/src/python/m5/SimObject.py", line 736, in __getattr__ raise AttributeError, err_string AttributeError: object 'System' has no attribute 'cpu_voltage_domain' (C++ object is not yet constructed, so wrapped C++ methods are unavailable.) Where else should I modify? -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Three level coherency
Hi As far as I remember, there wan't any three level cache coherency in old versions. Is there any news about that? -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Splash-2 with m5threads "panic address not mapped error"
As far as I remember, I didn't use such an option. You can try removing
that though I don't know what is the default value for that option.
Regards,
Mahmood
On Wed, Feb 19, 2014 at 11:15 PM, Siddharth Nilakantan wrote:
> That is supposed to mean that it is part of the global address map. In SE
> mode, without an OS present I'm not sure what it means other than all
> threads/cores having a global view of memory. Shouldn't be causing my
> issue.
>
> I'll try using Physical Memory as well. Thanks.
>
>
> On 19 February 2014 14:18, Mahmood Naderan wrote:
>
>> That is weird. I had the same issue with older versions and increasing
>> the memory was the solution. What does "in_addr_map = True" mean then?
>> I used PhysicalMemory for physmem
>>
>>
>>
>>
>> Regards,
>> Mahmood
>>
>>
>>
>> On Wed, Feb 19, 2014 at 10:28 PM, Siddharth Nilakantan > > wrote:
>>
>>> Hi All,
>>>
>>> I tried Mahmood's suggestion and ended up with the same issue. It
>>> reported higher memory usage now, but dies at the same address and same
>>> cycle number!
>>>
>>> warn: ignoring syscall futex(1, 7020308, ...)
>>> warn: ignoring syscall futex(1, 7020308, ...)
>>> *panic: Tried to read unmapped address 0x140495a85.*
>>> * @ cycle 143932527000*
>>> [invoke:build/X86_MESI_CMP_directory/arch/x86/faults.cc, line 160]
>>> *Memory Usage: 8793360 KBytes*
>>> Program aborted at cycle 143932527000
>>>
>>> Is there some other way I should be increasing memory size. I just have
>>> the following in my se.py:
>>>
>>> system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
>>> physmem = SimpleMemory(in_addr_map = True,range=AddrRange('8192MB')))
>>>
>>> Note, that this gem5 version is slightly older, checked out at the
>>> beginning of last year. Any suggestions would help.
>>>
>>> Regards,
>>> Sid
>>>
>>>
>>> On 19 February 2014 01:42, Siddharth Nilakantan wrote:
>>>
>>>> Hi Mahmood,
>>>>
>>>> Thanks for that. Will try 8GB next and report what I find. I linked the
>>>> executable to the m5 threads library. I also linked in some other custom
>>>> object code that shouldn't be called when running under Gem5 at all. This
>>>> is evidenced by the fact that I can also run the same executable natively
>>>> and confirm that it finishes. (I also did a Valgrind Memcheck just to make
>>>> sure.)
>>>>
>>>> Sid
>>>>
>>>>
>>>> On 18 February 2014 13:23, Mahmood Naderan wrote:
>>>>
>>>>> Hi
>>>>> Have you modified the code in a way to create new addresses?
>>>>> You should note that the unmapped address is in the range of 4GB< <
>>>>> 8GB. If you increase the memory to 8GB, that specific address will be
>>>>> resolved but you may see another error for addresses larger than 8GB!!
>>>>>
>>>>> Hope that helps
>>>>>
>>>>>
>>>>> On 2/18/14, Siddharth Nilakantan wrote:
>>>>> > Hi All,
>>>>> >
>>>>> > I'm using Gem5's SE mode with Splash-2 compiled for m5threads. When
>>>>> running
>>>>> > the Cholesky, water-spatial and ocean benchmarks I noticed the
>>>>> "panic:
>>>>> > Tried to read unmapped address" error. Based on previous questions
>>>>> of the
>>>>> > same type, I made sure to try testing the executables under
>>>>> Valgrind. There
>>>>> > are no memory leaks, so I'm not sure what is happening.
>>>>> >
>>>>> > build/X86_MESI_CMP_directory/gem5.opt configs/example/se.py
>>>>> > --garnet-network=fixed --topology=Mesh --ruby
>>>>> >
>>>>> --cmd=~/benchmarks/splash2_gem5se/splash2/codes/kernels/cholesky/CHOLESKY
>>>>> > --options="-p8
>>>>> >
>>>>> ~/benchmarks/splash2_gem5se/splash2/codes/kernels/cholesky/inputs/tk23.O"
>>>>> > --num-cpus=8 --num-dirs=8 --num-l2caches=8 --l1d_size=64kB
>>>>> --l1d_assoc=4
>>>>> > --l1i_size=64kB --l1i_assoc=4 --l2_size=4096kB --l2_assoc=8
>>>>> > .
>>>>> > .
>>>>> > .
>>>>> >
>>>>>
Re: [gem5-users] Splash-2 with m5threads "panic address not mapped error"
That is weird. I had the same issue with older versions and increasing the
memory was the solution. What does "in_addr_map = True" mean then?
I used PhysicalMemory for physmem
Regards,
Mahmood
On Wed, Feb 19, 2014 at 10:28 PM, Siddharth Nilakantan wrote:
> Hi All,
>
> I tried Mahmood's suggestion and ended up with the same issue. It reported
> higher memory usage now, but dies at the same address and same cycle
> number!
>
> warn: ignoring syscall futex(1, 7020308, ...)
> warn: ignoring syscall futex(1, 7020308, ...)
> *panic: Tried to read unmapped address 0x140495a85.*
> * @ cycle 143932527000*
> [invoke:build/X86_MESI_CMP_directory/arch/x86/faults.cc, line 160]
> *Memory Usage: 8793360 KBytes*
> Program aborted at cycle 143932527000
>
> Is there some other way I should be increasing memory size. I just have
> the following in my se.py:
>
> system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
> physmem = SimpleMemory(in_addr_map = True,range=AddrRange('8192MB')))
>
> Note, that this gem5 version is slightly older, checked out at the
> beginning of last year. Any suggestions would help.
>
> Regards,
> Sid
>
>
> On 19 February 2014 01:42, Siddharth Nilakantan wrote:
>
>> Hi Mahmood,
>>
>> Thanks for that. Will try 8GB next and report what I find. I linked the
>> executable to the m5 threads library. I also linked in some other custom
>> object code that shouldn't be called when running under Gem5 at all. This
>> is evidenced by the fact that I can also run the same executable natively
>> and confirm that it finishes. (I also did a Valgrind Memcheck just to make
>> sure.)
>>
>> Sid
>>
>>
>> On 18 February 2014 13:23, Mahmood Naderan wrote:
>>
>>> Hi
>>> Have you modified the code in a way to create new addresses?
>>> You should note that the unmapped address is in the range of 4GB< <
>>> 8GB. If you increase the memory to 8GB, that specific address will be
>>> resolved but you may see another error for addresses larger than 8GB!!
>>>
>>> Hope that helps
>>>
>>>
>>> On 2/18/14, Siddharth Nilakantan wrote:
>>> > Hi All,
>>> >
>>> > I'm using Gem5's SE mode with Splash-2 compiled for m5threads. When
>>> running
>>> > the Cholesky, water-spatial and ocean benchmarks I noticed the "panic:
>>> > Tried to read unmapped address" error. Based on previous questions of
>>> the
>>> > same type, I made sure to try testing the executables under Valgrind.
>>> There
>>> > are no memory leaks, so I'm not sure what is happening.
>>> >
>>> > build/X86_MESI_CMP_directory/gem5.opt configs/example/se.py
>>> > --garnet-network=fixed --topology=Mesh --ruby
>>> >
>>> --cmd=~/benchmarks/splash2_gem5se/splash2/codes/kernels/cholesky/CHOLESKY
>>> > --options="-p8
>>> >
>>> ~/benchmarks/splash2_gem5se/splash2/codes/kernels/cholesky/inputs/tk23.O"
>>> > --num-cpus=8 --num-dirs=8 --num-l2caches=8 --l1d_size=64kB
>>> --l1d_assoc=4
>>> > --l1i_size=64kB --l1i_assoc=4 --l2_size=4096kB --l2_assoc=8
>>> > .
>>> > .
>>> > .
>>> >
>>> > warn: ignoring syscall futex(0, 7020308, ...)
>>> > warn: ignoring syscall futex(0, 7020308, ...)
>>> > warn: ignoring syscall futex(0, 7020308, ...)
>>> > warn: ignoring syscall futex(0, 7020308, ...)
>>> > warn: ignoring syscall futex(0, 7020308, ...)
>>> > warn: ignoring syscall futex(0, 7020308, ...)
>>> > warn: ignoring syscall futex(0, 7020308, ...)
>>> > warn: ignoring syscall futex(0, 7020308, ...)
>>> > warn: ignoring syscall futex(0, 7020308, ...)
>>> > warn: ignoring syscall futex(0, 7020308, ...)
>>> > warn: ignoring syscall futex(0, 7020308, ...)
>>> > warn: ignoring syscall futex(0, 7020308, ...)
>>> > warn: ignoring syscall futex(1, 7020308, ...)
>>> > warn: ignoring syscall futex(1, 7020308, ...)
>>> > *panic: Tried to read unmapped address 0x140495a85.*
>>> > @ cycle 143932527000
>>> > [invoke:build/X86_MESI_CMP_directory/arch/x86/faults.cc, line 160]
>>> > Memory Usage: 4599016 KBytes
>>> > Program aborted at cycle 143932527000
>>> >
>>> > The system is configured to have 4GB of Physical memory and the memory
>>> > usage is still higher. It always dies at the same address and the same
>>> > cycle number.
>>> >
>>> > Can anyone help me figure out why this is happening? What flags should
>>> I
>>> > turn on to get more useful information?
>>> >
>>> > Regards,
>>> > Sid
>>> >
>>>
>>>
>>> --
>>> Regards,
>>> Mahmood
>>> ___
>>> gem5-users mailing list
>>> gem5-users@gem5.org
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>
>>
>>
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
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Re: [gem5-users] Splash-2 with m5threads "panic address not mapped error"
Hi Have you modified the code in a way to create new addresses? You should note that the unmapped address is in the range of 4GB< < 8GB. If you increase the memory to 8GB, that specific address will be resolved but you may see another error for addresses larger than 8GB!! Hope that helps On 2/18/14, Siddharth Nilakantan wrote: > Hi All, > > I'm using Gem5's SE mode with Splash-2 compiled for m5threads. When running > the Cholesky, water-spatial and ocean benchmarks I noticed the "panic: > Tried to read unmapped address" error. Based on previous questions of the > same type, I made sure to try testing the executables under Valgrind. There > are no memory leaks, so I'm not sure what is happening. > > build/X86_MESI_CMP_directory/gem5.opt configs/example/se.py > --garnet-network=fixed --topology=Mesh --ruby > --cmd=~/benchmarks/splash2_gem5se/splash2/codes/kernels/cholesky/CHOLESKY > --options="-p8 > ~/benchmarks/splash2_gem5se/splash2/codes/kernels/cholesky/inputs/tk23.O" > --num-cpus=8 --num-dirs=8 --num-l2caches=8 --l1d_size=64kB --l1d_assoc=4 > --l1i_size=64kB --l1i_assoc=4 --l2_size=4096kB --l2_assoc=8 > . > . > . > > warn: ignoring syscall futex(0, 7020308, ...) > warn: ignoring syscall futex(0, 7020308, ...) > warn: ignoring syscall futex(0, 7020308, ...) > warn: ignoring syscall futex(0, 7020308, ...) > warn: ignoring syscall futex(0, 7020308, ...) > warn: ignoring syscall futex(0, 7020308, ...) > warn: ignoring syscall futex(0, 7020308, ...) > warn: ignoring syscall futex(0, 7020308, ...) > warn: ignoring syscall futex(0, 7020308, ...) > warn: ignoring syscall futex(0, 7020308, ...) > warn: ignoring syscall futex(0, 7020308, ...) > warn: ignoring syscall futex(0, 7020308, ...) > warn: ignoring syscall futex(1, 7020308, ...) > warn: ignoring syscall futex(1, 7020308, ...) > *panic: Tried to read unmapped address 0x140495a85.* > @ cycle 143932527000 > [invoke:build/X86_MESI_CMP_directory/arch/x86/faults.cc, line 160] > Memory Usage: 4599016 KBytes > Program aborted at cycle 143932527000 > > The system is configured to have 4GB of Physical memory and the memory > usage is still higher. It always dies at the same address and the same > cycle number. > > Can anyone help me figure out why this is happening? What flags should I > turn on to get more useful information? > > Regards, > Sid > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] IPC
You can write a script to sum all committed instructions, sum(commit0, ..., commitN), and then divide that by the number of cycles -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Memory contention: Odd results
Hi >- work: which accesses memory very frequently and each > access produces a L1 and L2 miss Are you sure about that? Can you confirm that the hit stats are zero? -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DRAM prefetcher
>The pre-fetcher for L2, does it fetch from DRAM and place the data in L2 >(assuming L2 is the last level cache)? Or is it fetching from L2 and placing >the data in L1? Hi, The easiest way is to turn on the debug messages "DPRINTF" and track one prefetch request that has been issued. I am not sure about the latest gem5 revision, but in cache_impl.hh you should find this line if (prefetcher && !mshrQueue.isFull()) In the body, a prefetch request will be issued. Normally, if you attach the prefetcher to L1, then L1 is the source and will get response from either L2 or mem. If you attach it to L2, then it will get the response from mem. -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Regarding ipc_total
Hi,
Looking in to code cpu.cc, I see
ipc
.name(name() + ".ipc")
.desc("IPC: Instructions Per Cycle")
.precision(6);
ipc = committedInsts / numCycles;
totalIpc
.name(name() + ".ipc_total")
.desc("IPC: Total IPC of All Threads")
.precision(6);
totalIpc = totalCommittedInsts / numCycles;
That means, in a multicore simulation the ipc_total is calculated based on
the aggregate number of instructions. For example, assume
core0: inst=500, cycle=500
core1: inst=400, cycle=500
core2: inst=600, cycle=500
core3: inst=600, cycle=500
So gem5 will report ipc_total=2100/500=4.2.Is that right?
However another approach is to take HMEAN since we are averaging of rates.
IPC_of_multicore=HMEAN(IPC_of_each_core)
So the result will be 1.02
Any idea on that?
Regards,
Mahmood
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Re: [gem5-users] regarding mcpat
Agree with that. One more question. While using McPAT, I don't see any energy stat (J) Processor: Area = 337.539 mm^2 Peak Power = 133.749 W Total Leakage = 15.506 W Peak Dynamic = 118.243 W Subthreshold Leakage = 11.6106 W Subthreshold Leakage with power gating = 6.51873 W Gate Leakage = 3.89534 W Runtime Dynamic = 0.874712 W The peak power normally doesn't change when I modify the accesses/reads/writes stats. Do you know what does "Runtime Dynamic" mean? On 11/25/13, Fernando Endo wrote: > Hello, > > If you're using the Classic memory model, there's no cache directory, > because it uses the snooping protocol. I would disable the cache > directories. Correct me if I'm wrong please. > > Regards, > > -- > Fernando A. Endo, PhD student and researcher > > Université de Grenoble, UJF > France > > > > 2013/11/20 Amin Farmahini > >> This might give you some idea. >> https://www.cl.cam.ac.uk/~acr31/sicsa/mcpat-template.xml >> >> Amin >> >> >> On Wed, Nov 20, 2013 at 8:58 AM, Mahmood Naderan >> wrote: >> >>> Hi, >>> While porting stats from gem5 to mcpat, I could not find the >>> counterpart of the following stats. >>> >>> 1- Shall we use the same L1D stats for L1Directory? For example, are >>> these equal >>> >>> >>> >>> >>> >>> >>> 2- The same question regarding L2 and L2Directory >>> >>> 3- >>> >>> >>> >>> >>> -- >>> Regards, >>> Mahmood >>> ___ >>> gem5-users mailing list >>> gem5-users@gem5.org >>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>> >> >> >> ___ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] regarding mcpat
Hi, While porting stats from gem5 to mcpat, I could not find the counterpart of the following stats. 1- Shall we use the same L1D stats for L1Directory? For example, are these equal 2- The same question regarding L2 and L2Directory 3- -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] blocking causes
Hi,
I see some stats regarding block causes.
system.l2.blocked_cycles::no_mshrs 9584945079 # number of
cycles access was blocked
system.l2.blocked_cycles::no_targets 0 # number of
cycles access was blocked
system.l2.blocked::no_mshrs 1765905 # number of cycles
access was blocked
system.l2.blocked::no_targets 0 # number of cycles
access was blocked
With the descriptions and the source code, it is not very clear what
does "no_mshr" mean? Also in the code, I see
void clearBlocked(BlockedCause cause)
{
uint8_t flag = 1 << cause;
blocked &= ~flag;
DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
if (blocked == 0) {
blocked_cycles[cause] += curTick() - blockedCycle;
cpuSidePort->clearBlocked();
}
}
Here it seems that the cause is an *enum* variable, but there is no
description for that.
Any comment is appreciated.
--
Regards,
Mahmood
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[gem5-users] Shall we solve "unable to find destination addr" once for all ?!
Hi
I think I found why randomly one receives this error:
fatal: Unable to find destination for addr 0xNNN on bus system.membus
A workaround for this issue is to increase the memory as discussed in
the following posts
http://www.mail-archive.com/gem5-users@gem5.org/msg04502.html
http://www.mail-archive.com/gem5-users@gem5.org/msg05886.html
The roots for this error are some hard coded hex values in the
X86_64LiveProcess::X86_64LiveProcess(). For x86 this function is
located at src/sim/arch/x86/process.cc. Currently, the hard coded
values are in the range of 64GB but not every body who has built his
application on a 64-bit host, uses a 64GB RAM.
In anther word, someone may compile his application with 8GB of
memory, but LiveProcess() and mmap() in gem5 will allocate some
virtual memory at the size of 64GB because of the hard coded numbers.
Now what is wrong with that? The wrong is, these hard coded numbers
will overwrite the memory value defined in the configuration script
system = System(cpu = cpus, physmem =
PhysicalMemory(range=AddrRange("4096MB")), membus = Bus())
That means, you might define a 4GB memory for gem5, but it will
allocate the whole 64GB address space for the virtual memory and
randomly (depends on how mmap allocate the address space) will fire
the "unable to find the destination addr" error message.
I am not aware of other archs, but for x86 it is an error prone code.
--
Regards,
Mahmood
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[gem5-users] modifying trace messages
Hi Where can I customize the trace messages in the source files? I am executing --debug-flags=Exec --trace-file=trace.out ... -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] consistency issue with gem5
>you can use the util/tracediff script >(http://www.m5sim.org/Debugging#tracediff). It seems that I can not pass all parameters to command line. Currently, in my cmp.py, I have system.l2.prefetcher = Prefetcher() However in Caches.py, I have class Prefetcher(BasePrefetcher): type = 'StridePrefeter' ... And I don't know how to pass the prefetcher type to Caches.py tracediff works with different arguments so I wonder how can I pass the prefetcher type to command line. Something like this which has not correct syntax build/X86/m5.debug configs/cmp/py ... --caches --prefetcher StridePrefetcher -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] consistency issue with gem5
The simulator job is to *simulate* the given code. Otherwise, it will be extremely difficult to verify the code because everything is possible! Specifically for my prefetcher, assume the program code looks like this LD 0x90 ADD ... Assume my prefetcher, predict something else which is wrong. Then there should be a annotating mechanism that compare what I predicted and what is actually accessed (from the assembly code). Then the result will be a "wrong prefetch". However with the current infrastructure, no matter what is prefetched, they are always considered to be correct. -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] consistency issue with gem5
Hi I have a concern about gem5 simulator consistency and will be glad for any help. Thing is, I have implemented two different prefetchers, but with the same binary and command lines, I see that different block addresses are accessed. However which block is accessed must be a function of the program binary itself (e.g the assembly code) and not the cache structure or simulator. In short, gem5 can change the program execution path! -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Issue with mounting the disk image
Hi Maybe the question is not directly related to gem5, but the problem is users (not sudoers) can not execute mount command because of the permission set by the so they can not mount the disk image. Has anyone faced such problem? -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Low IP for SPEC CPU 2006 benchmarks
An update to this issue is to hear a feedback from someone who uses ALPHA binaries in SE mode. X86 is not as rich as ALPHA. If IPC values are normal in ALPHA, then there is something wrong with X86 decoder. On 6/17/13, Manmohan Manoharan wrote: > > Jerry Backer students.poly.edu> writes: > >> >> >> I am using the most up to date gem5 (from development repository) with > detailed cpu-type for various cint >> 2006 benchmarks. >> However, the IPC for all the benchmarks are extremely low ( <= 0.1 for > most benchmarks). >> The binaries are 32-bit statically linked and have been used with other > simulators and presented >> reasonable >> ipc numbers. I also tried simulating with timing and also obtained low ipc >> > ( <0.01 for most benchmarks). >> I am simulating with se.py using the default configuration with caches and >> > l2cache enabled for detailed >> cpu type. >> >> Has anyone encountered this issue ? >> >> Thanks, >> > > I also find the same issue when I run the SPEC 2006 benchmarks. I am using > the X86 detailed model and statically linked binaries. I tried both the SSE2 > > as well as non-SSE2 compiled binaries on the corresponding gem5 versions. > However the results seem to be the same. Any updates on this would be very > helpful. > > > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] "terminate called after throwing an instance of 'std::bad_alloc' " when using trunk
>Not really :). If you know precisely what I should type, I'll do it. Simply run "valgrind build/X86/m5.debug ." Note that you have to compile in debug mode and valgrind is slow. So you have to lower the fast forward and other times. On 6/4/13, Ali Saidi wrote: > > > Normally you see a bad_alloc when a program tries to allocate memory > and it can't (because there isn't enough in the system). Could you run > the simulator in the debugger and see where it's actually coming from? > > > Ali > > On 04.06.2013 08:06, Maxime Chéramy wrote: > >> Hi, >> >> I've > just updated my instance of gem5 with the last changes from the > mercurial repo. The code still compile properly but when I try to run a > bench in SE mode, it crashes quickly: >> >> command line: > build/X86/gem5.opt configs/example/se.py -n 1 --cpu-type=timing --caches > --l2cache --l1d_size=256B --l1d_assoc=4 --l1i_size=256B --l1i_assoc=4 > --l2_size=16kB --l2_assoc=4 --num-l2caches=1 -c > /home/max/bench/automotive/basicmath/basicmath_small >> Global frequency > set at 1 ticks per second >> terminate called after throwing > an instance of 'std::bad_alloc' >> what(): std::bad_alloc >> Program > aborted at cycle 0 >> >> My last update was the 28th of February and the > exact same command line was working (I still have a copy of the > directory before the update). >> >> Do you have any opinion or > suggestion? I have not tried yet "scons -c", I am rebuilding > currently. >> >> Regards, >> >> Maxime. >> >> > ___ >> gem5-users mailing > list >> gem5-users@gem5.org >> > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1] > > > > > Links: > -- > [1] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] "terminate called after throwing an instance of 'std::bad_alloc' " when using trunk
Hi bad_alloc() messages usually means running out of memory. You can attach valgrind to find memory leakage. Hope that help On 6/4/13, Maxime Chéramy wrote: > Hi, > > I've just updated my instance of gem5 with the last changes from the > mercurial repo. The code still compile properly but when I try to run a > bench in SE mode, it crashes quickly: > > command line: build/X86/gem5.opt configs/example/se.py -n 1 > --cpu-type=timing --caches --l2cache --l1d_size=256B --l1d_assoc=4 > --l1i_size=256B --l1i_assoc=4 --l2_size=16kB --l2_assoc=4 --num-l2caches=1 > -c /home/max/bench/automotive/basicmath/basicmath_small > Global frequency set at 1 ticks per second > terminate called after throwing an instance of 'std::bad_alloc' > what(): std::bad_alloc > Program aborted at cycle 0 > > My last update was the 28th of February and the exact same command line was > working (I still have a copy of the directory before the update). > > > Do you have any opinion or suggestion? I have not tried yet "scons -c", I > am rebuilding currently. > > > Regards, > > Maxime. > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Meaning of "warn: instruction 'fld' unimplemented"
Hi That means specific floating point instructions are not implemented. So they are ignored. If your benchmark, uses these instructions a lot, then your results are not very representative. On 5/24/13, Maxime Chéramy wrote: > Hello, > > With a specific bench, I encountered the warnings: > > warn: instruction 'fldcw_Mw' unimplemented > warn: instruction 'fld' unimplemented > warn: instruction 'fld' unimplemented > warn: instruction 'fstp' unimplemented > warn: instruction 'fmul' unimplemented > ... > > I'd like to know what exactly does it imply on the simulation: is it just a > nop? Are there any cache accesses anyway? > > Also, I would like to know what can I do about that issue. I tried to > compile with soft fp for x86 with no success. > > Thank you for your help. > > Regards, > > Maxime. > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] cc1plus:warnings being treated as errors
Hi Comment or remove the following line from src/SConscript new_env.Append(CCFLAGS='-Werror') Hope that helps On 5/16/13, Ranga, L Udaya wrote: > Hi, > > I get a lot of error messages while building gem5 which are related to > uninitialized warnings being treated as errors. I tried adding specific > flags for compiler to ignore this fact, but couldn't get past this check. Is > there a single point in SConstruct(s), where I can force this behavior. Or, > the generated file should have correct code. > > For example, /python/swig/core_wrap.cc always fails to initialize PyObject > *argv[2]; > > Thanks, > Uday > > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] GHB prefetcher
This may be useful http://www.mail-archive.com/gem5-users@gem5.org/msg02490.html On 5/7/13, Xiangyang Guo wrote: > Hi, gem5-user, > > I take a look at the GHB prefetcher provided by Gem5 , I'm wondering if > this part is finished or not? It seems that the code is like a stride based > GHB prefetcher, but I'm not sure because there is no a obvious index table > and buffer. So could anyone give me any hints? Thanks in advance. > > Regards > > Xiangyang > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Splash2
There are some scripts in config/splash2. Have you tried them? On 4/21/13, Northwestern wrote: > Hi guys, > > Because nobody answer my question and I am still working on it. I decide > send my simple question again. Thank you for your help! > > Best, > Tony > > Begin forwarded message: > >> From: Yijie Bai >> Date: 2013年4月19日 格林尼治标准时间-050023时26分50秒 >> To: gem5 users mailing list >> Subject: Splash2 >> >> Hello guys, >> >> It's tony. Again. >> I just want to know how to run Splash2 on X86 system? I have already built >> the X86 gem5.opt and can successfully run the FS mode. The question is I >> don't know how to configure the files and run the Splash2 on it. I have >> searched the internet for whole day but turn out to be useless. There >> isn't any guide that can help me with the process step by step. >> >> Can somebody help me with it?? Thank you very much for your help!! >> >> Best, >> Tony >> > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Low IP for SPEC CPU 2006 benchmarks
Hi I confirm that for some benchmarks. However it is very hard to pin point the fault. The most probable thing is the incorrect implementation of some special instructions. For example, CFP benhcmarks uses some special instructions a lot. So if the instruction has not been implemented correctly, then the whole execution goes wrong. On 4/3/13, Jerry Backer wrote: > > I am using the most up to date gem5 (from development repository) with > detailed cpu-type for various cint 2006 benchmarks. > However, the IPC for all the benchmarks are extremely low ( <= 0.1 for most > benchmarks). > The binaries are 32-bit statically linked and have been used with other > simulators and presented reasonable > ipc numbers. I also tried simulating with timing and also obtained low ipc ( > <0.01 for most benchmarks). > I am simulating with se.py using the default configuration with caches and > l2cache enabled for detailed cpu type. > > Has anyone encountered this issue ? > > > Thanks, > > > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] L1 cache miss count
Hi Regarding your first question, you can modify the code and print the stats to a file or std::cout whenever you want. Check and see where in the code, your desired miss stat is increased. On 3/8/13, tejasi pimpalkhute wrote: > Hi All, > > Could anyone please tell me if I can check the count of L1 cache miss at > runtime, say after x cycles? The cache profiler has the record of all the > cache misses but is there any way I can get the information from it at > runtime and pass it to its router/NI? > > Also, I wanted to know if the data request packets which encounter a L1 > cache miss travel through the Garnet interconnection network to reach to > the L2 cache/memory or are they passed through the sequencer? I am a bit > confused here. Can anyone please guide me? > > -- > Thanks and Regards, > Tejasi > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Unimplemented Function
Hi What is the IPC you get from h264? On 2/4/13, Rodrigo Reynolds Ramírez wrote: > > Hello everyone, > I was using the stable version (f75ee4849c40), I download the version in > development (890fc69ba53c) and only one benckmark does not work. I suppose > this syscall will be supported in future releases. This is the benchmark > that does not work. > 483.xalancbmkfatal: syscall lstat (#6) unimplemented. @ cycle > 1556716000[unimplementedFunc:build/X86/sim/syscall_emul.cc, line 83] > Thanks in advance, Rodrigo > > Date: Sat, 2 Feb 2013 13:22:56 -0700 > From: yidin...@aggiemail.usu.edu > To: gem5-users@gem5.org > Subject: Re: [gem5-users] Unimplemented Function > > Hi Rodrigo, > > You could fix the "fatal: Out of memory, please increase size of physical > memory." by giving more memory to the simulation, for example 2048MB works > for me. > > -Yiding > > > On Sat, Feb 2, 2013 at 10:37 AM, Rodrigo Reynolds Ramírez > wrote: > > > > > > Hi I did everyone explained in http://www.gem5.org/SPEC2006_benchmarks but > not only perlbench has problems, I found 9 benchmarks that report a error. > Specifically I found these errors: > > 400.perlbench, 410.bwaves, 437.leslie3d, 459.GemsFDTD, 481.wrf, > 465.tontofatal: syscall ioctl (#16) unimplemented. @ cycle > 31165000[unimplementedFunc:build/X86/sim/syscall_emul.cc, line 83] > > 483.xalancbmkfatal: syscall lstat (#6) unimplemented. @ cycle > 1556716000[unimplementedFunc:build/X86/sim/syscall_emul.cc, line 83] > > 434.zeusmp, 416.gamessfatal: Out of memory, please increase size of physical > memory. @ cycle 0[allocPhysPages:build/X86/sim/system.cc, line 305] > > That means that 9/29 benchmarks don't work with gem5. > Thanks in advance, Rodrigo > > > Date: Sat, 2 Feb 2013 11:41:48 -0500 > > From: tao.zhang.0...@gmail.com > To: gem5-users@gem5.org > Subject: Re: [gem5-users] Unimplemented Function > > > > > > > > > Hi Rodrigo, > > > > Yes, SPEC2006 can be run in SE mode definitely. However, perlbench > has some trouble so that it should be skipped. see > http://www.gem5.org/SPEC2006_benchmarks for the detail. > > > > -Tao > > > > On 02/02/2013 11:34 AM, Rodrigo Reynolds Ramírez wrote: > > > > Hello everyone: > > > > I am trying to run the SPEC CPU2006 I compile it using the > toolchain created for x86_64 using crosstool-ng. But I when I > run some benchmarks for example perlbench I got a syscall > error: > > > > > fatal: syscall ioctl (#16) unimplemented. >@ cycle 241952000 > [unimplementedFunc:build/X86/sim/syscall_emul.cc, line > 83] > > > > > Is it possible to run the spec2006 in se.py? > > > > Thanks in advance > Rodrigo > > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > ___ > > gem5-users mailing list > > gem5-users@gem5.org > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > -- > Ph.D. Candidate, Yiding Han > BRIDGE Lab, ECE Dept.,Utah State University, Logan, UT 84322, USA > E-mail: yidin...@aggiemail.usu.edu, bitc...@gmail.com > > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] memory management
That is my observation that mmap allocates N*4GB. However I don't know how to verify. Assume I have 8 benchmarks. Simulating a uniprocessor with 4GB memory with each of the benchmarks has no problem. I mean -n 1 -b app1 -n 1 -b app2 -n 1 -b app3 ... -n 1 -b app8 However when I define 4GB and run -n 8 -b app1,app2, ..., app8 the unmapped address is outside 4GB. On 2/2/13, Ali Saidi wrote: > Why should it be N*4GB? In each process using 4GB of memory? That doesn't > seem right. I'd guess your issue is that a bad request is being generated > somewhere in the memory system and making it incredibly large is just > covering the problem up. > > Ali > > On Feb 2, 2013, at 2:57 AM, Mahmood Naderan wrote: > >> It is really annoying. I think mmap is responsible for this behavior. >> >> On 1/31/13, Mahmood Naderan wrote: >>> Hi >>> I have found that in a N multicore simulation, defined memory size >>> should be N*4GB. For example, I am simulting eight cores so I have to >>> define 32GB memory. Otherwise I randomly get "unable to find >>> destination ..." error. >>> >>> However in reality while the simulation is running, "top" command >>> shows that about 1.5GB of memory is used. >>> >>> Another problem is that in a systeam with 32GB memory installed and >>> 20GB free memory, I can not define a 32GB memory in gem5 simulation >>> script. Otherwise I get "could not mmap" error message. >>> >>> Is there any better memory management? >>> >>> >>> Regards, >>> Mahmood >>> >> >> >> -- >> Regards, >> Mahmood >> ___ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] memory management
It is really annoying. I think mmap is responsible for this behavior. On 1/31/13, Mahmood Naderan wrote: > Hi > I have found that in a N multicore simulation, defined memory size > should be N*4GB. For example, I am simulting eight cores so I have to > define 32GB memory. Otherwise I randomly get "unable to find > destination ..." error. > > However in reality while the simulation is running, "top" command > shows that about 1.5GB of memory is used. > > Another problem is that in a systeam with 32GB memory installed and > 20GB free memory, I can not define a 32GB memory in gem5 simulation > script. Otherwise I get "could not mmap" error message. > > Is there any better memory management? > > > Regards, > Mahmood > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] memory management
Hi I have found that in a N multicore simulation, defined memory size should be N*4GB. For example, I am simulting eight cores so I have to define 32GB memory. Otherwise I randomly get "unable to find destination ..." error. However in reality while the simulation is running, "top" command shows that about 1.5GB of memory is used. Another problem is that in a systeam with 32GB memory installed and 20GB free memory, I can not define a 32GB memory in gem5 simulation script. Otherwise I get "could not mmap" error message. Is there any better memory management? Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Last leve cache accesses
I think so. However Andreas says MasterID is the right thing http://comments.gmane.org/gmane.comp.emulators.m5.users/13388 On 1/27/13, mihai pricopi wrote: > In cache_imple.hh access() function, is the returned value of > pkt->req->contextId() the id of the core who made the cache request > (assuming no SMT) ? > > > On Sun, Jan 27, 2013 at 5:45 AM, Nilay wrote: > >> On Fri, January 25, 2013 10:30 pm, mihai pricopi wrote: >> > Hi, >> > >> > I would like to trace only the requests coming from lower level of >> caches >> > to the last level of cache indicating the cpu that made that request. I >> > used debug flag Cache but that contains too much information and I >> > don't >> > know if it indicates who made the request. >> > Is there a debug flag for this ? >> >> No, I don't think there is a debug flag for printing such a specific >> info. >> >> -- >> Nilay >> >> > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] core id in PacketPtr
Sorry but I think I didn't get what you said . >You can ask the system what a specific master ID corresponds to (and get a string back). What I undesrtand is that I have to define a table that maps the master id to a meaning full string. If that is true, then I have to manually change the code and add/modify the number of cpus and their corresponding master id every time. However I am pretty sure that gem5 should have such a table as the simulation starts. Another thing is the contextId. In a single core simulation, I see this variable is 0 for all requests and on a 2 core simulation, it toggles (0 and 1). Don't you think contextId is what I asked in the first post? On 1/25/13, Andreas Hansson wrote: > Hi Mahmood, > > You can ask the system what a specific master ID corresponds to (and get a > string back). > > Each master in the system gets an ID. That includes DMAs etc. Thus, every > block that on its own generates requests should have a master id. > > Good luck. > > Andreas > > On 25/01/2013 10:56, "Mahmood Naderan" wrote: > >>I see this in stride.cc >> >>MasterID master_id = useMasterId ? pkt->req->masterId() : 0; >> >>However, on a single core simulation, I see that master_id is 6. How >>that is possible? >> >>On 1/25/13, Andreas Hansson wrote: >>> Hi Mahmood, >>> >>> Have a look at the MasterID. >>> >>> The src/dest field is hop to hop and is only used by (de)multiplexing >>> components to send responses to the right port. >>> >>> Andreas >>> >>> On 25/01/2013 10:27, "Mahmood Naderan" wrote: >>> >>>>Hi, >>>>How can I find which core send a message? As I read packet.hh, there >>>>is no member like core_id or something else. >>>> >>>>The only thing that I guess is >>>>/** >>>> * Device address (e.g., bus ID) of the source of the >>>> * transaction. The source is not responsible for setting this >>>> * field; it is set implicitly by the interconnect when the packet >>>> * is first sent. >>>> */ >>>>NodeID src; >>>> >>>>However don't know how many devices are defined. For example, if L2 >>>>receives a packet, how can I check the id of the sender core? >>>> >>>> >>>>-- >>>>Regards, >>>>Mahmood >>>>___ >>>>gem5-users mailing list >>>>gem5-users@gem5.org >>>>http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>>> >>> >>> >>> -- IMPORTANT NOTICE: The contents of this email and any attachments are >>> confidential and may also be privileged. If you are not the intended >>> recipient, please notify the sender immediately and do not disclose the >>> contents to any other person, use it for any purpose, or store or copy >>>the >>> information in any medium. Thank you. >>> >>> ___ >>> gem5-users mailing list >>> gem5-users@gem5.org >>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>> >> >> >>-- >>Regards, >>Mahmood >>___ >>gem5-users mailing list >>gem5-users@gem5.org >>http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] core id in PacketPtr
I see this in stride.cc MasterID master_id = useMasterId ? pkt->req->masterId() : 0; However, on a single core simulation, I see that master_id is 6. How that is possible? On 1/25/13, Andreas Hansson wrote: > Hi Mahmood, > > Have a look at the MasterID. > > The src/dest field is hop to hop and is only used by (de)multiplexing > components to send responses to the right port. > > Andreas > > On 25/01/2013 10:27, "Mahmood Naderan" wrote: > >>Hi, >>How can I find which core send a message? As I read packet.hh, there >>is no member like core_id or something else. >> >>The only thing that I guess is >>/** >> * Device address (e.g., bus ID) of the source of the >> * transaction. The source is not responsible for setting this >> * field; it is set implicitly by the interconnect when the packet >> * is first sent. >> */ >>NodeID src; >> >>However don't know how many devices are defined. For example, if L2 >>receives a packet, how can I check the id of the sender core? >> >> >>-- >>Regards, >>Mahmood >>___ >>gem5-users mailing list >>gem5-users@gem5.org >>http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] core id in PacketPtr
Hi, How can I find which core send a message? As I read packet.hh, there is no member like core_id or something else. The only thing that I guess is /** * Device address (e.g., bus ID) of the source of the * transaction. The source is not responsible for setting this * field; it is set implicitly by the interconnect when the packet * is first sent. */ NodeID src; However don't know how many devices are defined. For example, if L2 receives a packet, how can I check the id of the sender core? -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] prefetcher configuration has been changed
ok thanks. it seems that the prefetcher has to be defined in Caches.py as part of of "class L2Cache(BaseCache):" On 1/22/13, Nilay wrote: > > On Tue, January 22, 2013 1:33 am, Mahmood Naderan wrote: >> Hi >> it seems that the way we configure and define a prefetcher has been >> chnaged in the latest revision 9476. So far, my cmp.py looked like: >> >> system.l2 = L2Cache() >> system.l2.prefetcher = Prefetcher() >> >> and Caches.py looked like >> >> class Prefetcher(BasePrefetcher): >> type = 'StridePrefetcher' >> degree = 5 >> cross_pages = True >> latency = 1 >> size = 512 >> serial_squash = True >> >> class L2Cache(BaseCache): >> size= '512kB' >> hit_latency = 12 >> response_latency = 12 >> assoc = 16 >> block_size = 64 >> mshrs = 20 >> tgts_per_mshr = 15 >> >> >> And there was no problem with that. Now, I get this error: >> >> ... >> File "/home/mahmood/gem5/configs/common/Caches_l2pf.py", line 31, in >> >> class Prefetcher(BasePrefetcher): >> File "/home/mahmood/gem5/src/python/m5/SimObject.py", line 137, in >> __new__ >> assert name not in allClasses, "SimObject %s already present" % name >> AssertionError: SimObject Prefetcher already present >> >> >> Can someone explain? > > grep for "class Prefetcher". > > -- > Nilay > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] prefetcher configuration has been changed
Hi it seems that the way we configure and define a prefetcher has been chnaged in the latest revision 9476. So far, my cmp.py looked like: system.l2 = L2Cache() system.l2.prefetcher = Prefetcher() and Caches.py looked like class Prefetcher(BasePrefetcher): type = 'StridePrefetcher' degree = 5 cross_pages = True latency = 1 size = 512 serial_squash = True class L2Cache(BaseCache): size= '512kB' hit_latency = 12 response_latency = 12 assoc = 16 block_size = 64 mshrs = 20 tgts_per_mshr = 15 And there was no problem with that. Now, I get this error: ... File "/home/mahmood/gem5/configs/common/Caches_l2pf.py", line 31, in class Prefetcher(BasePrefetcher): File "/home/mahmood/gem5/src/python/m5/SimObject.py", line 137, in __new__ assert name not in allClasses, "SimObject %s already present" % name AssertionError: SimObject Prefetcher already present Can someone explain? -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Again... "Tried to write unmapped address"
Thank you. It is fine now On 1/21/13, Nilay wrote: > On Sun, January 20, 2013 2:14 pm, Mahmood Naderan wrote: >> Here is my findings: >> 1) for r9460, I get a segmentation fault (and not the unmapped >> address). I attached the gdb output and the config.ini and the config >> file >> >> 2) for r9461, I get the unmapped error. I attached the output and >> config.ini and the config file (which is the same as above). >> >> >> Also, please note that although I used a unique value for fast >> forwarding, the reported switch cpu tick is different in two revisions >> which is strange for me. >> > > The following patch should solve your problem -- > > http://reviews.gem5.org/r/1658/ > > -- > Nilay > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Again... "Tried to write unmapped address"
By the way, I see that error for read/write/execute On 1/20/13, Mahmood Naderan wrote: > Hi, > With the latest revision on gem5, I get "Tried to write unmapped > address" for a number of spec2k6 benchmarks however I previous > revisions have no problem. > This time the unmapped address is 0x58, 0xb8 or even 0x00!! > > REAL SIMULATION > info: Entering event queue @ 23127352500. Starting simulation... > panic: Tried to write unmapped address 0x16. > @ cycle 23127357500 > [invoke:build/X86/arch/x86/faults.cc, line 160] > Memory Usage: 4303264 KBytes > > > There is no problem with the memory configuration. Previously, I found > that the unmapped address is outside of the configured memory. So why > should I get this error with those numbers? > > -- > Regards, > Mahmood > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Again... "Tried to write unmapped address"
Hi, With the latest revision on gem5, I get "Tried to write unmapped address" for a number of spec2k6 benchmarks however I previous revisions have no problem. This time the unmapped address is 0x58, 0xb8 or even 0x00!! REAL SIMULATION info: Entering event queue @ 23127352500. Starting simulation... panic: Tried to write unmapped address 0x16. @ cycle 23127357500 [invoke:build/X86/arch/x86/faults.cc, line 160] Memory Usage: 4303264 KBytes There is no problem with the memory configuration. Previously, I found that the unmapped address is outside of the configured memory. So why should I get this error with those numbers? -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] How I compile the spec2006 binaries statically
Hi you have to modify the config files (the compiler and system you use) and add the -static option to the compiler flag and then build with runspec. On 12/6/12, mir shan wrote: > Dear members > I have licensed SPEC2006, I go through > http://www.m5sim.org/SPEC2006_benchmarks page but couldn't understand how to > built/compile SPEC2006 benchmarks so I used in the below command > build/X86SE/gem5.opt configs/example/se.py -c test/test-prog/bzip2 > regards > Mir > > > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] flaoting point instructions
Hi Is there any plan to implement some floating point X86 instructions? fnstcw_Mw fldcw_Mw emms fwait There were some efforts but seems that they have not been committed to the repository. I remember a discussion on that. Any news? -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Where to change SimpleDRAM size
Thanks -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Where to change SimpleDRAM size
Hi How can I increase the size of a SimpleDRAM memory? in SimpleDRAM.py, I see only some timing parameters. -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] error setting --prog-interval
Didn't get the point! can you state an example? Doesn't "1" imply 1 ticks? On 11/23/12, Ali Saidi wrote: > You need at specify a time.. 1 has no units. > Ali > > On Nov 16, 2012, at 6:00 AM, Mahmood Naderan wrote: > >> Hi >> In the lastest revision, when I use "--prog-interval=1" or >> "--prog-interval 1" it says >> >> TypeError: wrong type '' should be str >> Error setting param AtomicSimpleCPU.progress_interval to 1 >> >> According to the Options.py, it should be integer. >> Why I receive that error? >> >> Regards, >> Mahmood >> >> ___ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] error setting --prog-interval
Hi In the lastest revision, when I use "--prog-interval=1" or "--prog-interval 1" it says TypeError: wrong type '' should be str Error setting param AtomicSimpleCPU.progress_interval to 1 According to the Options.py, it should be integer. Why I receive that error? Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Can Any one Suggest any good tool to Analyze the Source code
I use kdevelop and it is fine. Just import gem5/ and let it parse the source files. On 11/15/12, Steve Reinhardt wrote: > The .cc files are not "managed C++" (whatever that is), they're just plain > old C++. If your Eclipse or whatever doesn't recognize .cc files as plain > C++, you just need to update its mapping from extensions to languages. > > For local analysis, I use cscope; I think it's available as an ubuntu > package, and there's a script in the util directory (util/cscope-index.py) > that correctly builds the index across all the src subdirectories. > Combined with the xemacs xcscope package it's pretty nice, though it only > covers the C++ part of the code. > > We also have an experimental grok server running at grok.gem5.org. > > Steve > > > On Thu, Nov 15, 2012 at 10:53 AM, Paul Rosenfeld > wrote: > >> I imagine you mean something that can jump to a specific function or >> symbol in the tree? I think the go to tool is cscope. It works for C++, >> but >> it's not great since it can't understand namespaces or classes. >> >> There is a tool called "silentbob" supposed to be better for C++, but >> it's >> not maintained anymore. I haven't had any luck with it on large C++ >> codebases (but never tried with gem5). Perhaps you can get it to work. >> http://silentbob.sourceforge.net/ >> >> I was hoping some of the veterans might have some super awesome tool they >> use -- but maybe we're all stuck without a good answer. >> >> On Wed, Nov 14, 2012 at 11:07 AM, mir shan wrote: >> >>> >>> Hi Community >>> Suggest any tool for analyzing the source files. >>> I try eclipse but it supports c/c++ and Gem5 has .cc files (Managed c++) >>> I couldn't find any plugin in Eclipse for .cc files. An other Software >>> "SourceInsight" but linux doesn't support this. >>> >>> Thanks and regards >>> Mir >>> * >>> * >>> >>> ___ >>> gem5-users mailing list >>> gem5-users@gem5.org >>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>> >> >> >> ___ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] MSHR full status
>Does that mean for each core I have 10 mshrs Right >Also is there any way to differentiate which CACHE this MSHR belongs to, L1 >cache or L2 cache or others? There is a bool variable "isTopLevel" in cache_impl.hh that you can differenciate cache levels. For L1 it is 1 an for L2 it is 0. On 11/8/12, Xi Chen wrote: > Hi all, > > > > I think I found in mshr_queue.hh, there is a function called isFull() which > can tell whether MSHR is full or not. My following question is that: I run > with ruby+alpha+garnet. Will this MSHR still work with Ruby or it just work > with simple classic memory? Also is there any way to differentiate which > CACHE this MSHR belongs to, L1 cache or L2 cache or others? > > > > Thanks, > > xi > > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] About L1 dcache prefetcher
So, you don't have system.cpu0.dcache.prefetcher ? On 11/8/12, IC wrote: > Hello, > > When I enable stride prefetcher on L1 dcache, and run timing mode on 4 > cores configuration, > > The stats.txt shows that only one core (core1) has prefetch statistics.The > number are zero on other core's prefetcher. > > system.cpu1.dcache.prefetcher.prefetcher.num_hwpf_identified > 10455 # number of hwpf identified > system.cpu1.dcache.prefetcher.prefetcher.num_hwpf_already_in_mshr > 0 # number of hwpf that were already in mshr > system.cpu1.dcache.prefetcher.prefetcher.num_hwpf_already_in_cache > 358 # number of hwpf that were already in the cache > system.cpu1.dcache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher > 0 # number of hwpf that were already in the prefetch > queue > system.cpu1.dcache.prefetcher.prefetcher.num_hwpf_evicted >0 # number of hwpf removed due to no > buffer left > system.cpu1.dcache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit > 0 # number of hwpf removed because MSHR > allocated > system.cpu1.dcache.prefetcher.prefetcher.num_hwpf_issued > 10097 # number of hwpf issued > system.cpu1.dcache.prefetcher.prefetcher.num_hwpf_span_page > 154 # number of hwpf spanning a virtual page > system.cpu1.dcache.prefetcher.prefetcher.num_hwpf_squashed_from_miss > 0 # number of hwpf that got squashed due to a miss > aborting calculation time > > The behavior just likes only core1 enables the prefetcher. > > What is the reason of the problem? > > Thanks! > > My command are: > First time: > ./build/X86/m5.fast ./configs/example/fs.py --cpu-type=atomic > -n4 --script=/Barnes_core4 > and will create a checkpoint file before ROI part. > > Second time: > ./build/X86/m5.fast ./configs/example/fs.py --cpu-type=timing > -n4 --caches --l2cache -r1 > restore from checkpoint, and run simulation on timing mode. > -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] gem5-installation freezing
>bash: -/.bashrc: No such file or directory So you can create this file manually. >cp: cannot stat `/home/talpur/bench.c': No such file or directory Simple. You don't have `/home/talpur/bench.c'. check the path -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] gem5-installation freezing
>bash: -/.bashrc: No such file or directory So you are not using bash. what is you shell? csh? zsh?... -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] memory bandwidth
Currently, I use an older version of gem5. Is there any rough estimation on that? Regards, Mahmood On Fri, Nov 2, 2012 at 12:19 AM, Andreas Hansson wrote: > If you use a recent version of gem5 the SimpleMemory has a bandwidth > parameter. > > I would suggest using the DRAM controller model, SimpleDRAM and configure > the timing accordingly. > > Andreas > > On 01/11/2012 20:52, "Mahmood Naderan" wrote: > > >Hi > >How can I calculate the PhysicalMemory bandwidth? Is that infinite in > >gem5? > > > >-- > >Regards, > >Mahmood > >___ > >gem5-users mailing list > >gem5-users@gem5.org > >http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] memory bandwidth
Hi How can I calculate the PhysicalMemory bandwidth? Is that infinite in gem5? -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] --debug-flag Cache trace file information
Basically, for every address you can do Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1); to find the block address. -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] --debug-flag Cache trace file information
That mesage is printed in cache_impl.hh (Cache::access). Just see the code and you will find that this is not the block address. -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] nan in stats file
>There are lot of statas with 0 value I mean which stat is nan? >For example, switch_cpu1.numCycles If that stat is zero, then it means you didn't switch the cpu from atomic to detailed or timing (though I don't kniw what you ran). -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] nan in stats file
What is the stat then? Regards, Mahmood On Fri, Oct 26, 2012 at 3:26 PM, Runjie Zhang wrote: > Good point! They are ratios. So I guess my real questions is, why gem5 > reports 0 cycle? > > Thanks! > Runjie > > -- > > Message: 3 > Date: Fri, 26 Oct 2012 09:47:30 +0200 > From: Mahmood Naderan > To: gem5 users mailing list > Subject: Re: [gem5-users] nan in stats file > Message-ID: > < > cada2p2v9ydfjrmya3wpwozvmug34r82vlfuysgpfkx43ubp...@mail.gmail.com> > Content-Type: text/plain; charset="iso-8859-1" > > > Hi, > Are these single stats or ratios? > > Regards, > Mahmood > > > > On Fri, Oct 26, 2012 at 3:47 AM, Runjie Zhang wrote: > > > Hello, > > > > I simulated Parsec2.1 benchmark suites with X86_MOESI_hammer and O3 > cpu. > > I also dumpreset stats frequently to monitor processor activity. > > > > When I simulate only 1 core, things look fine but when I go to multi > > cores, some cpus, not all, reports nan values. Does this indicate the cpu > > is idling? > > > > Thanks! > > Runjie > > > > CS@UVA > > > > ___ > > gem5-users mailing list > > gem5-users@gem5.org > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] nan in stats file
Hi, Are these single stats or ratios? Regards, Mahmood On Fri, Oct 26, 2012 at 3:47 AM, Runjie Zhang wrote: > Hello, > > I simulated Parsec2.1 benchmark suites with X86_MOESI_hammer and O3 cpu. > I also dumpreset stats frequently to monitor processor activity. > > When I simulate only 1 core, things look fine but when I go to multi > cores, some cpus, not all, reports nan values. Does this indicate the cpu > is idling? > > Thanks! > Runjie > > CS@UVA > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Running List of Programs
If you search the list archive, you will find the benchamrks (from spec2k6) that are not runnable in SE mode. I think those syscalls for x86 are still unimplemented expecially the ones needed for CFP benchmarks. Some can be bypassed by simply ignoring the syscall or borrowing from ALPHA. -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] How to compute CPU utilization rate from stats.txt
system.switch_cpus.idleCycles seems to be a new stat because I don't have that in my stats. If you are talking about "unscheduled due to idling", then I think you should look at idle cycles at IEW stage. If cpu is idle in decode stage, are you going to include that? -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] numThreads in BaseCPU.py
yes. If you want to change issue width, have a look at issueWidth in o3/O3PU.py -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Access icache every cycle
How about *not to* push cache latencies in to the queue? Though I am not quite sure about if this is correct. Regards, Mahmood On Mon, Oct 22, 2012 at 10:58 PM, Runjie Zhang wrote: > Greetings, > > I tried to write stressmarks in X86 assembly so that the simulated IPC > or O3CPU can hit N for a N-way out-of-order core. However, no matter how I > modify the assembly, the IPC could never reach 4 for a 4-way OoO core. > > According to the execution trace, icache stall was the trouble maker. In > my case, even if the whole program fits in icache, the fetch unit still > stalls for a few cycles between fetching 32 instructions over 8 cycles(I > assume 32 X86 ADD instructions fill one cache line?). With Gem5 memory > system (no Ruby), this latency is 2 cycles. With Ruby memory, this latency > is 3 cycles. > > So my questions are: > > 1. Since Gem5 does not accept a zero hit latency, is there a way to > access icache every cycle without any stall? Let's assume there are no > icache misses. > > 2. The icache hit latencies for both Ruby memory and Gem5 memory cores > were 2 cycles, why the Ruby case experienced an extra cycle stall? > > I was running Full System Gem5(changeset: 9305:ac608464be80) with X86 > ISA and single detailed CPU. For Ruby, I used MOESI_hammer protocol. > > > Thanks! > > Runjie Zhang > University of Virginia > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Problems with McPAT and gem5
I remember that "Andreas Hansson" said a json format is under development
which will close the gap between gem5 and mcpat. Any news for that?
Regards,
Mahmood
On Mon, Oct 22, 2012 at 3:44 AM, Amin Farmahini wrote:
> Hi Hongyuan,
>
> I wonder if you have made any progress on using the McPAT script (
> m5_mcpat.pl) for gem5? I'd like to use that script to automatically get
> power numbers. So I was wondering if you could share your exprience or your
> updated script so lazy engineers like me save some time.
>
> Thanks,
> Amin
>
> On Fri, Oct 5, 2012 at 7:57 AM, Erik Tomusk wrote:
>
>> Hi Hongyuan,
>>
>> From my personal experience, tool #1 has been broken for quite some time
>> and when I looked at it, it was far too complicated for me to
>> reverse-engineer and fix.
>>
>> I've had much more success with #2, but for various reasons, I can't make
>> my updated version available yet. It probably wouldn't do what you need it
>> to anyway.
>>
>> #2 might look a bit complex, but all it does is take a template McPAT XML
>> file (mcpat-template.xml) and plug in values from gem5's config.ini and
>> stats.txt. Most of the values in mcpat-template.xml are hardwired, but some
>> are of the form value="{...}". The script just replaces everything inside
>> {} with values from gem5.
>>
>> If I remember correctly, the problems with tool #2 are that the format of
>> stats.txt has changed slightly, there are some values in the template that
>> shouldn't be hardwired but are, and in some cases the template is picking
>> up the wrong value from gem5.
>>
>> To get #2 to work, the first thing you'd need to do is get m5-mcpat.plto
>> correctly fill in the template. Depending on how comfortable you are
>> with Perl, you might be better off rolling your own script in something
>> like Python to complete the template--m5-mcpat.pl has some particularly
>> nasty Perl in it. Then it's just case of figuring out what the values in
>> mcpat-template.xml correspond to in config.ini and stats.txt. Here you can
>> focus on the parameters you're actually researching. For the CPU core, this
>> isn't too difficult; if you're working on something like cache or NoC, it
>> could be hard.
>>
>> Keep in mind that McPAT isn't nearly as configurable as gem5, so a lot of
>> the things you can do in gem5 won't readily translate over to McPAT.
>>
>> Hope this helps.
>>
>> -Erik
>>
>>
>>
>> On 05/10/12 04:26, Ding, Hongyuan wrote:
>>
>> Dear All,
>> I'm new to gem5. Recently I tired to integrate McPAT on gem5. I found two
>> possible tools:
>> 1. m5-mcpat-parse-se.py, http://cseweb.ucsd.edu/~rstrong/
>> 2. m5-mcpat.pl, https://www.cl.cam.ac.uk/~acr31/sicsa/
>>
>> I tried a simple example in gem5 to get the output files:
>> *build/ARM/gem5.opt configs/example/se.py -c
>> tests/test-progs/hello/bin/arm/linux/hello*
>> *
>> *
>> I used m5-mcpat-parse-se.py to transform the output files but got the
>> following error information:
>> *ERROR, UNEXPECTED EXCEPTION *
>> *int() argument must be a string or a number, not 'NoneType' *
>> *Traceback (most recent call last): *
>> * File "m5-mcpat-parse-se.py", line 1896, in *
>> * exit_code = main() *
>> * File "m5-mcpat-parse-se.py", line 1847, in main *
>> * run() *
>> * File "m5-mcpat-parse-se.py", line 1036, in run *
>> * parseSystemConfig(config_file_path, stat_file_path, out_file_path,
>> out_file_path_2, component_hash, stats_hash) *
>> * File "m5-mcpat-parse-se.py", line 1682, in parseSystemConfig *
>> * createComponentTree (cht, sht) *
>> * File "m5-mcpat-parse-se.py", line 1568, in createComponentTree *
>> * generateCalcStats(cht, sht) *
>> * File "m5-mcpat-parse-se.py", line 1494, in generateCalcStats *
>> * cht[options.system_name].statistics["total_cycles"] =
>> str(int(sht["%s.sim_ticks"%(options.system_name)])/int(fastest_clock))*
>> *TypeError: int() argument must be a string or a number, not 'NoneType' *
>> *
>> *
>> I used m5-mcpat.pl to get the xml file and used mcpat-exec.pl to run
>> McPAT, but also got errors:
>> *Parse error (couldn't find runtime_sec in XML file)*
>> *
>> *
>> Then I used McPAT directly to run the XML file generated by m5-mcpat.pl,
>> but got the following error information:
>> *ERROR: no valid tag organizations found*
>> *
>> *
>> I guess these two tools are too old to support the current version of
>> gem5.
>> Does anyone has a modified tools for McPAT integration or some clues on
>> how to fix it?
>> Thank you very much for any comments!
>>
>> --
>> Best regards,
>> Hongyuan Ding
>>
>>
>> ___
>> gem5-users mailing
>> listgem5-users@gem5.orghttp://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>>
>> The University of Edinburgh is a charitable body, registered in
>> Scotland, with registration number SC005336.
>>
>>
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>
>
> ___
Re: [gem5-users] stats.txt
src/base/stats/text.cc what do you want to do? Regards, Mahmood On Tue, Oct 16, 2012 at 11:47 PM, Tianwei Zhang wrote: > source file ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] PARSEC compilation problem
PARSEC has its own mailing list. Regards, Mahmood On Mon, Sep 24, 2012 at 11:11 AM, Ardalan Pouya wrote: > Hello everyone , > I am building PARSEC benchmark and having this error please help me to > solve it : > (OS is Ubuntu 11.04 and I upgraded the openssl to it's latest version) > > > md5-x86_64.s: Assembler messages: > md5-x86_64.s:41: Error: 0xd76aa478 out range of signed 32bit displacement > md5-x86_64.s:50: Error: 0xe8c7b756 out range of signed 32bit displacement > md5-x86_64.s:68: Error: 0xc1bdceee out range of signed 32bit displacement > md5-x86_64.s:77: Error: 0xf57c0faf out range of signed 32bit displacement > md5-x86_64.s:95: Error: 0xa8304613 out range of signed 32bit displacement > md5-x86_64.s:104: Error: 0xfd469501 out range of signed 32bit displacement > md5-x86_64.s:122: Error: 0x8b44f7af out range of signed 32bit displacement > md5-x86_64.s:131: Error: 0x5bb1 out range of signed 32bit displacement > md5-x86_64.s:140: Error: 0x895cd7be out range of signed 32bit displacement > md5-x86_64.s:158: Error: 0xfd987193 out range of signed 32bit displacement > md5-x86_64.s:167: Error: 0xa679438e out range of signed 32bit displacement > md5-x86_64.s:187: Error: 0xf61e2562 out range of signed 32bit displacement > md5-x86_64.s:196: Error: 0xc040b340 out range of signed 32bit displacement > md5-x86_64.s:214: Error: 0xe9b6c7aa out range of signed 32bit displacement > md5-x86_64.s:223: Error: 0xd62f105d out range of signed 32bit displacement > md5-x86_64.s:241: Error: 0xd8a1e681 out range of signed 32bit displacement > md5-x86_64.s:250: Error: 0xe7d3fbc8 out range of signed 32bit displacement > md5-x86_64.s:268: Error: 0xc33707d6 out range of signed 32bit displacement > md5-x86_64.s:277: Error: 0xf4d50d87 out range of signed 32bit displacement > md5-x86_64.s:295: Error: 0xa9e3e905 out range of signed 32bit displacement > md5-x86_64.s:304: Error: 0xfcefa3f8 out range of signed 32bit displacement > md5-x86_64.s:322: Error: 0x8d2a4c8a out range of signed 32bit displacement > md5-x86_64.s:332: Error: 0xfffa3942 out range of signed 32bit displacement > md5-x86_64.s:340: Error: 0x8771f681 out range of signed 32bit displacement > md5-x86_64.s:356: Error: 0xfde5380c out range of signed 32bit displacement > md5-x86_64.s:364: Error: 0xa4beea44 out range of signed 32bit displacement > md5-x86_64.s:380: Error: 0xf6bb4b60 out range of signed 32bit displacement > md5-x86_64.s:388: Error: 0xbebfbc70 out range of signed 32bit displacement > md5-x86_64.s:404: Error: 0xeaa127fa out range of signed 32bit displacement > md5-x86_64.s:412: Error: 0xd4ef3085 out range of signed 32bit displacement > md5-x86_64.s:428: Error: 0xd9d4d039 out range of signed 32bit displacement > md5-x86_64.s:436: Error: 0xe6db99e5 out range of signed 32bit displacement > md5-x86_64.s:452: Error: 0xc4ac5665 out range of signed 32bit displacement > md5-x86_64.s:463: Error: 0xf4292244 out range of signed 32bit displacement > md5-x86_64.s:481: Error: 0xab9423a7 out range of signed 32bit displacement > md5-x86_64.s:490: Error: 0xfc93a039 out range of signed 32bit displacement > md5-x86_64.s:508: Error: 0x8f0ccc92 out range of signed 32bit displacement > md5-x86_64.s:517: Error: 0xffeff47d out range of signed 32bit displacement > md5-x86_64.s:526: Error: 0x85845dd1 out range of signed 32bit displacement > md5-x86_64.s:544: Error: 0xfe2ce6e0 out range of signed 32bit displacement > md5-x86_64.s:553: Error: 0xa3014314 out range of signed 32bit displacement > md5-x86_64.s:571: Error: 0xf7537e82 out range of signed 32bit displacement > md5-x86_64.s:580: Error: 0xbd3af235 out range of signed 32bit displacement > md5-x86_64.s:598: Error: 0xeb86d391 out range of signed 32bit displacement > make[2]: *** [md5-x86_64.o] Error 1 > make[2]: Leaving directory > `/home/ardalan/Desktop/gem5/parsec/parsec-2.1/pkgs/libs/ssl/obj/amd64-linux.gcc/crypto/md5' > make[1]: *** [subdirs] Error 1 > make[1]: Leaving directory > `/home/ardalan/Desktop/gem5/parsec/parsec-2.1/pkgs/libs/ssl/obj/amd64-linux.gcc/crypto' > make: *** [build_crypto] Error 1 > [PARSEC] Error: 'env > PATH=/usr/bin:/home/ardalan/Desktop/gem5/parsec/parsec-2.1/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games > /usr/bin/make' failed. > > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Dealing with a full prefetch queue
>What does correct mean?
I mean, do we have such implementation is a producer/consumer model?
Is this fuctionality correct?
>Do you think a not 'correct' event can occur if the packet is dropped?
Yes and that is a natural problem with a fix sized buffer.
So how do you deal with a full buffer?
In the current implementation, the full buffer is masked since
remove the head and insert a new one. Hence we are not aware
if the producer sends too much packets or the consumer is too slow
processing the received packets. In another word, we have not a 'correct'
view of the prefetch traffic.
Regards,
Mahmood
On Wed, Sep 19, 2012 at 12:13 PM, Nilay Vaish wrote:
> On Wed, 19 Sep 2012, Mahmood Naderan wrote:
>
> Hi
>> In the default prefetch code of gem5, we see
>>
>>// We just remove the head if we are full
>>if (pf.size() == size) {
>>pfRemovedFull++;
>>PacketPtr old_pkt = *pf.begin();
>>DPRINTF(HWPrefetch, "Prefetch queue full, "
>>"removing oldest 0x%x\n", old_pkt->getAddr());
>>delete old_pkt->req;
>>delete old_pkt;
>>pf.pop_front();
>>}
>>
>> That says, if the prefetch queue is full, inserting a new packet will
>> cause
>> the head
>> packet to be removed. I want to know is that really correct?
>>
>
> What does correct mean?
>
>
>
>> Normally in a producer/consumer model, if the receiver is full, wither the
>> sender should
>> wait or receiver should discard the incoming packet (overflow).
>>
>>
> Do you think a not 'correct' event can occur if the packet is dropped?
>
> --
> Nilay
> __**_
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>
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