[gem5-users] Re: SPEC CPU2017 X86 SE mode - instruction 'palignr_Vdq_Wdq_Ib' unimplemented
On 3/13/2023 5:33 PM, Abitha Thyagarajan via gem5-users wrote: Hi Eliot and Mirco, I had the same issue with `palignr_Vdq_Wdq_Ib` being unimplemented. I tried compiling my application binary (i.e., the one I was trying to run on gem5, not gem5 itself) to exclude SSE which contains that instruction. I used gcc flags `-mno-sse3 -mno-ssse3 -mno-sse4.1 -mno-sse4.2 -mno-sse4`. However, I still get the warning message about `palignr_Vdq_Wdq_Ib` being unimplemented. Do either of you have any idea about this? If you had success with resolving this warning by another method, please let me know. Sorry - I have no deep knowledge on this and was only making a suggestion. However, maybe the instruction is coming from a library routine that gets linked in later, and this not from your actual gcc output. You can probably locate the offending instruction using objdump, looking at (searching) the assembly code of a fully linked executable. If it *is* a library routine, I'm not sure exactly how to get a version that does not use that instruction. Some library routines test hardware ability at run time and choose different function versions based on the result. If the gem5 modeled cpu say "I have SSE", then you may get that version. It may be possible to configure the gem5 cpu without SSE (I've not researched that). I hope this gives you some useful possibilities to pursue. Best - EM ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Re: SPEC CPU2017 X86 SE mode - instruction 'palignr_Vdq_Wdq_Ib' unimplemented
Hi Eliot and Abitha, After Eliot's advice, I also tried to compile spec using the flags you used, and also "-march=nocona". Unfortunately, inspecting the generated assembly, I see that the "palignr" instruction is always present. I'll update you if I manage to compile the binaries without using that instruction. Thank you both. Mirco Il 13/03/23 21:33, Abitha Thyagarajan via gem5-users ha scritto: Hi Eliot and Mirco, I had the same issue with `palignr_Vdq_Wdq_Ib` being unimplemented. I tried compiling my application binary (i.e., the one I was trying to run on gem5, not gem5 itself) to exclude SSE which contains that instruction. I used gcc flags `-mno-sse3 -mno-ssse3 -mno-sse4.1 -mno-sse4.2 -mno-sse4`. However, I still get the warning message about `palignr_Vdq_Wdq_Ib` being unimplemented. Do either of you have any idea about this? If you had success with resolving this warning by another method, please let me know. Thanks, Abitha ___ gem5-users mailing list --gem5-users@gem5.org To unsubscribe send an email togem5-users-le...@gem5.org -- *Mirco Mannino, PhD student * Dipartimento di Ingegneria dell'Informazione e Scienze Matematiche Università degli Studi di Siena___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Re: SPEC CPU2017 X86 SE mode - instruction 'palignr_Vdq_Wdq_Ib' unimplemented
Hi Eliot and Mirco, I had the same issue with \`palignr_Vdq_Wdq_Ib\` being unimplemented. I tried compiling my application binary (i.e., the one I was trying to run on gem5, not gem5 itself) to exclude SSE which contains that instruction. I used gcc flags \`-mno-sse3 -mno-ssse3 -mno-sse4.1 -mno-sse4.2 -mno-sse4\`. However, I still get the warning message about \`palignr_Vdq_Wdq_Ib\` being unimplemented. Do either of you have any idea about this? If you had success with resolving this warning by another method, please let me know. Thanks,\ Abitha ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Re: SPEC CPU2017 X86 SE mode - instruction 'palignr_Vdq_Wdq_Ib' unimplemented
On 3/9/2023 6:45 PM, Mirco Mannino via gem5-users wrote: Hi all, I'm trying to take checkpoints from SimPoints for SPEC CPU 2017 in SE mode. I would like to generate checkpoints for different ISAs (RISCV and X86). So far, I did the following: 1) BBV files created using "qpoints" tool (https://github.com/pranith/qpoints), since "--simpoint-profile", from se.py, was taking too long. 2) For the SimPoints, I used the tool from UCSD (https://cseweb.ucsd.edu/~calder/simpoint/). 3) For the checkpoint generation I used the "--take-simpoint-checkpoint" option from se.py. With RISCV I had no problem to take checkpoints for all the benchmarks of IntRate suite (apart from 502.gcc_r). On the other hand, using X86 I am not able to run several benchmarks of IntRate suite. In particular, the benchmarks that give me problems are: * 500.perlbench_r * 502.gcc_r * 520.omnetpp_r * 523.xalancbmk_r * 557.xz_r I noticed that all the benchmarks that fail with X86 display the following warning several times: "build/X86/arch/x86/generated/exec-ns.cc.inc:27: warn: instruction 'palignr_Vdq_Wdq_Ib' unimplemented" Any hints on how to solve this? Is there a solution other than implementing the "palignr" instruction I am using the last stable version of gem5 (v22.1, commit 5fa484e) What comes to my mind is compiling while telling gcc to use an x86 model that does not have the "offending" instruction. Best - Eliot Moss ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
