Re: LAE instruction

2012-03-07 Thread Ngafei Huang
I think you meant SSAR. This requires another set of setups. To SSAR to other 
than yourself,  you need to be AX authorized.



-Original Message-
From: Micheal Butz michealb...@optonline.net
To: IBM-MAIN IBM-MAIN@bama.ua.edu
Sent: Wed, Mar 7, 2012 7:52 am
Subject: Re: LAE instruction


You are right about LAE vs L.  
As far as being on my dual/pasn list

f Saar then load Arx with 1 will go to secondary with out being on my list
ent from my iPhone
On Mar 6, 2012, at 9:52 PM, Ngafei Huang dailom...@aol.com wrote:
 Chaining these control blocks requires supporting environment and setups as 
ollow:
 
 AR register basing ASNALET needs to be setup.
 
 AR register basing ASXBFTCB needs to be setup.
 
 Instead of LAE R4,TCBRBP, it should be L R4,TCBRBP.
 
 Target address space needs to be on your access-list.
 
 Target address space must be non-swappable.
 
 
 Raymond Wong
 
 
 
 -Original Message-
 From: Micheal Butz michealb...@optonline.net
 To: IBM-MAIN IBM-MAIN@bama.ua.edu
 Sent: Tue, Mar 6, 2012 8:30 pm
 Subject: Re: LAE instruction
 
 
 Or a more practical use of LAE
 
 s chaing thru control blocks from another address space 
 AC. 512
 AM   R3,R3,ASNALET
 .   R3,ASXBFTCB
 SING TCB,R3
 AE.   R4,TCBRBP
 SING R4,RB
 
 
 ent from my iPhone
 On Mar 6, 2012, at 5:53 PM, Rob Scott rsc...@rocketsoftware.com wrote:
 Micheal, 
 
 Putting a bit of meat on the bones to create an example piece of code with 
 omments and notes :
 
 (o) We are going to process a linked list of FOO elements in a dataspace and 
 alculate some random hash value based on a subset of bytes in the FOO_NAME 
 ield.
 (o) This code has been just typed into my e-mail - they may be typos/errors
 (o) WA is the working storage structure/DSECT
 
 
 DO,
ALESERV ADD,STOKEN=WA_FOO_STOKEN,  Add dataspace containing linked list 
 f FOOs
ALET=WA_FOO_ALET,  
AL=WORKUNIT,
   MF=(E,WA_ALESERV_LIST)
DOEXIT (LTR,R15,R15,NZ)Failed - quick exit
SAC512AR-Mode (1)
SYSSTATE ASCENV=ARInform assembler of AR-mode
LR6,WA_FOO_HEADGet head of list
LAMAR6,AR6,WA_FOO_ALETGet dataspace ALET (2) 
USING FOO,R6
DO UNTIL=(ICM,R6,B'',FOO_NEXT,Z)Traverse list (3)
LAER7,FOO_NAMEPoint to FOO_NAME (4)
LAER1,8(,R7)Use R1 for temp pointer (5)
XCWA_HASH,WA_HASHZero hash value
DO FROM=(R14,=AL4(L'FOO_NAME-8))
XRR0,R0
ICR0,0(,R1)Get 1-byte (6)
ALR0,WA_HASHAdd to hash value
STR0,WA_HASHStore new value
LAER1,1(,R1)Next byte of name (6)
ENDDO
NCWA_HASH,=X'00FF'0-255 range for hash
ENDDO
SAC0Inform assembler (7)
SYSSTATE ASCENV=P
 ENDDO(8)
 
 rest of code (9)
 
 Notes :
 
 (1) I think it is always worth having a macro to do both the SAC and the 
 YSSTATE for you in one hit (not shown)- stops you forgetting the SYSSTATE and 
 hat can confuse any macros that follow.
 (2) Loading the ALET in to the AR for the first time - R6 will be able to 
 ddress data in the dataspace
 (3) AR-mode makes traversing data structures in dataspaces easy as you can 
 ust use normal instructions (if you play by the rules)
 (4) Because LAE used and FOO dsect covers R6+AR6 - AR7 will contain ALET for 
 ataspace after instruction executed
 (5) This time we are using R1 to point at 8 bytes into FOO_NAME (for whatever 
 eason) - note that AR1 will get the dataspace ALET
 (6) Loading and using a byte from the dataspace 
 (7) See (1) 
 (8) Assuming all ARs are zero before we start, if the code goes thru 
 uccessfully, then AR1, AR6 and AR7 will contain the ALET of the dataspace here 
 you may wish to consider zeroing the ARs at this point if they are no longer 
 eeded.
 (9) Prudent use of LAM   AR14,AR1,=4A(0) will protect you from unintentional 
 R values in working regs after calling certain system services - you can 
 ever be sure how in-house macros expand.  
 
 Hope this helps
 
 
 Rob Scott
 Lead Developer
 Rocket Software
 275 Grove Street * Newton, MA 02466-2272 * USA
 Tel: +1.781.684.2305
 Email: rsc...@rs.com
 Web: www.rocketsoftware.com
 
 
 -Original Message-
 From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of 
 icheal Butz
 Sent: 06 March 2012 21:53
 To: IBM-MAIN@bama.ua.edu
 Subject: Re: LAE instruction
 
 So  SAC 512
LAE R3,0(,R4)
 
 R3 is CPYA from access R4  right 
 
 -Original Message-
 From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of 
 cKown, John
 Sent: Tuesday, March 06, 2012 4:22 PM
 To: IBM-MAIN@bama.ua.edu
 Subject: Re: LAE instruction
 
 Yes, from the LAE instruction text

Re: LAE instruction

2012-03-07 Thread Ngafei Huang
You are not kidding.

Raymond Wong

-Original Message-
From: Edward Jaffe edja...@phoenixsoftware.com
To: IBM-MAIN IBM-MAIN@bama.ua.edu
Sent: Wed, Mar 7, 2012 10:07 am
Subject: Re: LAE instruction


On 3/7/2012 6:34 AM, Ngafei Huang wrote:
 I think you meant SSAR. This requires another set of setups. To SSAR to other 
han yourself,  you need to be AX authorized.
Thankfully, SSAR doesn't work with reusable ASIDs. Best to avoid it completely.
-- 
dward E Jaffe
hoenix Software International, Inc
31 Parkview Drive North
l Segundo, CA 90245
10-338-0400 x318
dja...@phoenixsoftware.com
ttp://www.phoenixsoftware.com/
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Re: LAE instruction

2012-03-06 Thread Ngafei Huang
Chaining these control blocks requires supporting environment and setups as 
follow:

AR register basing ASNALET needs to be setup.

AR register basing ASXBFTCB needs to be setup.

Instead of LAE R4,TCBRBP, it should be L R4,TCBRBP.

Target address space needs to be on your access-list.

Target address space must be non-swappable.


Raymond Wong



-Original Message-
From: Micheal Butz michealb...@optonline.net
To: IBM-MAIN IBM-MAIN@bama.ua.edu
Sent: Tue, Mar 6, 2012 8:30 pm
Subject: Re: LAE instruction


Or a more practical use of LAE

s chaing thru control blocks from another address space 
AC. 512
AM   R3,R3,ASNALET
.   R3,ASXBFTCB
SING TCB,R3
AE.   R4,TCBRBP
SING R4,RB


ent from my iPhone
On Mar 6, 2012, at 5:53 PM, Rob Scott rsc...@rocketsoftware.com wrote:
 Micheal, 
 
 Putting a bit of meat on the bones to create an example piece of code with 
omments and notes :
 
 (o) We are going to process a linked list of FOO elements in a dataspace and 
alculate some random hash value based on a subset of bytes in the FOO_NAME 
ield.
 (o) This code has been just typed into my e-mail - they may be typos/errors
 (o) WA is the working storage structure/DSECT
 
 
 DO,
ALESERV ADD,STOKEN=WA_FOO_STOKEN,  Add dataspace containing linked list 
f FOOs
ALET=WA_FOO_ALET,  
AL=WORKUNIT,
   MF=(E,WA_ALESERV_LIST)
DOEXIT (LTR,R15,R15,NZ)Failed - quick exit
SAC512AR-Mode (1)
SYSSTATE ASCENV=ARInform assembler of AR-mode
LR6,WA_FOO_HEADGet head of list
LAMAR6,AR6,WA_FOO_ALETGet dataspace ALET (2) 
USING FOO,R6
DO UNTIL=(ICM,R6,B'',FOO_NEXT,Z)Traverse list (3)
LAER7,FOO_NAMEPoint to FOO_NAME (4)
LAER1,8(,R7)Use R1 for temp pointer (5)
XCWA_HASH,WA_HASHZero hash value
DO FROM=(R14,=AL4(L'FOO_NAME-8))
XRR0,R0
ICR0,0(,R1)Get 1-byte (6)
ALR0,WA_HASHAdd to hash value
STR0,WA_HASHStore new value
LAER1,1(,R1)Next byte of name (6)
ENDDO
NCWA_HASH,=X'00FF'0-255 range for hash
ENDDO
SAC0Inform assembler (7)
SYSSTATE ASCENV=P
 ENDDO(8)
 
 rest of code (9)
 
 Notes :
 
 (1) I think it is always worth having a macro to do both the SAC and the 
YSSTATE for you in one hit (not shown)- stops you forgetting the SYSSTATE and 
hat can confuse any macros that follow.
 (2) Loading the ALET in to the AR for the first time - R6 will be able to 
ddress data in the dataspace
 (3) AR-mode makes traversing data structures in dataspaces easy as you can 
ust use normal instructions (if you play by the rules)
 (4) Because LAE used and FOO dsect covers R6+AR6 - AR7 will contain ALET for 
ataspace after instruction executed
 (5) This time we are using R1 to point at 8 bytes into FOO_NAME (for whatever 
eason) - note that AR1 will get the dataspace ALET
 (6) Loading and using a byte from the dataspace 
 (7) See (1) 
 (8) Assuming all ARs are zero before we start, if the code goes thru 
uccessfully, then AR1, AR6 and AR7 will contain the ALET of the dataspace here 
 you may wish to consider zeroing the ARs at this point if they are no longer 
eeded.
 (9) Prudent use of LAM   AR14,AR1,=4A(0) will protect you from unintentional 
R values in working regs after calling certain system services - you can 
ever be sure how in-house macros expand.  
 
 Hope this helps

 
 Rob Scott
 Lead Developer
 Rocket Software
 275 Grove Street * Newton, MA 02466-2272 * USA
 Tel: +1.781.684.2305
 Email: rsc...@rs.com
 Web: www.rocketsoftware.com
 
 
 -Original Message-
 From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of 
icheal Butz
 Sent: 06 March 2012 21:53
 To: IBM-MAIN@bama.ua.edu
 Subject: Re: LAE instruction
 
 So  SAC 512
LAE R3,0(,R4)
 
 R3 is CPYA from access R4  right 
 
 -Original Message-
 From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of 
cKown, John
 Sent: Tuesday, March 06, 2012 4:22 PM
 To: IBM-MAIN@bama.ua.edu
 Subject: Re: LAE instruction
 
 Yes, from the LAE instruction text:
 
 quote
 The address specified by the X2, B2, and D2 fields is placed in general 
egister R1. Access register R1 is loaded with a value that depends on the 
urrent value of the address-space-control bits, bits 16 and
 17 of the PSW. If the address-space-control bits are
 01 binary, the value placed in the access register also depends on whether the 
2 field is zero or non- zero.
 
 ...
 
 PSW Bits
 16 and 17
 Value Placed in Access Register R1
 00  hex (zeros in bit positions 0-31)
 
 10 0001 hex (zeros in bit positions 0-30 and one in bit position 

Re: S402 ABEND upon cross-memory POST

2011-12-12 Thread Ngafei Huang
-Original Message-
From: Justin R. Bendich jbend...@austin.rr.com
To: IBM-MAIN IBM-MAIN@bama.ua.edu
Sent: Mon, Dec 12, 2011 12:31 pm
Subject: S402 ABEND upon cross-memory POST


I am attempting a cross-memory POST and receiving a S402 ABEND, RSN=0.
ere is the environment:
The code is running in key zero, AMODE 31, ASC=PRIMARY, PASN=HASN=SASN .
It is running out of a FRR for a SRB.
The macro invocation is specified as follows:
POST  THE_ECB,0,ASCB=(2),ERRET=LBL1,ECBKEY=7,LINKAGE=SYSTEM,MF=(E,PL_LIST)
R2 addresses the correct ASCB.
The ECB resides in CSA.
The key of the ECB is, indeed, 7.
The code at LBL1 (the ERRET) is XL2'07FE' (BR R14).
The parameter list ends up looking like:
 X'00'(R1): ecb address
X'04'(R1): ASCB address
X'08'(R1): ERRET address
X'0C'(R1): A(X'7000')
There does not appear to be anything wrong with it.
There is a task whose PSW key is zero which has issued
n EVENTS macro whose table includes the ECB in question.
The home address space of that task is described by the
assed ASCB.
The table for the EVENTS macro is in key-8 storage.
Thank you for any information you might be able to provide,
Justin R. Bendich
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Re: S402 ABEND upon cross-memory POST

2011-12-12 Thread Ngafei Huang
Can you clarify what you mean by There is a task whose PSW key is zero which 
has issued
an EVENTS macro whose table includes the ECB in question. 

Because as far as I know EVENT table does not own ECBs. It is the ECBs that 
reference the event table.


Raymond Wong



-Original Message-
From: Justin R. Bendich jbend...@austin.rr.com
To: IBM-MAIN IBM-MAIN@bama.ua.edu
Sent: Mon, Dec 12, 2011 12:31 pm
Subject: S402 ABEND upon cross-memory POST


I am attempting a cross-memory POST and receiving a S402 ABEND, RSN=0.
ere is the environment:
The code is running in key zero, AMODE 31, ASC=PRIMARY, PASN=HASN=SASN .
It is running out of a FRR for a SRB.
The macro invocation is specified as follows:
POST  THE_ECB,0,ASCB=(2),ERRET=LBL1,ECBKEY=7,LINKAGE=SYSTEM,MF=(E,PL_LIST)
R2 addresses the correct ASCB.
The ECB resides in CSA.
The key of the ECB is, indeed, 7.
The code at LBL1 (the ERRET) is XL2'07FE' (BR R14).
The parameter list ends up looking like:
 X'00'(R1): ecb address
X'04'(R1): ASCB address
X'08'(R1): ERRET address
X'0C'(R1): A(X'7000')
There does not appear to be anything wrong with it.
There is a task whose PSW key is zero which has issued
n EVENTS macro whose table includes the ECB in question.
The home address space of that task is described by the
assed ASCB.
The table for the EVENTS macro is in key-8 storage.
Thank you for any information you might be able to provide,
Justin R. Bendich
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Re: Opening a Spanned File for Input Using Assembler

2011-03-08 Thread Ngafei Huang
Maybe you want to give amode 24 a try.




-Original Message-
From: Bruce Hunt bruce.h...@trs.state.tx.us
To: IBM-MAIN@bama.ua.edu
Sent: Tue, Mar 8, 2011 10:43 am
Subject: Opening a Spanned File for Input Using Assembler


I an trying to read a spanned file that has a record organzation of PS, a 
record 
format of VBS, a record length of 1, a blocksize of 27998 as per the file 
ttributes, and a possible real record length of 65535. But in trying to open 
ne file I get a SOC4. I am not the greatest Assembler coder but my program 
s pretty simple. I know it is abending on the open. Anyone have any ideas. My 
ctual input records in the spanned file are header records that are 76 bytes, 
ata records that are 136 bytes, and trailer records that are 28 bytes. Any 
elp will be greatly appreciated.
 TITLE 'XP1000' 
   
 02/25/11  B HUNT   CHANGED A SPANNED FILE TO A FIXED FILE 
   
P1000   AMODE 31   
P1000   RMODE ANY  
P1000   START  
COPY  EQUATES  
SAVE  (14,12) SAVE REGISTERS 14 THRU 12
BASR  BASE1,0 ESTABLISH ADDRESSABILITY 
USING *,BASE1 PROVIDE BASE ID  
WTO   ' START XP1000',X
  ROUTCDE=(2),X
  DESC=(7) 
B BEGIN
SPACE 1
DS0D   
DCCL8'XP1000'  
DCCL8'SYSDATE'
DCCL8'SYSTIME'  
SPACE 1  
EGINDS0H 
WTO   ' BEFORE OPEN',ROUTCDE=(2),DESC=(7)
OPEN  (INFILE,INPUT,OUTFILE,OUTPUT)  
LTR   15,15  
BNZ   BADOPEN
WTO   ' GOOD OPEN FILE',ROUTCDE=(2),DESC=(7) 
OOP DS 0H
GET   INFILE,INREC   
WTO   ' GOOD FILE READ',ROUTCDE=(2),DESC=(7) 
MVC   BATA,DATA  
WTO   ' GOOD MOVE',ROUTCDE=(2),DESC=(7)  
PUT   OUTFILE,OUTREC 
WTO   ' GOOD FILE WRITE',ROUTCDE=(2),DESC=(7)
B LOOP   
INAL DS 0H   
WTO   ' BEFORE FILE CLOSE',ROUTCDE=(2),DESC=(7)  
CLOSE (INFILE,,OUTFILE)  
WTO   ' GOOD FILE CLOSE',ROUTCDE=(2),DESC=(7)
B C100 
ADOPEN  WTO   ' UABLE TO OPEN FILE',ROUTCDE=(2),DESC=(7)   
B C100 
ADREAD  WTO   ' READ UNSUCCESSFUL ',ROUTCDE=(2),DESC=(7)   
B C100 
ADWRITE WTO   ' WRITE UNSUCCESSFUL ',ROUTCDE=(2),DESC=(7)  
B C100 
100 DS0H   
RETURN (14,12)RESTORE REGISTERS AND RETURN 
NFILE   DCB   DSORG=PS,RECFM=VBS,MACRF=GM,+
  DDNAME=INDD,EODAD=FINAL  
UTFILE  DCB   
SORG=PS,RECFM=FB,LRECL=28,BLKSIZE=2800,MACRF=PM,   +
  DDNAME=OUTDD 
UTREC   DS0CL28
ATA DSCL28 
AVEAREA DS18F  
LTORG  
NRECDS0F   
ATA DSCL28 
DSCL32000  
DSCL32000  
DSCL32000  
END   XP1000   


Re: Opening a Spanned File for Input Using Assembler

2011-03-08 Thread Ngafei Huang
Does the load module linked with RM 24? Maybe it should be.





-Original Message-
From: Hunt, Bruce bruce.h...@trs.state.tx.us
To: IBM-MAIN@bama.ua.edu
Sent: Tue, Mar 8, 2011 2:08 pm
Subject: Re: Opening a Spanned File for Input Using Assembler


I tried BFTEK=A and DCB=BFTEK=A on my input file JCL and still got soc4's but 
hanks.
-Original Message-
rom: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of 
ick Fochtman
ent: Tuesday, March 08, 2011 12:01 PM
o: IBM-MAIN@bama.ua.edu
ubject: Re: Opening a Spanned File for Input Using Assembler
Adding the parameter BFTEK=A will cause the spanned records to be 
e-assembled during input processing, before they are handed to the 
pplication.
Rick
-
ruce Hunt wrote:
I an trying to read a spanned file that has a record organzation of PS, a 
ecord 
format of VBS, a record length of 1, a blocksize of 27998 as per the file 
attributes, and a possible real record length of 65535. But in trying to open 
tne file I get a SOC4. I am not the greatest Assembler coder but my program 
is pretty simple. I know it is abending on the open. Anyone have any ideas. My 
actual input records in the spanned file are header records that are 76 bytes, 
data records that are 136 bytes, and trailer records that are 28 bytes. Any 
help will be greatly appreciated.

 TITLE 'XP1000' 
*   
* 02/25/11  B HUNT   CHANGED A SPANNED FILE TO A FIXED FILE 
*   
XP1000   AMODE 31   
XP1000   RMODE ANY  
XP1000   START  
 COPY  EQUATES  
 SAVE  (14,12) SAVE REGISTERS 14 THRU 12
 BASR  BASE1,0 ESTABLISH ADDRESSABILITY 
 USING *,BASE1 PROVIDE BASE ID  
 WTO   ' START XP1000',X
   ROUTCDE=(2),X
   DESC=(7) 
 B BEGIN
 SPACE 1
 DS0D   
 DCCL8'XP1000'  
 DCCL8'SYSDATE'
 DCCL8'SYSTIME'  
 SPACE 1  
BEGINDS0H 
 WTO   ' BEFORE OPEN',ROUTCDE=(2),DESC=(7)
 OPEN  (INFILE,INPUT,OUTFILE,OUTPUT)  
 LTR   15,15  
 BNZ   BADOPEN
 WTO   ' GOOD OPEN FILE',ROUTCDE=(2),DESC=(7) 
LOOP DS 0H
 GET   INFILE,INREC   
 WTO   ' GOOD FILE READ',ROUTCDE=(2),DESC=(7) 
 MVC   BATA,DATA  
 WTO   ' GOOD MOVE',ROUTCDE=(2),DESC=(7)  
 PUT   OUTFILE,OUTREC 
 WTO   ' GOOD FILE WRITE',ROUTCDE=(2),DESC=(7)
 B LOOP   
FINAL DS 0H   
 WTO   ' BEFORE FILE CLOSE',ROUTCDE=(2),DESC=(7)  
 CLOSE (INFILE,,OUTFILE)  
 WTO   ' GOOD FILE CLOSE',ROUTCDE=(2),DESC=(7)
 B C100 
BADOPEN  WTO   ' UABLE TO OPEN FILE',ROUTCDE=(2),DESC=(7)   
 B C100 
BADREAD  WTO   ' READ UNSUCCESSFUL ',ROUTCDE=(2),DESC=(7)   
 B C100 
BADWRITE WTO   ' WRITE UNSUCCESSFUL ',ROUTCDE=(2),DESC=(7)  
 B C100 
C100 DS0H   
 RETURN (14,12)RESTORE REGISTERS AND RETURN 
INFILE   DCB   DSORG=PS,RECFM=VBS,MACRF=GM,+
   DDNAME=INDD,EODAD=FINAL  
OUTFILE  DCB   
DSORG=PS,RECFM=FB,LRECL=28,BLKSIZE=2800,MACRF=PM,   +
   DDNAME=OUTDD 

Re: PSATOLD = 0 when under PRB !?!?

2009-12-17 Thread Ngafei Huang
Such a suggestion.  VTAM exits can also run under SRB.  How about make sure 
that is not the case.

Raymond Wong


-Original Message-
From: Thompson, Steve steve_thomp...@stercomm.com
To: IBM-MAIN@bama.ua.edu
Sent: Wed, Dec 16, 2009 11:26 am
Subject: Re: PSATOLD = 0 when under PRB !?!?


-Original Message-
rom: IBM Mainframe Discussion List [mailto:ibm-m...@bama.ua.edu] On
ehalf Of Edward Jaffe
ent: Wednesday, December 16, 2009 11:08 AM
o: IBM-MAIN@bama.ua.edu
ubject: Re: PSATOLD = 0 when under PRB !?!?
Thompson, Steve wrote:
 So the question that I have is, under what conditions can PSATOLD be
 zero? From days gone by, this would seem to be some kind of
ispatching
 bug if this is not set prior to dispatching a program that is PRB
ased.
   
Our code uses PSATOLD=0 as a way to check whether we're in SRB mode.
SNIP
We have NO SRB code in this case. NONE, NADA, ZILCH.
But the code path taken is only done with PSATOLD = zero. 
There are two of us here who say this is impossible (I'm one). But here
e are, and we have seen this at 1.7, 1.9, and 1.10 (that I know about).
nd it is only here and there.
So there must be some other way for PSATOLD to be zero. And that's all
'm asking: SRB does it, what else does it? Do IRBs? Because we do use
RBs from time to time (we do use VTAM).
Regards,
teve Thompson
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Re: ERRET completion code for asynch cross mem POST

2009-01-22 Thread Ngafei Huang
Authorized Assembler Services References, volume 3, SA22-7611


-Original Message-
From: Jim Whitehurst j...@jimwhitehurst.com
To: IBM-MAIN@bama.ua.edu
Sent: Thu, 22 Jan 2009 11:01 am
Subject: ERRET completion code for asynch cross mem POST



Can anyone point me to documention on interpreting the contents of Reg 3 on 
entry to an ERRET routine from the POST macro?

Thanks

Jim Whitehurst

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Re: Basic Cross Memory questions

2007-12-18 Thread Ngafei Huang
If you absolutely need to run with EAX in your PC routine, I think in your case 
you may want to just set the AX to 1 for your PC routine provider space (as the 
way it is now).? And for the PCRTN EAX, reserve a different AX for it.? But for 
the EAX to work, you need to go through the necessary setup, e.g, again, ATSET.


Raymond Wong

Boston,? MA


-Original Message-
From: Binyamin Dissen [EMAIL PROTECTED]
To: IBM-MAIN@BAMA.UA.EDU
Sent: Tue, 18 Dec 2007 2:24 am
Subject: Re: Basic Cross Memory questions




On Mon, 17 Dec 2007 21:59:21 -0800 Henry Willard [EMAIL PROTECTED]
wrote:

:Logan, David wrote:

: Even with my AXSET, I still get a S052/319 ABEND at the ETCRE macro. I
: have no idea why. My code looks right based on what I think I know. What
: am I doing wrong?

:  MODESET MODE=SUP,KEY=ZERO
: GETAXDS0H
:  LA6,1
:  AXSET AX=(6)
:  MVC   LXCOUNT,=F'1'
: GETLXWTO   'BEFORE LXRES'
: XETLXLXRES LXLIST=LXL,SYSTEM=YES
:  WTO   'AFTER LXRES'
:  L 5,PCRTNADR
:  ETDEF TYPE=SET,ETEADR=ETD1,ROUTINE=(5),EAX=(6),AKM=(0:15),X
:SSWITCH=YES,STATE=SUPERVISOR,EKM=(0:15),PKM=OR, X
:ASCMODE=AR
:  WTO   'AFTER ETDEF'-- Last WTO to be written
: CET1 ETCRE ENTRIES=ETDESC
:  WTO   'AFTER ETCRE'
:  ST   0,TKVALUE
:  MODESET MODE=PROB,KEY=NZERO
:  EDCEPIL

:Get rid of the EAX altogether.

Ditto.

You will be running with AX=1 in the PC routine.

Also, you will need an ETCON.

--
Binyamin Dissen [EMAIL PROTECTED]
http://www.dissensoftware.com

Director, Dissen Software, Bar  Grill - Israel


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Re: Basic Cross Memory questions

2007-12-17 Thread Ngafei Huang
Correct me if I am wrong on this.? I think system LX or non, if you have a 
SSWITCH=YES requirement, i.e., use private instead of common, you must have the 
AX ATSET to the client space. Of course unless you're talking AX=1


Raymond Wong




-Original Message-
From: Logan, David [EMAIL PROTECTED]
To: IBM-MAIN@BAMA.UA.EDU
Sent: Mon, 17 Dec 2007 8:10 am
Subject: Re: Basic Cross Memory questions




SSWITCH=NO means you put your system LX PC routine into common storage?
LPA or LOAD GLOBAL=YES? Having the system LX validate the client and set
up the non-system LX makes sense.

You also implied the answer to my question about not having an
AXRES/ATSET for a system LX.

David Logan

-Original Message-
From: IBM Mainframe Discussion List [mailto:[EMAIL PROTECTED] On
Behalf Of Rob Scott
Sent: Monday, December 17, 2007 7:02 AM
To: IBM-MAIN@BAMA.UA.EDU
Subject: Re: Basic Cross Memory questions

David,

Believe me this is possible as I use it for my products :

(o) APF-auth server code issues LXRES, ETDEF, ETCRE and ETCON for a
System-LX
(o) APF-auth server code also builds one or more non-system LXs for
other PC routines
(o) The system-LX PC routine's only function is to validate client
authority to the product (RACROUTE) and connect/disconnect the client
(ATSET and ETCON/ETDIS) to the non-system LX (the code that is the
meat of the product).

Here is the definition for the system-LX :

ETDEF TYPE=SET,ETEADR=ETTBSYS1,
  ROUTINE=(R7),
  ARR=(R9),
  PC=STACKING,
  ASCMODE=PRIMARY,
  SSWITCH=NO,
  SASN=OLD,
  STATE=SUPERVISOR,
  RAMODE=31,
  AKM=(0:15),
  EK=(0)
ETCRE ENTRIES=ETTBSYSCreate the Entry Table
STCM  R0,B'',TKVALUE
MVC   TKCOUNT,=F'1'  Set # ET tokens
ETCON LXLIST=LXL,Connect LX to Entry Table
  TKLIST=TKL,
  MF=(E,ETCONL)




Rob Scott
Rocket Software, Inc
275 Grove Street
Newton, MA 02466
617-614-2305
[EMAIL PROTECTED]


-Original Message-
From: IBM Mainframe Discussion List [mailto:[EMAIL PROTECTED] On
Behalf Of Logan, David
Sent: 17 December 2007 13:19
To: IBM-MAIN@BAMA.UA.EDU
Subject: Re: Basic Cross Memory questions

I believe I understand the ETDEF options. Took me a bit, because the
authorization and execution key parameters are a bit complicated.

But this fact remains:  The client only needs to issue an ATSET, which
does require authorization. -- and as long as this is true, I need an
SVC, since this seems to be the best way to get my client connected to
my server.

If there is a better way than an SVC, I would love to hear about it.

Also, this means that there is no reason whatsoever to use a system LX,
since I need to be in supervisor state anyway for the ATSET. I might as
well go ahead after that and connect my LX/entry table at the same time.
There is no way to get around the supervisor state requirement for
client (i.e. problem program) setup.

David Logan

-Original Message-
From: IBM Mainframe Discussion List [mailto:[EMAIL PROTECTED] On
Behalf Of Binyamin Dissen
Sent: Monday, December 17, 2007 6:10 AM
To: IBM-MAIN@BAMA.UA.EDU
Subject: Re: Basic Cross Memory questions

On Mon, 17 Dec 2007 07:51:56 -0500 Logan, David [EMAIL PROTECTED]
wrote:

:Apologies, you are right...I was writing from memory, and
:mis-remembered. The client needs an AXSET and an ETCON. The only way
to :issues AXSET and ETCON seems to be in supervisor state. The only
way for :a problem program to gain access to supervisor state code
seems to be :via an SVC.

The client only needs to issue an ATSET, which does require
authorization.

:I tried using a system LX, and removed the above setup. I get a S0C2
in :the client. This indicates to me that even WITH a system LX, I
still :need an SVC to issue the ATSET and the ETCON.

Depends on how you define the PC. It can be defined as requiring
supervisor state/system key, or acceptable in problem state. It can be
defined as switching to supervisor state, or staying in problem state.

Look carefully at the ETDEF operands.

--
Binyamin Dissen [EMAIL PROTECTED]
http://www.dissensoftware.com

Director, Dissen Software, Bar  Grill - Israel


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Re: TPROT condition code

2007-12-13 Thread Ngafei Huang
Can happen when the page has been paged out or?the page is not accessible or 
simply means no such page.

Raymond Wong


-Original Message-
From: Miklos Szigetvari [EMAIL PROTECTED]
To: IBM-MAIN@BAMA.UA.EDU
Sent: Thu, 13 Dec 2007 10:37 am
Subject: TPROT condition code


Hi?
?
? A question about the TPROT condition code 3, translation not available:?
Can happen if the referenced address paged out, or it is already an error 
condition ??
?
-- Miklos Szigetvari?
?
Development Team?
ISIS Information Systems Gmbh tel: (+43) 2236 27551 570?
Fax: (+43) 2236 21081 ?
E-mail: [EMAIL PROTECTED] ?
Info: [EMAIL PROTECTED] Hotline: +43-2236-27551-111 ?
Visit our Website: http://www.isis-papyrus.com 
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Re: TPROT condition code

2007-12-13 Thread Ngafei Huang
Getmained storage can be paged out and?TPROT can get cc 3 because of it.?


-Original Message-
From: Michael Poil [EMAIL PROTECTED]
To: IBM-MAIN@BAMA.UA.EDU
Sent: Thu, 13 Dec 2007 11:26 am
Subject: Re: TPROT condition code




Can happen when the page has been paged out or?the page is not accessible 
or simply means no such page.


Not due to  a normal page fault. This is fixed up by z/OS under the 
covers after it gets the program check 11. Referencing an invalid page in 
the Address Space (i..e not getmained) will give you a S0C4.

--
Mike Poil
Java z/OS Level 3 Service
IBM United Kingdom Limited, Hursley Park, Winchester SO21 2JN
Internal: 246824  External: +44 (0)1962 816824 
Java debugging: http://www.ibm.com/developerworks/java/jdk/diagnosis/
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Re: TPROT condition code

2007-12-13 Thread Ngafei Huang
I would??TPROT first and only if cc 3 before issuing VSMLOC to save a few 
cycles.

Raymond Wong

-Original Message-
From: Wayne Driscoll [EMAIL PROTECTED]
To: IBM-MAIN@BAMA.UA.EDU
Sent: Thu, 13 Dec 2007 11:53 am
Subject: Re: TPROT condition code




Yes, getmained storage can be paged out, unless it is in a page fixed
subpool, or has been page fixed by the application.  As for TPROT, it
doesn't really help to determine if a page is valid, just if it is paged
in.  A cc=3 could be that a page fault will occur OR the page is
invalid, so you still need to deal with a possible S0C4.  If you are
attempting to determine if a piece of storage is valid, use VSMLOC.

Wayne Driscoll
Product Developer
JME Software LLC
NOTE:  All opinions are strictly my own.



-Original Message-
From: IBM Mainframe Discussion List [mailto:[EMAIL PROTECTED] On
Behalf Of Ngafei Huang
Sent: Thursday, December 13, 2007 11:42 AM
To: IBM-MAIN@BAMA.UA.EDU
Subject: Re: TPROT condition code

Getmained storage can be paged out and?TPROT can get cc 3 because of
it.?


-Original Message-
From: Michael Poil [EMAIL PROTECTED]
To: IBM-MAIN@BAMA.UA.EDU
Sent: Thu, 13 Dec 2007 11:26 am
Subject: Re: TPROT condition code




Can happen when the page has been paged out or?the page is not
accessible 
or simply means no such page.


Not due to  a normal page fault. This is fixed up by z/OS under the 
covers after it gets the program check 11. Referencing an invalid page
in 
the Address Space (i..e not getmained) will give you a S0C4.


--
Mike Poil
Java z/OS Level 3 Service
IBM United Kingdom Limited, Hursley Park, Winchester SO21 2JN
Internal: 246824  External: +44 (0)1962 816824 
Java debugging: http://www.ibm.com/developerworks/java/jdk/diagnosis/

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Re: TPROT condition code

2007-12-13 Thread Ngafei Huang
Getmained storage can be paged out and?TPROT can get cc 3 because of it.?

I was making a statement, wasn't asking questions.? For whatever reason ? was 
inserted amongst the text in my AOL mail. Sorry for the confusion and please 
ignore the ? above.

Raymond Wong


-Original Message-
From: Michael Poil [EMAIL PROTECTED]
To: IBM-MAIN@BAMA.UA.EDU
Sent: Thu, 13 Dec 2007 2:18 pm
Subject: Re: TPROT condition code




No

--
Mike Poil
Java z/OS Level 3 Service
IBM United Kingdom Limited, Hursley Park, Winchester SO21 2JN
Internal: 246824  External: +44 (0)1962 816824 
Java debugging: http://www.ibm.com/developerworks/java/jdk/diagnosis/
--



Ngafei Huang [EMAIL PROTECTED] 
Sent by: IBM Mainframe Discussion List IBM-MAIN@BAMA.UA.EDU
13/12/2007 17:42
Please respond to
IBM Mainframe Discussion List IBM-MAIN@BAMA.UA.EDU


To
IBM-MAIN@BAMA.UA.EDU
cc

Subject
Re: TPROT condition code






Getmained storage can be paged out and?TPROT can get cc 3 because of it.?


-Original Message-
From: Michael Poil [EMAIL PROTECTED]
To: IBM-MAIN@BAMA.UA.EDU
Sent: Thu, 13 Dec 2007 11:26 am
Subject: Re: TPROT condition code




Can happen when the page has been paged out or?the page is not accessible 
or simply means no such page.


Not due to  a normal page fault. This is fixed up by z/OS under the 
covers after it gets the program check 11. Referencing an invalid page in 
the Address Space (i..e not getmained) will give you a S0C4.

--
Mike Poil
Java z/OS Level 3 Service
IBM United Kingdom Limited, Hursley Park, Winchester SO21 2JN
Internal: 246824  External: +44 (0)1962 816824 
Java debugging: http://www.ibm.com/developerworks/java/jdk/diagnosis/
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Re: Mainframe Assembler Coding Contest

2007-12-12 Thread Ngafei Huang
Just uploaded EZSAMPLE for #6.


Raymond Wong
Brookline, MA



-Original Message-
From: Don Higgins [EMAIL PROTECTED]
To: IBM-MAIN@BAMA.UA.EDU
Sent: Wed, 12 Dec 2007 6:50 am
Subject: Mainframe Assembler Coding Contest



There is a new Mainframe Assembler Coding Contest underway here:

http://z390.sourceforge.net/z390_Mainframe_Assemble_Coding_Contest.htm

I've just added direct link to Powerpoint presentation by Khristine Harper on 
Asembler in the 21 Century.  There is also a new link to upcoming SHARE 
session search page where if you select search by topic, you will find 22 
sessions on mainframe assembler.  There are also now links to the online POP, 
HLASM, and z390 references.

This contest is intended to help new assembly language programmers to learn 
the language and for old timers to share some of their knowledge.
you are welcome to submit as many new problems and solutions as you like.
I'm also still looking for a few volunteer judges to help rank solutions.
Even the simplest problems may have numerious solutions with different 
performance and or results on different machines.  Joining the contest email 
group using Yahoo ID provides access to the submitted programs for 
download, assembly, and execution.  The email group is used for posting 
updates on problems and solution rankings along with contributor names and 
school affiliations.  The email group is also for discussion of the submitted 
solutions.

Currently there are 8 problems posted and proposed solutions have been 
posted on the contest group email site for most but not all of them.  Solutions 
consist of ASCII mainframe assembler source programs which can be 
assembled, linked, and executed using www.z390.org open source portable 
mainframe assembler and emulator on Windows or Linux systems.  Check out 
problem #6 submitted by John Erhman for which no solutions have been 
posted yet.

Don Higgins
[EMAIL PROTECTED]

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Re: About dispatching process

2007-10-25 Thread Ngafei Huang
If RB3 is pointed to by TCBRBP, RB3 is newest and is the top RB.  TopRB get 
executed first when the TCB is given control.  The way it’s chained is 
RB3-RBLINK field points to RB2.  RB2-RBLINK points to RB1 and RB1-RBLINK points 
to the TCB.   

 

 

I think to obtain a spin lock (unconditional request) the SETLOCK routine first 
disables then goes into a spin loop to execute a sequence of instructions.  The 
instruction sequences are tests-for-and-if-available-obtain-the-lock, return if 
successful, enable for interrupt, then disable, retry the lock obtain.  So in 
that sense the spin loop is the same as the disabled loop.  The enablement is 
accomplished via the WINDOW macro which enables for external interrupts and 
immediately disables so that emergency signal maybe received.  The number of 
time to loop I think is limited (the detection) by a value set in some system 
area, possibly the CVT.

 

(Of course somewhere within the instruction sequence, it would have to check 
for hierarchy.)

 

 

Regards,

Raymond Wong

Compuware Corp

 





-Original Message-
From: Johnny Luo [EMAIL PROTECTED]
To: IBM-MAIN@BAMA.UA.EDU
Sent: Thu, 25 Oct 2007 7:19 am
Subject: Re: About dispatching process





On 10/24/07, Vernooy, C.P. - SPLXM [EMAIL PROTECTED] wrote:


 
  I think what the manual says is the same as what you said. In a MP
 system, a
  disabled loop is observed as a spin loop by other processors.

 This is not exactly true:
 A disabled loop by itsself will not generate a problem. However, other
 processors will regularly want to talk to the disabled processor, via
 the SIGP instruction. The calling processor will spin (in a disabled
 loop, therefor spin loop) waiting for an answer. The disabled called
 processor will of course not answer and the calling processor will
 detect this and generate an excessive spinloop time out condition. So
 the spinloop is a normal, short duration, situation; an excisive
 spinloop timeout is a condition detected by an active processor, where
 an other processor does not answer. This can be for many reasons, being
 disabled, hardware problems etc. etc.

 Have a look at Initialization and Tuning Reference, member EXCPATxx, for
 more information on spinloops.

his leads me to reconsider my understanding about the process of getting a
pin lock. I used to think what SETLOCK does is just keeping on check the
ockword and running disabled. Then, what is the difference between a spin
oop and a disabled loop?
So my guess is, what SETLOCK does is a 'timed disabled loop'. That is, most
f the time it'll loop disabled but not forever. It will enable the
rocessor regularly thus an excessive spin loop can be detected and handled
y system. Did I miss something here?

 have another question about RB queue/chain. (A little off-topic but at
east it is involved in dispatching process -_-  )
Here is a RB chain after a new RB is added:
TCB -- RB1 -- RB2 -- RB3
I think RB1 is the oldest and RB3 is the newest but is it true?
Then this TCB is dispatched and the RB pointed by TCBRBP will be executed.
hich one? I think it should be RB3 ( the newest)  but I'm not sure.
Thanks,
ohnny
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Re: Using different storage key's

2006-06-29 Thread Ngafei Huang
Just a thought.
 
I think using key zero along with plain MVC instruction is probably the most 
effective way.  But I do think this is the last thing you want to do for 
obvious reasons.
 
If the source areas are not fetch protected, in the PC routine, can you just 
setup your data accessing environment accordingly (e.g. setup your ARs, 
ASCMODE) and just move the data between the 2 areas.
 
Ngafei
 
 
 
-Original Message-
From: Miklos Szigetvari [EMAIL PROTECTED]
To: IBM-MAIN@BAMA.UA.EDU
Sent: Thu, 29 Jun 2006 14:09:52 +0200
Subject: Using different storage key's


Hi 
 
The short question: 
What is the most effective (fast) way to move data between different storage 
keys ? 
 
The longer story: 
We have an FSS application ( running in JESKEY) which starts different user 
programs, and exchange the data with the user programs 
(via SVC screening and access method routine changes ) 
For a long time, the user application was also run in JESKEY.. 
Since a year, the user applications started to use the shared memory (over Uss) 
and we found, it is necesary to run in key 8 to use shared memory 
So now the user applications are running in key8 , and we are using PC routines 
to go into JESKEY, and MVCSK and MVCDK to move data. 
It is working so, but the CPU consumption is much higher as it was before. 
 
How can I solve this ? 
Can I use here KEY=NINE (Storage Protection Override) . 
 
 
-- Mit freundlichen Grüßen / Best regards 
 
Miklos Szigetvari 
 
ISIS Information Systems GmbH 
Alter Wienerweg 12 
2344 Maria Enzersdorf 
Austria 
 
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Re: VTAM Trace and manuals

2006-02-15 Thread Ngafei Huang
 Here's a link.
 
http://www.elink.ibmlink.ibm.com/public/applications/publications/cgibin/pbi.cgi?SSN=06BOM0041890452602FNC=SRH
 
 
-Original Message-
From: Chris Mason [EMAIL PROTECTED]
To: IBM-MAIN@BAMA.UA.EDU
Sent: Wed, 15 Feb 2006 11:31:10 +0100
Subject: Re: VTAM Trace and manuals


A reference to the following appeared in a Google Groups  digest but not in my 
reader. I'll be interested to see whether or not this response will be 
correctly 
attached to the original. I suspect not. If not, perhaps someone will explain 
how postings get connected.

freelance wrote:

Hi, I'm trying to read a Vtam trace. 
Anyone knows what manual do I need? 
I guess I need at least the following: 
Systems Network Architecture: Formats (GA27-3136) 
Anyone knows where I can find it online, or if there is some kind of 
tutorial ? 
Thank you ! 

---

The obvious manual is CS SNA Diagnosis Vol 1 and, perhaps, 2, GC31-6850-00 and 
GC31-6850-00 for z/OS V1R7.0. Perhaps also CS SNA Data Areas Vol 1 and 2, 
GC31-6852-00 and GC31-6853-00. You can view all of these online using the 
following URL:
http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/Shelves/F1A1BK60 again for 
V1R7.0.

Start from here http://www-03.ibm.com/servers/eserver/zseries/zose/bkserv/ if 
you need another release, select All bookshelves and scroll down to 
Communications Server.

SNA Formats is always handy. Use this URL:
http://www.elink.ibmlink.ibm.com/public/applications/publications/cgibin/pbi.cgi?CTY=USFNC=SRXPBL=GA27-3136-16
and click on Read for most effective online access.

Of course, there are many different VTAM traces from the many options of the 
internal trace to the relatively simple buffer trace. You didn't say which type 
you were trying to read.

In connection with VTAM tracing, there's also another point I never hesitate to 
mention - well, I shouldn't but there's one lister who takes me to task when 
I 
do - that, if you know you need a VTAM buffer trace, it's (one of) your local 
system(s) that needs tracing and you have access to NetView, you should use the 
Session Monitor complete PIU (CPIU) trace rather than messing about with GTF 
and having to create a printout.

In terms of really understanding what's going on, the only tutorial is 
suitable education and experience. By experience here I mean that you have 
learned to understand traces where everything is working perfectly. This way, 
when something goes wrong, you can mentally compare the trace with what you 
know 
you should expect.

Chris Mason

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