[Intel-gfx] linux-next: manual merge of the drm-intel tree with Linus' tree
Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in
drivers/gpu/drm/i915/intel_panel.c between commit b1289371fcd5 ("Revert
"drm/i915: write backlight harder"") from Linus' tree and commit
31ad8ec6a614 ("drm/i915: group backlight related stuff into a struct")
from the drm-intel tree.
I fixed it up (see below) and can carry the fix as necessary (no action
is required).
--
Cheers,
Stephen Rothwells...@canb.auug.org.au
diff --cc drivers/gpu/drm/i915/intel_panel.c
index bee8cb6,0e7e873..000
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@@ -318,9 -321,16 +321,13 @@@ void intel_panel_enable_backlight(struc
{
struct drm_i915_private *dev_priv = dev->dev_private;
- if (dev_priv->backlight_level == 0)
- dev_priv->backlight_level = intel_panel_get_max_backlight(dev);
+ if (dev_priv->backlight.level == 0) {
+ dev_priv->backlight.level = intel_panel_get_max_backlight(dev);
+ if (dev_priv->backlight.device)
+ dev_priv->backlight.device->props.brightness =
+ dev_priv->backlight.level;
+ }
- dev_priv->backlight.enabled = true;
- intel_panel_actually_set_backlight(dev, dev_priv->backlight.level);
-
if (INTEL_INFO(dev)->gen >= 4) {
uint32_t reg, tmp;
@@@ -356,12 -366,12 +363,12 @@@
}
set_level:
- /* Check the current backlight level and try to set again if it's zero.
- * On some machines, BLC_PWM_CPU_CTL is cleared to zero automatically
- * when BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1 are written.
+ /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1.
+ * BLC_PWM_CPU_CTL may be cleared to zero automatically when these
+ * registers are set.
*/
- dev_priv->backlight_enabled = true;
- intel_panel_actually_set_backlight(dev, dev_priv->backlight_level);
- if (!intel_panel_get_backlight(dev))
- intel_panel_actually_set_backlight(dev,
dev_priv->backlight.level);
++ dev_priv->backlight.enabled = true;
++ intel_panel_actually_set_backlight(dev, dev_priv->backlight.level);
}
static void intel_panel_init_backlight(struct drm_device *dev)
pgpQ_ewlYZ83T.pgp
Description: PGP signature
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[Intel-gfx] [PATCH] drm/i915: Better overclock support
Most importantly this will allow users to set overclock frequencies in
sysfs. Previously the max was limited by the RP0 max as opposed to the
overclock max. This is useful if one wants to either limit the max
overclock frequency, or set the minimum frequency to be in the overclock
range. It also fixes an issue where if one sets the max frequency to be
below the overclock max, they wouldn't be able to set back the proper
overclock max.
In addition I've added a couple of other bits:
Show the overclock freq. as max in sysfs
Print the overclock max in debugfs.
Print a warning if the user sets the min frequency to be in the
overclock range.
In this patch I've decided to store the hw_max when we read it from the
pcode at init. The reason I do this is the pcode reads can fail, and are
slow.
Reported-by: freezer?
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 +++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_sysfs.c | 12
drivers/gpu/drm/i915/intel_pm.c | 3 ++-
4 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 7df8351..f081bb3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1006,6 +1006,9 @@ static int i915_cur_delayinfo(struct seq_file *m, void
*unused)
max_freq = rp_state_cap & 0xff;
seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
max_freq * GT_FREQUENCY_MULTIPLIER);
+
+ seq_printf(m, "Max overclocked frequency: %dMHz\n",
+ dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
} else {
seq_printf(m, "no P-state info available\n");
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1657d873..9b53b39c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -648,6 +648,7 @@ struct intel_gen6_power_mgmt {
u8 cur_delay;
u8 min_delay;
u8 max_delay;
+ u8 hw_max;
struct delayed_work delayed_resume_work;
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index a3a3e22..5faf1a7 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -226,7 +226,7 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev,
struct device_attribute
int ret;
mutex_lock(&dev_priv->rps.hw_lock);
- ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
+ ret = dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER;
mutex_unlock(&dev_priv->rps.hw_lock);
return snprintf(buf, PAGE_SIZE, "%d\n", ret);
@@ -251,7 +251,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
mutex_lock(&dev_priv->rps.hw_lock);
rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
- hw_max = (rp_state_cap & 0xff);
+ hw_max = dev_priv->rps.hw_max;
hw_min = ((rp_state_cap & 0xff) >> 16);
if (val < hw_min || val > hw_max || val < dev_priv->rps.min_delay) {
@@ -290,7 +290,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
struct drm_device *dev = minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- u32 val, rp_state_cap, hw_max, hw_min;
+ u32 val, rp_state_cap, hw_max, hw_min, non_oc_max;
ssize_t ret;
ret = kstrtou32(buf, 0, &val);
@@ -302,7 +302,8 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
mutex_lock(&dev_priv->rps.hw_lock);
rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
- hw_max = (rp_state_cap & 0xff);
+ hw_max = dev_priv->rps.hw_max;
+ non_oc_max = (rp_state_cap & 0xff);
hw_min = ((rp_state_cap & 0xff) >> 16);
if (val < hw_min || val > hw_max || val > dev_priv->rps.max_delay) {
@@ -310,6 +311,9 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
return -EINVAL;
}
+ if (val > non_oc_max)
+ DRM_DEBUG("User selected overclocked frequency for min\n");
+
if (dev_priv->rps.cur_delay < val)
gen6_set_rps(dev_priv->dev, val);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ce3db2c..2edb743 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2555,7 +2555,7 @@ static void gen6_enable_rps(struct drm_device *dev)
gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
/* In units of 100MHz */
- dev_priv->rps.max_delay = rp_state_cap & 0xff;
+ dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
dev_priv->rps.min_delay = (rp_state_cap & 0xff) >> 16;
dev_priv->rps.cur_delay = 0;
@@ -2635,6 +2635,7 @@ static void gen6_enable_rps(struct drm_
Re: [Intel-gfx] [PATCH 1/2] [v3] drm/i915: reference count for i915_hw_contexts
On Tue, Apr 02, 2013 at 03:45:42PM -0700, Ben Widawsky wrote:
> From: Mika Kuoppala
>
> In preparation to do analysis of which context was
> guilty of gpu hung, store kreffed context pointer
> into request struct.
>
> This allows us to inspect contexts when gpu is reset
> even if those contexts would already be released
> by userspace.
>
> v2: track i915_hw_context pointers instead of using ctx_ids
> (from Chris Wilson)
>
> v3 (Ben): Get rid of do_release() and handle refcounting more compactly.
> (recommended by Chris)
>
> Signed-off-by: Mika Kuoppala
> Signed-off-by: Ben Widawsky
Now I remember why my version of reference counting was so much more
complicated. In my case, I want to keep the last context around instead
of the last context object. To do this we can't do a kref_put until
we've switched to the next context (similar to how we manage the context
object). I want to do this since the context stores the PPGTT which will
currently be in use. I need to switch PDEs at context switch time.
So the below isn't really useful to me, I think, and I believe I need a
more complex refcounting mechanism as I described on IRC earlier today.
Daniel, Chris, thoughts?
> ---
> drivers/gpu/drm/i915/i915_drv.h| 10 --
> drivers/gpu/drm/i915/i915_gem.c| 16 +++-
> drivers/gpu/drm/i915/i915_gem_context.c| 17 +
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 7 ---
> 4 files changed, 40 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5b0c699..b88b67d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -437,6 +437,7 @@ struct i915_hw_ppgtt {
> /* This must match up with the value previously used for execbuf2.rsvd1. */
> #define DEFAULT_CONTEXT_ID 0
> struct i915_hw_context {
> + struct kref ref;
> int id;
> bool is_initialized;
> struct drm_i915_file_private *file_priv;
> @@ -1240,6 +1241,9 @@ struct drm_i915_gem_request {
> /** Postion in the ringbuffer of the end of the request */
> u32 tail;
>
> + /** Context related to this request */
> + struct i915_hw_context *ctx;
> +
> /** Time at which this request was emitted, in jiffies. */
> unsigned long emitted_jiffies;
>
> @@ -1630,9 +1634,10 @@ int __must_check i915_gpu_idle(struct drm_device *dev);
> int __must_check i915_gem_idle(struct drm_device *dev);
> int i915_do_add_request(struct intel_ring_buffer *ring,
> u32 *seqno,
> - struct drm_file *file);
> + struct drm_file *file,
> + struct i915_hw_context *ctx);
> #define i915_add_request(ring, seqno) \
> - i915_do_add_request(ring, seqno, NULL)
> + i915_do_add_request(ring, seqno, NULL, NULL)
> int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
>uint32_t seqno);
> int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
> @@ -1676,6 +1681,7 @@ void i915_gem_context_close(struct drm_device *dev,
> struct drm_file *file);
> struct i915_hw_context * __must_check
> i915_switch_context(struct intel_ring_buffer *ring,
> struct drm_file *file, int to_id);
> +void i915_gem_context_free(struct kref *ctx_ref);
> int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file);
> int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index fbbe7d9..e55c4a8 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1997,7 +1997,8 @@ i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
> int
> i915_do_add_request(struct intel_ring_buffer *ring,
> u32 *out_seqno,
> - struct drm_file *file)
> + struct drm_file *file,
> + struct i915_hw_context *ctx)
> {
> drm_i915_private_t *dev_priv = ring->dev->dev_private;
> struct drm_i915_gem_request *request;
> @@ -2037,6 +2038,11 @@ i915_do_add_request(struct intel_ring_buffer *ring,
> request->seqno = intel_ring_get_seqno(ring);
> request->ring = ring;
> request->tail = request_ring_position;
> + request->ctx = ctx;
> +
> + if (request->ctx)
> + kref_get(&request->ctx->ref);
> +
> request->emitted_jiffies = jiffies;
> was_empty = list_empty(&ring->request_list);
> list_add_tail(&request->list, &ring->request_list);
> @@ -2101,6 +2107,10 @@ static void i915_gem_reset_ring_lists(struct
> drm_i915_private *dev_priv,
>
> list_del(&request->list);
> i915_gem_request_remove_from_client(request);
> +
> + if (request->ctx)
> + kref_put(&request->ctx->ref, i915_gem_context_free);
[Intel-gfx] [PATCH 1/2] [v3] drm/i915: reference count for i915_hw_contexts
From: Mika Kuoppala
In preparation to do analysis of which context was
guilty of gpu hung, store kreffed context pointer
into request struct.
This allows us to inspect contexts when gpu is reset
even if those contexts would already be released
by userspace.
v2: track i915_hw_context pointers instead of using ctx_ids
(from Chris Wilson)
v3 (Ben): Get rid of do_release() and handle refcounting more compactly.
(recommended by Chris)
Signed-off-by: Mika Kuoppala
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h| 10 --
drivers/gpu/drm/i915/i915_gem.c| 16 +++-
drivers/gpu/drm/i915/i915_gem_context.c| 17 +
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 7 ---
4 files changed, 40 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5b0c699..b88b67d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -437,6 +437,7 @@ struct i915_hw_ppgtt {
/* This must match up with the value previously used for execbuf2.rsvd1. */
#define DEFAULT_CONTEXT_ID 0
struct i915_hw_context {
+ struct kref ref;
int id;
bool is_initialized;
struct drm_i915_file_private *file_priv;
@@ -1240,6 +1241,9 @@ struct drm_i915_gem_request {
/** Postion in the ringbuffer of the end of the request */
u32 tail;
+ /** Context related to this request */
+ struct i915_hw_context *ctx;
+
/** Time at which this request was emitted, in jiffies. */
unsigned long emitted_jiffies;
@@ -1630,9 +1634,10 @@ int __must_check i915_gpu_idle(struct drm_device *dev);
int __must_check i915_gem_idle(struct drm_device *dev);
int i915_do_add_request(struct intel_ring_buffer *ring,
u32 *seqno,
- struct drm_file *file);
+ struct drm_file *file,
+ struct i915_hw_context *ctx);
#define i915_add_request(ring, seqno) \
- i915_do_add_request(ring, seqno, NULL)
+ i915_do_add_request(ring, seqno, NULL, NULL)
int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
uint32_t seqno);
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
@@ -1676,6 +1681,7 @@ void i915_gem_context_close(struct drm_device *dev,
struct drm_file *file);
struct i915_hw_context * __must_check
i915_switch_context(struct intel_ring_buffer *ring,
struct drm_file *file, int to_id);
+void i915_gem_context_free(struct kref *ctx_ref);
int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fbbe7d9..e55c4a8 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1997,7 +1997,8 @@ i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
int
i915_do_add_request(struct intel_ring_buffer *ring,
u32 *out_seqno,
- struct drm_file *file)
+ struct drm_file *file,
+ struct i915_hw_context *ctx)
{
drm_i915_private_t *dev_priv = ring->dev->dev_private;
struct drm_i915_gem_request *request;
@@ -2037,6 +2038,11 @@ i915_do_add_request(struct intel_ring_buffer *ring,
request->seqno = intel_ring_get_seqno(ring);
request->ring = ring;
request->tail = request_ring_position;
+ request->ctx = ctx;
+
+ if (request->ctx)
+ kref_get(&request->ctx->ref);
+
request->emitted_jiffies = jiffies;
was_empty = list_empty(&ring->request_list);
list_add_tail(&request->list, &ring->request_list);
@@ -2101,6 +2107,10 @@ static void i915_gem_reset_ring_lists(struct
drm_i915_private *dev_priv,
list_del(&request->list);
i915_gem_request_remove_from_client(request);
+
+ if (request->ctx)
+ kref_put(&request->ctx->ref, i915_gem_context_free);
+
kfree(request);
}
@@ -2195,6 +2205,10 @@ i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring)
list_del(&request->list);
i915_gem_request_remove_from_client(request);
+
+ if (request->ctx)
+ kref_put(&request->ctx->ref, i915_gem_context_free);
+
kfree(request);
}
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index ddf26a6..19feeb6 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -126,11 +126,18 @@ static int get_context_size(struct drm_device *dev)
static void do_destroy(struct i915_hw_context *ctx)
{
+ drm_gem_object_unreference(&ctx-
[Intel-gfx] [PATCH 2/2] drm/i915: Print all contexts in debugfs
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 7299ea4..70369e4 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1479,11 +1479,23 @@ static int i915_gem_framebuffer_info(struct seq_file
*m, void *data)
return 0;
}
+static int context_show(int id, void *p, void *data)
+{
+ struct i915_hw_context *ctx = p;
+ struct seq_file *m = data;
+
+ seq_printf(m, "context = %d\n", id);
+ describe_obj(m, ctx->obj);
+ seq_printf(m, "\n");
+ return 0;
+}
+
static int i915_context_status(struct seq_file *m, void *unused)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
drm_i915_private_t *dev_priv = dev->dev_private;
+ struct drm_file *file;
struct intel_ring_buffer *ring;
int ret, i;
@@ -1511,6 +1523,13 @@ static int i915_context_status(struct seq_file *m, void
*unused)
}
}
+ list_for_each_entry(file, &dev->filelist, lhead) {
+ struct drm_i915_file_private *file_priv = file->driver_priv;
+ seq_printf(m, "File = %p ", file);
+ idr_for_each(&file_priv->context_idr, context_show, m);
+ seq_printf(m, "\n");
+ }
+
mutex_unlock(&dev->mode_config.mutex);
return 0;
--
1.8.2
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[Intel-gfx] [PATCH] drm/i915: move dp_m_n computation to dp_encoder->compute_config
We need a flag to designate dp encoders and the dp link m_n parameters
in the pipe config for that. And now that the pipe bpp computations
have been moved up and stored in the pipe config, too, we can do this
without losing our sanity.
v2: Rebased on top of Takashi Iwai's fix to (again) fix the target
clock handling for eDP. Luckily the new code is sane enough and just
does the right thing!
v3: Move ->has_dp_encoder to this patch (Jesse).
Reviewed-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 30 +-
drivers/gpu/drm/i915/intel_dp.c | 59 ++--
drivers/gpu/drm/i915/intel_drv.h | 6 ++--
3 files changed, 28 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a53a02c..dfa8919 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4182,6 +4182,14 @@ static void i9xx_update_pll_dividers(struct drm_crtc
*crtc,
}
}
+static void intel_dp_set_m_n(struct intel_crtc *crtc)
+{
+ if (crtc->config.has_pch_encoder)
+ intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
+ else
+ intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
+}
+
static void vlv_update_pll(struct drm_crtc *crtc,
intel_clock_t *clock, intel_clock_t *reduced_clock,
int num_connectors)
@@ -4189,9 +4197,6 @@ static void vlv_update_pll(struct drm_crtc *crtc,
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- struct drm_display_mode *adjusted_mode =
- &intel_crtc->config.adjusted_mode;
- struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
int pipe = intel_crtc->pipe;
u32 dpll, mdiv, pdiv;
u32 bestn, bestm1, bestm2, bestp1, bestp2;
@@ -4247,8 +4252,8 @@ static void vlv_update_pll(struct drm_crtc *crtc,
intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
- if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
- intel_dp_set_m_n(crtc, mode, adjusted_mode);
+ if (intel_crtc->config.has_dp_encoder)
+ intel_dp_set_m_n(intel_crtc);
I915_WRITE(DPLL(pipe), dpll);
@@ -4294,9 +4299,6 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- struct drm_display_mode *adjusted_mode =
- &intel_crtc->config.adjusted_mode;
- struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
struct intel_encoder *encoder;
int pipe = intel_crtc->pipe;
u32 dpll;
@@ -4371,8 +4373,8 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
if (encoder->pre_pll_enable)
encoder->pre_pll_enable(encoder);
- if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
- intel_dp_set_m_n(crtc, mode, adjusted_mode);
+ if (intel_crtc->config.has_dp_encoder)
+ intel_dp_set_m_n(intel_crtc);
I915_WRITE(DPLL(pipe), dpll);
@@ -5588,8 +5590,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
} else
intel_put_pch_pll(intel_crtc);
- if (is_dp)
- intel_dp_set_m_n(crtc, mode, adjusted_mode);
+ if (intel_crtc->config.has_dp_encoder)
+ intel_dp_set_m_n(intel_crtc);
for_each_encoder_on_crtc(dev, crtc, encoder)
if (encoder->pre_pll_enable)
@@ -5738,8 +5740,8 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
drm_mode_debug_printmodeline(mode);
- if (is_dp)
- intel_dp_set_m_n(crtc, mode, adjusted_mode);
+ if (intel_crtc->config.has_dp_encoder)
+ intel_dp_set_m_n(intel_crtc);
intel_crtc->lowfreq_avail = false;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6b8a279..ef680d5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -193,6 +193,8 @@ intel_dp_mode_valid(struct drm_connector *connector,
if (mode->vdisplay > fixed_mode->vdisplay)
return MODE_PANEL;
+
+ target_clock = fixed_mode->clock;
}
max_link_clock =
drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
@@ -688,6 +690,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
pipe_config->has_pch_encoder = true;
+ pipe_config->has_dp_encoder = true;
+
if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
[Intel-gfx] [PATCH] drm/i915: clear up the fdi/dp set_m_n confusion
There's a rather decent confusion going on around transcoder m_n
values. So let's clarify:
- All dp encoders need this, either on the pch transcoder if it's a
pch port, or on the cpu transcoder/pipe if it's a cpu port.
- fdi links need to have the right m_n values for the fdi link set in
the cpu transcoder.
To handle the pch vs transcoder stuff a bit better, extract transcoder
set_m_n helpers. To make them simpler, set intel_crtc->cpu_transcoder
als in ironlake_crtc_mode_set, so that gen5+ (where the cpu m_n
registers are all at the same offset) can use it.
Haswell modeset is decently confused about dp vs. edp vs. fdi. dp vs.
edp works exactly the same as dp (since there's no pch dp any more),
so use that as a check. And only set up the fdi m_n values if we
really have a pch encoder present (which means we have a VGA encoder).
On ilk+ we've called ironlake_set_m_n both for cpu_edp and for pch
encoders. Now that dp_set_m_n handles all dp links (thanks to the
pch encoder check), we can ditch the cpu_edp stuff from the
fdi_set_m_n function.
Since the dp_m_n values are not readily available, we need to
carefully coax the edp values out of the encoder. Hence we can't (yet)
kill this superflous complexity.
v2: Rebase on top of the ivb fdi B/C check patch - we need to properly
clear intel_crtc->fdi_lane, otherwise those checks will misfire.
v3: Rebased on top of a s/IS_HASWELL/HAS_DDI/ patch from Paulo Zanoni.
v4: Drop the addition of has_dp_encoder, it's in the wrong patch (Jesse).
Reviewed-by: Jesse Barnes
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_display.c | 86 +++-
drivers/gpu/drm/i915/intel_dp.c | 30 ++---
drivers/gpu/drm/i915/intel_drv.h | 5 +++
3 files changed, 64 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 9c71240..a53a02c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5314,15 +5314,47 @@ int ironlake_get_lanes_required(int target_clock, int
link_bw, int bpp)
return bps / (link_bw * 8) + 1;
}
-static void ironlake_set_m_n(struct drm_crtc *crtc)
+void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
+ struct intel_link_m_n *m_n)
{
- struct drm_device *dev = crtc->dev;
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int pipe = crtc->pipe;
+
+ I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
+ I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
+ I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
+ I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
+}
+
+void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
+ struct intel_link_m_n *m_n)
+{
+ struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ int pipe = crtc->pipe;
+ enum transcoder transcoder = crtc->cpu_transcoder;
+
+ if (INTEL_INFO(dev)->gen >= 5) {
+ I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) |
m_n->gmch_m);
+ I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
+ I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
+ I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
+ } else {
+ I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) |
m_n->gmch_m);
+ I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
+ I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
+ I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
+ }
+}
+
+static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct drm_display_mode *adjusted_mode =
&intel_crtc->config.adjusted_mode;
struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
- enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
struct intel_encoder *intel_encoder, *edp_encoder = NULL;
struct intel_link_m_n m_n = {0};
int target_clock, lane, link_bw;
@@ -5342,22 +5374,14 @@ static void ironlake_set_m_n(struct drm_crtc *crtc)
}
}
- /* FDI link */
- lane = 0;
- /* CPU eDP doesn't require FDI link, so just set DP M/N
- according to current link config */
- if (is_cpu_edp) {
- intel_edp_link_config(edp_encoder, &lane, &link_bw);
- } else {
- /* FDI is a binary signal running at ~2.7GHz, encoding
-* each output octet as 10 bits. The actual frequency
-* is stored as a divider into a 100MHz clock, and the
-* mode pixel clock is stored in units of 1KHz.
-* Hence the bw of each lane in terms of the mode
Re: [Intel-gfx] [PATCH] drm/i915: remove leaky eDP functions
On Tue, 2 Apr 2013 23:27:41 +0200
Daniel Vetter wrote:
> Jesse Barnes noticed in his review of my DP cleanup series that
> intel_edp_target_clock is now unused. Checking related code I've
> noticed that also intel_edp_link_config is long unused.
>
> Kill them both.
>
> Wrt leaky eDP functions used in the common crtc code, the only thing
> still left is intel_encoder_is_pch_edp. That one is just due to the
> massive confusion between eDP vs. DP and port A vs. port D. Crtc code
> should at most concern itself with the later, never with the former.
>
> But that's material for another patch series.
>
> Cc: Jesse Barnes
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/intel_dp.c | 23 ---
> drivers/gpu/drm/i915/intel_drv.h | 3 ---
> 2 files changed, 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 6bf144c..f90ce47 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -109,29 +109,6 @@ bool intel_encoder_is_pch_edp(struct drm_encoder
> *encoder)
>
> static void intel_dp_link_down(struct intel_dp *intel_dp);
>
> -void
> -intel_edp_link_config(struct intel_encoder *intel_encoder,
> -int *lane_num, int *link_bw)
> -{
> - struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
> -
> - *lane_num = intel_dp->lane_count;
> - *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
> -}
> -
> -int
> -intel_edp_target_clock(struct intel_encoder *intel_encoder,
> -struct drm_display_mode *mode)
> -{
> - struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
> - struct intel_connector *intel_connector = intel_dp->attached_connector;
> -
> - if (intel_connector->panel.fixed_mode)
> - return intel_connector->panel.fixed_mode->clock;
> - else
> - return mode->clock;
> -}
> -
> static int
> intel_dp_max_link_bw(struct intel_dp *intel_dp)
> {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 094c940..2b31d7e 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -520,9 +520,6 @@ extern void ironlake_edp_panel_on(struct intel_dp
> *intel_dp);
> extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
> extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
> extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
> -extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
> -extern int intel_edp_target_clock(struct intel_encoder *,
> - struct drm_display_mode *mode);
> extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
> extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
> extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
Reviewed-by: Jesse Barnes
--
Jesse Barnes, Intel Open Source Technology Center
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[Intel-gfx] [PATCH] drm/i915: remove leaky eDP functions
Jesse Barnes noticed in his review of my DP cleanup series that
intel_edp_target_clock is now unused. Checking related code I've
noticed that also intel_edp_link_config is long unused.
Kill them both.
Wrt leaky eDP functions used in the common crtc code, the only thing
still left is intel_encoder_is_pch_edp. That one is just due to the
massive confusion between eDP vs. DP and port A vs. port D. Crtc code
should at most concern itself with the later, never with the former.
But that's material for another patch series.
Cc: Jesse Barnes
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_dp.c | 23 ---
drivers/gpu/drm/i915/intel_drv.h | 3 ---
2 files changed, 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6bf144c..f90ce47 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -109,29 +109,6 @@ bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
static void intel_dp_link_down(struct intel_dp *intel_dp);
-void
-intel_edp_link_config(struct intel_encoder *intel_encoder,
- int *lane_num, int *link_bw)
-{
- struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
-
- *lane_num = intel_dp->lane_count;
- *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
-}
-
-int
-intel_edp_target_clock(struct intel_encoder *intel_encoder,
- struct drm_display_mode *mode)
-{
- struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
- struct intel_connector *intel_connector = intel_dp->attached_connector;
-
- if (intel_connector->panel.fixed_mode)
- return intel_connector->panel.fixed_mode->clock;
- else
- return mode->clock;
-}
-
static int
intel_dp_max_link_bw(struct intel_dp *intel_dp)
{
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 094c940..2b31d7e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -520,9 +520,6 @@ extern void ironlake_edp_panel_on(struct intel_dp
*intel_dp);
extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
-extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
-extern int intel_edp_target_clock(struct intel_encoder *,
- struct drm_display_mode *mode);
extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
--
1.7.11.7
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Re: [Intel-gfx] [PATCH 8/8] drm/i915: move dp clock computations to encoder->compute_config
On Tue, Apr 2, 2013 at 11:20 PM, Jesse Barnes wrote: > On Thu, 28 Mar 2013 10:42:03 +0100 > Daniel Vetter wrote: > > > With the exception of hsw, which has dedicated DP clocks which run at > > the fixed frequency already, and vlv, which doesn't have optmized > > pre-defined dp clock parameters (yet). > > > > Nice. I think we should do this for common HDMI modes too. We have > some extra clock manipulation regs we can use to tune things, so having > fixed dividers for 720p and 1080p along with the tuning params should > give us better behavior than what we have today. Imo we still have a few lower-hanging fruit before we need to start doing clock fine-tuning in hdmi-land: Atm we don't really bother with supporting the 1001/1000 modified clocks in the CEA spec at all ... Once we have the support code for that, adding fine-tuned clocks for those modes starts to make sense, so that we really hit them spot-on. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 8/8] drm/i915: move dp clock computations to encoder->compute_config
On Thu, 28 Mar 2013 10:42:03 +0100 Daniel Vetter wrote: > With the exception of hsw, which has dedicated DP clocks which run at > the fixed frequency already, and vlv, which doesn't have optmized > pre-defined dp clock parameters (yet). > Nice. I think we should do this for common HDMI modes too. We have some extra clock manipulation regs we can use to tune things, so having fixed dividers for 720p and 1080p along with the tuning params should give us better behavior than what we have today. Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 7/8] drm/i915: create pipe_config->dpll for clock state
On Thu, 28 Mar 2013 10:42:02 +0100
Daniel Vetter wrote:
> Clock computations and handling are highly encoder specific, both in
> the optimal clock selection and also in which clocks to use and when
> sharing of clocks is possible.
>
> So the best place to do this is somewhere in the encoders, with a
> generic fallback for those encoders without special needs. To facility
> this, add a pipe_config->clocks_set boolean.
>
> This patch here is only prep work, it simply sets the computed clock
> values in pipe_config->dpll, and uses that data in the hw clock
> setting functions.
>
> Haswell code isn't touched, simply because Haswell clocks work much
> different and need their own infrastructure (with probably a
> Haswell-specific config->ddi_clock substruct).
>
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/intel_display.c | 155
> +++
> drivers/gpu/drm/i915/intel_drv.h | 12 +++
> 2 files changed, 95 insertions(+), 72 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index c9e873e..5319133 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4118,37 +4118,38 @@ static int i9xx_get_refclk(struct drm_crtc *crtc, int
> num_connectors)
> return refclk;
> }
>
> -static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
> - intel_clock_t *clock)
> +static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
> {
> + unsigned dotclock = crtc->config.adjusted_mode.clock;
> + struct dpll *clock = &crtc->config.dpll;
> +
> /* SDVO TV has fixed PLL values depend on its clock range,
> this mirrors vbios setting. */
> - if (adjusted_mode->clock >= 10
> - && adjusted_mode->clock < 140500) {
> + if (dotclock >= 10 && dotclock < 140500) {
> clock->p1 = 2;
> clock->p2 = 10;
> clock->n = 3;
> clock->m1 = 16;
> clock->m2 = 8;
> - } else if (adjusted_mode->clock >= 140500
> -&& adjusted_mode->clock <= 20) {
> + } else if (dotclock >= 140500 && dotclock <= 20) {
> clock->p1 = 1;
> clock->p2 = 10;
> clock->n = 6;
> clock->m1 = 12;
> clock->m2 = 8;
> }
> +
> + crtc->config.clock_set = true;
> }
>
> -static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
> - intel_clock_t *clock,
> +static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
>intel_clock_t *reduced_clock)
> {
> - struct drm_device *dev = crtc->dev;
> + struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - int pipe = intel_crtc->pipe;
> + int pipe = crtc->pipe;
> u32 fp, fp2 = 0;
> + struct dpll *clock = &crtc->config.dpll;
>
> if (IS_PINEVIEW(dev)) {
> fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
> @@ -4164,11 +4165,11 @@ static void i9xx_update_pll_dividers(struct drm_crtc
> *crtc,
>
> I915_WRITE(FP0(pipe), fp);
>
> - intel_crtc->lowfreq_avail = false;
> - if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
> + crtc->lowfreq_avail = false;
> + if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
> reduced_clock && i915_powersave) {
> I915_WRITE(FP1(pipe), fp2);
> - intel_crtc->lowfreq_avail = true;
> + crtc->lowfreq_avail = true;
> } else {
> I915_WRITE(FP1(pipe), fp);
> }
> @@ -4182,14 +4183,11 @@ static void intel_dp_set_m_n(struct intel_crtc *crtc)
> intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
> }
>
> -static void vlv_update_pll(struct drm_crtc *crtc,
> -intel_clock_t *clock, intel_clock_t *reduced_clock,
> -int num_connectors)
> +static void vlv_update_pll(struct intel_crtc *crtc)
> {
> - struct drm_device *dev = crtc->dev;
> + struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - int pipe = intel_crtc->pipe;
> + int pipe = crtc->pipe;
> u32 dpll, mdiv, pdiv;
> u32 bestn, bestm1, bestm2, bestp1, bestp2;
> bool is_sdvo;
> @@ -4197,8 +4195,8 @@ static void vlv_update_pll(struct drm_crtc *crtc,
>
> mutex_lock(&dev_priv->dpio_lock);
>
> - is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
> - intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
> + is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
> + intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
>
> dpll = DP
Re: [Intel-gfx] [PATCH 6/8] drm/i915: hw readout support for ->has_pch_encoders
On Thu, 28 Mar 2013 10:42:01 +0100
Daniel Vetter wrote:
> Now we can ditch the checks in the Haswell disable code.
>
> v2: add support for Haswell
>
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/intel_display.c | 34 +-
> 1 file changed, 25 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index a5adaa0..c9e873e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2975,11 +2975,6 @@ static void intel_crtc_wait_for_pending_flips(struct
> drm_crtc *crtc)
> mutex_unlock(&dev->struct_mutex);
> }
>
> -static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
> -{
> - return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
> -}
> -
> /* Program iCLKIP clock to the desired frequency */
> static void lpt_program_iclkip(struct drm_crtc *crtc)
> {
> @@ -3562,13 +3557,10 @@ static void haswell_crtc_disable(struct drm_crtc
> *crtc)
> int pipe = intel_crtc->pipe;
> int plane = intel_crtc->plane;
> enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
> - bool is_pch_port;
>
> if (!intel_crtc->active)
> return;
>
> - is_pch_port = haswell_crtc_driving_pch(crtc);
> -
> for_each_encoder_on_crtc(dev, crtc, encoder)
> encoder->disable(encoder);
>
> @@ -3595,7 +3587,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
> if (encoder->post_disable)
> encoder->post_disable(encoder);
>
> - if (is_pch_port) {
> + if (intel_crtc->config.has_pch_encoder) {
> lpt_disable_pch_transcoder(dev_priv);
> intel_ddi_fdi_disable(crtc);
> }
> @@ -5635,6 +5627,9 @@ static bool ironlake_get_pipe_config(struct intel_crtc
> *crtc,
> if (!(tmp & PIPECONF_ENABLE))
> return false;
>
> + if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
> + pipe_config->has_pch_encoder = true;
> +
> return true;
> }
>
> @@ -5763,6 +5758,17 @@ static bool haswell_get_pipe_config(struct intel_crtc
> *crtc,
> if (!(tmp & PIPECONF_ENABLE))
> return false;
>
> + /*
> + * aswell has only FDI/PCH transcoder A. It is which is connected to
> + * DDI E. So just check whether this pipe is wired to DDI E and whether
> + * the PCH transcoder is on.
> + */
> + tmp = I915_READ(TRANS_DDI_FUNC_CTL(crtc->pipe));
> + if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
> + I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
> + pipe_config->has_pch_encoder = true;
> +
> +
> return true;
> }
>
> @@ -7692,6 +7698,14 @@ static bool
> intel_pipe_config_compare(struct intel_crtc_config *current_config,
> struct intel_crtc_config *pipe_config)
> {
> + if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
> + DRM_ERROR("mismatch in has_pch_encoder "
> + "(expected %i, found %i)\n",
> + current_config->has_pch_encoder,
> + pipe_config->has_pch_encoder);
> + return false;
> + }
> +
> return true;
> }
>
> @@ -7791,6 +7805,7 @@ intel_modeset_check_state(struct drm_device *dev)
>"crtc's computed enabled state doesn't match tracked
> enabled state "
>"(expected %i, found %i)\n", enabled, crtc->base.enabled);
>
> + memset(&pipe_config, 0, sizeof(pipe_config));
> active = dev_priv->display.get_pipe_config(crtc,
> &pipe_config);
> WARN(crtc->active != active,
> @@ -9155,6 +9170,7 @@ void intel_modeset_setup_hw_state(struct drm_device
> *dev,
> setup_pipes:
> list_for_each_entry(crtc, &dev->mode_config.crtc_list,
> base.head) {
> + memset(&crtc->config, 0, sizeof(crtc->config));
> crtc->active = dev_priv->display.get_pipe_config(crtc,
>&crtc->config);
>
I think this is correct; I was worried about mode_set, crtc_disable,
crtc_enable. But in that case, the pipe_config shouldn't be overridden
(that won't happen until the next mode_set). So I think this is safe.
Reviewed-by: Jesse Barnes
--
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Re: [Intel-gfx] [PATCH 5/8] drm/i915: add hw state readout/checking for pipe_config
On Thu, 28 Mar 2013 10:42:00 +0100
Daniel Vetter wrote:
> We need to be able to read out the hw state code for a bunch
> of reasons:
> - Correctly disabling boot-up/resume state.
> - Pure paranoia.
>
> Since not all of the pipe configuration is e.g. relevant for
> fastboot (or at least we can allow some wiggle room in some
> parameters, like the clocks), we need to add a strict_checking
> parameter to intel_pipe_config_compare for fastboot.
>
> For now intel_pipe_config_compare should be fully paranoid and
> check everything that the hw state readout code supports. Which
> for this infrastructure code is nothing.
>
> I've gone a bit overboard with adding 3 get_pipe_config functions:
> The ilk version will differ with the next patch, so it's not too
> onerous.
>
> v2: Don't check the hw config if the pipe is off, since an enabled,
> but dpms off crtc will obviously have tons of difference with the hw
> state.
>
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/i915_drv.h | 5 +++
> drivers/gpu/drm/i915/intel_display.c | 77
> +++-
> 2 files changed, 72 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 86777c8..99d7f81 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -285,6 +285,7 @@ struct drm_i915_error_state {
> };
>
> struct intel_crtc_config;
> +struct intel_crtc;
>
> struct drm_i915_display_funcs {
> bool (*fbc_enabled)(struct drm_device *dev);
> @@ -298,6 +299,10 @@ struct drm_i915_display_funcs {
> void (*update_linetime_wm)(struct drm_device *dev, int pipe,
>struct drm_display_mode *mode);
> void (*modeset_global_resources)(struct drm_device *dev);
> + /* Returns the active state of the crtc, and if the crtc is active,
> + * fills out the pipe-config with the hw state. */
> + bool (*get_pipe_config)(struct intel_crtc *,
> + struct intel_crtc_config *);
> int (*crtc_mode_set)(struct drm_crtc *crtc,
>int x, int y,
>struct drm_framebuffer *old_fb);
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index e925efe..a5adaa0 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4695,6 +4695,20 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
> return ret;
> }
>
> +static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> + struct intel_crtc_config *pipe_config)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + uint32_t tmp;
> +
> + tmp = I915_READ(PIPECONF(crtc->pipe));
> + if (!(tmp & PIPECONF_ENABLE))
> + return false;
> +
> + return true;
> +}
> +
> static void ironlake_init_pch_refclk(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -5355,7 +5369,6 @@ static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
> &intel_crtc->config.adjusted_mode;
> struct intel_link_m_n m_n = {0};
> int target_clock, lane, link_bw;
> - uint32_t bps;
>
> /* FDI is a binary signal running at ~2.7GHz, encoding
>* each output octet as 10 bits. The actual frequency
> @@ -5611,6 +5624,20 @@ static int ironlake_crtc_mode_set(struct drm_crtc
> *crtc,
> return fdi_config_ok ? ret : -EINVAL;
> }
>
> +static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
> + struct intel_crtc_config *pipe_config)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + uint32_t tmp;
> +
> + tmp = I915_READ(PIPECONF(crtc->pipe));
> + if (!(tmp & PIPECONF_ENABLE))
> + return false;
> +
> + return true;
> +}
> +
> static void haswell_modeset_global_resources(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -5725,6 +5752,20 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
> return ret;
> }
>
> +static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> + struct intel_crtc_config *pipe_config)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + uint32_t tmp;
> +
> + tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
> + if (!(tmp & PIPECONF_ENABLE))
> + return false;
> +
> + return true;
> +}
> +
> static int intel_crtc_mode_set(struct drm_crtc *crtc,
> int x, int y,
> struct drm_framebuffer *fb)
> @@ -7647,12 +7688,21 @@ intel_modeset_update_state(struct drm_device *dev,
> unsigned prepare_pipes)
>
Re: [Intel-gfx] [PATCH 4/8] drm/i915: rip out superflous is_dp&is_cpu_edp tracking
On Thu, 28 Mar 2013 10:41:59 +0100
Daniel Vetter wrote:
> The only exception left is is_cpu_edp in the haswell modeset code.
> We need that to assign the cpu transcoder, but we might want to
> move that eventually into the encoder, too.
>
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/intel_display.c | 37
> +++-
> 1 file changed, 7 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 464eb90..e925efe 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4532,7 +4532,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
> intel_clock_t clock, reduced_clock;
> u32 dspcntr, pipeconf;
> bool ok, has_reduced_clock = false, is_sdvo = false;
> - bool is_lvds = false, is_tv = false, is_dp = false;
> + bool is_lvds = false, is_tv = false;
> struct intel_encoder *encoder;
> const intel_limit_t *limit;
> int ret;
> @@ -4551,9 +4551,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
> case INTEL_OUTPUT_TVOUT:
> is_tv = true;
> break;
> - case INTEL_OUTPUT_DISPLAYPORT:
> - is_dp = true;
> - break;
> }
>
> num_connectors++;
> @@ -4636,7 +4633,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>
> /* default to 8bpc */
> pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
> - if (is_dp) {
> + if (intel_crtc->config.has_dp_encoder) {
> if (intel_crtc->config.dither) {
> pipeconf |= PIPECONF_6BPC |
> PIPECONF_DITHER_EN |
> @@ -5397,7 +5394,6 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc
> *intel_crtc,
> uint32_t dpll;
> int factor, num_connectors = 0;
> bool is_lvds = false, is_sdvo = false, is_tv = false;
> - bool is_dp = false, is_cpu_edp = false;
>
> for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
> switch (intel_encoder->type) {
> @@ -5413,14 +5409,6 @@ static uint32_t ironlake_compute_dpll(struct
> intel_crtc *intel_crtc,
> case INTEL_OUTPUT_TVOUT:
> is_tv = true;
> break;
> - case INTEL_OUTPUT_DISPLAYPORT:
> - is_dp = true;
> - break;
> - case INTEL_OUTPUT_EDP:
> - is_dp = true;
> - if (!intel_encoder_is_pch_edp(&intel_encoder->base))
> - is_cpu_edp = true;
> - break;
> }
>
> num_connectors++;
> @@ -5452,7 +5440,8 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc
> *intel_crtc,
> }
> dpll |= DPLL_DVO_HIGH_SPEED;
> }
> - if (is_dp && !is_cpu_edp)
> + if (intel_crtc->config.has_dp_encoder &&
> + intel_crtc->config.has_pch_encoder)
> dpll |= DPLL_DVO_HIGH_SPEED;
>
> /* compute bitmask from p1 value */
> @@ -5505,7 +5494,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
> intel_clock_t clock, reduced_clock;
> u32 dpll, fp = 0, fp2 = 0;
> bool ok, has_reduced_clock = false;
> - bool is_lvds = false, is_dp = false, is_cpu_edp = false;
> + bool is_lvds = false;
> struct intel_encoder *encoder;
> int ret;
> bool dither, fdi_config_ok;
> @@ -5515,14 +5504,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc
> *crtc,
> case INTEL_OUTPUT_LVDS:
> is_lvds = true;
> break;
> - case INTEL_OUTPUT_DISPLAYPORT:
> - is_dp = true;
> - break;
> - case INTEL_OUTPUT_EDP:
> - is_dp = true;
> - if (!intel_encoder_is_pch_edp(&encoder->base))
> - is_cpu_edp = true;
> - break;
> }
>
> num_connectors++;
> @@ -5559,7 +5540,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
> drm_mode_debug_printmodeline(mode);
>
> /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
> - if (!is_cpu_edp) {
> + if (intel_crtc->config.has_pch_encoder) {
> struct intel_pch_pll *pll;
>
> pll = intel_get_pch_pll(intel_crtc, dpll, fp);
> @@ -5672,18 +5653,14 @@ static int haswell_crtc_mode_set(struct drm_crtc
> *crtc,
> int pipe = intel_crtc->pipe;
> int plane = intel_crtc->plane;
> int num_connectors = 0;
> - bool is_dp = false, is_cpu_edp = false;
> + bool is_cpu_edp = false;
> struct intel_encoder *encoder;
> int ret;
> bool dither;
>
> for_each_encoder_on_crtc(dev, crtc, encoder) {
>
Re: [Intel-gfx] [PATCH 3/8] drm/i915: track dp target_clock in pipe_config
On Thu, 28 Mar 2013 10:41:58 +0100
Daniel Vetter wrote:
> We need it in the fdi m_n computation, which nicely kills almost
> all ugly special cases in there.
>
> It looks like we also need this to handle 12bpc hdmi correctly.
>
> Eventually it might be better to switch things around and put the
> target clock into adjusted_mode->clock and create a new pipe_config
> parameter for the port link clock.
>
> v2: Add a massive comment in the code to explain this mess.
>
> v3: s/dp_target_clock/pixel_target_clock in anticipation of the hdmi
> use-case.
>
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/intel_display.c | 25 +++--
> drivers/gpu/drm/i915/intel_dp.c | 1 +
> drivers/gpu/drm/i915/intel_drv.h | 7 ++-
> 3 files changed, 10 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index dfa8919..464eb90 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5356,25 +5356,9 @@ static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct drm_display_mode *adjusted_mode =
> &intel_crtc->config.adjusted_mode;
> - struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
> - struct intel_encoder *intel_encoder, *edp_encoder = NULL;
> struct intel_link_m_n m_n = {0};
> int target_clock, lane, link_bw;
> - bool is_dp = false, is_cpu_edp = false;
> -
> - for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
> - switch (intel_encoder->type) {
> - case INTEL_OUTPUT_DISPLAYPORT:
> - is_dp = true;
> - break;
> - case INTEL_OUTPUT_EDP:
> - is_dp = true;
> - if (!intel_encoder_is_pch_edp(&intel_encoder->base))
> - is_cpu_edp = true;
> - edp_encoder = intel_encoder;
> - break;
> - }
> - }
> + uint32_t bps;
>
> /* FDI is a binary signal running at ~2.7GHz, encoding
>* each output octet as 10 bits. The actual frequency
> @@ -5385,11 +5369,8 @@ static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
>*/
> link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
>
> - /* [e]DP over FDI requires target mode clock instead of link clock. */
> - if (edp_encoder)
> - target_clock = intel_edp_target_clock(edp_encoder, mode);
> - else if (is_dp)
> - target_clock = mode->clock;
> + if (intel_crtc->config.pixel_target_clock)
> + target_clock = intel_crtc->config.pixel_target_clock;
> else
> target_clock = adjusted_mode->clock;
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index ef680d5..b1bf00b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -753,6 +753,7 @@ found:
> intel_dp->lane_count = lane_count;
> adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
> pipe_config->pipe_bpp = bpp;
> + pipe_config->pixel_target_clock = target_clock;
>
> DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
> intel_dp->link_bw, intel_dp->lane_count,
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 41fabcb..2a86a12 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -198,7 +198,12 @@ struct intel_crtc_config {
> bool dither;
> int pipe_bpp;
> struct intel_link_m_n dp_m_n;
> -
> + /**
> + * This is currently used by DP and HDMI encoders since those can have a
> + * target pixel clock != the port link clock (which is currently stored
> + * in adjusted_mode->clock).
> + */
> + int pixel_target_clock;
> /* Used by SDVO (and if we ever fix it, HDMI). */
> unsigned pixel_multiplier;
> };
Since you already explained there are other callers of
edp_target_clock():
Reviewed-by: Jesse Barnes
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Re: [Intel-gfx] [PATCH 2/8] drm/i915: move dp_m_n computation to dp_encoder->compute_config
On Thu, 28 Mar 2013 10:41:57 +0100
Daniel Vetter wrote:
> We need a flag to designate dp encoders and the dp link m_n parameters
> in the pipe config for that. And now that the pipe bpp computations
> have been moved up and stored in the pipe config, too, we can do this
> without losing our sanity.
>
> v2: Rebased on top of Takashi Iwai's fix to (again) fix the target
> clock handling for eDP. Luckily the new code is sane enough and just
> does the right thing!
>
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/intel_display.c | 30 +-
> drivers/gpu/drm/i915/intel_dp.c | 59
> ++--
> drivers/gpu/drm/i915/intel_drv.h | 3 --
> 3 files changed, 25 insertions(+), 67 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index a53a02c..dfa8919 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4182,6 +4182,14 @@ static void i9xx_update_pll_dividers(struct drm_crtc
> *crtc,
> }
> }
>
> +static void intel_dp_set_m_n(struct intel_crtc *crtc)
> +{
> + if (crtc->config.has_pch_encoder)
> + intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
> + else
> + intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
> +}
> +
> static void vlv_update_pll(struct drm_crtc *crtc,
> intel_clock_t *clock, intel_clock_t *reduced_clock,
> int num_connectors)
> @@ -4189,9 +4197,6 @@ static void vlv_update_pll(struct drm_crtc *crtc,
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - struct drm_display_mode *adjusted_mode =
> - &intel_crtc->config.adjusted_mode;
> - struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
> int pipe = intel_crtc->pipe;
> u32 dpll, mdiv, pdiv;
> u32 bestn, bestm1, bestm2, bestp1, bestp2;
> @@ -4247,8 +4252,8 @@ static void vlv_update_pll(struct drm_crtc *crtc,
>
> intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
>
> - if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
> - intel_dp_set_m_n(crtc, mode, adjusted_mode);
> + if (intel_crtc->config.has_dp_encoder)
> + intel_dp_set_m_n(intel_crtc);
>
> I915_WRITE(DPLL(pipe), dpll);
>
> @@ -4294,9 +4299,6 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - struct drm_display_mode *adjusted_mode =
> - &intel_crtc->config.adjusted_mode;
> - struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
> struct intel_encoder *encoder;
> int pipe = intel_crtc->pipe;
> u32 dpll;
> @@ -4371,8 +4373,8 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
> if (encoder->pre_pll_enable)
> encoder->pre_pll_enable(encoder);
>
> - if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
> - intel_dp_set_m_n(crtc, mode, adjusted_mode);
> + if (intel_crtc->config.has_dp_encoder)
> + intel_dp_set_m_n(intel_crtc);
>
> I915_WRITE(DPLL(pipe), dpll);
>
> @@ -5588,8 +5590,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
> } else
> intel_put_pch_pll(intel_crtc);
>
> - if (is_dp)
> - intel_dp_set_m_n(crtc, mode, adjusted_mode);
> + if (intel_crtc->config.has_dp_encoder)
> + intel_dp_set_m_n(intel_crtc);
>
> for_each_encoder_on_crtc(dev, crtc, encoder)
> if (encoder->pre_pll_enable)
> @@ -5738,8 +5740,8 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
> DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
> drm_mode_debug_printmodeline(mode);
>
> - if (is_dp)
> - intel_dp_set_m_n(crtc, mode, adjusted_mode);
> + if (intel_crtc->config.has_dp_encoder)
> + intel_dp_set_m_n(intel_crtc);
>
> intel_crtc->lowfreq_avail = false;
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 6b8a279..ef680d5 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -193,6 +193,8 @@ intel_dp_mode_valid(struct drm_connector *connector,
>
> if (mode->vdisplay > fixed_mode->vdisplay)
> return MODE_PANEL;
> +
> + target_clock = fixed_mode->clock;
> }
>
> max_link_clock =
> drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
> @@ -688,6 +690,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
> pipe_config->has_pch_encoder
Re: [Intel-gfx] [PATCH 1/8] drm/i915: clear up the fdi/dp set_m_n confusion
On Tue, 2 Apr 2013 13:47:52 -0700 Jesse Barnes wrote: > On Thu, 28 Mar 2013 10:41:56 +0100 > Daniel Vetter wrote: > > > > > + /* DP has a bunch of special case unfortunately, so mark the pipe > > +* accordingly. */ > > + bool has_dp_encoder; > > Looks pretty good, but I don't think this field is used anywhere? > Maybe it belongs in a later patch? > > Also, this makes me wonder if we should be clearing the m_n regs > somewhere and asserting for them in a few places. > > Definitely looks better than the current code though; CPU vs PCH writes > sprinkled all about, and FDI thrown into the mix. > > It's probably a bit unfair to say the HSW mode set is confused though; > it's just using existing code as best it can. These new bits are > definitely clearer though. > Oh and with the new field moved to another patch: Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/8] drm/i915: clear up the fdi/dp set_m_n confusion
On Thu, 28 Mar 2013 10:41:56 +0100 Daniel Vetter wrote: > > + /* DP has a bunch of special case unfortunately, so mark the pipe > + * accordingly. */ > + bool has_dp_encoder; Looks pretty good, but I don't think this field is used anywhere? Maybe it belongs in a later patch? Also, this makes me wonder if we should be clearing the m_n regs somewhere and asserting for them in a few places. Definitely looks better than the current code though; CPU vs PCH writes sprinkled all about, and FDI thrown into the mix. It's probably a bit unfair to say the HSW mode set is confused though; it's just using existing code as best it can. These new bits are definitely clearer though. -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Fix sdvo connector get_hw_state function
The active output is only the currently selected one, which does not imply that it's actually enabled. Since we don't use the sdvo encoder side dpms support, we need to check whether the chip-side sdvo port is enabled instead. v2: Fix up Bugzilla links. v3: Simplify logic a bit (Chris). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60138 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63031 Cc: Egbert Eich Cc: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_sdvo.c |4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 33b46d9..35187d9 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -1219,8 +1219,12 @@ static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(&connector->base); struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); + struct drm_i915_private *dev_priv = intel_sdvo->base.base.dev->dev_private; u16 active_outputs; + if (!(I915_READ(intel_sdvo->sdvo_reg) & SDVO_ENABLE)) + return false; + intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); if (active_outputs & intel_sdvo_connector->output_flag) -- 1.7.10.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/11] drm/i915/dp: program VSwing and Preemphasis control settings on VLV
On Tue, 2 Apr 2013 21:04:29 +0200 Daniel Vetter wrote: > On Thu, Mar 28, 2013 at 09:55:46AM -0700, Jesse Barnes wrote: > > From: Pallavi G > > > > Program few Tx buffer Swing control settings through DPIO. > > > > Signed-off-by: Pallavi G > > Signed-off-by: Yogesh M > > Signed-off-by: Gajanan Bhat > > Grumpy maintainer is more grumpy: > > http://lists.freedesktop.org/archives/intel-gfx/2013-March/025831.html Sorry I did see that mail but must have missed the update. Will fix. -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: sprite support for ValleyView v4
On Tue, Apr 02, 2013 at 11:22:20AM -0700, Jesse Barnes wrote:
> No constant alpha yet though, that needs a new ioctl and/or property to
> get/set.
>
> v2: use drm_plane_format_cpp (Ville)
> fix up vlv_disable_plane, remove IVB bits (Ville)
> remove error path rework (Ville)
> fix component order confusion (Ville)
> clean up platform init (Ville)
> use compute_offset_xtiled (Ville)
> v3: fix up more format confusion (Ville)
> update to new page offset function (Ville)
> v4: remove incorrect formats from framebuffer_init (Ville)
>
> Reviewed-by: Ville Syrjälä
> Signed-off-by: Jesse Barnes
Ok, I've slurped in a few more patches and droped comments on a few
others. For the not-merged, not-commented-on ones I simply think someone
should grab vlv docs or hw and cross-check.
Cheers, Daniel
> ---
> drivers/gpu/drm/i915/i915_dma.c |4 +
> drivers/gpu/drm/i915/i915_drv.h |1 +
> drivers/gpu/drm/i915/i915_reg.h | 57 +
> drivers/gpu/drm/i915/intel_display.c | 11 +-
> drivers/gpu/drm/i915/intel_drv.h |3 +-
> drivers/gpu/drm/i915/intel_sprite.c | 213
> --
> 6 files changed, 275 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index ebcfe2e..4be58e3 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -1630,6 +1630,10 @@ int i915_driver_load(struct drm_device *dev, unsigned
> long flags)
> mutex_init(&dev_priv->rps.hw_lock);
> mutex_init(&dev_priv->modeset_restore_lock);
>
> + dev_priv->num_plane = 1;
> + if (IS_VALLEYVIEW(dev))
> + dev_priv->num_plane = 2;
> +
> ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
> if (ret)
> goto out_gem_unload;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1657d873..2832cdb 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -914,6 +914,7 @@ typedef struct drm_i915_private {
> bool enable_hotplug_processing;
>
> int num_pch_pll;
> + int num_plane;
>
> unsigned long cfb_size;
> unsigned int cfb_fb;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bceca11..d0f7cb9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3261,6 +3261,63 @@
> #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
> #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
>
> +#define _SPACNTR 0x72180
> +#define SP_ENABLE (1<<31)
> +#define SP_GEAMMA_ENABLE (1<<30)
> +#define SP_PIXFORMAT_MASK (0xf<<26)
> +#define SP_FORMAT_YUV422 (0<<26)
> +#define SP_FORMAT_BGR565 (5<<26)
> +#define SP_FORMAT_BGRX (6<<26)
> +#define SP_FORMAT_BGRA (7<<26)
> +#define SP_FORMAT_RGBX1010102 (8<<26)
> +#define SP_FORMAT_RGBA1010102 (9<<26)
> +#define SP_FORMAT_RGBX (0xe<<26)
> +#define SP_FORMAT_RGBA (0xf<<26)
> +#define SP_SOURCE_KEY (1<<22)
> +#define SP_YUV_BYTE_ORDER_MASK (3<<16)
> +#define SP_YUV_ORDER_YUYV (0<<16)
> +#define SP_YUV_ORDER_UYVY (1<<16)
> +#define SP_YUV_ORDER_YVYU (2<<16)
> +#define SP_YUV_ORDER_VYUY (3<<16)
> +#define SP_TILED (1<<10)
> +#define _SPALINOFF 0x72184
> +#define _SPASTRIDE 0x72188
> +#define _SPAPOS 0x7218c
> +#define _SPASIZE 0x72190
> +#define _SPAKEYMINVAL0x72194
> +#define _SPAKEYMSK 0x72198
> +#define _SPASURF 0x7219c
> +#define _SPAKEYMAXVAL0x721a0
> +#define _SPATILEOFF 0x721a4
> +#define _SPACONSTALPHA 0x721a8
> +#define _SPAGAMC 0x721f4
> +
> +#define _SPBCNTR 0x72280
> +#define _SPBLINOFF 0x72284
> +#define _SPBSTRIDE 0x72288
> +#define _SPBPOS 0x7228c
> +#define _SPBSIZE 0x72290
> +#define _SPBKEYMINVAL0x72294
> +#define _SPBKEYMSK 0x72298
> +#define _SPBSURF 0x7229c
> +#define _SPBKEYMAXVAL0x722a0
> +#define _SPBTILEOFF 0x722a4
> +#define _SPBCONSTALPHA 0x722a8
> +#define _SPBGAMC 0x722f4
> +
> +#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
> +#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
> +#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
> +#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
> +#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
> +#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL,
> _SPB
Re: [Intel-gfx] [PATCH 10/11] drm/i915/dp: program VSwing and Preemphasis control settings on VLV
On Thu, Mar 28, 2013 at 09:55:46AM -0700, Jesse Barnes wrote:
> From: Pallavi G
>
> Program few Tx buffer Swing control settings through DPIO.
>
> Signed-off-by: Pallavi G
> Signed-off-by: Yogesh M
> Signed-off-by: Gajanan Bhat
Grumpy maintainer is more grumpy:
http://lists.freedesktop.org/archives/intel-gfx/2013-March/025831.html
Cheers, Daniel
> ---
> drivers/gpu/drm/i915/intel_display.c |3 +-
> drivers/gpu/drm/i915/intel_dp.c | 114
> +-
> drivers/gpu/drm/i915/intel_drv.h |2 +
> 3 files changed, 115 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 5cc12dc..4364829 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -451,8 +451,7 @@ u32 intel_dpio_read(struct drm_i915_private *dev_priv,
> int reg)
> return I915_READ(DPIO_DATA);
> }
>
> -static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
> - u32 val)
> +void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
> {
> WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index dd9efe8..557a33b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1527,7 +1527,9 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> {
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
>
> - if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
> + if (IS_VALLEYVIEW(dev))
> + return DP_TRAIN_VOLTAGE_SWING_1200;
> + else if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
> return DP_TRAIN_VOLTAGE_SWING_800;
> else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
> return DP_TRAIN_VOLTAGE_SWING_1200;
> @@ -1552,7 +1554,19 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp,
> uint8_t voltage_swing)
> default:
> return DP_TRAIN_PRE_EMPHASIS_0;
> }
> - } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
> {
> + } else if (IS_VALLEYVIEW(dev)) {
> + switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> + case DP_TRAIN_VOLTAGE_SWING_400:
> + return DP_TRAIN_PRE_EMPHASIS_9_5;
> + case DP_TRAIN_VOLTAGE_SWING_600:
> + return DP_TRAIN_PRE_EMPHASIS_6;
> + case DP_TRAIN_VOLTAGE_SWING_800:
> + return DP_TRAIN_PRE_EMPHASIS_3_5;
> + case DP_TRAIN_VOLTAGE_SWING_1200:
> + default:
> + return DP_TRAIN_PRE_EMPHASIS_0;
> + }
> + } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
> switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> case DP_TRAIN_VOLTAGE_SWING_400:
> return DP_TRAIN_PRE_EMPHASIS_6;
> @@ -1577,15 +1591,111 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp,
> uint8_t voltage_swing)
> }
> }
>
> +static void vlv_set_vswing_pre_emphasis(struct intel_dp *intel_dp, uint8_t v,
> + uint8_t p)
> +{
> + struct drm_device *dev = intel_dp_to_dev(intel_dp);
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + unsigned long Demph_reg_value, Preemph_reg_value,
> + Uniqtranscale_reg_value;
> + switch (p) {
> + case DP_TRAIN_PRE_EMPHASIS_0:
> + Preemph_reg_value = 0x0004000;
> + switch (v) {
> + case DP_TRAIN_VOLTAGE_SWING_400:
> + Demph_reg_value = 0x2B40;
> + Uniqtranscale_reg_value = 0x552AB83A;
> + break;
> + case DP_TRAIN_VOLTAGE_SWING_600:
> + Demph_reg_value = 0x2B404040;
> + Uniqtranscale_reg_value = 0x5548B83A;
> + break;
> + case DP_TRAIN_VOLTAGE_SWING_800:
> + Demph_reg_value = 0x2B24;
> + Uniqtranscale_reg_value = 0x5560B83A;
> + break;
> + case DP_TRAIN_VOLTAGE_SWING_1200:
> + Demph_reg_value = 0x2B40;
> + Uniqtranscale_reg_value = 0x5598DA3A;
> + break;
> + default:
> + return;
> + }
> + break;
> + case DP_TRAIN_PRE_EMPHASIS_3_5:
> + Preemph_reg_value = 0x0002000;
> + switch (v) {
> + case DP_TRAIN_VOLTAGE_SWING_400:
> + Demph_reg_value = 0x2B404040;
> + Uniqtranscale_reg_value = 0x5552B83A;
> + break;
> + case DP_TRAIN_VOLTAGE_SWING_600:
> + Demph_reg_value = 0x2B404848;
> + Uniqtranscale_reg_value = 0x5580B83A;
> +
Re: [Intel-gfx] [PATCH] drm/i915: add Punit read/write routines for VLV v2
On Tue, Apr 02, 2013 at 11:23:05AM -0700, Jesse Barnes wrote: > Slightly different than other platforms. > > v2 [Jani]: Fix IOSF_BYTE_ENABLES_SHIFT shift. Use common routine. > v3: drop turbo defines from this patch (Ville) > use PCI_DEVFN(2,0) instead of open coding (Ville) > > Reviewed-by: Ville Syrjälä > Signed-off-by: Jesse Barnes > Signed-off-by: Jani Nikula Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 07/11] drm/i915: fix VLV limits and m/n/p calculations v2
On Thu, Mar 28, 2013 at 09:55:43AM -0700, Jesse Barnes wrote: > From: Pallavi G > > For high res modes m n p calculation is fixed for VLV platform. > > v2: use 64 bit types and math (Ville) > > Signed-off-by: Pallavi G > Signed-off-by: Vijay Purushothaman > Signed-off-by: Yogesh M > Signed-off-by: Gajanan Bhat I'd love to have a fixed dp pll values look-up table like we have for other platforms, so that we use _exactly_ what the hw guys recommend. Also: Did I mention that I've failed to count the indent level of the vlv pll computation function? And iirc that's been promised to eventually get fixed ... I'll random-punt on this one here for now. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/11] drm/i915: panel power sequencing for VLV eDP v2
On Thu, Mar 28, 2013 at 09:55:41AM -0700, Jesse Barnes wrote:
> PPS register offsets have changed in Valleyview.
>
> v2: don't clobber port select bits on VLV when fixing up PPS timings
> don't bother with G4x PPS regs (Jani)
>
> Signed-off-by: Jesse Barnes
> Signed-off-by: Gajanan Bhat
> Signed-off-by: Vijay Purushothaman
> Signed-off-by: Ben Widawsky
Someone should have seriously considered putting a pp_mmio_base somewhere
and switching this mess over to relative offsets, abolishing all the
VLV_PIPE_FOO and PIPE._BAR madness. Whoever is volunteered to enable the
pipe B pp stuff on vlv, please adjust your expectations ;-) Maybe even
consider shoveling everything into an intel_pp struct (including the
vbt/fixup code).
Queued for -next, thanks for the patch.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_reg.h |9 ++
> drivers/gpu/drm/i915/intel_dp.c | 173
> +++
> 2 files changed, 131 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 858a712..834e79f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4182,6 +4182,15 @@
> #define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
> #define PIPEB_PP_DIVISOR(VLV_DISPLAY_BASE + 0x61310)
>
> +#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS,
> PIPEB_PP_STATUS)
> +#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL,
> PIPEB_PP_CONTROL)
> +#define VLV_PIPE_PP_ON_DELAYS(pipe) \
> + _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
> +#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
> + _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
> +#define VLV_PIPE_PP_DIVISOR(pipe) \
> + _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
> +
> #define PCH_PP_STATUS0xc7200
> #define PCH_PP_CONTROL 0xc7204
> #define PANEL_UNLOCK_REGS (0xabcd << 16)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 7fb9213..dd9efe8 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -294,16 +294,20 @@ static bool ironlake_edp_have_panel_power(struct
> intel_dp *intel_dp)
> {
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
> struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 pp_stat_reg;
>
> - return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
> + pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> + return (I915_READ(pp_stat_reg) & PP_ON) != 0;
> }
>
> static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
> {
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
> struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 pp_ctrl_reg;
>
> - return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
> + pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> + return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
> }
>
> static void
> @@ -311,14 +315,19 @@ intel_dp_check_edp(struct intel_dp *intel_dp)
> {
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
> struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 pp_stat_reg, pp_ctrl_reg;
>
> if (!is_edp(intel_dp))
> return;
> +
> + pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> + pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
> +
> if (!ironlake_edp_have_panel_power(intel_dp) &&
> !ironlake_edp_have_panel_vdd(intel_dp)) {
> WARN(1, "eDP powered off while attempting aux channel
> communication.\n");
> DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
> - I915_READ(PCH_PP_STATUS),
> - I915_READ(PCH_PP_CONTROL));
> + I915_READ(pp_stat_reg),
> + I915_READ(pp_ctrl_reg));
> }
> }
>
> @@ -986,16 +995,20 @@ static void ironlake_wait_panel_status(struct intel_dp
> *intel_dp,
> {
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
> struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 pp_stat_reg, pp_ctrl_reg;
> +
> + pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> + pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
>
> DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
> - mask, value,
> - I915_READ(PCH_PP_STATUS),
> - I915_READ(PCH_PP_CONTROL));
> + mask, value,
> + I915_READ(pp_stat_reg),
> + I915_READ(pp_ctrl_reg));
>
> - if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
> + if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
> DRM_ERROR("Panel status timeout:
Re: [Intel-gfx] [PATCH 04/11] drm/i915/dp: fix up VLV DP handling v2
On Thu, Mar 28, 2013 at 09:55:40AM -0700, Jesse Barnes wrote:
> Needed to handle pre/post enable/disable paths on VLV and avoid a few
> fields that are marked reserved on VLV.
>
> v2: don't set color range or DP PLL fields (Jani)
>
> Signed-off-by: Jesse Barnes
This maze of platform checks in our DP code is getting messy. Still,
queued for -next, thanks for the patch.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_dp.c | 11 +++
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 2f2ec42..7fb9213 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -941,7 +941,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct
> drm_display_mode *mode,
> else
> intel_dp->DP |= DP_PLL_FREQ_270MHZ;
> } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
> - if (!HAS_PCH_SPLIT(dev))
> + if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
> intel_dp->DP |= intel_dp->color_range;
>
> if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> @@ -956,7 +956,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct
> drm_display_mode *mode,
> if (intel_crtc->pipe == 1)
> intel_dp->DP |= DP_PIPEB_SELECT;
>
> - if (is_cpu_edp(intel_dp)) {
> + if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> /* don't miss out required setting for eDP */
> if (adjusted_mode->clock < 20)
> intel_dp->DP |= DP_PLL_FREQ_160MHZ;
> @@ -1388,10 +1388,12 @@ static void intel_disable_dp(struct intel_encoder
> *encoder)
> static void intel_post_disable_dp(struct intel_encoder *encoder)
> {
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> + struct drm_device *dev = encoder->base.dev;
>
> if (is_cpu_edp(intel_dp)) {
> intel_dp_link_down(intel_dp);
> - ironlake_edp_pll_off(intel_dp);
> + if (!IS_VALLEYVIEW(dev))
> + ironlake_edp_pll_off(intel_dp);
> }
> }
>
> @@ -1417,8 +1419,9 @@ static void intel_enable_dp(struct intel_encoder
> *encoder)
> static void intel_pre_enable_dp(struct intel_encoder *encoder)
> {
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> + struct drm_device *dev = encoder->base.dev;
>
> - if (is_cpu_edp(intel_dp))
> + if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
> ironlake_edp_pll_on(intel_dp);
> }
>
> --
> 1.7.10.4
>
> ___
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
___
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Re: [Intel-gfx] [PATCH 03/11] drm/i915: update VLV PLL and DPIO code v8
On Thu, Mar 28, 2013 at 09:55:39AM -0700, Jesse Barnes wrote: > In Valleyview voltage swing, pre-emphasis and lane control registers can > be programmed only through the h/w side band fabric. Update > vlv_update_pll, i9xx_crtc_enable, and intel_enable_pll with the > appropriate programming. > > We need to make sure that the tx lane reset occurs in both the full mode > set and DPMS paths, so factor things out to allow that. > > v2: use different DPIO_DIVISOR values for VGA and DisplayPort > v3: Fix update pll logic to use same DPIO_DIVISOR & DPIO_REFSFR values > for all display interfaces > v4: collapse with various updates > v5: squash with crtc enable/pll enable bits > v6: split out DP code (jbarnes) > put phyready check under IS_VALLEYVIEW (jbarnes) > remove unneeded check in 9xx pll div update (Jani) > wrap VLV pll update call in IS_VALLEYVIEW (Jani) > move port enable back to end of crtc enable (jbarnes) > put phyready check under IS_VALLEYVIEW (jbarnes) > v7: fix up conflicts against latest drm-intel-next-queued > v8: use DPIO reg names, fix pipes (Jani) > from mPhy_registers_VLV2_ww20p5 doc > > Signed-off-by: Pallavi G > Signed-off-by: Vijay Purushothaman > Signed-off-by: Gajanan Bhat > Signed-off-by: Ben Widawsky Imo this is still a bit too horrible to live. Iirc I've had a massive bikeshed review, but then noticed that I don't understand at all what this code does and so dropped it. A few random things I've remembered: - There's lots of magic pipe checks, imo if (pipe == PIPE_B) reads better than if (pipe). Especially since we also have now platforms with more than just 2 pipes. Also s/1/PIPE_B/ at some places. - This patch does too much, e.g. vlv_init_dpio seems to now be used as a generic reset function in crtc_disable, but is still called _init. Also looks like an orthogonal patch to me. - Some of the #defines are seriously misguided as to whether they're dealing with a pipe or a port. Last time I've check some #defines weren't used, but I didn't bother this time around with checking them all again. - Some of the intel_has_type checks look fishy and would look better when replaced with a port enum or something like that. Others look like they hardcode pll selections in strange ways (I have no clue with all that magic). - intel_mode_get_pixel_multiplier is gone, so this doesn't apply on latest dinq. - Some function extraction looks easily doable, e.g. extracting the "port ready" wait in mode_set and crtc_enable - I still suspect that some of these checks/hacks predate the modeset rework since stuff is seemingly duplicated at a bunch of places ... I think some gentle patch splitting, slight refactoring and liberal sprinklig of FIXME comments should get this one here into shape. Especially if we know that a given piece of code here is just pre-silicon hacks or hard-wired to the sdv board layout. Cheers, Daniel > --- > drivers/gpu/drm/i915/i915_reg.h | 107 - > drivers/gpu/drm/i915/intel_display.c | 274 > ++ > 2 files changed, 320 insertions(+), 61 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index d0f7cb9..858a712 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -362,6 +362,11 @@ > #define DPIO_SFR_BYPASS (1<<1) > #define DPIO_RESET (1<<0) > > +#define _DPIO_TX3_SWING_CTL4_A 0x690 > +#define _DPIO_TX3_SWING_CTL4_B 0x2a90 > +#define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX_SWING_CTL4_A, \ > + _DPIO_TX3_SWING_CTL4_B) > + > #define _DPIO_DIV_A 0x800c > #define DPIO_POST_DIV_SHIFT(28) /* 3 bits */ > #define DPIO_K_SHIFT (24) /* 4 bits */ > @@ -389,14 +394,109 @@ > #define _DPIO_CORE_CLK_B 0x803c > #define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B) > > +#define _DPIO_IREF_CTL_A 0x8040 > +#define _DPIO_IREF_CTL_B 0x8060 > +#define DPIO_IREF_CTL(pipe) _PIPE(pipe, _DPIO_IREF_CTL_A, _DPIO_IREF_CTL_B) > + > +#define DPIO_IREF_BCAST 0xc044 > +#define _DPIO_IREF_A 0x8044 > +#define _DPIO_IREF_B 0x8064 > +#define DPIO_IREF(pipe) _PIPE(pipe, _DPIO_IREF_A, _DPIO_IREF_B) > + > +#define _DPIO_PLL_CML_A 0x804c > +#define _DPIO_PLL_CML_B 0x806c > +#define DPIO_PLL_CML(pipe) _PIPE(pipe, _DPIO_PLL_CML_A, _DPIO_PLL_CML_B) > + > #define _DPIO_LFP_COEFF_A0x8048 > #define _DPIO_LFP_COEFF_B0x8068 > #define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, > _DPIO_LFP_COEFF_B) > > +#define DPIO_CALIBRATION 0x80ac > + > #define DPIO_FASTCLK_DISABLE 0x8100 > > -#define DPIO_DATA_CHANNEL1 0x8220 > -#define DPIO_DATA_CHANNEL2
[Intel-gfx] [PATCH] drm/i915: drop DPFLIPSTAT enables on VLV v3
We don't need this until we start using the wait event commands. v2: move to i915_irq.c (Jesse) drop unneeded sprite flip done enables (Ville) v3: drop the DPFLIPSTAT enables altogether (Ville) Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_pm.c | 13 - 1 file changed, 13 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index fabe013..556e861 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4112,19 +4112,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev) _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); /* -* On ValleyView, the GUnit needs to signal the GT -* when flip and other events complete. So enable -* all the GUnit->GT interrupts here -*/ - I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN | - PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN | - SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN | - PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN | - PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN | - SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN | - PLANEA_FLIPDONE_INT_EN); - - /* * WaDisableVLVClockGating_VBIIssue * Disable clock gating on th GCFG unit to prevent a delay * in the reporting of vblank events. -- 1.7.10.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: turbo & RC6 support for VLV v4
From: Ben Widawsky
Uses slightly different interfaces than other platforms.
v2: track actual set freq, not requested (Rohit)
fix debug prints in init code (Jesse)
v3: don't write sleep reg (Jesse)
re-add RC6 wake limit write (Ben)
fixup thresholds to match other platforms (Ben)
clean up mem freq calculation (Ben)
clean up debug prints (Ben)
v4: move defines from punit patch (Ville)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/i915_irq.c |5 +-
drivers/gpu/drm/i915/i915_reg.h |9 +++
drivers/gpu/drm/i915/intel_pm.c | 145 +--
4 files changed, 155 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 642cb1f..68f1256 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1816,6 +1816,7 @@ extern void intel_disable_fbc(struct drm_device *dev);
extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
extern void intel_init_pch_refclk(struct drm_device *dev);
extern void gen6_set_rps(struct drm_device *dev, u8 val);
+extern void valleyview_set_rps(struct drm_device *dev, u8 val);
extern void intel_detect_pch(struct drm_device *dev);
extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
extern int intel_enable_rc6(const struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3c2b05c..46f6f1a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -394,7 +394,10 @@ static void gen6_pm_rps_work(struct work_struct *work)
*/
if (!(new_delay > dev_priv->rps.max_delay ||
new_delay < dev_priv->rps.min_delay)) {
- gen6_set_rps(dev_priv->dev, new_delay);
+ if (IS_VALLEYVIEW(dev_priv->dev))
+ valleyview_set_rps(dev_priv->dev, new_delay);
+ else
+ gen6_set_rps(dev_priv->dev, new_delay);
}
mutex_unlock(&dev_priv->rps.hw_lock);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 85f8b0b..e3fcc32 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4369,6 +4369,7 @@
#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
+#define GEN7_RC_CTL_TO_MODE (1<<28)
#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
#define GEN6_RC_CTL_HW_ENABLE(1<<31)
#define GEN6_RP_DOWN_TIMEOUT 0xA010
@@ -4465,6 +4466,14 @@
#define PUNIT_OPCODE_REG_READ 6
#define PUNIT_OPCODE_REG_WRITE 7
+#define PUNIT_REG_GPU_LFM 0xd3
+#define PUNIT_REG_GPU_FREQ_REQ 0xd4
+#define PUNIT_REG_GPU_FREQ_STS 0xd8
+#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
+
+#define PUNIT_FUSE_BUS20xf6 /* bits 47:40 */
+#define PUNIT_FUSE_BUS10xf5 /* bits 55:48 */
+
#define GEN6_GT_CORE_STATUS0x138060
#define GEN6_CORE_CPD_STATE_MASK (7<<4)
#define GEN6_RCn_MASK7
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9776281..fabe013 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2477,6 +2477,47 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
trace_intel_gpu_freq_change(val * 50);
}
+void valleyview_set_rps(struct drm_device *dev, u8 val)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned long timeout = jiffies + msecs_to_jiffies(100);
+ u32 limits = gen6_rps_limits(dev_priv, &val);
+ u32 pval;
+
+ WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+ WARN_ON(val > dev_priv->rps.max_delay);
+ WARN_ON(val < dev_priv->rps.min_delay);
+
+ if (val == dev_priv->rps.cur_delay)
+ return;
+
+ valleyview_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
+
+ do {
+ valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
+ if (time_after(jiffies, timeout)) {
+ DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
+ break;
+ }
+ udelay(10);
+ } while (pval & 1);
+
+ valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
+ if ((pval >> 8) != val)
+ DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got
%d\n",
+ val, pval >> 8);
+
+ /* Make sure we continue to get interrupts
+* until we hit the minimum or maximum frequencies.
+*/
+ I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
+
+ dev_priv->rps.cur_delay = pval >> 8;
+
+
[Intel-gfx] [PATCH] drm/i915: add Punit read/write routines for VLV v2
Slightly different than other platforms.
v2 [Jani]: Fix IOSF_BYTE_ENABLES_SHIFT shift. Use common routine.
v3: drop turbo defines from this patch (Ville)
use PCI_DEVFN(2,0) instead of open coding (Ville)
Reviewed-by: Ville Syrjälä
Signed-off-by: Jesse Barnes
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h |2 ++
drivers/gpu/drm/i915/i915_reg.h | 14 +++
drivers/gpu/drm/i915/intel_pm.c | 53 +++
3 files changed, 69 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 182c494..642cb1f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1845,6 +1845,8 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv);
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32
*val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32
val);
+int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32
*val);
+int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32
val);
#define __i915_read(x, y) \
u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 68051d6..85f8b0b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4451,6 +4451,20 @@
#define GEN6_PCODE_DATA0x138128
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
+#define VLV_IOSF_DOORBELL_REQ 0x182100
+#define IOSF_DEVFN_SHIFT 24
+#define IOSF_OPCODE_SHIFT16
+#define IOSF_PORT_SHIFT 8
+#define IOSF_BYTE_ENABLES_SHIFT 4
+#define IOSF_BAR_SHIFT 1
+#define IOSF_SB_BUSY (1<<0)
+#define IOSF_PORT_PUNIT 0x4
+#define VLV_IOSF_DATA 0x182104
+#define VLV_IOSF_ADDR 0x182108
+
+#define PUNIT_OPCODE_REG_READ 6
+#define PUNIT_OPCODE_REG_WRITE 7
+
#define GEN6_GT_CORE_STATUS0x138060
#define GEN6_CORE_CPD_STATE_MASK (7<<4)
#define GEN6_RCn_MASK7
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6fa9b79..9776281 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4525,3 +4525,56 @@ int sandybridge_pcode_write(struct drm_i915_private
*dev_priv, u8 mbox, u32 val)
return 0;
}
+
+static int vlv_punit_rw(struct drm_i915_private *dev_priv, u8 opcode,
+ u8 addr, u32 *val)
+{
+ u32 cmd, devfn, port, be, bar;
+
+ bar = 0;
+ be = 0xf;
+ port = IOSF_PORT_PUNIT;
+ devfn = PCI_DEVFN(2,0);
+
+ cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
+ (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
+ (bar << IOSF_BAR_SHIFT);
+
+ WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+ if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
+ DRM_DEBUG_DRIVER("warning: pcode (%s) mailbox access failed\n",
+opcode == PUNIT_OPCODE_REG_READ ?
+"read" : "write");
+ return -EAGAIN;
+ }
+
+ I915_WRITE(VLV_IOSF_ADDR, addr);
+ if (opcode == PUNIT_OPCODE_REG_WRITE)
+ I915_WRITE(VLV_IOSF_DATA, *val);
+ I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
+
+ if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
+500)) {
+ DRM_ERROR("timeout waiting for pcode %s (%d) to finish\n",
+ opcode == PUNIT_OPCODE_REG_READ ? "read" : "write",
+ addr);
+ return -ETIMEDOUT;
+ }
+
+ if (opcode == PUNIT_OPCODE_REG_READ)
+ *val = I915_READ(VLV_IOSF_DATA);
+ I915_WRITE(VLV_IOSF_DATA, 0);
+
+ return 0;
+}
+
+int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
+{
+ return vlv_punit_rw(dev_priv, PUNIT_OPCODE_REG_READ, addr, val);
+}
+
+int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
+{
+ return vlv_punit_rw(dev_priv, PUNIT_OPCODE_REG_WRITE, addr, &val);
+}
--
1.7.10.4
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[Intel-gfx] [PATCH] drm/i915: sprite support for ValleyView v4
No constant alpha yet though, that needs a new ioctl and/or property to
get/set.
v2: use drm_plane_format_cpp (Ville)
fix up vlv_disable_plane, remove IVB bits (Ville)
remove error path rework (Ville)
fix component order confusion (Ville)
clean up platform init (Ville)
use compute_offset_xtiled (Ville)
v3: fix up more format confusion (Ville)
update to new page offset function (Ville)
v4: remove incorrect formats from framebuffer_init (Ville)
Reviewed-by: Ville Syrjälä
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_dma.c |4 +
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/i915_reg.h | 57 +
drivers/gpu/drm/i915/intel_display.c | 11 +-
drivers/gpu/drm/i915/intel_drv.h |3 +-
drivers/gpu/drm/i915/intel_sprite.c | 213 --
6 files changed, 275 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index ebcfe2e..4be58e3 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1630,6 +1630,10 @@ int i915_driver_load(struct drm_device *dev, unsigned
long flags)
mutex_init(&dev_priv->rps.hw_lock);
mutex_init(&dev_priv->modeset_restore_lock);
+ dev_priv->num_plane = 1;
+ if (IS_VALLEYVIEW(dev))
+ dev_priv->num_plane = 2;
+
ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
if (ret)
goto out_gem_unload;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1657d873..2832cdb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -914,6 +914,7 @@ typedef struct drm_i915_private {
bool enable_hotplug_processing;
int num_pch_pll;
+ int num_plane;
unsigned long cfb_size;
unsigned int cfb_fb;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bceca11..d0f7cb9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3261,6 +3261,63 @@
#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
+#define _SPACNTR 0x72180
+#define SP_ENABLE(1<<31)
+#define SP_GEAMMA_ENABLE (1<<30)
+#define SP_PIXFORMAT_MASK(0xf<<26)
+#define SP_FORMAT_YUV422 (0<<26)
+#define SP_FORMAT_BGR565 (5<<26)
+#define SP_FORMAT_BGRX (6<<26)
+#define SP_FORMAT_BGRA (7<<26)
+#define SP_FORMAT_RGBX1010102(8<<26)
+#define SP_FORMAT_RGBA1010102(9<<26)
+#define SP_FORMAT_RGBX (0xe<<26)
+#define SP_FORMAT_RGBA (0xf<<26)
+#define SP_SOURCE_KEY(1<<22)
+#define SP_YUV_BYTE_ORDER_MASK (3<<16)
+#define SP_YUV_ORDER_YUYV(0<<16)
+#define SP_YUV_ORDER_UYVY(1<<16)
+#define SP_YUV_ORDER_YVYU(2<<16)
+#define SP_YUV_ORDER_VYUY(3<<16)
+#define SP_TILED (1<<10)
+#define _SPALINOFF 0x72184
+#define _SPASTRIDE 0x72188
+#define _SPAPOS0x7218c
+#define _SPASIZE 0x72190
+#define _SPAKEYMINVAL 0x72194
+#define _SPAKEYMSK 0x72198
+#define _SPASURF 0x7219c
+#define _SPAKEYMAXVAL 0x721a0
+#define _SPATILEOFF0x721a4
+#define _SPACONSTALPHA 0x721a8
+#define _SPAGAMC 0x721f4
+
+#define _SPBCNTR 0x72280
+#define _SPBLINOFF 0x72284
+#define _SPBSTRIDE 0x72288
+#define _SPBPOS0x7228c
+#define _SPBSIZE 0x72290
+#define _SPBKEYMINVAL 0x72294
+#define _SPBKEYMSK 0x72298
+#define _SPBSURF 0x7229c
+#define _SPBKEYMAXVAL 0x722a0
+#define _SPBTILEOFF0x722a4
+#define _SPBCONSTALPHA 0x722a8
+#define _SPBGAMC 0x722f4
+
+#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
+#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
+#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
+#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
+#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
+#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL,
_SPBKEYMINVAL)
+#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
+#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
+#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL,
_SPBKEYMAXVAL)
+#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF,
_SPBTILEOFF)
+#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA,
_SPBCONSTALPHA)
Re: [Intel-gfx] [PATCH 03/13] drm/i915: Wrap the preallocated BIOS framebuffer and preserve for KMS fbcon v3
On Tue, Apr 02, 2013 at 10:03:47AM -0700, Jesse Barnes wrote:
> v2: check for non-native modes and adjust (Jesse)
> fixup aperture and cmap frees (Imre)
> use unlocked unref if init_bios fails (Jesse)
> fix curly brace around DSPADDR check (Imre)
> comment failure path for pin_and_fence (Imre)
> v3: fixup fixup of aperture frees (Chris)
>
> Signed-off-by: Chris Wilson
> Signed-off-by: Jesse Barnes
> ---
> drivers/gpu/drm/i915/i915_dma.c |8 +-
> drivers/gpu/drm/i915/i915_drv.h |2 +-
> drivers/gpu/drm/i915/intel_display.c | 14 +-
> drivers/gpu/drm/i915/intel_drv.h |4 +
> drivers/gpu/drm/i915/intel_fb.c | 295
> --
> 5 files changed, 304 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index ebcfe2e..1389247 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -1273,6 +1273,7 @@ static const struct vga_switcheroo_client_ops
> i915_switcheroo_ops = {
> static int i915_load_modeset_init(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> + bool was_vga_enabled;
> int ret;
>
> ret = intel_parse_bios(dev);
> @@ -1309,7 +1310,11 @@ static int i915_load_modeset_init(struct drm_device
> *dev)
>
> /* Important: The output setup functions called by modeset_init need
>* working irqs for e.g. gmbus and dp aux transfers. */
> - intel_modeset_init(dev);
> + intel_modeset_init(dev, &was_vga_enabled);
> +
> + /* Wrap existing BIOS mode configuration prior to GEM takeover */
> + if (!was_vga_enabled)
> + intel_fbdev_init_bios(dev);
I'm not really happy that the fbdev is initialized at different points
here depending upon whether. Also this seems to tie the bios fb
reconstruction quite heavily into our fbdev code ...
Can't we instead reconstruct the bios fb in intel_modeset_setup_hw_state
and assign it to each active crtc if we detect one? The fbdev init code
down below could then check whether the in-use fbs are suitable or not.
That would also make it easier to move some of the pipe state readout into
the pipe_config hw state checking/read out infrastructure. Since that's
only setup up at the end of modeset_gem_init. Or do I miss a delicate
ordering constraint here?
-Daniel
>
> ret = i915_gem_init(dev);
> if (ret)
> @@ -1323,6 +1328,7 @@ static int i915_load_modeset_init(struct drm_device
> *dev)
> /* FIXME: do pre/post-mode set stuff in core KMS code */
> dev->vblank_disable_allowed = 1;
>
> + /* Install a default KMS/GEM fbcon if we failed to wrap the BIOS fb */
> ret = intel_fbdev_init(dev);
> if (ret)
> goto cleanup_gem;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7f6452b..d32ed27 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1806,7 +1806,7 @@ static inline void intel_unregister_dsm_handler(void) {
> return; }
>
> /* modesetting */
> extern void intel_modeset_init_hw(struct drm_device *dev);
> -extern void intel_modeset_init(struct drm_device *dev);
> +extern void intel_modeset_init(struct drm_device *dev, bool
> *was_vga_enabled);
> extern void intel_modeset_gem_init(struct drm_device *dev);
> extern void intel_modeset_cleanup(struct drm_device *dev);
> extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index dfc8152..a55ef8f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8854,12 +8854,17 @@ static void intel_init_quirks(struct drm_device *dev)
> }
>
> /* Disable the VGA plane that we never use */
> -static void i915_disable_vga(struct drm_device *dev)
> +static bool i915_disable_vga(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> + bool was_enabled;
> u8 sr1;
> u32 vga_reg = i915_vgacntrl_reg(dev);
>
> + was_enabled = !(I915_READ(vga_reg) & VGA_DISP_DISABLE);
> + DRM_DEBUG_KMS("VGA output is currently %s\n",
> + was_enabled ? "enabled" : "disabled");
> +
> vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
> outb(SR01, VGA_SR_INDEX);
> sr1 = inb(VGA_SR_DATA);
> @@ -8869,6 +8874,8 @@ static void i915_disable_vga(struct drm_device *dev)
>
> I915_WRITE(vga_reg, VGA_DISP_DISABLE);
> POSTING_READ(vga_reg);
> +
> + return was_enabled;
> }
>
> void intel_modeset_init_hw(struct drm_device *dev)
> @@ -8884,7 +8891,8 @@ void intel_modeset_init_hw(struct drm_device *dev)
> mutex_unlock(&dev->struct_mutex);
> }
>
> -void intel_modeset_init(struct drm_device *dev)
> +void intel_modeset_init(struct drm_device *dev,
> + bool *was_vga_en
Re: [Intel-gfx] [PATCH 11/11] drm/i915: limit DPFLIPSTAT enables to those we use on VLV
On Tue, 2 Apr 2013 21:14:30 +0300 Ville Syrjälä wrote: > On Tue, Apr 02, 2013 at 11:09:30AM -0700, Jesse Barnes wrote: > > On Tue, 2 Apr 2013 13:37:50 +0300 > > Ville Syrjälä wrote: > > > > > On Thu, Mar 28, 2013 at 09:55:47AM -0700, Jesse Barnes wrote: > > > > Thus preventing the display from keeping the GT awake with unnecessary > > > > signals. > > > > > > > > Signed-off-by: Jesse Barnes > > > > --- > > > > drivers/gpu/drm/i915/intel_pm.c |6 ++ > > > > 1 file changed, 2 insertions(+), 4 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > > > > b/drivers/gpu/drm/i915/intel_pm.c > > > > index 2b02702..de9f898 100644 > > > > --- a/drivers/gpu/drm/i915/intel_pm.c > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > > > @@ -4116,11 +4116,9 @@ static void valleyview_init_clock_gating(struct > > > > drm_device *dev) > > > > * when flip and other events complete. So enable > > > > * all the GUnit->GT interrupts here > > > > */ > > > > - I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN | > > > > - PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN | > > > > + I915_WRITE(VLV_DPFLIPSTAT, > > > >SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN | > > > > - PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN | > > > > - PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN | > > > > + PLANEB_FLIPDONE_INT_EN | > > > >SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN | > > > >PLANEA_FLIPDONE_INT_EN); > > > > > > We're not doing CS page flips w/ sprites currently, so I think you > > > could drop the sprite bits too. > > > > Ok thanks, will drop. > > > > > > > > Actually, now that I think about it, do we need any bits enabled here? > > > i915_gem_execbuffer_wait_for_flips() is gone, so AFAICS GT no longer > > > needs to know when page flips complete. > > > > We still use the flipdone interrupt for tracking fb state though, for > > unpinning the buffer. > > AFAIK this register only controls the display->GT signals, but > shouldn't affect the CPU display interrupts. Oh right, it should just enable the wait events... so yeah we can drop it if/until we start using vblank waits again. Thanks, -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/11] drm/i915: add Punit read/write routines for VLV
On Tue, 2 Apr 2013 14:37:42 +0300 Ville Syrjälä wrote: > On Thu, Mar 28, 2013 at 09:55:44AM -0700, Jesse Barnes wrote: > > Slightly different than other platforms. > > > > v2 [Jani]: Fix IOSF_BYTE_ENABLES_SHIFT shift. Use common routine. > > > > Signed-off-by: Jesse Barnes > > Signed-off-by: Jani Nikula Fixed these up, thanks. -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 11/11] drm/i915: limit DPFLIPSTAT enables to those we use on VLV
On Tue, Apr 02, 2013 at 11:09:30AM -0700, Jesse Barnes wrote: > On Tue, 2 Apr 2013 13:37:50 +0300 > Ville Syrjälä wrote: > > > On Thu, Mar 28, 2013 at 09:55:47AM -0700, Jesse Barnes wrote: > > > Thus preventing the display from keeping the GT awake with unnecessary > > > signals. > > > > > > Signed-off-by: Jesse Barnes > > > --- > > > drivers/gpu/drm/i915/intel_pm.c |6 ++ > > > 1 file changed, 2 insertions(+), 4 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > > > b/drivers/gpu/drm/i915/intel_pm.c > > > index 2b02702..de9f898 100644 > > > --- a/drivers/gpu/drm/i915/intel_pm.c > > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > > @@ -4116,11 +4116,9 @@ static void valleyview_init_clock_gating(struct > > > drm_device *dev) > > >* when flip and other events complete. So enable > > >* all the GUnit->GT interrupts here > > >*/ > > > - I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN | > > > -PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN | > > > + I915_WRITE(VLV_DPFLIPSTAT, > > > SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN | > > > -PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN | > > > -PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN | > > > +PLANEB_FLIPDONE_INT_EN | > > > SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN | > > > PLANEA_FLIPDONE_INT_EN); > > > > We're not doing CS page flips w/ sprites currently, so I think you > > could drop the sprite bits too. > > Ok thanks, will drop. > > > > > Actually, now that I think about it, do we need any bits enabled here? > > i915_gem_execbuffer_wait_for_flips() is gone, so AFAICS GT no longer > > needs to know when page flips complete. > > We still use the flipdone interrupt for tracking fb state though, for > unpinning the buffer. AFAIK this register only controls the display->GT signals, but shouldn't affect the CPU display interrupts. -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/11] drm/i915: sprite support for ValleyView v3
On Tue, 2 Apr 2013 13:26:47 +0300
Ville Syrjälä wrote:
> On Thu, Mar 28, 2013 at 09:55:37AM -0700, Jesse Barnes wrote:
> > No constant alpha yet though, that needs a new ioctl and/or property to
> > get/set.
> >
> > v2: use drm_plane_format_cpp (Ville)
> > fix up vlv_disable_plane, remove IVB bits (Ville)
> > remove error path rework (Ville)
> > fix component order confusion (Ville)
> > clean up platform init (Ville)
> > use compute_offset_xtiled (Ville)
> > v3: fix up more format confusion (Ville)
> > update to new page offset function (Ville)
> >
> > Signed-off-by: Jesse Barnes
> > ---
> > drivers/gpu/drm/i915/i915_dma.c |4 +
> > drivers/gpu/drm/i915/i915_drv.h |1 +
> > drivers/gpu/drm/i915/i915_reg.h | 57 +
> > drivers/gpu/drm/i915/intel_display.c | 13 ++-
> > drivers/gpu/drm/i915/intel_drv.h |3 +-
> > drivers/gpu/drm/i915/intel_sprite.c | 213
> > --
> > 6 files changed, 277 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_dma.c
> > b/drivers/gpu/drm/i915/i915_dma.c
> > index ebcfe2e..4be58e3 100644
> > --- a/drivers/gpu/drm/i915/i915_dma.c
> > +++ b/drivers/gpu/drm/i915/i915_dma.c
> > @@ -1630,6 +1630,10 @@ int i915_driver_load(struct drm_device *dev,
> > unsigned long flags)
> > mutex_init(&dev_priv->rps.hw_lock);
> > mutex_init(&dev_priv->modeset_restore_lock);
> >
> > + dev_priv->num_plane = 1;
> > + if (IS_VALLEYVIEW(dev))
> > + dev_priv->num_plane = 2;
> > +
> > ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
> > if (ret)
> > goto out_gem_unload;
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 1657d873..2832cdb 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -914,6 +914,7 @@ typedef struct drm_i915_private {
> > bool enable_hotplug_processing;
> >
> > int num_pch_pll;
> > + int num_plane;
> >
> > unsigned long cfb_size;
> > unsigned int cfb_fb;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index bceca11..d0f7cb9 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3261,6 +3261,63 @@
> > #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
> > #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
> >
> > +#define _SPACNTR 0x72180
> > +#define SP_ENABLE(1<<31)
> > +#define SP_GEAMMA_ENABLE (1<<30)
> > +#define SP_PIXFORMAT_MASK(0xf<<26)
> > +#define SP_FORMAT_YUV422 (0<<26)
> > +#define SP_FORMAT_BGR565 (5<<26)
> > +#define SP_FORMAT_BGRX (6<<26)
> > +#define SP_FORMAT_BGRA (7<<26)
> > +#define SP_FORMAT_RGBX1010102(8<<26)
> > +#define SP_FORMAT_RGBA1010102(9<<26)
> > +#define SP_FORMAT_RGBX (0xe<<26)
> > +#define SP_FORMAT_RGBA (0xf<<26)
> > +#define SP_SOURCE_KEY(1<<22)
> > +#define SP_YUV_BYTE_ORDER_MASK (3<<16)
> > +#define SP_YUV_ORDER_YUYV(0<<16)
> > +#define SP_YUV_ORDER_UYVY(1<<16)
> > +#define SP_YUV_ORDER_YVYU(2<<16)
> > +#define SP_YUV_ORDER_VYUY(3<<16)
> > +#define SP_TILED (1<<10)
> > +#define _SPALINOFF 0x72184
> > +#define _SPASTRIDE 0x72188
> > +#define _SPAPOS0x7218c
> > +#define _SPASIZE 0x72190
> > +#define _SPAKEYMINVAL 0x72194
> > +#define _SPAKEYMSK 0x72198
> > +#define _SPASURF 0x7219c
> > +#define _SPAKEYMAXVAL 0x721a0
> > +#define _SPATILEOFF0x721a4
> > +#define _SPACONSTALPHA 0x721a8
> > +#define _SPAGAMC 0x721f4
> > +
> > +#define _SPBCNTR 0x72280
> > +#define _SPBLINOFF 0x72284
> > +#define _SPBSTRIDE 0x72288
> > +#define _SPBPOS0x7228c
> > +#define _SPBSIZE 0x72290
> > +#define _SPBKEYMINVAL 0x72294
> > +#define _SPBKEYMSK 0x72298
> > +#define _SPBSURF 0x7229c
> > +#define _SPBKEYMAXVAL 0x722a0
> > +#define _SPBTILEOFF0x722a4
> > +#define _SPBCONSTALPHA 0x722a8
> > +#define _SPBGAMC 0x722f4
> > +
> > +#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
> > +#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF,
> > _SPBLINOFF)
> > +#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE,
> > _SPBSTRIDE)
> > +#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
> > +#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
> > +#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL,
> > _SPBKE
Re: [Intel-gfx] [PATCH 11/11] drm/i915: limit DPFLIPSTAT enables to those we use on VLV
On Tue, 2 Apr 2013 13:37:50 +0300 Ville Syrjälä wrote: > On Thu, Mar 28, 2013 at 09:55:47AM -0700, Jesse Barnes wrote: > > Thus preventing the display from keeping the GT awake with unnecessary > > signals. > > > > Signed-off-by: Jesse Barnes > > --- > > drivers/gpu/drm/i915/intel_pm.c |6 ++ > > 1 file changed, 2 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > > b/drivers/gpu/drm/i915/intel_pm.c > > index 2b02702..de9f898 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -4116,11 +4116,9 @@ static void valleyview_init_clock_gating(struct > > drm_device *dev) > > * when flip and other events complete. So enable > > * all the GUnit->GT interrupts here > > */ > > - I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN | > > - PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN | > > + I915_WRITE(VLV_DPFLIPSTAT, > >SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN | > > - PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN | > > - PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN | > > + PLANEB_FLIPDONE_INT_EN | > >SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN | > >PLANEA_FLIPDONE_INT_EN); > > We're not doing CS page flips w/ sprites currently, so I think you > could drop the sprite bits too. Ok thanks, will drop. > > Actually, now that I think about it, do we need any bits enabled here? > i915_gem_execbuffer_wait_for_flips() is gone, so AFAICS GT no longer > needs to know when page flips complete. We still use the flipdone interrupt for tracking fb state though, for unpinning the buffer. -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: fix intel_framebuffer_pitch_for_width for <8bpp
On Tue, Apr 02, 2013 at 10:28:11AM -0700, Jesse Barnes wrote:
> As Imre pointed out, this will do the wrong thing.
>
> Reported-by: Imre Deak
> Signed-off-by: Jesse Barnes
We don't actually support anything w/ bpp%8!=0, so either works.
Actually, for something like bpp=4, the original code might even be
more correct. But I don't really want to think about <8bpp stuff,
so I won't object to the patch.
> ---
> drivers/gpu/drm/i915/intel_drv.h |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 37f4bb3..18f0547 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -137,7 +137,7 @@ struct intel_framebuffer {
> inline static u32
> intel_framebuffer_pitch_for_width(int width, int bpp)
> {
> - u32 pitch = DIV_ROUND_UP(width * bpp, 8);
> + u32 pitch = width * DIV_ROUND_UP(bpp, 8);
> return ALIGN(pitch, 64);
> }
>
> --
> 1.7.9.5
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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Re: [Intel-gfx] [PATCH 12/13] drm/i915: fix DP get_hw_state return value
On Tue, Apr 02, 2013 at 10:03:56AM -0700, Jesse Barnes wrote: > If we couldn't find a pipe we shouldn't return true. This might be even > better as a WARN though, since it should be impossible to have the port > enabled without a pipe selected. > > Signed-off-by: Jesse Barnes These two fixes are merged for -next, thanks. -Daniel > --- > drivers/gpu/drm/i915/intel_dp.c |2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index e1b0c94..720ff50 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -1366,7 +1366,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder > *encoder, > intel_dp->output_reg); > } > > - return true; > + return false; > } > > static unsigned intel_dp_get_mode_flags(struct intel_encoder *encoder) > -- > 1.7.9.5 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 07/13] drm/i915: check panel fit status at update_plane time v2
On Tue, 2 Apr 2013 19:58:37 +0200 Daniel Vetter wrote: > On Tue, Apr 02, 2013 at 10:03:51AM -0700, Jesse Barnes wrote: > > We may need to disable the panel when flipping to a new buffer, so check > > the state here and zero it out if needed, otherwise leave it alone. > > > > v2: fixup pipe_set_base check (Imre) > > > > Signed-off-by: Jesse Barnes > > tbh I have no idea yet how we should best handle this and the following > patch. My current guess is that we need a special pipe_update path, which > sits in between the fb_update and the full modeset we currently have. A > bunch of things we might want to do in that case: > - kill the vga plane > - update watermarks to our (hopefully power-efficient) ones > - adjust pfit state (the bios tends to enable that even on non-lvds/edp > outputs) > - update other/global pm state (power well, refclocks, ...) > - update infoframes/audio bits (not relevant for panels luckily) > > Of course I'd prefer if the code is somehow shared between the update_pipe > path and the full modeset, since we'll inevitably get something wrong ... Agree that we should share code paths where possible. I think we could add new paths in enable/disable crtc for adjusting the global state. pfit would probably fit better there anyway, since it's not really panel specific. -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 07/13] drm/i915: check panel fit status at update_plane time v2
On Tue, Apr 02, 2013 at 10:03:51AM -0700, Jesse Barnes wrote: > We may need to disable the panel when flipping to a new buffer, so check > the state here and zero it out if needed, otherwise leave it alone. > > v2: fixup pipe_set_base check (Imre) > > Signed-off-by: Jesse Barnes tbh I have no idea yet how we should best handle this and the following patch. My current guess is that we need a special pipe_update path, which sits in between the fb_update and the full modeset we currently have. A bunch of things we might want to do in that case: - kill the vga plane - update watermarks to our (hopefully power-efficient) ones - adjust pfit state (the bios tends to enable that even on non-lvds/edp outputs) - update other/global pm state (power well, refclocks, ...) - update infoframes/audio bits (not relevant for panels luckily) Of course I'd prefer if the code is somehow shared between the update_pipe path and the full modeset, since we'll inevitably get something wrong ... -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/9] drm/i915: Skip modifying PCH DREF if not changing clock sources
On Thu, Mar 28, 2013 at 09:27:31AM +0200, Jani Nikula wrote:
> On Wed, 27 Mar 2013, Jesse Barnes wrote:
> > From: Chris Wilson
> >
> > Modifying the clock sources (via the DREF control on the PCH) is a slow
> > multi-stage process as we need to let the clocks stabilise between each
> > stage. If we are not actually changing the clock sources, then we can
> > return early.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 83
> > +-
> > 1 file changed, 61 insertions(+), 22 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 8f0db8c..9d05b30 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4833,7 +4833,7 @@ static void ironlake_init_pch_refclk(struct
> > drm_device *dev)
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > struct drm_mode_config *mode_config = &dev->mode_config;
> > struct intel_encoder *encoder;
> > - u32 temp;
> > + u32 val, final;
> > bool has_lvds = false;
> > bool has_cpu_edp = false;
> > bool has_pch_edp = false;
> > @@ -4876,70 +4876,109 @@ static void ironlake_init_pch_refclk(struct
> > drm_device *dev)
> > * PCH B stepping, previous chipset stepping should be
> > * ignoring this setting.
> > */
> > - temp = I915_READ(PCH_DREF_CONTROL);
> > + val = I915_READ(PCH_DREF_CONTROL);
> > +
> > + /* As we must carefully and slowly disable/enable each source in turn,
> > +* compute the final state we want first and check if we need to
> > +* make any changes at all.
> > +*/
> > + final = val;
> > + final &= ~DREF_NONSPREAD_SOURCE_MASK;
> > + if (has_ck505)
> > + final |= DREF_NONSPREAD_CK505_ENABLE;
> > + else
> > + final |= DREF_NONSPREAD_SOURCE_ENABLE;
> > +
> > + final &= ~DREF_SSC_SOURCE_MASK;
> > + final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
> > + final &= ~DREF_SSC1_ENABLE;
> > +
> > + if (has_panel) {
> > + final |= DREF_SSC_SOURCE_ENABLE;
> > +
> > + if (intel_panel_use_ssc(dev_priv) && can_ssc)
> > + final |= DREF_SSC1_ENABLE;
> > +
> > + if (has_cpu_edp) {
> > + if (intel_panel_use_ssc(dev_priv) && can_ssc)
> > + final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
> > + else
> > + final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
> > + } else
> > + final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
>
> I've been assimilated, I dislike not having braces in all branches if
> one branch requires them... but that's bikeshedding. On the stuff that
> matters,
I've punted on this bikeshed (checkpatch didn't yell), but fixed another
one ;-)
>
> Reviewed-by: Jani Nikula
I've figured that speeding this up and moving it into
->global_modeset_resources are rather orthogonal, since even with fastboot
we might want to adjust pm state a bit (e.g. with the power wells stuff).
So even when this is move into the modeset code and thought more clever
tricks, we'll still run it in the boot-up modeset path.
Queued for -next, thanks for the patch.
-Daniel
--
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Software Engineer, Intel Corporation
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Re: [Intel-gfx] [PATCH i-g-t 3/5] tests: Use IGT_SIMULATION to tune the list of tests to run
On Tue, Apr 02, 2013 at 06:16:59PM +0100, Damien Lespiau wrote: > On Tue, Apr 02, 2013 at 10:06:37AM -0700, Ben Widawsky wrote: > > > [Sun, Yi] So what's the conclusion, how can I do to solve the too long > > > time issue? > > > I noticed Damien's patches aren't on the branch yet. > > > If we want to split all i-g-t test cases to different HAS, how can we > > > split it? > > > > > > > Daniel, can you please advise Sun Yi since the solution I like has been > > shot down? > > It's not unreasonable to want to run test cases by default and black > list the ones we don't want to run. I'm on holidays soon though and > won't be able to rework this before a little while. tbh I'm not set in stone on this issue, and blocking enabling on fulsim feels bad, too. So please go ahead with whatever approach you deem best. Since for both approaches the interface for QA/testing would be just a magic enviroment variable, we could even switch without much fuzz. So I don't mind if you go ahead with the current patches. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: fix intel_framebuffer_pitch_for_width for <8bpp
As Imre pointed out, this will do the wrong thing.
Reported-by: Imre Deak
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_drv.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 37f4bb3..18f0547 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -137,7 +137,7 @@ struct intel_framebuffer {
inline static u32
intel_framebuffer_pitch_for_width(int width, int bpp)
{
- u32 pitch = DIV_ROUND_UP(width * bpp, 8);
+ u32 pitch = width * DIV_ROUND_UP(bpp, 8);
return ALIGN(pitch, 64);
}
--
1.7.9.5
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Re: [Intel-gfx] [PATCH i-g-t 3/5] tests: Use IGT_SIMULATION to tune the list of tests to run
On Tue, Apr 02, 2013 at 10:06:37AM -0700, Ben Widawsky wrote: > > [Sun, Yi] So what's the conclusion, how can I do to solve the too long time > > issue? > > I noticed Damien's patches aren't on the branch yet. > > If we want to split all i-g-t test cases to different HAS, how can we split > > it? > > > > Daniel, can you please advise Sun Yi since the solution I like has been > shot down? It's not unreasonable to want to run test cases by default and black list the ones we don't want to run. I'm on holidays soon though and won't be able to rework this before a little while. -- Damien ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 02/13] drm/i915: Split the framebuffer_info creation into a separate routine
On Tue, Apr 02, 2013 at 10:03:46AM -0700, Jesse Barnes wrote:
> static u32
> -intel_framebuffer_pitch_for_width(int width, int bpp)
> -{
> - u32 pitch = DIV_ROUND_UP(width * bpp, 8);
> - return ALIGN(pitch, 64);
> -}
Before this patch we need:
statuc u32 intel_framebuffer_pitch_for_width(int width, int bpp)
{
u32 pitch = width * DIV_ROUND_UP(bpp, 8);
return ALIGN(pitch, 64);
}
to address the issue Imre pointed out earlier.
-Chris
--
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[Intel-gfx] [PATCH 10/13] drm/i915: fetch PCH PLL state at init time
We need to properly track PCH PLL sharing configs, and generally set up
PCH PLL state at init time as part of the state readout process.
I-told-you-so-by: Daniel Vetter
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 51 ++
1 file changed, 51 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8b55427..208dde4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6915,6 +6915,54 @@ static int ironlake_crtc_clock_get(struct drm_crtc *crtc)
return clock;
}
+static bool ironlake_crtc_pll_get(struct drm_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ u32 dpll_sel;
+
+ if (HAS_PCH_IBX(dev_priv->dev))
+ intel_crtc->pch_pll = &dev_priv->pch_plls[intel_crtc->pipe];
+
+ if (HAS_PCH_CPT(dev_priv->dev)) {
+ dpll_sel = I915_READ(PCH_DPLL_SEL);
+
+ switch (intel_crtc->pipe) {
+ case PIPE_A:
+ if ((dpll_sel & TRANSA_DPLL_ENABLE) &&
+ (dpll_sel & TRANSA_DPLLB_SEL))
+ intel_crtc->pch_pll = &dev_priv->pch_plls[1];
+ else if (dpll_sel & TRANSA_DPLL_ENABLE)
+ intel_crtc->pch_pll = &dev_priv->pch_plls[0];
+ break;
+ case PIPE_B:
+ if ((dpll_sel & TRANSB_DPLL_ENABLE) &&
+ (dpll_sel & TRANSB_DPLLB_SEL))
+ intel_crtc->pch_pll = &dev_priv->pch_plls[1];
+ else if (dpll_sel & TRANSB_DPLL_ENABLE)
+ intel_crtc->pch_pll = &dev_priv->pch_plls[0];
+ break;
+ case PIPE_C:
+ if ((dpll_sel & TRANSC_DPLL_ENABLE) &&
+ (dpll_sel & TRANSC_DPLLB_SEL))
+ intel_crtc->pch_pll = &dev_priv->pch_plls[1];
+ else if (dpll_sel & TRANSC_DPLL_ENABLE)
+ intel_crtc->pch_pll = &dev_priv->pch_plls[0];
+ break;
+ default:
+ break;
+ }
+ }
+
+ if (intel_crtc->pch_pll) {
+ intel_crtc->pch_pll->refcount++;
+ intel_crtc->pch_pll->active = 1;
+ return true;
+ }
+
+ return false;
+}
+
static bool ironlake_crtc_get_mode(struct drm_crtc *crtc,
struct drm_display_mode *mode)
{
@@ -6943,6 +6991,9 @@ static bool ironlake_crtc_get_mode(struct drm_crtc *crtc,
mode->clock = ironlake_crtc_clock_get(crtc);
+ if (!ironlake_crtc_pll_get(crtc))
+ return false;
+
drm_mode_set_name(mode);
return true;
--
1.7.9.5
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[Intel-gfx] [PATCH 12/13] drm/i915: fix DP get_hw_state return value
If we couldn't find a pipe we shouldn't return true. This might be even better as a WARN though, since it should be impossible to have the port enabled without a pipe selected. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_dp.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index e1b0c94..720ff50 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1366,7 +1366,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder, intel_dp->output_reg); } - return true; + return false; } static unsigned intel_dp_get_mode_flags(struct intel_encoder *encoder) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 13/13] drm/i915: drop check for invalid pipe after fetching current hw state
Shouldn't be possible with return value fixes.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c |4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 208dde4..af0f5c4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9374,9 +9374,7 @@ setup_pipes:
list_for_each_entry(encoder, &dev->mode_config.encoder_list,
base.head) {
- pipe = -1;
-
- if (encoder->get_hw_state(encoder, &pipe) && pipe != -1) {
+ if (encoder->get_hw_state(encoder, &pipe)) {
crtc =
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
if (crtc->mode_valid && encoder->get_mode_flags)
crtc->base.mode.flags |=
encoder->get_mode_flags(encoder);
--
1.7.9.5
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[Intel-gfx] [PATCH 11/13] drm/i915: fix DDI get_hw_state return value
If we couldn't find a pipe we shouldn't return true. This might be even
better as a WARN though, since it should be impossible to have the port
enabled without a pipe selected.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_ddi.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 258e38e..3c77077 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1153,7 +1153,7 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port);
- return true;
+ return false;
}
static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
--
1.7.9.5
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Re: [Intel-gfx] [PATCH i-g-t 3/5] tests: Use IGT_SIMULATION to tune the list of tests to run
On Mon, Apr 01, 2013 at 07:21:59AM +, Sun, Yi wrote: > > On Tue, Mar 26, 2013 at 10:00:23AM -0700, Ben Widawsky wrote: > > > On Tue, Mar 26, 2013 at 04:38:58PM +0100, Daniel Vetter wrote: > > > > On Tue, Mar 26, 2013 at 03:24:37PM +, Damien Lespiau wrote: > > > > > There are two ways to run tests, directly with make check/test or > > > > > through piglit. > > > > > > > > > > When IGT_SIMULATION is set to '1', we substitute the list of tests > > > > > in those two code paths with carefully selected tests. The stress > > > > > tests and other horrors are left to torture the real hardware as > > > > > they don't make too much sense in simulation. > > > > > > > > > > Signed-off-by: Damien Lespiau > > > > > > > > This feels a bit fragile since even just now I often fail to put a > > > > test newly converted to the subtest stuff into the right > > > > single/multi make target list. Also, this way we exclude a test by > > > > default, which also feels like the wrong way round (most of the > > > > tests we're adding aren't heavy stress-tests, but more excercise some > > corner-case). > > > > > > > > So what about a sprinkling > > > > > > > > drmtest_skip_on_simulation(); > > > > > > > > over the remaining testcases instead, which just calls exit(77);? > > > > Only caveat is that for subtests we need to put it into the right > > > > spot to not break subtest enumeration in piglit (it's a bit fragile). > > > > > > > > Cheers, Daniel > > > > > > I prefer Damien's explicit definitions in a file. It makes it much > > > easier to see exactly what's run, and add a test as needed. Since > > > simulation testing will always be a massive subset of the whole i-g-t > > > suite, and we'll probably only rarely add or remove a test, I think > > > it's not a big concern that we might miss a test. > > > > Imo that's the wrong approach, since most of the tests we've recently added > > exercise corner-cases of our code, and in a rather deterministic way. If we > > currently have too many tests to get through all of the useful ones in a > > day, we > > need more machines, not fewer tests. > > > > In the end we want to be able to run full piglit on all this stuff in > > simulation after > > all. Cc'ing Yi so he knows where I'm aiming at ;-) -Daniel > > > [Sun, Yi] So what's the conclusion, how can I do to solve the too long time > issue? > I noticed Damien's patches aren't on the branch yet. > If we want to split all i-g-t test cases to different HAS, how can we split > it? > Daniel, can you please advise Sun Yi since the solution I like has been shot down? -- Ben Widawsky, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/13] drm/i915: treat no fb -> fb as simple flip instead of full mode set
In case we don't get an fb from the BIOS, we may still be able to re-use
existing state and flip a new buffer.
Jesse: Do we want a macro for "no mode set" or just a new check for
crtc->active here?
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c |4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 0f3c036..f24da1a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8109,10 +8109,8 @@ intel_set_config_compute_mode_changes(struct
drm_mode_set *set,
/* We should be able to check here if the fb has the same properties
* and then just flip_or_move it */
if (set->crtc->fb != set->fb) {
- /* If we have no fb then treat it as a full mode set */
if (set->crtc->fb == NULL) {
- DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
- config->mode_changed = true;
+ config->fb_changed = true;
} else if (set->fb == NULL) {
config->mode_changed = true;
} else if (set->fb->depth != set->crtc->fb->depth) {
--
1.7.9.5
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[Intel-gfx] [PATCH 09/13] drm/i915: add debug messages for mode_valid checks
Lets us see what's going on if we slowboot instead of fastboot.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index f24da1a..8b55427 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9298,12 +9298,19 @@ setup_pipes:
crtc->active ? "enabled" : "disabled");
- if (crtc->base.enabled)
+ if (crtc->base.enabled) {
crtc->mode_valid = intel_crtc_get_mode(&crtc->base,
&crtc->base.mode);
+ DRM_DEBUG_KMS("[CRTC:%d]: mode valid? %s\n",
+ crtc->base.base.id,
+ crtc->mode_valid ? "yes" : "no");
+ }
if (crtc->base.fb &&
- !mode_fits_in_fb(&crtc->base.mode, crtc->base.fb))
+ !mode_fits_in_fb(&crtc->base.mode, crtc->base.fb)) {
crtc->mode_valid = false;
+ DRM_DEBUG_KMS("[CRTC:%d] mode doesn't fit in fb\n",
+ crtc->base.base.id);
+ }
if (crtc->mode_valid) {
DRM_DEBUG_KMS("found active mode: ");
--
1.7.9.5
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[Intel-gfx] [PATCH 07/13] drm/i915: check panel fit status at update_plane time v2
We may need to disable the panel when flipping to a new buffer, so check
the state here and zero it out if needed, otherwise leave it alone.
v2: fixup pipe_set_base check (Imre)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3741fe8..0f3c036 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2363,6 +2363,18 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
return ret;
}
+ /* Update pipe size and adjust fitter if needed */
+ I915_WRITE(PIPESRC(intel_crtc->pipe),
+ ((crtc->mode.hdisplay - 1) << 16) |
+ (crtc->mode.vdisplay - 1));
+ if (!dev_priv->pch_pf_size &&
+ (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
+intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
+ I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
+ I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
+ I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
+ }
+
ret = dev_priv->display.update_plane(crtc, fb, x, y);
if (ret) {
intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/13] drm/i915: Wrap the preallocated BIOS framebuffer and preserve for KMS fbcon v3
v2: check for non-native modes and adjust (Jesse)
fixup aperture and cmap frees (Imre)
use unlocked unref if init_bios fails (Jesse)
fix curly brace around DSPADDR check (Imre)
comment failure path for pin_and_fence (Imre)
v3: fixup fixup of aperture frees (Chris)
Signed-off-by: Chris Wilson
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_dma.c |8 +-
drivers/gpu/drm/i915/i915_drv.h |2 +-
drivers/gpu/drm/i915/intel_display.c | 14 +-
drivers/gpu/drm/i915/intel_drv.h |4 +
drivers/gpu/drm/i915/intel_fb.c | 295 --
5 files changed, 304 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index ebcfe2e..1389247 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1273,6 +1273,7 @@ static const struct vga_switcheroo_client_ops
i915_switcheroo_ops = {
static int i915_load_modeset_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ bool was_vga_enabled;
int ret;
ret = intel_parse_bios(dev);
@@ -1309,7 +1310,11 @@ static int i915_load_modeset_init(struct drm_device *dev)
/* Important: The output setup functions called by modeset_init need
* working irqs for e.g. gmbus and dp aux transfers. */
- intel_modeset_init(dev);
+ intel_modeset_init(dev, &was_vga_enabled);
+
+ /* Wrap existing BIOS mode configuration prior to GEM takeover */
+ if (!was_vga_enabled)
+ intel_fbdev_init_bios(dev);
ret = i915_gem_init(dev);
if (ret)
@@ -1323,6 +1328,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
/* FIXME: do pre/post-mode set stuff in core KMS code */
dev->vblank_disable_allowed = 1;
+ /* Install a default KMS/GEM fbcon if we failed to wrap the BIOS fb */
ret = intel_fbdev_init(dev);
if (ret)
goto cleanup_gem;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7f6452b..d32ed27 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1806,7 +1806,7 @@ static inline void intel_unregister_dsm_handler(void) {
return; }
/* modesetting */
extern void intel_modeset_init_hw(struct drm_device *dev);
-extern void intel_modeset_init(struct drm_device *dev);
+extern void intel_modeset_init(struct drm_device *dev, bool *was_vga_enabled);
extern void intel_modeset_gem_init(struct drm_device *dev);
extern void intel_modeset_cleanup(struct drm_device *dev);
extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index dfc8152..a55ef8f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8854,12 +8854,17 @@ static void intel_init_quirks(struct drm_device *dev)
}
/* Disable the VGA plane that we never use */
-static void i915_disable_vga(struct drm_device *dev)
+static bool i915_disable_vga(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ bool was_enabled;
u8 sr1;
u32 vga_reg = i915_vgacntrl_reg(dev);
+ was_enabled = !(I915_READ(vga_reg) & VGA_DISP_DISABLE);
+ DRM_DEBUG_KMS("VGA output is currently %s\n",
+ was_enabled ? "enabled" : "disabled");
+
vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
outb(SR01, VGA_SR_INDEX);
sr1 = inb(VGA_SR_DATA);
@@ -8869,6 +8874,8 @@ static void i915_disable_vga(struct drm_device *dev)
I915_WRITE(vga_reg, VGA_DISP_DISABLE);
POSTING_READ(vga_reg);
+
+ return was_enabled;
}
void intel_modeset_init_hw(struct drm_device *dev)
@@ -8884,7 +8891,8 @@ void intel_modeset_init_hw(struct drm_device *dev)
mutex_unlock(&dev->struct_mutex);
}
-void intel_modeset_init(struct drm_device *dev)
+void intel_modeset_init(struct drm_device *dev,
+ bool *was_vga_enabled)
{
struct drm_i915_private *dev_priv = dev->dev_private;
int i, ret;
@@ -8932,7 +8940,7 @@ void intel_modeset_init(struct drm_device *dev)
intel_pch_pll_init(dev);
/* Just disable it once at startup */
- i915_disable_vga(dev);
+ *was_vga_enabled = i915_disable_vga(dev);
intel_setup_outputs(dev);
/* Just in case the BIOS is doing something questionable. */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f593e26..52e4924 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -146,6 +146,8 @@ struct intel_fbdev {
struct intel_framebuffer ifb;
struct list_head fbdev_list;
struct drm_display_mode *our_mode;
+ bool stolen;
+ int preferred_bpp;
};
struct intel_encoder {
@@ -212,6 +214,7 @@ s
[Intel-gfx] [PATCH 06/13] drm/i915: Validate that the framebuffer accommodates the current mode
From: Chris Wilson
As we retrieve the mode from the BIOS it may be constructed using
different assumptions for its configuration, such as utilizing the panel
fitter in a conflicting manner. As such the associated framebuffer may be
insufficient for our setup, and so we need to reject the current mode
and install our own.
Jesse: This should probably be put into a new state readout function separate
from the fb code
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_display.c | 38 +-
1 file changed, 28 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d1dd1ec..3741fe8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6580,27 +6580,40 @@ intel_framebuffer_create_for_mode(struct drm_device
*dev,
return intel_framebuffer_create(dev, &mode_cmd, obj);
}
+static bool
+mode_fits_in_fb(struct drm_display_mode *mode,
+ struct drm_framebuffer *fb)
+{
+ struct drm_i915_gem_object *obj;
+ int min_pitch;
+
+ min_pitch = intel_framebuffer_pitch_for_width(mode->hdisplay,
+ fb->bits_per_pixel);
+ if (fb->pitches[0] < min_pitch)
+ return false;
+
+ obj = to_intel_framebuffer(fb)->obj;
+ if (obj == NULL)
+ return false;
+
+ if (obj->base.size < mode->vdisplay * fb->pitches[0])
+ return false;
+
+ return true;
+}
+
static struct drm_framebuffer *
mode_fits_in_fbdev(struct drm_device *dev,
struct drm_display_mode *mode)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- struct drm_i915_gem_object *obj;
struct drm_framebuffer *fb;
if (dev_priv->fbdev == NULL)
return NULL;
- obj = dev_priv->fbdev->ifb.obj;
- if (obj == NULL)
- return NULL;
-
fb = &dev_priv->fbdev->ifb.base;
- if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
-
fb->bits_per_pixel))
- return NULL;
-
- if (obj->base.size < mode->vdisplay * fb->pitches[0])
+ if (!mode_fits_in_fb(mode, fb))
return NULL;
return fb;
@@ -9277,6 +9290,11 @@ setup_pipes:
if (crtc->base.enabled)
crtc->mode_valid = intel_crtc_get_mode(&crtc->base,
&crtc->base.mode);
+
+ if (crtc->base.fb &&
+ !mode_fits_in_fb(&crtc->base.mode, crtc->base.fb))
+ crtc->mode_valid = false;
+
if (crtc->mode_valid) {
DRM_DEBUG_KMS("found active mode: ");
drm_mode_debug_printmodeline(&crtc->base.mode);
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/13] drm/i915: Retrieve the current mode upon KMS takeover v2
Read the current hardware state to retrieve the active mode and populate
our CRTC config if that mode matches our presumptions.
v2: check that get_hw_state gave us a valid pipe (Imre)
add clock_get for ILK+ (Jesse)
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h |2 +
drivers/gpu/drm/i915/intel_crt.c | 27 ++-
drivers/gpu/drm/i915/intel_display.c | 139 +++---
drivers/gpu/drm/i915/intel_dp.c | 22 ++
drivers/gpu/drm/i915/intel_drv.h |7 +-
drivers/gpu/drm/i915/intel_dvo.c | 36 ++---
drivers/gpu/drm/i915/intel_hdmi.c| 22 ++
drivers/gpu/drm/i915/intel_lvds.c| 27 ++-
drivers/gpu/drm/i915/intel_sdvo.c| 23 ++
9 files changed, 262 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d32ed27..905ce86 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -283,6 +283,8 @@ struct drm_i915_display_funcs {
void (*update_linetime_wm)(struct drm_device *dev, int pipe,
struct drm_display_mode *mode);
void (*modeset_global_resources)(struct drm_device *dev);
+ bool (*crtc_get_mode)(struct drm_crtc *crtc,
+struct drm_display_mode *mode);
int (*crtc_mode_set)(struct drm_crtc *crtc,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode,
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 32a3693..da0ae7e 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -81,6 +81,27 @@ static bool intel_crt_get_hw_state(struct intel_encoder
*encoder,
return true;
}
+static unsigned intel_crt_get_mode_flags(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+ struct intel_crt *crt = intel_encoder_to_crt(encoder);
+ u32 tmp, flags = 0;
+
+ tmp = I915_READ(crt->adpa_reg);
+
+ if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
+ flags |= DRM_MODE_FLAG_PHSYNC;
+ else
+ flags |= DRM_MODE_FLAG_NHSYNC;
+
+ if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
+ flags |= DRM_MODE_FLAG_PVSYNC;
+ else
+ flags |= DRM_MODE_FLAG_NVSYNC;
+
+ return flags;
+}
+
static void intel_disable_crt(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
@@ -776,10 +797,12 @@ void intel_crt_init(struct drm_device *dev)
crt->base.disable = intel_disable_crt;
crt->base.enable = intel_enable_crt;
- if (HAS_DDI(dev))
+ if (HAS_DDI(dev)) {
crt->base.get_hw_state = intel_ddi_get_hw_state;
- else
+ } else {
crt->base.get_hw_state = intel_crt_get_hw_state;
+ crt->base.get_mode_flags = intel_crt_get_mode_flags;
+ }
intel_connector->get_hw_state = intel_connector_get_hw_state;
drm_encoder_helper_add(&crt->base.base, &crt_encoder_funcs);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a55ef8f..35a1984 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6748,11 +6748,12 @@ void intel_release_load_detect_pipe(struct
drm_connector *connector,
}
/* Returns the clock of the currently programmed mode of the given pipe. */
-static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
+static int i9xx_crtc_clock_get(struct drm_crtc *crtc)
{
+ struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- int pipe = intel_crtc->pipe;
+ enum pipe pipe = intel_crtc->pipe;
u32 dpll = I915_READ(DPLL(pipe));
u32 fp;
intel_clock_t clock;
@@ -6835,35 +6836,104 @@ static int intel_crtc_clock_get(struct drm_device
*dev, struct drm_crtc *crtc)
}
/** Returns the currently programmed mode of the given pipe. */
-struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
-struct drm_crtc *crtc)
+static bool i9xx_crtc_get_mode(struct drm_crtc *crtc,
+ struct drm_display_mode *mode)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = crtc->dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
- struct drm_display_mode *mode;
- int htot = I915_READ(HTOTAL(cpu_transcoder));
- int hsync = I915_READ(HSYNC(cpu_transcoder));
- int vtot = I915_READ(VTOTAL(cpu_transcoder));
- int vsync = I915_READ(VSYNC(cpu_transcoder));
+ u32 t
[Intel-gfx] [PATCH 05/13] drm/i915: Only preserve the BIOS modes if they are the preferred ones
From: Chris Wilson
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_display.c |9 +
drivers/gpu/drm/i915/intel_dp.c |1 +
drivers/gpu/drm/i915/intel_drv.h |8
drivers/gpu/drm/i915/intel_fb.c |9 +
drivers/gpu/drm/i915/intel_lvds.c|1 +
drivers/gpu/drm/i915/intel_panel.c | 10 ++
6 files changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 35a1984..d1dd1ec 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9424,6 +9424,15 @@ void intel_connector_attach_encoder(struct
intel_connector *connector,
&encoder->base);
}
+bool intel_connector_get_preferred_mode(struct intel_connector *connector,
+ struct drm_display_mode *mode)
+{
+ if (!connector->get_preferred_mode)
+ return false;
+
+ return connector->get_preferred_mode(connector, mode);
+}
+
/*
* set vga decode state - true == enable VGA decode
*/
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1262f25..e1b0c94 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2926,6 +2926,7 @@ intel_dp_init_connector(struct intel_digital_port
*intel_dig_port,
}
if (is_edp(intel_dp)) {
+ intel_connector->get_preferred_mode =
intel_connector_get_panel_fixed_mode;
intel_panel_init(&intel_connector->panel, fixed_mode);
intel_panel_setup_backlight(connector);
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3036576..37f4bb3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -204,6 +204,9 @@ struct intel_connector {
* and active (i.e. dpms ON state). */
bool (*get_hw_state)(struct intel_connector *);
+ bool (*get_preferred_mode)(struct intel_connector *,
+ struct drm_display_mode *);
+
/* Panel info for eDP and LVDS */
struct intel_panel panel;
@@ -514,6 +517,9 @@ extern int intel_panel_init(struct intel_panel *panel,
struct drm_display_mode *fixed_mode);
extern void intel_panel_fini(struct intel_panel *panel);
+extern bool intel_connector_get_panel_fixed_mode(struct intel_connector
*connector,
+struct drm_display_mode *mode);
+
extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode);
extern void intel_pch_panel_fitting(struct drm_device *dev,
@@ -585,6 +591,8 @@ hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
struct intel_digital_port *port);
+extern bool intel_connector_get_preferred_mode(struct intel_connector
*connector,
+ struct drm_display_mode *mode);
extern void intel_connector_attach_encoder(struct intel_connector *connector,
struct intel_encoder *encoder);
extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index 651077c..f381073 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -216,6 +216,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper
*fb_helper,
for (i = 0; i < fb_helper->connector_count; i++) {
struct drm_connector *connector;
struct drm_encoder *encoder;
+ struct drm_display_mode mode;
connector = fb_helper->connector_info[i]->connector;
if (!enabled[i]) {
@@ -245,6 +246,14 @@ static bool intel_fb_initial_config(struct drm_fb_helper
*fb_helper,
return false;
}
+ if
(intel_connector_get_preferred_mode(to_intel_connector(connector), &mode) &&
+ !drm_mode_equal(&mode, &encoder->crtc->mode)) {
+ DRM_DEBUG_KMS("connector %s on crtc %d has an
non-native mode, aborting\n",
+ drm_get_connector_name(connector),
+ encoder->crtc->base.id);
+ return false;
+ }
+
modes[i] = &encoder->crtc->mode;
crtcs[i] = intel_fb_helper_crtc(fb_helper, encoder->crtc);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c
b/drivers/gpu/drm/i915/intel_lvds.c
index 2530927..e29bc72 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -1129,6 +1129,7 @@ bool intel_lvds_init(struct drm_device *dev)
intel_encoder->g
[Intel-gfx] [PATCH 02/13] drm/i915: Split the framebuffer_info creation into a separate routine
This will be shared with wrapping the BIOS framebuffer into the fbdev
later. In the meantime, we can tidy the code slightly and improve the
error path handling.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_display.c |7 --
drivers/gpu/drm/i915/intel_drv.h |7 ++
drivers/gpu/drm/i915/intel_fb.c | 154 ++
3 files changed, 91 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 9d05b30..dfc8152 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6552,13 +6552,6 @@ intel_framebuffer_create(struct drm_device *dev,
}
static u32
-intel_framebuffer_pitch_for_width(int width, int bpp)
-{
- u32 pitch = DIV_ROUND_UP(width * bpp, 8);
- return ALIGN(pitch, 64);
-}
-
-static u32
intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
{
u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 276f665..f593e26 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -134,6 +134,13 @@ struct intel_framebuffer {
struct drm_i915_gem_object *obj;
};
+inline static u32
+intel_framebuffer_pitch_for_width(int width, int bpp)
+{
+ u32 pitch = DIV_ROUND_UP(width * bpp, 8);
+ return ALIGN(pitch, 64);
+}
+
struct intel_fbdev {
struct drm_fb_helper helper;
struct intel_framebuffer ifb;
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index 8d81c929..8736a77 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -57,30 +57,97 @@ static struct fb_ops intelfb_ops = {
.fb_debug_leave = drm_fb_helper_debug_leave,
};
+static struct fb_info *intelfb_create_info(struct intel_fbdev *ifbdev)
+{
+ struct drm_framebuffer *fb = &ifbdev->ifb.base;
+ struct drm_device *dev = fb->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct fb_info *info;
+ u32 gtt_offset, size;
+ int ret;
+
+ info = framebuffer_alloc(0, &dev->pdev->dev);
+ if (!info)
+ return NULL;
+
+ info->par = ifbdev;
+ ifbdev->helper.fb = fb;
+ ifbdev->helper.fbdev = info;
+
+ strcpy(info->fix.id, "inteldrmfb");
+
+ info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT;
+ info->fbops = &intelfb_ops;
+
+ ret = fb_alloc_cmap(&info->cmap, 256, 0);
+ if (ret)
+ goto err_info;
+
+ /* setup aperture base/size for vesafb takeover */
+ info->apertures = alloc_apertures(1);
+ if (!info->apertures)
+ goto err_cmap;
+
+ info->apertures->ranges[0].base = dev->mode_config.fb_base;
+ info->apertures->ranges[0].size = dev_priv->gtt.mappable_end;
+
+ gtt_offset = ifbdev->ifb.obj->gtt_offset;
+ size = ifbdev->ifb.obj->base.size;
+
+ info->fix.smem_start = dev->mode_config.fb_base + gtt_offset;
+ info->fix.smem_len = size;
+
+ info->screen_size = size;
+ info->screen_base = ioremap_wc(dev_priv->gtt.mappable_base + gtt_offset,
+ size);
+ if (!info->screen_base)
+ goto err_cmap;
+
+ /* If the object is shmemfs backed, it will have given us zeroed pages.
+* If the object is stolen however, it will be full of whatever
+* garbage was left in there.
+*/
+ if (ifbdev->ifb.obj->stolen)
+ memset_io(info->screen_base, 0, info->screen_size);
+
+ /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
+
+ drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth);
+ drm_fb_helper_fill_var(info, &ifbdev->helper, fb->width, fb->height);
+
+ return info;
+
+err_cmap:
+ if (info->cmap.len)
+ fb_dealloc_cmap(&info->cmap);
+err_info:
+ framebuffer_release(info);
+ return NULL;
+}
+
static int intelfb_create(struct drm_fb_helper *helper,
struct drm_fb_helper_surface_size *sizes)
{
struct intel_fbdev *ifbdev = (struct intel_fbdev *)helper;
struct drm_device *dev = ifbdev->helper.dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct fb_info *info;
- struct drm_framebuffer *fb;
- struct drm_mode_fb_cmd2 mode_cmd = {};
+ struct drm_mode_fb_cmd2 mode_cmd = { 0 };
struct drm_i915_gem_object *obj;
- struct device *device = &dev->pdev->dev;
+ struct fb_info *info;
int size, ret;
/* we don't do packed 24bpp */
if (sizes->surface_bpp == 24)
sizes->surface_bpp = 32;
- mode_cmd.width = sizes->surface_width;
+ mode_cmd.width = sizes->surface_width;
mode_cmd.height = sizes->surface_height;
- mode_cmd.pit
[Intel-gfx] [PATCH 01/13] drm/i915: Skip modifying PCH DREF if not changing clock sources
From: Chris Wilson
Modifying the clock sources (via the DREF control on the PCH) is a slow
multi-stage process as we need to let the clocks stabilise between each
stage. If we are not actually changing the clock sources, then we can
return early.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_display.c | 83 +-
1 file changed, 61 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8f0db8c..9d05b30 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4833,7 +4833,7 @@ static void ironlake_init_pch_refclk(struct drm_device
*dev)
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_mode_config *mode_config = &dev->mode_config;
struct intel_encoder *encoder;
- u32 temp;
+ u32 val, final;
bool has_lvds = false;
bool has_cpu_edp = false;
bool has_pch_edp = false;
@@ -4876,70 +4876,109 @@ static void ironlake_init_pch_refclk(struct drm_device
*dev)
* PCH B stepping, previous chipset stepping should be
* ignoring this setting.
*/
- temp = I915_READ(PCH_DREF_CONTROL);
+ val = I915_READ(PCH_DREF_CONTROL);
+
+ /* As we must carefully and slowly disable/enable each source in turn,
+* compute the final state we want first and check if we need to
+* make any changes at all.
+*/
+ final = val;
+ final &= ~DREF_NONSPREAD_SOURCE_MASK;
+ if (has_ck505)
+ final |= DREF_NONSPREAD_CK505_ENABLE;
+ else
+ final |= DREF_NONSPREAD_SOURCE_ENABLE;
+
+ final &= ~DREF_SSC_SOURCE_MASK;
+ final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
+ final &= ~DREF_SSC1_ENABLE;
+
+ if (has_panel) {
+ final |= DREF_SSC_SOURCE_ENABLE;
+
+ if (intel_panel_use_ssc(dev_priv) && can_ssc)
+ final |= DREF_SSC1_ENABLE;
+
+ if (has_cpu_edp) {
+ if (intel_panel_use_ssc(dev_priv) && can_ssc)
+ final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
+ else
+ final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
+ } else
+ final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
+ } else {
+ final |= DREF_SSC_SOURCE_DISABLE;
+ final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
+ }
+
+ if (final == val)
+ return;
+
/* Always enable nonspread source */
- temp &= ~DREF_NONSPREAD_SOURCE_MASK;
+ val &= ~DREF_NONSPREAD_SOURCE_MASK;
if (has_ck505)
- temp |= DREF_NONSPREAD_CK505_ENABLE;
+ val |= DREF_NONSPREAD_CK505_ENABLE;
else
- temp |= DREF_NONSPREAD_SOURCE_ENABLE;
+ val |= DREF_NONSPREAD_SOURCE_ENABLE;
if (has_panel) {
- temp &= ~DREF_SSC_SOURCE_MASK;
- temp |= DREF_SSC_SOURCE_ENABLE;
+ val &= ~DREF_SSC_SOURCE_MASK;
+ val |= DREF_SSC_SOURCE_ENABLE;
/* SSC must be turned on before enabling the CPU output */
if (intel_panel_use_ssc(dev_priv) && can_ssc) {
DRM_DEBUG_KMS("Using SSC on panel\n");
- temp |= DREF_SSC1_ENABLE;
+ val |= DREF_SSC1_ENABLE;
} else
- temp &= ~DREF_SSC1_ENABLE;
+ val &= ~DREF_SSC1_ENABLE;
/* Get SSC going before enabling the outputs */
- I915_WRITE(PCH_DREF_CONTROL, temp);
+ I915_WRITE(PCH_DREF_CONTROL, val);
POSTING_READ(PCH_DREF_CONTROL);
udelay(200);
- temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
+ val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
/* Enable CPU source on CPU attached eDP */
if (has_cpu_edp) {
if (intel_panel_use_ssc(dev_priv) && can_ssc) {
DRM_DEBUG_KMS("Using SSC on eDP\n");
- temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
+ val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
}
else
- temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
+ val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
} else
- temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
+ val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
- I915_WRITE(PCH_DREF_CONTROL, temp);
+ I915_WRITE(PCH_DREF_CONTROL, val);
POSTING_READ(PCH_DREF_CONTROL);
udelay(200);
} else {
DRM_DEBUG_KMS("Disabling SSC entirely\n");
- temp &= ~DREF_
[Intel-gfx] Updated fastboot bits
Still need to mash these into the pipe_config bits, but with the PCH PLL readout, at least they don't crash after DPMS anymore. So that patch may be ok to apply as-is; I think the main bits needing rework involve the mode readout checks in intel_fb.c. They belong in intel_display.c as part of the state readout into an adjusted_mode struct. Jesse ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Fix sdvo connector get_hw_state function
On Tue, Apr 02, 2013 at 06:39:37PM +0200, Daniel Vetter wrote: > The active output is only the currently selected one, which does not > imply that it's actually enabled. Since we don't use the sdvo encoder > side dpms support, we need to check whether the chip-side sdvo port is > enabled instead. > > v2: Fix up Bugzilla links. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60138 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63031 > Cc: Egbert Eich Signed-off-by: Daniel Vetter > --- > drivers/gpu/drm/i915/intel_sdvo.c |6 +- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_sdvo.c > b/drivers/gpu/drm/i915/intel_sdvo.c > index 33b46d9..0e55bee 100644 > --- a/drivers/gpu/drm/i915/intel_sdvo.c > +++ b/drivers/gpu/drm/i915/intel_sdvo.c > @@ -1219,11 +1219,15 @@ static bool intel_sdvo_connector_get_hw_state(struct > intel_connector *connector) > struct intel_sdvo_connector *intel_sdvo_connector = > to_intel_sdvo_connector(&connector->base); > struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); > + struct drm_i915_private *dev_priv = > intel_sdvo->base.base.dev->dev_private; > u16 active_outputs; > + u32 tmp; > > + tmp = I915_READ(intel_sdvo->sdvo_reg); > intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); > > - if (active_outputs & intel_sdvo_connector->output_flag) > + if ((active_outputs & intel_sdvo_connector->output_flag) && > + (tmp & SDVO_ENABLE)) > return true; > else > return false; Would this function be tidier as: /* Check if this SDVO pipe is on and connected to our output */ if (I915_READ(intel_sdvo->sdvo_reg) & SDVO_ENABLE) return false; intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); return (active_outputs & intel_sdvo_connector->output_flag) != 0; At the very least the patch by shrunk by adjusting it to only add the earlier check. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Fix sdvo connector get_hw_state function
The active output is only the currently selected one, which does not imply that it's actually enabled. Since we don't use the sdvo encoder side dpms support, we need to check whether the chip-side sdvo port is enabled instead. v2: Fix up Bugzilla links. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60138 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63031 Cc: Egbert Eich --- drivers/gpu/drm/i915/intel_sdvo.c |6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 33b46d9..0e55bee 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -1219,11 +1219,15 @@ static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(&connector->base); struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); + struct drm_i915_private *dev_priv = intel_sdvo->base.base.dev->dev_private; u16 active_outputs; + u32 tmp; + tmp = I915_READ(intel_sdvo->sdvo_reg); intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); - if (active_outputs & intel_sdvo_connector->output_flag) + if ((active_outputs & intel_sdvo_connector->output_flag) && + (tmp & SDVO_ENABLE)) return true; else return false; -- 1.7.10.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Fix sdvo connector get_hw_state function
The active output is only the currently selected one, which does not imply that it's actually enabled. Since we don't use the sdvo encoder side dpms support, we need to check whether the chip-side sdvo port is enabled instead. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60138 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62944 Cc: Egbert Eich --- drivers/gpu/drm/i915/intel_sdvo.c |6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 33b46d9..0e55bee 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -1219,11 +1219,15 @@ static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(&connector->base); struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); + struct drm_i915_private *dev_priv = intel_sdvo->base.base.dev->dev_private; u16 active_outputs; + u32 tmp; + tmp = I915_READ(intel_sdvo->sdvo_reg); intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); - if (active_outputs & intel_sdvo_connector->output_flag) + if ((active_outputs & intel_sdvo_connector->output_flag) && + (tmp & SDVO_ENABLE)) return true; else return false; -- 1.7.10.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Add i915.dp_limit_max_lane_count driver option.
On Tuesday 26 of March 2013 16:49:30 Daniel Vetter wrote: > On Tue, Mar 26, 2013 at 4:40 PM, Michal Srb wrote: > > I have IBM POS machine (4852-570 Truman) that has internal monitor > > connected over display port. It reports to have 2 lanes, but only 1 > > lane works reliably. With 2 lanes used, the monitor sometimes doesn't > > turn on. It seems that this is hardware issue specific for this model. > > > > From discussion that was around the > > 2514bc510d0c3aadcc5204056bb440fa36845147 commit I understand there are > > more machines that have similar problems. This option can be used to > > solve them. > > It sounds like we need to start with a DPCD quirk database ... Ajax? > -Daniel Any update? DPCD of this monitor is 10 0a 82 40 00 00 01 00 02 00 00 00 10 01 00 by the way. Is the i915.dp_limit_max_lane_count unacceptable even as temporary workaround? Michal Srb ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/5] drm/i915: group backlight related stuff into a struct
On Tue, Apr 02, 2013 at 03:48:09PM +0300, Jani Nikula wrote:
> No functional changes.
>
> Signed-off-by: Jani Nikula
Queued for -next, thanks for the patch.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_drv.h| 11 +
> drivers/gpu/drm/i915/intel_panel.c | 44
> ++--
> 2 files changed, 29 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2962a9a..5e38a2c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -939,9 +939,14 @@ typedef struct drm_i915_private {
> struct intel_overlay *overlay;
> unsigned int sprite_scaling_enabled;
>
> + /* backlight */
> + struct {
> + int level;
> + bool enabled;
> + struct backlight_device *device;
> + } backlight;
> +
> /* LVDS info */
> - int backlight_level; /* restore backlight to this value */
> - bool backlight_enabled;
> struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
> struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
>
> @@ -1043,8 +1048,6 @@ typedef struct drm_i915_private {
>*/
> struct work_struct console_resume_work;
>
> - struct backlight_device *backlight;
> -
> struct drm_property *broadcast_rgb_property;
> struct drm_property *force_audio_property;
>
> diff --git a/drivers/gpu/drm/i915/intel_panel.c
> b/drivers/gpu/drm/i915/intel_panel.c
> index 21f415a..0e7e873 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -286,11 +286,11 @@ void intel_panel_set_backlight(struct drm_device *dev,
> u32 level)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> - dev_priv->backlight_level = level;
> - if (dev_priv->backlight)
> - dev_priv->backlight->props.brightness = level;
> + dev_priv->backlight.level = level;
> + if (dev_priv->backlight.device)
> + dev_priv->backlight.device->props.brightness = level;
>
> - if (dev_priv->backlight_enabled)
> + if (dev_priv->backlight.enabled)
> intel_panel_actually_set_backlight(dev, level);
> }
>
> @@ -298,7 +298,7 @@ void intel_panel_disable_backlight(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> - dev_priv->backlight_enabled = false;
> + dev_priv->backlight.enabled = false;
> intel_panel_actually_set_backlight(dev, 0);
>
> if (INTEL_INFO(dev)->gen >= 4) {
> @@ -321,15 +321,15 @@ void intel_panel_enable_backlight(struct drm_device
> *dev,
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> - if (dev_priv->backlight_level == 0) {
> - dev_priv->backlight_level = intel_panel_get_max_backlight(dev);
> - if (dev_priv->backlight)
> - dev_priv->backlight->props.brightness =
> - dev_priv->backlight_level;
> + if (dev_priv->backlight.level == 0) {
> + dev_priv->backlight.level = intel_panel_get_max_backlight(dev);
> + if (dev_priv->backlight.device)
> + dev_priv->backlight.device->props.brightness =
> + dev_priv->backlight.level;
> }
>
> - dev_priv->backlight_enabled = true;
> - intel_panel_actually_set_backlight(dev, dev_priv->backlight_level);
> + dev_priv->backlight.enabled = true;
> + intel_panel_actually_set_backlight(dev, dev_priv->backlight.level);
>
> if (INTEL_INFO(dev)->gen >= 4) {
> uint32_t reg, tmp;
> @@ -371,15 +371,15 @@ set_level:
>* when BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1 are written.
>*/
> if (!intel_panel_get_backlight(dev))
> - intel_panel_actually_set_backlight(dev,
> dev_priv->backlight_level);
> + intel_panel_actually_set_backlight(dev,
> dev_priv->backlight.level);
> }
>
> static void intel_panel_init_backlight(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> - dev_priv->backlight_level = intel_panel_get_backlight(dev);
> - dev_priv->backlight_enabled = dev_priv->backlight_level != 0;
> + dev_priv->backlight.level = intel_panel_get_backlight(dev);
> + dev_priv->backlight.enabled = dev_priv->backlight.level != 0;
> }
>
> enum drm_connector_status
> @@ -433,21 +433,21 @@ int intel_panel_setup_backlight(struct drm_connector
> *connector)
>
> memset(&props, 0, sizeof(props));
> props.type = BACKLIGHT_RAW;
> - props.brightness = dev_priv->backlight_level;
> + props.brightness = dev_priv->backlight.level;
> props.max_brightness = _intel_panel_get_max_backlight(dev);
> if (props.max_brightness == 0) {
> DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n");
> return -ENODEV;
> }
> - dev_priv->backlight =
> +
Re: [Intel-gfx] [PATCH] drm/i915: drop the coditional mutex
On Tue, Apr 02, 2013 at 03:30:58PM +0200, Sebastian Andrzej Siewior wrote:
> mutex_is_locked_by() checks the owner of the lock against current. This
> is done by accessing a private member of struct mutex which works on
> mainline but does not on RT.
> I did not figure out, why this "lock-owner-check" and the "lock stealing
> flag" is required. If the lock can not be acquire the lock (because it
> would deadlock) then it can return -1.
> The lock stealing makes actually no sense to me. If
> shrinker_no_lock_stealing is true then the same functions
> (i915_gem_purge(), i915_gem_shrink_all()) are called from
> i915_gem_object_create_mmap_offset() as from i915_gem_inactive_shrink().
> I haven't found a path in which i915_gem_inactive_shrink() is invoked
> from i915_gem_object_create_mmap_offset() that means there is no way
> shrinker_no_lock_stealing is true _and_ the lock is owned by the current
> process.
Every invocation of a memory allocation function can potentially recourse
into the shrinker callbacks. Since we currently protect almost all our gpu
buffer object state with one single lock, and we can also easily hold onto
tons of memory, we can easily OOM without that lock stealing trick.
The patch you're reverting here was added to work around spurious OOM when
trying to allocate sg tables, so this is real.
I fully realize that this is an awful hack and I'll burn on a pretty big
pyre for merging it. I also know that it doesn't really work if someone
else is trying to allocate while another thread is hogging our single
mutex. But without a replacement fix, this is nacked.
The no_lock_stealing hack is probably even worse, we use it to protect
critical section which are touching the gpu lru.
Long term we're working towards that goal (also for a bunch of other
reasons) and aim for more fine-grained locking, so that we can free memory
in smaller chunks. But that's gonna be a lot of work.
Cheers, Daniel
> Since I don't see why the i915 needs this hack while all other user do
> not I recommend to remove this hack and return -1 in case of a dead
> lock. Here is the patch.
>
> Signed-off-by: Sebastian Andrzej Siewior
> ---
> drivers/gpu/drm/i915/i915_drv.h |1 -
> drivers/gpu/drm/i915/i915_gem.c | 32 +++-
> 2 files changed, 3 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 01769e2..47f28ee 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -724,7 +724,6 @@ struct i915_gem_mm {
> struct i915_hw_ppgtt *aliasing_ppgtt;
>
> struct shrinker inactive_shrinker;
> - bool shrinker_no_lock_stealing;
>
> /**
>* List of objects currently involved in rendering.
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 0e207e6..7949517 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1500,8 +1500,6 @@ static int i915_gem_object_create_mmap_offset(struct
> drm_i915_gem_object *obj)
> if (obj->base.map_list.map)
> return 0;
>
> - dev_priv->mm.shrinker_no_lock_stealing = true;
> -
> ret = drm_gem_create_mmap_offset(&obj->base);
> if (ret != -ENOSPC)
> goto out;
> @@ -1521,8 +1519,6 @@ static int i915_gem_object_create_mmap_offset(struct
> drm_i915_gem_object *obj)
> i915_gem_shrink_all(dev_priv);
> ret = drm_gem_create_mmap_offset(&obj->base);
> out:
> - dev_priv->mm.shrinker_no_lock_stealing = false;
> -
> return ret;
> }
>
> @@ -4368,19 +4364,6 @@ void i915_gem_release(struct drm_device *dev, struct
> drm_file *file)
> spin_unlock(&file_priv->mm.lock);
> }
>
> -static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
> -{
> - if (!mutex_is_locked(mutex))
> - return false;
> -
> -#if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
> - return mutex->owner == task;
> -#else
> - /* Since UP may be pre-empted, we cannot assume that we own the lock */
> - return false;
> -#endif
> -}
> -
> static int
> i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control
> *sc)
> {
> @@ -4391,18 +4374,10 @@ i915_gem_inactive_shrink(struct shrinker *shrinker,
> struct shrink_control *sc)
> struct drm_device *dev = dev_priv->dev;
> struct drm_i915_gem_object *obj;
> int nr_to_scan = sc->nr_to_scan;
> - bool unlock = true;
> int cnt;
>
> - if (!mutex_trylock(&dev->struct_mutex)) {
> - if (!mutex_is_locked_by(&dev->struct_mutex, current))
> - return 0;
> -
> - if (dev_priv->mm.shrinker_no_lock_stealing)
> - return 0;
> -
> - unlock = false;
> - }
> + if (!mutex_trylock(&dev->struct_mutex))
> + return -1;
>
> if (nr_to_scan) {
> nr_to_scan -= i915_gem_purge(dev_priv, nr_to
Re: [Intel-gfx] [PATCH 2/5] drm/i915: protect backlight enable and level with spinlock
On Tue, Apr 02, 2013 at 03:48:10PM +0300, Jani Nikula wrote:
> Backlight is fiddled both through backlight sysfs files and asle
> interrupts. Protect the relevant data.
It's also used by our modeset code in the lvds/edp enable/disable hooks.
> Signed-off-by: Jani Nikula
Besides the panel code there's also the register save/restore code in
i915_suspend.c. I think that also needs to be protected with this new
spinlock.
That will get a bit ugly though, since that code is also used for ums and
in that case we won't set up the backlight code and so not initialize the
spinlock. Either splatter really ugly if (DRIVER_MODESET) checks or make
two copies of that stuff ...
Cheers, Daniel
> ---
> drivers/gpu/drm/i915/i915_drv.h|1 +
> drivers/gpu/drm/i915/intel_panel.c | 16
> 2 files changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5e38a2c..2e59610 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -943,6 +943,7 @@ typedef struct drm_i915_private {
> struct {
> int level;
> bool enabled;
> + spinlock_t lock;
> struct backlight_device *device;
> } backlight;
>
> diff --git a/drivers/gpu/drm/i915/intel_panel.c
> b/drivers/gpu/drm/i915/intel_panel.c
> index 0e7e873..2a95297 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -285,6 +285,9 @@ static void intel_panel_actually_set_backlight(struct
> drm_device *dev, u32 level
> void intel_panel_set_backlight(struct drm_device *dev, u32 level)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&dev_priv->backlight.lock, flags);
>
> dev_priv->backlight.level = level;
> if (dev_priv->backlight.device)
> @@ -292,11 +295,16 @@ void intel_panel_set_backlight(struct drm_device *dev,
> u32 level)
>
> if (dev_priv->backlight.enabled)
> intel_panel_actually_set_backlight(dev, level);
> +
> + spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
> }
>
> void intel_panel_disable_backlight(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&dev_priv->backlight.lock, flags);
>
> dev_priv->backlight.enabled = false;
> intel_panel_actually_set_backlight(dev, 0);
> @@ -314,12 +322,17 @@ void intel_panel_disable_backlight(struct drm_device
> *dev)
> I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
> }
> }
> +
> + spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
> }
>
> void intel_panel_enable_backlight(struct drm_device *dev,
> enum pipe pipe)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&dev_priv->backlight.lock, flags);
>
> if (dev_priv->backlight.level == 0) {
> dev_priv->backlight.level = intel_panel_get_max_backlight(dev);
> @@ -372,12 +385,15 @@ set_level:
>*/
> if (!intel_panel_get_backlight(dev))
> intel_panel_actually_set_backlight(dev,
> dev_priv->backlight.level);
> +
> + spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
> }
>
> static void intel_panel_init_backlight(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> + spin_lock_init(&dev_priv->backlight.lock);
> dev_priv->backlight.level = intel_panel_get_backlight(dev);
> dev_priv->backlight.enabled = dev_priv->backlight.level != 0;
> }
> --
> 1.7.9.5
>
> ___
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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[Intel-gfx] [PATCH 3/3] drm/i915: Don't use the HDMI port color range bit on Valleyview
From: Ville Syrjälä VLV docs still list the the color range selection bit for the HDMI ports, but for DP ports it has been repurposed. I have no idea whether the HDMI color range selection bit still works on VLV, but since we now have to use the PIPECONF color range bit for DP, we might as well do the same for HDMI. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_hdmi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index b206a0d..ee4a8da 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -602,7 +602,7 @@ static void intel_hdmi_mode_set(struct drm_encoder *encoder, u32 hdmi_val; hdmi_val = SDVO_ENCODING_HDMI; - if (!HAS_PCH_SPLIT(dev)) + if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) hdmi_val |= intel_hdmi->color_range; if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; -- 1.8.1.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm/i915: Introduce i9xx_set_pipeconf()
From: Ville Syrjälä
Extract the PIPECONF setup into i9xx_set_pipeconf(). This makes the
<=Gen4/VLV code follow the same pattern as the Gen5+ codepaths.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 123 +++
1 file changed, 68 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 298bc0c..dfaea15 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4514,6 +4514,71 @@ static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc,
((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
}
+static void i9xx_set_pipeconf(struct drm_crtc *crtc,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode,
+ bool is_dp)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc->pipe;
+ u32 pipeconf;
+
+ /* setup pipeconf */
+ pipeconf = I915_READ(PIPECONF(pipe));
+
+ if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
+ /* Enable pixel doubling when the dot clock is > 90% of the
(display)
+* core speed.
+*
+* XXX: No double-wide on 915GM pipe B. Is that the only reason
for the
+* pipe == 0 check?
+*/
+ if (mode->clock >
+ dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
+ pipeconf |= PIPECONF_DOUBLE_WIDE;
+ else
+ pipeconf &= ~PIPECONF_DOUBLE_WIDE;
+ }
+
+ /* default to 8bpc */
+ pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
+ if (is_dp && intel_crtc->config.dither) {
+ pipeconf |= PIPECONF_6BPC |
+ PIPECONF_DITHER_EN |
+ PIPECONF_DITHER_TYPE_SP;
+ }
+
+ if (IS_VALLEYVIEW(dev) &&
+ intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP) &&
+ intel_crtc->config.dither) {
+ pipeconf |= PIPECONF_6BPC |
+ PIPECONF_ENABLE |
+ I965_PIPECONF_ACTIVE;
+ }
+
+ if (HAS_PIPE_CXSR(dev)) {
+ if (intel_crtc->lowfreq_avail) {
+ DRM_DEBUG_KMS("enabling CxSR downclocking\n");
+ pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
+ } else {
+ DRM_DEBUG_KMS("disabling CxSR downclocking\n");
+ pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
+ }
+ }
+
+ pipeconf &= ~PIPECONF_INTERLACE_MASK;
+ if (!IS_GEN2(dev) &&
+ adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
+ pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
+ else
+ pipeconf |= PIPECONF_PROGRESSIVE;
+
+ I915_WRITE(PIPECONF(pipe), pipeconf);
+ POSTING_READ(PIPECONF(pipe));
+}
+
static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
int x, int y,
struct drm_framebuffer *fb)
@@ -4528,7 +4593,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
int plane = intel_crtc->plane;
int refclk, num_connectors = 0;
intel_clock_t clock, reduced_clock;
- u32 dspcntr, pipeconf;
+ u32 dspcntr;
bool ok, has_reduced_clock = false, is_sdvo = false;
bool is_lvds = false, is_tv = false, is_dp = false;
struct intel_encoder *encoder;
@@ -4605,9 +4670,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
has_reduced_clock ? &reduced_clock : NULL,
num_connectors);
- /* setup pipeconf */
- pipeconf = I915_READ(PIPECONF(pipe));
-
/* Set up the display plane register */
dspcntr = DISPPLANE_GAMMA_ENABLE;
@@ -4618,58 +4680,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
dspcntr |= DISPPLANE_SEL_PIPE_B;
}
- if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
- /* Enable pixel doubling when the dot clock is > 90% of the
(display)
-* core speed.
-*
-* XXX: No double-wide on 915GM pipe B. Is that the only reason
for the
-* pipe == 0 check?
-*/
- if (mode->clock >
- dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
- pipeconf |= PIPECONF_DOUBLE_WIDE;
- else
- pipeconf &= ~PIPECONF_DOUBLE_WIDE;
- }
-
- /* default to 8bpc */
- pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
- if (is_dp) {
- if (intel_crtc->config.
[Intel-gfx] [PATCH 2/3] drm/i915: Set PIPECONF color range bit on Valleyview
From: Ville Syrjälä
VLV has the color range selection bit in the PIPECONF register.
Configure it appropriately.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index dfaea15..e49d86a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4575,6 +4575,13 @@ static void i9xx_set_pipeconf(struct drm_crtc *crtc,
else
pipeconf |= PIPECONF_PROGRESSIVE;
+ if (IS_VALLEYVIEW(dev)) {
+ if (intel_crtc->config.limited_color_range)
+ pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
+ else
+ pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
+ }
+
I915_WRITE(PIPECONF(pipe), pipeconf);
POSTING_READ(PIPECONF(pipe));
}
--
1.8.1.5
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[Intel-gfx] [PATCH 0/3] drm/i915: VLV color range stuff
This is an attempt to make the RGB output color range selection work on VLV. I also decided to refactor the <=gen4 PIPECONF setup code, so that it looks a bit more like the the ILK/HSW codepaths. So far this is only compile tested. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/5] drm/i915: drop code duplication in favor of asle interrupt handler
With the previous work asle and gse interrupt handlers should now be
functionally the same. Drop the duplicated code.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h |1 -
drivers/gpu/drm/i915/i915_irq.c |4 ++--
drivers/gpu/drm/i915/intel_opregion.c | 37 -
3 files changed, 2 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2e59610..968a76e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1801,7 +1801,6 @@ extern int intel_opregion_setup(struct drm_device *dev);
extern void intel_opregion_init(struct drm_device *dev);
extern void intel_opregion_fini(struct drm_device *dev);
extern void intel_opregion_asle_intr(struct drm_device *dev);
-extern void intel_opregion_gse_intr(struct drm_device *dev);
extern void intel_opregion_enable_asle(struct drm_device *dev);
#else
static inline void intel_opregion_init(struct drm_device *dev) { return; }
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4c5bdd0..76cd3f2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -790,7 +790,7 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
dp_aux_irq_handler(dev);
if (de_iir & DE_GSE_IVB)
- intel_opregion_gse_intr(dev);
+ intel_opregion_asle_intr(dev);
for (i = 0; i < 3; i++) {
if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
@@ -882,7 +882,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
dp_aux_irq_handler(dev);
if (de_iir & DE_GSE)
- intel_opregion_gse_intr(dev);
+ intel_opregion_asle_intr(dev);
if (de_iir & DE_PIPEA_VBLANK)
drm_handle_vblank(dev, 0);
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
b/drivers/gpu/drm/i915/intel_opregion.c
index c3a288e..3e22cea 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -224,43 +224,6 @@ void intel_opregion_asle_intr(struct drm_device *dev)
iowrite32(asle_stat, &asle->aslc);
}
-void intel_opregion_gse_intr(struct drm_device *dev)
-{
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct opregion_asle __iomem *asle = dev_priv->opregion.asle;
- u32 asle_stat = 0;
- u32 asle_req;
-
- if (!asle)
- return;
-
- asle_req = ioread32(&asle->aslc) & ASLE_REQ_MSK;
-
- if (!asle_req) {
- DRM_DEBUG_DRIVER("non asle set request??\n");
- return;
- }
-
- if (asle_req & ASLE_SET_ALS_ILLUM) {
- DRM_DEBUG_DRIVER("Illum is not supported\n");
- asle_stat |= ASLE_ALS_ILLUM_FAILED;
- }
-
- if (asle_req & ASLE_SET_BACKLIGHT)
- asle_stat |= asle_set_backlight(dev, ioread32(&asle->bclp));
-
- if (asle_req & ASLE_SET_PFIT) {
- DRM_DEBUG_DRIVER("Pfit is not supported\n");
- asle_stat |= ASLE_PFIT_FAILED;
- }
-
- if (asle_req & ASLE_SET_PWM_FREQ) {
- DRM_DEBUG_DRIVER("PWM freq is not supported\n");
- asle_stat |= ASLE_PWM_FREQ_FAILED;
- }
-
- iowrite32(asle_stat, &asle->aslc);
-}
#define ASLE_ALS_EN(1<<0)
#define ASLE_BLC_EN(1<<1)
#define ASLE_PFIT_EN (1<<2)
--
1.7.9.5
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[Intel-gfx] [PATCH 4/5] drm/i915/opregion: don't pretend we did something when we didn't
In theory, the BIOS should not even request these from us now that we
aren't claiming we support these, but when it does anyway, don't pretend it
succeeded. It should be the right thing to do, but might confuse the BIOS.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_opregion.c | 19 ++-
1 file changed, 6 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
b/drivers/gpu/drm/i915/intel_opregion.c
index a622fd0..c3a288e 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -174,29 +174,22 @@ static u32 asle_set_als_illum(struct drm_device *dev, u32
alsi)
{
/* alsi is the current ALS reading in lux. 0 indicates below sensor
range, 0x indicates above sensor range. 1-0xfffe are valid */
- return 0;
+ DRM_DEBUG_DRIVER("Illum is not supported\n");
+ return ASLE_ALS_ILLUM_FAILED;
}
static u32 asle_set_pwm_freq(struct drm_device *dev, u32 pfmb)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
- if (pfmb & ASLE_PFMB_PWM_VALID) {
- u32 blc_pwm_ctl = I915_READ(BLC_PWM_CTL);
- u32 pwm = pfmb & ASLE_PFMB_PWM_MASK;
- blc_pwm_ctl &= BACKLIGHT_DUTY_CYCLE_MASK;
- pwm = pwm >> 9;
- /* FIXME - what do we do with the PWM? */
- }
- return 0;
+ DRM_DEBUG_DRIVER("PWM freq is not supported\n");
+ return ASLE_PWM_FREQ_FAILED;
}
static u32 asle_set_pfit(struct drm_device *dev, u32 pfit)
{
/* Panel fitting is currently controlled by the X code, so this is a
noop until modesetting support works fully */
- if (!(pfit & ASLE_PFIT_VALID))
- return ASLE_PFIT_FAILED;
- return 0;
+ DRM_DEBUG_DRIVER("Pfit is not supported\n");
+ return ASLE_PFIT_FAILED;
}
void intel_opregion_asle_intr(struct drm_device *dev)
--
1.7.9.5
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[Intel-gfx] [PATCH 3/5] drm/i915: don't pretend we support ASLE ALS, PFIT, or PFMB
In theory, this should prevent the BIOS from requesting them from us, and this should be the right thing. In practice, this is not always the case, and might surprise the BIOS. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_opregion.c |4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c index 4d33874..a622fd0 100644 --- a/drivers/gpu/drm/i915/intel_opregion.c +++ b/drivers/gpu/drm/i915/intel_opregion.c @@ -282,9 +282,7 @@ void intel_opregion_enable_asle(struct drm_device *dev) if (IS_MOBILE(dev)) intel_enable_asle(dev); - iowrite32(ASLE_ALS_EN | ASLE_BLC_EN | ASLE_PFIT_EN | - ASLE_PFMB_EN, - &asle->tche); + iowrite32(ASLE_BLC_EN, &asle->tche); iowrite32(1, &asle->ardy); } } -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/5] drm/i915: protect backlight enable and level with spinlock
Backlight is fiddled both through backlight sysfs files and asle
interrupts. Protect the relevant data.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h|1 +
drivers/gpu/drm/i915/intel_panel.c | 16
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5e38a2c..2e59610 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -943,6 +943,7 @@ typedef struct drm_i915_private {
struct {
int level;
bool enabled;
+ spinlock_t lock;
struct backlight_device *device;
} backlight;
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index 0e7e873..2a95297 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -285,6 +285,9 @@ static void intel_panel_actually_set_backlight(struct
drm_device *dev, u32 level
void intel_panel_set_backlight(struct drm_device *dev, u32 level)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned long flags;
+
+ spin_lock_irqsave(&dev_priv->backlight.lock, flags);
dev_priv->backlight.level = level;
if (dev_priv->backlight.device)
@@ -292,11 +295,16 @@ void intel_panel_set_backlight(struct drm_device *dev,
u32 level)
if (dev_priv->backlight.enabled)
intel_panel_actually_set_backlight(dev, level);
+
+ spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
}
void intel_panel_disable_backlight(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned long flags;
+
+ spin_lock_irqsave(&dev_priv->backlight.lock, flags);
dev_priv->backlight.enabled = false;
intel_panel_actually_set_backlight(dev, 0);
@@ -314,12 +322,17 @@ void intel_panel_disable_backlight(struct drm_device *dev)
I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
}
}
+
+ spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
}
void intel_panel_enable_backlight(struct drm_device *dev,
enum pipe pipe)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned long flags;
+
+ spin_lock_irqsave(&dev_priv->backlight.lock, flags);
if (dev_priv->backlight.level == 0) {
dev_priv->backlight.level = intel_panel_get_max_backlight(dev);
@@ -372,12 +385,15 @@ set_level:
*/
if (!intel_panel_get_backlight(dev))
intel_panel_actually_set_backlight(dev,
dev_priv->backlight.level);
+
+ spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
}
static void intel_panel_init_backlight(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ spin_lock_init(&dev_priv->backlight.lock);
dev_priv->backlight.level = intel_panel_get_backlight(dev);
dev_priv->backlight.enabled = dev_priv->backlight.level != 0;
}
--
1.7.9.5
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[Intel-gfx] [PATCH 1/5] drm/i915: group backlight related stuff into a struct
No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h| 11 +
drivers/gpu/drm/i915/intel_panel.c | 44 ++--
2 files changed, 29 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2962a9a..5e38a2c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -939,9 +939,14 @@ typedef struct drm_i915_private {
struct intel_overlay *overlay;
unsigned int sprite_scaling_enabled;
+ /* backlight */
+ struct {
+ int level;
+ bool enabled;
+ struct backlight_device *device;
+ } backlight;
+
/* LVDS info */
- int backlight_level; /* restore backlight to this value */
- bool backlight_enabled;
struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
@@ -1043,8 +1048,6 @@ typedef struct drm_i915_private {
*/
struct work_struct console_resume_work;
- struct backlight_device *backlight;
-
struct drm_property *broadcast_rgb_property;
struct drm_property *force_audio_property;
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index 21f415a..0e7e873 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -286,11 +286,11 @@ void intel_panel_set_backlight(struct drm_device *dev,
u32 level)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- dev_priv->backlight_level = level;
- if (dev_priv->backlight)
- dev_priv->backlight->props.brightness = level;
+ dev_priv->backlight.level = level;
+ if (dev_priv->backlight.device)
+ dev_priv->backlight.device->props.brightness = level;
- if (dev_priv->backlight_enabled)
+ if (dev_priv->backlight.enabled)
intel_panel_actually_set_backlight(dev, level);
}
@@ -298,7 +298,7 @@ void intel_panel_disable_backlight(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- dev_priv->backlight_enabled = false;
+ dev_priv->backlight.enabled = false;
intel_panel_actually_set_backlight(dev, 0);
if (INTEL_INFO(dev)->gen >= 4) {
@@ -321,15 +321,15 @@ void intel_panel_enable_backlight(struct drm_device *dev,
{
struct drm_i915_private *dev_priv = dev->dev_private;
- if (dev_priv->backlight_level == 0) {
- dev_priv->backlight_level = intel_panel_get_max_backlight(dev);
- if (dev_priv->backlight)
- dev_priv->backlight->props.brightness =
- dev_priv->backlight_level;
+ if (dev_priv->backlight.level == 0) {
+ dev_priv->backlight.level = intel_panel_get_max_backlight(dev);
+ if (dev_priv->backlight.device)
+ dev_priv->backlight.device->props.brightness =
+ dev_priv->backlight.level;
}
- dev_priv->backlight_enabled = true;
- intel_panel_actually_set_backlight(dev, dev_priv->backlight_level);
+ dev_priv->backlight.enabled = true;
+ intel_panel_actually_set_backlight(dev, dev_priv->backlight.level);
if (INTEL_INFO(dev)->gen >= 4) {
uint32_t reg, tmp;
@@ -371,15 +371,15 @@ set_level:
* when BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1 are written.
*/
if (!intel_panel_get_backlight(dev))
- intel_panel_actually_set_backlight(dev,
dev_priv->backlight_level);
+ intel_panel_actually_set_backlight(dev,
dev_priv->backlight.level);
}
static void intel_panel_init_backlight(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- dev_priv->backlight_level = intel_panel_get_backlight(dev);
- dev_priv->backlight_enabled = dev_priv->backlight_level != 0;
+ dev_priv->backlight.level = intel_panel_get_backlight(dev);
+ dev_priv->backlight.enabled = dev_priv->backlight.level != 0;
}
enum drm_connector_status
@@ -433,21 +433,21 @@ int intel_panel_setup_backlight(struct drm_connector
*connector)
memset(&props, 0, sizeof(props));
props.type = BACKLIGHT_RAW;
- props.brightness = dev_priv->backlight_level;
+ props.brightness = dev_priv->backlight.level;
props.max_brightness = _intel_panel_get_max_backlight(dev);
if (props.max_brightness == 0) {
DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n");
return -ENODEV;
}
- dev_priv->backlight =
+ dev_priv->backlight.device =
backlight_device_register("intel_backlight",
&connector->kdev, dev,
&intel_panel_bl_ops, &p
[Intel-gfx] [PATCH 0/5] drm/i915: backlight locking, cleanup
I think these should DTRT, but with backlight and BIOS you never seem to know... BR, Jani. Jani Nikula (5): drm/i915: group backlight related stuff into a struct drm/i915: protect backlight enable and level with spinlock drm/i915: don't pretend we support ASLE ALS, PFIT, or PFMB drm/i915/opregion: don't pretend we did something when we didn't drm/i915: drop code duplication in favor of asle interrupt handler drivers/gpu/drm/i915/i915_drv.h | 13 --- drivers/gpu/drm/i915/i915_irq.c |4 +-- drivers/gpu/drm/i915/intel_opregion.c | 60 - drivers/gpu/drm/i915/intel_panel.c| 60 + 4 files changed, 55 insertions(+), 82 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/11] drm/i915: add Punit read/write routines for VLV
On Thu, Mar 28, 2013 at 09:55:44AM -0700, Jesse Barnes wrote:
> Slightly different than other platforms.
>
> v2 [Jani]: Fix IOSF_BYTE_ENABLES_SHIFT shift. Use common routine.
>
> Signed-off-by: Jesse Barnes
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_drv.h |2 ++
> drivers/gpu/drm/i915/i915_reg.h | 22
> drivers/gpu/drm/i915/intel_pm.c | 53
> +++
> 3 files changed, 77 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 182c494..642cb1f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1845,6 +1845,8 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private
> *dev_priv);
>
> int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32
> *val);
> int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32
> val);
> +int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32
> *val);
> +int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32
> val);
>
> #define __i915_read(x, y) \
> u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 68051d6..87a59eb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4451,6 +4451,28 @@
> #define GEN6_PCODE_DATA 0x138128
> #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
>
> +#define VLV_IOSF_DOORBELL_REQ0x182100
> +#define IOSF_DEVFN_SHIFT 24
> +#define IOSF_OPCODE_SHIFT 16
> +#define IOSF_PORT_SHIFT8
> +#define IOSF_BYTE_ENABLES_SHIFT4
> +#define IOSF_BAR_SHIFT 1
> +#define IOSF_SB_BUSY (1<<0)
> +#define IOSF_PORT_PUNIT0x4
> +#define VLV_IOSF_DATA0x182104
> +#define VLV_IOSF_ADDR0x182108
> +
> +#define PUNIT_REG_GPU_LFM0xd3
> +#define PUNIT_REG_GPU_FREQ_REQ 0xd4
> +#define PUNIT_REG_GPU_FREQ_STS 0xd8
> +#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
These should be part of the turbo patch.
> +
> +#define PUNIT_OPCODE_REG_READ6
> +#define PUNIT_OPCODE_REG_WRITE 7
> +
> +#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
> +#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
Ditto.
> +
> #define GEN6_GT_CORE_STATUS 0x138060
> #define GEN6_CORE_CPD_STATE_MASK (7<<4)
> #define GEN6_RCn_MASK 7
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6fa9b79..8256d0d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4525,3 +4525,56 @@ int sandybridge_pcode_write(struct drm_i915_private
> *dev_priv, u8 mbox, u32 val)
>
> return 0;
> }
> +
> +static int vlv_punit_rw(struct drm_i915_private *dev_priv, u8 opcode,
> + u8 addr, u32 *val)
> +{
> + u32 cmd, devfn, port, be, bar;
> +
> + bar = 0;
> + be = 0xf;
> + port = IOSF_PORT_PUNIT;
> + devfn = 16;
PCI_DEVFN(2,0) maybe? I think I'm missing some doc that tells
me what kind of magic devfn and bar should contain.
Apart from those small nits:
Reviewed-by: Ville Syrjälä
> +
> + cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
> + (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
> + (bar << IOSF_BAR_SHIFT);
> +
> + WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> +
> + if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
> + DRM_DEBUG_DRIVER("warning: pcode (%s) mailbox access failed\n",
> + opcode == PUNIT_OPCODE_REG_READ ?
> + "read" : "write");
> + return -EAGAIN;
> + }
> +
> + I915_WRITE(VLV_IOSF_ADDR, addr);
> + if (opcode == PUNIT_OPCODE_REG_WRITE)
> + I915_WRITE(VLV_IOSF_DATA, *val);
> + I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
> +
> + if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
> + 500)) {
> + DRM_ERROR("timeout waiting for pcode %s (%d) to finish\n",
> + opcode == PUNIT_OPCODE_REG_READ ? "read" : "write",
> + addr);
> + return -ETIMEDOUT;
> + }
> +
> + if (opcode == PUNIT_OPCODE_REG_READ)
> + *val = I915_READ(VLV_IOSF_DATA);
> + I915_WRITE(VLV_IOSF_DATA, 0);
> +
> + return 0;
> +}
> +
> +int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32
> *val)
> +{
> + return vlv_punit_rw(dev_priv, PUNIT_
Re: [Intel-gfx] [PATCH 11/11] drm/i915: limit DPFLIPSTAT enables to those we use on VLV
On Thu, Mar 28, 2013 at 09:55:47AM -0700, Jesse Barnes wrote: > Thus preventing the display from keeping the GT awake with unnecessary > signals. > > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/intel_pm.c |6 ++ > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 2b02702..de9f898 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4116,11 +4116,9 @@ static void valleyview_init_clock_gating(struct > drm_device *dev) >* when flip and other events complete. So enable >* all the GUnit->GT interrupts here >*/ > - I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN | > -PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN | > + I915_WRITE(VLV_DPFLIPSTAT, > SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN | > -PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN | > -PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN | > +PLANEB_FLIPDONE_INT_EN | > SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN | > PLANEA_FLIPDONE_INT_EN); We're not doing CS page flips w/ sprites currently, so I think you could drop the sprite bits too. Actually, now that I think about it, do we need any bits enabled here? i915_gem_execbuffer_wait_for_flips() is gone, so AFAICS GT no longer needs to know when page flips complete. -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/11] drm/i915: sprite support for ValleyView v3
On Thu, Mar 28, 2013 at 09:55:37AM -0700, Jesse Barnes wrote:
> No constant alpha yet though, that needs a new ioctl and/or property to
> get/set.
>
> v2: use drm_plane_format_cpp (Ville)
> fix up vlv_disable_plane, remove IVB bits (Ville)
> remove error path rework (Ville)
> fix component order confusion (Ville)
> clean up platform init (Ville)
> use compute_offset_xtiled (Ville)
> v3: fix up more format confusion (Ville)
> update to new page offset function (Ville)
>
> Signed-off-by: Jesse Barnes
> ---
> drivers/gpu/drm/i915/i915_dma.c |4 +
> drivers/gpu/drm/i915/i915_drv.h |1 +
> drivers/gpu/drm/i915/i915_reg.h | 57 +
> drivers/gpu/drm/i915/intel_display.c | 13 ++-
> drivers/gpu/drm/i915/intel_drv.h |3 +-
> drivers/gpu/drm/i915/intel_sprite.c | 213
> --
> 6 files changed, 277 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index ebcfe2e..4be58e3 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -1630,6 +1630,10 @@ int i915_driver_load(struct drm_device *dev, unsigned
> long flags)
> mutex_init(&dev_priv->rps.hw_lock);
> mutex_init(&dev_priv->modeset_restore_lock);
>
> + dev_priv->num_plane = 1;
> + if (IS_VALLEYVIEW(dev))
> + dev_priv->num_plane = 2;
> +
> ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
> if (ret)
> goto out_gem_unload;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1657d873..2832cdb 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -914,6 +914,7 @@ typedef struct drm_i915_private {
> bool enable_hotplug_processing;
>
> int num_pch_pll;
> + int num_plane;
>
> unsigned long cfb_size;
> unsigned int cfb_fb;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bceca11..d0f7cb9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3261,6 +3261,63 @@
> #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
> #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
>
> +#define _SPACNTR 0x72180
> +#define SP_ENABLE (1<<31)
> +#define SP_GEAMMA_ENABLE (1<<30)
> +#define SP_PIXFORMAT_MASK (0xf<<26)
> +#define SP_FORMAT_YUV422 (0<<26)
> +#define SP_FORMAT_BGR565 (5<<26)
> +#define SP_FORMAT_BGRX (6<<26)
> +#define SP_FORMAT_BGRA (7<<26)
> +#define SP_FORMAT_RGBX1010102 (8<<26)
> +#define SP_FORMAT_RGBA1010102 (9<<26)
> +#define SP_FORMAT_RGBX (0xe<<26)
> +#define SP_FORMAT_RGBA (0xf<<26)
> +#define SP_SOURCE_KEY (1<<22)
> +#define SP_YUV_BYTE_ORDER_MASK (3<<16)
> +#define SP_YUV_ORDER_YUYV (0<<16)
> +#define SP_YUV_ORDER_UYVY (1<<16)
> +#define SP_YUV_ORDER_YVYU (2<<16)
> +#define SP_YUV_ORDER_VYUY (3<<16)
> +#define SP_TILED (1<<10)
> +#define _SPALINOFF 0x72184
> +#define _SPASTRIDE 0x72188
> +#define _SPAPOS 0x7218c
> +#define _SPASIZE 0x72190
> +#define _SPAKEYMINVAL0x72194
> +#define _SPAKEYMSK 0x72198
> +#define _SPASURF 0x7219c
> +#define _SPAKEYMAXVAL0x721a0
> +#define _SPATILEOFF 0x721a4
> +#define _SPACONSTALPHA 0x721a8
> +#define _SPAGAMC 0x721f4
> +
> +#define _SPBCNTR 0x72280
> +#define _SPBLINOFF 0x72284
> +#define _SPBSTRIDE 0x72288
> +#define _SPBPOS 0x7228c
> +#define _SPBSIZE 0x72290
> +#define _SPBKEYMINVAL0x72294
> +#define _SPBKEYMSK 0x72298
> +#define _SPBSURF 0x7229c
> +#define _SPBKEYMAXVAL0x722a0
> +#define _SPBTILEOFF 0x722a4
> +#define _SPBCONSTALPHA 0x722a8
> +#define _SPBGAMC 0x722f4
> +
> +#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
> +#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
> +#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
> +#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
> +#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
> +#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL,
> _SPBKEYMINVAL)
> +#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
> +#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
> +#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL,
> _SPBKEYMAXVAL)
> +#define SPTILEOFF(pipe, plane
Re: [Intel-gfx] [PATCH xf96-video-intel] DRI2GetMSC: Do not send a bogus ust when no drawable is not displayed
On Fri, Mar 29, 2013 at 09:54:50AM -0700, Stéphane Marchesin wrote: > On Fri, Mar 29, 2013 at 5:54 AM, Chris Wilson > wrote: > > That's a problem as we would need a running pipe, which is not > > guaranteed. I wonder if CLOCK_MONOTONIC would suffice? > > Yeah that's what I had in mind. Would that work for you? I think so, the value looks like it should be consistent with the kernel. I've applied a patch to return the CLOCK_MONOTONIC usec, thanks. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-intel-next
Hi Dave, So I've figured we should get drm-next for 3.10 started ;-) Highlights: - Imre's for_each_sg_pages rework (now also with the stolen mem backed case fixed with a hack) plus the drm prime sg list coalescing patch from Rahul Sharma. I have some follow-up cleanups pending, already acked by Andrew Morton. - Some prep-work for the crazy no-pch/display-less platform by Ben. - Some vlv patches, by far not all (Jesse et al). - Clean up the HDMI/SDVO #define confusion (Paulo) - gen2-4 vblank fixes from Ville. - Unclaimed register warning fixes for hsw (Paulo). More still to come ... - Complete pageflips which have been stuck in a gpu hang, should prevent stuck gl compositors (Ville). - pm patches for vt-switchless resume (Jesse). Note that the i915 enabling is not (yet) included, that took a bit longer to settle. PM patches are acked by Rafael Wysocki. - Minor fixlets all over from various people. All together it's been pretty quiet thus far. Cheers, Daniel The following changes since commit a937536b868b8369b98967929045f1df54234323: Linux 3.9-rc3 (2013-03-17 15:59:32 -0700) are available in the git repository at: git://people.freedesktop.org/~danvet/drm-intel tags/drm-intel-next-2013-03-23 for you to fetch changes up to e3dff585508636c8d2915cc1595e04f16ccd66ba: drm/i915: Implement WaSwitchSolVfFArbitrationPriority (2013-03-23 12:18:06 +0100) Ben Widawsky (9): drm/i915: Created a sized object error dump drm/i915: exclude CCID for platforms without it drm/i915: Capture current context on error drm/i915: Remove unused file arg from execbuf drm/i915: Remove unneeded dev argument drm/i915: Move num_pipes to intel info drm/i915: Introduce GEN7_FEATURES for device info drm/i915: Correct sandybrige overclocking drm/i915: Implement WaSwitchSolVfFArbitrationPriority Chris Wilson (1): drm/i915: Resurrect ring kicking for semaphores, selectively Damien Lespiau (1): drm/i915: Remove platforms in the preliminary_hw_support description Daniel Vetter (4): drm/i915: gen2 has no tv out support Merge tag 'v3.9-rc3' into drm-intel-next-queued style nit: Align function parameter continuation properly. drm/i915: fixup pd vs pt confusion in gen6 ppgtt code Imre Deak (5): drm: handle compact dma scatter lists in drm_clflush_sg() drm/i915: set dummy page for stolen objects drm/i915: handle walking compact dma scatter lists drm/i915: create compact dma scatter lists for gem objects drm/i915: use for_each_sg_page for setting up the gtt ptes Jani Nikula (2): drm/i915: add \n to the end of sysfs attributes drm/i915: reduce power in the ilk rc6 enable error message Jesse Barnes (18): PM: make VT switching to the suspend console optional v3 fb: add support for drivers not needing VT switch at suspend/resume time drm/i915: don't restore LVDS enable state blindly v2 drm/i915: remove disabled memset of framebuffer from intel_fb drm/i915: don't init LVDS on VLV drm/i915: VLV has force wake drm/i915/dp: don't use ILK paths on VLV drm/i915: use gen6 stolen check on VLV drm/i915/dp: add pre-PCH eDP checking to DP detect for VLV drm/i915: allow force wake at init time on VLV v2 drm/i915: don't use plane pipe select on VLV drm/i915: add media well to VLV force wake routines v2 drm/i915: use VLV DIP routines on VLV v2 drm/i915: add more VLV IDs drm/i915: fix WaDisablePSDDualDispatchEnable on VLV v2 drm/i915: set conservative clock gating values on VLV v2 drm/i915: DSPFW and BLC regs are in the display offset range drm/i915: VLV doesn't have HDMI on port C Kees Cook (2): drm/i915: use simple attribute in debugfs routines drm/i915: clarify reasoning for the access_ok call Mihnea Dobrescu-Balaur (1): gpu: don't cast kzalloc() return value Mika Kuoppala (1): drm/i915: remove obsolete obj assignment in page flip Paulo Zanoni (19): drm/i915: use HAS_DDI on intel_hdmi.c and intel_display.c drm/i915: wait_event_timeout's timeout is in jiffies drm/i915: add aux_ch_ctl_reg to struct intel_dp drm/i915: rename sdvox_reg to hdmi_reg on HDMI context drm/i915: create functions for the "unclaimed register" checks drm/i915: use FPGA_DBG for the "unclaimed register" checks drm/i915: clear the FPGA_DBG_RM_NOCLAIM bit at driver init drm/i915: clarify confusion between SDVO and HDMI registers drm/i915: unify the definitions of the HDMI/SDVO register drm/i915: remove duplicated SDVO/HDMI bit definitions drm/i915: rename some HDMI bit definitions drm/i915: disable sound first on intel_disable_ddi drm/i915: capture the correct cursor registers on IVB drm/i915: there's no DSPSIZE register on gen4+ drm/i915: there's no DS
Re: [Intel-gfx] [PATCH] drm/i915: implement ibx_hpd_irq_setup
Hi Daniel, Daniel Vetter writes: > On Fri, Mar 29, 2013 at 5:35 PM, Egbert Eich wrote: > > Yeah, makes sense now that I think about it - I've simply didn't look > ahead in your patch series while writing this little fixup ;-) Can you > just re-add this when resending your patches again please? > Sure, I have prepared all the patches. I just wanted to give them a try before sending them. Unfortunately I did not get around to do so over the Easter holidays. Cheers, Egbert. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
