Re: [Intel-gfx] [PATCH 35/43] drm/i915: Move __raw_i915_read8() & co. into i915_drv.h

[Chris Wilson]

On Fri, Sep 18, 2015 at 09:37:38PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 18, 2015 at 07:33:50PM +0100, Chris Wilson wrote:
> > On Fri, Sep 18, 2015 at 09:23:11PM +0300, Ville Syrjälä wrote:
> > > On Fri, Sep 18, 2015 at 06:42:17PM +0100, Chris Wilson wrote:
> > > > On Fri, Sep 18, 2015 at 08:03:48PM +0300, ville.syrj...@linux.intel.com 
> > > > wrote:
> > > > > From: Ville Syrjälä 
> > > > > 
> > > > > We have a few users of the raw register acces functions outside
> > > > > intel_uncore.c, so let's just move the functions into intel_drv.h.
> > > > 
> > > > I would rather see those external users converted to
> > > > I915_READ_FW/I915_WRITE_FW etc. You will then, no doubt, want to convert
> > > > those _FW macro definitions over to the uncore set.
> > > > 
> > > > Also due to how we write and post our accesses, the raw functions can be
> > > > the _relaxed variants.
> > > 
> > > Hmm. I think the only difference with the relaxed vs. not would be
> > > potential compiler reordering of memory accesses vs. mmio. So if we
> > > start using the relaxed versions we may need to start sprinkling
> > > barriers around.
> > 
> > Yes. We have been working under that assumption (weak ordering of writes),
> > or at least I hope we all have been...
> 
> Well, looking at the irq code that uses the _FW, what would prevent the
> compiler from eg. reorder the seqno read to happen before the IIR read?
> Well in practice function calls are involved, so there's a barrier
> there, but say we would want to read the seqno straight from the irq
> handler...

What seqno read? We definitely don't want to be doing those expensive
reads from an irq handler...

Anyway, I thought we had strongly ordered reads on x64/x32?
-Chris

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Re: [Intel-gfx] [PATCH 00/43] drm/i915: Type safe register read/write and a ton of prep work

[Chris Wilson]

On Fri, Sep 18, 2015 at 08:03:13PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> Inspired by the recent misplaced parenthesis fix from Damien, I decided to try
> and see what it would take to make our register access type safe. By that mean
> you shouldn't be able to pass in anything by a proper register offset in. 
> After
> a couple of days of hacking, this series is the result.
> 
> I managed to split out all the cleanup stuff upfront, but there is quite a bit
> of it. I did include a few random patches no strictly needed, but as long as I
> was going through the register macros I tried to fix whatever was wrong.
> 
> The actual type safe stuff is in the last patch, and I'm posting that on as an
> RFC to see what other people think about the idea. I think most of the prep
> work would be nice to have even if we decide against the type safety. Oh, 
> turns
> out I couldn't find any new "passing crap as the register offset" type of bugs
> with this work, but this would prevent them from sneaking in. As mentioned in
> the patch, I limited this only for mmio regs for now, but we could expand it
> cover other register types.
> 
> I've only smoke tested this on IVB, HSW and BSW.
> 
> The whole thing is available in my git repo:
> git://github.com/vsyrjala/linux.git type_safe_reg_access_3
> 
> Ville Syrjälä (43):
>   drm/i915: Don't pass sdvo_reg to intel_sdvo_select_{ddc,i2c}_bus()
>   drm/i915: Parametrize LRC registers
>   drm/i915: Parametrize GEN7_GT_SCRATCH and GEN7_LRA_LIMITS
>   drm/i915: Parametrize fence registers
>   drm/i915: Parametrize FBC_TAG registers
>   drm/i915: Parametrize ILK turbo registers
>   drm/i915: Replace raw numbers with the approproate register name in
> ILK turbo code
>   drm/i915: Parametrize TV luma/chroma filter registers
>   drm/i915: Parametrize DDI_BUF_TRANS registers
>   drm/i915: Parametrize CSR_PROGRAM registers
>   drm/i915: Parametrize UOS_RSA_SCRATCH
>   drm/i915: Add LO/HI PRIVATE_PAT registers
>   drm/i915: Always use GEN8_RING_PDP_{LDW,UDW} instead of hand rolling
> the register offsets
>   drm/i915: Include MCHBAR_MIRROR_BASE in ILK_GDSR
>   drm/i915: Parametrize PALETTE and LGC_PALETTE
>   drm/i915: s/_CURACNTR/CURCNTR(PIPE_A)/
>   drm/i915: s/_FDI_RXA_.../FDI_RX_...(PIPE_A)/
>   drm/i915: s/_TRANSA_CHICKEN/TRANS_CHICKEN(PIPE_A)/
>   drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc.
>   drm/i915: Use paramtrized WRPLL_CTL()
>   drm/i915: Add VLV_HDMIB etc. which already include VLV_DISPLAY_BASE
>   drm/i915: s/DDI_BUF_CTL_A/DDI_BUF_CTL(PORT_A)/
>   drm/i915: Eliminate weird parameter inversion from BXT PPS registers
>   drm/i915: Parametrize HSW video DIP data registers
>   drm/i915: Include gpio_mmio_base in GMBUS reg defines
>   drm/i915: Protect register macro arguments
>   drm/i915: Fix a few bad hex numbers in register defines
>   drm/i915: Turn GEN5_ASSERT_IIR_IS_ZERO() into a function
>   drm/i915: s/PIPE_FRMCOUNT_GM45/PIPE_FRMCOUNT_G4X/ etc.
>   drm/i915: Parametrize and fix SWF registers
>   drm/i915: Throw out some useless variables
>   drm/i915: Clean up LVDS register handling
>   drm/i915: Remove dev_priv argument from NEEDS_FORCE_WAKE
>   drm/i915: Turn __raw_i915_read8() & co. in to inline functions
>   drm/i915: Move __raw_i915_read8() & co. into i915_drv.h
>   drm/i915: Remove the magic AUX_CTL is at DP + foo tricks
>   drm/i915: Replace the aux ddc name switch statement with a table
>   drm/i915: Parametrize AUX registes
>   drm/i915: Add dev_priv->psr_mmio_base
>   drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[]
>   drm/i915: Model PSR AUX register selection more like the normal AUX
> code
>   drm/i915: Prefix raw register defines with underscore
>   WIP: drm/i915: Type safe register read/write

I've read through the series, and it looks good. I commented in a couple
of places, and I have yet to scrutinize the parametrizations to check the
values are the same (except for where you think the original values are
bogus), but I like it and I think it is worthwhile.
-Chris

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Re: [Intel-gfx] Changing the screen resolution permanently

[Felix Miata]

Engin FIRAT composed on 2015-09-18 20:07 (UTC+0300):

> In my system there are two monitors and these monitors are fed by mirrored
> displays. To get such a configuration I have created a script that
> dynamically adjusts the system by using xrandr. The script is attached as
> changeres.sh. Everything works well. However I've note that the system
> startup time is increased by ~15 seconds and I do not want such a case. To
> handle this problem, I think that I need to adjust the screen resolution
> permanently with a xorg.conf file. However I cannot create one that adjusts
> the monitors as expected. xorg.conf file is also attached to this post.

> Details of the system:
> Processor: Intel Atom E3845
> OS: Lubuntu 14.04.1
> Driver: Installed via intel-graphics-installer 1.0.7

> I have tried to create a xorg.conf file with the command X -configure,
> however the created file is for only one monitors since the system uses
> only the first monitor at its default configuration (ie. no xrandr setting)

> Could you please help me to create a correct xorg.conf file.

See if this provides enough skeleton to get you going.
http://fm.no-ip.com/Share/Linux/xorg.conf-inteldual03

Note that for your needs, each Section "Monitor" in it is overkill. It should
be sufficient to include in each only an identifier and a position option.
For 1280x1024 displays, everything else should either be unnecessary, or
auto-generate via EDID.

Note too that it intentionally contains no modelines. At least 99.% of
the time, the system is smart enough to auto-generate whatever modeline is
applicable to the appropriate mode, so don't waste your time looking for or
including any modelines unless your Commander and Operator 1280x1024 displays
have already proven themselves incapable of allowing appropriate 
auto-generation.

Note that Kubuntu has a built-in utility called kscreen that autostarts
unless you explicitly override it. Were you to add KDE to your Lubuntu, you
might find Kscreen overriding your custom configuration:
https://bugs.kde.org/show_bug.cgi?id=317929
-- 
"The wise are known for their understanding, and pleasant
words are persuasive." Proverbs 16:21 (New Living Translation)

 Team OS/2 ** Reg. Linux User #211409 ** a11y rocks!

Felix Miata  ***  http://fm.no-ip.com/
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[Intel-gfx] [PATCH 2/2] drm/i915/bxt: eDP low vswing support

[Sonika Jindal]

Adding voltage swing table for edp to support low vswings.

Signed-off-by: Sonika Jindal 
---
 drivers/gpu/drm/i915/intel_ddi.c |   23 +++
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0d9b304..17281bc 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -256,9 +256,6 @@ struct bxt_ddi_buf_trans {
bool default_index; /* true if the entry represents default value */
 };
 
-/* BSpec does not define separate vswing/pre-emphasis values for eDP.
- * Using DP values for eDP as well.
- */
 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
/* Idx  NT mV diff  db  */
{ 52,  0, 0, 128, true  },  /* 0:   400 0   */
@@ -273,6 +270,20 @@ static const struct bxt_ddi_buf_trans 
bxt_ddi_translations_dp[] = {
{ 154, 0x9A, 1, 128, false },   /* 9:   12000   */
 };
 
+static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
+   /* Idx  NT mV diff  db  */
+   { 26, 0, 0, 128, false },   /* 0:   200 0   */
+   { 38, 0, 0, 112, false },   /* 1:   200 1.5 */
+   { 48, 0, 0, 96,  false },   /* 2:   200 4   */
+   { 54, 0, 0, 69,  false },   /* 3:   200 6   */
+   { 32, 0, 0, 128, false },   /* 4:   250 0   */
+   { 48, 0, 0, 104, false },   /* 5:   250 1.5 */
+   { 54, 0, 0, 85,  false },   /* 6:   250 4   */
+   { 43, 0, 0, 128, false },   /* 7:   300 0   */
+   { 54, 0, 0, 101, false },   /* 8:   300 1.5 */
+   { 48, 0, 0, 128, false },   /* 9:   300 0   */
+};
+
 /* BSpec has 2 recommended values - entries 0 and 8.
  * Using the entry with higher vswing.
  */
@@ -2113,7 +2124,11 @@ static void bxt_ddi_vswing_sequence(struct drm_device 
*dev, u32 level,
u32 n_entries, i;
uint32_t val;
 
-   if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
+   if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) {
+   n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
+   ddi_translations = bxt_ddi_translations_edp;
+   } else if (type == INTEL_OUTPUT_DISPLAYPORT
+   || type == INTEL_OUTPUT_EDP) {
n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
ddi_translations = bxt_ddi_translations_dp;
} else if (type == INTEL_OUTPUT_HDMI) {
-- 
1.7.10.4

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[Intel-gfx] [PATCH 1/2] drm/i915/bxt: Set oscaledcompmethod to enable scale value

[Sonika Jindal]

Bspec update tells that we have to enable oscaledcompmethod instead of
ouniqetrangenmethod for enabling scale value during swing programming.
Also, scale value is 'don't care' for other levels except the last entry
translation table. So, make it 0 instead of 0x9A.

Signed-off-by: Sonika Jindal 
---
 drivers/gpu/drm/i915/i915_reg.h  |2 +-
 drivers/gpu/drm/i915/intel_ddi.c |   22 +++---
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 812b7b2..cec6546 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1395,7 +1395,7 @@ enum skl_disp_power_wells {
 #define BXT_PORT_TX_DW3_LN0(port)  _PORT3(port, _PORT_TX_DW3_LN0_A,  \
 _PORT_TX_DW3_LN0_B,  \
 _PORT_TX_DW3_LN0_C)
-#define   UNIQE_TRANGE_EN_METHOD   (1 << 27)
+#define   SCALE_DCOMP_METHOD   (1 << 26)
 
 #define _PORT_TX_DW4_LN0_A 0x162510
 #define _PORT_TX_DW4_LN0_B 0x6C510
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index fec51df..0d9b304 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -261,15 +261,15 @@ struct bxt_ddi_buf_trans {
  */
 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
/* Idx  NT mV diff  db  */
-   { 52,  0x9A, 0, 128, true  },   /* 0:   400 0   */
-   { 78,  0x9A, 0, 85,  false },   /* 1:   400 3.5 */
-   { 104, 0x9A, 0, 64,  false },   /* 2:   400 6   */
-   { 154, 0x9A, 0, 43,  false },   /* 3:   400 9.5 */
-   { 77,  0x9A, 0, 128, false },   /* 4:   600 0   */
-   { 116, 0x9A, 0, 85,  false },   /* 5:   600 3.5 */
-   { 154, 0x9A, 0, 64,  false },   /* 6:   600 6   */
-   { 102, 0x9A, 0, 128, false },   /* 7:   800 0   */
-   { 154, 0x9A, 0, 85,  false },   /* 8:   800 3.5 */
+   { 52,  0, 0, 128, true  },  /* 0:   400 0   */
+   { 78,  0, 0, 85,  false },  /* 1:   400 3.5 */
+   { 104, 0, 0, 64,  false },  /* 2:   400 6   */
+   { 154, 0, 0, 43,  false },  /* 3:   400 9.5 */
+   { 77,  0, 0, 128, false },  /* 4:   600 0   */
+   { 116, 0, 0, 85,  false },  /* 5:   600 3.5 */
+   { 154, 0, 0, 64,  false },  /* 6:   600 6   */
+   { 102, 0, 0, 128, false },  /* 7:   800 0   */
+   { 154, 0, 0, 85,  false },  /* 8:   800 3.5 */
{ 154, 0x9A, 1, 128, false },   /* 9:   12000   */
 };
 
@@ -2151,9 +2151,9 @@ static void bxt_ddi_vswing_sequence(struct drm_device 
*dev, u32 level,
I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
 
val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
-   val &= ~UNIQE_TRANGE_EN_METHOD;
+   val &= ~SCALE_DCOMP_METHOD;
if (ddi_translations[level].enable)
-   val |= UNIQE_TRANGE_EN_METHOD;
+   val |= SCALE_DCOMP_METHOD;
I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
 
val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
-- 
1.7.10.4

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Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/bxt: work around HW context corruption due to coherency problem

[Chris Wilson]

On Thu, Sep 17, 2015 at 07:17:44PM +0300, Imre Deak wrote:
> The execlist context object is mapped with a CPU/GPU coherent mapping
> everywhere, but on BXT A stepping due to a HW issue the coherency is not
> guaranteed. To work around this flush the context object after pinning
> it (to flush cache lines left by the context initialization/read-back
> from backing storage) and mark it as uncached so later updates during
> context switching will be coherent.
> 
> I noticed this problem via a GPU hang, where IPEHR pointed to an invalid
> opcode value. I couldn't find this value on the ring but looking at the
> contents of the active context object it turned out to be a parameter
> dword of a bigger command there. The original command opcode itself
> was zeroed out, based on the above I assume due to a CPU writeback of
> the corresponding cacheline. When restoring the context the GPU would
> jump over the zeroed out opcode and hang when trying to execute the
> above parameter dword.
> 
> I could easily reproduce this by running igt/gem_render_copy_redux and
> gem_tiled_blits/basic in parallel, but I guess it could be triggered by
> anything involving frequent switches between two separate contexts. With
> this workaround I couldn't reproduce the problem.
> 
> v2:
> - instead of clflushing after updating the tail and PDP values during
>   context switching, map the corresponding page as uncached to avoid a
>   race between CPU and GPU, both updating the same cacheline at the same
>   time (Ville)

No. Changing PAT involves a stop_machine() and is severely detrimental
to performance (context creation overhead does impact userspace).
Mapping it as uncached doesn't remove the race anyway.
-Chris

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Re: [Intel-gfx] [PATCH] drm/i915: cleanup pipe_update trace functions with new crtc debug info v3

[Ville Syrjälä]

On Thu, Sep 17, 2015 at 08:08:32AM -0700, Jesse Barnes wrote:
> Use the new debug info in the intel_crtc struct in these functions
> rather than passing them as args.
> 
> v2: move min/max assignment back above first trace call (Ville)
> use scanline from crtc->debug rather than fetching a new one (Ville)
> v3: fix up trace_i915_pipe_update_end, needs end scanline (Ville)
> 
> Requested-by: Ville Syrjälä 
> Signed-off-by: Jesse Barnes 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/i915_trace.h   | 26 +-
>  drivers/gpu/drm/i915/intel_sprite.c | 11 +--
>  2 files changed, 18 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_trace.h 
> b/drivers/gpu/drm/i915/i915_trace.h
> index e6b5c74..d0993bc 100644
> --- a/drivers/gpu/drm/i915/i915_trace.h
> +++ b/drivers/gpu/drm/i915/i915_trace.h
> @@ -17,8 +17,8 @@
>  /* pipe updates */
>  
>  TRACE_EVENT(i915_pipe_update_start,
> - TP_PROTO(struct intel_crtc *crtc, u32 min, u32 max),
> - TP_ARGS(crtc, min, max),
> + TP_PROTO(struct intel_crtc *crtc),
> + TP_ARGS(crtc),
>  
>   TP_STRUCT__entry(
>__field(enum pipe, pipe)
> @@ -33,8 +33,8 @@ TRACE_EVENT(i915_pipe_update_start,
>  __entry->frame = 
> crtc->base.dev->driver->get_vblank_counter(crtc->base.dev,
>   
>crtc->pipe);
>  __entry->scanline = intel_get_crtc_scanline(crtc);
> -__entry->min = min;
> -__entry->max = max;
> +__entry->min = crtc->debug.min_vbl;
> +__entry->max = crtc->debug.max_vbl;
>  ),
>  
>   TP_printk("pipe %c, frame=%u, scanline=%u, min=%u, max=%u",
> @@ -43,8 +43,8 @@ TRACE_EVENT(i915_pipe_update_start,
>  );
>  
>  TRACE_EVENT(i915_pipe_update_vblank_evaded,
> - TP_PROTO(struct intel_crtc *crtc, u32 min, u32 max, u32 frame),
> - TP_ARGS(crtc, min, max, frame),
> + TP_PROTO(struct intel_crtc *crtc),
> + TP_ARGS(crtc),
>  
>   TP_STRUCT__entry(
>__field(enum pipe, pipe)
> @@ -56,10 +56,10 @@ TRACE_EVENT(i915_pipe_update_vblank_evaded,
>  
>   TP_fast_assign(
>  __entry->pipe = crtc->pipe;
> -__entry->frame = frame;
> -__entry->scanline = intel_get_crtc_scanline(crtc);
> -__entry->min = min;
> -__entry->max = max;
> +__entry->frame = crtc->debug.start_vbl_count;
> +__entry->scanline = crtc->debug.scanline_start;
> +__entry->min = crtc->debug.min_vbl;
> +__entry->max = crtc->debug.max_vbl;
>  ),
>  
>   TP_printk("pipe %c, frame=%u, scanline=%u, min=%u, max=%u",
> @@ -68,8 +68,8 @@ TRACE_EVENT(i915_pipe_update_vblank_evaded,
>  );
>  
>  TRACE_EVENT(i915_pipe_update_end,
> - TP_PROTO(struct intel_crtc *crtc, u32 frame),
> - TP_ARGS(crtc, frame),
> + TP_PROTO(struct intel_crtc *crtc, u32 frame, int scanline_end),
> + TP_ARGS(crtc, frame, scanline_end),
>  
>   TP_STRUCT__entry(
>__field(enum pipe, pipe)
> @@ -80,7 +80,7 @@ TRACE_EVENT(i915_pipe_update_end,
>   TP_fast_assign(
>  __entry->pipe = crtc->pipe;
>  __entry->frame = frame;
> -__entry->scanline = intel_get_crtc_scanline(crtc);
> +__entry->scanline = scanline_end;
>  ),
>  
>   TP_printk("pipe %c, frame=%u, scanline=%u",
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 7de121d..79f7cc2 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -102,7 +102,9 @@ void intel_pipe_update_start(struct intel_crtc *crtc)
>   if (WARN_ON(drm_crtc_vblank_get(>base)))
>   return;
>  
> - trace_i915_pipe_update_start(crtc, min, max);
> + crtc->debug.min_vbl = min;
> + crtc->debug.max_vbl = max;
> + trace_i915_pipe_update_start(crtc);
>  
>   for (;;) {
>   /*
> @@ -133,15 +135,12 @@ void intel_pipe_update_start(struct intel_crtc *crtc)
>  
>   drm_crtc_vblank_put(>base);
>  
> - crtc->debug.min_vbl = min;
> - crtc->debug.max_vbl = max;
>   crtc->debug.scanline_start = scanline;
>   crtc->debug.start_vbl_time = ktime_get();
>   crtc->debug.start_vbl_count =
>   dev->driver->get_vblank_counter(dev, pipe);
>  
> - trace_i915_pipe_update_vblank_evaded(crtc, min, max,
> -

Re: [Intel-gfx] [PATCH] tests/gem_ctx_param_basic: fix up non-root-set-no-zeromap subtest

[Thomas Wood]

It's helpful to include "i-g-t" in the subject line for
intel-gpu-tools patches so that they are easily identified. This can
be done by using the --subject-prefix "PATCH i-g-t" option when using
git format-patch or send-email and can also be set as a local
configuration option using the following command: git config
format.subjectprefix "PATCH i-g-t"


On 17 September 2015 at 17:41, Jesse Barnes  wrote:
> This subtest is trying to set the no-zeromap flag on the context without
> root privs.  Rather than expecting an EPERM on what's presumably a
> nonzero value, we should expect success on a set call w/o root privs.
> This looks like a copy & paste error from when the subtest was added,
> since setting the ban period has different expected behavior.

There is already a patch for this: http://patchwork.freedesktop.org/patch/58991/

I was waiting for confirmation on the expected behaviour, but also
testing both root and non-root for success seems a bit redundant.
Perhaps removing the root-set test would be worthwhile.


>
> Cc: David Weinehall 
> Signed-off-by: Jesse Barnes 
> ---
>  tests/gem_ctx_param_basic.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/tests/gem_ctx_param_basic.c b/tests/gem_ctx_param_basic.c
> index 6a1694d..f7d9592 100644
> --- a/tests/gem_ctx_param_basic.c
> +++ b/tests/gem_ctx_param_basic.c
> @@ -126,8 +126,8 @@ igt_main
>
> ctx_param.context = ctx;
> TEST_SUCCESS(LOCAL_IOCTL_I915_GEM_CONTEXT_GETPARAM);
> -   ctx_param.value--;
> -   TEST_FAIL(LOCAL_IOCTL_I915_GEM_CONTEXT_SETPARAM, 
> EPERM);
> +   ctx_param.value = 0;
> +   TEST_SUCCESS(LOCAL_IOCTL_I915_GEM_CONTEXT_SETPARAM);
> }
>
> igt_waitchildren();
> --
> 1.9.1
>
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[Intel-gfx] i915: framebuffer compression causing occasional screen flickering

[Petr Kulhavy]

Hi,

I would like to post a bug report for the Intel i915 driver, not sure if 
this is the right place to do it.


The framebuffer compression feature is sometimes causing screen 
flickering on my Asus UX501 laptop (i7-4720HQ with the HD4600 graphics). 
Konsole out
I'm trying to reduce my battery usage and the kernel parameter 
"i915.enable_fbc=1" saves about 2W actually!


I'm running Kubuntu 15.04 with mainstream kernel 4.1.0 and the latest 
Intel drivers from 01.org version 1.2.0.

However I was experiencing the same problem also with previous versions.

The flickering itself is as follows. In most cases the picture (X with 
KDE desktop) is OK. However with certain image patterns the screen 
starts to flicker multiple times per second, sometimes it affects only 
part of the screen, and it looks like the picture switching fast between 
normal and a bit scrambled. The screen is still readable.


An example of an image pattern triggering the flickering  Firefox with 
youtube at the end of the video when you see the tiles with other 
similar videos to watch. If I navigate to a different page the 
flickering disappears. It is really picture dependent.


Not sure what it exactly is but with the enable_fbc=0 the problem 
reliably disappears. So I believe it is related to the framebuffer 
compression.


It would be really great if you could make the FBC working well also on 
this HW. It saves a lot of battery.


Please let me know if you need some more information.

Thanks a lot
Petr


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[Intel-gfx] regression/bug introduced by commit [0e572fe7383a376992364914694c39aa7fe44c1d] drm/i915: runtime PM support for DPMS

[Frank de Jong]

Hello,

A regression/bug was introduced by commit 
[0e572fe7383a376992364914694c39aa7fe44c1d] drm/i915: runtime PM support 
for DPMS.
It causes my linux box to emit PATA and NIC errors (PCI bus stops 
working), SATA is unaffected. The system freezes shorty after. Trouble 
starts within 12 hours, but not right away.
Git bisect was used to find the regression/bug. It was initially 
introduced somewhere around kernel v3.15.0-rc8 (code has moved around 
since).


*** for details and logs, please scroll down ***

Hardware details:
- MSI MS-7732/PH61A-P35 (MS-7732), BIOS V2.4 09/19/2014
- Sandy Bridge Intel(R) Pentium(R) CPU G620
- 8 GiB RAM
- CRT monitor without EDID (not "plug and play") hooked up to the i915 
CRT port

- 1x SSD connected to ASM1062 SATA controller
- 2x HDD connected to Intel SATA controller
- CDROM drive (ata9) and HDD (ata10) connected to Promise PDC20268
- Uncommon hardware configuration (old PCI PATA controller and PCI NIC)

Other:
- Running on LFS 7.1+ x86_64
- DPMS powersave enabled (setterm -powersave powerdown -powerdown 5)
- text based, no X
- Has VM's (QEMU KVM) running on top

Testing revealed:
v3.18.21: NOT OK
v3.17.8 : NOT OK
v3.17.0 : NOT OK
v3.16.7 : OK
v3.16.0 : OK
v3.14.51: OK

As a test, function intel_crtc_update_dpms() in 
v3.18.20/drivers/gpu/drm/i915/intel_display.c was replaced with an older 
revision (see below). The older revision works fine; it bypasses the 
function intel_crtc_control().


So what is going wrong here? Perhaps something to do with the power 
domains, lack of EDID? Or might it just trigger some bug/regression 
hidden deep in the kernel?


I do not have the know-how to fix this. You guys do, ofcourse! :-)


/**
 * Sets the power management mode of the pipe and plane.
 */
void intel_crtc_update_dpms(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_encoder *intel_encoder;
bool enable = false;

for_each_encoder_on_crtc(dev, crtc, intel_encoder)
enable |= intel_encoder->connectors_active;

if (enable)
dev_priv->display.crtc_enable(crtc);
else
dev_priv->display.crtc_disable(crtc);

intel_crtc_update_sarea(crtc, enable);
}


# /proc/cmdline
# noirqdebug: "ASM1083/1085 PCIe to PCI Bridge" has hardware issues, 
skips a IRQ beat now and then
root=LABEL=ROOTFS selinux=0 video=800x600-32@72 
acpi_enforce_resources=lax thermal.off=1 noirqdebug



# /proc/interrupts
  0: 14  0   IO-APIC-edge  timer
  1: 12  0   IO-APIC-edge  i8042
  4:  57380  0   IO-APIC-edge  serial
  5:  0  0   IO-APIC-edge  parport0
  8:119  0   IO-APIC-edge  rtc0
  9:  3  0   IO-APIC-fasteoi   acpi
 12:147  0   IO-APIC-edge  i8042
 16:746  0   IO-APIC  16-fasteoi   ehci_hcd:usb1
 18:   7305  0   IO-APIC  18-fasteoi   :03:00.0
 19:  64979  0   IO-APIC  19-fasteoi   eth0
 23: 33  0   IO-APIC  23-fasteoi   ehci_hcd:usb3
 24:762  0   PCI-MSI-edge  :00:1f.2
 25:  12926  0   PCI-MSI-edge  :06:00.0
 26:  16017  0   PCI-MSI-edge  eth1
 27:  0  0   PCI-MSI-edge  xhci_hcd
 28:  0  0   PCI-MSI-edge  xhci_hcd
 29:  0  0   PCI-MSI-edge  xhci_hcd
 30:517  0   PCI-MSI-edge  snd_hda_intel
 31:  7  0   PCI-MSI-edge  i915
NMI:  0  0   Non-maskable interrupts
LOC:1024537 205875   Local timer interrupts
SPU:  0  0   Spurious interrupts
PMI:  0  0   Performance monitoring interrupts
IWI:  0  0   IRQ work interrupts
RTR:  1  0   APIC ICR read retries
RES:  17909  21506   Rescheduling interrupts
CAL:   7297   7219   Function call interrupts
TLB:346209   TLB shootdowns
TRM:  0  0   Thermal event interrupts
THR:  0  0   Threshold APIC interrupts
MCE:  0  0   Machine check exceptions
MCP: 11 11   Machine check polls
ERR:  0
MIS:  0


# lspci
00:00.0 Host bridge: Intel Corporation 2nd Generation Core Processor 
Family DRAM Controller (rev 09)
00:02.0 VGA compatible controller: Intel Corporation 2nd Generation Core 
Processor Family Integrated Graphics Controller (rev 09)
00:16.0 Communication controller: Intel Corporation 6 Series/C200 Series 
Chipset Family MEI Controller #1 (rev 04)
00:1a.0 USB controller: Intel Corporation 6 Series/C200 Series Chipset 
Family USB Enhanced Host Controller #2 (rev 05)
00:1b.0 Audio device: Intel Corporation 6 Series/C200 Series Chipset 
Family High Definition Audio Controller (rev 05)
00:1c.0 PCI bridge: Intel Corporation 6 Series/C200 Series Chipset 

Re: [Intel-gfx] [PATCH] drm/i915: Clean up intel_plane->plane usage

[Ville Syrjälä]

On Thu, Sep 17, 2015 at 06:55:21PM -0700, Matt Roper wrote:
> intel_plane->plane has inconsistent meanings across the driver:
>  * For primary planes, intel_plane->plane is usually the pipe number
>(except for old platforms where it had to be swapped for FBC
>reasons).
>  * For sprite planes, intel_plane->plane represents the sprite index for
>the specific CRTC the sprite belongs to (0, 1, 2, ...)
>  * For cursor planes, intel_plane->plane is again the pipe number,
>but without the FBC swapping on old platforms.
> 
> This overloading of the field can be quite confusing and easily leads to
> bugs due to differences in how the hardware actually gets programmed
> (e.g., SKL code needs to use p->plane + 1 because the hardware expects
> universal plane ID's that include the primary, whereas VLV code needs to
> use just p->plane because hardware expects a sprite index that does not
> include the primary).
> 
> Let's try to clean up this situation by giving intel_plane->plane a
> consistent meaning across all plane types, and then update all uses
> across driver code to use macros to interpret it properly.  The
> following macros should be used in the code where we previously accessed
> p->plane and will do additional plane type checking to help prevent
> misuse:
>  * I915_UNIVERSAL_NUM(p) --- Universal plane ID (primary = 0, sprites
>start from 1); intended for use in gen9+ code.
>  * I915_I915_PRIMARY_NUM(p) --- Primary plane ID for pre-gen9 platforms;
>determines whether FBC-related swapping is needed or not.
>  * I915_SPRITE_NUM(p) --- Sprite plane ID (first sprite = 0); intended
>for use in pre-gen9 code.
> 
> Cc: Maarten Lankhorst 
> Signed-off-by: Matt Roper 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  | 24 ++--
>  drivers/gpu/drm/i915/intel_display.c | 12 
>  drivers/gpu/drm/i915/intel_pm.c  | 10 +-
>  drivers/gpu/drm/i915/intel_sprite.c  | 13 +++--
>  4 files changed, 34 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3bf8a9b..132fe53 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -131,22 +131,34 @@ enum transcoder {
>  #define transcoder_name(t) ((t) + 'A')
>  
>  /*
> - * This is the maximum (across all platforms) number of planes (primary +
> - * sprites) that can be active at the same time on one pipe.
> - *
> - * This value doesn't count the cursor plane.
> + * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
> + * number of planes per CRTC.  Not all platforms really have this many 
> planes,
> + * which means some arrays of size I915_MAX_PLANES may have unused entries
> + * between the topmost sprite plane and the cursor plane.
>   */
> -#define I915_MAX_PLANES  4
> -
>  enum plane {
>   PLANE_A = 0,
> + PLANE_PRIMARY = PLANE_A,
>   PLANE_B,
>   PLANE_C,
> + PLANE_CURSOR,
> + I915_MAX_PLANES,
>  };

If we're really going to redefine this as a per-pipe thing, then I
think we'd need to rename it. A,B,C have a definite meaning on most of
our hardware, so using it for something else is confusing.

I know that looking for enum plane in the code probably won't give you
a lot of hits, but that's just because we suck and usually use int or
something. I have a patch series in a branch somewhere to clean that
stuff up, but I don't think I posted it to the list so far.

I think it would be better to have a separate per-pipe plane enum.
enum plane_id or something? And maybe store it as plane->id.

>  #define plane_name(p) ((p) + 'A')
>  
>  #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 
> 'A')
>  
> +#define I915_UNIVERSAL_NUM(p) ( \
> + WARN_ON(p->base.type == DRM_PLANE_TYPE_CURSOR), \

I don't think that'll fly with SKL. The cursor is just another universal
plane, or well, will be. I think the patch to do that change got stuck
in review or something.

I guess that should be easily fixable by tossing in a !IS_SKL&& once
that patch lands.

> + p->plane)
> +#define I915_PRIMARY_NUM(p) ( \
> + WARN_ON(p->base.type != DRM_PLANE_TYPE_PRIMARY), \
> + (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) ? \
> +   !p->pipe : p->pipe)

I'm not sure we want to do this swapping here.

Maybe we'll just want a some kind of
enum plane plane_id_to_plane(crtc, enum plane_id) function.
Or we could just store the enum plane alongside the plane_id in the
plane, and make it clear that it should only be used by pre-SKL
platforms. In theory we could limit it to pre-gen4, or just gmch, but
I think we probably want to share a bunch of the primary plane code
all the way up to BDW, so allowing it's use there seems sane to me.

> +#define I915_SPRITE_NUM(p) ( \
> + WARN_ON(p->base.type != DRM_PLANE_TYPE_OVERLAY), \
> + p->plane - 1)
> +
>  enum port {
>   

[Intel-gfx] [PATCH 1/1] drm/i915/bxt: Set time interval unit to 0.833us

[Sagar Arun Kamble]

From: Akash Goel 

Signed-off-by: Ankitprasad Sharma 
Signed-off-by: Akash Goel 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_reg.h | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 67bf205..6b1998c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2802,8 +2802,11 @@ enum skl_disp_power_wells {
 
 #define INTERVAL_1_28_US(us)   (((us) * 100) >> 7)
 #define INTERVAL_1_33_US(us)   (((us) * 3)   >> 2)
+#define INTERVAL_0_833_US(us)  (((us) * 6) / 5)
 #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
-   INTERVAL_1_33_US(us) : \
+   (IS_BROXTON(dev_priv) ? \
+   INTERVAL_0_833_US(us) : \
+   INTERVAL_1_33_US(us)) : \
INTERVAL_1_28_US(us))
 
 /*
-- 
1.9.1

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Re: [Intel-gfx] [RFC][PATCH 43/43] WIP: drm/i915: Type safe register read/write

[Ville Syrjälä]

On Fri, Sep 18, 2015 at 07:12:30PM +0100, Chris Wilson wrote:
> On Fri, Sep 18, 2015 at 08:43:27PM +0300, Ville Syrjälä wrote:
> > On Fri, Sep 18, 2015 at 06:33:38PM +0100, Chris Wilson wrote:
> > > On Fri, Sep 18, 2015 at 08:03:56PM +0300, ville.syrj...@linux.intel.com 
> > > wrote:
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 140076d..0589aba 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -25,16 +25,28 @@
> > > >  #ifndef _I915_REG_H_
> > > >  #define _I915_REG_H_
> > > >  
> > > > +struct i915_reg {
> > > > +   uint32_t reg;
> > > > +};
> > > 
> > > Fundamental objection averted. Maybe even typedef it to hide the struct,
> > > ignornace is bliss.  i915_reg_t reg; looks reasonable in this instance.
> > 
> > Yeah typedef would make it less ugly. Maybe i915_mmio_reg_t or something,
> > so we can add other register types?
> 
> Yes. Separating out the display/mmio/gpio registers would be nice, that
> should spawn a few functions that can check we don't add the wrong base
> (if any such remain!). It would mean we end up with a construct like
> union i915_reg {
>   i915_gt_reg_t gt;
>   i915_mmio_reg_t mmio;
>   i915_gpio_reg_t gpio;
>   i915_display_reg_t display;
> };
> and typecasting when we try to write a register. Or maybe we just have
> more typesafe helpers that call the private vfuncs. It may even be a net
> reduction in code size, since we move all the addition of display
> offsets into a central location. However, it looks like it may just be
> an inconvenient mess.

I don't think I'll go as far as having different classes of mmio regs.

I was thinking more about sideband stuff. We had at least one case on
CHV where we read the register from a totally wrong sideband port.

I was somewhat thinking of VGA registers too since those are a bit
special (either mmio or port io depending on the gen). Though we have so
little interaction with them that I'm not sure it's worth the effort.

> 
> > > The downside with this patch is that we have a lot of places that cares
> > > about the reg.reg,
> > 
> > That is a bit annoying, yes. I think most of those are in the ring code
> > where we emit LRIs. I suppose we could add a special version of ring_emit
> > that takes the struct and thus hides the reg.reg part from the calling
> > code?
> 
> Right, even just adding an inline can be down in a preceding patch and
> so reduce churn here and extends the typesafety argument for LRI as
> well (and SRM).
> 
> I half considered a function to return the raw offset from a struct i915_reg,
> that is only marginally better than adding .reg (but only in the case
> where we end up with a few very similar i915_reg structs). But it
> doesn't actually reduce the churn... unless you add a stub in a previous
> patch such that any location that wants to use the register offset as a
> value is converted first.
>  
> > > and even more where we make up reg on the fly, so it
> > > looks like we are just doing I915_WRITE(_REG(old_u32), x) i.e. more or
> > > less subverting the extra safety, and we would still want something like
> > > 
> > >   i915_write16(reg) { WARN_ON(reg & 1); }
> > >   i915_write32(reg) { WARN_ON(reg & 3); }
> > > 
> > > to catch the class of bug where we create an invalid reg address.
> > 
> > I've killed off almost all of the "make up regs on the fly" in the prep
> > work. I think what was left were vgpu and the 2x32 register read ioctl.
> > I don't recall any other significant places off the top of my head.
> 
> Never underestimate the cunning of the lazy programmer. Not that I want
> to add any more instructions to register access. Going forward, I guess
> the rule is to scrutinize _REG() etc very careful and limit them to headers?

Yeah I wanted to undef _REG() at the end of the header so it can't be
abused, but someone had gone and added register defines to other files
too so I left out the undef for now. And I guess I even abused it myself
in one place myself. So there are still some things to clean up.

-- 
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Re: [Intel-gfx] [PATCH 35/43] drm/i915: Move __raw_i915_read8() & co. into i915_drv.h

[Chris Wilson]

On Fri, Sep 18, 2015 at 09:23:11PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 18, 2015 at 06:42:17PM +0100, Chris Wilson wrote:
> > On Fri, Sep 18, 2015 at 08:03:48PM +0300, ville.syrj...@linux.intel.com 
> > wrote:
> > > From: Ville Syrjälä 
> > > 
> > > We have a few users of the raw register acces functions outside
> > > intel_uncore.c, so let's just move the functions into intel_drv.h.
> > 
> > I would rather see those external users converted to
> > I915_READ_FW/I915_WRITE_FW etc. You will then, no doubt, want to convert
> > those _FW macro definitions over to the uncore set.
> > 
> > Also due to how we write and post our accesses, the raw functions can be
> > the _relaxed variants.
> 
> Hmm. I think the only difference with the relaxed vs. not would be
> potential compiler reordering of memory accesses vs. mmio. So if we
> start using the relaxed versions we may need to start sprinkling
> barriers around.

Yes. We have been working under that assumption (weak ordering of writes),
or at least I hope we all have been...
-Chris

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Re: [Intel-gfx] [PATCH 35/43] drm/i915: Move __raw_i915_read8() & co. into i915_drv.h

[Ville Syrjälä]

On Fri, Sep 18, 2015 at 07:44:34PM +0100, Chris Wilson wrote:
> On Fri, Sep 18, 2015 at 09:37:38PM +0300, Ville Syrjälä wrote:
> > On Fri, Sep 18, 2015 at 07:33:50PM +0100, Chris Wilson wrote:
> > > On Fri, Sep 18, 2015 at 09:23:11PM +0300, Ville Syrjälä wrote:
> > > > On Fri, Sep 18, 2015 at 06:42:17PM +0100, Chris Wilson wrote:
> > > > > On Fri, Sep 18, 2015 at 08:03:48PM +0300, 
> > > > > ville.syrj...@linux.intel.com wrote:
> > > > > > From: Ville Syrjälä 
> > > > > > 
> > > > > > We have a few users of the raw register acces functions outside
> > > > > > intel_uncore.c, so let's just move the functions into intel_drv.h.
> > > > > 
> > > > > I would rather see those external users converted to
> > > > > I915_READ_FW/I915_WRITE_FW etc. You will then, no doubt, want to 
> > > > > convert
> > > > > those _FW macro definitions over to the uncore set.
> > > > > 
> > > > > Also due to how we write and post our accesses, the raw functions can 
> > > > > be
> > > > > the _relaxed variants.
> > > > 
> > > > Hmm. I think the only difference with the relaxed vs. not would be
> > > > potential compiler reordering of memory accesses vs. mmio. So if we
> > > > start using the relaxed versions we may need to start sprinkling
> > > > barriers around.
> > > 
> > > Yes. We have been working under that assumption (weak ordering of writes),
> > > or at least I hope we all have been...
> > 
> > Well, looking at the irq code that uses the _FW, what would prevent the
> > compiler from eg. reorder the seqno read to happen before the IIR read?
> > Well in practice function calls are involved, so there's a barrier
> > there, but say we would want to read the seqno straight from the irq
> > handler...
> 
> What seqno read? We definitely don't want to be doing those expensive
> reads from an irq handler...

Yeah I guess that was a crappy example. Trying to think of a better one,
I figure execlist status could be read from memory, but apparently
that's just mmio. I guess the context update + ELSP write is something
we do from the irq handler, but there are plenty of barriers between
those two it seems. Maybe there's no good example here.

> 
> Anyway, I thought we had strongly ordered reads on x64/x32?

The cpu won't reoder reads vs. reads, or writes vs. writes for that
matter if you ignore the nt stuff and whatnot. But AFAIU the whole
point of _relaxed() on x86 is that it allows the compiler to reoder
memory vs. mmio any which way it wants.

-- 
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Re: [Intel-gfx] [PATCH 35/43] drm/i915: Move __raw_i915_read8() & co. into i915_drv.h

[Ville Syrjälä]

On Fri, Sep 18, 2015 at 06:42:17PM +0100, Chris Wilson wrote:
> On Fri, Sep 18, 2015 at 08:03:48PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä 
> > 
> > We have a few users of the raw register acces functions outside
> > intel_uncore.c, so let's just move the functions into intel_drv.h.
> 
> I would rather see those external users converted to
> I915_READ_FW/I915_WRITE_FW etc. You will then, no doubt, want to convert
> those _FW macro definitions over to the uncore set.
> 
> Also due to how we write and post our accesses, the raw functions can be
> the _relaxed variants.

Hmm. I think the only difference with the relaxed vs. not would be
potential compiler reordering of memory accesses vs. mmio. So if we
start using the relaxed versions we may need to start sprinkling
barriers around.

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 35/43] drm/i915: Move __raw_i915_read8() & co. into i915_drv.h

[Ville Syrjälä]

On Fri, Sep 18, 2015 at 07:33:50PM +0100, Chris Wilson wrote:
> On Fri, Sep 18, 2015 at 09:23:11PM +0300, Ville Syrjälä wrote:
> > On Fri, Sep 18, 2015 at 06:42:17PM +0100, Chris Wilson wrote:
> > > On Fri, Sep 18, 2015 at 08:03:48PM +0300, ville.syrj...@linux.intel.com 
> > > wrote:
> > > > From: Ville Syrjälä 
> > > > 
> > > > We have a few users of the raw register acces functions outside
> > > > intel_uncore.c, so let's just move the functions into intel_drv.h.
> > > 
> > > I would rather see those external users converted to
> > > I915_READ_FW/I915_WRITE_FW etc. You will then, no doubt, want to convert
> > > those _FW macro definitions over to the uncore set.
> > > 
> > > Also due to how we write and post our accesses, the raw functions can be
> > > the _relaxed variants.
> > 
> > Hmm. I think the only difference with the relaxed vs. not would be
> > potential compiler reordering of memory accesses vs. mmio. So if we
> > start using the relaxed versions we may need to start sprinkling
> > barriers around.
> 
> Yes. We have been working under that assumption (weak ordering of writes),
> or at least I hope we all have been...

Well, looking at the irq code that uses the _FW, what would prevent the
compiler from eg. reorder the seqno read to happen before the IIR read?
Well in practice function calls are involved, so there's a barrier
there, but say we would want to read the seqno straight from the irq
handler...

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[Intel-gfx] [PATCH] drm/i915: Skip fence installation for objects with rotated views (v2)

[Vivek Kasireddy]

v2:
Look at the object's map_and_fenceable flag to determine whether to
install a fence or not (Chris).

v1:
While pinning a fb object to the display plane, only install a fence
if the object is using a normal view. This corresponds with the
behavior found in i915_gem_object_do_pin() where the fencability
criteria is determined only for objects with normal views.

Cc: Chris Wilson 
Cc: Tvrtko Ursulin 
Signed-off-by: Vivek Kasireddy 
---
 drivers/gpu/drm/i915/intel_display.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 52fb3f2..108c000 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2357,7 +2357,8 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
 * framebuffer compression.  For simplicity, we always install
 * a fence as the cost is not that onerous.
 */
-   ret = i915_gem_object_get_fence(obj);
+   if (obj->map_and_fenceable)
+   ret = i915_gem_object_get_fence(obj);
if (ret == -EDEADLK) {
/*
 * -EDEADLK means there are no free fences
-- 
2.4.3

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Re: [Intel-gfx] [PATCH] drm/i915: Skip fence installation for objects with rotated views

[Vivek Kasireddy]

On Thu, 17 Sep 2015 11:25:18 +0100
Tvrtko Ursulin  wrote:

> 
> On 09/16/2015 06:36 PM, Vivek Kasireddy wrote:
> > On Wed, 16 Sep 2015 09:03:33 +0100
> > Chris Wilson  wrote:
> >
> >> On Tue, Sep 15, 2015 at 07:05:12PM -0700, Vivek Kasireddy wrote:
> >>> While pinning a fb object to the display plane, only install a
> >>> fence if the object is using a normal view. This corresponds with
> >>> the behavior found in i915_gem_object_do_pin() where the
> >>> fencability criteria is determined only for objects with normal
> >>> views.
> >>>
> >>> Suggested-by: Tvrtko Ursulin 
> >>> Cc: Chris Wilson 
> >>> Cc: Tvrtko Ursulin 
> >>> Signed-off-by: Vivek Kasireddy 
> >>> ---
> >>>   drivers/gpu/drm/i915/intel_display.c | 3 ++-
> >>>   1 file changed, 2 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/intel_display.c
> >>> b/drivers/gpu/drm/i915/intel_display.c index 52fb3f2..8b3e943
> >>> 100644 --- a/drivers/gpu/drm/i915/intel_display.c
> >>> +++ b/drivers/gpu/drm/i915/intel_display.c
> >>> @@ -2357,7 +2357,8 @@ intel_pin_and_fence_fb_obj(struct drm_plane
> >>> *plane,
> >>>* framebuffer compression.  For simplicity, we always
> >>> install
> >>>* a fence as the cost is not that onerous.
> >>>*/
> >>> - ret = i915_gem_object_get_fence(obj);
> >>> + ret = view.type == I915_GGTT_VIEW_NORMAL ?
> >>> + i915_gem_object_get_fence(obj) :
> >>> 0;
> >>
> >> ret = 0;
> >> if (vma->map_and_fenceable)
> >>ret = i915_gem_object_get_fence(obj);
> >>
> >> is how I wrote it in my patch. One day that will become
> >> i915_vma_get_fence().
> >> -Chris
> > Hi Chris,
> >
> > Looks like your solution to this problem -- and potentially others
> > -- is better and more comprehensive. When do you plan on sending
> > your patch out to the mailing list?
> 
> For a quick fix maybe just respin this patch to use 
> obj->map_and_fenceable criteria as Chris suggested?
> 
> You should also add a test case for this into igt/kms_addfb_basic.
Hi Tvrtko,
I'll send out a patch soon that will serve as as stop-gap measure until
Chris revamps that part of the code. As far as the igt test case is
concerned, I'll do that in the next few days.


Thanks,
Vivek

> 
> Regards,
> 
> Tvrtko

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Re: [Intel-gfx] [PATCH i-g-t] gem_ppgtt: Test VMA leak on context destruction

[Thomas Wood]

On 11 September 2015 at 15:31, Tvrtko Ursulin
 wrote:
> From: Tvrtko Ursulin 
>
> Test that VMAs associated with a context are cleaned up when
> contexts are destroyed.
>
> In practice this emulates the leak seen between fbcon and X server.
> Every time the X server exits we gain one VMA on the fbcon frame
> buffer object as externally visible via for example
> /sys/kernel/debug/dri/0/i915_gem_gtt.
>
> Signed-off-by: Tvrtko Ursulin 
> ---
>  tests/gem_ppgtt.c | 80 
> +++
>  1 file changed, 80 insertions(+)
>
> diff --git a/tests/gem_ppgtt.c b/tests/gem_ppgtt.c
> index 4f6df063214a..363f9d701585 100644
> --- a/tests/gem_ppgtt.c
> +++ b/tests/gem_ppgtt.c
> @@ -265,6 +265,83 @@ static void flink_and_close(void)
> close(fd2);
>  }
>
> +static int grep_name(char *match, int to_match)

This could be added to igt_debugfs.c, as it might be useful for other tests.


> +{
> +   int fdd, ret, matched;
> +
> +   fdd = open("/sys/kernel/debug/dri/0/i915_gem_gtt", O_RDONLY);

igt_debugfs_open would be more robust here, as it checks various
locations for the debugfs and also attempts to mount it if it can't be
found.


> +   igt_assert(fdd >= 0);
> +
> +   matched = 0;
> +   do {
> +   char ch;
> +
> +   ret = read(fdd, , 1);
> +   if (ret == 0)
> +   break;
> +   igt_assert(ret == 1);
> +
> +   if (ch == match[matched])
> +   matched++;
> +   else
> +   matched = 0;
> +   } while (matched < to_match);

igt_debugfs_fopen is also available, which would allow the use of
getline and strstr here instead, as a slightly simpler implementation.


> +
> +   close(fdd);
> +
> +   return matched;
> +}
> +
> +static void flink_and_exit(void)
> +{
> +   uint32_t fd, fd2;
> +   uint32_t bo, flinked_bo, name;
> +   char match[100];
> +   int matched, to_match;
> +   int retry = 0;
> +   const int retries = 50;
> +
> +   fd = drm_open_any();
> +   igt_require(uses_full_ppgtt(fd));
> +
> +   bo = gem_create(fd, 4096);
> +   name = gem_flink(fd, bo);
> +
> +   to_match  = snprintf(match, sizeof(match), "(name: %u)", name);
> +   igt_assert(to_match < sizeof(match));
> +
> +   fd2 = drm_open_any();
> +
> +   flinked_bo = gem_open(fd2, name);
> +   exec_and_get_offset(fd2, flinked_bo);
> +   gem_sync(fd2, flinked_bo);
> +
> +   /* Verify looking for string works OK. */
> +   matched = grep_name(match, to_match);
> +   igt_assert_eq(matched, to_match);
> +
> +   gem_close(fd2, flinked_bo);
> +
> +   /* Close the context. */
> +   close(fd2);
> +
> +retry:
> +   /* Give cleanup some time to run. */
> +   usleep(10);
> +
> +   /* The flinked bo VMA should have been cleared now, so list of VMAs
> +* in debugfs should not contain the one for the imported object.
> +*/
> +   matched = grep_name(match, to_match);
> +   if (matched >= to_match && retry++ < retries)
> +   goto retry;
> +
> +   igt_assert_lt(matched, to_match);
> +
> +   gem_close(fd, bo);
> +   close(fd);
> +}
> +
>  #define N_CHILD 8
>  int main(int argc, char **argv)
>  {
> @@ -297,5 +374,8 @@ int main(int argc, char **argv)
> igt_subtest("flink-and-close-vma-leak")
> flink_and_close();
>
> +   igt_subtest("flink-and-exit-vma-leak")
> +   flink_and_exit();
> +
> igt_exit();
>  }
> --
> 2.5.1
>
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Re: [Intel-gfx] [PATCH] drm/i915: Don't leak VBT mode data

[Jani Nikula]

On Tue, 15 Sep 2015, Matt Roper  wrote:
> We allocate memory for LVDS modes while parsing the VBT at startup, but
> never free this memory when the driver is unloaded, causing a small
> leak.
>
> Signed-off-by: Matt Roper 

Pushed to drm-intel-next-queued, thanks for the patch.

BR,
Jani.



> ---
>  drivers/gpu/drm/i915/i915_dma.c | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 066a0ef..c069550 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -1137,6 +1137,10 @@ int i915_driver_unload(struct drm_device *dev)
>   dev_priv->vbt.child_dev = NULL;
>   dev_priv->vbt.child_dev_num = 0;
>   }
> + kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
> + dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
> + kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
> + dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
>  
>   vga_switcheroo_unregister_client(dev->pdev);
>   vga_client_register(dev->pdev, NULL, NULL, NULL);
> -- 
> 2.1.4
>
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Re: [Intel-gfx] [PATCH] drm/i915: fix kernel-doc warnings in intel_audio.c

[Jani Nikula]

On Tue, 15 Sep 2015, Geliang Tang  wrote:
> Fix the following 'make htmldocs' warnings:
>
>   .//drivers/gpu/drm/i915/intel_audio.c:439: warning: No description found 
> for parameter 'intel_encoder'
>   .//drivers/gpu/drm/i915/intel_audio.c:439: warning: Excess function 
> parameter 'encoder' description in 'intel_audio_codec_disable'
>   .//drivers/gpu/drm/i915/intel_audio.c:439: warning: No description found 
> for parameter 'intel_encoder'
>   .//drivers/gpu/drm/i915/intel_audio.c:439: warning: Excess function 
> parameter 'encoder' description in 'intel_audio_codec_disable'
>
> Signed-off-by: Geliang Tang 

Pushed to drm-intel-fixes, thanks for the patch.

BR,
Jani.


> ---
>  drivers/gpu/drm/i915/intel_audio.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_audio.c 
> b/drivers/gpu/drm/i915/intel_audio.c
> index f73de0b..e35997e 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -430,7 +430,7 @@ void intel_audio_codec_enable(struct intel_encoder 
> *intel_encoder)
>  
>  /**
>   * intel_audio_codec_disable - Disable the audio codec for HD audio
> - * @encoder: encoder on which to disable audio
> + * @intel_encoder: encoder on which to disable audio
>   *
>   * The disable sequences must be performed before disabling the transcoder or
>   * port.
> -- 
> 1.9.1
>
>

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Re: [Intel-gfx] [PATCH] drm/i915/bxt: Fix wrongly placed ')' in I915_READ()

[Jani Nikula]

On Thu, 17 Sep 2015, Imre Deak  wrote:
> On to, 2015-09-17 at 14:20 +0100, Damien Lespiau wrote:
>> Not the first time! not the last time?
>> 
>> There is a possibility to use gcc 5's -Wbool-compare to try and compare
>> (reg) in those macros to a constant and gcc will warn that the
>> comparison between a boolean expression and a constant is always either
>> true or false. Maybe.
>> 
>> Cc: Imre Deak 
>> Signed-off-by: Damien Lespiau 
>
> E. Thanks for catching it:
> Reviewed-by: Imre Deak 

Pushed to drm-intel-next-queued, thanks for the patch and review.

BR,
Jani.


>
>> ---
>>  drivers/gpu/drm/i915/intel_ddi.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
>> b/drivers/gpu/drm/i915/intel_ddi.c
>> index 4823184..5b600bf 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -2882,7 +2882,7 @@ static bool bxt_ddi_pll_get_hw_state(struct 
>> drm_i915_private *dev_priv,
>>   * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
>>   */
>>  hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
>> -if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12))
>> +if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
>>  DRM_DEBUG_DRIVER("lane stagger config different for lane 01 
>> (%08x) and 23 (%08x)\n",
>>   hw_state->pcsdw12,
>>   I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
>
>
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Re: [Intel-gfx] [PATCH] drm/i915: cleanup pipe_update trace functions with new crtc debug info v3

[Jani Nikula]

On Fri, 18 Sep 2015, Ville Syrjälä  wrote:
> On Thu, Sep 17, 2015 at 08:08:32AM -0700, Jesse Barnes wrote:
>> Use the new debug info in the intel_crtc struct in these functions
>> rather than passing them as args.
>> 
>> v2: move min/max assignment back above first trace call (Ville)
>> use scanline from crtc->debug rather than fetching a new one (Ville)
>> v3: fix up trace_i915_pipe_update_end, needs end scanline (Ville)
>> 
>> Requested-by: Ville Syrjälä 
>> Signed-off-by: Jesse Barnes 
>
> Reviewed-by: Ville Syrjälä 

Both pushed to drm-intel-next-queued, thanks for the patches and review.

BR,
Jani.


>
>> ---
>>  drivers/gpu/drm/i915/i915_trace.h   | 26 +-
>>  drivers/gpu/drm/i915/intel_sprite.c | 11 +--
>>  2 files changed, 18 insertions(+), 19 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_trace.h 
>> b/drivers/gpu/drm/i915/i915_trace.h
>> index e6b5c74..d0993bc 100644
>> --- a/drivers/gpu/drm/i915/i915_trace.h
>> +++ b/drivers/gpu/drm/i915/i915_trace.h
>> @@ -17,8 +17,8 @@
>>  /* pipe updates */
>>  
>>  TRACE_EVENT(i915_pipe_update_start,
>> -TP_PROTO(struct intel_crtc *crtc, u32 min, u32 max),
>> -TP_ARGS(crtc, min, max),
>> +TP_PROTO(struct intel_crtc *crtc),
>> +TP_ARGS(crtc),
>>  
>>  TP_STRUCT__entry(
>>   __field(enum pipe, pipe)
>> @@ -33,8 +33,8 @@ TRACE_EVENT(i915_pipe_update_start,
>> __entry->frame = 
>> crtc->base.dev->driver->get_vblank_counter(crtc->base.dev,
>>  
>>crtc->pipe);
>> __entry->scanline = intel_get_crtc_scanline(crtc);
>> -   __entry->min = min;
>> -   __entry->max = max;
>> +   __entry->min = crtc->debug.min_vbl;
>> +   __entry->max = crtc->debug.max_vbl;
>> ),
>>  
>>  TP_printk("pipe %c, frame=%u, scanline=%u, min=%u, max=%u",
>> @@ -43,8 +43,8 @@ TRACE_EVENT(i915_pipe_update_start,
>>  );
>>  
>>  TRACE_EVENT(i915_pipe_update_vblank_evaded,
>> -TP_PROTO(struct intel_crtc *crtc, u32 min, u32 max, u32 frame),
>> -TP_ARGS(crtc, min, max, frame),
>> +TP_PROTO(struct intel_crtc *crtc),
>> +TP_ARGS(crtc),
>>  
>>  TP_STRUCT__entry(
>>   __field(enum pipe, pipe)
>> @@ -56,10 +56,10 @@ TRACE_EVENT(i915_pipe_update_vblank_evaded,
>>  
>>  TP_fast_assign(
>> __entry->pipe = crtc->pipe;
>> -   __entry->frame = frame;
>> -   __entry->scanline = intel_get_crtc_scanline(crtc);
>> -   __entry->min = min;
>> -   __entry->max = max;
>> +   __entry->frame = crtc->debug.start_vbl_count;
>> +   __entry->scanline = crtc->debug.scanline_start;
>> +   __entry->min = crtc->debug.min_vbl;
>> +   __entry->max = crtc->debug.max_vbl;
>> ),
>>  
>>  TP_printk("pipe %c, frame=%u, scanline=%u, min=%u, max=%u",
>> @@ -68,8 +68,8 @@ TRACE_EVENT(i915_pipe_update_vblank_evaded,
>>  );
>>  
>>  TRACE_EVENT(i915_pipe_update_end,
>> -TP_PROTO(struct intel_crtc *crtc, u32 frame),
>> -TP_ARGS(crtc, frame),
>> +TP_PROTO(struct intel_crtc *crtc, u32 frame, int scanline_end),
>> +TP_ARGS(crtc, frame, scanline_end),
>>  
>>  TP_STRUCT__entry(
>>   __field(enum pipe, pipe)
>> @@ -80,7 +80,7 @@ TRACE_EVENT(i915_pipe_update_end,
>>  TP_fast_assign(
>> __entry->pipe = crtc->pipe;
>> __entry->frame = frame;
>> -   __entry->scanline = intel_get_crtc_scanline(crtc);
>> +   __entry->scanline = scanline_end;
>> ),
>>  
>>  TP_printk("pipe %c, frame=%u, scanline=%u",
>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
>> b/drivers/gpu/drm/i915/intel_sprite.c
>> index 7de121d..79f7cc2 100644
>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> @@ -102,7 +102,9 @@ void intel_pipe_update_start(struct intel_crtc *crtc)
>>  if (WARN_ON(drm_crtc_vblank_get(>base)))
>>  return;
>>  
>> -trace_i915_pipe_update_start(crtc, min, max);
>> +crtc->debug.min_vbl = min;
>> +crtc->debug.max_vbl = max;
>> +trace_i915_pipe_update_start(crtc);
>>  
>>  for (;;) {
>>  /*
>> @@ -133,15 +135,12 @@ void intel_pipe_update_start(struct intel_crtc *crtc)
>>  
>>  drm_crtc_vblank_put(>base);
>>  
>> -crtc->debug.min_vbl = min;
>> -crtc->debug.max_vbl = max;
>>  crtc->debug.scanline_start = scanline;
>> 

Re: [Intel-gfx] [PATCH] drm/i915: fix kernel-doc warnings in i915_gem.c

[Jani Nikula]

On Tue, 15 Sep 2015, Geliang Tang  wrote:
> Fix the following 'make htmldocs' warnings:
>
>   .//drivers/gpu/drm/i915/i915_gem.c:1729: warning: No description found for 
> parameter 'vma'
>   .//drivers/gpu/drm/i915/i915_gem.c:1729: warning: No description found for 
> parameter 'vmf'
>
>   .//drivers/gpu/drm/i915/i915_gem.c:4962: warning: No description found for 
> parameter 'old'
>   .//drivers/gpu/drm/i915/i915_gem.c:4962: warning: No description found for 
> parameter 'new'
>   .//drivers/gpu/drm/i915/i915_gem.c:4962: warning: No description found for 
> parameter 'frontbuffer_bits'
>
> Signed-off-by: Geliang Tang 

Pushed to drm-intel-next-queued, thanks for the patch.

BR,
Jani.


> ---
>  drivers/gpu/drm/i915/i915_gem.c | 10 +-
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 4d631a9..a96f97c 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1711,8 +1711,8 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
>  
>  /**
>   * i915_gem_fault - fault a page into the GTT
> - * vma: VMA in question
> - * vmf: fault info
> + * @vma: VMA in question
> + * @vmf: fault info
>   *
>   * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
>   * from userspace.  The fault handler takes care of binding the object to
> @@ -4949,9 +4949,9 @@ int i915_gem_open(struct drm_device *dev, struct 
> drm_file *file)
>  
>  /**
>   * i915_gem_track_fb - update frontbuffer tracking
> - * old: current GEM buffer for the frontbuffer slots
> - * new: new GEM buffer for the frontbuffer slots
> - * frontbuffer_bits: bitmask of frontbuffer slots
> + * @old: current GEM buffer for the frontbuffer slots
> + * @new: new GEM buffer for the frontbuffer slots
> + * @frontbuffer_bits: bitmask of frontbuffer slots
>   *
>   * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing 
> them
>   * from @old and setting them in @new. Both @old and @new can be NULL.
> -- 
> 1.9.1
>
>

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Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/bxt: work around HW context corruption due to coherency problem

[Imre Deak]

On Fri, 2015-09-18 at 10:02 +0100, Chris Wilson wrote:
> On Thu, Sep 17, 2015 at 07:17:44PM +0300, Imre Deak wrote:
> > The execlist context object is mapped with a CPU/GPU coherent mapping
> > everywhere, but on BXT A stepping due to a HW issue the coherency is not
> > guaranteed. To work around this flush the context object after pinning
> > it (to flush cache lines left by the context initialization/read-back
> > from backing storage) and mark it as uncached so later updates during
> > context switching will be coherent.
> > 
> > I noticed this problem via a GPU hang, where IPEHR pointed to an invalid
> > opcode value. I couldn't find this value on the ring but looking at the
> > contents of the active context object it turned out to be a parameter
> > dword of a bigger command there. The original command opcode itself
> > was zeroed out, based on the above I assume due to a CPU writeback of
> > the corresponding cacheline. When restoring the context the GPU would
> > jump over the zeroed out opcode and hang when trying to execute the
> > above parameter dword.
> > 
> > I could easily reproduce this by running igt/gem_render_copy_redux and
> > gem_tiled_blits/basic in parallel, but I guess it could be triggered by
> > anything involving frequent switches between two separate contexts. With
> > this workaround I couldn't reproduce the problem.
> > 
> > v2:
> > - instead of clflushing after updating the tail and PDP values during
> >   context switching, map the corresponding page as uncached to avoid a
> >   race between CPU and GPU, both updating the same cacheline at the same
> >   time (Ville)
> 
> No. Changing PAT involves a stop_machine() and is severely detrimental
> to performance (context creation overhead does impact userspace).

Hm, where on that path is stop_machine(), I haven't found it. I guess
there is an overhead because of the TLB flush on each CPU, I haven't
benchmarked it. If that's a real issue (atm this is only a w/a for
stepping A) we could have a cache of uncached pages.

> Mapping it as uncached doesn't remove the race anyway.

Please explain, I do believe it does.

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Re: [Intel-gfx] [BXT MIPI PATCH v3 03/14] drm/i915/bxt: Disable DSI PLL for BXT

[Jani Nikula]

On Tue, 01 Sep 2015, Uma Shankar  wrote:
> From: Shashank Sharma 
>
> This patch adds two new functions:
> - disable_dsi_pll.
>   BXT DSI disable sequence and registers are
>   different from previous platforms.
> - intel_disable_dsi_pll
>   wrapper function to re-use the same code for
>   multiple platforms. It checks platform type and
>   calls appropriate core pll disable function.
>
> v2: Fixed Jani's review comments.
>
> v3: Rebased on latest drm-nightly branch.
>
> Signed-off-by: Shashank Sharma 
> Signed-off-by: Uma Shankar 

Reviewed-by: Jani Nikula 

> ---
>  drivers/gpu/drm/i915/intel_dsi.c |2 +-
>  drivers/gpu/drm/i915/intel_dsi.h |2 +-
>  drivers/gpu/drm/i915/intel_dsi_pll.c |   32 +++-
>  3 files changed, 33 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c 
> b/drivers/gpu/drm/i915/intel_dsi.c
> index fb259fb..bac988a 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -553,7 +553,7 @@ static void intel_dsi_clear_device_ready(struct 
> intel_encoder *encoder)
>   usleep_range(2000, 2500);
>   }
>  
> - vlv_disable_dsi_pll(encoder);
> + intel_disable_dsi_pll(encoder);
>  }
>  
>  static void intel_dsi_post_disable(struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h 
> b/drivers/gpu/drm/i915/intel_dsi.h
> index 20cfcf07..759983e 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -122,7 +122,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct 
> drm_encoder *encoder)
>  }
>  
>  extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
> -extern void vlv_disable_dsi_pll(struct intel_encoder *encoder);
> +extern void intel_disable_dsi_pll(struct intel_encoder *encoder);
>  extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
>  
>  struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id);
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c 
> b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 3830a4f..21a2e37 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -267,7 +267,7 @@ static void vlv_enable_dsi_pll(struct intel_encoder 
> *encoder)
>   DRM_DEBUG_KMS("DSI PLL locked\n");
>  }
>  
> -void vlv_disable_dsi_pll(struct intel_encoder *encoder)
> +static void vlv_disable_dsi_pll(struct intel_encoder *encoder)
>  {
>   struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
>   u32 tmp;
> @@ -284,6 +284,26 @@ void vlv_disable_dsi_pll(struct intel_encoder *encoder)
>   mutex_unlock(_priv->sb_lock);
>  }
>  
> +static void bxt_disable_dsi_pll(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> + u32 val;
> +
> + DRM_DEBUG_KMS("\n");
> +
> + val = I915_READ(BXT_DSI_PLL_ENABLE);
> + val &= ~BXT_DSI_PLL_DO_ENABLE;
> + I915_WRITE(BXT_DSI_PLL_ENABLE, val);
> +
> + /*
> +  * PLL lock should deassert within 200us.
> +  * Wait up to 1ms before timing out.
> +  */
> + if (wait_for((I915_READ(BXT_DSI_PLL_ENABLE)
> + & BXT_DSI_PLL_LOCKED) == 0, 1))
> + DRM_ERROR("Timeout waiting for PLL lock deassertion\n");
> +}
> +
>  static void assert_bpp_mismatch(int pixel_format, int pipe_bpp)
>  {
>   int bpp;
> @@ -461,3 +481,13 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder)
>   else if (IS_BROXTON(dev))
>   bxt_enable_dsi_pll(encoder);
>  }
> +
> +void intel_disable_dsi_pll(struct intel_encoder *encoder)
> +{
> + struct drm_device *dev = encoder->base.dev;
> +
> + if (IS_VALLEYVIEW(dev))
> + vlv_disable_dsi_pll(encoder);
> + else if (IS_BROXTON(dev))
> + bxt_disable_dsi_pll(encoder);
> +}
> -- 
> 1.7.9.5
>

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Re: [Intel-gfx] [BXT MIPI PATCH v3 01/14] drm/i915/bxt: Initialize MIPI for BXT

[Jani Nikula]

On Tue, 01 Sep 2015, Uma Shankar  wrote:
> From: Shashank Sharma 
>
> This patch contains following changes:
> 1. Add BXT MIPI display address base.
> 2. Call dsi_init from display_setup function.
>
> v2: Rebased on latest nightly branch
>
> Signed-off-by: Shashank Sharma 
> Signed-off-by: Uma Shankar 

I'm not sure if this should be applied as the first patch or not, but

Reviewed-by: Jani Nikula 

> ---
>  drivers/gpu/drm/i915/i915_reg.h  |1 +
>  drivers/gpu/drm/i915/intel_display.c |3 +++
>  drivers/gpu/drm/i915/intel_dsi.c |2 ++
>  3 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2030f60..621151b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1641,6 +1641,7 @@ enum skl_disp_power_wells {
>  
>  #define VLV_DISPLAY_BASE 0x18
>  #define VLV_MIPI_BASE VLV_DISPLAY_BASE
> +#define BXT_MIPI_BASE 0x6
>  
>  #define VLV_GU_CTL0  (VLV_DISPLAY_BASE + 0x2030)
>  #define VLV_GU_CTL1  (VLV_DISPLAY_BASE + 0x2034)
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 87476ff..b8e0310 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13906,6 +13906,9 @@ static void intel_setup_outputs(struct drm_device 
> *dev)
>* DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
>* detect the ports.
>*/
> + /* Initialize MIPI for BXT */
> + intel_dsi_init(dev);
> +
>   intel_ddi_init(dev, PORT_A);
>   intel_ddi_init(dev, PORT_B);
>   intel_ddi_init(dev, PORT_C);
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c 
> b/drivers/gpu/drm/i915/intel_dsi.c
> index b5a5558..b59b828 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -998,6 +998,8 @@ void intel_dsi_init(struct drm_device *dev)
>  
>   if (IS_VALLEYVIEW(dev)) {
>   dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
> + } else if (IS_BROXTON(dev)) {
> + dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
>   } else {
>   DRM_ERROR("Unsupported Mipi device to reg base");
>   return;
> -- 
> 1.7.9.5
>

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Re: [Intel-gfx] [PATCH] drm/i915: make prelim hw msg in log a bit more harsh

[Jani Nikula]

On Fri, 18 Sep 2015, Rob Clark  wrote:
> Apparently some people see this message and try to turn on
> preliminary_hw_support.  And then for some reason are surprised
> when it doesn't work.  So let's set expectations a bit lower.

I think the message goes wrong already at the beginning, "hardware
requires preliminary hardware support". The hardware really requires
full support, but preliminary is all we've got so far, and that's been
disabled by default...

How about something along the lines of,

"""
This kernel version does not properly support the hardware.
Preliminary support disabled by default.
See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT or i915.preliminary_hw_support.
"""

BR,
Jani.



>
> Signed-off-by: Rob Clark 
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 8edcec8..5e87fe1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -926,7 +926,8 @@ static int i915_pci_probe(struct pci_dev *pdev, const 
> struct pci_device_id *ent)
>  
>   if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
>   DRM_INFO("This hardware requires preliminary hardware 
> support.\n"
> -  "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or 
> modparam preliminary_hw_support\n");
> +  "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or 
> modparam preliminary_hw_support.\n"
> +  "Note that preliminary hw support is unsupported, use 
> at your own risk!\n");
>   return -ENODEV;
>   }
>  
> -- 
> 2.4.3
>
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Re: [Intel-gfx] [BXT MIPI PATCH v3 02/14] drm/i915/bxt: Enable BXT DSI PLL

[Jani Nikula]

On Tue, 01 Sep 2015, Uma Shankar  wrote:
> From: Shashank Sharma 
>
> This patch adds new functions for BXT clock and PLL programming.
> They are:
> 1. configure_dsi_pll for BXT.
>This function does the basic math and generates the divider ratio
>based on requested pixclock, and program clock registers.
> 2. enable_dsi_pll function.
>This function programs the calculated clock values on the PLL.
> 3. intel_enable_dsi_pll
>Wrapper function to use same code for multiple platforms. It checks the
>platform and calls appropriate core pll enable function.
>
> v2: Fixed Jani's review comments. Macros are adjusted as per convention.
>
> v3: Removed a redundant change wrt code comment.
>
> Signed-off-by: Shashank Sharma 
> Signed-off-by: Uma Shankar 

Reviewed-by: Jani Nikula 


> ---
>  drivers/gpu/drm/i915/i915_reg.h  |   22 
>  drivers/gpu/drm/i915/intel_dsi.c |2 +-
>  drivers/gpu/drm/i915/intel_dsi.h |2 +-
>  drivers/gpu/drm/i915/intel_dsi_pll.c |   95 
> +-
>  4 files changed, 118 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 621151b..06bb2e1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7362,6 +7362,28 @@ enum skl_disp_power_wells {
>  
>  #define _MIPI_PORT(port, a, c)   _PORT3(port, a, 0, c)   /* ports A and 
> C only */
>  
> +#define BXT_DSI_PLL_CTL  0x161000
> +#define  BXT_DSI_PLL_PVD_RATIO_SHIFT 16
> +#define  BXT_DSI_PLL_PVD_RATIO_MASK  (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
> +#define  BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
> +#define  BXT_DSIC_16X_BY2(1 << 10)
> +#define  BXT_DSIC_16X_BY3(2 << 10)
> +#define  BXT_DSIC_16X_BY4(3 << 10)
> +#define  BXT_DSIA_16X_BY2(1 << 8)
> +#define  BXT_DSIA_16X_BY3(2 << 8)
> +#define  BXT_DSIA_16X_BY4(3 << 8)
> +#define  BXT_DSI_FREQ_SEL_SHIFT  8
> +#define  BXT_DSI_FREQ_SEL_MASK   (0xF << BXT_DSI_FREQ_SEL_SHIFT)
> +
> +#define BXT_DSI_PLL_RATIO_MAX0x7D
> +#define BXT_DSI_PLL_RATIO_MIN0x22
> +#define BXT_DSI_PLL_RATIO_MASK   0xFF
> +#define BXT_REF_CLOCK_KHZ19500
> +
> +#define BXT_DSI_PLL_ENABLE   0x46080
> +#define  BXT_DSI_PLL_DO_ENABLE   (1 << 31)
> +#define  BXT_DSI_PLL_LOCKED  (1 << 30)
> +
>  #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
>  #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
>  #define MIPI_PORT_CTRL(port) _MIPI_PORT(port, _MIPIA_PORT_CTRL, 
> _MIPIC_PORT_CTRL)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c 
> b/drivers/gpu/drm/i915/intel_dsi.c
> index b59b828..fb259fb 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -903,8 +903,8 @@ static void intel_dsi_pre_pll_enable(struct intel_encoder 
> *encoder)
>   DRM_DEBUG_KMS("\n");
>  
>   intel_dsi_prepare(encoder);
> + intel_enable_dsi_pll(encoder);
>  
> - vlv_enable_dsi_pll(encoder);
>  }
>  
>  static enum drm_connector_status
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h 
> b/drivers/gpu/drm/i915/intel_dsi.h
> index 2784ac4..20cfcf07 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -121,7 +121,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct 
> drm_encoder *encoder)
>   return container_of(encoder, struct intel_dsi, base.base);
>  }
>  
> -extern void vlv_enable_dsi_pll(struct intel_encoder *encoder);
> +extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
>  extern void vlv_disable_dsi_pll(struct intel_encoder *encoder);
>  extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
>  
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c 
> b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index d20cf37..3830a4f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -237,7 +237,7 @@ static void vlv_configure_dsi_pll(struct intel_encoder 
> *encoder)
>   vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl);
>  }
>  
> -void vlv_enable_dsi_pll(struct intel_encoder *encoder)
> +static void vlv_enable_dsi_pll(struct intel_encoder *encoder)
>  {
>   struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
>   u32 tmp;
> @@ -368,3 +368,96 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int 
> pipe_bpp)
>  
>   return pclk;
>  }
> +
> +static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
> + u8 dsi_ratio;
> + 

[Intel-gfx] [PATCH] drm/i915/skl: handle port E in cpt_digital_port_connected

[Jani Nikula]

SKL port E handling was added in

commit 26951caf55d73ceb1967b0bf12f6d0b96853508e
Author: Xiong Zhang 
Date:   Mon Aug 17 15:55:50 2015 +0800

drm/i915/skl: enable DDI-E hotplug

but the whole function was moved in a another branch in

commit b93433ccf64846820b9448f5ff5dd4348b58a8ed
Author: Jani Nikula 
Date:   Thu Aug 20 10:47:36 2015 +0300

drm/i915: move ibx_digital_port_connected to intel_dp.c

and the addition was lost at some backmerge that I was unable to
identify. Put it back in.

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/intel_dp.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a6872508adec..77e4115fc847 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4583,6 +4583,9 @@ static bool cpt_digital_port_connected(struct 
drm_i915_private *dev_priv,
case PORT_D:
bit = SDE_PORTD_HOTPLUG_CPT;
break;
+   case PORT_E:
+   bit = SDE_PORTE_HOTPLUG_SPT;
+   break;
default:
MISSING_CASE(port->port);
return false;
-- 
2.1.4

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Re: [Intel-gfx] [PATCH] drm/i915/skl: handle port E in cpt_digital_port_connected

[Jani Nikula]

On Fri, 18 Sep 2015, Jani Nikula  wrote:
> SKL port E handling was added in
>
> commit 26951caf55d73ceb1967b0bf12f6d0b96853508e
> Author: Xiong Zhang 
> Date:   Mon Aug 17 15:55:50 2015 +0800
>
> drm/i915/skl: enable DDI-E hotplug
>
> but the whole function was moved in a another branch in
>
> commit b93433ccf64846820b9448f5ff5dd4348b58a8ed
> Author: Jani Nikula 
> Date:   Thu Aug 20 10:47:36 2015 +0300
>
> drm/i915: move ibx_digital_port_connected to intel_dp.c
>
> and the addition was lost at some backmerge that I was unable to
> identify. Put it back in.
>
> Signed-off-by: Jani Nikula 

Tested-by: Tomi Sarvela 

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index a6872508adec..77e4115fc847 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4583,6 +4583,9 @@ static bool cpt_digital_port_connected(struct 
> drm_i915_private *dev_priv,
>   case PORT_D:
>   bit = SDE_PORTD_HOTPLUG_CPT;
>   break;
> + case PORT_E:
> + bit = SDE_PORTE_HOTPLUG_SPT;
> + break;
>   default:
>   MISSING_CASE(port->port);
>   return false;
> -- 
> 2.1.4
>

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Re: [Intel-gfx] [BXT MIPI PATCH v3 04/14] drm/i915/bxt: DSI prepare changes for BXT

[Jani Nikula]

On Tue, 01 Sep 2015, Uma Shankar  wrote:
> From: Shashank Sharma 
>
> This patch modifies dsi_prepare() function to support the same
> modeset prepare sequence for BXT also. Main changes are:
> 1. BXT port control register is different than VLV.
> 2. BXT modeset sequence needs vdisplay and hdisplay programmed
>for transcoder.
> 3. BXT can select PIPE for MIPI transcoders.
> 4. BXT needs to program register MIPI_INIT_COUNT for both the ports,
>even if only one is being used.
>
> v2: Fixed Jani's review comments. Rectified the DSI Macros to get
> proper register offsets using _MIPI_PORT instead of _TRANSCODER
>
> v3: Rebased on latest drm-nightly branch. Fixed Jani's review comments.
>
> Signed-off-by: Shashank Sharma 
> Signed-off-by: Uma Shankar 

Reviewed-by: Jani Nikula 


> ---
>  drivers/gpu/drm/i915/i915_reg.h  |   21 
>  drivers/gpu/drm/i915/intel_dsi.c |   69 
> --
>  2 files changed, 80 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 06bb2e1..997a999 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7362,6 +7362,22 @@ enum skl_disp_power_wells {
>  
>  #define _MIPI_PORT(port, a, c)   _PORT3(port, a, 0, c)   /* ports A and 
> C only */
>  
> +/* BXT MIPI mode configure */
> +#define  _BXT_MIPIA_TRANS_HACTIVE0x6B0F8
> +#define  _BXT_MIPIC_TRANS_HACTIVE0x6B8F8
> +#define  BXT_MIPI_TRANS_HACTIVE(tc)  _MIPI_PORT(tc, \
> + _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
> +
> +#define  _BXT_MIPIA_TRANS_VACTIVE0x6B0FC
> +#define  _BXT_MIPIC_TRANS_VACTIVE0x6B8FC
> +#define  BXT_MIPI_TRANS_VACTIVE(tc)  _MIPI_PORT(tc, \
> + _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
> +
> +#define  _BXT_MIPIA_TRANS_VTOTAL 0x6B100
> +#define  _BXT_MIPIC_TRANS_VTOTAL 0x6B900
> +#define  BXT_MIPI_TRANS_VTOTAL(tc)   _MIPI_PORT(tc, \
> + _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
> +
>  #define BXT_DSI_PLL_CTL  0x161000
>  #define  BXT_DSI_PLL_PVD_RATIO_SHIFT 16
>  #define  BXT_DSI_PLL_PVD_RATIO_MASK  (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
> @@ -7797,6 +7813,11 @@ enum skl_disp_power_wells {
>  #define  READ_REQUEST_PRIORITY_HIGH  (3 << 3)
>  #define  RGB_FLIP_TO_BGR (1 << 2)
>  
> +#define  BXT_PIPE_SELECT_MASK(7 << 7)
> +#define  BXT_PIPE_SELECT_C   (2 << 7)
> +#define  BXT_PIPE_SELECT_B   (1 << 7)
> +#define  BXT_PIPE_SELECT_A   (0 << 7)
> +
>  #define _MIPIA_DATA_ADDRESS  (dev_priv->mipi_mmio_base + 0xb108)
>  #define _MIPIC_DATA_ADDRESS  (dev_priv->mipi_mmio_base + 0xb908)
>  #define MIPI_DATA_ADDRESS(port)  _MIPI_PORT(port, 
> _MIPIA_DATA_ADDRESS, \
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c 
> b/drivers/gpu/drm/i915/intel_dsi.c
> index bac988a..6d0c992 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -726,6 +726,21 @@ static void set_dsi_timings(struct drm_encoder *encoder,
>   hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
>  
>   for_each_dsi_port(port, intel_dsi->ports) {
> + if (IS_BROXTON(dev)) {
> + /*
> +  * Program hdisplay and vdisplay on MIPI transcoder.
> +  * This is different from calculated hactive and
> +  * vactive, as they are calculated per channel basis,
> +  * whereas these values should be based on resolution.
> +  */
> + I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
> + mode->hdisplay);
> + I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
> + mode->vdisplay);
> + I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
> + mode->vtotal);
> + }
> +
>   I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
>   I915_WRITE(MIPI_HFP_COUNT(port), hfp);
>  
> @@ -766,16 +781,39 @@ static void intel_dsi_prepare(struct intel_encoder 
> *intel_encoder)
>   }
>  
>   for_each_dsi_port(port, intel_dsi->ports) {
> - /* escape clock divider, 20MHz, shared for A and C.
> -  * device ready must be off when doing this! txclkesc? */
> - tmp = I915_READ(MIPI_CTRL(PORT_A));
> - tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
> - I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1);
> -
> - /* read request 

Re: [Intel-gfx] [BXT MIPI PATCH v3 06/14] drm/i915/bxt: DSI enable for BXT

[Jani Nikula]

On Tue, 01 Sep 2015, Uma Shankar  wrote:
> From: Shashank Sharma 
>
> This patch contains following changes:
> 1. MIPI device ready changes to support dsi_pre_enable. Changes
>are specific to BXT device ready sequence. Added check for
>ULPS mode(No effects on VLV).
> 2. Changes in dsi_enable to pick BXT port control register.
> 3. Changes in dsi_pre_enable to restrict DPIO programming for VLV
>
> v2: Fixed Jani's review comments. Removed the changes in VLV/CHV
> code. Fixed the macros to get proper port offsets.
>
> v3: Rebased on latest drm-nightly branch. Fixed Jani's review comments.
>
> Signed-off-by: Shashank Sharma 
> Signed-off-by: Uma Shankar 

Reviewed-by: Jani Nikula 

When you look at the commits before sending, you should pay more
attention to what the diffs end up looking like. In this case, the
review becomes unnecessarily hard just because you've moved code
(intel_dsi_port_enable) around for no apparent reason, and the diff
seems like intel_dsi_port_enable is rewritten into
bxt_dsi_device_ready. It should be a hint to *not* combine code movement
into the same patch.


> ---
>  drivers/gpu/drm/i915/i915_reg.h  |7 ++
>  drivers/gpu/drm/i915/intel_dsi.c |  165 
> ++
>  2 files changed, 119 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 997a999..57c5dbf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7403,6 +7403,13 @@ enum skl_disp_power_wells {
>  #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
>  #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
>  #define MIPI_PORT_CTRL(port) _MIPI_PORT(port, _MIPIA_PORT_CTRL, 
> _MIPIC_PORT_CTRL)
> +
> + /* BXT port control */
> +#define _BXT_MIPIA_PORT_CTRL 0x6B0C0
> +#define _BXT_MIPIC_PORT_CTRL 0x6B8C0
> +#define BXT_MIPI_PORT_CTRL(tc)   _MIPI_PORT(tc, _BXT_MIPIA_PORT_CTRL, \
> + _BXT_MIPIC_PORT_CTRL)
> +
>  #define  DPI_ENABLE  (1 << 31) /* A + C */
>  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT   27
>  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK(0xf << 27)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c 
> b/drivers/gpu/drm/i915/intel_dsi.c
> index 6d0c992..5a42f87 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -286,58 +286,46 @@ static bool intel_dsi_compute_config(struct 
> intel_encoder *encoder,
>   return true;
>  }
>  
> -static void intel_dsi_port_enable(struct intel_encoder *encoder)
> +static void bxt_dsi_device_ready(struct intel_encoder *encoder)
>  {
> - struct drm_device *dev = encoder->base.dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
>   struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
>   enum port port;
> - u32 temp;
> + u32 val;
>  
> - if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
> - temp = I915_READ(VLV_CHICKEN_3);
> - temp &= ~PIXEL_OVERLAP_CNT_MASK |
> - intel_dsi->pixel_overlap <<
> - PIXEL_OVERLAP_CNT_SHIFT;
> - I915_WRITE(VLV_CHICKEN_3, temp);
> - }
> + DRM_DEBUG_KMS("\n");
>  
> + /* Exit Low power state in 4 steps*/
>   for_each_dsi_port(port, intel_dsi->ports) {
> - temp = I915_READ(MIPI_PORT_CTRL(port));
> - temp &= ~LANE_CONFIGURATION_MASK;
> - temp &= ~DUAL_LINK_MODE_MASK;
>  
> - if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) {
> - temp |= (intel_dsi->dual_link - 1)
> - << DUAL_LINK_MODE_SHIFT;
> - temp |= intel_crtc->pipe ?
> - LANE_CONFIGURATION_DUAL_LINK_B :
> - LANE_CONFIGURATION_DUAL_LINK_A;
> - }
> - /* assert ip_tg_enable signal */
> - I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
> - POSTING_READ(MIPI_PORT_CTRL(port));
> - }
> -}
> + /* 1. Enable MIPI PHY transparent latch */
> + val = I915_READ(BXT_MIPI_PORT_CTRL(port));
> + I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
> + usleep_range(2000, 2500);
>  
> -static void intel_dsi_port_disable(struct intel_encoder *encoder)
> -{
> - struct drm_device *dev = encoder->base.dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_dsi 

Re: [Intel-gfx] [BXT MIPI PATCH v3 07/14] drm/i915/bxt: Program Tx Rx and Dphy clocks

[Jani Nikula]

On Tue, 01 Sep 2015, Uma Shankar  wrote:
> From: Shashank Sharma 
>
> BXT DSI clocks are different than previous platforms. So adding a
> new function to program following clocks and dividers:
> 1. Program variable divider to generate input to Tx clock divider
>(Output value must be < 39.5Mhz)
> 2. Select divide by 2 option to get < 20Mhz for Tx clock
> 3. Program 8by3 divider to generate Rx clock
>
> v2: Fixed Jani's review comments. Adjusted the Macro definition as
> per convention. Simplified the logic for bit definitions for
> MIPI PORT A and PORT C in same registers.
>
> v3: Refactored the macros for TX, RX Escape and DPHY clocks as per
> Jani's suggestion.
>
> Signed-off-by: Shashank Sharma 
> Signed-off-by: Uma Shankar 

Minor comments below, anyway

Reviewed-by: Jani Nikula 


> ---
>  drivers/gpu/drm/i915/i915_reg.h  |   62 
> ++
>  drivers/gpu/drm/i915/intel_dsi_pll.c |   39 +
>  2 files changed, 101 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 57c5dbf..e43b053 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7362,6 +7362,68 @@ enum skl_disp_power_wells {
>  
>  #define _MIPI_PORT(port, a, c)   _PORT3(port, a, 0, c)   /* ports A and 
> C only */
>  
> +/* BXT MIPI clock controls */
> +#define BXT_MAX_VAR_OUTPUT_KHZ   39500
> +
> +#define BXT_MIPI_CLOCK_CTL   0x46090
> +#define  BXT_MIPI1_DIV_SHIFT 26
> +#define  BXT_MIPI2_DIV_SHIFT 10
> +#define  BXT_MIPI_DIV_SHIFT(port)\
> + _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
> + BXT_MIPI2_DIV_SHIFT)
> +/* Var clock divider to generate TX source. Result must be < 39.5 M */
> +#define  BXT_MIPI1_ESCLK_VAR_DIV_MASK(0x3F << 26)
> +#define  BXT_MIPI2_ESCLK_VAR_DIV_MASK(0x3F << 10)
> +#define  BXT_MIPI_ESCLK_VAR_DIV_MASK(port)   \
> + _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
> + BXT_MIPI2_ESCLK_VAR_DIV_MASK)
> +
> +#define  BXT_MIPI_ESCLK_VAR_DIV(port, val)   \
> + (val << BXT_MIPI_DIV_SHIFT(port))
> +/* TX control divider to select actual TX clock output from (8x/var) */
> +#define  BXT_MIPI1_TX_ESCLK_SHIFT21
> +#define  BXT_MIPI2_TX_ESCLK_SHIFT5
> +#define  BXT_MIPI_TX_ESCLK_SHIFT(port)   \
> + _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
> + BXT_MIPI2_TX_ESCLK_SHIFT)
> +#define  BXT_MIPI1_TX_ESCLK_FIXDIV_MASK  (3 << 21)
> +#define  BXT_MIPI2_TX_ESCLK_FIXDIV_MASK  (3 << 5)
> +#define  BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
> + _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
> + BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
> +#define  BXT_MIPI_TX_ESCLK_8XDIV_BY2(port)   \
> + (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
> +#define  BXT_MIPI_TX_ESCLK_8XDIV_BY4(port)   \
> + (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
> +#define  BXT_MIPI_TX_ESCLK_8XDIV_BY8(port)   \
> + (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
> +/* RX control divider to select actual RX clock output from 8x*/
> +#define  BXT_MIPI1_RX_ESCLK_SHIFT19
> +#define  BXT_MIPI2_RX_ESCLK_SHIFT3
> +#define  BXT_MIPI_RX_ESCLK_SHIFT(port)   \
> + _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
> + BXT_MIPI2_RX_ESCLK_SHIFT)
> +#define  BXT_MIPI1_RX_ESCLK_FIXDIV_MASK  (3 << 19)
> +#define  BXT_MIPI2_RX_ESCLK_FIXDIV_MASK  (3 << 3)
> +#define  BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \
> + (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> +#define  BXT_MIPI_RX_ESCLK_8X_BY2(port)  \
> + (1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> +#define  BXT_MIPI_RX_ESCLK_8X_BY3(port)  \
> + (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> +#define  BXT_MIPI_RX_ESCLK_8X_BY4(port)  \
> + (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> +/* BXT: Always prog DPHY dividers to 00 */

Actually BXT A stepping W/A, but I don't know the name for it.

> +#define  BXT_MIPI1_DPHY_DIV_SHIFT16
> +#define  BXT_MIPI2_DPHY_DIV_SHIFT0
> +#define  BXT_MIPI_DPHY_DIV_SHIFT(port)   \
> + _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
> + BXT_MIPI2_DPHY_DIV_SHIFT)
> +#define  BXT_MIPI_1_DPHY_DIVIDER_MASK(3 << 16)
> +#define  BXT_MIPI_2_DPHY_DIVIDER_MASK(3 << 0)
> +#define  BXT_MIPI_DPHY_DIVIDER_MASK(port)\
> + (3 << 

Re: [Intel-gfx] [PATCH] drm/i915: make prelim hw msg in log a bit more harsh

[Rob Clark]

On Fri, Sep 18, 2015 at 7:59 AM, Jani Nikula
 wrote:
> On Fri, 18 Sep 2015, Rob Clark  wrote:
>> Apparently some people see this message and try to turn on
>> preliminary_hw_support.  And then for some reason are surprised
>> when it doesn't work.  So let's set expectations a bit lower.
>
> I think the message goes wrong already at the beginning, "hardware
> requires preliminary hardware support". The hardware really requires
> full support, but preliminary is all we've got so far, and that's been
> disabled by default...
>
> How about something along the lines of,
>
> """
> This kernel version does not properly support the hardware.
> Preliminary support disabled by default.
> See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT or i915.preliminary_hw_support.
> """

I'm not too picky on the wording, but I think it should include
something along the lines of "unsupported" or "use at your own risk"
just to make it clear that you may be left with a dark screen..

I kinda think we should also drop
CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT too and leave only the module
param (since the config option encourages one to build a kernel that
won't work unless you know to override i915.reliminary_hw_support in
grub.

After that, perhaps switch to module_param_named_unsafe() for good measure..

BR,
-R

> BR,
> Jani.
>
>
>
>>
>> Signed-off-by: Rob Clark 
>> ---
>>  drivers/gpu/drm/i915/i915_drv.c | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c 
>> b/drivers/gpu/drm/i915/i915_drv.c
>> index 8edcec8..5e87fe1 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -926,7 +926,8 @@ static int i915_pci_probe(struct pci_dev *pdev, const 
>> struct pci_device_id *ent)
>>
>>   if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
>>   DRM_INFO("This hardware requires preliminary hardware 
>> support.\n"
>> -  "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or 
>> modparam preliminary_hw_support\n");
>> +  "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or 
>> modparam preliminary_hw_support.\n"
>> +  "Note that preliminary hw support is unsupported, use 
>> at your own risk!\n");
>>   return -ENODEV;
>>   }
>>
>> --
>> 2.4.3
>>
>> ___
>> dri-devel mailing list
>> dri-de...@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/dri-devel
>
> --
> Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [BXT MIPI PATCH v3 14/14] drm/i915: Added BXT DSI backlight support

[Jani Nikula]

On Tue, 01 Sep 2015, Uma Shankar  wrote:
> DSI backlight support for bxt is added.
>
> TODO: There is no support for backlight control in drm panel
>   framework. This will be added as part of VBT version patches
>   fixing the backlight sequence.
>
> v2: Fixed Jani's review comments from previous patch. Added the
> BXT DSI backlight code in this patch. Backlight setup and
> enable/disable code for backlight is added in intel_dsi.c.
>
> v3: Rebased on latest drm-nightly. Fixed Jani's review comments.

I'm not sure why these calls need to be within IS_BROXTON blocks. What
happens with the current backlight calls? Shouldn't we just have one set
of calls?

Also, I think we should get this [1] in first, and see how that affects
things.

BR,
Jani.


[1] http://mid.gmane.org/cover.1442227790.git.jani.nik...@intel.com

>
> Signed-off-by: Uma Shankar 
> ---
>  drivers/gpu/drm/i915/intel_dsi.c |   20 +++-
>  1 file changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c 
> b/drivers/gpu/drm/i915/intel_dsi.c
> index 08bade2..aee1539 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -438,6 +438,7 @@ static void intel_dsi_enable(struct intel_encoder 
> *encoder)
>   struct drm_device *dev = encoder->base.dev;
>   struct drm_i915_private *dev_priv = dev->dev_private;
>   struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
> + struct intel_connector *intel_connector = intel_dsi->attached_connector;
>   enum port port;
>  
>   DRM_DEBUG_KMS("\n");
> @@ -458,6 +459,11 @@ static void intel_dsi_enable(struct intel_encoder 
> *encoder)
>  
>   intel_dsi_port_enable(encoder);
>   }
> +
> + if (IS_BROXTON(dev)) {
> + msleep(intel_dsi->backlight_on_delay);
> + intel_panel_enable_backlight(intel_connector);
> + }
>  }
>  
>  static void intel_dsi_pre_enable(struct intel_encoder *encoder)
> @@ -623,10 +629,16 @@ static void intel_dsi_post_disable(struct intel_encoder 
> *encoder)
>  {
>   struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
>   struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
> + struct intel_connector *intel_connector = intel_dsi->attached_connector;
>   u32 val;
>  
>   DRM_DEBUG_KMS("\n");
>  
> + if (IS_BROXTON(dev_priv->dev)) {
> + intel_panel_disable_backlight(intel_connector);
> + msleep(intel_dsi->backlight_off_delay);
> + }
> +
>   intel_dsi_disable(encoder);
>  
>   intel_dsi_clear_device_ready(encoder);
> @@ -1226,8 +1238,14 @@ void intel_dsi_init(struct drm_device *dev)
>  
>   intel_panel_init(_connector->panel, fixed_mode, NULL);
>  
> - return;
> + /*
> +  * Pipe parameter is not used for BXT.
> +  * Passing INVALID_PIPE to adher to API requirement.
> +  */
> + if (IS_BROXTON(dev))
> + intel_panel_setup_backlight(connector, INVALID_PIPE);
>  
> + return;
>  err:
>   drm_encoder_cleanup(_encoder->base);
>   kfree(intel_dsi);
> -- 
> 1.7.9.5
>

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [BXT MIPI PATCH v3 11/14] drm/i915/bxt: Modify BXT BLC according to VBT changes

[Jani Nikula]

On Tue, 01 Sep 2015, Uma Shankar  wrote:
> From: Sunil Kamath 
>
> Latest VBT mentions which set of registers will be used for BLC,
> as controller number field. Making use of this field in BXT
> BLC implementation. Also, the registers are used in case control
> pin indicates display DDI. Adding a check for this.
> According to Bspec, BLC_PWM_*_2 uses the display utility pin for output.
> To use backlight 2, enable the utility pin with mode = PWM
>v2: Jani's review comments
>addressed
>- Add a prefix _ to BXT BLC registers definitions.
>- Add "bxt only" comment for u8 controller
>- Remove control_pin check for DDI controller
>- Check for valid controller values
>- Set pipe bits in UTIL_PIN_CTL
>- Enable/Disable UTIL_PIN_CTL in enable/disable_backlight()
>- If BLC 2 is used, read active_low_pwm from UTIL_PIN polarity
>Satheesh's review comment addressed
>- If UTIL PIN is already enabled, BIOS would have programmed it. No
>need to disable and enable again.
>v3: Jani's review comments
>- add UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK
>- Disable UTIL_PIN if controller 1 is used
>- Mask out UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK before enabling
>UTIL_PIN
>- check valid controller value in intel_bios.c
>- add backlight.util_pin_active_low
>- disable util pin before enabling
>v4: Change for BXT-PO branch:
>Stubbed unwanted definition which was existing before
>because of DC6 patch.
>UTIL_PIN_MODE_PWM (0x1b << 24)
>
> v2: Fixed Jani's review comment.
>
> v3: Split the backight PWM frequency programming into separate patch,
> in cases BIOS doesn't initializes it.
>
> Signed-off-by: Vandana Kannan 
> Signed-off-by: Sunil Kamath 
> Signed-off-by: Uma Shankar 
> ---
>  drivers/gpu/drm/i915/i915_reg.h|   28 
>  drivers/gpu/drm/i915/intel_drv.h   |2 +
>  drivers/gpu/drm/i915/intel_panel.c |   84 
> 
>  3 files changed, 89 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e43b053..8407b5c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3512,17 +3512,29 @@ enum skl_disp_power_wells {
>  #define UTIL_PIN_CTL 0x48400
>  #define   UTIL_PIN_ENABLE(1 << 31)
>  
> +#define   UTIL_PIN_PIPE(x) ((x) << 29)
> +#define   UTIL_PIN_PIPE_MASK   (3 << 29)
> +#define   UTIL_PIN_MODE_PWM(1 << 24)
> +#define   UTIL_PIN_MODE_MASK   (0xf << 24)
> +#define   UTIL_PIN_POLARITY(1 << 22)
> +
>  /* BXT backlight register definition. */
> -#define BXT_BLC_PWM_CTL1 0xC8250
> +#define _BXT_BLC_PWM_CTL10xC8250
>  #define   BXT_BLC_PWM_ENABLE (1 << 31)
>  #define   BXT_BLC_PWM_POLARITY   (1 << 29)
> -#define BXT_BLC_PWM_FREQ10xC8254
> -#define BXT_BLC_PWM_DUTY10xC8258
> -
> -#define BXT_BLC_PWM_CTL2 0xC8350
> -#define BXT_BLC_PWM_FREQ20xC8354
> -#define BXT_BLC_PWM_DUTY20xC8358
> -
> +#define _BXT_BLC_PWM_FREQ1   0xC8254
> +#define _BXT_BLC_PWM_DUTY1   0xC8258
> +
> +#define _BXT_BLC_PWM_CTL20xC8350
> +#define _BXT_BLC_PWM_FREQ2   0xC8354
> +#define _BXT_BLC_PWM_DUTY2   0xC8358
> +
> +#define BXT_BLC_PWM_CTL(controller)_PIPE(controller, \
> + _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
> +#define BXT_BLC_PWM_FREQ(controller)   _PIPE(controller, \
> + _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
> +#define BXT_BLC_PWM_DUTY(controller)   _PIPE(controller, \
> + _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
>  
>  #define PCH_GTC_CTL  0xe7000
>  #define   PCH_GTC_ENABLE (1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index 1059283..d8ca075 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -182,7 +182,9 @@ struct intel_panel {
>   bool enabled;
>   bool combination_mode;  /* gen 2/4 only */
>   bool active_low_pwm;
> + bool util_pin_active_low;   /* bxt+ */
>   struct backlight_device *device;
> + u8 controller;  /* bxt+ only */
>   } backlight;
>  
>   void (*backlight_power)(struct intel_connector *, bool enable);
> diff --git a/drivers/gpu/drm/i915/intel_panel.c 
> b/drivers/gpu/drm/i915/intel_panel.c
> index 55aad23..9fcf86c 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -539,9 

Re: [Intel-gfx] [BXT MIPI PATCH v3 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset

[Jani Nikula]

On Tue, 01 Sep 2015, Uma Shankar  wrote:
> From: Shashank Sharma 
>
> SKL and BXT qualifies the HAS_DDI() check, and hence haswell
> modeset functions are re-used for modeset sequence. But DDI
> interface doesn't include support for DSI.
> This patch adds:
> 1. cases for DSI encoder, in those modeset functions and allows
>a CRTC modeset
> 2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
>needs to be done as such in CRTC for DSI encoder, as PLL, clock
>and and transcoder programming will be taken care in encoder's
>pre_enable and pre_pll_enable function.
>
> v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
> encoder like DSI for platforms having HAS_DDI as true.
>
> v3: Rebased on latest drm-nightly branch. Added a WARN_ON for invalid
> encoder.
>
> Signed-off-by: Shashank Sharma 
> Signed-off-by: Uma Shankar 
> ---
>  drivers/gpu/drm/i915/i915_drv.h   |1 +
>  drivers/gpu/drm/i915/intel_ddi.c  |   29 -
>  drivers/gpu/drm/i915/intel_display.c  |   19 ++-
>  drivers/gpu/drm/i915/intel_dp_mst.c   |1 +
>  drivers/gpu/drm/i915/intel_opregion.c |3 ++-
>  5 files changed, 46 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fd1de45..78d31c5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -142,6 +142,7 @@ enum plane {
>  #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 
> 'A')
>  
>  enum port {
> + PORT_INVALID = -1,
>   PORT_A = 0,
>   PORT_B,
>   PORT_C,
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index cacb07b..5d5aad2 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -227,6 +227,10 @@ static void ddi_get_encoder_port(struct intel_encoder 
> *intel_encoder,
>   } else if (type == INTEL_OUTPUT_ANALOG) {
>   *dig_port = NULL;
>   *port = PORT_E;
> + } else if (type == INTEL_OUTPUT_DSI) {
> + *dig_port = NULL;
> + *port = PORT_INVALID;
> + DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");

Please remind me again what are the legitimate paths to get here with
DSI?

With all the changes and warns across the driver, I'm beginning to think
we should have a version of this function that accepts DSI, and another
one that (calls the other one) and WARNS on DSI, and that should be
called on all paths that should never encounter a DSI encoder.

The proliferation of WARNS all over the place is not very nice.

I'm sorry, I know this is not the review I gave previously on this.


BR,
Jani.


>   } else {
>   DRM_ERROR("Invalid DDI encoder type %d\n", type);
>   BUG();
> @@ -392,6 +396,11 @@ void intel_prepare_ddi(struct drm_device *dev)
>  
>   ddi_get_encoder_port(intel_encoder, _dig_port, );
>  
> + if (port == PORT_INVALID) {
> + WARN_ON(1);
> + continue;
> + }
> +
>   if (visited[port])
>   continue;
>  
> @@ -980,6 +989,8 @@ static void bxt_ddi_clock_get(struct intel_encoder 
> *encoder,
>   enum port port = intel_ddi_get_encoder_port(encoder);
>   uint32_t dpll = port;
>  
> + WARN_ON(port == PORT_INVALID);
> +
>   pipe_config->port_clock =
>   bxt_calc_pll_link(dev_priv, dpll);
>  
> @@ -1572,6 +1583,8 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc 
> *crtc)
>   int type = intel_encoder->type;
>   uint32_t temp;
>  
> + WARN_ON(port == PORT_INVALID);
> +
>   /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
>   temp = TRANS_DDI_FUNC_ENABLE;
>   temp |= TRANS_DDI_SELECT_PORT(port);
> @@ -1684,6 +1697,8 @@ bool intel_ddi_connector_get_hw_state(struct 
> intel_connector *intel_connector)
>   enum intel_display_power_domain power_domain;
>   uint32_t tmp;
>  
> + WARN_ON(port == PORT_INVALID);
> +
>   power_domain = intel_display_port_power_domain(intel_encoder);
>   if (!intel_display_power_is_enabled(dev_priv, power_domain))
>   return false;
> @@ -1730,6 +1745,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder 
> *encoder,
>   u32 tmp;
>   int i;
>  
> + WARN_ON(port == PORT_INVALID);
> +
>   power_domain = intel_display_port_power_domain(encoder);
>   if (!intel_display_power_is_enabled(dev_priv, power_domain))
>   return false;
> @@ -1779,11 +1796,14 @@ bool intel_ddi_get_hw_state(struct intel_encoder 
> *encoder,
>  void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
>  {
>   struct drm_crtc *crtc = _crtc->base;
> - struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> + struct 

Re: [Intel-gfx] [BXT MIPI PATCH v3 09/14] drm/i915/bxt: get_hw_state for BXT

[Jani Nikula]

On Tue, 01 Sep 2015, Uma Shankar  wrote:
> From: Shashank Sharma 
>
> Pick appropriate port control register (BXT or VLV), based on device.
> Get the current hw state wrt Mipi port.
>
> v2: Rebased on latest drm nightly branch.
>
> v3: Removed the GET_DSI_PORT_CTRL Macro for consistency with earlier
> implementations as per Jani's suggestion.
>
> Signed-off-by: Shashank Sharma 
> Signed-off-by: Uma Shankar 

Reviewed-by: Jani Nikula 


> ---
>  drivers/gpu/drm/i915/intel_dsi.c |7 ---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c 
> b/drivers/gpu/drm/i915/intel_dsi.c
> index 110a895..001569b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -648,7 +648,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder 
> *encoder,
>   struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
>   struct drm_device *dev = encoder->base.dev;
>   enum intel_display_power_domain power_domain;
> - u32 dpi_enabled, func;
> + u32 dpi_enabled, func, ctrl_reg;
>   enum port port;
>  
>   DRM_DEBUG_KMS("\n");
> @@ -660,8 +660,9 @@ static bool intel_dsi_get_hw_state(struct intel_encoder 
> *encoder,
>   /* XXX: this only works for one DSI output */
>   for_each_dsi_port(port, intel_dsi->ports) {
>   func = I915_READ(MIPI_DSI_FUNC_PRG(port));
> - dpi_enabled = I915_READ(MIPI_PORT_CTRL(port)) &
> - DPI_ENABLE;
> + ctrl_reg = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) :
> + MIPI_PORT_CTRL(port);
> + dpi_enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
>  
>   /* Due to some hardware limitations on BYT, MIPI Port C DPI
>* Enable bit does not get set. To check whether DSI Port C
> -- 
> 1.7.9.5
>

-- 
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Re: [Intel-gfx] [BXT MIPI PATCH v3 12/14] drm/i915/bxt: Program Backlight PWM frequency

[Jani Nikula]

On Tue, 01 Sep 2015, Uma Shankar  wrote:
> In some cases, BIOS doesn't initializes DSI panel.DSI and
> backlight registers are thereby not initialized. Programming
> the same in driver backlight setup.
>
> Signed-off-by: Uma Shankar 

This is probably obsolete now. See current bxt_setup_backlight.

BR,
Jani.


> ---
>  drivers/gpu/drm/i915/i915_reg.h|3 +++
>  drivers/gpu/drm/i915/intel_panel.c |   11 +++
>  2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8407b5c..10f73b1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7166,6 +7166,9 @@ enum skl_disp_power_wells {
>  #define  TRANS_MSA_12_BPC(3<<5)
>  #define  TRANS_MSA_16_BPC(4<<5)
>  
> +/* Max CDCLK freq for BXT in HZ */
> +#define BXT_CDCLK_MAX   62400
> +
>  /* LCPLL Control */
>  #define LCPLL_CTL0x130040
>  #define  LCPLL_PLL_DISABLE   (1<<31)
> diff --git a/drivers/gpu/drm/i915/intel_panel.c 
> b/drivers/gpu/drm/i915/intel_panel.c
> index 9fcf86c..8225cea 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -1427,6 +1427,17 @@ bxt_setup_backlight(struct intel_connector *connector, 
> enum pipe unused)
>   panel->backlight.max = I915_READ(
>   BXT_BLC_PWM_FREQ(panel->backlight.controller));
>  
> + if (!panel->backlight.max) {
> + DRM_DEBUG_KMS("PWM freq not programmed by BIOS\n");
> + DRM_DEBUG_KMS("Programming PWM freq\n");
> +
> + /* Max Backlight = Max CD Clock / pwm freq) */
> + panel->backlight.max = (BXT_CDCLK_MAX /
> + dev_priv->vbt.backlight.pwm_freq_hz);
> + I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
> + panel->backlight.max);
> + }
> +
>   val = bxt_get_backlight(connector);
>   panel->backlight.level = intel_panel_compute_brightness(connector, val);
>  
> -- 
> 1.7.9.5
>

-- 
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Re: [Intel-gfx] [BXT MIPI PATCH v3 13/14] drm/i915/bxt: Remove DSP CLK_GATE programming for BXT

[Jani Nikula]

On Tue, 01 Sep 2015, Uma Shankar  wrote:
> DSP CLK_GATE registers are specific to BYT and CHT.
> Avoid programming the same for BXT platform.
>
> v2: Rebased on latest drm nightly branch.
>
> v3: Fixed Jani's review comments
>
> Signed-off-by: Uma Shankar 

Reviewed-by: Jani Nikula 


> ---
>  drivers/gpu/drm/i915/intel_dsi.c |8 +---
>  1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c 
> b/drivers/gpu/drm/i915/intel_dsi.c
> index 6a0071f..08bade2 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -631,9 +631,11 @@ static void intel_dsi_post_disable(struct intel_encoder 
> *encoder)
>  
>   intel_dsi_clear_device_ready(encoder);
>  
> - val = I915_READ(DSPCLK_GATE_D);
> - val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
> - I915_WRITE(DSPCLK_GATE_D, val);
> + if (!IS_BROXTON(dev_priv->dev)) {
> + val = I915_READ(DSPCLK_GATE_D);
> + val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
> + I915_WRITE(DSPCLK_GATE_D, val);
> + }
>  
>   drm_panel_unprepare(intel_dsi->panel);
>  
> -- 
> 1.7.9.5
>

-- 
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Re: [Intel-gfx] [BXT MIPI PATCH v3 08/14] drm/i915/bxt: DSI disable and post-disable

[Jani Nikula]

On Tue, 01 Sep 2015, Uma Shankar  wrote:
> From: Shashank Sharma 
>
> This patch contains changes to support DSI disble sequence in BXT.
> The changes are:
> 1. BXT specific changes in clear_device_ready function.
> 2. BXT specific changes in DSI disable and post-disable functions.
> 3. Add a new function to reset BXT Dphy clock and dividers
>(bxt_dsi_reset_clocks).
> 4. Moved some part of the vlv clock reset code, in a new function
>(vlv_dsi_reset_clocks) maintaining the exact same sequence.
> 5. Wrapper function to call corresponding reset clock function.
>
> v2: Fixed Jani's review comments.
>
> v3: Removed the GET_DSI_PORT_CTRL Macro for consistency with earlier
> implementations as per Jani's suggestion.
>
> Signed-off-by: Uma Shankar 
> Signed-off-by: Shashank Sharma 

Reviewed-by: Jani Nikula 


> ---
>  drivers/gpu/drm/i915/intel_dsi.c |   36 +--
>  drivers/gpu/drm/i915/intel_dsi.h |2 ++
>  drivers/gpu/drm/i915/intel_dsi_pll.c |   39 
> ++
>  3 files changed, 61 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c 
> b/drivers/gpu/drm/i915/intel_dsi.c
> index 5a42f87..110a895 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -421,12 +421,15 @@ static void intel_dsi_port_disable(struct intel_encoder 
> *encoder)
>   struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
>   enum port port;
>   u32 temp;
> + u32 port_ctrl;
>  
>   for_each_dsi_port(port, intel_dsi->ports) {
>   /* de-assert ip_tg_enable signal */
> - temp = I915_READ(MIPI_PORT_CTRL(port));
> - I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
> - POSTING_READ(MIPI_PORT_CTRL(port));
> + port_ctrl = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) :
> + MIPI_PORT_CTRL(port);
> + temp = I915_READ(port_ctrl);
> + I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
> + POSTING_READ(port_ctrl);
>   }
>  }
>  
> @@ -550,12 +553,7 @@ static void intel_dsi_disable(struct intel_encoder 
> *encoder)
>   /* Panel commands can be sent when clock is in LP11 */
>   I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
>  
> - temp = I915_READ(MIPI_CTRL(port));
> - temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
> - I915_WRITE(MIPI_CTRL(port), temp |
> -intel_dsi->escape_clk_div <<
> -ESCAPE_CLOCK_DIVIDER_SHIFT);
> -
> + intel_dsi_reset_clocks(encoder, port);
>   I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
>  
>   temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
> @@ -574,10 +572,12 @@ static void intel_dsi_disable(struct intel_encoder 
> *encoder)
>  
>  static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
>  {
> + struct drm_device *dev = encoder->base.dev;
>   struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
>   struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
>   enum port port;
>   u32 val;
> + u32 port_ctrl = 0;
>  
>   DRM_DEBUG_KMS("\n");
>   for_each_dsi_port(port, intel_dsi->ports) {
> @@ -594,18 +594,22 @@ static void intel_dsi_clear_device_ready(struct 
> intel_encoder *encoder)
>   ULPS_STATE_ENTER);
>   usleep_range(2000, 2500);
>  
> + if (IS_BROXTON(dev))
> + port_ctrl = BXT_MIPI_PORT_CTRL(port);
> + else if (IS_VALLEYVIEW(dev))
> + /* Common bit for both MIPI Port A & MIPI Port C */
> + port_ctrl = MIPI_PORT_CTRL(PORT_A);
> +
>   /* Wait till Clock lanes are in LP-00 state for MIPI Port A
>* only. MIPI Port C has no similar bit for checking
>*/
> - if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A)) & AFE_LATCHOUT)
> - == 0x0), 30))
> + if (wait_for(((I915_READ(port_ctrl) & AFE_LATCHOUT)
> + == 0x0), 30))
>   DRM_ERROR("DSI LP not going Low\n");
>  
> - /* Disable MIPI PHY transparent latch
> -  * Common bit for both MIPI Port A & MIPI Port C
> -  */
> - val = I915_READ(MIPI_PORT_CTRL(PORT_A));
> - I915_WRITE(MIPI_PORT_CTRL(PORT_A), val & ~LP_OUTPUT_HOLD);
> + /* Disable MIPI PHY transparent latch */
> + val = I915_READ(port_ctrl);
> + I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
>   usleep_range(1000, 1500);
>  
>   I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
> diff 

Re: [Intel-gfx] [PATCH] drm/i915: make prelim hw msg in log a bit more harsh

[Jani Nikula]

On Fri, 18 Sep 2015, Rob Clark  wrote:
> On Fri, Sep 18, 2015 at 7:59 AM, Jani Nikula
>  wrote:
>> On Fri, 18 Sep 2015, Rob Clark  wrote:
>>> Apparently some people see this message and try to turn on
>>> preliminary_hw_support.  And then for some reason are surprised
>>> when it doesn't work.  So let's set expectations a bit lower.
>>
>> I think the message goes wrong already at the beginning, "hardware
>> requires preliminary hardware support". The hardware really requires
>> full support, but preliminary is all we've got so far, and that's been
>> disabled by default...
>>
>> How about something along the lines of,
>>
>> """
>> This kernel version does not properly support the hardware.
>> Preliminary support disabled by default.
>> See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT or i915.preliminary_hw_support.
>> """
>
> I'm not too picky on the wording, but I think it should include
> something along the lines of "unsupported" or "use at your own risk"
> just to make it clear that you may be left with a dark screen..

I was just tring to avoid writing "unsupported support" there. ;)

> I kinda think we should also drop
> CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT too and leave only the module

I think that was for distros so they wouldn't have to enable the module
parameter if they take their chances.

> param (since the config option encourages one to build a kernel that
> won't work unless you know to override i915.reliminary_hw_support in
> grub.
>
> After that, perhaps switch to module_param_named_unsafe() for good measure..

Actually I'm slightly surprised it isn't already. I take it that alone
isn't enough of a "sharp edges inside" warning for you?

BR,
Jani.


>
> BR,
> -R
>
>> BR,
>> Jani.
>>
>>
>>
>>>
>>> Signed-off-by: Rob Clark 
>>> ---
>>>  drivers/gpu/drm/i915/i915_drv.c | 3 ++-
>>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.c 
>>> b/drivers/gpu/drm/i915/i915_drv.c
>>> index 8edcec8..5e87fe1 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.c
>>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>>> @@ -926,7 +926,8 @@ static int i915_pci_probe(struct pci_dev *pdev, const 
>>> struct pci_device_id *ent)
>>>
>>>   if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
>>>   DRM_INFO("This hardware requires preliminary hardware 
>>> support.\n"
>>> -  "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or 
>>> modparam preliminary_hw_support\n");
>>> +  "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or 
>>> modparam preliminary_hw_support.\n"
>>> +  "Note that preliminary hw support is unsupported, 
>>> use at your own risk!\n");
>>>   return -ENODEV;
>>>   }
>>>
>>> --
>>> 2.4.3
>>>
>>> ___
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>>
>> --
>> Jani Nikula, Intel Open Source Technology Center

-- 
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Re: [Intel-gfx] [BXT MIPI PATCH v3 10/14] drm/i915/bxt: get DSI pixelclock

[Jani Nikula]

On Tue, 01 Sep 2015, Uma Shankar  wrote:
> From: Shashank Sharma 
>
> BXT's DSI PLL is different from that of VLV. So this patch
> adds a new function to get the current DSI pixel clock based
> on the PLL divider ratio and lane count.
>
> This function is required for intel_dsi_get_config() function.
>
> v2: Fixed Jani's review comments.
>
> Signed-off-by: Shashank Sharma 
> Signed-off-by: Uma Shankar 

Reviewed-by: Jani Nikula 


> ---
>  drivers/gpu/drm/i915/intel_dsi.c |8 ++--
>  drivers/gpu/drm/i915/intel_dsi.h |1 +
>  drivers/gpu/drm/i915/intel_dsi_pll.c |   35 
> ++
>  3 files changed, 42 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c 
> b/drivers/gpu/drm/i915/intel_dsi.c
> index 001569b..6a0071f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -687,7 +687,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder 
> *encoder,
>  static void intel_dsi_get_config(struct intel_encoder *encoder,
>struct intel_crtc_state *pipe_config)
>  {
> - u32 pclk;
> + u32 pclk = 0;
>   DRM_DEBUG_KMS("\n");
>  
>   /*
> @@ -696,7 +696,11 @@ static void intel_dsi_get_config(struct intel_encoder 
> *encoder,
>*/
>   pipe_config->dpll_hw_state.dpll_md = 0;
>  
> - pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
> + if (IS_BROXTON(encoder->base.dev))
> + pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
> + else if (IS_VALLEYVIEW(encoder->base.dev))
> + pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
> +
>   if (!pclk)
>   return;
>  
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h 
> b/drivers/gpu/drm/i915/intel_dsi.h
> index 078ea1b..24fc550 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -124,6 +124,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct 
> drm_encoder *encoder)
>  extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
>  extern void intel_disable_dsi_pll(struct intel_encoder *encoder);
>  extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
> +extern u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
>  extern void intel_dsi_reset_clocks(struct intel_encoder *encoder,
>   enum port port);
>  
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c 
> b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 918bc5f..9860bb5 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -389,6 +389,41 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int 
> pipe_bpp)
>   return pclk;
>  }
>  
> +u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
> +{
> + u32 pclk;
> + u32 dsi_clk;
> + u32 dsi_ratio;
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
> + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> +
> + /* Divide by zero */
> + if (!pipe_bpp) {
> + DRM_ERROR("Invalid BPP(0)\n");
> + return 0;
> + }
> +
> + dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) &
> + BXT_DSI_PLL_RATIO_MASK;
> +
> + /* Invalid DSI ratio ? */
> + if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
> + dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
> + DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio);
> + return 0;
> + }
> +
> + dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
> +
> + /* pixel_format and pipe_bpp should agree */
> + assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
> +
> + pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp);
> +
> + DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk);
> + return pclk;
> +}
> +
>  void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
>  {
>   u32 temp;
> -- 
> 1.7.9.5
>

-- 
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Re: [Intel-gfx] [PATCH] drm/i915: make prelim hw msg in log a bit more harsh

[Rob Clark]

On Fri, Sep 18, 2015 at 10:01 AM, Jani Nikula
 wrote:
> On Fri, 18 Sep 2015, Rob Clark  wrote:
>> On Fri, Sep 18, 2015 at 7:59 AM, Jani Nikula
>>  wrote:
>>> On Fri, 18 Sep 2015, Rob Clark  wrote:
 Apparently some people see this message and try to turn on
 preliminary_hw_support.  And then for some reason are surprised
 when it doesn't work.  So let's set expectations a bit lower.
>>>
>>> I think the message goes wrong already at the beginning, "hardware
>>> requires preliminary hardware support". The hardware really requires
>>> full support, but preliminary is all we've got so far, and that's been
>>> disabled by default...
>>>
>>> How about something along the lines of,
>>>
>>> """
>>> This kernel version does not properly support the hardware.
>>> Preliminary support disabled by default.
>>> See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT or i915.preliminary_hw_support.
>>> """
>>
>> I'm not too picky on the wording, but I think it should include
>> something along the lines of "unsupported" or "use at your own risk"
>> just to make it clear that you may be left with a dark screen..
>
> I was just tring to avoid writing "unsupported support" there. ;)
>
>> I kinda think we should also drop
>> CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT too and leave only the module
>
> I think that was for distros so they wouldn't have to enable the module
> parameter if they take their chances.

I'm not sure that is something to be encouraged.. at least it has been
my experience that people enable this option and then file bug reports
when they end up with a non-booting system ;-)

>> param (since the config option encourages one to build a kernel that
>> won't work unless you know to override i915.reliminary_hw_support in
>> grub.
>>
>> After that, perhaps switch to module_param_named_unsafe() for good measure..
>
> Actually I'm slightly surprised it isn't already. I take it that alone
> isn't enough of a "sharp edges inside" warning for you?

well, _unsafe() makes more sense if we drop the config option, ie. we
shouldn't taint the kernel if you are overriding to *disable* prelim..

it would almost be enough 'sharp edges', except that if you wind up
with a non-booting kernel and no display and never see the tainted
kernel warning ;-)

BR,
-R

> BR,
> Jani.
>
>
>>
>> BR,
>> -R
>>
>>> BR,
>>> Jani.
>>>
>>>
>>>

 Signed-off-by: Rob Clark 
 ---
  drivers/gpu/drm/i915/i915_drv.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

 diff --git a/drivers/gpu/drm/i915/i915_drv.c 
 b/drivers/gpu/drm/i915/i915_drv.c
 index 8edcec8..5e87fe1 100644
 --- a/drivers/gpu/drm/i915/i915_drv.c
 +++ b/drivers/gpu/drm/i915/i915_drv.c
 @@ -926,7 +926,8 @@ static int i915_pci_probe(struct pci_dev *pdev, const 
 struct pci_device_id *ent)

   if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
   DRM_INFO("This hardware requires preliminary hardware 
 support.\n"
 -  "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or 
 modparam preliminary_hw_support\n");
 +  "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or 
 modparam preliminary_hw_support.\n"
 +  "Note that preliminary hw support is unsupported, 
 use at your own risk!\n");
   return -ENODEV;
   }

 --
 2.4.3

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>>>
>>> --
>>> Jani Nikula, Intel Open Source Technology Center
>
> --
> Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH] drm/i915: Do not hardcode s_max, ss_max and eu_mask for BXT

[Arun Siluvery]

On 17/09/2015 19:26, Dongwon Kim wrote:

We can calculate BXT values correctly from GFX fuse values without
hardcoding special limits.

Cc: Imre Deak 
Cc: Matthew D Roper 
signed-off-by: Dongwon Kim 
---
  drivers/gpu/drm/i915/i915_dma.c | 11 ---
  1 file changed, 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 066a0ef..4fe82d7 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -631,17 +631,6 @@ static void gen9_sseu_info_init(struct drm_device *dev)
u32 fuse2, s_enable, ss_disable, eu_disable;
u8 eu_mask = 0xff;

-   /*
-* BXT has a single slice. BXT also has at most 6 EU per subslice,
-* and therefore only the lowest 6 bits of the 8-bit EU disable
-* fields are valid.
-   */
-   if (IS_BROXTON(dev)) {
-   s_max = 1;
-   eu_max = 6;
-   eu_mask = 0x3f;
-   }
-
info = (struct intel_device_info *)_priv->info;
fuse2 = I915_READ(GEN8_FUSE2);
s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>



Without this change we are actually getting incorrect values in 'SSEU 
Device Info',


# cat i915_sseu_status
SSEU Device Info
  Available Slice Total: 1
  Available Subslice Total: 3
  Available Subslice Per Slice: 3
  Available EU Total: 15
  Available EU Per Subslice: 5
  Has Slice Power Gating: no
  Has Subslice Power Gating: yes
  Has EU Power Gating: yes
SSEU Device Status
  Enabled Slice Total: 1
  Enabled Subslice Total: 3
  Enabled Subslice Per Slice: 3
  Enabled EU Total: 18
  Enabled EU Per Subslice: 6

Looks good to me,
Reviewed-by: Arun Siluvery 

regards
Arun


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Re: [Intel-gfx] [PATCH] tests/gem_ctx_param_basic: fix up non-root-set-no-zeromap subtest

[Thomas Wood]

On 18 September 2015 at 17:02, Jesse Barnes  wrote:
> On 09/18/2015 03:22 AM, Thomas Wood wrote:
>> It's helpful to include "i-g-t" in the subject line for
>> intel-gpu-tools patches so that they are easily identified. This can
>> be done by using the --subject-prefix "PATCH i-g-t" option when using
>> git format-patch or send-email and can also be set as a local
>> configuration option using the following command: git config
>> format.subjectprefix "PATCH i-g-t"
>
> Yeah you mentioned this before and I forgot, sorry.  I'll add git configs to 
> my igt repos so make it happen automatically.
>
>> On 17 September 2015 at 17:41, Jesse Barnes  wrote:
>>> This subtest is trying to set the no-zeromap flag on the context without
>>> root privs.  Rather than expecting an EPERM on what's presumably a
>>> nonzero value, we should expect success on a set call w/o root privs.
>>> This looks like a copy & paste error from when the subtest was added,
>>> since setting the ban period has different expected behavior.
>>
>> There is already a patch for this: 
>> http://patchwork.freedesktop.org/patch/58991/
>>
>> I was waiting for confirmation on the expected behaviour, but also
>> testing both root and non-root for success seems a bit redundant.
>> Perhaps removing the root-set test would be worthwhile.
>
> Yeah that would be ok too.  FWIW the other patch has my r-b too, though I 
> haven't heard back from David.
>
> Do you want to commit Daniele's patch or should I just push mine?

Thanks for the review, I've pushed Daniele's patch with your
reviewed-by tag as I already had it queued.


>
> Thanks,
> Jesse
>
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[Intel-gfx] [PATCH] drm/i915/bxt: Update revision id for BXT C0

[Arun Siluvery]

Cc: Nick Hoath 
Cc: Imre Deak 
Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5e30893..7c50973 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2499,7 +2499,7 @@ struct drm_i915_cmd_table {
 
 #define BXT_REVID_A0   (0x0)
 #define BXT_REVID_B0   (0x3)
-#define BXT_REVID_C0   (0x6)
+#define BXT_REVID_C0   (0x9)
 
 /*
  * The genX designation typically refers to the render engine, so render
-- 
1.9.1

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[Intel-gfx] [PATCH 01/43] drm/i915: Don't pass sdvo_reg to intel_sdvo_select_{ddc, i2c}_bus()

[ville . syrjala]

From: Ville Syrjälä 

intel_sdvo_select_ddc_bus() and intel_sdvo_select_i2c_bus() have no used
for the passed in 'reg', so just drop it.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_sdvo.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c 
b/drivers/gpu/drm/i915/intel_sdvo.c
index ca3dd7c..05521b5 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -,7 +,7 @@ intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
  */
 static void
 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
- struct intel_sdvo *sdvo, u32 reg)
+ struct intel_sdvo *sdvo)
 {
struct sdvo_device_mapping *mapping;
 
@@ -2239,7 +2239,7 @@ intel_sdvo_select_ddc_bus(struct drm_i915_private 
*dev_priv,
 
 static void
 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
- struct intel_sdvo *sdvo, u32 reg)
+ struct intel_sdvo *sdvo)
 {
struct sdvo_device_mapping *mapping;
u8 pin;
@@ -2925,7 +2925,7 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t 
sdvo_reg, bool is_sdvob)
intel_sdvo->sdvo_reg = sdvo_reg;
intel_sdvo->is_sdvob = is_sdvob;
intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 
1;
-   intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
+   intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo);
if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
goto err_i2c_bus;
 
@@ -2987,7 +2987,7 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t 
sdvo_reg, bool is_sdvob)
 */
intel_sdvo->base.cloneable = 0;
 
-   intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
+   intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo);
 
/* Set the input timing to the screen. Assume always input 0. */
if (!intel_sdvo_set_target_input(intel_sdvo))
-- 
2.4.6

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[Intel-gfx] [PATCH 04/43] drm/i915: Parametrize fence registers

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_gem_fence.c | 42 +--
 drivers/gpu/drm/i915/i915_gpu_error.c | 21 --
 drivers/gpu/drm/i915/i915_reg.h   | 12 +-
 3 files changed, 37 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c 
b/drivers/gpu/drm/i915/i915_gem_fence.c
index 6077dff..ff94560 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence.c
@@ -59,19 +59,19 @@ static void i965_write_fence_reg(struct drm_device *dev, 
int reg,
 struct drm_i915_gem_object *obj)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
-   int fence_reg;
+   int fence_reg_lo, fence_reg_hi;
int fence_pitch_shift;
 
if (INTEL_INFO(dev)->gen >= 6) {
-   fence_reg = FENCE_REG_SANDYBRIDGE_0;
-   fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
+   fence_reg_lo = FENCE_REG_GEN6_LO(reg);
+   fence_reg_hi = FENCE_REG_GEN6_HI(reg);
+   fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
} else {
-   fence_reg = FENCE_REG_965_0;
+   fence_reg_lo = FENCE_REG_965_LO(reg);
+   fence_reg_hi = FENCE_REG_965_HI(reg);
fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
}
 
-   fence_reg += reg * 8;
-
/* To w/a incoherency with non-atomic 64-bit register updates,
 * we split the 64-bit update into two 32-bit writes. In order
 * for a partial fence not to be evaluated between writes, we
@@ -81,8 +81,8 @@ static void i965_write_fence_reg(struct drm_device *dev, int 
reg,
 * For extra levels of paranoia, we make sure each step lands
 * before applying the next step.
 */
-   I915_WRITE(fence_reg, 0);
-   POSTING_READ(fence_reg);
+   I915_WRITE(fence_reg_lo, 0);
+   POSTING_READ(fence_reg_lo);
 
if (obj) {
u32 size = i915_gem_obj_ggtt_size(obj);
@@ -103,14 +103,14 @@ static void i965_write_fence_reg(struct drm_device *dev, 
int reg,
val |= 1 << I965_FENCE_TILING_Y_SHIFT;
val |= I965_FENCE_REG_VALID;
 
-   I915_WRITE(fence_reg + 4, val >> 32);
-   POSTING_READ(fence_reg + 4);
+   I915_WRITE(fence_reg_hi, val >> 32);
+   POSTING_READ(fence_reg_hi);
 
-   I915_WRITE(fence_reg + 0, val);
-   POSTING_READ(fence_reg);
+   I915_WRITE(fence_reg_lo, val);
+   POSTING_READ(fence_reg_lo);
} else {
-   I915_WRITE(fence_reg + 4, 0);
-   POSTING_READ(fence_reg + 4);
+   I915_WRITE(fence_reg_hi, 0);
+   POSTING_READ(fence_reg_hi);
}
 }
 
@@ -118,7 +118,7 @@ static void i915_write_fence_reg(struct drm_device *dev, 
int reg,
 struct drm_i915_gem_object *obj)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
-   u32 val;
+   u32 fence_reg, val;
 
if (obj) {
u32 size = i915_gem_obj_ggtt_size(obj);
@@ -150,12 +150,12 @@ static void i915_write_fence_reg(struct drm_device *dev, 
int reg,
val = 0;
 
if (reg < 8)
-   reg = FENCE_REG_830_0 + reg * 4;
+   fence_reg = FENCE_REG_830(reg);
else
-   reg = FENCE_REG_945_8 + (reg - 8) * 4;
+   fence_reg = FENCE_REG_945_8(reg);
 
-   I915_WRITE(reg, val);
-   POSTING_READ(reg);
+   I915_WRITE(fence_reg, val);
+   POSTING_READ(fence_reg);
 }
 
 static void i830_write_fence_reg(struct drm_device *dev, int reg,
@@ -186,8 +186,8 @@ static void i830_write_fence_reg(struct drm_device *dev, 
int reg,
} else
val = 0;
 
-   I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
-   POSTING_READ(FENCE_REG_830_0 + reg * 4);
+   I915_WRITE(FENCE_REG_830(reg), val);
+   POSTING_READ(FENCE_REG_830(reg));
 }
 
 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 3379f9c..e873eb4 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -787,19 +787,16 @@ static void i915_gem_record_fences(struct drm_device *dev,
 
if (IS_GEN3(dev) || IS_GEN2(dev)) {
for (i = 0; i < 8; i++)
-   error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
-   if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
-   for (i = 0; i < 8; i++)
-   error->fence[i+8] = I915_READ(FENCE_REG_945_8 +
- (i * 4));
-   } else if (IS_GEN5(dev) || IS_GEN4(dev))
-   

[Intel-gfx] [PATCH 02/43] drm/i915: Parametrize LRC registers

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 8 
 drivers/gpu/drm/i915/intel_lrc.c| 8 +++-
 drivers/gpu/drm/i915/intel_lrc.h| 6 --
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 72ae347..5615d3d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2069,8 +2069,8 @@ static int i915_execlists(struct seq_file *m, void *data)
 
seq_printf(m, "%s\n", ring->name);
 
-   status = I915_READ(RING_EXECLIST_STATUS(ring));
-   ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
+   status = I915_READ(RING_EXECLIST_STATUS_LO(ring));
+   ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(ring));
seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
   status, ctx_id);
 
@@ -2085,8 +2085,8 @@ static int i915_execlists(struct seq_file *m, void *data)
   read_pointer, write_pointer);
 
for (i = 0; i < 6; i++) {
-   status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
-   ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i 
+ 4);
+   status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i));
+   ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i));
 
seq_printf(m, "\tStatus buffer %d: 0x%08X, context: 
%u\n",
   i, status, ctx_id);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index fe06accb0..ca9f161 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -349,7 +349,7 @@ static void execlists_elsp_write(struct 
drm_i915_gem_request *rq0,
I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[0]));
 
/* ELSP is a wo register, use another nearby reg for posting */
-   POSTING_READ_FW(RING_EXECLIST_STATUS(ring));
+   POSTING_READ_FW(RING_EXECLIST_STATUS_LO(ring));
intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
spin_unlock(_priv->uncore.lock);
 }
@@ -519,10 +519,8 @@ void intel_lrc_irq_handler(struct intel_engine_cs *ring)
 
while (read_pointer < write_pointer) {
read_pointer++;
-   status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
-   (read_pointer % 6) * 8);
-   status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
-   (read_pointer % 6) * 8 + 4);
+   status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, 
read_pointer % 6));
+   status_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, 
read_pointer % 6));
 
if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
continue;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 69d99f0..8a08a27 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -28,12 +28,14 @@
 
 /* Execlists regs */
 #define RING_ELSP(ring)((ring)->mmio_base+0x230)
-#define RING_EXECLIST_STATUS(ring) ((ring)->mmio_base+0x234)
+#define RING_EXECLIST_STATUS_LO(ring)  ((ring)->mmio_base+0x234)
+#define RING_EXECLIST_STATUS_HI(ring)  ((ring)->mmio_base+0x234 + 4)
 #define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244)
 #define  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH   (1 << 3)
 #define  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT   (1 << 0)
 #define   CTX_CTRL_RS_CTX_ENABLE(1 << 1)
-#define RING_CONTEXT_STATUS_BUF(ring)  ((ring)->mmio_base+0x370)
+#define RING_CONTEXT_STATUS_BUF_LO(ring, i)((ring)->mmio_base+0x370 + (i) 
* 8)
+#define RING_CONTEXT_STATUS_BUF_HI(ring, i)((ring)->mmio_base+0x370 + (i) 
* 8 + 4)
 #define RING_CONTEXT_STATUS_PTR(ring)  ((ring)->mmio_base+0x3a0)
 
 /* Logical Rings */
-- 
2.4.6

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[Intel-gfx] [PATCH 10/43] drm/i915: Parametrize CSR_PROGRAM registers

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_csr.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index b69264d..8174335 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -48,7 +48,7 @@ MODULE_FIRMWARE(I915_CSR_SKL);
 /*
 * SKL CSR registers for DC5 and DC6
 */
-#define CSR_PROGRAM_BASE   0x8
+#define CSR_PROGRAM(i) (0x8 + (i) * 4)
 #define CSR_SSP_BASE_ADDR_GEN9 0x2FC0
 #define CSR_HTP_ADDR_SKL   0x00500034
 #define CSR_SSP_BASE   0x8F074
@@ -255,8 +255,7 @@ void intel_csr_load_program(struct drm_device *dev)
mutex_lock(_priv->csr_lock);
fw_size = dev_priv->csr.dmc_fw_size;
for (i = 0; i < fw_size; i++)
-   I915_WRITE(CSR_PROGRAM_BASE + i * 4,
-   payload[i]);
+   I915_WRITE(CSR_PROGRAM(i), payload[i]);
 
for (i = 0; i < dev_priv->csr.mmio_count; i++) {
I915_WRITE(dev_priv->csr.mmioaddr[i],
@@ -456,7 +455,7 @@ void assert_csr_loaded(struct drm_i915_private *dev_priv)
 {
WARN_ONCE(intel_csr_load_status_get(dev_priv) != FW_LOADED,
  "CSR is not loaded.\n");
-   WARN_ONCE(!I915_READ(CSR_PROGRAM_BASE),
+   WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
  "CSR program storage start is NULL\n");
WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
-- 
2.4.6

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Re: [Intel-gfx] [RFC][PATCH 43/43] WIP: drm/i915: Type safe register read/write

[Chris Wilson]

On Fri, Sep 18, 2015 at 08:43:27PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 18, 2015 at 06:33:38PM +0100, Chris Wilson wrote:
> > On Fri, Sep 18, 2015 at 08:03:56PM +0300, ville.syrj...@linux.intel.com 
> > wrote:
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 140076d..0589aba 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -25,16 +25,28 @@
> > >  #ifndef _I915_REG_H_
> > >  #define _I915_REG_H_
> > >  
> > > +struct i915_reg {
> > > + uint32_t reg;
> > > +};
> > 
> > Fundamental objection averted. Maybe even typedef it to hide the struct,
> > ignornace is bliss.  i915_reg_t reg; looks reasonable in this instance.
> 
> Yeah typedef would make it less ugly. Maybe i915_mmio_reg_t or something,
> so we can add other register types?

Yes. Separating out the display/mmio/gpio registers would be nice, that
should spawn a few functions that can check we don't add the wrong base
(if any such remain!). It would mean we end up with a construct like
union i915_reg {
i915_gt_reg_t gt;
i915_mmio_reg_t mmio;
i915_gpio_reg_t gpio;
i915_display_reg_t display;
};
and typecasting when we try to write a register. Or maybe we just have
more typesafe helpers that call the private vfuncs. It may even be a net
reduction in code size, since we move all the addition of display
offsets into a central location. However, it looks like it may just be
an inconvenient mess.

> > The downside with this patch is that we have a lot of places that cares
> > about the reg.reg,
> 
> That is a bit annoying, yes. I think most of those are in the ring code
> where we emit LRIs. I suppose we could add a special version of ring_emit
> that takes the struct and thus hides the reg.reg part from the calling
> code?

Right, even just adding an inline can be down in a preceding patch and
so reduce churn here and extends the typesafety argument for LRI as
well (and SRM).

I half considered a function to return the raw offset from a struct i915_reg,
that is only marginally better than adding .reg (but only in the case
where we end up with a few very similar i915_reg structs). But it
doesn't actually reduce the churn... unless you add a stub in a previous
patch such that any location that wants to use the register offset as a
value is converted first.
 
> > and even more where we make up reg on the fly, so it
> > looks like we are just doing I915_WRITE(_REG(old_u32), x) i.e. more or
> > less subverting the extra safety, and we would still want something like
> > 
> > i915_write16(reg) { WARN_ON(reg & 1); }
> > i915_write32(reg) { WARN_ON(reg & 3); }
> > 
> > to catch the class of bug where we create an invalid reg address.
> 
> I've killed off almost all of the "make up regs on the fly" in the prep
> work. I think what was left were vgpu and the 2x32 register read ioctl.
> I don't recall any other significant places off the top of my head.

Never underestimate the cunning of the lazy programmer. Not that I want
to add any more instructions to register access. Going forward, I guess
the rule is to scrutinize _REG() etc very careful and limit them to headers?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH] tests/gem_ctx_param_basic: fix up non-root-set-no-zeromap subtest

[Jesse Barnes]

On 09/18/2015 03:22 AM, Thomas Wood wrote:
> It's helpful to include "i-g-t" in the subject line for
> intel-gpu-tools patches so that they are easily identified. This can
> be done by using the --subject-prefix "PATCH i-g-t" option when using
> git format-patch or send-email and can also be set as a local
> configuration option using the following command: git config
> format.subjectprefix "PATCH i-g-t"

Yeah you mentioned this before and I forgot, sorry.  I'll add git configs to my 
igt repos so make it happen automatically.

> On 17 September 2015 at 17:41, Jesse Barnes  wrote:
>> This subtest is trying to set the no-zeromap flag on the context without
>> root privs.  Rather than expecting an EPERM on what's presumably a
>> nonzero value, we should expect success on a set call w/o root privs.
>> This looks like a copy & paste error from when the subtest was added,
>> since setting the ban period has different expected behavior.
> 
> There is already a patch for this: 
> http://patchwork.freedesktop.org/patch/58991/
> 
> I was waiting for confirmation on the expected behaviour, but also
> testing both root and non-root for success seems a bit redundant.
> Perhaps removing the root-set test would be worthwhile.

Yeah that would be ok too.  FWIW the other patch has my r-b too, though I 
haven't heard back from David.

Do you want to commit Daniele's patch or should I just push mine?

Thanks,
Jesse

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[Intel-gfx] [PATCH 3/5] drm/i915: Add dmc firmware version to error state

[Mika Kuoppala]

We have had one case where buggy csr/dmc firmware version influenced
gt side and caused a hang. Add dmc firmware version to error state.

Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 3379f9c..fef708d 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -366,6 +366,8 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf 
*m,
err_printf(m, "Suspend count: %u\n", error->suspend_count);
err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
+   err_printf(m, "DMC fw: %u.%u\n", dev_priv->csr.dmc_ver_major,
+  dev_priv->csr.dmc_ver_minor);
err_printf(m, "EIR: 0x%08x\n", error->eir);
err_printf(m, "IER: 0x%08x\n", error->ier);
if (INTEL_INFO(dev)->gen >= 8) {
-- 
2.1.4

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[Intel-gfx] [PATCH 1/5] drm/i915: Store and print dmc firmware version

[Mika Kuoppala]

Parse csr/dmc firmware version and augment debug message
by printing it.

Cc: Animesh Manna 
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_drv.h  | 2 ++
 drivers/gpu/drm/i915/intel_csr.c | 7 ++-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3bf8a9b..17e8b25 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -755,6 +755,8 @@ struct intel_csr {
const char *fw_path;
uint32_t *dmc_payload;
uint32_t dmc_fw_size;
+   uint16_t dmc_ver_major;
+   uint16_t dmc_ver_minor;
uint32_t mmio_count;
uint32_t mmioaddr[8];
uint32_t mmiodata[8];
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index b69264d..58edc3f 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -377,11 +377,16 @@ static void finish_csr_load(const struct firmware *fw, 
void *context)
dmc_payload = csr->dmc_payload;
memcpy(dmc_payload, >data[readcount], nbytes);
 
+   csr->dmc_ver_major = dmc_header->header_ver;
+   csr->dmc_ver_minor = ((dmc_header->fw_version & 0x) >> 16) * 10
+   + (dmc_header->fw_version & 0x);
+
/* load csr program during system boot, as needed for DC states */
intel_csr_load_program(dev);
fw_loaded = true;
 
-   DRM_DEBUG_KMS("Finished loading %s\n", dev_priv->csr.fw_path);
+   DRM_DEBUG_KMS("Finished loading %s v%u.%u\n", dev_priv->csr.fw_path,
+ csr->dmc_ver_major, csr->dmc_ver_minor);
 out:
if (fw_loaded)
intel_runtime_pm_put(dev_priv);
-- 
2.1.4

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[Intel-gfx] [PATCH 5/5] drm/i915: Add dmc firmware debugfs status entry

[Mika Kuoppala]

Add debugfs entry for csr/dmc fw to inspect firmware
loading status and version.

Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 32 
 drivers/gpu/drm/i915/i915_reg.h |  5 +
 drivers/gpu/drm/i915/intel_csr.c|  3 ---
 3 files changed, 37 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 72ae347..4a798a6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2509,6 +2509,37 @@ static int i915_guc_log_dump(struct seq_file *m, void 
*data)
return 0;
 }
 
+static int i915_dmc_load_status_info(struct seq_file *m, void *data)
+{
+   struct drm_info_node *node = m->private;
+   struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
+   struct intel_csr *csr = _priv->csr;
+   uint32_t state;
+   const char * const state_str[] = { "uninitialized",
+  "loaded",
+  "failed",
+  "unknown" };
+
+   seq_puts(m, "DMC firmware status:\n");
+
+   mutex_lock(_priv->csr_lock);
+
+   seq_printf(m, "\tpath: %s\n", csr->fw_path);
+   seq_printf(m, "\tfw_ver: %u.%u\n", csr->dmc_ver_major,
+  csr->dmc_ver_minor);
+   seq_printf(m, "\tsize: %u bytes\n", csr->dmc_fw_size * 4);
+   state = (uint32_t)csr->state <= 3 ? csr->state : 3;
+   seq_printf(m, "\tstate: %s\n", state_str[state]);
+
+   seq_printf(m, "\tprogram base: 0x%08x\n", I915_READ(CSR_PROGRAM_BASE));
+   seq_printf(m, "\tssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
+   seq_printf(m, "\thtp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
+
+   mutex_unlock(_priv->csr_lock);
+
+   return 0;
+}
+
 static int i915_edp_psr_status(struct seq_file *m, void *data)
 {
struct drm_info_node *node = m->private;
@@ -5173,6 +5204,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_guc_info", i915_guc_info, 0},
{"i915_guc_load_status", i915_guc_load_status_info, 0},
{"i915_guc_log_dump", i915_guc_log_dump, 0},
+   {"i915_dmc_load_status", i915_dmc_load_status_info, 0},
{"i915_frequency_info", i915_frequency_info, 0},
{"i915_hangcheck_info", i915_hangcheck_info, 0},
{"i915_drpc_info", i915_drpc_info, 0},
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 67bf205..cd040ff 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7977,4 +7977,9 @@ enum skl_disp_power_wells {
 #define GEN9_VEBOX_MOCS_0  0xcb00  /* Video MOCS base register*/
 #define GEN9_BLT_MOCS_00xcc00  /* Blitter MOCS base register*/
 
+/* DMC/CSR firmware */
+#define CSR_PROGRAM_BASE   0x8
+#define CSR_SSP_BASE   0x8F074
+#define CSR_HTP_SKL0x8F004
+
 #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 73807c3..876c839 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -51,11 +51,8 @@ MODULE_FIRMWARE(I915_CSR_SKL);
 /*
 * SKL CSR registers for DC5 and DC6
 */
-#define CSR_PROGRAM_BASE   0x8
 #define CSR_SSP_BASE_ADDR_GEN9 0x2FC0
 #define CSR_HTP_ADDR_SKL   0x00500034
-#define CSR_SSP_BASE   0x8F074
-#define CSR_HTP_SKL0x8F004
 #define CSR_LAST_WRITE 0x8F034
 #define CSR_LAST_WRITE_VALUE   0xc003b400
 /* MMIO address range for CSR program (0x8 - 0x82FFF) */
-- 
2.1.4

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[Intel-gfx] [PATCH 4/5] drm/i915: Add pci device revision to error state

[Mika Kuoppala]

We have codepaths that branch using the revision of the device.
Add pci revision to error state.

Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index fef708d..a29377e 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -364,7 +364,8 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf 
*m,
}
err_printf(m, "Reset count: %u\n", error->reset_count);
err_printf(m, "Suspend count: %u\n", error->suspend_count);
-   err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
+   err_printf(m, "PCI ID: 0x%04x (rev %02x)\n", dev->pdev->device,
+  dev->pdev->revision);
err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
err_printf(m, "DMC fw: %u.%u\n", dev_priv->csr.dmc_ver_major,
   dev_priv->csr.dmc_ver_minor);
-- 
2.1.4

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[Intel-gfx] [PATCH 2/5] drm/i915: Notify user about outdated dmc firmware

[Mika Kuoppala]

If csr/dmc firmware is known to be outdated, notify
user.

Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_csr.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 58edc3f..73807c3 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -45,6 +45,9 @@
 
 MODULE_FIRMWARE(I915_CSR_SKL);
 
+#define RECOMMENDED_FW_MAJOR   1
+#define RECOMMENDED_FW_MINOR   21
+
 /*
 * SKL CSR registers for DC5 and DC6
 */
@@ -387,6 +390,12 @@ static void finish_csr_load(const struct firmware *fw, 
void *context)
 
DRM_DEBUG_KMS("Finished loading %s v%u.%u\n", dev_priv->csr.fw_path,
  csr->dmc_ver_major, csr->dmc_ver_minor);
+
+   if (csr->dmc_ver_major < RECOMMENDED_FW_MAJOR ||
+   csr->dmc_ver_minor < RECOMMENDED_FW_MINOR)
+   DRM_INFO("Outdated dmc firmware found, please upgrade to %u.%u 
or newer\n",
+RECOMMENDED_FW_MAJOR, RECOMMENDED_FW_MINOR);
+
 out:
if (fw_loaded)
intel_runtime_pm_put(dev_priv);
-- 
2.1.4

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[Intel-gfx] [PATCH 05/43] drm/i915: Parametrize FBC_TAG registers

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  | 2 +-
 drivers/gpu/drm/i915/intel_fbc.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b1cf17a..fcd1e81 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2013,7 +2013,7 @@ enum skl_disp_power_wells {
 #define   FBC_CTL_CPU_FENCE(1<<1)
 #define   FBC_CTL_PLANE(plane) ((plane)<<0)
 #define FBC_FENCE_OFF  0x03218 /* BSpec typo has 321Bh */
-#define FBC_TAG0x03300
+#define FBC_TAG(i) (0x03300 + (i) * 4)
 
 #define FBC_STATUS20x43214
 #define  FBC_COMPRESSION_MASK  0x7ff
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 1f97fb5..f8c527f 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -88,7 +88,7 @@ static void i8xx_fbc_enable(struct intel_crtc *crtc)
 
/* Clear old tags */
for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
-   I915_WRITE(FBC_TAG + (i * 4), 0);
+   I915_WRITE(FBC_TAG(i), 0);
 
if (IS_GEN4(dev_priv)) {
u32 fbc_ctl2;
-- 
2.4.6

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[Intel-gfx] [PATCH 06/43] drm/i915: Parametrize ILK turbo registers

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h | 10 +-
 drivers/gpu/drm/i915/intel_pm.c | 14 +++---
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fcd1e81..b95f7f1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2576,7 +2576,7 @@ enum skl_disp_power_wells {
 #define   TSFS_INTR_MASK   0x00ff
 
 #define CRSTANDVID 0x11100
-#define PXVFREQ_BASE   0x0 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) 
*/
+#define PXVFREQ(i) (0x0 + (i) * 4) /* P[0-15]VIDFREQ (0x1114c) 
(Ironlake) */
 #define   PXVFREQ_PX_MASK  0x7f00
 #define   PXVFREQ_PX_SHIFT 24
 #define VIDFREQ_BASE   0x0
@@ -2760,8 +2760,8 @@ enum skl_disp_power_wells {
 #define CSIEW0 0x11250
 #define CSIEW1 0x11254
 #define CSIEW2 0x11258
-#define PEW0x1125c
-#define DEW0x11270
+#define PEW(i) (0x1125c + (i) * 4) /* 5 registers */
+#define DEW(i) (0x11270 + (i) * 4) /* 3 registers */
 #define MCHAFE 0x112c0
 #define CSIEC  0x112e0
 #define DMIEC  0x112e4
@@ -2785,8 +2785,8 @@ enum skl_disp_power_wells {
 #define EG50x11624
 #define EG60x11628
 #define EG70x1162c
-#define PXW0x11664
-#define PXWL   0x11680
+#define PXW(i) (0x11664 + (i) * 4) /* 4 registers */
+#define PXWL(i)(0x11680 + (i) * 4) /* 8 registers */
 #define LCFUSE02   0x116c0
 #define   LCFUSE_HIV_MASK  0x00ff
 #define CSIPLL00x12c10
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 62de97e..0320675 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4274,7 +4274,7 @@ static void ironlake_enable_drps(struct drm_device *dev)
fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
MEMMODE_FSTART_SHIFT;
 
-   vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
+   vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
PXVFREQ_PX_SHIFT;
 
dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
@@ -5877,7 +5877,7 @@ static unsigned long __i915_gfx_val(struct 
drm_i915_private *dev_priv)
 
assert_spin_locked(_lock);
 
-   pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
+   pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
pxvid = (pxvid >> 24) & 0x7f;
ext_v = pvid_to_extvid(dev_priv, pxvid);
 
@@ -6120,13 +6120,13 @@ static void intel_init_emon(struct drm_device *dev)
I915_WRITE(CSIEW2, 0x0404);
 
for (i = 0; i < 5; i++)
-   I915_WRITE(PEW + (i * 4), 0);
+   I915_WRITE(PEW(i), 0);
for (i = 0; i < 3; i++)
-   I915_WRITE(DEW + (i * 4), 0);
+   I915_WRITE(DEW(i), 0);
 
/* Program P-state weights to account for frequency power adjustment */
for (i = 0; i < 16; i++) {
-   u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
+   u32 pxvidfreq = I915_READ(PXVFREQ(i));
unsigned long freq = intel_pxfreq(pxvidfreq);
unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
PXVFREQ_PX_SHIFT;
@@ -6147,7 +6147,7 @@ static void intel_init_emon(struct drm_device *dev)
for (i = 0; i < 4; i++) {
u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
(pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
-   I915_WRITE(PXW + (i * 4), val);
+   I915_WRITE(PXW(i), val);
}
 
/* Adjust magic regs to magic values (more experimental results) */
@@ -6163,7 +6163,7 @@ static void intel_init_emon(struct drm_device *dev)
I915_WRITE(EG7, 0);
 
for (i = 0; i < 8; i++)
-   I915_WRITE(PXWL + (i * 4), 0);
+   I915_WRITE(PXWL(i), 0);
 
/* Enable PMON + select events */
I915_WRITE(ECR, 0x8019);
-- 
2.4.6

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[Intel-gfx] [PATCH 14/43] drm/i915: Include MCHBAR_MIRROR_BASE in ILK_GDSR

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h |  2 +-
 drivers/gpu/drm/i915/intel_uncore.c | 10 +-
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a04fa2a..610ce25 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -105,7 +105,7 @@
 #define  GRDOM_RESET_STATUS (1<<1)
 #define  GRDOM_RESET_ENABLE (1<<0)
 
-#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
+#define ILK_GDSR (MCHBAR_MIRROR_BASE + 0x2ca4)
 #define  ILK_GRDOM_FULL(0<<1)
 #define  ILK_GRDOM_RENDER  (1<<1)
 #define  ILK_GRDOM_MEDIA   (3<<1)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 440e2a5..3294f63 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1429,21 +1429,21 @@ static int ironlake_do_reset(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
int ret;
 
-   I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
+   I915_WRITE(ILK_GDSR,
   ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
-   ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
+   ret = wait_for((I915_READ(ILK_GDSR) &
ILK_GRDOM_RESET_ENABLE) == 0, 500);
if (ret)
return ret;
 
-   I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
+   I915_WRITE(ILK_GDSR,
   ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
-   ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
+   ret = wait_for((I915_READ(ILK_GDSR) &
ILK_GRDOM_RESET_ENABLE) == 0, 500);
if (ret)
return ret;
 
-   I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0);
+   I915_WRITE(ILK_GDSR, 0);
 
return 0;
 }
-- 
2.4.6

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[Intel-gfx] [PATCH 09/43] drm/i915: Parametrize DDI_BUF_TRANS registers

[ville . syrjala]

From: Ville Syrjälä 

FIXME: Should there be a WARN(i != 9) or something, or what does the
entry 9 comment mean?

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  |  3 ++-
 drivers/gpu/drm/i915/intel_ddi.c | 19 +--
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 13b52f7..61414c8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7194,7 +7194,8 @@ enum skl_disp_power_wells {
 /* DDI Buffer Translations */
 #define DDI_BUF_TRANS_A0x64E00
 #define DDI_BUF_TRANS_B0x64E60
-#define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
+#define DDI_BUF_TRANS_LO(port, i) (_PORT(port, DDI_BUF_TRANS_A, 
DDI_BUF_TRANS_B) + (i) * 8)
+#define DDI_BUF_TRANS_HI(port, i) (_PORT(port, DDI_BUF_TRANS_A, 
DDI_BUF_TRANS_B) + (i) * 8 + 4)
 
 /* Sideband Interface (SBI) is programmed indirectly, via
  * SBI_ADDR, which contains the register offset; and SBI_DATA,
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 5b600bf..9e640ea 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -414,7 +414,6 @@ static void intel_prepare_ddi_buffers(struct drm_device 
*dev, enum port port,
  bool supports_hdmi)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
-   u32 reg;
u32 iboost_bit = 0;
int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
size;
@@ -505,11 +504,11 @@ static void intel_prepare_ddi_buffers(struct drm_device 
*dev, enum port port,
BUG();
}
 
-   for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
-   I915_WRITE(reg, ddi_translations[i].trans1 | iboost_bit);
-   reg += 4;
-   I915_WRITE(reg, ddi_translations[i].trans2);
-   reg += 4;
+   for (i = 0; i < size; i++) {
+   I915_WRITE(DDI_BUF_TRANS_LO(port, i),
+  ddi_translations[i].trans1 | iboost_bit);
+   I915_WRITE(DDI_BUF_TRANS_HI(port, i),
+  ddi_translations[i].trans2);
}
 
if (!supports_hdmi)
@@ -521,10 +520,10 @@ static void intel_prepare_ddi_buffers(struct drm_device 
*dev, enum port port,
hdmi_level = hdmi_default_entry;
 
/* Entry 9 is for HDMI: */
-   I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
-   reg += 4;
-   I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
-   reg += 4;
+   I915_WRITE(DDI_BUF_TRANS_LO(port, i),
+  ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
+   I915_WRITE(DDI_BUF_TRANS_HI(port, i),
+  ddi_translations_hdmi[hdmi_level].trans2);
 }
 
 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
-- 
2.4.6

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[Intel-gfx] [PATCH 03/43] drm/i915: Parametrize GEN7_GT_SCRATCH and GEN7_LRA_LIMITS

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_drv.c | 8 
 drivers/gpu/drm/i915/i915_reg.h | 4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e2bf9e2..e6d7a69 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1120,7 +1120,7 @@ static void vlv_save_gunit_s0ix_state(struct 
drm_i915_private *dev_priv)
s->gfx_pend_tlb1= I915_READ(GEN7_GFX_PEND_TLB1);
 
for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
-   s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
+   s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
 
s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
s->gfx_max_req_count= I915_READ(GEN7_GFX_MAX_REQ_COUNT);
@@ -1164,7 +1164,7 @@ static void vlv_save_gunit_s0ix_state(struct 
drm_i915_private *dev_priv)
s->pm_ier   = I915_READ(GEN6_PMIER);
 
for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
-   s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
+   s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
 
/* GT SA CZ domain, 0x10-0x138124 */
s->tilectl  = I915_READ(TILECTL);
@@ -1202,7 +1202,7 @@ static void vlv_restore_gunit_s0ix_state(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
 
for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
-   I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
+   I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
 
I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
@@ -1246,7 +1246,7 @@ static void vlv_restore_gunit_s0ix_state(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN6_PMIER,  s->pm_ier);
 
for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
-   I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
+   I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
 
/* GT SA CZ domain, 0x10-0x138124 */
I915_WRITE(TILECTL, s->tilectl);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 67bf205..44cedbf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1527,7 +1527,7 @@ enum skl_disp_power_wells {
 #define GEN7_GFX_PEND_TLB0 0x4034
 #define GEN7_GFX_PEND_TLB1 0x4038
 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
-#define GEN7_LRA_LIMITS_BASE   0x403C
+#define GEN7_LRA_LIMITS(i) (0x403C + (i) * 4)
 #define GEN7_LRA_LIMITS_REG_NUM13
 #define GEN7_MEDIA_MAX_REQ_COUNT   0x4070
 #define GEN7_GFX_MAX_REQ_COUNT 0x4074
@@ -6808,7 +6808,7 @@ enum skl_disp_power_wells {
 GEN6_PM_RP_DOWN_THRESHOLD | \
 GEN6_PM_RP_DOWN_TIMEOUT)
 
-#define GEN7_GT_SCRATCH_BASE   0x4F100
+#define GEN7_GT_SCRATCH(i) (0x4F100 + (i) * 4)
 #define GEN7_GT_SCRATCH_REG_NUM8
 
 #define VLV_GTLC_SURVIVABILITY_REG  0x130098
-- 
2.4.6

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[Intel-gfx] [PATCH 18/43] drm/i915: s/_TRANSA_CHICKEN/TRANS_CHICKEN(PIPE_A)/

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 8 
 drivers/gpu/drm/i915/intel_pm.c  | 4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 7343e14..63cf5eb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2003,9 +2003,9 @@ static void lpt_enable_pch_transcoder(struct 
drm_i915_private *dev_priv,
assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
 
/* Workaround: set timing override bit. */
-   val = I915_READ(_TRANSA_CHICKEN2);
+   val = I915_READ(TRANS_CHICKEN2(PIPE_A));
val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
-   I915_WRITE(_TRANSA_CHICKEN2, val);
+   I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
 
val = TRANS_ENABLE;
pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
@@ -2063,9 +2063,9 @@ static void lpt_disable_pch_transcoder(struct 
drm_i915_private *dev_priv)
DRM_ERROR("Failed to disable PCH transcoder\n");
 
/* Workaround: clear timing override bit. */
-   val = I915_READ(_TRANSA_CHICKEN2);
+   val = I915_READ(TRANS_CHICKEN2(PIPE_A));
val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
-   I915_WRITE(_TRANSA_CHICKEN2, val);
+   I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index dc765eb..0d43d51 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6623,8 +6623,8 @@ static void lpt_init_clock_gating(struct drm_device *dev)
   PCH_LP_PARTITION_LEVEL_DISABLE);
 
/* WADPOClockGatingDisable:hsw */
-   I915_WRITE(_TRANSA_CHICKEN1,
-  I915_READ(_TRANSA_CHICKEN1) |
+   I915_WRITE(TRANS_CHICKEN1(PIPE_A),
+  I915_READ(TRANS_CHICKEN1(PIPE_A)) |
   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
 }
 
-- 
2.4.6

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[Intel-gfx] [PATCH 08/43] drm/i915: Parametrize TV luma/chroma filter registers

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h | 12 
 drivers/gpu/drm/i915/intel_tv.c |  8 
 2 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b95f7f1..13b52f7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4079,14 +4079,10 @@ enum skl_disp_power_wells {
 # define TV_CC_DATA_1_MASK 0x007f
 # define TV_CC_DATA_1_SHIFT0
 
-#define TV_H_LUMA_00x68100
-#define TV_H_LUMA_59   0x681ec
-#define TV_H_CHROMA_0  0x68200
-#define TV_H_CHROMA_59 0x682ec
-#define TV_V_LUMA_00x68300
-#define TV_V_LUMA_42   0x683a8
-#define TV_V_CHROMA_0  0x68400
-#define TV_V_CHROMA_42 0x684a8
+#define TV_H_LUMA(i)   (0x68100 + (i) * 4) /* 60 registers */
+#define TV_H_CHROMA(i) (0x68200 + (i) * 4) /* 60 registers */
+#define TV_V_LUMA(i)   (0x68300 + (i) * 4) /* 43 registers */
+#define TV_V_CHROMA(i) (0x68400 + (i) * 4) /* 43 registers */
 
 /* Display Port */
 #define DP_A   0x64000 /* eDP */
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 29983cba..6bea789 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1138,13 +1138,13 @@ static void intel_tv_pre_enable(struct intel_encoder 
*encoder)
 
j = 0;
for (i = 0; i < 60; i++)
-   I915_WRITE(TV_H_LUMA_0 + (i<<2), tv_mode->filter_table[j++]);
+   I915_WRITE(TV_H_LUMA(i), tv_mode->filter_table[j++]);
for (i = 0; i < 60; i++)
-   I915_WRITE(TV_H_CHROMA_0 + (i<<2), tv_mode->filter_table[j++]);
+   I915_WRITE(TV_H_CHROMA(i), tv_mode->filter_table[j++]);
for (i = 0; i < 43; i++)
-   I915_WRITE(TV_V_LUMA_0 + (i<<2), tv_mode->filter_table[j++]);
+   I915_WRITE(TV_V_LUMA(i), tv_mode->filter_table[j++]);
for (i = 0; i < 43; i++)
-   I915_WRITE(TV_V_CHROMA_0 + (i<<2), tv_mode->filter_table[j++]);
+   I915_WRITE(TV_V_CHROMA(i), tv_mode->filter_table[j++]);
I915_WRITE(TV_DAC, I915_READ(TV_DAC) & TV_DAC_SAVE);
I915_WRITE(TV_CTL, tv_ctl);
 }
-- 
2.4.6

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[Intel-gfx] [PATCH 00/43] drm/i915: Type safe register read/write and a ton of prep work

[ville . syrjala]

From: Ville Syrjälä 

Inspired by the recent misplaced parenthesis fix from Damien, I decided to try
and see what it would take to make our register access type safe. By that mean
you shouldn't be able to pass in anything by a proper register offset in. After
a couple of days of hacking, this series is the result.

I managed to split out all the cleanup stuff upfront, but there is quite a bit
of it. I did include a few random patches no strictly needed, but as long as I
was going through the register macros I tried to fix whatever was wrong.

The actual type safe stuff is in the last patch, and I'm posting that on as an
RFC to see what other people think about the idea. I think most of the prep
work would be nice to have even if we decide against the type safety. Oh, turns
out I couldn't find any new "passing crap as the register offset" type of bugs
with this work, but this would prevent them from sneaking in. As mentioned in
the patch, I limited this only for mmio regs for now, but we could expand it
cover other register types.

I've only smoke tested this on IVB, HSW and BSW.

The whole thing is available in my git repo:
git://github.com/vsyrjala/linux.git type_safe_reg_access_3

Ville Syrjälä (43):
  drm/i915: Don't pass sdvo_reg to intel_sdvo_select_{ddc,i2c}_bus()
  drm/i915: Parametrize LRC registers
  drm/i915: Parametrize GEN7_GT_SCRATCH and GEN7_LRA_LIMITS
  drm/i915: Parametrize fence registers
  drm/i915: Parametrize FBC_TAG registers
  drm/i915: Parametrize ILK turbo registers
  drm/i915: Replace raw numbers with the approproate register name in
ILK turbo code
  drm/i915: Parametrize TV luma/chroma filter registers
  drm/i915: Parametrize DDI_BUF_TRANS registers
  drm/i915: Parametrize CSR_PROGRAM registers
  drm/i915: Parametrize UOS_RSA_SCRATCH
  drm/i915: Add LO/HI PRIVATE_PAT registers
  drm/i915: Always use GEN8_RING_PDP_{LDW,UDW} instead of hand rolling
the register offsets
  drm/i915: Include MCHBAR_MIRROR_BASE in ILK_GDSR
  drm/i915: Parametrize PALETTE and LGC_PALETTE
  drm/i915: s/_CURACNTR/CURCNTR(PIPE_A)/
  drm/i915: s/_FDI_RXA_.../FDI_RX_...(PIPE_A)/
  drm/i915: s/_TRANSA_CHICKEN/TRANS_CHICKEN(PIPE_A)/
  drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc.
  drm/i915: Use paramtrized WRPLL_CTL()
  drm/i915: Add VLV_HDMIB etc. which already include VLV_DISPLAY_BASE
  drm/i915: s/DDI_BUF_CTL_A/DDI_BUF_CTL(PORT_A)/
  drm/i915: Eliminate weird parameter inversion from BXT PPS registers
  drm/i915: Parametrize HSW video DIP data registers
  drm/i915: Include gpio_mmio_base in GMBUS reg defines
  drm/i915: Protect register macro arguments
  drm/i915: Fix a few bad hex numbers in register defines
  drm/i915: Turn GEN5_ASSERT_IIR_IS_ZERO() into a function
  drm/i915: s/PIPE_FRMCOUNT_GM45/PIPE_FRMCOUNT_G4X/ etc.
  drm/i915: Parametrize and fix SWF registers
  drm/i915: Throw out some useless variables
  drm/i915: Clean up LVDS register handling
  drm/i915: Remove dev_priv argument from NEEDS_FORCE_WAKE
  drm/i915: Turn __raw_i915_read8() & co. in to inline functions
  drm/i915: Move __raw_i915_read8() & co. into i915_drv.h
  drm/i915: Remove the magic AUX_CTL is at DP + foo tricks
  drm/i915: Replace the aux ddc name switch statement with a table
  drm/i915: Parametrize AUX registes
  drm/i915: Add dev_priv->psr_mmio_base
  drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[]
  drm/i915: Model PSR AUX register selection more like the normal AUX
code
  drm/i915: Prefix raw register defines with underscore
  WIP: drm/i915: Type safe register read/write

 drivers/gpu/drm/i915/dvo.h |2 +-
 drivers/gpu/drm/i915/i915_cmd_parser.c |   17 +-
 drivers/gpu/drm/i915/i915_debugfs.c|   26 +-
 drivers/gpu/drm/i915/i915_drv.c|8 +-
 drivers/gpu/drm/i915/i915_drv.h|   66 +-
 drivers/gpu/drm/i915/i915_gem_context.c|4 +-
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |2 +-
 drivers/gpu/drm/i915/i915_gem_fence.c  |   41 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c|   35 +-
 drivers/gpu/drm/i915/i915_gpu_error.c  |   25 +-
 drivers/gpu/drm/i915/i915_guc_reg.h|   50 +-
 drivers/gpu/drm/i915/i915_guc_submission.c |2 +-
 drivers/gpu/drm/i915/i915_irq.c|   68 +-
 drivers/gpu/drm/i915/i915_reg.h| 2768 ++--
 drivers/gpu/drm/i915/i915_suspend.c|   45 +-
 drivers/gpu/drm/i915/i915_sysfs.c  |6 +-
 drivers/gpu/drm/i915/i915_trace.h  |4 +-
 drivers/gpu/drm/i915/i915_vgpu.c   |6 +-
 drivers/gpu/drm/i915/i915_vgpu.h   |2 +-
 drivers/gpu/drm/i915/intel_audio.c |   14 +-
 drivers/gpu/drm/i915/intel_crt.c   |   16 +-
 drivers/gpu/drm/i915/intel_csr.c   |   17 +-
 drivers/gpu/drm/i915/intel_ddi.c   |  117 +-
 drivers/gpu/drm/i915/intel_display.c   |  260 ++-
 drivers/gpu/drm/i915/intel_dp.c|  220 ++-
 drivers/gpu/drm/i915/intel_drv.h

[Intel-gfx] [PATCH 13/43] drm/i915: Always use GEN8_RING_PDP_{LDW, UDW} instead of hand rolling the register offsets

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5615d3d..24baa5a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2231,10 +2231,9 @@ static void gen8_ppgtt_info(struct seq_file *m, struct 
drm_device *dev)
for_each_ring(ring, dev_priv, unused) {
seq_printf(m, "%s\n", ring->name);
for (i = 0; i < 4; i++) {
-   u32 offset = 0x270 + i * 8;
-   u64 pdp = I915_READ(ring->mmio_base + offset + 4);
+   u64 pdp = I915_READ(GEN8_RING_PDP_UDW(ring, i));
pdp <<= 32;
-   pdp |= I915_READ(ring->mmio_base + offset);
+   pdp |= I915_READ(GEN8_RING_PDP_LDW(ring, i));
seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
}
}
-- 
2.4.6

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[Intel-gfx] [PATCH 17/43] drm/i915: s/_FDI_RXA_.../FDI_RX_...(PIPE_A)/

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_crt.c |  2 +-
 drivers/gpu/drm/i915/intel_ddi.c | 46 
 2 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index af5e43b..086b5c5 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -891,7 +891,7 @@ void intel_crt_init(struct drm_device *dev)
u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
 FDI_RX_LINK_REVERSAL_OVERRIDE;
 
-   dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config;
+   dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & 
fdi_config;
}
 
intel_crt_reset(connector);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9e640ea..b885b70 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -592,7 +592,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 *
 * WaFDIAutoLinkSetTimingOverrride:hsw
 */
-   I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
+   I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
  FDI_RX_PWRDN_LANE0_VAL(2) |
  FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 
@@ -600,13 +600,13 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 FDI_RX_PLL_ENABLE |
 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
-   I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
-   POSTING_READ(_FDI_RXA_CTL);
+   I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
+   POSTING_READ(FDI_RX_CTL(PIPE_A));
udelay(220);
 
/* Switch from Rawclk to PCDclk */
rx_ctl_val |= FDI_PCDCLK;
-   I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
+   I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 
/* Configure Port Clock Select */
I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
@@ -635,21 +635,21 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
udelay(600);
 
/* Program PCH FDI Receiver TU */
-   I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
+   I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
 
/* Enable PCH FDI Receiver with auto-training */
rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
-   I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
-   POSTING_READ(_FDI_RXA_CTL);
+   I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
+   POSTING_READ(FDI_RX_CTL(PIPE_A));
 
/* Wait for FDI receiver lane calibration */
udelay(30);
 
/* Unset FDI_RX_MISC pwrdn lanes */
-   temp = I915_READ(_FDI_RXA_MISC);
+   temp = I915_READ(FDI_RX_MISC(PIPE_A));
temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
-   I915_WRITE(_FDI_RXA_MISC, temp);
-   POSTING_READ(_FDI_RXA_MISC);
+   I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
+   POSTING_READ(FDI_RX_MISC(PIPE_A));
 
/* Wait for FDI auto training time */
udelay(5);
@@ -683,15 +683,15 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 
rx_ctl_val &= ~FDI_RX_ENABLE;
-   I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
-   POSTING_READ(_FDI_RXA_CTL);
+   I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
+   POSTING_READ(FDI_RX_CTL(PIPE_A));
 
/* Reset FDI_RX_MISC pwrdn lanes */
-   temp = I915_READ(_FDI_RXA_MISC);
+   temp = I915_READ(FDI_RX_MISC(PIPE_A));
temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
-   I915_WRITE(_FDI_RXA_MISC, temp);
-   POSTING_READ(_FDI_RXA_MISC);
+   I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
+   POSTING_READ(FDI_RX_MISC(PIPE_A));
}
 
DRM_ERROR("FDI link training failed!\n");
@@ -2999,22 +2999,22 @@ void intel_ddi_fdi_disable(struct drm_crtc *crtc)
 
intel_ddi_post_disable(intel_encoder);
 
-   val = I915_READ(_FDI_RXA_CTL);
+   val = I915_READ(FDI_RX_CTL(PIPE_A));
val &= ~FDI_RX_ENABLE;
-   I915_WRITE(_FDI_RXA_CTL, val);
+   I915_WRITE(FDI_RX_CTL(PIPE_A), val);
 
-   val = I915_READ(_FDI_RXA_MISC);
+   val = I915_READ(FDI_RX_MISC(PIPE_A));
val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
-   

[Intel-gfx] [PATCH 15/43] drm/i915: Parametrize PALETTE and LGC_PALETTE

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  |  6 +++---
 drivers/gpu/drm/i915/intel_display.c | 14 --
 2 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 610ce25..93cb6ed 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2478,8 +2478,8 @@ enum skl_disp_power_wells {
 #define PALETTE_A_OFFSET 0xa000
 #define PALETTE_B_OFFSET 0xa800
 #define CHV_PALETTE_C_OFFSET 0xc000
-#define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
-  dev_priv->info.display_mmio_offset)
+#define PALETTE(pipe, i) (dev_priv->info.palette_offsets[pipe] + \
+ dev_priv->info.display_mmio_offset + (i) * 4)
 
 /* MCH MMIO space */
 
@@ -5629,7 +5629,7 @@ enum skl_disp_power_wells {
 /* legacy palette */
 #define _LGC_PALETTE_A   0x4a000
 #define _LGC_PALETTE_B   0x4a800
-#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
+#define LGC_PALETTE(pipe, i) (_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + 
(i) * 4)
 
 #define _GAMMA_MODE_A  0x4a480
 #define _GAMMA_MODE_B  0x4ac80
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index fc00867..f385dd3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4558,7 +4558,6 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
enum pipe pipe = intel_crtc->pipe;
-   int palreg = PALETTE(pipe);
int i;
bool reenable_ips = false;
 
@@ -4573,10 +4572,6 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
assert_pll_enabled(dev_priv, pipe);
}
 
-   /* use legacy palette for Ironlake */
-   if (!HAS_GMCH_DISPLAY(dev))
-   palreg = LGC_PALETTE(pipe);
-
/* Workaround : Do not read or write the pipe palette/gamma data while
 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
 */
@@ -4588,7 +4583,14 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
}
 
for (i = 0; i < 256; i++) {
-   I915_WRITE(palreg + 4 * i,
+   u32 palreg;
+
+   if (HAS_GMCH_DISPLAY(dev))
+   palreg = PALETTE(pipe, i);
+   else
+   palreg = LGC_PALETTE(pipe, i);
+
+   I915_WRITE(palreg,
   (intel_crtc->lut_r[i] << 16) |
   (intel_crtc->lut_g[i] << 8) |
   intel_crtc->lut_b[i]);
-- 
2.4.6

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[Intel-gfx] [PATCH 07/43] drm/i915: Replace raw numbers with the approproate register name in ILK turbo code

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_pm.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0320675..dc765eb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4305,10 +4305,10 @@ static void ironlake_enable_drps(struct drm_device *dev)
 
ironlake_set_drps(dev, fstart);
 
-   dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
-   I915_READ(0x112e0);
+   dev_priv->ips.last_count1 = I915_READ(DMIEC) +
+   I915_READ(DDREC) + I915_READ(CSIEC);
dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
-   dev_priv->ips.last_count2 = I915_READ(0x112f4);
+   dev_priv->ips.last_count2 = I915_READ(GFXEC);
dev_priv->ips.last_time2 = ktime_get_raw_ns();
 
spin_unlock_irq(_lock);
-- 
2.4.6

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[Intel-gfx] [PATCH 11/43] drm/i915: Parametrize UOS_RSA_SCRATCH

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_guc_reg.h | 2 +-
 drivers/gpu/drm/i915/intel_guc_loader.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h 
b/drivers/gpu/drm/i915/i915_guc_reg.h
index 8c8e574..848a563 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -40,7 +40,7 @@
 
 #define SOFT_SCRATCH(n)(0xc180 + ((n) * 4))
 
-#define UOS_RSA_SCRATCH_0  0xc200
+#define UOS_RSA_SCRATCH(i) (0xc200 + (i) * 4)
 #define DMA_ADDR_0_LOW 0xc300
 #define DMA_ADDR_0_HIGH0xc304
 #define DMA_ADDR_1_LOW 0xc308
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index e0601cc..7432832 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -257,7 +257,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private 
*dev_priv)
/* Copy RSA signature from the fw image to HW for verification */
sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, UOS_RSA_SIG_SIZE, offset);
for (i = 0; i < UOS_RSA_SIG_SIZE / sizeof(u32); i++)
-   I915_WRITE(UOS_RSA_SCRATCH_0 + i * sizeof(u32), rsa[i]);
+   I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
 
/* Set the source address for the new blob */
offset = i915_gem_obj_ggtt_offset(fw_obj);
-- 
2.4.6

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[Intel-gfx] [PATCH 25/43] drm/i915: Include gpio_mmio_base in GMBUS reg defines

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  | 12 -
 drivers/gpu/drm/i915/intel_i2c.c | 54 +---
 2 files changed, 29 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b35e24f..0216771 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2114,7 +2114,7 @@ enum skl_disp_power_wells {
 # define GPIO_DATA_VAL_IN  (1 << 12)
 # define GPIO_DATA_PULLUP_DISABLE  (1 << 13)
 
-#define GMBUS0 0x5100 /* clock/port select */
+#define GMBUS0 (dev_priv->gpio_mmio_base + 0x5100) /* 
clock/port select */
 #define   GMBUS_RATE_100KHZ(0<<8)
 #define   GMBUS_RATE_50KHZ (1<<8)
 #define   GMBUS_RATE_400KHZ(2<<8) /* reserved on Pineview */
@@ -2133,7 +2133,7 @@ enum skl_disp_power_wells {
 #define   GMBUS_PIN_2_BXT  2
 #define   GMBUS_PIN_3_BXT  3
 #define   GMBUS_NUM_PINS   7 /* including 0 */
-#define GMBUS1 0x5104 /* command/status */
+#define GMBUS1 (dev_priv->gpio_mmio_base + 0x5104) /* 
command/status */
 #define   GMBUS_SW_CLR_INT (1<<31)
 #define   GMBUS_SW_RDY (1<<30)
 #define   GMBUS_ENT(1<<29) /* enable timeout */
@@ -2147,7 +2147,7 @@ enum skl_disp_power_wells {
 #define   GMBUS_SLAVE_ADDR_SHIFT 1
 #define   GMBUS_SLAVE_READ (1<<0)
 #define   GMBUS_SLAVE_WRITE(0<<0)
-#define GMBUS2 0x5108 /* status */
+#define GMBUS2 (dev_priv->gpio_mmio_base + 0x5108) /* status */
 #define   GMBUS_INUSE  (1<<15)
 #define   GMBUS_HW_WAIT_PHASE  (1<<14)
 #define   GMBUS_STALL_TIMEOUT  (1<<13)
@@ -2155,14 +2155,14 @@ enum skl_disp_power_wells {
 #define   GMBUS_HW_RDY (1<<11)
 #define   GMBUS_SATOER (1<<10)
 #define   GMBUS_ACTIVE (1<<9)
-#define GMBUS3 0x510c /* data buffer bytes 3-0 */
-#define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
+#define GMBUS3 (dev_priv->gpio_mmio_base + 0x510c) /* data 
buffer bytes 3-0 */
+#define GMBUS4 (dev_priv->gpio_mmio_base + 0x5110) /* 
interrupt mask (Pineview+) */
 #define   GMBUS_SLAVE_TIMEOUT_EN (1<<4)
 #define   GMBUS_NAK_EN (1<<3)
 #define   GMBUS_IDLE_EN(1<<2)
 #define   GMBUS_HW_WAIT_EN (1<<1)
 #define   GMBUS_HW_RDY_EN  (1<<0)
-#define GMBUS5 0x5120 /* byte index */
+#define GMBUS5 (dev_priv->gpio_mmio_base + 0x5120) /* byte 
index */
 #define   GMBUS_2BYTE_INDEX_EN (1<<31)
 
 /*
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index a64f26c..1369fc4 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -114,8 +114,8 @@ intel_i2c_reset(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
 
-   I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
-   I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
+   I915_WRITE(GMBUS0, 0);
+   I915_WRITE(GMBUS4, 0);
 }
 
 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
@@ -261,7 +261,6 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
 u32 gmbus4_irq_en)
 {
int i;
-   int reg_offset = dev_priv->gpio_mmio_base;
u32 gmbus2 = 0;
DEFINE_WAIT(wait);
 
@@ -271,13 +270,13 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
/* Important: The hw handles only the first bit, so set only one! Since
 * we also need to check for NAKs besides the hw ready/idle signal, we
 * need to wake up periodically and check that ourselves. */
-   I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
+   I915_WRITE(GMBUS4, gmbus4_irq_en);
 
for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
prepare_to_wait(_priv->gmbus_wait_queue, ,
TASK_UNINTERRUPTIBLE);
 
-   gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset);
+   gmbus2 = I915_READ_NOTRACE(GMBUS2);
if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
break;
 
@@ -285,7 +284,7 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
}
finish_wait(_priv->gmbus_wait_queue, );
 
-   I915_WRITE(GMBUS4 + reg_offset, 0);
+   I915_WRITE(GMBUS4, 0);
 
if (gmbus2 & GMBUS_SATOER)
return -ENXIO;
@@ -298,20 +297,19 @@ static int
 gmbus_wait_idle(struct drm_i915_private *dev_priv)
 {
int ret;
-   int reg_offset = dev_priv->gpio_mmio_base;
 
-#define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0)
+#define C ((I915_READ_NOTRACE(GMBUS2) & GMBUS_ACTIVE) == 0)
 
if (!HAS_GMBUS_IRQ(dev_priv->dev))
return wait_for(C, 10);
 

[Intel-gfx] [PATCH 20/43] drm/i915: Use paramtrized WRPLL_CTL()

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  | 2 +-
 drivers/gpu/drm/i915/intel_ddi.c | 8 
 drivers/gpu/drm/i915/intel_display.c | 4 ++--
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 25864ae..a8fb5f7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7253,7 +7253,7 @@ enum skl_disp_power_wells {
 /* WRPLL */
 #define WRPLL_CTL1 0x46040
 #define WRPLL_CTL2 0x46060
-#define WRPLL_CTL(pll) (pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2)
+#define WRPLL_CTL(pll) _PIPE(pll, WRPLL_CTL1, WRPLL_CTL2)
 #define  WRPLL_PLL_ENABLE  (1<<31)
 #define  WRPLL_PLL_SSC (1<<28)
 #define  WRPLL_PLL_NON_SSC (2<<28)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 399e70e..fb456a4 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1094,10 +1094,10 @@ static void hsw_ddi_clock_get(struct intel_encoder 
*encoder,
link_clock = 27;
break;
case PORT_CLK_SEL_WRPLL1:
-   link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
+   link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
break;
case PORT_CLK_SEL_WRPLL2:
-   link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
+   link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
break;
case PORT_CLK_SEL_SPLL:
pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
@@ -2485,13 +2485,13 @@ static const struct skl_dpll_regs skl_dpll_regs[3] = {
},
{
/* DPLL 2 */
-   .ctl = WRPLL_CTL1,
+   .ctl = WRPLL_CTL(0),
.cfgcr1 = DPLL_CFGCR1(2),
.cfgcr2 = DPLL_CFGCR2(2),
},
{
/* DPLL 3 */
-   .ctl = WRPLL_CTL2,
+   .ctl = WRPLL_CTL(1),
.cfgcr1 = DPLL_CFGCR1(3),
.cfgcr2 = DPLL_CFGCR2(3),
},
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 63cf5eb..fa7c10fa 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9237,8 +9237,8 @@ static void assert_can_disable_lcpll(struct 
drm_i915_private *dev_priv)
 
I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL 
enabled\n");
-   I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 
enabled\n");
-   I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 
enabled\n");
+   I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 
enabled\n");
+   I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 
enabled\n");
I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
 "CPU PWM1 enabled\n");
-- 
2.4.6

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[Intel-gfx] [PATCH 19/43] drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc.

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  |  4 ++--
 drivers/gpu/drm/i915/intel_ddi.c | 16 
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 93cb6ed..25864ae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7401,8 +7401,8 @@ enum skl_disp_power_wells {
 #define  DPLL_CFGCR2_PDIV_7 (4<<2)
 #define  DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
 
-#define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8)
-#define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8)
+#define DPLL_CFGCR1(id) (DPLL1_CFGCR1 + ((id) - SKL_DPLL1) * 8)
+#define DPLL_CFGCR2(id) (DPLL1_CFGCR2 + ((id) - SKL_DPLL1) * 8)
 
 /* BXT display engine PLL */
 #define BXT_DE_PLL_CTL 0x6d000
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index b885b70..399e70e 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -953,8 +953,8 @@ static int skl_calc_wrpll_link(struct drm_i915_private 
*dev_priv,
uint32_t cfgcr1_val, cfgcr2_val;
uint32_t p0, p1, p2, dco_freq;
 
-   cfgcr1_reg = GET_CFG_CR1_REG(dpll);
-   cfgcr2_reg = GET_CFG_CR2_REG(dpll);
+   cfgcr1_reg = DPLL_CFGCR1(dpll);
+   cfgcr2_reg = DPLL_CFGCR2(dpll);
 
cfgcr1_val = I915_READ(cfgcr1_reg);
cfgcr2_val = I915_READ(cfgcr2_reg);
@@ -2480,20 +2480,20 @@ static const struct skl_dpll_regs skl_dpll_regs[3] = {
{
/* DPLL 1 */
.ctl = LCPLL2_CTL,
-   .cfgcr1 = DPLL1_CFGCR1,
-   .cfgcr2 = DPLL1_CFGCR2,
+   .cfgcr1 = DPLL_CFGCR1(1),
+   .cfgcr2 = DPLL_CFGCR2(1),
},
{
/* DPLL 2 */
.ctl = WRPLL_CTL1,
-   .cfgcr1 = DPLL2_CFGCR1,
-   .cfgcr2 = DPLL2_CFGCR2,
+   .cfgcr1 = DPLL_CFGCR1(2),
+   .cfgcr2 = DPLL_CFGCR2(2),
},
{
/* DPLL 3 */
.ctl = WRPLL_CTL2,
-   .cfgcr1 = DPLL3_CFGCR1,
-   .cfgcr2 = DPLL3_CFGCR2,
+   .cfgcr1 = DPLL_CFGCR1(3),
+   .cfgcr2 = DPLL_CFGCR2(3),
},
 };
 
-- 
2.4.6

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[Intel-gfx] [PATCH 24/43] drm/i915: Parametrize HSW video DIP data registers

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h   | 16 
 drivers/gpu/drm/i915/intel_hdmi.c | 26 ++
 drivers/gpu/drm/i915/intel_psr.c  | 18 ++
 3 files changed, 32 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 134b075..b35e24f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6236,16 +6236,16 @@ enum skl_disp_power_wells {
 
 #define HSW_TVIDEO_DIP_CTL(trans) \
 _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A)
-#define HSW_TVIDEO_DIP_AVI_DATA(trans) \
-_TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A)
-#define HSW_TVIDEO_DIP_VS_DATA(trans) \
-_TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A)
-#define HSW_TVIDEO_DIP_SPD_DATA(trans) \
-_TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A)
+#define HSW_TVIDEO_DIP_AVI_DATA(trans, i) \
+   (_TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A) + (i) * 4)
+#define HSW_TVIDEO_DIP_VS_DATA(trans, i) \
+   (_TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A) + (i) * 4)
+#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) \
+   (_TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A) + (i) * 4)
 #define HSW_TVIDEO_DIP_GCP(trans) \
_TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A)
-#define HSW_TVIDEO_DIP_VSC_DATA(trans) \
-_TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A)
+#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) \
+   (_TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A) + (i) * 4)
 
 #define HSW_STEREO_3D_CTL_A0x70020
 #define   S3D_ENABLE   (1<<31)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index e978c59..6b16292 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -113,17 +113,18 @@ static u32 hsw_infoframe_enable(enum hdmi_infoframe_type 
type)
}
 }
 
-static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
- enum transcoder cpu_transcoder,
- struct drm_i915_private *dev_priv)
+static u32 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
+   enum transcoder cpu_transcoder,
+   enum hdmi_infoframe_type type,
+   int i)
 {
switch (type) {
case HDMI_INFOFRAME_TYPE_AVI:
-   return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
+   return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_SPD:
-   return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
+   return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_VENDOR:
-   return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
+   return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
default:
DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
return 0;
@@ -365,14 +366,13 @@ static void hsw_write_infoframe(struct drm_encoder 
*encoder,
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-   u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
+   enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
+   u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
u32 data_reg;
int i;
u32 val = I915_READ(ctl_reg);
 
-   data_reg = hsw_infoframe_data_reg(type,
- intel_crtc->config->cpu_transcoder,
- dev_priv);
+   data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
if (data_reg == 0)
return;
 
@@ -381,12 +381,14 @@ static void hsw_write_infoframe(struct drm_encoder 
*encoder,
 
mmiowb();
for (i = 0; i < len; i += 4) {
-   I915_WRITE(data_reg + i, *data);
+   I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
+   type, i >> 2), *data);
data++;
}
/* Write every possible data byte to force correct ECC calculation. */
for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
-   I915_WRITE(data_reg + i, 0);
+   I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
+   type, i >> 2), 0);
mmiowb();
 
val |= hsw_infoframe_enable(type);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index a04b4dc..213581c 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -73,14 +73,14 @@ static bool vlv_is_psr_active_on_pipe(struct drm_device 
*dev, int pipe)
 }
 
 static void intel_psr_write_vsc(struct intel_dp *intel_dp,
-   

[Intel-gfx] [PATCH 22/43] drm/i915: s/DDI_BUF_CTL_A/DDI_BUF_CTL(PORT_A)/

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index e20abd5..92e624b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13948,7 +13948,7 @@ static void intel_setup_outputs(struct drm_device *dev)
 * On SKL pre-D0 the strap isn't connected, so we assume
 * it's there.
 */
-   found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
+   found = I915_READ(DDI_BUF_CTL(PORT_A)) & 
DDI_INIT_DISPLAY_DETECTED;
/* WaIgnoreDDIAStrap: skl */
if (found || IS_SKYLAKE(dev))
intel_ddi_init(dev, PORT_A);
-- 
2.4.6

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[Intel-gfx] [PATCH 27/43] drm/i915: Fix a few bad hex numbers in register defines

[ville . syrjala]

From: Ville Syrjälä 

A few register mask defines were missing the '0x' from hex numbers. Or
at least I assume those were meant to be hex numbers. Put the '0x' in
place.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 21d49e7..02f0935 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4234,7 +4234,7 @@ enum skl_disp_power_wells {
 #define   DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL   (1 << 14)
 #define   DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL(1 << 13)
 #define   DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL   (1 << 12)
-#define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (1f << 5)
+#define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
 #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
 #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
 
@@ -7819,7 +7819,7 @@ enum skl_disp_power_wells {
 #define  VIRTUAL_CHANNEL_SHIFT 6
 #define  VIRTUAL_CHANNEL_MASK  (3 << 6)
 #define  DATA_TYPE_SHIFT   0
-#define  DATA_TYPE_MASK(3f << 0)
+#define  DATA_TYPE_MASK(0x3f << 0)
 /* data type values, see include/video/mipi_display.h */
 
 #define _MIPIA_GEN_FIFO_STAT   (dev_priv->mipi_mmio_base + 0xb074)
-- 
2.4.6

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[Intel-gfx] [PATCH 12/43] drm/i915: Add LO/HI PRIVATE_PAT registers

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 8 
 drivers/gpu/drm/i915/i915_reg.h | 3 ++-
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 8786281..2b6dd70 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2879,8 +2879,8 @@ static void bdw_setup_private_ppat(struct 
drm_i915_private *dev_priv)
 
/* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
 * write would work. */
-   I915_WRITE(GEN8_PRIVATE_PAT, pat);
-   I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
+   I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
+   I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
 }
 
 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
@@ -2914,8 +2914,8 @@ static void chv_setup_private_ppat(struct 
drm_i915_private *dev_priv)
  GEN8_PPAT(6, CHV_PPAT_SNOOP) |
  GEN8_PPAT(7, CHV_PPAT_SNOOP);
 
-   I915_WRITE(GEN8_PRIVATE_PAT, pat);
-   I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
+   I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
+   I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
 }
 
 static int gen8_gmch_probe(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 61414c8..a04fa2a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1544,7 +1544,8 @@ enum skl_disp_power_wells {
 #define   RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
 #define   RING_FAULT_VALID (1<<0)
 #define DONE_REG   0x40b0
-#define GEN8_PRIVATE_PAT   0x40e0
+#define GEN8_PRIVATE_PAT_LO0x40e0
+#define GEN8_PRIVATE_PAT_HI(0x40e0 + 4)
 #define BSD_HWS_PGA_GEN7   (0x04180)
 #define BLT_HWS_PGA_GEN7   (0x04280)
 #define VEBOX_HWS_PGA_GEN7 (0x04380)
-- 
2.4.6

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[Intel-gfx] [PATCH 26/43] drm/i915: Protect register macro arguments

[ville . syrjala]

From: Ville Syrjälä 

Always put parens around macro argument evaluations.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h | 92 -
 1 file changed, 46 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0216771..21d49e7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -429,7 +429,7 @@
 #define   ASYNC_FLIP(1<<22)
 #define   DISPLAY_PLANE_A   (0<<20)
 #define   DISPLAY_PLANE_B   (1<<20)
-#define GFX_OP_PIPE_CONTROL(len)   ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
+#define GFX_OP_PIPE_CONTROL(len)   
((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
 #define   PIPE_CONTROL_FLUSH_L3(1<<27)
 #define   PIPE_CONTROL_GLOBAL_GTT_IVB  (1<<24) /* gen7+ */
 #define   PIPE_CONTROL_MMIO_WRITE  (1<<23)
@@ -1250,7 +1250,7 @@ enum skl_disp_power_wells {
 #define  PORT_PLL_DCO_AMP_OVR_EN_H (1<<27)
 #define  PORT_PLL_DCO_AMP_DEFAULT  15
 #define  PORT_PLL_DCO_AMP_MASK 0x3c00
-#define  PORT_PLL_DCO_AMP(x)   (x<<10)
+#define  PORT_PLL_DCO_AMP(x)   ((x)<<10)
 #define _PORT_PLL_BASE(port)   _PORT3(port, _PORT_PLL_0_A, \
_PORT_PLL_0_B,  \
_PORT_PLL_0_C)
@@ -1540,8 +1540,8 @@ enum skl_disp_power_wells {
 #define RENDER_HWS_PGA_GEN7(0x04080)
 #define RING_FAULT_REG(ring)   (0x4094 + 0x100*(ring)->id)
 #define   RING_FAULT_GTTSEL_MASK (1<<11)
-#define   RING_FAULT_SRCID(x)  ((x >> 3) & 0xff)
-#define   RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
+#define   RING_FAULT_SRCID(x)  (((x) >> 3) & 0xff)
+#define   RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
 #define   RING_FAULT_VALID (1<<0)
 #define DONE_REG   0x40b0
 #define GEN8_PRIVATE_PAT_LO0x40e0
@@ -1626,9 +1626,9 @@ enum skl_disp_power_wells {
 #define   ERR_INT_PIPE_CRC_DONE_B  (1<<5)
 #define   ERR_INT_FIFO_UNDERRUN_B  (1<<3)
 #define   ERR_INT_PIPE_CRC_DONE_A  (1<<2)
-#define   ERR_INT_PIPE_CRC_DONE(pipe)  (1<<(2 + pipe*3))
+#define   ERR_INT_PIPE_CRC_DONE(pipe)  (1<<(2 + (pipe)*3))
 #define   ERR_INT_FIFO_UNDERRUN_A  (1<<0)
-#define   ERR_INT_FIFO_UNDERRUN(pipe)  (1<<(pipe*3))
+#define   ERR_INT_FIFO_UNDERRUN(pipe)  (1<<((pipe)*3))
 
 #define GEN8_FAULT_TLB_DATA0   0x04b10
 #define GEN8_FAULT_TLB_DATA1   0x04b14
@@ -1689,8 +1689,8 @@ enum skl_disp_power_wells {
 #define   GEN6_WIZ_HASHING_16x4
GEN6_WIZ_HASHING(1, 0)
 #define   GEN6_WIZ_HASHING_MASK
GEN6_WIZ_HASHING(1, 1)
 #define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE(1 << 5)
-#define   GEN9_IZ_HASHING_MASK(slice)  (0x3 << (slice * 2))
-#define   GEN9_IZ_HASHING(slice, val)  ((val) << (slice * 2))
+#define   GEN9_IZ_HASHING_MASK(slice)  (0x3 << ((slice) * 2))
+#define   GEN9_IZ_HASHING(slice, val)  ((val) << ((slice) * 2))
 
 #define GFX_MODE   0x02520
 #define GFX_MODE_GEN7  0x0229c
@@ -2828,21 +2828,21 @@ enum skl_disp_power_wells {
  *   doesn't need saving on GT1
  */
 #define CXT_SIZE   0x21a0
-#define GEN6_CXT_POWER_SIZE(cxt_reg)   ((cxt_reg >> 24) & 0x3f)
-#define GEN6_CXT_RING_SIZE(cxt_reg)((cxt_reg >> 18) & 0x3f)
-#define GEN6_CXT_RENDER_SIZE(cxt_reg)  ((cxt_reg >> 12) & 0x3f)
-#define GEN6_CXT_EXTENDED_SIZE(cxt_reg)((cxt_reg >> 6) & 0x3f)
-#define GEN6_CXT_PIPELINE_SIZE(cxt_reg)((cxt_reg >> 0) & 0x3f)
+#define GEN6_CXT_POWER_SIZE(cxt_reg)   (((cxt_reg) >> 24) & 0x3f)
+#define GEN6_CXT_RING_SIZE(cxt_reg)(((cxt_reg) >> 18) & 0x3f)
+#define GEN6_CXT_RENDER_SIZE(cxt_reg)  (((cxt_reg) >> 12) & 0x3f)
+#define GEN6_CXT_EXTENDED_SIZE(cxt_reg)(((cxt_reg) >> 6) & 0x3f)
+#define GEN6_CXT_PIPELINE_SIZE(cxt_reg)(((cxt_reg) >> 0) & 0x3f)
 #define GEN6_CXT_TOTAL_SIZE(cxt_reg)   (GEN6_CXT_RING_SIZE(cxt_reg) + \
GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
GEN6_CXT_PIPELINE_SIZE(cxt_reg))
 #define GEN7_CXT_SIZE  0x21a8
-#define GEN7_CXT_POWER_SIZE(ctx_reg)   ((ctx_reg >> 25) & 0x7f)
-#define GEN7_CXT_RING_SIZE(ctx_reg)((ctx_reg >> 22) & 0x7)
-#define GEN7_CXT_RENDER_SIZE(ctx_reg)  ((ctx_reg >> 16) & 0x3f)
-#define GEN7_CXT_EXTENDED_SIZE(ctx_reg)((ctx_reg >> 9) & 0x7f)
-#define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7)
-#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f)
+#define GEN7_CXT_POWER_SIZE(ctx_reg)   (((ctx_reg) >> 25) & 0x7f)
+#define GEN7_CXT_RING_SIZE(ctx_reg)(((ctx_reg) >> 22) & 0x7)
+#define GEN7_CXT_RENDER_SIZE(ctx_reg)  (((ctx_reg) >> 16) & 0x3f)
+#define GEN7_CXT_EXTENDED_SIZE(ctx_reg)

[Intel-gfx] [PATCH 33/43] drm/i915: Remove dev_priv argument from NEEDS_FORCE_WAKE

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_uncore.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 3294f63..197ca397 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -525,7 +525,7 @@ void assert_forcewakes_inactive(struct drm_i915_private 
*dev_priv)
 }
 
 /* We give fast paths for the really cool registers */
-#define NEEDS_FORCE_WAKE(dev_priv, reg) \
+#define NEEDS_FORCE_WAKE(reg) \
 ((reg) < 0x4 && (reg) != FORCEWAKE)
 
 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
@@ -727,7 +727,7 @@ static u##x \
 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
GEN6_READ_HEADER(x); \
hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
-   if (NEEDS_FORCE_WAKE((dev_priv), (reg))) \
+   if (NEEDS_FORCE_WAKE(reg)) \
__force_wake_get(dev_priv, FORCEWAKE_RENDER); \
val = __raw_i915_read##x(dev_priv, reg); \
hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
@@ -761,7 +761,7 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg, 
bool trace) { \
GEN6_READ_FOOTER; \
 }
 
-#define SKL_NEEDS_FORCE_WAKE(dev_priv, reg)\
+#define SKL_NEEDS_FORCE_WAKE(reg) \
 ((reg) < 0x4 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
 
 #define __gen9_read(x) \
@@ -770,9 +770,9 @@ gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, 
bool trace) { \
enum forcewake_domains fw_engine; \
GEN6_READ_HEADER(x); \
hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
-   if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)))   \
+   if (!SKL_NEEDS_FORCE_WAKE(reg)) \
fw_engine = 0; \
-   else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg))   \
+   else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
fw_engine = FORCEWAKE_RENDER; \
else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
fw_engine = FORCEWAKE_MEDIA; \
@@ -868,7 +868,7 @@ static void \
 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool 
trace) { \
u32 __fifo_ret = 0; \
GEN6_WRITE_HEADER; \
-   if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
+   if (NEEDS_FORCE_WAKE(reg)) { \
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
} \
__raw_i915_write##x(dev_priv, reg, val); \
@@ -883,7 +883,7 @@ static void \
 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool 
trace) { \
u32 __fifo_ret = 0; \
GEN6_WRITE_HEADER; \
-   if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
+   if (NEEDS_FORCE_WAKE(reg)) { \
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
} \
hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
@@ -985,7 +985,7 @@ gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, 
u##x val, \
enum forcewake_domains fw_engine; \
GEN6_WRITE_HEADER; \
hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
-   if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \
+   if (!SKL_NEEDS_FORCE_WAKE(reg) || \
is_gen9_shadowed(dev_priv, reg)) \
fw_engine = 0; \
else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
-- 
2.4.6

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[Intel-gfx] [PATCH 23/43] drm/i915: Eliminate weird parameter inversion from BXT PPS registers

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h |  8 
 drivers/gpu/drm/i915/intel_dp.c | 17 -
 2 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ddfcd68..134b075 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6537,10 +6537,10 @@ enum skl_disp_power_wells {
 #define _BXT_PP_ON_DELAYS2 0xc7308
 #define _BXT_PP_OFF_DELAYS20xc730c
 
-#define BXT_PP_STATUS(n)   ((!n) ? PCH_PP_STATUS : _BXT_PP_STATUS2)
-#define BXT_PP_CONTROL(n)  ((!n) ? PCH_PP_CONTROL : _BXT_PP_CONTROL2)
-#define BXT_PP_ON_DELAYS(n)((!n) ? PCH_PP_ON_DELAYS : _BXT_PP_ON_DELAYS2)
-#define BXT_PP_OFF_DELAYS(n)   ((!n) ? PCH_PP_OFF_DELAYS : _BXT_PP_OFF_DELAYS2)
+#define BXT_PP_STATUS(n)   _PIPE(n, PCH_PP_STATUS, _BXT_PP_STATUS2)
+#define BXT_PP_CONTROL(n)  _PIPE(n, PCH_PP_CONTROL, _BXT_PP_CONTROL2)
+#define BXT_PP_ON_DELAYS(n)_PIPE(n, PCH_PP_ON_DELAYS, _BXT_PP_ON_DELAYS2)
+#define BXT_PP_OFF_DELAYS(n)   _PIPE(n, PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)
 
 #define PCH_DP_B   0xe4100
 #define PCH_DPB_AUX_CH_CTL 0xe4110
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a687250..7e64555 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -546,7 +546,7 @@ static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
struct drm_device *dev = intel_dp_to_dev(intel_dp);
 
if (IS_BROXTON(dev))
-   return BXT_PP_CONTROL(0);
+   return BXT_PP_CONTROL(1);
else if (HAS_PCH_SPLIT(dev))
return PCH_PP_CONTROL;
else
@@ -558,7 +558,7 @@ static u32 _pp_stat_reg(struct intel_dp *intel_dp)
struct drm_device *dev = intel_dp_to_dev(intel_dp);
 
if (IS_BROXTON(dev))
-   return BXT_PP_STATUS(0);
+   return BXT_PP_STATUS(1);
else if (HAS_PCH_SPLIT(dev))
return PCH_PP_STATUS;
else
@@ -5318,9 +5318,9 @@ intel_dp_init_panel_power_sequencer(struct drm_device 
*dev,
 * Correct Register for Broxton need to be identified
 * using VBT. hardcoding for now
 */
-   pp_ctrl_reg = BXT_PP_CONTROL(0);
-   pp_on_reg = BXT_PP_ON_DELAYS(0);
-   pp_off_reg = BXT_PP_OFF_DELAYS(0);
+   pp_ctrl_reg = BXT_PP_CONTROL(1);
+   pp_on_reg = BXT_PP_ON_DELAYS(1);
+   pp_off_reg = BXT_PP_OFF_DELAYS(1);
} else if (HAS_PCH_SPLIT(dev)) {
pp_ctrl_reg = PCH_PP_CONTROL;
pp_on_reg = PCH_PP_ON_DELAYS;
@@ -5438,10 +5438,9 @@ intel_dp_init_panel_power_sequencer_registers(struct 
drm_device *dev,
 * Correct Register for Broxton need to be identified
 * using VBT. hardcoding for now
 */
-   pp_ctrl_reg = BXT_PP_CONTROL(0);
-   pp_on_reg = BXT_PP_ON_DELAYS(0);
-   pp_off_reg = BXT_PP_OFF_DELAYS(0);
-
+   pp_ctrl_reg = BXT_PP_CONTROL(1);
+   pp_on_reg = BXT_PP_ON_DELAYS(1);
+   pp_off_reg = BXT_PP_OFF_DELAYS(1);
} else if (HAS_PCH_SPLIT(dev)) {
pp_on_reg = PCH_PP_ON_DELAYS;
pp_off_reg = PCH_PP_OFF_DELAYS;
-- 
2.4.6

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[Intel-gfx] [PATCH 35/43] drm/i915: Move __raw_i915_read8() & co. into i915_drv.h

[ville . syrjala]

From: Ville Syrjälä 

We have a few users of the raw register acces functions outside
intel_uncore.c, so let's just move the functions into intel_drv.h.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_debugfs.c |  2 +-
 drivers/gpu/drm/i915/i915_drv.h | 28 
 drivers/gpu/drm/i915/i915_irq.c |  2 --
 drivers/gpu/drm/i915/intel_uncore.c | 28 
 4 files changed, 29 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 47ef007..2322dac 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1516,7 +1516,7 @@ static int gen6_drpc_info(struct seq_file *m)
seq_printf(m, "RC information accurate: %s\n", yesno(count < 
51));
}
 
-   gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
+   gt_core_status = __raw_i915_read32(dev_priv, GEN6_GT_CORE_STATUS);
trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
 
rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3e35e08..91ed3c2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3502,4 +3502,32 @@ static inline void i915_trace_irq_get(struct 
intel_engine_cs *ring,
i915_gem_request_assign(>trace_irq_req, req);
 }
 
+#define __raw_read(x, s) \
+static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private 
*dev_priv, \
+uint32_t reg) \
+{ \
+   return read##s(dev_priv->regs + reg); \
+}
+
+#define __raw_write(x, s) \
+static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
+  uint32_t reg, uint##x##_t val) \
+{ \
+   write##s(val, dev_priv->regs + reg); \
+}
+__raw_read(8, b)
+__raw_read(16, w)
+__raw_read(32, l)
+__raw_read(64, q)
+
+__raw_write(8, b)
+__raw_write(16, w)
+__raw_write(32, l)
+__raw_write(64, q)
+
+#undef __raw_read
+#undef __raw_write
+
+#define __raw_posting_read(dev_priv__, reg__) 
(void)__raw_i915_read32((dev_priv__), (reg__))
+
 #endif
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d181dab..a6c23b2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -679,8 +679,6 @@ static u32 g4x_get_vblank_counter(struct drm_device *dev, 
int pipe)
 }
 
 /* raw reads, only for fast reads of display block, no need for forcewake etc. 
*/
-#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + 
(reg__))
-
 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 {
struct drm_device *dev = crtc->base.dev;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 5b27ee1..acf9b4b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -29,34 +29,6 @@
 
 #define FORCEWAKE_ACK_TIMEOUT_MS 2
 
-#define __raw_read(x, s) \
-static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private 
*dev_priv, \
-uint32_t reg) \
-{ \
-   return read##s(dev_priv->regs + reg); \
-}
-
-#define __raw_write(x, s) \
-static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
-  uint32_t reg, uint##x##_t val) \
-{ \
-   write##s(val, dev_priv->regs + reg); \
-}
-__raw_read(8, b)
-__raw_read(16, w)
-__raw_read(32, l)
-__raw_read(64, q)
-
-__raw_write(8, b)
-__raw_write(16, w)
-__raw_write(32, l)
-__raw_write(64, q)
-
-#undef __raw_read
-#undef __raw_write
-
-#define __raw_posting_read(dev_priv__, reg__) 
(void)__raw_i915_read32((dev_priv__), (reg__))
-
 static const char * const forcewake_domain_names[] = {
"render",
"blitter",
-- 
2.4.6

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[Intel-gfx] [PATCH 42/43] drm/i915: Prefix raw register defines with underscore

[ville . syrjala]

From: Ville Syrjälä 

Most of our register defines follow the convention that if there's a
need for the raw register offset, that one has an underscore sa a
prefix. The define (possibly parametrized) without the underscore is
the one people should normally use, since it will take into account
all the paramters and other potential offsets that are needed.

Fix up the few stragglers that don't follow this convention.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h | 262 
 1 file changed, 131 insertions(+), 131 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3437934..140076d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4689,37 +4689,37 @@ enum skl_disp_power_wells {
 #define I965_CURSOR_DFT_WM 8
 
 /* Watermark register definitions for SKL */
-#define CUR_WM_A_0 0x70140
-#define CUR_WM_B_0 0x71140
-#define PLANE_WM_1_A_0 0x70240
-#define PLANE_WM_1_B_0 0x71240
-#define PLANE_WM_2_A_0 0x70340
-#define PLANE_WM_2_B_0 0x71340
-#define PLANE_WM_TRANS_1_A_0   0x70268
-#define PLANE_WM_TRANS_1_B_0   0x71268
-#define PLANE_WM_TRANS_2_A_0   0x70368
-#define PLANE_WM_TRANS_2_B_0   0x71368
-#define CUR_WM_TRANS_A_0   0x70168
-#define CUR_WM_TRANS_B_0   0x71168
+#define _CUR_WM_A_00x70140
+#define _CUR_WM_B_00x71140
+#define _PLANE_WM_1_A_00x70240
+#define _PLANE_WM_1_B_00x71240
+#define _PLANE_WM_2_A_00x70340
+#define _PLANE_WM_2_B_00x71340
+#define _PLANE_WM_TRANS_1_A_0  0x70268
+#define _PLANE_WM_TRANS_1_B_0  0x71268
+#define _PLANE_WM_TRANS_2_A_0  0x70368
+#define _PLANE_WM_TRANS_2_B_0  0x71368
+#define _CUR_WM_TRANS_A_0  0x70168
+#define _CUR_WM_TRANS_B_0  0x71168
 #define   PLANE_WM_EN  (1 << 31)
 #define   PLANE_WM_LINES_SHIFT 14
 #define   PLANE_WM_LINES_MASK  0x1f
 #define   PLANE_WM_BLOCKS_MASK 0x3ff
 
-#define CUR_WM_0(pipe) _PIPE(pipe, CUR_WM_A_0, CUR_WM_B_0)
-#define CUR_WM(pipe, level) (CUR_WM_0(pipe) + ((4) * (level)))
-#define CUR_WM_TRANS(pipe) _PIPE(pipe, CUR_WM_TRANS_A_0, CUR_WM_TRANS_B_0)
+#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
+#define CUR_WM(pipe, level) (_CUR_WM_0(pipe) + ((4) * (level)))
+#define CUR_WM_TRANS(pipe) _PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
 
-#define _PLANE_WM_1(pipe) _PIPE(pipe, PLANE_WM_1_A_0, PLANE_WM_1_B_0)
-#define _PLANE_WM_2(pipe) _PIPE(pipe, PLANE_WM_2_A_0, PLANE_WM_2_B_0)
+#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
+#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
 #define _PLANE_WM_BASE(pipe, plane)\
_PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
 #define PLANE_WM(pipe, plane, level)   \
(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
 #define _PLANE_WM_TRANS_1(pipe)\
-   _PIPE(pipe, PLANE_WM_TRANS_1_A_0, PLANE_WM_TRANS_1_B_0)
+   _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, 
_PLANE_WM_TRANS_1_B_0)
 #define _PLANE_WM_TRANS_2(pipe)\
-   _PIPE(pipe, PLANE_WM_TRANS_2_A_0, PLANE_WM_TRANS_2_B_0)
+   _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, 
_PLANE_WM_TRANS_2_B_0)
 #define PLANE_WM_TRANS(pipe, plane)\
_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))
 
@@ -6185,74 +6185,74 @@ enum skl_disp_power_wells {
 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
 
 /* Per-transcoder DIP controls (VLV) */
-#define VLV_VIDEO_DIP_CTL_A(VLV_DISPLAY_BASE + 0x60200)
-#define VLV_VIDEO_DIP_DATA_A   (VLV_DISPLAY_BASE + 0x60208)
-#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A   (VLV_DISPLAY_BASE + 0x60210)
+#define _VLV_VIDEO_DIP_CTL_A   (VLV_DISPLAY_BASE + 0x60200)
+#define _VLV_VIDEO_DIP_DATA_A  (VLV_DISPLAY_BASE + 0x60208)
+#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A  (VLV_DISPLAY_BASE + 0x60210)
 
-#define VLV_VIDEO_DIP_CTL_B(VLV_DISPLAY_BASE + 0x61170)
-#define VLV_VIDEO_DIP_DATA_B   (VLV_DISPLAY_BASE + 0x61174)
-#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B   (VLV_DISPLAY_BASE + 0x61178)
+#define _VLV_VIDEO_DIP_CTL_B   (VLV_DISPLAY_BASE + 0x61170)
+#define _VLV_VIDEO_DIP_DATA_B  (VLV_DISPLAY_BASE + 0x61174)
+#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B  (VLV_DISPLAY_BASE + 0x61178)
 
-#define CHV_VIDEO_DIP_CTL_C(VLV_DISPLAY_BASE + 0x611f0)
-#define CHV_VIDEO_DIP_DATA_C   (VLV_DISPLAY_BASE + 0x611f4)
-#define CHV_VIDEO_DIP_GDCP_PAYLOAD_C   (VLV_DISPLAY_BASE + 0x611f8)
+#define _CHV_VIDEO_DIP_CTL_C   (VLV_DISPLAY_BASE + 0x611f0)
+#define _CHV_VIDEO_DIP_DATA_C  (VLV_DISPLAY_BASE + 0x611f4)
+#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C  (VLV_DISPLAY_BASE + 0x611f8)
 
 

[Intel-gfx] [PATCH 21/43] drm/i915: Add VLV_HDMIB etc. which already include VLV_DISPLAY_BASE

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  |  8 +++-
 drivers/gpu/drm/i915/intel_display.c | 27 ---
 2 files changed, 19 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a8fb5f7..ddfcd68 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3262,7 +3262,9 @@ enum skl_disp_power_wells {
 #define GEN3_SDVOC 0x61160
 #define GEN4_HDMIB GEN3_SDVOB
 #define GEN4_HDMIC GEN3_SDVOC
-#define CHV_HDMID  0x6116C
+#define VLV_HDMIB  (VLV_DISPLAY_BASE + GEN4_HDMIB)
+#define VLV_HDMIC  (VLV_DISPLAY_BASE + GEN4_HDMIC)
+#define CHV_HDMID  (VLV_DISPLAY_BASE + 0x6116C)
 #define PCH_SDVOB  0xe1140
 #define PCH_HDMIB  PCH_SDVOB
 #define PCH_HDMIC  0xe1150
@@ -4091,6 +4093,10 @@ enum skl_disp_power_wells {
 #define DP_C   0x64200
 #define DP_D   0x64300
 
+#define VLV_DP_B   (VLV_DISPLAY_BASE + DP_B)
+#define VLV_DP_C   (VLV_DISPLAY_BASE + DP_C)
+#define CHV_DP_D   (VLV_DISPLAY_BASE + DP_D)
+
 #define   DP_PORT_EN   (1 << 31)
 #define   DP_PIPEB_SELECT  (1 << 30)
 #define   DP_PIPE_MASK (1 << 30)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index fa7c10fa..e20abd5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14009,29 +14009,26 @@ static void intel_setup_outputs(struct drm_device 
*dev)
 * eDP ports. Consult the VBT as well as DP_DETECTED to
 * detect eDP ports.
 */
-   if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
+   if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
!intel_dp_is_edp(dev, PORT_B))
-   intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
-   PORT_B);
-   if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
+   intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
+   if (I915_READ(VLV_DP_B) & DP_DETECTED ||
intel_dp_is_edp(dev, PORT_B))
-   intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
+   intel_dp_init(dev, VLV_DP_B, PORT_B);
 
-   if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
+   if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
!intel_dp_is_edp(dev, PORT_C))
-   intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
-   PORT_C);
-   if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
+   intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
+   if (I915_READ(VLV_DP_C) & DP_DETECTED ||
intel_dp_is_edp(dev, PORT_C))
-   intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
+   intel_dp_init(dev, VLV_DP_C, PORT_C);
 
if (IS_CHERRYVIEW(dev)) {
-   if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & 
SDVO_DETECTED)
-   intel_hdmi_init(dev, VLV_DISPLAY_BASE + 
CHV_HDMID,
-   PORT_D);
/* eDP not supported on port D, so don't check VBT */
-   if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
-   intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, 
PORT_D);
+   if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
+   intel_hdmi_init(dev, CHV_HDMID, PORT_D);
+   if (I915_READ(CHV_DP_D) & DP_DETECTED)
+   intel_dp_init(dev, CHV_DP_D, PORT_D);
}
 
intel_dsi_init(dev);
-- 
2.4.6

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 30/43] drm/i915: Parametrize and fix SWF registers

[ville . syrjala]

From: Ville Syrjälä 

Parametrize the SWF registers. This also fixes the register offsets,
which were mostly garbage in the old defines.

Also save/restore only as many SWF registers that each platform has.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_drv.h |  2 +-
 drivers/gpu/drm/i915/i915_reg.h | 28 +++
 drivers/gpu/drm/i915/i915_suspend.c | 45 -
 3 files changed, 50 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3bf8a9b..3e35e08 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1041,7 +1041,7 @@ struct i915_suspend_saved_registers {
u32 saveMI_ARB_STATE;
u32 saveSWF0[16];
u32 saveSWF1[16];
-   u32 saveSWF2[3];
+   u32 saveSWF3[3];
uint64_t saveFENCE[I915_MAX_NUM_FENCES];
u32 savePCH_PORT_HOTPLUG;
u16 saveGCDGMBUS;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0cc41e4b..57b9469 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4941,20 +4941,20 @@ enum skl_disp_power_wells {
 #define I915_LO_DISPBASE(val)  (val & ~DISP_BASEADDR_MASK)
 #define I915_HI_DISPBASE(val)  (val & DISP_BASEADDR_MASK)
 
-/* VBIOS flags */
-#define SWF00  (dev_priv->info.display_mmio_offset + 0x71410)
-#define SWF01  (dev_priv->info.display_mmio_offset + 0x71414)
-#define SWF02  (dev_priv->info.display_mmio_offset + 0x71418)
-#define SWF03  (dev_priv->info.display_mmio_offset + 0x7141c)
-#define SWF04  (dev_priv->info.display_mmio_offset + 0x71420)
-#define SWF05  (dev_priv->info.display_mmio_offset + 0x71424)
-#define SWF06  (dev_priv->info.display_mmio_offset + 0x71428)
-#define SWF10  (dev_priv->info.display_mmio_offset + 0x70410)
-#define SWF11  (dev_priv->info.display_mmio_offset + 0x70414)
-#define SWF14  (dev_priv->info.display_mmio_offset + 0x71420)
-#define SWF30  (dev_priv->info.display_mmio_offset + 0x72414)
-#define SWF31  (dev_priv->info.display_mmio_offset + 0x72418)
-#define SWF32  (dev_priv->info.display_mmio_offset + 0x7241c)
+/*
+ * VBIOS flags
+ * gen2:
+ * [00:06] alm,mgm
+ * [10:16] all
+ * [30:32] alm,mgm
+ * gen3+:
+ * [00:0f] all
+ * [10:1f] all
+ * [30:32] all
+ */
+#define SWF0(i)(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
+#define SWF1(i)(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
+#define SWF3(i)(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
 
 /* Pipe B */
 #define _PIPEBDSL  (dev_priv->info.display_mmio_offset + 0x71000)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c 
b/drivers/gpu/drm/i915/i915_suspend.c
index 1ccac61..2d91821 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -122,12 +122,24 @@ int i915_save_state(struct drm_device *dev)
dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
 
/* Scratch space */
-   for (i = 0; i < 16; i++) {
-   dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
-   dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
+   if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
+   for (i = 0; i < 7; i++) {
+   dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
+   dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
+   }
+   for (i = 0; i < 3; i++)
+   dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
+   } else if (IS_GEN2(dev_priv)) {
+   for (i = 0; i < 7; i++)
+   dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
+   } else if (HAS_GMCH_DISPLAY(dev_priv)) {
+   for (i = 0; i < 16; i++) {
+   dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
+   dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
+   }
+   for (i = 0; i < 3; i++)
+   dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
}
-   for (i = 0; i < 3; i++)
-   dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
 
mutex_unlock(>struct_mutex);
 
@@ -156,12 +168,25 @@ int i915_restore_state(struct drm_device *dev)
/* Memory arbitration state */
I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 
0x);
 
-   for (i = 0; i < 16; i++) {
-   I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
-   I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
+   /* Scratch space */
+   if 

[Intel-gfx] [PATCH 36/43] drm/i915: Remove the magic AUX_CTL is at DP + foo tricks

[ville . syrjala]

From: Ville Syrjälä 

Currently we determine the location of the AUX registers in a confusing
way. First we assume the PCH registers are used always, but then we
override it for everything but HSW/BDW to use DP+0x10. Very confusing.

Let's just make it straightforward and simply add a few functions to
pick the right AUX_CTL based on the DP port.

To deal with VLV/CHV we'll include the display_mmio_offset into the
AUX register defines.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h |  54 -
 drivers/gpu/drm/i915/intel_dp.c | 124 
 2 files changed, 113 insertions(+), 65 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 57b9469..4e97bf2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4182,33 +4182,33 @@ enum skl_disp_power_wells {
  * is 20 bytes in each direction, hence the 5 fixed
  * data registers
  */
-#define DPA_AUX_CH_CTL 0x64010
-#define DPA_AUX_CH_DATA1   0x64014
-#define DPA_AUX_CH_DATA2   0x64018
-#define DPA_AUX_CH_DATA3   0x6401c
-#define DPA_AUX_CH_DATA4   0x64020
-#define DPA_AUX_CH_DATA5   0x64024
-
-#define DPB_AUX_CH_CTL 0x64110
-#define DPB_AUX_CH_DATA1   0x64114
-#define DPB_AUX_CH_DATA2   0x64118
-#define DPB_AUX_CH_DATA3   0x6411c
-#define DPB_AUX_CH_DATA4   0x64120
-#define DPB_AUX_CH_DATA5   0x64124
-
-#define DPC_AUX_CH_CTL 0x64210
-#define DPC_AUX_CH_DATA1   0x64214
-#define DPC_AUX_CH_DATA2   0x64218
-#define DPC_AUX_CH_DATA3   0x6421c
-#define DPC_AUX_CH_DATA4   0x64220
-#define DPC_AUX_CH_DATA5   0x64224
-
-#define DPD_AUX_CH_CTL 0x64310
-#define DPD_AUX_CH_DATA1   0x64314
-#define DPD_AUX_CH_DATA2   0x64318
-#define DPD_AUX_CH_DATA3   0x6431c
-#define DPD_AUX_CH_DATA4   0x64320
-#define DPD_AUX_CH_DATA5   0x64324
+#define DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010)
+#define DPA_AUX_CH_DATA1   (dev_priv->info.display_mmio_offset + 0x64014)
+#define DPA_AUX_CH_DATA2   (dev_priv->info.display_mmio_offset + 0x64018)
+#define DPA_AUX_CH_DATA3   (dev_priv->info.display_mmio_offset + 0x6401c)
+#define DPA_AUX_CH_DATA4   (dev_priv->info.display_mmio_offset + 0x64020)
+#define DPA_AUX_CH_DATA5   (dev_priv->info.display_mmio_offset + 0x64024)
+
+#define DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110)
+#define DPB_AUX_CH_DATA1   (dev_priv->info.display_mmio_offset + 0x64114)
+#define DPB_AUX_CH_DATA2   (dev_priv->info.display_mmio_offset + 0x64118)
+#define DPB_AUX_CH_DATA3   (dev_priv->info.display_mmio_offset + 0x6411c)
+#define DPB_AUX_CH_DATA4   (dev_priv->info.display_mmio_offset + 0x64120)
+#define DPB_AUX_CH_DATA5   (dev_priv->info.display_mmio_offset + 0x64124)
+
+#define DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210)
+#define DPC_AUX_CH_DATA1   (dev_priv->info.display_mmio_offset + 0x64214)
+#define DPC_AUX_CH_DATA2   (dev_priv->info.display_mmio_offset + 0x64218)
+#define DPC_AUX_CH_DATA3   (dev_priv->info.display_mmio_offset + 0x6421c)
+#define DPC_AUX_CH_DATA4   (dev_priv->info.display_mmio_offset + 0x64220)
+#define DPC_AUX_CH_DATA5   (dev_priv->info.display_mmio_offset + 0x64224)
+
+#define DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310)
+#define DPD_AUX_CH_DATA1   (dev_priv->info.display_mmio_offset + 0x64314)
+#define DPD_AUX_CH_DATA2   (dev_priv->info.display_mmio_offset + 0x64318)
+#define DPD_AUX_CH_DATA3   (dev_priv->info.display_mmio_offset + 0x6431c)
+#define DPD_AUX_CH_DATA4   (dev_priv->info.display_mmio_offset + 0x64320)
+#define DPD_AUX_CH_DATA5   (dev_priv->info.display_mmio_offset + 0x64324)
 
 #define   DP_AUX_CH_CTL_SEND_BUSY  (1 << 31)
 #define   DP_AUX_CH_CTL_DONE   (1 << 30)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7e64555..bd8353f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -743,6 +743,7 @@ static uint32_t i9xx_get_aux_send_ctl(struct intel_dp 
*intel_dp,
 {
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = intel_dig_port->base.base.dev;
+   struct drm_i915_private *dev_priv = to_i915(dev);
uint32_t precharge, timeout;
 
if (IS_GEN6(dev))
@@ -1008,6 +1009,85 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct 
drm_dp_aux_msg *msg)
return ret;
 }
 
+static uint32_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
+   enum port port)
+{
+  

[Intel-gfx] [PATCH 34/43] drm/i915: Turn __raw_i915_read8() & co. in to inline functions

[ville . syrjala]

From: Ville Syrjälä 

There's no need for __raw_i915_read8() & co. bot be macros, so make them
inline funcitons. To avoid typo mistakes generate the inline functions
using preprocessor templates.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_uncore.c | 32 +++-
 1 file changed, 23 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 197ca397..5b27ee1 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -29,19 +29,33 @@
 
 #define FORCEWAKE_ACK_TIMEOUT_MS 2
 
-#define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
-#define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, 
(dev_priv__)->regs + (reg__))
+#define __raw_read(x, s) \
+static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private 
*dev_priv, \
+uint32_t reg) \
+{ \
+   return read##s(dev_priv->regs + reg); \
+}
 
-#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + 
(reg__))
-#define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, 
(dev_priv__)->regs + (reg__))
+#define __raw_write(x, s) \
+static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
+  uint32_t reg, uint##x##_t val) \
+{ \
+   write##s(val, dev_priv->regs + reg); \
+}
+__raw_read(8, b)
+__raw_read(16, w)
+__raw_read(32, l)
+__raw_read(64, q)
 
-#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + 
(reg__))
-#define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, 
(dev_priv__)->regs + (reg__))
+__raw_write(8, b)
+__raw_write(16, w)
+__raw_write(32, l)
+__raw_write(64, q)
 
-#define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + 
(reg__))
-#define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, 
(dev_priv__)->regs + (reg__))
+#undef __raw_read
+#undef __raw_write
 
-#define __raw_posting_read(dev_priv__, reg__) 
(void)__raw_i915_read32(dev_priv__, reg__)
+#define __raw_posting_read(dev_priv__, reg__) 
(void)__raw_i915_read32((dev_priv__), (reg__))
 
 static const char * const forcewake_domain_names[] = {
"render",
-- 
2.4.6

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[Intel-gfx] [PATCH 31/43] drm/i915: Throw out some useless variables

[ville . syrjala]

From: Ville Syrjälä 

Drop some useless 'reg' variables when we only use them once.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_irq.c  |  3 +-
 drivers/gpu/drm/i915/intel_display.c | 70 +++-
 2 files changed, 21 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4b61a42..d181dab 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -674,9 +674,8 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, 
int pipe)
 static u32 g4x_get_vblank_counter(struct drm_device *dev, int pipe)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
-   int reg = PIPE_FRMCOUNT_G4X(pipe);
 
-   return I915_READ(reg);
+   return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 }
 
 /* raw reads, only for fast reads of display block, no need for forcewake etc. 
*/
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 0074781..16e204d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1110,12 +1110,10 @@ static const char *state_string(bool enabled)
 void assert_pll(struct drm_i915_private *dev_priv,
enum pipe pipe, bool state)
 {
-   int reg;
u32 val;
bool cur_state;
 
-   reg = DPLL(pipe);
-   val = I915_READ(reg);
+   val = I915_READ(DPLL(pipe));
cur_state = !!(val & DPLL_VCO_ENABLE);
I915_STATE_WARN(cur_state != state,
 "PLL state assertion failure (expected %s, current %s)\n",
@@ -1172,20 +1170,16 @@ void assert_shared_dpll(struct drm_i915_private 
*dev_priv,
 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
  enum pipe pipe, bool state)
 {
-   int reg;
-   u32 val;
bool cur_state;
enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  pipe);
 
if (HAS_DDI(dev_priv->dev)) {
/* DDI does not have a specific FDI_TX register */
-   reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
-   val = I915_READ(reg);
+   u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
} else {
-   reg = FDI_TX_CTL(pipe);
-   val = I915_READ(reg);
+   u32 val = I915_READ(FDI_TX_CTL(pipe));
cur_state = !!(val & FDI_TX_ENABLE);
}
I915_STATE_WARN(cur_state != state,
@@ -1198,12 +1192,10 @@ static void assert_fdi_tx(struct drm_i915_private 
*dev_priv,
 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
  enum pipe pipe, bool state)
 {
-   int reg;
u32 val;
bool cur_state;
 
-   reg = FDI_RX_CTL(pipe);
-   val = I915_READ(reg);
+   val = I915_READ(FDI_RX_CTL(pipe));
cur_state = !!(val & FDI_RX_ENABLE);
I915_STATE_WARN(cur_state != state,
 "FDI RX state assertion failure (expected %s, current %s)\n",
@@ -1215,7 +1207,6 @@ static void assert_fdi_rx(struct drm_i915_private 
*dev_priv,
 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
  enum pipe pipe)
 {
-   int reg;
u32 val;
 
/* ILK FDI PLL is always enabled */
@@ -1226,20 +1217,17 @@ static void assert_fdi_tx_pll_enabled(struct 
drm_i915_private *dev_priv,
if (HAS_DDI(dev_priv->dev))
return;
 
-   reg = FDI_TX_CTL(pipe);
-   val = I915_READ(reg);
+   val = I915_READ(FDI_TX_CTL(pipe));
I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion 
failure, should be active but is disabled\n");
 }
 
 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
   enum pipe pipe, bool state)
 {
-   int reg;
u32 val;
bool cur_state;
 
-   reg = FDI_RX_CTL(pipe);
-   val = I915_READ(reg);
+   val = I915_READ(FDI_RX_CTL(pipe));
cur_state = !!(val & FDI_RX_PLL_ENABLE);
I915_STATE_WARN(cur_state != state,
 "FDI RX PLL assertion failure (expected %s, current %s)\n",
@@ -1309,8 +1297,6 @@ static void assert_cursor(struct drm_i915_private 
*dev_priv,
 void assert_pipe(struct drm_i915_private *dev_priv,
 enum pipe pipe, bool state)
 {
-   int reg;
-   u32 val;
bool cur_state;
enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  pipe);
@@ -1324,8 +1310,7 @@ void assert_pipe(struct drm_i915_private *dev_priv,
POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
cur_state = false;
} else {
-   reg = 

[Intel-gfx] [PATCH 40/43] drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[]

[ville . syrjala]

From: Ville Syrjälä 

Rather than computing on demand, store also the aux data reg
offsets under intel_dp.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_dp.c  | 49 +++-
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 2 files changed, 34 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 27df240..0e5f674 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -791,7 +791,6 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
-   uint32_t ch_data = ch_ctl + 4;
uint32_t aux_clock_divider;
int i, ret, recv_bytes;
uint32_t status;
@@ -857,7 +856,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
for (try = 0; try < 5; try++) {
/* Load the send data into the aux channel data 
registers */
for (i = 0; i < send_bytes; i += 4)
-   I915_WRITE(ch_data + i,
+   I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
   intel_dp_pack_aux(send + i,
 send_bytes - i));
 
@@ -921,7 +920,7 @@ done:
recv_bytes = recv_size;
 
for (i = 0; i < recv_bytes; i += 4)
-   intel_dp_unpack_aux(I915_READ(ch_data + i),
+   intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 
2]),
recv + i, recv_bytes - i);
 
ret = recv_bytes;
@@ -1009,19 +1008,22 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct 
drm_dp_aux_msg *msg)
return ret;
 }
 
-static uint32_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
-   enum port port)
+static uint32_t g4x_aux_reg(struct drm_i915_private *dev_priv,
+   enum port port, int index)
 {
-   return DP_AUX_CH_CTL(port);
+   return index < 0 ? DP_AUX_CH_CTL(port) :
+   DP_AUX_CH_DATA(port, index);
 }
 
-static uint32_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
-   enum port port)
+static uint32_t ilk_aux_reg(struct drm_i915_private *dev_priv,
+   enum port port, int index)
 {
if (port == PORT_A)
-   return DP_AUX_CH_CTL(port);
+   return index < 0 ? DP_AUX_CH_CTL(port) :
+   DP_AUX_CH_DATA(port, index);
else
-   return PCH_DP_AUX_CH_CTL(port);
+   return index < 0 ? PCH_DP_AUX_CH_CTL(port) :
+   PCH_DP_AUX_CH_DATA(port, index);
 }
 
 /*
@@ -1048,13 +1050,28 @@ static enum port skl_porte_aux_port(struct 
drm_i915_private *dev_priv)
}
 }
 
-static uint32_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
-   enum port port)
+static uint32_t skl_aux_reg(struct drm_i915_private *dev_priv,
+   enum port port, int index)
 {
if (port == PORT_E)
port = skl_porte_aux_port(dev_priv);
 
-   return DP_AUX_CH_CTL(port);
+   return index < 0 ? DP_AUX_CH_CTL(port) :
+   DP_AUX_CH_DATA(port, index);
+}
+
+static void aux_reg_init(struct intel_dp *intel_dp,
+uint32_t (*aux_reg)(struct drm_i915_private *dev_priv,
+enum port port, int index))
+{
+   struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
+   enum port port = dp_to_dig_port(intel_dp)->port;
+   int i;
+
+   intel_dp->aux_ch_ctl_reg = aux_reg(dev_priv, port, -1);
+
+   for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
+   intel_dp->aux_ch_data_reg[i] = aux_reg(dev_priv, port, i);
 }
 
 static void
@@ -1074,11 +1091,11 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct 
intel_connector *connector)
};
 
if (INTEL_INFO(dev_priv)->gen >= 9)
-   intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg(dev_priv, port);
+   aux_reg_init(intel_dp, skl_aux_reg);
else if (HAS_PCH_SPLIT(dev_priv))
-   intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg(dev_priv, port);
+   aux_reg_init(intel_dp, ilk_aux_reg);
else
-   intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg(dev_priv, port);
+   aux_reg_init(intel_dp, g4x_aux_reg);
 
intel_dp->aux.name = ddc_name[port];
intel_dp->aux.dev = dev->dev;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1df6ebf..3fea039 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -717,6 +717,7 @@ struct 

[Intel-gfx] [PATCH 28/43] drm/i915: Turn GEN5_ASSERT_IIR_IS_ZERO() into a function

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_irq.c | 31 +--
 1 file changed, 17 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 16948b2..24f68de 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -139,27 +139,30 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
 /*
  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
  */
-#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
-   u32 val = I915_READ(reg); \
-   if (val) { \
-   WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
-(reg), val); \
-   I915_WRITE((reg), 0x); \
-   POSTING_READ(reg); \
-   I915_WRITE((reg), 0x); \
-   POSTING_READ(reg); \
-   } \
-} while (0)
+static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, u32 reg)
+{
+   u32 val = I915_READ(reg);
+
+   if (val == 0)
+   return;
+
+   WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
+reg, val);
+   I915_WRITE(reg, 0x);
+   POSTING_READ(reg);
+   I915_WRITE(reg, 0x);
+   POSTING_READ(reg);
+}
 
 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
-   GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
+   gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
POSTING_READ(GEN8_##type##_IMR(which)); \
 } while (0)
 
 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
-   GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
+   gen5_assert_iir_is_zero(dev_priv, type##IIR); \
I915_WRITE(type##IER, (ier_val)); \
I915_WRITE(type##IMR, (imr_val)); \
POSTING_READ(type##IMR); \
@@ -3276,7 +3279,7 @@ static void ibx_irq_postinstall(struct drm_device *dev)
else
mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
 
-   GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
+   gen5_assert_iir_is_zero(dev_priv, SDEIIR);
I915_WRITE(SDEIMR, ~mask);
 }
 
-- 
2.4.6

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[Intel-gfx] [PATCH 38/43] drm/i915: Parametrize AUX registes

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  | 102 ---
 drivers/gpu/drm/i915/intel_dp.c  |  45 +++--
 drivers/gpu/drm/i915/intel_psr.c |   5 +-
 3 files changed, 62 insertions(+), 90 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4e97bf2..04b2063 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3062,11 +3062,7 @@ enum skl_disp_power_wells {
 #define   EDP_PSR_IDLE_FRAME_SHIFT 0
 
 #define EDP_PSR_AUX_CTL(dev)   (EDP_PSR_BASE(dev) + 0x10)
-#define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14)
-#define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18)
-#define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c)
-#define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20)
-#define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24)
+#define EDP_PSR_AUX_DATA(dev, i)   (EDP_PSR_BASE(dev) + 0x14 + (i) 
* 4) /* 5 registers */
 
 #define EDP_PSR_STATUS_CTL(dev)(EDP_PSR_BASE(dev) + 
0x40)
 #define   EDP_PSR_STATUS_STATE_MASK(7<<29)
@@ -4182,33 +4178,36 @@ enum skl_disp_power_wells {
  * is 20 bytes in each direction, hence the 5 fixed
  * data registers
  */
-#define DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010)
-#define DPA_AUX_CH_DATA1   (dev_priv->info.display_mmio_offset + 0x64014)
-#define DPA_AUX_CH_DATA2   (dev_priv->info.display_mmio_offset + 0x64018)
-#define DPA_AUX_CH_DATA3   (dev_priv->info.display_mmio_offset + 0x6401c)
-#define DPA_AUX_CH_DATA4   (dev_priv->info.display_mmio_offset + 0x64020)
-#define DPA_AUX_CH_DATA5   (dev_priv->info.display_mmio_offset + 0x64024)
-
-#define DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110)
-#define DPB_AUX_CH_DATA1   (dev_priv->info.display_mmio_offset + 0x64114)
-#define DPB_AUX_CH_DATA2   (dev_priv->info.display_mmio_offset + 0x64118)
-#define DPB_AUX_CH_DATA3   (dev_priv->info.display_mmio_offset + 0x6411c)
-#define DPB_AUX_CH_DATA4   (dev_priv->info.display_mmio_offset + 0x64120)
-#define DPB_AUX_CH_DATA5   (dev_priv->info.display_mmio_offset + 0x64124)
-
-#define DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210)
-#define DPC_AUX_CH_DATA1   (dev_priv->info.display_mmio_offset + 0x64214)
-#define DPC_AUX_CH_DATA2   (dev_priv->info.display_mmio_offset + 0x64218)
-#define DPC_AUX_CH_DATA3   (dev_priv->info.display_mmio_offset + 0x6421c)
-#define DPC_AUX_CH_DATA4   (dev_priv->info.display_mmio_offset + 0x64220)
-#define DPC_AUX_CH_DATA5   (dev_priv->info.display_mmio_offset + 0x64224)
-
-#define DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310)
-#define DPD_AUX_CH_DATA1   (dev_priv->info.display_mmio_offset + 0x64314)
-#define DPD_AUX_CH_DATA2   (dev_priv->info.display_mmio_offset + 0x64318)
-#define DPD_AUX_CH_DATA3   (dev_priv->info.display_mmio_offset + 0x6431c)
-#define DPD_AUX_CH_DATA4   (dev_priv->info.display_mmio_offset + 0x64320)
-#define DPD_AUX_CH_DATA5   (dev_priv->info.display_mmio_offset + 0x64324)
+#define _DPA_AUX_CH_CTL(dev_priv->info.display_mmio_offset + 
0x64010)
+#define _DPA_AUX_CH_DATA1  (dev_priv->info.display_mmio_offset + 0x64014)
+#define _DPA_AUX_CH_DATA2  (dev_priv->info.display_mmio_offset + 0x64018)
+#define _DPA_AUX_CH_DATA3  (dev_priv->info.display_mmio_offset + 0x6401c)
+#define _DPA_AUX_CH_DATA4  (dev_priv->info.display_mmio_offset + 0x64020)
+#define _DPA_AUX_CH_DATA5  (dev_priv->info.display_mmio_offset + 0x64024)
+
+#define _DPB_AUX_CH_CTL(dev_priv->info.display_mmio_offset + 
0x64110)
+#define _DPB_AUX_CH_DATA1  (dev_priv->info.display_mmio_offset + 0x64114)
+#define _DPB_AUX_CH_DATA2  (dev_priv->info.display_mmio_offset + 0x64118)
+#define _DPB_AUX_CH_DATA3  (dev_priv->info.display_mmio_offset + 0x6411c)
+#define _DPB_AUX_CH_DATA4  (dev_priv->info.display_mmio_offset + 0x64120)
+#define _DPB_AUX_CH_DATA5  (dev_priv->info.display_mmio_offset + 0x64124)
+
+#define _DPC_AUX_CH_CTL(dev_priv->info.display_mmio_offset + 
0x64210)
+#define _DPC_AUX_CH_DATA1  (dev_priv->info.display_mmio_offset + 0x64214)
+#define _DPC_AUX_CH_DATA2  (dev_priv->info.display_mmio_offset + 0x64218)
+#define _DPC_AUX_CH_DATA3  (dev_priv->info.display_mmio_offset + 0x6421c)
+#define _DPC_AUX_CH_DATA4  (dev_priv->info.display_mmio_offset + 0x64220)
+#define _DPC_AUX_CH_DATA5  (dev_priv->info.display_mmio_offset + 0x64224)
+
+#define _DPD_AUX_CH_CTL(dev_priv->info.display_mmio_offset + 
0x64310)
+#define _DPD_AUX_CH_DATA1  (dev_priv->info.display_mmio_offset + 0x64314)
+#define 

[Intel-gfx] [PATCH 16/43] drm/i915: s/_CURACNTR/CURCNTR(PIPE_A)/

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  2 +-
 drivers/gpu/drm/i915/intel_display.c | 10 +-
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 24baa5a..47ef007 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2905,7 +2905,7 @@ static bool cursor_active(struct drm_device *dev, int 
pipe)
u32 state;
 
if (IS_845G(dev) || IS_I865G(dev))
-   state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
+   state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
else
state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
 
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index f385dd3..7343e14 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1295,7 +1295,7 @@ static void assert_cursor(struct drm_i915_private 
*dev_priv,
bool cur_state;
 
if (IS_845G(dev) || IS_I865G(dev))
-   cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
+   cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
else
cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
 
@@ -9850,8 +9850,8 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 
base)
/* On these chipsets we can only modify the base/size/stride
 * whilst the cursor is disabled.
 */
-   I915_WRITE(_CURACNTR, 0);
-   POSTING_READ(_CURACNTR);
+   I915_WRITE(CURCNTR(PIPE_A), 0);
+   POSTING_READ(CURCNTR(PIPE_A));
intel_crtc->cursor_cntl = 0;
}
 
@@ -9866,8 +9866,8 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 
base)
}
 
if (intel_crtc->cursor_cntl != cntl) {
-   I915_WRITE(_CURACNTR, cntl);
-   POSTING_READ(_CURACNTR);
+   I915_WRITE(CURCNTR(PIPE_A), cntl);
+   POSTING_READ(CURCNTR(PIPE_A));
intel_crtc->cursor_cntl = cntl;
}
 }
-- 
2.4.6

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[Intel-gfx] [PATCH 32/43] drm/i915: Clean up LVDS register handling

[ville . syrjala]

From: Ville Syrjälä 

Keep single 'lvds_reg' and 'lvds' variable around in
intel_lvds_init(), and read it just once at the start.

Also intel_lvds_get_config() doesn't need to figure out which reg to use
since it can just consult lvds_encoder->reg.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_lvds.c | 30 ++
 1 file changed, 14 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lvds.c 
b/drivers/gpu/drm/i915/intel_lvds.c
index 2c2d1f0..35bad71 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -98,15 +98,11 @@ static void intel_lvds_get_config(struct intel_encoder 
*encoder,
 {
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
-   u32 lvds_reg, tmp, flags = 0;
+   struct intel_lvds_encoder *lvds_encoder = 
to_lvds_encoder(>base);
+   u32 tmp, flags = 0;
int dotclock;
 
-   if (HAS_PCH_SPLIT(dev))
-   lvds_reg = PCH_LVDS;
-   else
-   lvds_reg = LVDS;
-
-   tmp = I915_READ(lvds_reg);
+   tmp = I915_READ(lvds_encoder->reg);
if (tmp & LVDS_HSYNC_POLARITY)
flags |= DRM_MODE_FLAG_NHSYNC;
else
@@ -944,6 +940,7 @@ void intel_lvds_init(struct drm_device *dev)
struct drm_display_mode *downclock_mode = NULL;
struct edid *edid;
struct drm_crtc *crtc;
+   u32 lvds_reg;
u32 lvds;
int pipe;
u8 pin;
@@ -966,8 +963,15 @@ void intel_lvds_init(struct drm_device *dev)
if (dmi_check_system(intel_no_lvds))
return;
 
+   if (HAS_PCH_SPLIT(dev))
+   lvds_reg = PCH_LVDS;
+   else
+   lvds_reg = LVDS;
+
+   lvds = I915_READ(lvds_reg);
+
if (HAS_PCH_SPLIT(dev)) {
-   if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
+   if ((lvds & LVDS_DETECTED) == 0)
return;
if (dev_priv->vbt.edp_support) {
DRM_DEBUG_KMS("disable LVDS for eDP support\n");
@@ -977,8 +981,7 @@ void intel_lvds_init(struct drm_device *dev)
 
pin = GMBUS_PIN_PANEL;
if (!lvds_is_present_in_vbt(dev, )) {
-   u32 reg = HAS_PCH_SPLIT(dev) ? PCH_LVDS : LVDS;
-   if ((I915_READ(reg) & LVDS_PORT_EN) == 0) {
+   if ((lvds & LVDS_PORT_EN) == 0) {
DRM_DEBUG_KMS("LVDS is not present in VBT\n");
return;
}
@@ -1055,11 +1058,7 @@ void intel_lvds_init(struct drm_device *dev)
connector->interlace_allowed = false;
connector->doublescan_allowed = false;
 
-   if (HAS_PCH_SPLIT(dev)) {
-   lvds_encoder->reg = PCH_LVDS;
-   } else {
-   lvds_encoder->reg = LVDS;
-   }
+   lvds_encoder->reg = lvds_reg;
 
/* create the scaling mode property */
drm_mode_create_scaling_mode_property(dev);
@@ -1140,7 +1139,6 @@ void intel_lvds_init(struct drm_device *dev)
if (HAS_PCH_SPLIT(dev))
goto failed;
 
-   lvds = I915_READ(LVDS);
pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
crtc = intel_get_crtc_for_pipe(dev, pipe);
 
-- 
2.4.6

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[Intel-gfx] [PATCH 37/43] drm/i915: Replace the aux ddc name switch statement with a table

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_dp.c | 38 +-
 1 file changed, 13 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index bd8353f..fa4e8b1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1095,28 +1095,14 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct 
intel_connector *connector)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
enum port port = intel_dig_port->port;
-   const char *name = NULL;
int ret;
-
-   switch (port) {
-   case PORT_A:
-   name = "DPDDC-A";
-   break;
-   case PORT_B:
-   name = "DPDDC-B";
-   break;
-   case PORT_C:
-   name = "DPDDC-C";
-   break;
-   case PORT_D:
-   name = "DPDDC-D";
-   break;
-   case PORT_E:
-   name = "DPDDC-E";
-   break;
-   default:
-   BUG();
-   }
+   static const char * const ddc_name[] = {
+   [PORT_A] = "DPDDC-A",
+   [PORT_B] = "DPDDC-B",
+   [PORT_C] = "DPDDC-C",
+   [PORT_D] = "DPDDC-D",
+   [PORT_E] = "DPDDC-E",
+   };
 
if (INTEL_INFO(dev_priv)->gen >= 9)
intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg(dev_priv, port);
@@ -1125,17 +,18 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct 
intel_connector *connector)
else
intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg(dev_priv, port);
 
-   intel_dp->aux.name = name;
+   intel_dp->aux.name = ddc_name[port];
intel_dp->aux.dev = dev->dev;
intel_dp->aux.transfer = intel_dp_aux_transfer;
 
-   DRM_DEBUG_KMS("registering %s bus for %s\n", name,
+   DRM_DEBUG_KMS("registering %s bus for %s\n",
+ intel_dp->aux.name,
  connector->base.kdev->kobj.name);
 
ret = drm_dp_aux_register(_dp->aux);
if (ret < 0) {
DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
- name, ret);
+ intel_dp->aux.name, ret);
return;
}
 
@@ -1143,7 +1130,8 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct 
intel_connector *connector)
_dp->aux.ddc.dev.kobj,
intel_dp->aux.ddc.dev.kobj.name);
if (ret < 0) {
-   DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, 
ret);
+   DRM_ERROR("sysfs_create_link() for %s failed (%d)\n",
+ intel_dp->aux.name, ret);
drm_dp_aux_unregister(_dp->aux);
}
 }
-- 
2.4.6

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[Intel-gfx] [PATCH 39/43] drm/i915: Add dev_priv->psr_mmio_base

[ville . syrjala]

From: Ville Syrjälä 

Drop the EDP_PSR_BASE() thing, and just stick the PSR register offset
under dev_priv, like we for DSI and GPIO for example.

TODO: could probably move a bunch of this kind of stuff into the device
info instead...

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_debugfs.c |  4 ++--
 drivers/gpu/drm/i915/i915_drv.h |  2 ++
 drivers/gpu/drm/i915/i915_reg.h | 15 ---
 drivers/gpu/drm/i915/intel_psr.c| 28 
 4 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 2322dac..38b0e38 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2536,7 +2536,7 @@ static int i915_edp_psr_status(struct seq_file *m, void 
*data)
   yesno(work_busy(_priv->psr.work.work)));
 
if (HAS_DDI(dev))
-   enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
+   enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
else {
for_each_pipe(dev_priv, pipe) {
stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
@@ -2558,7 +2558,7 @@ static int i915_edp_psr_status(struct seq_file *m, void 
*data)
 
/* CHV PSR has no kind of performance counter */
if (HAS_DDI(dev)) {
-   psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
+   psrperf = I915_READ(EDP_PSR_PERF_CNT) &
EDP_PSR_PERF_CNT_MASK;
 
seq_printf(m, "Performance_Counter: %u\n", psrperf);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 91ed3c2..4359af1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1744,6 +1744,8 @@ struct drm_i915_private {
/* MMIO base address for MIPI regs */
uint32_t mipi_mmio_base;
 
+   uint32_t psr_mmio_base;
+
wait_queue_head_t gmbus_wait_queue;
 
struct pci_dev *bridge_dev;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 04b2063..3437934 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3037,8 +3037,9 @@ enum skl_disp_power_wells {
 #define VLV_PSRSTAT(pipe) _PIPE(pipe, _PSRSTATA, _PSRSTATB)
 
 /* HSW+ eDP PSR registers */
-#define EDP_PSR_BASE(dev)   (IS_HASWELL(dev) ? 0x64800 : 
0x6f800)
-#define EDP_PSR_CTL(dev)   (EDP_PSR_BASE(dev) + 0)
+#define HSW_EDP_PSR_BASE   0x64800
+#define BDW_EDP_PSR_BASE   0x6f800
+#define EDP_PSR_CTL(dev_priv->psr_mmio_base + 0)
 #define   EDP_PSR_ENABLE   (1<<31)
 #define   BDW_PSR_SINGLE_FRAME (1<<30)
 #define   EDP_PSR_LINK_STANDBY (1<<27)
@@ -3061,10 +3062,10 @@ enum skl_disp_power_wells {
 #define   EDP_PSR_TP1_TIME_0us (3<<4)
 #define   EDP_PSR_IDLE_FRAME_SHIFT 0
 
-#define EDP_PSR_AUX_CTL(dev)   (EDP_PSR_BASE(dev) + 0x10)
-#define EDP_PSR_AUX_DATA(dev, i)   (EDP_PSR_BASE(dev) + 0x14 + (i) 
* 4) /* 5 registers */
+#define EDP_PSR_AUX_CTL
(dev_priv->psr_mmio_base + 0x10)
+#define EDP_PSR_AUX_DATA(i)(dev_priv->psr_mmio_base + 0x14 
+ (i) * 4) /* 5 registers */
 
-#define EDP_PSR_STATUS_CTL(dev)(EDP_PSR_BASE(dev) + 
0x40)
+#define EDP_PSR_STATUS_CTL (dev_priv->psr_mmio_base + 0x40)
 #define   EDP_PSR_STATUS_STATE_MASK(7<<29)
 #define   EDP_PSR_STATUS_STATE_IDLE(0<<29)
 #define   EDP_PSR_STATUS_STATE_SRDONACK(1<<29)
@@ -3088,10 +3089,10 @@ enum skl_disp_power_wells {
 #define   EDP_PSR_STATUS_SENDING_TP1   (1<<4)
 #define   EDP_PSR_STATUS_IDLE_MASK 0xf
 
-#define EDP_PSR_PERF_CNT(dev)  (EDP_PSR_BASE(dev) + 0x44)
+#define EDP_PSR_PERF_CNT   (dev_priv->psr_mmio_base + 0x44)
 #define   EDP_PSR_PERF_CNT_MASK0xff
 
-#define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60)
+#define EDP_PSR_DEBUG_CTL  (dev_priv->psr_mmio_base + 0x60)
 #define   EDP_PSR_DEBUG_MASK_LPSP  (1<<27)
 #define   EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
 #define   EDP_PSR_DEBUG_MASK_HPD   (1<<25)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index ff66718..90153e7 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -183,9 +183,9 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
DP_AUX_FRAME_SYNC_ENABLE);
 
aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
-   DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(dev, 0);
+   DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(0);
aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
-

[Intel-gfx] [PATCH 41/43] drm/i915: Model PSR AUX register selection more like the normal AUX code

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_psr.c | 20 ++--
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 90153e7..0f944e2 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -151,13 +151,24 @@ static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
 }
 
+static uint32_t psr_aux_reg(struct drm_i915_private *dev_priv,
+   enum port port, int index)
+{
+   if (INTEL_INFO(dev_priv)->gen >= 9)
+   return index < 0 ? DP_AUX_CH_CTL(port) :
+   DP_AUX_CH_DATA(port, index);
+   else
+   return index < 0 ? EDP_PSR_AUX_CTL :
+   EDP_PSR_AUX_DATA(index);
+}
+
 static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 {
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t aux_clock_divider;
-   uint32_t aux_data_reg, aux_ctl_reg;
+   uint32_t aux_ctl_reg;
int precharge = 0x3;
static const uint8_t aux_msg[] = {
[0] = DP_AUX_NATIVE_WRITE << 4,
@@ -182,14 +193,11 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
DP_AUX_FRAME_SYNC_ENABLE);
 
-   aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
-   DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(0);
-   aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
-   DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL;
+   aux_ctl_reg = psr_aux_reg(dev_priv, port, -1);
 
/* Setup AUX registers */
for (i = 0; i < sizeof(aux_msg); i += 4)
-   I915_WRITE(aux_data_reg + i,
+   I915_WRITE(psr_aux_reg(dev_priv, port, i >> 2),
   intel_dp_pack_aux(_msg[i], sizeof(aux_msg) - i));
 
if (INTEL_INFO(dev)->gen >= 9) {
-- 
2.4.6

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[Intel-gfx] [PATCH 29/43] drm/i915: s/PIPE_FRMCOUNT_GM45/PIPE_FRMCOUNT_G4X/ etc.

[ville . syrjala]

From: Ville Syrjälä 

The PIPE_FRMCOUNT_GM45 and PIPE_FLIPCOUNT_GM45 names have bothered me
for a long time. The work equally well for ELK and onwards, so let's
s/GM45/G4X/.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_irq.c  |  6 +++---
 drivers/gpu/drm/i915/i915_reg.h  | 12 ++--
 drivers/gpu/drm/i915/intel_display.c |  4 ++--
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 24f68de..4b61a42 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -671,10 +671,10 @@ static u32 i915_get_vblank_counter(struct drm_device 
*dev, int pipe)
return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xff;
 }
 
-static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
+static u32 g4x_get_vblank_counter(struct drm_device *dev, int pipe)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
-   int reg = PIPE_FRMCOUNT_GM45(pipe);
+   int reg = PIPE_FRMCOUNT_G4X(pipe);
 
return I915_READ(reg);
 }
@@ -4311,7 +4311,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
} else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
dev->max_vblank_count = 0x; /* full 32 bit counter */
-   dev->driver->get_vblank_counter = gm45_get_vblank_counter;
+   dev->driver->get_vblank_counter = g4x_get_vblank_counter;
} else {
dev->driver->get_vblank_counter = i915_get_vblank_counter;
dev->max_vblank_count = 0xff; /* only 24 bits of frame 
count */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 02f0935..0cc41e4b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4796,10 +4796,10 @@ enum skl_disp_power_wells {
 #define   PIPE_PIXEL_MASK 0x00ff
 #define   PIPE_PIXEL_SHIFT0
 /* GM45+ just has to be different */
-#define _PIPEA_FRMCOUNT_GM45   0x70040
-#define _PIPEA_FLIPCOUNT_GM45  0x70044
-#define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45)
-#define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45)
+#define _PIPEA_FRMCOUNT_G4X0x70040
+#define _PIPEA_FLIPCOUNT_G4X   0x70044
+#define PIPE_FRMCOUNT_G4X(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
+#define PIPE_FLIPCOUNT_G4X(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
 
 /* Cursor A & B regs */
 #define _CURACNTR  0x70080
@@ -4962,8 +4962,8 @@ enum skl_disp_power_wells {
 #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
 #define _PIPEBFRAMEHIGH0x71040
 #define _PIPEBFRAMEPIXEL   0x71044
-#define _PIPEB_FRMCOUNT_GM45   (dev_priv->info.display_mmio_offset + 0x71040)
-#define _PIPEB_FLIPCOUNT_GM45  (dev_priv->info.display_mmio_offset + 0x71044)
+#define _PIPEB_FRMCOUNT_G4X(dev_priv->info.display_mmio_offset + 0x71040)
+#define _PIPEB_FLIPCOUNT_G4X   (dev_priv->info.display_mmio_offset + 0x71044)
 
 
 /* Display B control */
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 92e624b..0074781 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10769,7 +10769,7 @@ static bool page_flip_finished(struct intel_crtc *crtc)
 */
return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
crtc->unpin_work->gtt_offset &&
-   
g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
+   
g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
crtc->unpin_work->flip_count);
 }
 
@@ -11374,7 +11374,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
intel_crtc->reset_counter = 
atomic_read(_priv->gpu_error.reset_counter);
 
if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
-   work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
+   work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
 
if (IS_VALLEYVIEW(dev)) {
ring = _priv->ring[BCS];
-- 
2.4.6

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[Intel-gfx] Changing the screen resolution permanently

[Engin FIRAT]

Hello all,

In my system there are two monitors and these monitors are fed by mirrored
displays. To get such a configuration I have created a script that
dynamically adjusts the system by using xrandr. The script is attached as
changeres.sh. Everything works well. However I've note that the system
startup time is increased by ~15 seconds and I do not want such a case. To
handle this problem, I think that I need to adjust the screen resolution
permanently with a xorg.conf file. However I cannot create one that adjusts
the monitors as expected. xorg.conf file is also attached to this post.

Details of the system:
Processor: Intel Atom E3845
OS: Lubuntu 14.04.1
Driver: Installed via intel-graphics-installer 1.0.7

I have tried to create a xorg.conf file with the command X -configure,
however the created file is for only one monitors since the system uses
only the first monitor at its default configuration (ie. no xrandr setting)

Could you please help me to create a correct xorg.conf file.
Regards.


xorg.conf
Description: Binary data


changeres.sh
Description: Bourne shell script
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