[Intel-gfx] [PATCH i-g-t v2] tests/gem_exec_nop: Improved test run time

[Derek Morton]

Reduced the Sleep period to 200mS and reduced the repetition count to 7
to decrease the test run time significantly.

Also fixed a non ascii character that messed up the results table formatting.

v2: Changed uS to us

Signed-off-by: Derek Morton 
---
 tests/gem_exec_nop.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/tests/gem_exec_nop.c b/tests/gem_exec_nop.c
index a287d08..998e0eb 100644
--- a/tests/gem_exec_nop.c
+++ b/tests/gem_exec_nop.c
@@ -133,7 +133,7 @@ static void loop(int fd, uint32_t handle, unsigned ring_id, 
const char *ring_nam
gem_sync(fd, handle);
 
for (count = 1; count <= SLOW_QUICK(1<<17, 1<<4); count <<= 1) {
-   const int reps = 13;
+   const int reps = 7;
igt_stats_t stats;
int n;
 
@@ -142,7 +142,7 @@ static void loop(int fd, uint32_t handle, unsigned ring_id, 
const char *ring_nam
for (n = 0; n < reps; n++) {
struct timespec start, end;
int loops = count;
-   sleep(1); /* wait for the hw to go back to sleep */
+   usleep(20); /* wait 200mS for the hw to go back to 
sleep */
clock_gettime(CLOCK_MONOTONIC, );
while (loops--)
do_ioctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, 
);
@@ -151,7 +151,7 @@ static void loop(int fd, uint32_t handle, unsigned ring_id, 
const char *ring_nam
igt_stats_push(, elapsed(, , count));
}
 
-   igt_info("Time to exec x %d:%7.3fµs (ring=%s)\n",
+   igt_info("Time to exec x %d:%7.3fus (ring=%s)\n",
 count, igt_stats_get_trimean()/1000, ring_name);
fflush(stdout);
 
-- 
1.9.1

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Re: [Intel-gfx] [v3] drm/i915/skl: While sanitizing cdclock check the SWF18 as well

[Thulasimani, Sivakumar]

Reviewed-by: Sivakumar Thulasimani 

On 11/5/2015 3:05 PM, Shobhit Kumar wrote:

SWF18 is set if the display has been intialized by the pre-os. It also
gives what configuration is enabled on which pipe. In skl_sanitize_cdclk,
the DPLL sanity check can pass even if GOP/VBIOS is not loaded as BIOS
enables DPLL for integrated audio codec related programming.
So fisrt check if SWF18 is set and then follow through with other DPLL
and CDCLK verification. If not set then for sure we need to sanitize the
cdclock.

v2: Update the commit message for clarity (Siva)
v3: Correct the mask to check for bits[23:0] instead of only bits[16:0].
 Had missed checking for PIPE C altogether. Remaining are reserved (Siva)

Cc: Ville Syrjälä 
Signed-off-by: Shobhit Kumar 
---
  drivers/gpu/drm/i915/i915_reg.h  | 3 +++
  drivers/gpu/drm/i915/intel_display.c | 8 
  2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9ee9481..bd476ff 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5006,6 +5006,9 @@ enum skl_disp_power_wells {
  #define SWF1(i)   (dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
  #define SWF3(i)   (dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
  
+/* VBIOS flag for display initialized status */

+#define GEN6_SWF18  (dev_priv->info.display_mmio_offset + 0x4F060)
+
  /* Pipe B */
  #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
  #define _PIPEBCONF(dev_priv->info.display_mmio_offset + 0x71008)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 103cacb..81668b0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5761,6 +5761,14 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
uint32_t cdctl = I915_READ(CDCLK_CTL);
int freq = dev_priv->skl_boot_cdclk;
  
+	/*

+* check if the pre-os intialized the display
+* There is SWF18 scratchpad register defined which is set by the
+* pre-os which can be used by the OS drivers to check the status
+*/
+   if ((I915_READ(GEN6_SWF18) & 0x00FF) == 0)
+   goto sanitize;
+
/* Is PLL enabled and locked ? */
if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
goto sanitize;


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[Intel-gfx] [v3] drm/i915/skl: While sanitizing cdclock check the SWF18 as well

[Shobhit Kumar]

SWF18 is set if the display has been intialized by the pre-os. It also
gives what configuration is enabled on which pipe. In skl_sanitize_cdclk,
the DPLL sanity check can pass even if GOP/VBIOS is not loaded as BIOS
enables DPLL for integrated audio codec related programming.
So fisrt check if SWF18 is set and then follow through with other DPLL
and CDCLK verification. If not set then for sure we need to sanitize the
cdclock.

v2: Update the commit message for clarity (Siva)
v3: Correct the mask to check for bits[23:0] instead of only bits[16:0].
Had missed checking for PIPE C altogether. Remaining are reserved (Siva)

Cc: Ville Syrjälä 
Signed-off-by: Shobhit Kumar 
---
 drivers/gpu/drm/i915/i915_reg.h  | 3 +++
 drivers/gpu/drm/i915/intel_display.c | 8 
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9ee9481..bd476ff 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5006,6 +5006,9 @@ enum skl_disp_power_wells {
 #define SWF1(i)(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
 #define SWF3(i)(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
 
+/* VBIOS flag for display initialized status */
+#define GEN6_SWF18  (dev_priv->info.display_mmio_offset + 0x4F060)
+
 /* Pipe B */
 #define _PIPEBDSL  (dev_priv->info.display_mmio_offset + 0x71000)
 #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 103cacb..81668b0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5761,6 +5761,14 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
uint32_t cdctl = I915_READ(CDCLK_CTL);
int freq = dev_priv->skl_boot_cdclk;
 
+   /*
+* check if the pre-os intialized the display
+* There is SWF18 scratchpad register defined which is set by the
+* pre-os which can be used by the OS drivers to check the status
+*/
+   if ((I915_READ(GEN6_SWF18) & 0x00FF) == 0)
+   goto sanitize;
+
/* Is PLL enabled and locked ? */
if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
goto sanitize;
-- 
2.4.3

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Re: [Intel-gfx] [PATCH 03/29] drm/i915: Replace the aux ddc name switch statement with a table

[Ville Syrjälä]

On Thu, Nov 05, 2015 at 02:10:15PM +, Chris Wilson wrote:
> On Wed, Nov 04, 2015 at 11:19:51PM +0200, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä 
> > 
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 38 +-
> >  1 file changed, 13 insertions(+), 25 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index a26995a..62fb95c 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1095,28 +1095,14 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct 
> > intel_connector *connector)
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> > enum port port = intel_dig_port->port;
> > -   const char *name = NULL;
> > int ret;
> > -
> > -   switch (port) {
> > -   case PORT_A:
> > -   name = "DPDDC-A";
> > -   break;
> > -   case PORT_B:
> > -   name = "DPDDC-B";
> > -   break;
> > -   case PORT_C:
> > -   name = "DPDDC-C";
> > -   break;
> > -   case PORT_D:
> > -   name = "DPDDC-D";
> > -   break;
> > -   case PORT_E:
> > -   name = "DPDDC-E";
> > -   break;
> > -   default:
> > -   BUG();
> > -   }
> > +   static const char * const ddc_name[] = {
> > +   [PORT_A] = "DPDDC-A",
> > +   [PORT_B] = "DPDDC-B",
> > +   [PORT_C] = "DPDDC-C",
> > +   [PORT_D] = "DPDDC-D",
> > +   [PORT_E] = "DPDDC-E",
> > +   };
> >  
> > if (INTEL_INFO(dev_priv)->gen >= 9)
> > intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg(dev_priv, port);
> > @@ -1125,17 +,18 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct 
> > intel_connector *connector)
> > else
> > intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg(dev_priv, port);
> >  
> > -   intel_dp->aux.name = name;
> > +   intel_dp->aux.name = ddc_name[port];
> 
> What defense do we have against the introduction of PORT_F and somebody
> forgetting to check here?

None. And I'm the one on the hook for port F actually ;)

> 
> static const char *ddc_name(enum port port) {
>   static const char * const names[] = {
>   [PORT_A] = "DPDDC-A",
>   [PORT_B] = "DPDDC-B",
>   [PORT_C] = "DPDDC-C",
>   [PORT_D] = "DPDDC-D",
>   [PORT_E] = "DPDDC-E",
>   };
>   if (WARN_ON(port >= ARRAY_SIZE(names))
>   return "DPDDC-XXX";
>   return names[port];
> }

We can do that. Or we could just do
kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));

+ error handling and kfree() along drm_dp_aux_unregister()
of course.

-- 
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Intel OTC
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Re: [Intel-gfx] [PATCH 28/29] drm/i915: Add missing ')' to SKL_PS_ECC_STAT define

[Chris Wilson]

On Wed, Nov 04, 2015 at 11:20:16PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> Signed-off-by: Ville Syrjälä 
Reviewed-by: Chris Wilson 
-Chris

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Re: [Intel-gfx] [PATCH 03/29] drm/i915: Replace the aux ddc name switch statement with a table

[Chris Wilson]

On Thu, Nov 05, 2015 at 04:22:09PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 05, 2015 at 02:10:15PM +, Chris Wilson wrote:
> > static const char *ddc_name(enum port port) {
> > static const char * const names[] = {
> > [PORT_A] = "DPDDC-A",
> > [PORT_B] = "DPDDC-B",
> > [PORT_C] = "DPDDC-C",
> > [PORT_D] = "DPDDC-D",
> > [PORT_E] = "DPDDC-E",
> > };
> > if (WARN_ON(port >= ARRAY_SIZE(names))
> > return "DPDDC-XXX";
> > return names[port];
> > }
> 
> We can do that. Or we could just do
> kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
> 
> + error handling and kfree() along drm_dp_aux_unregister()
> of course.

Aye, that's better.
-Chris

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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use insert_page for pwrite_fast

[Tvrtko Ursulin]

On 05/11/15 12:58, Chris Wilson wrote:

On Thu, Nov 05, 2015 at 12:53:20PM +, Tvrtko Ursulin wrote:


On 05/11/15 12:42, Chris Wilson wrote:

On Thu, Nov 05, 2015 at 12:37:46PM +, Tvrtko Ursulin wrote:


On 05/11/15 11:45, ankitprasad.r.sha...@intel.com wrote:

From: Ankitprasad Sharma 

In pwrite_fast, map an object page by page if obj_ggtt_pin fails. First,
we try a nonblocking pin for the whole object (since that is fastest if
reused), then failing that we try to grab one page in the mappable
aperture. It also allows us to handle objects larger than the mappable
aperture (e.g. if we need to pwrite with vGPU restricting the aperture
to a measely 8MiB or something like that).


Aperture in aperture, reminds me of those "Yo dawg I've heard you
like X so I've put X in your X so you can Y while you Y" jokes. :D

Would using the partial view code be interesting for this? Might be
faster due to larger chunks possible, or slower due more expensive
set up time, I don't know.


It's the wrong abstraction.


Looks the same to me, only difference is the size.


There are many places that insert-page is used where we cannot do a
partial-pin.


Why not just to the page aperture then for simplicity? If there is
any performance gain from trying the full VMA first then why there
wouldn't be some to try with the partial VMA?


obj->base.size >> PAGE_SHIFT x partial pages is not even funny.


Well I did not suggest that but larger chunks so I will repeat my question.

If going page by page is fine for performance then why have the two code 
paths at all? One which tries top pin the whole object first, and second 
which goes page by page if that fails. Why not just do it page by page 
and avoid having two copy loops etc?


On the other hand, if there is significant performance hit with the page 
by page path, then why not use partial views with 1Mb chunks or something?


Regards,

Tvrtko
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[Intel-gfx] [v4] drm/i915/skl: While sanitizing cdclock check the SWF18 as well

[Shobhit Kumar]

SWF18 is set if the display has been intialized by the pre-os. It also
gives what configuration is enabled on which pipe. In skl_sanitize_cdclk,
the DPLL sanity check can pass even if GOP/VBIOS is not loaded as BIOS
enables DPLL for integrated audio codec related programming.
So fisrt check if SWF18 is set and then follow through with other DPLL
and CDCLK verification. If not set then for sure we need to sanitize the
cdclock.

v2: Update the commit message for clarity (Siva)
v3: Correct the mask to check for bits[23:0] instead of only bits[16:0].
Had missed checking for PIPE C altogether. Remaining are reserved (Siva)
v4: Use ILK_SWF macro for SWF register definitions. Taken from Ville's patch
http://lists.freedesktop.org/archives/intel-gfx/2015-November/079480.html

Cc: Ville Syrjälä 
Signed-off-by: Shobhit Kumar 
---
 drivers/gpu/drm/i915/i915_reg.h  | 1 +
 drivers/gpu/drm/i915/intel_display.c | 8 
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9ee9481..e8f1d42 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5005,6 +5005,7 @@ enum skl_disp_power_wells {
 #define SWF0(i)(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
 #define SWF1(i)(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
 #define SWF3(i)(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
+#define SWF_ILK(i) (0x4F000 + (i) * 4)
 
 /* Pipe B */
 #define _PIPEBDSL  (dev_priv->info.display_mmio_offset + 0x71000)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 103cacb..512747a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5761,6 +5761,14 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
uint32_t cdctl = I915_READ(CDCLK_CTL);
int freq = dev_priv->skl_boot_cdclk;
 
+   /*
+* check if the pre-os intialized the display
+* There is SWF18 scratchpad register defined which is set by the
+* pre-os which can be used by the OS drivers to check the status
+*/
+   if ((I915_READ(SWF_ILK(0x18)) & 0x00FF) == 0)
+   goto sanitize;
+
/* Is PLL enabled and locked ? */
if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
goto sanitize;
-- 
2.4.3

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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use insert_page for pwrite_fast

[Tvrtko Ursulin]

On 05/11/15 11:45, ankitprasad.r.sha...@intel.com wrote:

From: Ankitprasad Sharma 

In pwrite_fast, map an object page by page if obj_ggtt_pin fails. First,
we try a nonblocking pin for the whole object (since that is fastest if
reused), then failing that we try to grab one page in the mappable
aperture. It also allows us to handle objects larger than the mappable
aperture (e.g. if we need to pwrite with vGPU restricting the aperture
to a measely 8MiB or something like that).


Aperture in aperture, reminds me of those "Yo dawg I've heard you like X 
so I've put X in your X so you can Y while you Y" jokes. :D


Would using the partial view code be interesting for this? Might be 
faster due to larger chunks possible, or slower due more expensive set 
up time, I don't know.


Interesting thing is it was added for virtualization use cases so there 
is overlap here.


Regards,

Tvrtko
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use insert_page for pwrite_fast

[Chris Wilson]

On Thu, Nov 05, 2015 at 12:37:46PM +, Tvrtko Ursulin wrote:
> 
> On 05/11/15 11:45, ankitprasad.r.sha...@intel.com wrote:
> >From: Ankitprasad Sharma 
> >
> >In pwrite_fast, map an object page by page if obj_ggtt_pin fails. First,
> >we try a nonblocking pin for the whole object (since that is fastest if
> >reused), then failing that we try to grab one page in the mappable
> >aperture. It also allows us to handle objects larger than the mappable
> >aperture (e.g. if we need to pwrite with vGPU restricting the aperture
> >to a measely 8MiB or something like that).
> 
> Aperture in aperture, reminds me of those "Yo dawg I've heard you
> like X so I've put X in your X so you can Y while you Y" jokes. :D
> 
> Would using the partial view code be interesting for this? Might be
> faster due to larger chunks possible, or slower due more expensive
> set up time, I don't know.

It's the wrong abstraction.
-Chris

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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use insert_page for pwrite_fast

[Chris Wilson]

On Thu, Nov 05, 2015 at 12:53:20PM +, Tvrtko Ursulin wrote:
> 
> On 05/11/15 12:42, Chris Wilson wrote:
> >On Thu, Nov 05, 2015 at 12:37:46PM +, Tvrtko Ursulin wrote:
> >>
> >>On 05/11/15 11:45, ankitprasad.r.sha...@intel.com wrote:
> >>>From: Ankitprasad Sharma 
> >>>
> >>>In pwrite_fast, map an object page by page if obj_ggtt_pin fails. First,
> >>>we try a nonblocking pin for the whole object (since that is fastest if
> >>>reused), then failing that we try to grab one page in the mappable
> >>>aperture. It also allows us to handle objects larger than the mappable
> >>>aperture (e.g. if we need to pwrite with vGPU restricting the aperture
> >>>to a measely 8MiB or something like that).
> >>
> >>Aperture in aperture, reminds me of those "Yo dawg I've heard you
> >>like X so I've put X in your X so you can Y while you Y" jokes. :D
> >>
> >>Would using the partial view code be interesting for this? Might be
> >>faster due to larger chunks possible, or slower due more expensive
> >>set up time, I don't know.
> >
> >It's the wrong abstraction.
> 
> Looks the same to me, only difference is the size.

There are many places that insert-page is used where we cannot do a
partial-pin.
 
> Why not just to the page aperture then for simplicity? If there is
> any performance gain from trying the full VMA first then why there
> wouldn't be some to try with the partial VMA?

obj->base.size >> PAGE_SHIFT x partial pages is not even funny.
-Chris

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Re: [Intel-gfx] [PATCH 2/2] drm/i915/kbl: Kabylake uses the same GMS values as Skylake

[Jani Nikula]

On Thu, 05 Nov 2015, Rodrigo Vivi  wrote:
> Hi Jani,
>
> could you please consider to merge this already reviewed patch.

Pushed to drm-intel-next-queued, thanks for the patch and review.

BR,
Jani.


>
> Thanks,
> Rodrigo.
>
> On Thu, Oct 29, 2015 at 10:22 AM Rodrigo Vivi 
> wrote:
>
>> From: Deepak S 
>>
>> Reviewed-by: Damien Lespiau 
>> Signed-off-by: Deepak S 
>> Signed-off-by: Damien Lespiau 
>> Signed-off-by: Rodrigo Vivi 
>> ---
>>  arch/x86/kernel/early-quirks.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/x86/kernel/early-quirks.c
>> b/arch/x86/kernel/early-quirks.c
>> index 9f9cc68..5b85bf0 100644
>> --- a/arch/x86/kernel/early-quirks.c
>> +++ b/arch/x86/kernel/early-quirks.c
>> @@ -547,6 +547,7 @@ static const struct pci_device_id intel_stolen_ids[]
>> __initconst = {
>> INTEL_CHV_IDS(_stolen_funcs),
>> INTEL_SKL_IDS(_stolen_funcs),
>> INTEL_BXT_IDS(_stolen_funcs),
>> +   INTEL_KBL_IDS(_stolen_funcs),
>>  };
>>
>>  static void __init intel_graphics_stolen(int num, int slot, int func)
>> --
>> 2.4.3
>>
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Re: [Intel-gfx] [PATCH v2 05/29] drm/i915: Add dev_priv->psr_mmio_base

[Chris Wilson]

On Wed, Nov 04, 2015 at 11:19:53PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> Drop the EDP_PSR_BASE() thing, and just stick the PSR register offset
> under dev_priv, like we for DSI and GPIO for example.
> 
> TODO: could probably move a bunch of this kind of stuff into the device
> info instead...
> 
> v2: Drop the spurious whitespace change (Jani)
> 
> Reviewed-by: Jani Nikula 
> Signed-off-by: Ville Syrjälä 
> ---
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d2a546a..cf0367a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1721,6 +1721,8 @@ struct drm_i915_private {
>   /* MMIO base address for MIPI regs */
>   uint32_t mipi_mmio_base;
>  
> + uint32_t psr_mmio_base;

It appears I'm a bit late to the party, but is there any particular
reason why these two are in the middle of a gmbus block?

I expected that these would be added to intel_device_info (like the very
first display_mmio_offset). Has that fallen out of favour? But if not
intel_device_info, then the psr struct.

The mechanical changes lgtm.
-Chris

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Re: [Intel-gfx] [PATCH 26/29] drm/i915: Add 'offset' to uncore funcs

[Chris Wilson]

On Wed, Nov 04, 2015 at 11:20:14PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> Add 'uint32_t offset' to the uncore register access functions. For now
> it's the same as 'reg', but once type safety gets added 'reg' will be
> the type safe register variable and 'offset' the raw offset.

I presume this is patch 29? (I don't see patch 29/29 :(

But when did we start using off_t? Why would we use a uAPI typedef for an
internal type? I can't wait for you to kill it with fire.

We are mixing lots of uint32_t/u32 here. But the premise of the patch is
sound.
-Chris

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Re: [Intel-gfx] [PATCH] drm/i915: get runtime PM reference around GEM set_caching IOCTL

[Imre Deak]

On ke, 2015-11-04 at 20:57 +, Chris Wilson wrote:
> On Wed, Nov 04, 2015 at 09:25:32PM +0200, Imre Deak wrote:
> > After Damien's D3 fix I started to get runtime suspend residency for the
> > first time and that revealed a breakage on the set_caching IOCTL path
> > that accesses the HW but doesn't take an RPM ref. Fix this up.
> 
> Why here (and in so many random places) and not around the PTE write
> itself?

Imo we should take the RPM ref outside of any of our locks. Otherwise we
need hacks like we have currently in the runtime suspend handler to work
around lock inversions. It works now, but we couldn't do the same trick
if we needed to take struct_mutex for example in the resume handler too
for some reason.

> -Chris
> 


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Re: [Intel-gfx] [PATCH 07/13] drm/i915: don't disable_fbc() if FBC is already disabled

[Ville Syrjälä]

On Wed, Nov 04, 2015 at 05:10:51PM -0200, Paulo Zanoni wrote:
> If FBC is disabled we will still call intel_fbc_invalidate(), and as a
> result we may call intel_fbc_deactivate(), which will try to touch
> registers.
> 
> I'm pretty sure I saw this happen on a runtime suspended device, and

This is one of the BAT failures we have. I don't really understand why
we track the frontbuffer bits with FBC totally disabled, but this fix
seems simple enough on its own. Not sure if it applies without the
others, but if it doesn't I suggest trying to reorder the patchset so
we can put this in ASAP.

> I'm almost sure I was running igt/pm_rpm. It produced the "you touched
> registers while the device is suspended" WARNs. But this was some time
> ago and I can't remember exactly which conditions were necessary to
> reproduce the problem.
> 
> v2: Rebase to new series order.
> 
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/intel_fbc.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c 
> b/drivers/gpu/drm/i915/intel_fbc.c
> index dfb8657..5a853c6 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -438,7 +438,8 @@ static void __intel_fbc_disable(struct drm_i915_private 
> *dev_priv)
>  
>   intel_fbc_cancel_work(dev_priv);
>  
> - dev_priv->fbc.disable_fbc(dev_priv);
> + if (dev_priv->fbc.enabled)
> + dev_priv->fbc.disable_fbc(dev_priv);
>   dev_priv->fbc.crtc = NULL;
>  }
>  
> -- 
> 2.6.1
> 
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Re: [Intel-gfx] [PATCH 26/29] drm/i915: Add 'offset' to uncore funcs

[Ville Syrjälä]

On Thu, Nov 05, 2015 at 10:16:00AM +, Chris Wilson wrote:
> On Wed, Nov 04, 2015 at 11:20:14PM +0200, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä 
> > 
> > Add 'uint32_t offset' to the uncore register access functions. For now
> > it's the same as 'reg', but once type safety gets added 'reg' will be
> > the type safe register variable and 'offset' the raw offset.
> 
> I presume this is patch 29? (I don't see patch 29/29 :(

I presume you since saw 29/29 because you commented on it :)

> 
> But when did we start using off_t? Why would we use a uAPI typedef for an
> internal type? I can't wait for you to kill it with fire.

Looks like

commit 0b27448141bbe9da34a2fdf965dcba6f0f1b75c5
Author: Ben Widawsky 
Date:   Fri Oct 4 21:22:51 2013 -0700

drm/i915: Create MMIO virtual functions

> 
> We are mixing lots of uint32_t/u32 here. But the premise of the patch is
> sound.

I think a lot of people were moving towards uint32_t in recent times,
or at least I was. But given the recent Linus rant, I'm not sure if
we should reverse that direction and just try to stick to u32?

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Re: [Intel-gfx] [PATCH v2 19/29] drm/i915: Add functions to emit register offsets to the ring

[Ville Syrjälä]

On Thu, Nov 05, 2015 at 11:03:38AM +, Chris Wilson wrote:
> On Wed, Nov 04, 2015 at 11:20:07PM +0200, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä 
> > 
> > When register type safety happens, we can't just try to emit the
> > register itself to the ring. Instead we'll need to extract the
> > offset from it first. Add some convenience functions that will do
> > that.
> > 
> > v2: Convert MOCS setup too
> > 
> > Signed-off-by: Ville Syrjälä 
> 
> The only insane thing about this patch is the stupid ring emission API.

One extra idea just popped to my mind. Should I maybe make the
emit_reg() take the value too and emit both the reg offset and value?
They always come in pairs after all.

> Reviewed-by: Chris Wilson 
> -Chris
> 
> -- 
> Chris Wilson, Intel Open Source Technology Centre

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[Intel-gfx] [PATCH 3/3] drm/i915: Use insert_page for pwrite_fast

[ankitprasad . r . sharma]

From: Ankitprasad Sharma 

In pwrite_fast, map an object page by page if obj_ggtt_pin fails. First,
we try a nonblocking pin for the whole object (since that is fastest if
reused), then failing that we try to grab one page in the mappable
aperture. It also allows us to handle objects larger than the mappable
aperture (e.g. if we need to pwrite with vGPU restricting the aperture
to a measely 8MiB or something like that).

Signed-off-by: Ankitprasad Sharma 
---
 drivers/gpu/drm/i915/i915_gem.c | 92 ++---
 1 file changed, 69 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index bf5ef7a..9132240 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -766,14 +766,26 @@ i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 struct drm_file *file)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
+   struct drm_mm_node node;
ssize_t remain;
loff_t offset, page_base;
char __user *user_data;
-   int page_offset, page_length, ret;
+   int page_offset, page_length, ret, i;
+   bool pinned = true;
 
ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
-   if (ret)
-   goto out;
+   if (ret) {
+   pinned = false;
+   memset(, 0, sizeof(node));
+   ret = 
drm_mm_insert_node_in_range_generic(_priv->gtt.base.mm,
+ , 4096, 0,
+ I915_CACHE_NONE, 0,
+ 
dev_priv->gtt.mappable_end,
+ DRM_MM_SEARCH_DEFAULT,
+ 
DRM_MM_CREATE_DEFAULT);
+   if (ret)
+   goto out;
+   }
 
ret = i915_gem_object_set_to_gtt_domain(obj, true);
if (ret)
@@ -786,42 +798,76 @@ i915_gem_gtt_pwrite_fast(struct drm_device *dev,
user_data = to_user_ptr(args->data_ptr);
remain = args->size;
 
-   offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
-
intel_fb_obj_invalidate(obj, ORIGIN_GTT);
 
-   while (remain > 0) {
-   /* Operation in this page
+   if (likely(pinned)) {
+   offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
+   /* Operation in the page
 *
 * page_base = page offset within aperture
 * page_offset = offset within page
-* page_length = bytes to copy for this page
+* page_length = bytes to copy for the page
 */
page_base = offset & PAGE_MASK;
page_offset = offset_in_page(offset);
-   page_length = remain;
-   if ((page_offset + remain) > PAGE_SIZE)
-   page_length = PAGE_SIZE - page_offset;
+   while (remain > 0) {
+   page_length = remain;
+   if ((page_offset + remain) > PAGE_SIZE)
+   page_length = PAGE_SIZE - page_offset;
+
+   /* If we get a fault while copying data, then 
(presumably) our
+* source page isn't available.  Return the error and 
we'll
+* retry in the slow path.
+*/
+   if (fast_user_write(dev_priv->gtt.mappable, page_base,
+   page_offset, user_data, 
page_length)) {
+   ret = -EFAULT;
+   goto out_flush;
+   }
 
-   /* If we get a fault while copying data, then (presumably) our
-* source page isn't available.  Return the error and we'll
-* retry in the slow path.
-*/
-   if (fast_user_write(dev_priv->gtt.mappable, page_base,
-   page_offset, user_data, page_length)) {
-   ret = -EFAULT;
-   goto out_flush;
+   remain -= page_length;
+   user_data += page_length;
+   page_offset = 0;
}
+   } else {
+   i = args->offset / PAGE_SIZE;
+   page_offset = offset_in_page(args->offset);
+   while (remain > 0) {
+   page_length = remain;
+   if ((page_offset + remain) > PAGE_SIZE)
+   page_length = PAGE_SIZE - page_offset;
+
+   wmb();
+   dev_priv->gtt.base.insert_page(_priv->gtt.base,
+   

Re: [Intel-gfx] [PATCH v2 19/29] drm/i915: Add functions to emit register offsets to the ring

[Ville Syrjälä]

On Thu, Nov 05, 2015 at 12:01:51PM +, Chris Wilson wrote:
> On Thu, Nov 05, 2015 at 01:44:08PM +0200, Ville Syrjälä wrote:
> > On Thu, Nov 05, 2015 at 11:03:38AM +, Chris Wilson wrote:
> > > On Wed, Nov 04, 2015 at 11:20:07PM +0200, ville.syrj...@linux.intel.com 
> > > wrote:
> > > > From: Ville Syrjälä 
> > > > 
> > > > When register type safety happens, we can't just try to emit the
> > > > register itself to the ring. Instead we'll need to extract the
> > > > offset from it first. Add some convenience functions that will do
> > > > that.
> > > > 
> > > > v2: Convert MOCS setup too
> > > > 
> > > > Signed-off-by: Ville Syrjälä 
> > > 
> > > The only insane thing about this patch is the stupid ring emission API.
> > 
> > One extra idea just popped to my mind. Should I maybe make the
> > emit_reg() take the value too and emit both the reg offset and value?
> > They always come in pairs after all.
> 
> Uncertain. I think no. You need to do LRI and SRM separately (so that we
> don't get confused between the register value to load and the memory
> address to write to). But the more important factor for me, is that I
> don't want to hide the individual calls to emit() - as they need to be
> easily reviewed and checked against the count given to ring_begin().

Indeed, that's a good reason for keeping it separate.

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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use insert_page for pwrite_fast

[Chris Wilson]

On Thu, Nov 05, 2015 at 05:15:59PM +0530, ankitprasad.r.sha...@intel.com wrote:
> From: Ankitprasad Sharma 
> 
> In pwrite_fast, map an object page by page if obj_ggtt_pin fails. First,
> we try a nonblocking pin for the whole object (since that is fastest if
> reused), then failing that we try to grab one page in the mappable
> aperture. It also allows us to handle objects larger than the mappable
> aperture (e.g. if we need to pwrite with vGPU restricting the aperture
> to a measely 8MiB or something like that).
> 
> Signed-off-by: Ankitprasad Sharma 
> ---
>  drivers/gpu/drm/i915/i915_gem.c | 92 
> ++---
>  1 file changed, 69 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index bf5ef7a..9132240 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -766,14 +766,26 @@ i915_gem_gtt_pwrite_fast(struct drm_device *dev,
>struct drm_file *file)
>  {
>   struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_mm_node node;
>   ssize_t remain;
>   loff_t offset, page_base;
>   char __user *user_data;
> - int page_offset, page_length, ret;
> + int page_offset, page_length, ret, i;
> + bool pinned = true;
>  
>   ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
> - if (ret)
> - goto out;
> + if (ret) {
> + pinned = false;
> + memset(, 0, sizeof(node));
> + ret = 
> drm_mm_insert_node_in_range_generic(_priv->gtt.base.mm,
> +   , 4096, 0,
> +   I915_CACHE_NONE, 0,
> +   
> dev_priv->gtt.mappable_end,
> +   DRM_MM_SEARCH_DEFAULT,
> +   
> DRM_MM_CREATE_DEFAULT);
> + if (ret)
> + goto out;

Prefer to refer to my original patch as to why this wrong.
-Chris

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Re: [Intel-gfx] [PATCH] drm: Use userspace compatible type in fourcc_mod_code macro

[Jani Nikula]

On Wed, 23 Sep 2015, Ville Syrjälä  wrote:
> On Wed, Sep 23, 2015 at 10:10:31AM +0100, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin 
>> 
>> __u64 should be used instead of u64.
>> 
>> Feature originally added in:
>> 
>> commit e3eb3250d84ef97b766312345774367b6a310db8
>> Author: Rob Clark 
>> Date:   Thu Feb 5 14:41:52 2015 +
>> 
>> drm: add support for tiled/compressed/etc modifier in addfb2
>> 
>> Signed-off-by: Tvrtko Ursulin 
>> Cc: Rob Clark 
>> Cc: Daniel Stone 
>> Cc: Daniel Vetter 
>> Cc: dri-de...@lists.freedesktop.org
>> Cc: sta...@vger.kernel.org
>
> Reviewed-by: Ville Syrjälä 

Pushed to our topic/drm-fixes branch, thanks for the patch and review.

BR,
Jani.

>
>> ---
>>  include/uapi/drm/drm_fourcc.h | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>> 
>> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
>> index 8c5e8b91a3cb..0b69a7753558 100644
>> --- a/include/uapi/drm/drm_fourcc.h
>> +++ b/include/uapi/drm/drm_fourcc.h
>> @@ -158,7 +158,7 @@
>>  /* add more to the end as needed */
>>  
>>  #define fourcc_mod_code(vendor, val) \
>> -u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 
>> 0x00ffULL))
>> +__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 
>> 0x00ffULL))
>>  
>>  /*
>>   * Format Modifier tokens:
>> -- 
>> 2.5.1
>> 
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Re: [Intel-gfx] [PATCH 3/4] drm/i915: Sanitize watermarks after hardware state readout (v2)

[Jani Nikula]

On Thu, 05 Nov 2015, Matt Roper  wrote:
> On Wed, Nov 04, 2015 at 04:12:33PM +0200, Jani Nikula wrote:
>> On Tue, 03 Nov 2015, Matt Roper  wrote:
>> > Although we can do a good job of reading out hardware state, the
>> > graphics firmware may have programmed the watermarks in a creative way
>> > that doesn't match how i915 would have chosen to program them.  We
>> > shouldn't trust the firmware's watermark programming, but should rather
>> > re-calculate how we think WM's should be programmed and then shove those
>> > values into the hardware.
>> >
>> > We can do this pretty easily by creating a dummy top-level state,
>> > running it through the check process to calculate all the values, and
>> > then just programming the watermarks for each CRTC.
>> >
>> > v2:  Move watermark sanitization after our BIOS fb reconstruction; the
>> >  watermark calculations that we do here need to look at pstate->fb,
>> >  which isn't setup yet in intel_modeset_setup_hw_state(), even
>> >  though we have an enabled & visible plane.
>> >
>> > Cc: Jani Nikula 
>> > Cc: Maarten Lankhorst 
>> > Signed-off-by: Matt Roper 
>> > ---
>> > Jani, based on your logs it looks like the culprit is that we're 
>> > calculating
>> > watermarks at startup time after we've read out preliminary hardware state 
>> > (so
>> > we know the primary plane is enabled & visible), but before we reconstruct 
>> > the
>> > BIOS fb (so pstate->fb is NULL).  I think moving the watermark sanitization
>> > later in the process so that we'll have a proper fb setup should hopefully
>> > solve the issue.  Can you test this version when you get a chance?  I'll 
>> > also
>> > send a rebased patch #4 since the code movement here means that the 
>> > previous
>> > version won't apply cleanly.
>> 
>> Sorry Matt, black screen with new versions of patches 3-4. Dmesg at
>> http://pastebin.com/3LXZwvWu
>
> Hmm, okay, looks like we're getting closer (successfully avoided the
> divide by zero problem), but I neglected to grab the necessary locks so
> the sanitization doesn't actually happen.  Does applying
> http://paste.debian.net/322932 on top of the series work any better for
> you?  I haven't had time to pull back out an ILK-style system, so that's
> only compile-tested at the moment.

Still warns http://pastebin.com/yGtde5X2

BR,
Jani.


>
>
> Matt
>
>> 
>> BR,
>> Jani.
>> 
>> 
>> 
>> >
>> >  drivers/gpu/drm/i915/i915_drv.h  |  1 +
>> >  drivers/gpu/drm/i915/intel_display.c | 55 
>> > 
>> >  drivers/gpu/drm/i915/intel_pm.c  | 14 +
>> >  3 files changed, 64 insertions(+), 6 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_drv.h 
>> > b/drivers/gpu/drm/i915/i915_drv.h
>> > index 20cd6d8..09807c8 100644
>> > --- a/drivers/gpu/drm/i915/i915_drv.h
>> > +++ b/drivers/gpu/drm/i915/i915_drv.h
>> > @@ -629,6 +629,7 @@ struct drm_i915_display_funcs {
>> >  struct dpll *best_clock);
>> >int (*compute_pipe_wm)(struct intel_crtc *crtc,
>> >   struct drm_atomic_state *state);
>> > +  void (*program_watermarks)(struct intel_crtc_state *cstate);
>> >void (*update_wm)(struct drm_crtc *crtc);
>> >int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
>> >void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
>> > diff --git a/drivers/gpu/drm/i915/intel_display.c 
>> > b/drivers/gpu/drm/i915/intel_display.c
>> > index 7b3cfb6..e289311 100644
>> > --- a/drivers/gpu/drm/i915/intel_display.c
>> > +++ b/drivers/gpu/drm/i915/intel_display.c
>> > @@ -14936,6 +14936,54 @@ void intel_modeset_init_hw(struct drm_device *dev)
>> >intel_enable_gt_powersave(dev);
>> >  }
>> >  
>> > +/*
>> > + * Calculate what we think the watermarks should be for the state we've 
>> > read
>> > + * out of the hardware and then immediately program those watermarks so 
>> > that
>> > + * we ensure the hardware settings match our internal state.
>> > + */
>> > +static void sanitize_watermarks(struct drm_device *dev)
>> > +{
>> > +  struct drm_i915_private *dev_priv = to_i915(dev);
>> > +  struct drm_atomic_state *state;
>> > +  struct drm_crtc *crtc;
>> > +  struct drm_crtc_state *cstate;
>> > +  int ret;
>> > +  int i;
>> > +
>> > +  /* Only supported on platforms that use atomic watermark design */
>> > +  if (!dev_priv->display.program_watermarks)
>> > +  return;
>> > +
>> > +  /*
>> > +   * Calculate what we think WM's should be by creating a dummy state and
>> > +   * running it through the atomic check code.
>> > +   */
>> > +  state = drm_atomic_helper_duplicate_state(dev,
>> > +dev->mode_config.acquire_ctx);
>> > +  if (WARN_ON(IS_ERR(state)))
>> > +  return;
>> > +
>> > +  ret = intel_atomic_check(dev, state);
>> > +  if (ret) {
>> > +  /*
>> > + 

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use insert_page for pwrite_fast

[Tvrtko Ursulin]

On 05/11/15 12:42, Chris Wilson wrote:

On Thu, Nov 05, 2015 at 12:37:46PM +, Tvrtko Ursulin wrote:


On 05/11/15 11:45, ankitprasad.r.sha...@intel.com wrote:

From: Ankitprasad Sharma 

In pwrite_fast, map an object page by page if obj_ggtt_pin fails. First,
we try a nonblocking pin for the whole object (since that is fastest if
reused), then failing that we try to grab one page in the mappable
aperture. It also allows us to handle objects larger than the mappable
aperture (e.g. if we need to pwrite with vGPU restricting the aperture
to a measely 8MiB or something like that).


Aperture in aperture, reminds me of those "Yo dawg I've heard you
like X so I've put X in your X so you can Y while you Y" jokes. :D

Would using the partial view code be interesting for this? Might be
faster due to larger chunks possible, or slower due more expensive
set up time, I don't know.


It's the wrong abstraction.


Looks the same to me, only difference is the size.

Why not just to the page aperture then for simplicity? If there is any 
performance gain from trying the full VMA first then why there wouldn't 
be some to try with the partial VMA?


Regards,

Tvrtko
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Re: [Intel-gfx] [v4] drm/i915/skl: While sanitizing cdclock check the SWF18 as well

[Jani Nikula]

On Thu, 05 Nov 2015, Shobhit Kumar  wrote:
> SWF18 is set if the display has been intialized by the pre-os. It also
> gives what configuration is enabled on which pipe. In skl_sanitize_cdclk,
> the DPLL sanity check can pass even if GOP/VBIOS is not loaded as BIOS
> enables DPLL for integrated audio codec related programming.
> So fisrt check if SWF18 is set and then follow through with other DPLL
> and CDCLK verification. If not set then for sure we need to sanitize the
> cdclock.
>
> v2: Update the commit message for clarity (Siva)
> v3: Correct the mask to check for bits[23:0] instead of only bits[16:0].
> Had missed checking for PIPE C altogether. Remaining are reserved (Siva)
> v4: Use ILK_SWF macro for SWF register definitions. Taken from Ville's patch
> http://lists.freedesktop.org/archives/intel-gfx/2015-November/079480.html
>
> Cc: Ville Syrjälä 
> Signed-off-by: Shobhit Kumar 

Pushed to drm-intel-next-queued, thanks for the patch and review.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 1 +
>  drivers/gpu/drm/i915/intel_display.c | 8 
>  2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9ee9481..e8f1d42 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5005,6 +5005,7 @@ enum skl_disp_power_wells {
>  #define SWF0(i)  (dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
>  #define SWF1(i)  (dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
>  #define SWF3(i)  (dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
> +#define SWF_ILK(i)   (0x4F000 + (i) * 4)
>  
>  /* Pipe B */
>  #define _PIPEBDSL(dev_priv->info.display_mmio_offset + 0x71000)
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 103cacb..512747a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5761,6 +5761,14 @@ int skl_sanitize_cdclk(struct drm_i915_private 
> *dev_priv)
>   uint32_t cdctl = I915_READ(CDCLK_CTL);
>   int freq = dev_priv->skl_boot_cdclk;
>  
> + /*
> +  * check if the pre-os intialized the display
> +  * There is SWF18 scratchpad register defined which is set by the
> +  * pre-os which can be used by the OS drivers to check the status
> +  */
> + if ((I915_READ(SWF_ILK(0x18)) & 0x00FF) == 0)
> + goto sanitize;
> +
>   /* Is PLL enabled and locked ? */
>   if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
>   goto sanitize;

-- 
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Re: [Intel-gfx] [PATCH 07/22] drm/i915: Make intel_dp_source_supports_hbr2() take an intel_dp pointer

[Ander Conselvan De Oliveira]

On Sun, 2015-10-25 at 08:18 +0530, Thulasimani, Sivakumar wrote:
> Reviewed-by: Sivakumar Thulasimani 

Thanks for reviewing. I pushed the patches up to here.

Ander

> On 10/23/2015 3:31 PM, Ander Conselvan de Oliveira wrote:
> > The function name implies it should get intel_dp, and it mostly used
> > where there is an intel_dp in the context.
> > 
> > Signed-off-by: Ander Conselvan de Oliveira <
> > ander.conselvan.de.olive...@intel.com>
> > ---
> >   drivers/gpu/drm/i915/intel_dp.c   | 19 +++
> >   drivers/gpu/drm/i915/intel_dp_link_training.c |  4 +---
> >   drivers/gpu/drm/i915/intel_drv.h  |  2 +-
> >   3 files changed, 13 insertions(+), 12 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 5b04ade..5344de4 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1189,8 +1189,11 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const
> > int **sink_rates)
> > return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
> >   }
> >   
> > -bool intel_dp_source_supports_hbr2(struct drm_device *dev)
> > +bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
> >   {
> > +   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > +   struct drm_device *dev = dig_port->base.base.dev;
> > +
> > /* WaDisableHBR2:skl */
> > if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
> > return false;
> > @@ -1203,8 +1206,10 @@ bool intel_dp_source_supports_hbr2(struct drm_device
> > *dev)
> >   }
> >   
> >   static int
> > -intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
> > +intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
> >   {
> > +   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > +   struct drm_device *dev = dig_port->base.base.dev;
> > int size;
> >   
> > if (IS_BROXTON(dev)) {
> > @@ -1219,7 +1224,7 @@ intel_dp_source_rates(struct drm_device *dev, const
> > int **source_rates)
> > }
> >   
> > /* This depends on the fact that 5.4 is last value in the array */
> > -   if (!intel_dp_source_supports_hbr2(dev))
> > +   if (!intel_dp_source_supports_hbr2(intel_dp))
> > size--;
> >   
> > return size;
> > @@ -1284,12 +1289,11 @@ static int intersect_rates(const int *source_rates,
> > int source_len,
> >   static int intel_dp_common_rates(struct intel_dp *intel_dp,
> >  int *common_rates)
> >   {
> > -   struct drm_device *dev = intel_dp_to_dev(intel_dp);
> > const int *source_rates, *sink_rates;
> > int source_len, sink_len;
> >   
> > sink_len = intel_dp_sink_rates(intel_dp, _rates);
> > -   source_len = intel_dp_source_rates(dev, _rates);
> > +   source_len = intel_dp_source_rates(intel_dp, _rates);
> >   
> > return intersect_rates(source_rates, source_len,
> >sink_rates, sink_len,
> > @@ -1314,7 +1318,6 @@ static void snprintf_int_array(char *str, size_t len,
> >   
> >   static void intel_dp_print_rates(struct intel_dp *intel_dp)
> >   {
> > -   struct drm_device *dev = intel_dp_to_dev(intel_dp);
> > const int *source_rates, *sink_rates;
> > int source_len, sink_len, common_len;
> > int common_rates[DP_MAX_SUPPORTED_RATES];
> > @@ -1323,7 +1326,7 @@ static void intel_dp_print_rates(struct intel_dp
> > *intel_dp)
> > if ((drm_debug & DRM_UT_KMS) == 0)
> > return;
> >   
> > -   source_len = intel_dp_source_rates(dev, _rates);
> > +   source_len = intel_dp_source_rates(intel_dp, _rates);
> > snprintf_int_array(str, sizeof(str), source_rates, source_len);
> > DRM_DEBUG_KMS("source rates: %s\n", str);
> >   
> > @@ -3711,7 +3714,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
> > }
> >   
> > DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
> > - yesno(intel_dp_source_supports_hbr2(dev)),
> > + yesno(intel_dp_source_supports_hbr2(intel_dp)),
> >   yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
> >   
> > /* Intermediate frequency support */
> > diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c
> > b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > index bb036d5..793 100644
> > --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > @@ -218,8 +218,6 @@ intel_dp_link_training_clock_recovery(struct intel_dp
> > *intel_dp)
> >   static void
> >   intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
> >   {
> > -   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > -   struct drm_device *dev = dig_port->base.base.dev;
> > bool channel_eq = false;
> > int tries, cr_tries;
> > uint32_t training_pattern = DP_TRAINING_PATTERN_2;
> > @@ -233,7 +231,7 @@ intel_dp_link_training_channel_equalization(struct
> > intel_dp *intel_dp)

Re: [Intel-gfx] [PATCH v2 19/29] drm/i915: Add functions to emit register offsets to the ring

[Chris Wilson]

On Wed, Nov 04, 2015 at 11:20:07PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> When register type safety happens, we can't just try to emit the
> register itself to the ring. Instead we'll need to extract the
> offset from it first. Add some convenience functions that will do
> that.
> 
> v2: Convert MOCS setup too
> 
> Signed-off-by: Ville Syrjälä 

The only insane thing about this patch is the stupid ring emission API.
Reviewed-by: Chris Wilson 
-Chris

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Re: [Intel-gfx] [PATCH 18/29] drm/i915: Make the cmd parser 64bit regs explicit

[Chris Wilson]

On Wed, Nov 04, 2015 at 11:20:06PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> Add defines for the upper halves of the registers used by the cmd
> parser. Getting rid of the arithmetic with the register offset
> will help in making registers type safe.
> 
> Signed-off-by: Ville Syrjälä 
Reviewed-by: Chris Wilson 
-Chris

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[Intel-gfx] [PATCH] drm/i915: Do graphics device reset under forcewake

[Mika Kuoppala]

We have a timed release of a forcewake when using
I915_READ/WRITE macros. wait_for() macro will go to quite
long sleep if the first read doesn't satisfy the condition for
successful exit. With these two interacting, it is possible that
we lose the forcewake during the wait_for() and the subsequent read
will reaquire forcewake.

Further experiments with skl shows that when we lose forcewake,
we lose the reset request we submitted. So reset request register
is not power context saved.

Grab forcewakes for all engines before starting the reset/request
dance so that all requests stay valid for the duration of reset
requisition across all the engines.

v2: Add comment on power well sleeps. Wrap the reset handling
under forcewake instead of just reset requests (Chris)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92774
Cc: Chris Wilson 
Tested-by: Tomi Sarvela  (v1, v2)
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_uncore.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index f0f97b2..5bb269c 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1530,13 +1530,22 @@ static int (*intel_get_gpu_reset(struct drm_device 
*dev))(struct drm_device *)
 
 int intel_gpu_reset(struct drm_device *dev)
 {
+   struct drm_i915_private *dev_priv = to_i915(dev);
int (*reset)(struct drm_device *);
+   int ret;
 
reset = intel_get_gpu_reset(dev);
if (reset == NULL)
return -ENODEV;
 
-   return reset(dev);
+   /* If the power well sleeps during the reset, the reset
+* request may be dropped and never completes (causing -EIO).
+*/
+   intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+   ret = reset(dev);
+   intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+   return ret;
 }
 
 bool intel_has_gpu_reset(struct drm_device *dev)
-- 
2.5.0

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Re: [Intel-gfx] [PATCH] drm/i915: Do graphics device reset under forcewake

[Chris Wilson]

On Thu, Nov 05, 2015 at 01:11:38PM +0200, Mika Kuoppala wrote:
> We have a timed release of a forcewake when using
> I915_READ/WRITE macros. wait_for() macro will go to quite
> long sleep if the first read doesn't satisfy the condition for
> successful exit. With these two interacting, it is possible that
> we lose the forcewake during the wait_for() and the subsequent read
> will reaquire forcewake.
> 
> Further experiments with skl shows that when we lose forcewake,
> we lose the reset request we submitted. So reset request register
> is not power context saved.
> 
> Grab forcewakes for all engines before starting the reset/request
> dance so that all requests stay valid for the duration of reset
> requisition across all the engines.
> 
> v2: Add comment on power well sleeps. Wrap the reset handling
> under forcewake instead of just reset requests (Chris)
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92774
> Cc: Chris Wilson 
> Tested-by: Tomi Sarvela  (v1, v2)
> Signed-off-by: Mika Kuoppala 
Reviewed-by: Chris Wilson 
-Chris

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Re: [Intel-gfx] [PATCH 17/29] drm/i915: Make the high dword offset more explicit in i915_reg_read_ioctl

[Ville Syrjälä]

On Thu, Nov 05, 2015 at 10:59:05AM +, Chris Wilson wrote:
> On Wed, Nov 04, 2015 at 11:20:05PM +0200, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä 
> > 
> > Store the upper dword of the register offset in the whitelist as well.
> > This would allow it to read register where the two halves aren't sitting
> > right next to each other, and it'll make it easier to make register
> > access type safe.
> > 
> > While at it change the register offsets to u32 from u64. Our register
> > space isn't quite that big, yet :)
> > 
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h |  1 +
> >  drivers/gpu/drm/i915/intel_uncore.c | 10 ++
> >  2 files changed, 7 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 0510ca1..7cea51d 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1567,6 +1567,7 @@ enum skl_disp_power_wells {
> >  #define RING_IMR(base) ((base)+0xa8)
> >  #define RING_HWSTAM(base)  ((base)+0x98)
> >  #define RING_TIMESTAMP(base)   ((base)+0x358)
> > +#define RING_TIMESTAMP_HI(base)((base)+0x358 + 4)
> >  #define   TAIL_ADDR0x0018
> >  #define   HEAD_WRAP_COUNT  0xFFE0
> >  #define   HEAD_WRAP_ONE0x0020
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
> > b/drivers/gpu/drm/i915/intel_uncore.c
> > index f0f97b2..ced494a 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -1261,12 +1261,13 @@ void intel_uncore_fini(struct drm_device *dev)
> >  #define GEN_RANGE(l, h) GENMASK(h, l)
> >  
> >  static const struct register_whitelist {
> > -   uint64_t offset;
> > +   uint32_t offset, offset_hi;
> 
> Hmm, fwiw I was confused here thinking that you were storing a 64bit
> value split across the two u32. (I know that's silly but it has been
> common enough in the past.) Maybe offset_ldw and offset_udw?

Hmm. Yeah, I suppose I've been rather inconsistent with the low/high
dword stuff. Although some inconsistency was already there before I
started I think. Should we try to standardize on ldw/udw everywhere?

And what about cases where we had the ldw only on olders gens, and
the udw got added later, do we still want to put the _LDW suffix in
there, or just have FOO and FOO_UDW?

> 
> I'm not sure though if this is something that we are going to be reading
> enough that taking an extra few seconds to trace usage of
> offset/offset_hi is going to matter much.
> 
> Reviewed-by: Chris Wilson 
> 
> We should probably also document that when passing a reg_read for a u64
> register (that may or may not be split depending on gen) we always
> specify the offset of the lower 32bits.

I'll see about adding a note somewhere.

-- 
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Re: [Intel-gfx] [PATCH 15/29] drm/i915: Parametrize MOCS registers

[Chris Wilson]

On Wed, Nov 04, 2015 at 11:20:03PM +0200, ville.syrj...@linux.intel.com wrote:
>   if (get_mocs_settings(req->ring->dev, )) {
>   /* Program the control registers */
> - ret = emit_mocs_control_table(req, , GEN9_GFX_MOCS_0);
> + ret = emit_mocs_control_table(req, , RCS);
>   if (ret)
>   return ret;
>  
> - ret = emit_mocs_control_table(req, , GEN9_MFX0_MOCS_0);
> + ret = emit_mocs_control_table(req, , VCS);
>   if (ret)
>   return ret;
>  
> - ret = emit_mocs_control_table(req, , GEN9_MFX1_MOCS_0);
> + ret = emit_mocs_control_table(req, , VCS2);
>   if (ret)
>   return ret;
>  
> - ret = emit_mocs_control_table(req, , GEN9_VEBOX_MOCS_0);
> + ret = emit_mocs_control_table(req, , VECS);
>   if (ret)
>   return ret;
>  
> - ret = emit_mocs_control_table(req, , GEN9_BLT_MOCS_0);
> + ret = emit_mocs_control_table(req, , BCS);
>   if (ret)
>   return ret;

For bonus points!

if (get_mocs_settings())
for_each_ring(dev_priv, ring, i) {
ret = emit_mocs_control_table(req, , i);
if (ret)
return ret;
}

And then I am definitely sold.
-Chris

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Re: [Intel-gfx] [PATCH] drm/i915: get runtime PM reference around GEM set_caching IOCTL

[Chris Wilson]

On Thu, Nov 05, 2015 at 01:28:32PM +0200, Imre Deak wrote:
> On ke, 2015-11-04 at 20:57 +, Chris Wilson wrote:
> > On Wed, Nov 04, 2015 at 09:25:32PM +0200, Imre Deak wrote:
> > > After Damien's D3 fix I started to get runtime suspend residency for the
> > > first time and that revealed a breakage on the set_caching IOCTL path
> > > that accesses the HW but doesn't take an RPM ref. Fix this up.
> > 
> > Why here (and in so many random places) and not around the PTE write
> > itself?
> 
> Imo we should take the RPM ref outside of any of our locks. Otherwise we
> need hacks like we have currently in the runtime suspend handler to work
> around lock inversions. It works now, but we couldn't do the same trick
> if we needed to take struct_mutex for example in the resume handler too
> for some reason.

On the other hand, it leads to hard to track down bugs and improper
documentation. Neither solution is perfect.

Note since intel_runtime_suspend has ample barriers of its own, you can
avoid the struct_mutex if you have a dedicated dev_priv->mm.fault_list.

Something along the lines of:

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 86734be..fe91ce5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -180,11 +180,11 @@ describe_obj(struct seq_file *m, struct 
drm_i915_gem_object *obj)
}
if (obj->stolen)
seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
-   if (obj->pin_display || obj->fault_mappable) {
+   if (obj->pin_display || !list_empty(>fault_link)) {
char s[3], *t = s;
if (obj->pin_display)
*t++ = 'p';
-   if (obj->fault_mappable)
+   if (!list_empty(>fault_link))
*t++ = 'f';
*t = '\0';
seq_printf(m, " (%s mappable)", s);
@@ -474,7 +474,7 @@ static int i915_gem_object_info(struct seq_file *m, void* 
data)
 
size = count = mappable_size = mappable_count = 0;
list_for_each_entry(obj, _priv->mm.bound_list, global_list) {
-   if (obj->fault_mappable) {
+   if (!list_empty(>fault_link)) {
size += i915_gem_obj_ggtt_size(obj);
++count;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1d88745..179594e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1447,28 +1447,10 @@ static int intel_runtime_suspend(struct device *device)
DRM_DEBUG_KMS("Suspending device\n");
 
/*
-* We could deadlock here in case another thread holding struct_mutex
-* calls RPM suspend concurrently, since the RPM suspend will wait
-* first for this RPM suspend to finish. In this case the concurrent
-* RPM resume will be followed by its RPM suspend counterpart. Still
-* for consistency return -EAGAIN, which will reschedule this suspend.
-*/
-   if (!mutex_trylock(>struct_mutex)) {
-   DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
-   /*
-* Bump the expiration timestamp, otherwise the suspend won't
-* be rescheduled.
-*/
-   pm_runtime_mark_last_busy(device);
-
-   return -EAGAIN;
-   }
-   /*
 * We are safe here against re-faults, since the fault handler takes
 * an RPM reference.
 */
i915_gem_release_all_mmaps(dev_priv);
-   mutex_unlock(>struct_mutex);
 
intel_suspend_gt_powersave(dev);
intel_runtime_pm_disable_interrupts(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 55611d8..5e4904a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1268,6 +1268,8 @@ struct i915_gem_mm {
 */
struct list_head unbound_list;
 
+   struct list_head fault_list;
+
/** Usable portion of the GTT for GEM */
unsigned long stolen_base; /* limited to low memory (32-bit) */
 
@@ -2025,6 +2027,8 @@ struct drm_i915_gem_object {
 
struct list_head batch_pool_link;
 
+   struct list_head fault_link;
+
/**
 * This is set if the object is on the active lists (has pending
 * rendering and so a non-zero seqno), and is not set if it i s on
@@ -2069,13 +2073,6 @@ struct drm_i915_gem_object {
 */
unsigned int map_and_fenceable:1;
 
-   /**
-* Whether the current gtt mapping needs to be mappable (and isn't just
-* mappable by accident). Track pin and fault separate for a more
-* accurate mappable working set.
-*/
-   unsigned int fault_mappable:1;
-
/*
 * Is the object to be mapped as read-only to the GPU
 * Only honoured if hardware has relevant pte bit
diff --git 

Re: [Intel-gfx] [PATCH] drm/i915: Skip fence installation for objects with rotated views (v4)

[Jani Nikula]

On Fri, 30 Oct 2015, Ville Syrjälä  wrote:
> On Thu, Oct 29, 2015 at 06:54:38PM -0700, Vivek Kasireddy wrote:
>> While pinning a fb object to the display plane, only install a fence
>> if the object is using a normal view. This corresponds with the
>> behavior found in i915_gem_object_do_pin() where the fencability
>> criteria is determined only for objects with normal views.
>> 
>> v2:
>> Look at the object's map_and_fenceable flag to determine whether to
>> install a fence or not (Chris).
>> 
>> v3:
>> Pin and unpin a fence only if the current view type is normal.
>> 
>> v4:
>> Extend the "view type is normal" check for pin_fence as well.
>> 
>> Cc: Chris Wilson 
>> Cc: Tvrtko Ursulin 
>> Cc: Ville Syrjala 
>> Signed-off-by: Vivek Kasireddy 
>
> lgtm
> Reviewed-by: Ville Syrjälä 

Pushed to drm-intel-next-fixes, thanks for the patch and review.

BR,
Jani.

>
>> ---
>>  drivers/gpu/drm/i915/intel_display.c | 36 
>> 
>>  1 file changed, 20 insertions(+), 16 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_display.c 
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 2fdfca1..9c80968 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -2419,22 +2419,24 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
>>   * framebuffer compression.  For simplicity, we always install
>>   * a fence as the cost is not that onerous.
>>   */
>> -ret = i915_gem_object_get_fence(obj);
>> -if (ret == -EDEADLK) {
>> -/*
>> - * -EDEADLK means there are no free fences
>> - * no pending flips.
>> - *
>> - * This is propagated to atomic, but it uses
>> - * -EDEADLK to force a locking recovery, so
>> - * change the returned error to -EBUSY.
>> - */
>> -ret = -EBUSY;
>> -goto err_unpin;
>> -} else if (ret)
>> -goto err_unpin;
>> +if (view.type == I915_GGTT_VIEW_NORMAL) {
>> +ret = i915_gem_object_get_fence(obj);
>> +if (ret == -EDEADLK) {
>> +/*
>> + * -EDEADLK means there are no free fences
>> + * no pending flips.
>> + *
>> + * This is propagated to atomic, but it uses
>> + * -EDEADLK to force a locking recovery, so
>> + * change the returned error to -EBUSY.
>> + */
>> +ret = -EBUSY;
>> +goto err_unpin;
>> +} else if (ret)
>> +goto err_unpin;
>>  
>> -i915_gem_object_pin_fence(obj);
>> +i915_gem_object_pin_fence(obj);
>> +}
>>  
>>  dev_priv->mm.interruptible = true;
>>  intel_runtime_pm_put(dev_priv);
>> @@ -2460,7 +2462,9 @@ static void intel_unpin_fb_obj(struct drm_framebuffer 
>> *fb,
>>  ret = intel_fill_fb_ggtt_view(, fb, plane_state);
>>  WARN_ONCE(ret, "Couldn't get view from plane state!");
>>  
>> -i915_gem_object_unpin_fence(obj);
>> +if (view.type == I915_GGTT_VIEW_NORMAL)
>> +i915_gem_object_unpin_fence(obj);
>> +
>>  i915_gem_object_unpin_from_display_plane(obj, );
>>  }
>>  
>> -- 
>> 2.4.3

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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Add soft-pinning API for execbuffer

[Daniel, Thomas]

> -Original Message-
> From: akash goel [mailto:akash.go...@gmail.com]
> Sent: Tuesday, October 27, 2015 11:52 AM
> To: Chris Wilson
> Cc: intel-gfx@lists.freedesktop.org; Goel, Akash; Daniel, Thomas
> Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915: Add soft-pinning API for
> execbuffer
> 
> On Tue, Oct 6, 2015 at 4:23 PM, Chris Wilson  wrote:
> > Userspace can pass in an offset that it presumes the object is located
> > at. The kernel will then do its utmost to fit the object into that
> > location. The assumption is that userspace is handling its own object
> > locations (for example along with full-ppgtt) and that the kernel will
> > rarely have to make space for the user's requests.
> >
> > v2: Fix i915_gem_evict_range() (now evict_for_vma) to handle ordinary
> > and fixed objects within the same batch
> >
> > Signed-off-by: Chris Wilson 
> > Cc: "Daniel, Thomas" 
> > ---
> >  drivers/gpu/drm/i915/i915_dma.c|  3 ++
> >  drivers/gpu/drm/i915/i915_drv.h| 10 +++--
> >  drivers/gpu/drm/i915/i915_gem.c| 68 
> > +
> -
> >  drivers/gpu/drm/i915/i915_gem_evict.c  | 61
> +++
> >  drivers/gpu/drm/i915/i915_gem_execbuffer.c |  9 +++-
> >  drivers/gpu/drm/i915/i915_trace.h  | 23 ++
> >  include/uapi/drm/i915_drm.h|  4 +-
> >  7 files changed, 151 insertions(+), 27 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_dma.c
> b/drivers/gpu/drm/i915/i915_dma.c
> > index ab37d1121be8..cd79ef114b8e 100644
> > --- a/drivers/gpu/drm/i915/i915_dma.c
> > +++ b/drivers/gpu/drm/i915/i915_dma.c
> > @@ -170,6 +170,9 @@ static int i915_getparam(struct drm_device *dev, void
> *data,
> > case I915_PARAM_HAS_RESOURCE_STREAMER:
> > value = HAS_RESOURCE_STREAMER(dev);
> > break;
> > +   case I915_PARAM_HAS_EXEC_SOFTPIN:
> > +   value = 1;
> > +   break;
> > default:
> > DRM_DEBUG("Unknown parameter %d\n", param->param);
> > return -EINVAL;
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> > index a0ce011a5dc0..7d351d991022 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2778,10 +2778,11 @@ void i915_gem_vma_destroy(struct i915_vma
> *vma);
> >  #define PIN_NONBLOCK   (1<<1)
> >  #define PIN_GLOBAL (1<<2)
> >  #define PIN_OFFSET_BIAS(1<<3)
> > -#define PIN_USER   (1<<4)
> > -#define PIN_UPDATE (1<<5)
> > -#define PIN_ZONE_4G(1<<6)
> > -#define PIN_HIGH   (1<<7)
> > +#define PIN_OFFSET_FIXED (1<<4)
> > +#define PIN_USER   (1<<5)
> > +#define PIN_UPDATE (1<<6)
> > +#define PIN_ZONE_4G(1<<7)
> > +#define PIN_HIGH   (1<<8)
> >  #define PIN_OFFSET_MASK (~4095)
> >  int __must_check
> >  i915_gem_object_pin(struct drm_i915_gem_object *obj,
> > @@ -3127,6 +3128,7 @@ int __must_check
> i915_gem_evict_something(struct drm_device *dev,
> >   unsigned long start,
> >   unsigned long end,
> >   unsigned flags);
> > +int __must_check i915_gem_evict_for_vma(struct i915_vma *vma, unsigned
> flags);
> >  int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
> >
> >  /* belongs in i915_gem_gtt.h */
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c
> b/drivers/gpu/drm/i915/i915_gem.c
> > index 8fe3df0cdcb8..82efd6a6dee0 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -3334,7 +3334,6 @@ i915_gem_object_bind_to_vm(struct
> drm_i915_gem_object *obj,
> > struct drm_device *dev = obj->base.dev;
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > u64 start, end;
> > -   u32 search_flag, alloc_flag;
> > struct i915_vma *vma;
> > int ret;
> >
> > @@ -3409,30 +3408,53 @@ i915_gem_object_bind_to_vm(struct
> drm_i915_gem_object *obj,
> > if (IS_ERR(vma))
> > goto err_unpin;
> >
> > -   if (flags & PIN_HIGH) {
> > -   search_flag = DRM_MM_SEARCH_BELOW;
> > -   alloc_flag = DRM_MM_CREATE_TOP;
> > +   if (flags & PIN_OFFSET_FIXED) {
> > +   uint64_t offset = flags & PIN_OFFSET_MASK;
> > +   if (offset & (alignment - 1) || offset + size > end) {
> > +   vma = ERR_PTR(-EINVAL);
This causes a crash, since the err_free_vma path will get an invalid address in 
vma.
Should be ret = -EINVAL; goto err_free_vma;

> > +   goto err_free_vma;
> > +   }
> > +   vma->node.start = offset;
> > +   vma->node.size = size;
> > +   vma->node.color = obj->cache_level;
> > +   ret = drm_mm_reserve_node(>mm, >node);
> > +   

Re: [Intel-gfx] [PATCH 17/29] drm/i915: Make the high dword offset more explicit in i915_reg_read_ioctl

[Chris Wilson]

On Wed, Nov 04, 2015 at 11:20:05PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> Store the upper dword of the register offset in the whitelist as well.
> This would allow it to read register where the two halves aren't sitting
> right next to each other, and it'll make it easier to make register
> access type safe.
> 
> While at it change the register offsets to u32 from u64. Our register
> space isn't quite that big, yet :)
> 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/i915_reg.h |  1 +
>  drivers/gpu/drm/i915/intel_uncore.c | 10 ++
>  2 files changed, 7 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0510ca1..7cea51d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1567,6 +1567,7 @@ enum skl_disp_power_wells {
>  #define RING_IMR(base)   ((base)+0xa8)
>  #define RING_HWSTAM(base)((base)+0x98)
>  #define RING_TIMESTAMP(base) ((base)+0x358)
> +#define RING_TIMESTAMP_HI(base)  ((base)+0x358 + 4)
>  #define   TAIL_ADDR  0x0018
>  #define   HEAD_WRAP_COUNT0xFFE0
>  #define   HEAD_WRAP_ONE  0x0020
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
> b/drivers/gpu/drm/i915/intel_uncore.c
> index f0f97b2..ced494a 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1261,12 +1261,13 @@ void intel_uncore_fini(struct drm_device *dev)
>  #define GEN_RANGE(l, h) GENMASK(h, l)
>  
>  static const struct register_whitelist {
> - uint64_t offset;
> + uint32_t offset, offset_hi;

Hmm, fwiw I was confused here thinking that you were storing a 64bit
value split across the two u32. (I know that's silly but it has been
common enough in the past.) Maybe offset_ldw and offset_udw?

I'm not sure though if this is something that we are going to be reading
enough that taking an extra few seconds to trace usage of
offset/offset_hi is going to matter much.

Reviewed-by: Chris Wilson 

We should probably also document that when passing a reg_read for a u64
register (that may or may not be split depending on gen) we always
specify the offset of the lower 32bits.
-Chris

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Re: [Intel-gfx] [PATCH 20/29] drm/i915: Add wa_ctx_emit_reg()

[Chris Wilson]

On Wed, Nov 04, 2015 at 11:20:08PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> Add a helper for emitting register offsets (for LRI/SRM) into the w/a
> batch buffer.
> 
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Chris Wilson 
-Chris

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Re: [Intel-gfx] [PATCH 11/29] drm/i915: Store DVO SRCDIM register offset under intel_dvo_device

[Chris Wilson]

On Wed, Nov 04, 2015 at 11:19:59PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> Store the DVO SRCDIM register offset alongside the DVO control register
> offset in intel_dvo_device. This gets rid of the switch statement whose
> case values are the DVO control register offsets. Such a construct would
> cause problems for register type safety.
> 
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Chris Wilson 

> @@ -255,20 +262,8 @@ static void intel_dvo_pre_enable(struct intel_encoder 
> *encoder)
>   struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
>   int pipe = crtc->pipe;
>   u32 dvo_val;
> - u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg;
> -
> - switch (dvo_reg) {
> - case DVOA:
> - default:
> - dvo_srcdim_reg = DVOA_SRCDIM;
> - break;
> - case DVOB:
> - dvo_srcdim_reg = DVOB_SRCDIM;
> - break;
> - case DVOC:
> - dvo_srcdim_reg = DVOC_SRCDIM;
> - break;
> - }
> + u32 dvo_reg = intel_dvo->dev.dvo_reg;
> + u32 dvo_srcdim_reg = intel_dvo->dev.dvo_srcdim_reg;

It doesn't look like we get much advantage here from the locals now.
Or perhaps struct intel_dvo_device *info = _dvo->dev;

then

val = I915_READ(info->dvo_reg);

I915_WRITE(info->dvo_srcdim_reg, foo);
I915_WRITE(info->dvo_reg, val);
-Chris

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Re: [Intel-gfx] [PATCH 16/29] drm/i915: s/0x50/RING_PSMI_CTL/

[Chris Wilson]

On Wed, Nov 04, 2015 at 11:20:04PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> Use the RING_PSMI_CTL define insted of hand rolling the register offset.
> 
> Signed-off-by: Ville Syrjälä 
Reviewed-by: Chris Wilson 
-Chris

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Re: [Intel-gfx] [v3] drm/i915/skl: While sanitizing cdclock check the SWF18 as well

[Ville Syrjälä]

On Thu, Nov 05, 2015 at 03:05:58PM +0530, Shobhit Kumar wrote:
> SWF18 is set if the display has been intialized by the pre-os. It also
> gives what configuration is enabled on which pipe. In skl_sanitize_cdclk,
> the DPLL sanity check can pass even if GOP/VBIOS is not loaded as BIOS
> enables DPLL for integrated audio codec related programming.
> So fisrt check if SWF18 is set and then follow through with other DPLL
> and CDCLK verification. If not set then for sure we need to sanitize the
> cdclock.
> 
> v2: Update the commit message for clarity (Siva)
> v3: Correct the mask to check for bits[23:0] instead of only bits[16:0].
> Had missed checking for PIPE C altogether. Remaining are reserved (Siva)
> 
> Cc: Ville Syrjälä 
> Signed-off-by: Shobhit Kumar 
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 3 +++
>  drivers/gpu/drm/i915/intel_display.c | 8 
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9ee9481..bd476ff 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5006,6 +5006,9 @@ enum skl_disp_power_wells {
>  #define SWF1(i)  (dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
>  #define SWF3(i)  (dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
>  
> +/* VBIOS flag for display initialized status */
> +#define GEN6_SWF18  (dev_priv->info.display_mmio_offset + 0x4F060)

Could you steal the ILK_SWF() register define from my patch at?
http://lists.freedesktop.org/archives/intel-gfx/2015-November/079480.html
Would avoid a bit of churn at least.

Otherwise this seems reasonable enough to me.

> +
>  /* Pipe B */
>  #define _PIPEBDSL(dev_priv->info.display_mmio_offset + 0x71000)
>  #define _PIPEBCONF   (dev_priv->info.display_mmio_offset + 0x71008)
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 103cacb..81668b0 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5761,6 +5761,14 @@ int skl_sanitize_cdclk(struct drm_i915_private 
> *dev_priv)
>   uint32_t cdctl = I915_READ(CDCLK_CTL);
>   int freq = dev_priv->skl_boot_cdclk;
>  
> + /*
> +  * check if the pre-os intialized the display
> +  * There is SWF18 scratchpad register defined which is set by the
> +  * pre-os which can be used by the OS drivers to check the status
> +  */
> + if ((I915_READ(GEN6_SWF18) & 0x00FF) == 0)
> + goto sanitize;
> +
>   /* Is PLL enabled and locked ? */
>   if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
>   goto sanitize;
> -- 
> 2.4.3

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Re: [Intel-gfx] [PATCH 14/29] drm/i915: Parametrize L3 error registers

[Chris Wilson]

On Wed, Nov 04, 2015 at 11:20:02PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> Signed-off-by: Ville Syrjälä 
Reviewed-by: Chris Wilson 
-Chris

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[Intel-gfx] [PATCH v2 15/29] drm/i915: Parametrize MOCS registers

[ville . syrjala]

From: Ville Syrjälä 

v2: Use for_each_ring() (Chris)

Cc: Chris Wilson 
Cc: Francisco Jerez 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h   | 12 
 drivers/gpu/drm/i915/intel_mocs.c | 59 ++-
 2 files changed, 40 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0b017bd..0510ca1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8141,12 +8141,12 @@ enum skl_disp_power_wells {
 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
 
 /* MOCS (Memory Object Control State) registers */
-#define GEN9_LNCFCMOCS00xb020  /* L3 Cache Control base */
+#define GEN9_LNCFCMOCS(i)  (0xb020 + (i) * 4)  /* L3 Cache Control */
 
-#define GEN9_GFX_MOCS_00xc800  /* Graphics MOCS base register*/
-#define GEN9_MFX0_MOCS_0   0xc900  /* Media 0 MOCS base register*/
-#define GEN9_MFX1_MOCS_0   0xca00  /* Media 1 MOCS base register*/
-#define GEN9_VEBOX_MOCS_0  0xcb00  /* Video MOCS base register*/
-#define GEN9_BLT_MOCS_00xcc00  /* Blitter MOCS base register*/
+#define GEN9_GFX_MOCS(i)   (0xc800 + (i) * 4)  /* Graphics MOCS 
registers */
+#define GEN9_MFX0_MOCS(i)  (0xc900 + (i) * 4)  /* Media 0 MOCS 
registers */
+#define GEN9_MFX1_MOCS(i)  (0xca00 + (i) * 4)  /* Media 1 MOCS 
registers */
+#define GEN9_VEBOX_MOCS(i) (0xcb00 + (i) * 4)  /* Video MOCS registers 
*/
+#define GEN9_BLT_MOCS(i)   (0xcc00 + (i) * 4)  /* Blitter MOCS 
registers */
 
 #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_mocs.c 
b/drivers/gpu/drm/i915/intel_mocs.c
index b258a2a..d546319 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -159,11 +159,30 @@ static bool get_mocs_settings(struct drm_device *dev,
return result;
 }
 
+static uint32_t mocs_register(enum intel_ring_id ring, int index)
+{
+   switch (ring) {
+   case RCS:
+   return GEN9_GFX_MOCS(index);
+   case VCS:
+   return GEN9_MFX0_MOCS(index);
+   case BCS:
+   return GEN9_BLT_MOCS(index);
+   case VECS:
+   return GEN9_VEBOX_MOCS(index);
+   case VCS2:
+   return GEN9_MFX1_MOCS(index);
+   default:
+   MISSING_CASE(ring);
+   return 0;
+   }
+}
+
 /**
  * emit_mocs_control_table() - emit the mocs control table
  * @req:   Request to set up the MOCS table for.
  * @table: The values to program into the control regs.
- * @reg_base:  The base for the engine that needs to be programmed.
+ * @ring:  The engine for whom to emit the registers.
  *
  * This function simply emits a MI_LOAD_REGISTER_IMM command for the
  * given table starting at the given address.
@@ -172,7 +191,7 @@ static bool get_mocs_settings(struct drm_device *dev,
  */
 static int emit_mocs_control_table(struct drm_i915_gem_request *req,
   const struct drm_i915_mocs_table *table,
-  u32 reg_base)
+  enum intel_ring_id ring)
 {
struct intel_ringbuffer *ringbuf = req->ringbuf;
unsigned int index;
@@ -191,7 +210,7 @@ static int emit_mocs_control_table(struct 
drm_i915_gem_request *req,
MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
 
for (index = 0; index < table->size; index++) {
-   intel_logical_ring_emit(ringbuf, reg_base + index * 4);
+   intel_logical_ring_emit(ringbuf, mocs_register(ring, index));
intel_logical_ring_emit(ringbuf,
table->table[index].control_value);
}
@@ -205,7 +224,7 @@ static int emit_mocs_control_table(struct 
drm_i915_gem_request *req,
 * that value to all the used entries.
 */
for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
-   intel_logical_ring_emit(ringbuf, reg_base + index * 4);
+   intel_logical_ring_emit(ringbuf, mocs_register(ring, index));
intel_logical_ring_emit(ringbuf, table->table[0].control_value);
}
 
@@ -253,7 +272,7 @@ static int emit_mocs_l3cc_table(struct drm_i915_gem_request 
*req,
value = (table->table[count].l3cc_value & 0x) |
((table->table[count + 1].l3cc_value & 0x) << 16);
 
-   intel_logical_ring_emit(ringbuf, GEN9_LNCFCMOCS0 + i * 4);
+   intel_logical_ring_emit(ringbuf, GEN9_LNCFCMOCS(i));
intel_logical_ring_emit(ringbuf, value);
}
 
@@ -270,7 +289,7 @@ static int emit_mocs_l3cc_table(struct drm_i915_gem_request 
*req,
 * they are reserved by the hardware.
 */
for (; i < 

[Intel-gfx] [PATCH 2/3] drm/i915: Introduce i915_gem_object_get_dma_address()

[ankitprasad . r . sharma]

From: Chris Wilson 

This utility function is a companion to i915_gem_object_get_page() that
uses the same cached iterator for the scatterlist to perform fast
sequential lookup of the dma address associated with any page within the
object.

Signed-off-by: Chris Wilson 
Signed-off-by: Ankitprasad Sharma 
---
 drivers/gpu/drm/i915/i915_drv.h | 17 +
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2b5d587..4baf252 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2854,6 +2854,23 @@ static inline int __sg_page_count(struct scatterlist *sg)
return sg->length >> PAGE_SHIFT;
 }
 
+static inline dma_addr_t
+i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, int n)
+{
+   if (n < obj->get_page.last) {
+   obj->get_page.sg = obj->pages->sgl;
+   obj->get_page.last = 0;
+   }
+
+   while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
+   obj->get_page.last += __sg_page_count(obj->get_page.sg++);
+   if (unlikely(sg_is_chain(obj->get_page.sg)))
+   obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
+   }
+
+   return sg_dma_address(obj->get_page.sg) + ((n - obj->get_page.last) << 
PAGE_SHIFT);
+}
+
 static inline struct page *
 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
 {
-- 
1.9.1

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[Intel-gfx] [PATCH 1/3] drm/i915: Add support for mapping an object page by page

[ankitprasad . r . sharma]

From: Chris Wilson 

Introduced a new vm specfic callback insert_page() to program a single pte in
ggtt or ppgtt. This allows us to map a single page in to the mappable aperture
space. This can be iterated over to access the whole object by using space as
meagre as page size.

Signed-off-by: Chris Wilson 
Signed-off-by: Ankitprasad Sharma 
---
 drivers/char/agp/intel-gtt.c|  9 +++
 drivers/gpu/drm/i915/i915_gem_gtt.c | 49 +
 drivers/gpu/drm/i915/i915_gem_gtt.h |  5 
 include/drm/intel-gtt.h |  3 +++
 4 files changed, 66 insertions(+)

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 1341a94..7c68576 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -838,6 +838,15 @@ static bool i830_check_flags(unsigned int flags)
return false;
 }
 
+void intel_gtt_insert_page(dma_addr_t addr,
+  unsigned int pg,
+  unsigned int flags)
+{
+   intel_private.driver->write_entry(addr, pg, flags);
+   wmb();
+}
+EXPORT_SYMBOL(intel_gtt_insert_page);
+
 void intel_gtt_insert_sg_entries(struct sg_table *st,
 unsigned int pg_start,
 unsigned int flags)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 47344d0..f374360 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2340,6 +2340,23 @@ static void gen8_set_pte(void __iomem *addr, gen8_pte_t 
pte)
 #endif
 }
 
+static void gen8_ggtt_insert_page(struct i915_address_space *vm,
+ dma_addr_t addr,
+ uint64_t offset,
+ enum i915_cache_level level,
+ u32 unused)
+{
+   struct drm_i915_private *dev_priv = to_i915(vm->dev);
+   gen8_pte_t __iomem *pte =
+   (gen8_pte_t __iomem *)dev_priv->gtt.gsm +
+   (offset >> PAGE_SHIFT);
+
+   gen8_set_pte(pte, gen8_pte_encode(addr, level, true));
+   wmb();
+
+   I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
+}
+
 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
 struct sg_table *st,
 uint64_t start,
@@ -2380,6 +2397,23 @@ static void gen8_ggtt_insert_entries(struct 
i915_address_space *vm,
POSTING_READ(GFX_FLSH_CNTL_GEN6);
 }
 
+static void gen6_ggtt_insert_page(struct i915_address_space *vm,
+ dma_addr_t addr,
+ uint64_t offset,
+ enum i915_cache_level level,
+ u32 flags)
+{
+   struct drm_i915_private *dev_priv = to_i915(vm->dev);
+   gen6_pte_t __iomem *pte =
+   (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
+   (offset >> PAGE_SHIFT);
+
+   iowrite32(vm->pte_encode(addr, level, true, flags), pte);
+   wmb();
+
+   I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
+}
+
 /*
  * Binds an object into the global gtt with the specified cache level. The 
object
  * will be accessible to the GPU via commands whose operands reference offsets
@@ -2476,6 +2510,18 @@ static void gen6_ggtt_clear_range(struct 
i915_address_space *vm,
readl(gtt_base);
 }
 
+static void i915_ggtt_insert_page(struct i915_address_space *vm,
+ dma_addr_t addr,
+ uint64_t offset,
+ enum i915_cache_level cache_level,
+ u32 unused)
+{
+   unsigned int flags = (cache_level == I915_CACHE_NONE) ?
+   AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
+
+   intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
+}
+
 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
 struct sg_table *pages,
 uint64_t start,
@@ -2969,6 +3015,7 @@ static int gen8_gmch_probe(struct drm_device *dev,
ret = ggtt_probe_common(dev, gtt_size);
 
dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
+   dev_priv->gtt.base.insert_page = gen8_ggtt_insert_page;
dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
@@ -3011,6 +3058,7 @@ static int gen6_gmch_probe(struct drm_device *dev,
ret = ggtt_probe_common(dev, gtt_size);
 
dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
+   dev_priv->gtt.base.insert_page = gen6_ggtt_insert_page;
dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
   

[Intel-gfx] [PATCH 0/3] Support for mapping an object page by page

[ankitprasad . r . sharma]

From: Ankitprasad Sharma 

It is possible that when we want to map an object to the aperture, either
we run out of aperture space or the size of the object is larger than
the mappable aperture. In such cases we might not be able to map the whole
object to the aperture. For cases as such, here we introduce insert_page()
which allows us to map a single page in to the mappable aperture space
(which has a higher probabilty of succeeding). This can be iterated
over to access the whole object by using space as meagre as page size.

Here we try to use insert_page() for pwrite_fast in case a nonblocking
pin for the whole object fails, which helps us to iterate over the whole
object and perform the pwrite without mapping the whole object to the
mappable aperture.

We also introduce i915_gem_object_get_dma_address() to perform fast
sequential lookup of the dma address associated with any page within the
object.

Ankitprasad Sharma (1):
  drm/i915: Use insert_page for pwrite_fast

Chris Wilson (2):
  drm/i915: Add support for mapping an object page by page
  drm/i915: Introduce i915_gem_object_get_dma_address()

 drivers/char/agp/intel-gtt.c|  9 
 drivers/gpu/drm/i915/i915_drv.h | 17 +++
 drivers/gpu/drm/i915/i915_gem.c | 92 +++--
 drivers/gpu/drm/i915/i915_gem_gtt.c | 49 
 drivers/gpu/drm/i915/i915_gem_gtt.h |  5 ++
 include/drm/intel-gtt.h |  3 ++
 6 files changed, 152 insertions(+), 23 deletions(-)

-- 
1.9.1

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[Intel-gfx] [PATCH] drm: Add aux plane verification in addFB2

[Vandana Kannan]

From: Daniel Vetter 

For render compression, userspace passes aux stride and offset values as an
additional entry in the fb structure. This should not be treated as garbage
and discarded as data belonging to no plane.
This patch introduces a check related to AUX plane to support the
scenario of render compression.

v2: Based on a discussion with Siva
Moving num_planes check below the increment.

Changing the author to Daniel instead of suggested-by, since the core logic is
his.

Signed-off-by: Daniel Vetter 
Signed-off-by: Vandana Kannan 
Cc: Sivakumar Thulasimani 
---
 drivers/gpu/drm/drm_crtc.c  | 19 ++-
 drivers/gpu/drm/drm_ioctl.c |  3 +++
 include/drm/drm_crtc.h  |  3 +++
 include/uapi/drm/drm.h  |  1 +
 include/uapi/drm/drm_mode.h |  1 +
 5 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 24c5434..0d1030b 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -3204,6 +3204,16 @@ static int framebuffer_check(const struct 
drm_mode_fb_cmd2 *r)
}
}
 
+   if (r->flags & DRM_MODE_FB_AUX_PLANE) {
+   num_planes++;
+
+   if (num_planes == 4) {
+   DRM_DEBUG_KMS("Number of planes cannot exceed 3"
+   "(including aux plane)\n");
+   return -EINVAL;
+   }
+   }
+
for (i = num_planes; i < 4; i++) {
if (r->modifier[i]) {
DRM_DEBUG_KMS("non-zero modifier for unused plane 
%d\n", i);
@@ -3242,7 +3252,8 @@ internal_framebuffer_create(struct drm_device *dev,
struct drm_framebuffer *fb;
int ret;
 
-   if (r->flags & ~(DRM_MODE_FB_INTERLACED | DRM_MODE_FB_MODIFIERS)) {
+   if (r->flags & ~(DRM_MODE_FB_INTERLACED | DRM_MODE_FB_MODIFIERS |
+   DRM_MODE_FB_AUX_PLANE)) {
DRM_DEBUG_KMS("bad framebuffer flags 0x%08x\n", r->flags);
return ERR_PTR(-EINVAL);
}
@@ -3264,6 +3275,12 @@ internal_framebuffer_create(struct drm_device *dev,
return ERR_PTR(-EINVAL);
}
 
+   if (r->flags & DRM_MODE_FB_AUX_PLANE &&
+   !dev->mode_config.allow_aux_plane) {
+   DRM_DEBUG_KMS("driver does not support render compression\n");
+   return ERR_PTR(-EINVAL);
+   }
+
ret = framebuffer_check(r);
if (ret)
return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 8ce2a0c..ee00782 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -312,6 +312,9 @@ static int drm_getcap(struct drm_device *dev, void *data, 
struct drm_file *file_
case DRM_CAP_ADDFB2_MODIFIERS:
req->value = dev->mode_config.allow_fb_modifiers;
break;
+   case DRM_CAP_RENDER_COMPRESSION:
+   req->value = dev->mode_config.allow_aux_plane;
+   break;
default:
return -EINVAL;
}
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 3f0c690..a5a9da2 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -1152,6 +1152,9 @@ struct drm_mode_config {
/* whether the driver supports fb modifiers */
bool allow_fb_modifiers;
 
+   /* whether the driver supports render compression */
+   bool allow_aux_plane;
+
/* cursor size */
uint32_t cursor_width, cursor_height;
 };
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index 3801584..0834bf7 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -631,6 +631,7 @@ struct drm_gem_open {
 #define DRM_CAP_CURSOR_WIDTH   0x8
 #define DRM_CAP_CURSOR_HEIGHT  0x9
 #define DRM_CAP_ADDFB2_MODIFIERS   0x10
+#define DRM_CAP_RENDER_COMPRESSION 0x11
 
 /** DRM_IOCTL_GET_CAP ioctl argument type */
 struct drm_get_cap {
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 6c11ca4..de59ace 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -354,6 +354,7 @@ struct drm_mode_fb_cmd {
 
 #define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
 #define DRM_MODE_FB_MODIFIERS  (1<<1) /* enables ->modifer[] */
+#define DRM_MODE_FB_AUX_PLANE   (1<<2) /* for compressed buffer */
 
 struct drm_mode_fb_cmd2 {
__u32 fb_id;
-- 
1.9.1

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Re: [Intel-gfx] [PATCH v2 02/14] drm/i915: Extend DSL readout fix to BDW and SKL.

[Jesse Barnes]

On 11/03/2015 04:44 AM, Maarten Lankhorst wrote:
> Hey,
> 
> Op 03-11-15 om 12:32 schreef Jani Nikula:
>> On Tue, 03 Nov 2015, Ville Syrjälä  wrote:
>>> On Tue, Nov 03, 2015 at 08:31:41AM +0100, Maarten Lankhorst wrote:
 Those platforms have the same bug as haswell, and the same fix applies to 
 them.
>> How about Broxton? IS_DDI matches that.
>>
>> Jani.
>>
> Judging from irc it's very likely it suffers from the same problem, but it 
> would be nice if we had someone who could confirm. :)

It won't hurt (much) if we apply this workaround and it doesn't affect
BXT, so I think we may as well apply given what we know of BXT's lineage.

Jesse

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Re: [Intel-gfx] [PATCH 4/8] drm/i915: Add a modeset power domain

[Patrik Jakobsson]

On Thu, Nov 5, 2015 at 4:02 PM, Daniel Stone  wrote:
> Hi,
>
> On 3 November 2015 at 12:31, Patrik Jakobsson
>  wrote:
>> We need DC5/DC6 to be disabled around modesets to prevent confusing the
>> DMC. Also, we've run out of bits in the 32 bit power domain mask so now
>> it's a 64 bit mask.
>
> There are quite a lot of users in intel_display.c (search for
> put_domains, display_power_put, put_power_domains) which need updating
> for the unsigned long long change.

Ah yes, we carry the mask around there as well. Thanks for catching
that. I like the move of POWER_DOMAIN_MODESET into put_domain as well.
I will resend the whole series again rebased on Imre's latest series.
Ok if I incorporate your changes directly?

Thanks
Patrik

>
> Cheers,
> Daniel
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[Intel-gfx] Fixing i915/opregion issues with firmware which lists more then 8 output devices

[Hans de Goede]

Hi,

As discussed in the past, the i915 opregion code does not do the
right thing wrt the CADL field when there are more then 8 outputs,
this is causing issues on many different types of Asus laptops.

This thread has details and a number of attempts to fix this:

https://lkml.org/lkml/2014/2/11/1032

This is impacting many users, here is an incomplete list of bug reports:

https://bugzilla.kernel.org/show_bug.cgi?id=70241
https://bugzilla.kernel.org/show_bug.cgi?id=88941
https://bugzilla.redhat.com/show_bug.cgi?id=1144866
https://bugzilla.redhat.com/show_bug.cgi?id=1277785

And I'm pretty sure that is just the tip of the iceberg, some users
have even analyzed their BIOS AML code and come up with an AML
hack in an attempt to fix this:

http://blog.yjwong.name/fixing-display-backlight-hotkeys-on-asus-n550jk/

It would be really great of someone from Intel could step up and start
working on a proper fix for this.

Regards,

Hans

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[Intel-gfx] [PATCH] drm/i915: Use extended power domain bitmask

[Daniel Stone]

c4111f0ac6 extended the size of the power-domain enum to 64 bits wide,
but there are still a few 'unsigned long' users inside intel_display.c.

Make these unsigned long long so we can also capture DRIVER_MODESET,
and use this to simplify the modeset power domain handling a little.

[daniels: New; only required when working against Patrik/Imre's tree.]

Signed-off-by: Daniel Stone 
---
 drivers/gpu/drm/i915/intel_display.c | 27 +--
 1 file changed, 13 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index dc31f33..9c3aa68 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5240,12 +5240,12 @@ static unsigned long get_crtc_power_domains(struct 
drm_crtc *crtc)
return mask;
 }
 
-static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
+static unsigned long long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
 {
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
enum intel_display_power_domain domain;
-   unsigned long domains, new_domains, old_domains;
+   unsigned long long domains, new_domains, old_domains;
 
old_domains = intel_crtc->enabled_power_domains;
intel_crtc->enabled_power_domains = new_domains = 
get_crtc_power_domains(crtc);
@@ -5259,7 +5259,7 @@ static unsigned long 
modeset_get_crtc_power_domains(struct drm_crtc *crtc)
 }
 
 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
- unsigned long domains)
+ unsigned long long domains)
 {
enum intel_display_power_domain domain;
 
@@ -5271,7 +5271,7 @@ static void modeset_update_crtc_power_domains(struct 
drm_atomic_state *state)
 {
struct drm_device *dev = state->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
-   unsigned long put_domains[I915_MAX_PIPES] = {};
+   unsigned long long put_domains[I915_MAX_PIPES] = {};
struct drm_crtc_state *crtc_state;
struct drm_crtc *crtc;
int i;
@@ -6250,7 +6250,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc 
*crtc)
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
enum intel_display_power_domain domain;
-   unsigned long domains;
+   unsigned long long domains;
 
if (!intel_crtc->active)
return;
@@ -13318,10 +13318,12 @@ static int intel_atomic_commit(struct drm_device *dev,
bool modeset = needs_modeset(crtc->state);
bool update_pipe = !modeset &&
to_intel_crtc_state(crtc->state)->update_pipe;
-   unsigned long put_domains = 0;
+   unsigned long long put_domains = 0;
 
-   if (modeset)
+   if (modeset) {
intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
+   put_domains |= POWER_DOMAIN_MODESET;
+   }
 
if (modeset && crtc->state->active) {
update_scanline_offset(to_intel_crtc(crtc));
@@ -13329,7 +13331,7 @@ static int intel_atomic_commit(struct drm_device *dev,
}
 
if (update_pipe) {
-   put_domains = modeset_get_crtc_power_domains(crtc);
+   put_domains |= modeset_get_crtc_power_domains(crtc);
 
/* make sure intel_modeset_check_state runs */
any_ms = true;
@@ -13342,13 +13344,10 @@ static int intel_atomic_commit(struct drm_device *dev,
(crtc->state->planes_changed || update_pipe))
drm_atomic_helper_commit_planes_on_crtc(crtc_state);
 
-   if (put_domains)
-   modeset_put_power_domains(dev_priv, put_domains);
-
intel_post_plane_update(intel_crtc);
 
-   if (modeset)
-   intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
+   if (put_domains)
+   modeset_put_power_domains(dev_priv, put_domains);
}
 
/* FIXME: add subpixel order */
@@ -15514,7 +15513,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
ilk_wm_get_hw_state(dev);
 
for_each_intel_crtc(dev, crtc) {
-   unsigned long put_domains;
+   unsigned long long put_domains;
 
put_domains = modeset_get_crtc_power_domains(>base);
if (WARN_ON(put_domains))
-- 
2.5.0

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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Add soft-pinning API for execbuffer

[Kristian Høgsberg]

On Tue, Oct 6, 2015 at 3:53 AM, Chris Wilson  wrote:
> Userspace can pass in an offset that it presumes the object is located
> at. The kernel will then do its utmost to fit the object into that
> location. The assumption is that userspace is handling its own object
> locations (for example along with full-ppgtt) and that the kernel will
> rarely have to make space for the user's requests.

I know the commit message isn't documentation, but the phrase "do its
utmost" makes me uncomfortable. I'd like to be explicit about what
might make it fail (should only be pinned fbs in case of aliased ppgtt
or userspace errors such as overlapping placements), or conversely,
spell out when the flag can be expected to work (full ppgtt).

Kristian

> v2: Fix i915_gem_evict_range() (now evict_for_vma) to handle ordinary
> and fixed objects within the same batch
>
> Signed-off-by: Chris Wilson 
> Cc: "Daniel, Thomas" 
> ---
>  drivers/gpu/drm/i915/i915_dma.c|  3 ++
>  drivers/gpu/drm/i915/i915_drv.h| 10 +++--
>  drivers/gpu/drm/i915/i915_gem.c| 68 
> +-
>  drivers/gpu/drm/i915/i915_gem_evict.c  | 61 +++
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c |  9 +++-
>  drivers/gpu/drm/i915/i915_trace.h  | 23 ++
>  include/uapi/drm/i915_drm.h|  4 +-
>  7 files changed, 151 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index ab37d1121be8..cd79ef114b8e 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -170,6 +170,9 @@ static int i915_getparam(struct drm_device *dev, void 
> *data,
> case I915_PARAM_HAS_RESOURCE_STREAMER:
> value = HAS_RESOURCE_STREAMER(dev);
> break;
> +   case I915_PARAM_HAS_EXEC_SOFTPIN:
> +   value = 1;
> +   break;
> default:
> DRM_DEBUG("Unknown parameter %d\n", param->param);
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a0ce011a5dc0..7d351d991022 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2778,10 +2778,11 @@ void i915_gem_vma_destroy(struct i915_vma *vma);
>  #define PIN_NONBLOCK   (1<<1)
>  #define PIN_GLOBAL (1<<2)
>  #define PIN_OFFSET_BIAS(1<<3)
> -#define PIN_USER   (1<<4)
> -#define PIN_UPDATE (1<<5)
> -#define PIN_ZONE_4G(1<<6)
> -#define PIN_HIGH   (1<<7)
> +#define PIN_OFFSET_FIXED (1<<4)
> +#define PIN_USER   (1<<5)
> +#define PIN_UPDATE (1<<6)
> +#define PIN_ZONE_4G(1<<7)
> +#define PIN_HIGH   (1<<8)
>  #define PIN_OFFSET_MASK (~4095)
>  int __must_check
>  i915_gem_object_pin(struct drm_i915_gem_object *obj,
> @@ -3127,6 +3128,7 @@ int __must_check i915_gem_evict_something(struct 
> drm_device *dev,
>   unsigned long start,
>   unsigned long end,
>   unsigned flags);
> +int __must_check i915_gem_evict_for_vma(struct i915_vma *vma, unsigned 
> flags);
>  int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
>
>  /* belongs in i915_gem_gtt.h */
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 8fe3df0cdcb8..82efd6a6dee0 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3334,7 +3334,6 @@ i915_gem_object_bind_to_vm(struct drm_i915_gem_object 
> *obj,
> struct drm_device *dev = obj->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> u64 start, end;
> -   u32 search_flag, alloc_flag;
> struct i915_vma *vma;
> int ret;
>
> @@ -3409,30 +3408,53 @@ i915_gem_object_bind_to_vm(struct drm_i915_gem_object 
> *obj,
> if (IS_ERR(vma))
> goto err_unpin;
>
> -   if (flags & PIN_HIGH) {
> -   search_flag = DRM_MM_SEARCH_BELOW;
> -   alloc_flag = DRM_MM_CREATE_TOP;
> +   if (flags & PIN_OFFSET_FIXED) {
> +   uint64_t offset = flags & PIN_OFFSET_MASK;
> +   if (offset & (alignment - 1) || offset + size > end) {
> +   vma = ERR_PTR(-EINVAL);
> +   goto err_free_vma;
> +   }
> +   vma->node.start = offset;
> +   vma->node.size = size;
> +   vma->node.color = obj->cache_level;
> +   ret = drm_mm_reserve_node(>mm, >node);
> +   if (ret) {
> +   ret = i915_gem_evict_for_vma(vma, flags);
> +   if (ret == 0)
> +   ret = drm_mm_reserve_node(>mm, 
> >node);
> +   }
> +   if (ret) {
> +   vma 

[Intel-gfx] [PATCH 05/31] drm/i915: Fix IPS initialization.

[Rodrigo Vivi]

With Fastboot by default we don't necessarily do a
full modeset enabling the primary plane.
So IPS enable call that was in that path wasn't being
called anymore.

So, let's relly on post atomic modeset path
and on ips_ready to enabled IPS when we judge necessary.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_display.c | 14 +-
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 2 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index e5c4056..b2c5c55 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4607,14 +4607,6 @@ intel_post_enable_primary(struct drm_crtc *crtc)
intel_wait_for_vblank(dev, pipe);
 
/*
-* FIXME IPS should be fine as long as one plane is
-* enabled, but in practice it seems to have problems
-* when going from primary only to sprite only and vice
-* versa.
-*/
-   intel_ips_enable(intel_crtc);
-
-   /*
 * Gen2 reports pipe underruns whenever all planes are disabled.
 * So don't enable underrun reporting before at least some planes
 * are enabled.
@@ -4700,6 +4692,9 @@ static void intel_post_plane_update(struct intel_crtc 
*crtc)
if (atomic->update_fbc)
intel_fbc_update(dev_priv);
 
+   if (atomic->enable_ips)
+   intel_ips_enable(crtc);
+
if (atomic->post_enable_primary)
intel_post_enable_primary(>base);
 
@@ -11578,7 +11573,8 @@ int intel_plane_atomic_calc_changes(struct 
drm_crtc_state *crtc_state,
 
intel_crtc->atomic.disable_fbc = true;
}
-
+   if (visible && intel_crtc->config->ips_ready)
+   intel_crtc->atomic.enable_ips = true;
/*
 * FBC does not work on some platforms for rotated
 * planes, so disable it when rotation is not 0 and
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index cc08566..92010f7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -538,6 +538,7 @@ struct intel_crtc_atomic_commit {
unsigned fb_bits;
bool wait_vblank;
bool update_fbc;
+   bool enable_ips;
bool post_enable_primary;
unsigned update_sprite_watermarks;
 };
-- 
2.4.3

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[Intel-gfx] [PATCH 31/31] drm/i915: Enable PSR by default.

[Rodrigo Vivi]

With a reliable frontbuffer tracking and all instability corner cases
solved let's re-enabled PSR by default on all supported platforms.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_params.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 368df67..ce20917 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -36,7 +36,7 @@ struct i915_params i915 __read_mostly = {
.enable_execlists = -1,
.enable_hangcheck = true,
.enable_ppgtt = -1,
-   .enable_psr = 0,
+   .enable_psr = 1,
.preliminary_hw_support = 
IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT),
.disable_power_well = 1,
.enable_ips = 1,
@@ -119,7 +119,7 @@ MODULE_PARM_DESC(enable_execlists,
"(-1=auto [default], 0=disabled, 1=enabled)");
 
 module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
-MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)");
+MODULE_PARM_DESC(enable_psr, "Enable PSR (default: true)");
 
 module_param_named_unsafe(preliminary_hw_support, i915.preliminary_hw_support, 
int, 0600);
 MODULE_PARM_DESC(preliminary_hw_support,
-- 
2.4.3

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[Intel-gfx] [PATCH 08/31] drm/i915: Add psr_ready on pipe_config

[Rodrigo Vivi]

Let's know beforehand if PSR is ready and will be enabled so we can
prevent DRRS to get enabled.

WARN_ON(!drm_modeset_is_locked(>mutex)) on intel_psr_ready()
has been removed on v3. We don't dereferrence crtc here anymore so
we don't need this check. All configs are now checked from received
pipe config.

v2: Removing is_edp_psr func that is not used after this patch.
Rename match_conditions and document it since it is now external.
Moving to a propper place as pointed out by Sivakumar.
Use a better name as pointed out by Ram.

v3: Don't dereferrence drm_encoder->crtc and intel_crtc->config on
psr_ready check. Fix a opps caused with previous versions.

v4: Mention and explain on commit message the crtc->mutex check
removal that happened on v3.

v5: Rebase on top of ips_ready rework.

Cc: Sivakumar Thulasimani 
Cc: Ramalingam C 
Cc: Chris Wilson 
Cc: Daniel Vetter 
Reviewed-by: Ramalingam C  (v2)
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_display.c |  1 +
 drivers/gpu/drm/i915/intel_dp.c  |  2 ++
 drivers/gpu/drm/i915/intel_drv.h |  3 ++
 drivers/gpu/drm/i915/intel_psr.c | 57 
 4 files changed, 38 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index a0e053e..869929d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11871,6 +11871,7 @@ static void intel_dump_pipe_config(struct intel_crtc 
*crtc,
  pipe_config->pch_pfit.size,
  pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
DRM_DEBUG_KMS("ips ready: %i\n", pipe_config->ips_ready);
+   DRM_DEBUG_KMS("psr ready: %i\n", pipe_config->psr_ready);
DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
 
if (IS_BROXTON(dev)) {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 273e1ad..e1c3e9a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1467,6 +1467,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 */
min_lane_count = max_lane_count;
min_clock = max_clock;
+
+   pipe_config->psr_ready = intel_psr_ready(intel_dp, pipe_config);
}
 
for (; bpp >= 6*3; bpp -= 2*3) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6f0b359..06511d2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -477,6 +477,7 @@ struct intel_crtc_state {
struct intel_link_m_n fdi_m_n;
 
bool ips_ready;
+   bool psr_ready;
 
bool double_wide;
 
@@ -1396,6 +1397,8 @@ void intel_backlight_unregister(struct drm_device *dev);
 
 
 /* intel_psr.c */
+bool intel_psr_ready(struct intel_dp *intel_dp,
+struct intel_crtc_state *pipe_config);
 void intel_psr_enable(struct intel_dp *intel_dp);
 void intel_psr_disable(struct intel_dp *intel_dp);
 void intel_psr_invalidate(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 213581c..4a9d620 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -56,11 +56,6 @@
 #include "intel_drv.h"
 #include "i915_drv.h"
 
-static bool is_edp_psr(struct intel_dp *intel_dp)
-{
-   return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
-}
-
 static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -287,19 +282,32 @@ static void hsw_psr_enable_source(struct intel_dp 
*intel_dp)
EDP_SU_TRACK_ENABLE | EDP_PSR2_TP2_TIME_100);
 }
 
-static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
+/**
+ * intel_psr_ready - PSR ready
+ * @intel_dp: Intel DP
+ * @pipe_config: Pipe Config
+ *
+ * This function Checks if PSR is supported by Hardware/Source and
+ * Panel/Sink and if all conditions to be enabled are fulfilled.
+ *
+ * It is used to know beforehand if PSR is going to be enabled.
+ *
+ * Returns:
+ * True when PSR is ready to be enabled, false otherwise.
+ */
+bool intel_psr_ready(struct intel_dp *intel_dp,
+struct intel_crtc_state *pipe_config)
 {
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
-   struct drm_crtc *crtc = dig_port->base.base.crtc;
-   struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 
-   lockdep_assert_held(_priv->psr.lock);
-   WARN_ON(!drm_modeset_is_locked(>mode_config.connection_mutex));
-   WARN_ON(!drm_modeset_is_locked(>mutex));
+   if 

[Intel-gfx] [PATCH 17/31] drm/i915: Add sys PSR toggle interface.

[Rodrigo Vivi]

This interface allows an immediate enabling of PSR feature.
What allow us to see immediately the PSR savings and will
allow us to expose this through powertop interface.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_sysfs.c | 82 +++
 drivers/gpu/drm/i915/intel_drv.h  |  4 +-
 drivers/gpu/drm/i915/intel_psr.c  | 19 +++--
 3 files changed, 99 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
b/drivers/gpu/drm/i915/i915_sysfs.c
index 2d092c1..0f371c6 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -111,6 +111,81 @@ static struct attribute_group ips_attr_group = {
.attrs =  ips_attrs
 };
 
+static ssize_t
+psr_show(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+   struct drm_minor *dminor = dev_to_drm_minor(kdev);
+   struct drm_device *dev = dminor->dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   ssize_t ret;
+
+   mutex_lock(_priv->psr.lock);
+   ret = snprintf(buf, PAGE_SIZE, "%s\n", dev_priv->psr.enabled ?
+  "enabled" : "disabled");
+   mutex_unlock(_priv->psr.lock);
+
+   return ret;
+}
+
+
+static ssize_t
+psr_toggle(struct device *kdev, struct device_attribute *attr,
+  const char *buf, size_t count)
+{
+   struct drm_minor *dminor = dev_to_drm_minor(kdev);
+   struct drm_device *dev = dminor->dev;
+   struct intel_connector *connector;
+   struct intel_encoder *encoder;
+   struct intel_crtc *crtc = NULL;
+   u32 val;
+   ssize_t ret;
+
+   ret = kstrtou32(buf, 0, );
+   if (ret)
+   return ret;
+
+   for_each_intel_connector(dev, connector) {
+   if (!connector->base.encoder)
+   continue;
+   encoder = to_intel_encoder(connector->base.encoder);
+   crtc = to_intel_crtc(encoder->base.crtc);
+   }
+
+   if (!crtc)
+   return -ENODEV;
+
+   switch (val) {
+   case 0:
+   ret = intel_psr_disable(crtc);
+   if (ret)
+   return ret;
+   break;
+   case 1:
+   ret = intel_psr_enable(crtc);
+   if (ret)
+   return ret;
+   break;
+   default:
+   return -EINVAL;
+   }
+
+   return count;
+
+
+}
+
+static DEVICE_ATTR(psr_enable, S_IRUGO | S_IWUSR, psr_show, psr_toggle);
+
+static struct attribute *psr_attrs[] = {
+   _attr_psr_enable.attr,
+   NULL
+};
+
+static struct attribute_group psr_attr_group = {
+   .name = power_group_name,
+   .attrs =  psr_attrs
+};
+
 static u32 calc_residency(struct drm_device *dev, const u32 reg)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -667,6 +742,12 @@ void i915_setup_sysfs(struct drm_device *dev)
if (ret)
DRM_ERROR("IPS sysfs setup failed\n");
}
+   if (HAS_PSR(dev)) {
+   ret = sysfs_merge_group(>primary->kdev->kobj,
+   _attr_group);
+   if (ret)
+   DRM_ERROR("PSR sysfs setup failed\n");
+   }
if (HAS_RC6(dev)) {
ret = sysfs_merge_group(>primary->kdev->kobj,
_attr_group);
@@ -724,6 +805,7 @@ void i915_teardown_sysfs(struct drm_device *dev)
device_remove_bin_file(dev->primary->kdev,  _attrs);
 #ifdef CONFIG_PM
sysfs_unmerge_group(>primary->kdev->kobj, _attr_group);
+   sysfs_unmerge_group(>primary->kdev->kobj, _attr_group);
sysfs_unmerge_group(>primary->kdev->kobj, _attr_group);
sysfs_unmerge_group(>primary->kdev->kobj, _attr_group);
 #endif
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index bf5e77c..76e0805 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1408,8 +1408,8 @@ void intel_backlight_unregister(struct drm_device *dev);
 /* intel_psr.c */
 bool intel_psr_ready(struct intel_dp *intel_dp,
 struct intel_crtc_state *pipe_config);
-void intel_psr_enable(struct intel_crtc *intel_crtc);
-void intel_psr_disable(struct intel_crtc *intel_crtc);
+int intel_psr_enable(struct intel_crtc *intel_crtc);
+int intel_psr_disable(struct intel_crtc *intel_crtc);
 void intel_psr_invalidate(struct drm_device *dev,
  unsigned frontbuffer_bits);
 void intel_psr_flush(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index bcf2d9d..4ca682a 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -374,21 +374,26 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
  * @intel_crtc: Intel CRTC
  *
  * This function can only be called after the pipe is fully trained and 
enabled.
+ *
+ 

[Intel-gfx] [PATCH 28/31] drm/i915: Make Sink crc calculation waiting for counter to reset.

[Rodrigo Vivi]

According to VESA DP spec TEST_CRC_COUNT (Bits 3:0) at
TEST_SINK_MISC (00246h) is "Reset to 0 when TEST_SINK bit 0 = 0;

So let's give few vblanks so we are really sure that this counter
is really zeroed on the next sink_crc read.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_dp.c | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c0fa90a..5d810cd 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3806,6 +3806,8 @@ static int intel_dp_sink_crc_stop(struct intel_dp 
*intel_dp)
struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
u8 buf;
int ret = 0;
+   int count = 0;
+   int attempts = 10;
 
if (drm_dp_dpcd_readb(_dp->aux, DP_TEST_SINK, ) < 0) {
DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
@@ -3820,7 +3822,22 @@ static int intel_dp_sink_crc_stop(struct intel_dp 
*intel_dp)
goto out;
}
 
-   intel_wait_for_vblank(dev, intel_crtc->pipe);
+   do {
+   intel_wait_for_vblank(dev, intel_crtc->pipe);
+
+   if (drm_dp_dpcd_readb(_dp->aux,
+ DP_TEST_SINK_MISC, ) < 0) {
+   ret = -EIO;
+   goto out;
+   }
+   count = buf & DP_TEST_COUNT_MASK;
+   } while (--attempts && count);
+
+   if (attempts == 0) {
+   DRM_ERROR("TIMEOUT: Sink CRC counter is not zeroed\n");
+   ret = -ETIMEDOUT;
+   }
+
intel_dp->sink_crc.started = false;
  out:
intel_ips_enable(intel_crtc);
-- 
2.4.3

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[Intel-gfx] [PATCH 12/31] drm/i915: Fix PSR initialization.

[Rodrigo Vivi]

PSR is still disabled by default, but even passing i915.enable_psr=1
at this point we weren't able to get PSR working because with
fastboot by default in place we weren't executing the path that enables
encoder and consequently PSR.

Now with psr_ready in place and PSR using crtc signature we can move
its enable/disable sequences from the encoder enable to the post
atomic modeset functions.

i915.enable_psr parameter is still used to enable/disable psr feature
on the next primary plane update. So current test cases that relies
on this flow still works.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_ddi.c |  2 --
 drivers/gpu/drm/i915/intel_display.c | 15 +++
 drivers/gpu/drm/i915/intel_dp.c  |  5 -
 drivers/gpu/drm/i915/intel_drv.h |  2 ++
 4 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index b8f8dee..36db970 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2404,7 +2404,6 @@ static void intel_enable_ddi(struct intel_encoder 
*intel_encoder)
intel_dp_stop_link_train(intel_dp);
 
intel_edp_backlight_on(intel_dp);
-   intel_psr_enable(intel_crtc);
intel_edp_drrs_enable(intel_dp);
}
 
@@ -2432,7 +2431,6 @@ static void intel_disable_ddi(struct intel_encoder 
*intel_encoder)
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
intel_edp_drrs_disable(intel_dp);
-   intel_psr_disable(intel_crtc);
intel_edp_backlight_off(intel_dp);
}
 }
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 869929d..f67e2ee 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4687,6 +4687,9 @@ static void intel_post_plane_update(struct intel_crtc 
*crtc)
if (atomic->enable_ips)
intel_ips_enable(crtc);
 
+   if (atomic->enable_psr)
+   intel_psr_enable(crtc);
+
if (atomic->post_enable_primary)
intel_post_enable_primary(>base);
 
@@ -4705,6 +4708,9 @@ static void intel_pre_plane_update(struct intel_crtc 
*crtc)
if (crtc->atomic.disable_ips)
intel_ips_disable_if_alone(crtc);
 
+   if (crtc->atomic.disable_psr)
+   intel_psr_disable(crtc);
+
if (atomic->pre_disable_primary)
intel_pre_disable_primary(>base);
 
@@ -11560,9 +11566,18 @@ int intel_plane_atomic_calc_changes(struct 
drm_crtc_state *crtc_state,
intel_crtc->atomic.disable_ips = true;
 
intel_crtc->atomic.disable_fbc = true;
+
+   intel_crtc->atomic.disable_psr = true;
}
if (visible && intel_crtc->config->ips_ready)
intel_crtc->atomic.enable_ips = true;
+
+   if (visible && intel_crtc->config->psr_ready) {
+   if (i915.enable_psr)
+   intel_crtc->atomic.enable_psr = true;
+   else
+   intel_crtc->atomic.disable_psr = true;
+   }
/*
 * FBC does not work on some platforms for rotated
 * planes, so disable it when rotation is not 0 and
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 92f59cc..f0ee497 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2373,9 +2373,6 @@ static void intel_disable_dp(struct intel_encoder 
*encoder)
if (crtc->config->has_audio)
intel_audio_codec_disable(encoder);
 
-   if (HAS_PSR(dev) && !HAS_DDI(dev))
-   intel_psr_disable(crtc);
-
/* Make sure the panel is off before trying to change the mode. But also
 * ensure that we have vdd while we switch off the panel. */
intel_edp_panel_vdd_on(intel_dp);
@@ -2629,10 +2626,8 @@ static void g4x_enable_dp(struct intel_encoder *encoder)
 static void vlv_enable_dp(struct intel_encoder *encoder)
 {
struct intel_dp *intel_dp = enc_to_intel_dp(>base);
-   struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 
intel_edp_backlight_on(intel_dp);
-   intel_psr_enable(crtc);
 }
 
 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index cafe4c1..d599d54 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -531,6 +531,7 @@ struct intel_crtc_atomic_commit {
/* Sleepable operations to perform before commit */
bool disable_fbc;
bool disable_ips;
+   bool disable_psr;
bool disable_cxsr;
bool pre_disable_primary;
bool update_wm_pre, update_wm_post;
@@ -540,6 

[Intel-gfx] [PATCH 22/31] drm/i915: Delay first PSR activation.

[Rodrigo Vivi]

When debuging the frozen screen caused by HW tracking with low
power state I noticed that if we keep moving the mouse non stop
you will miss the screen updates for a while. At least
until we stop moving the mouse for a small time and move again.

The actual enabling should happen immediately after
Display Port enabling sequence finished with links trained and
everything enabled. However we face many issues when enabling PSR
right after a modeset.

On VLV/CHV we face blank screens on this scenario and on HSW+
we face a recoverable frozen screen, at least until next
exit-activate sequence.

Another workaround for the same issue here would be to increase
re-enable idle time from 100 to 500 as we did for VLV/CHV.
However this patch workaround this issue in a better
way since it doesn't reduce PSR residency and also
allow us to reduce the delay time between re-enables at least
on VLV/CHV.

This is also important to make the sysfs toggle working properly.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_psr.c | 18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index da28f0c..6e7e8e6 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -448,6 +448,19 @@ int intel_psr_enable(struct intel_crtc *intel_crtc)
vlv_psr_enable_source(intel_dp);
}
 
+   /*
+* FIXME: Activation should happen immediately since this function
+* is just called after pipe is fully trained and enabled.
+* However on every platform we face issues when first activation
+* follows a modeset so quickly.
+* - On VLV/CHV we get bank screen on first activation
+* - On HSW/BDW we get a recoverable frozen screen until next
+*   exit-activate sequence.
+*/
+   if (INTEL_INFO(dev)->gen < 9)
+   schedule_delayed_work(_priv->psr.work,
+ 
msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
+
dev_priv->psr.enabled = intel_dp;
 unlock:
mutex_unlock(_priv->psr.lock);
@@ -744,8 +757,9 @@ void intel_psr_flush(struct drm_device *dev,
intel_psr_exit(dev);
 
if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
-   schedule_delayed_work(_priv->psr.work,
- msecs_to_jiffies(delay_ms));
+   if (!work_busy(_priv->psr.work.work))
+   schedule_delayed_work(_priv->psr.work,
+ msecs_to_jiffies(delay_ms));
mutex_unlock(_priv->psr.lock);
 }
 
-- 
2.4.3

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[Intel-gfx] [PATCH 16/31] drm/i915: Fix DRRS initialization.

[Rodrigo Vivi]

With Fastboot by default we don't necessarily do a
full modeset enabling the primary plane.
So DRRS enable call that was in that path wasn't being
called anymore.

So, let's relly on post atomic modeset path
and on has_drrs to enabled DRRS when we judge necessary.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_display.c | 11 +++
 drivers/gpu/drm/i915/intel_drv.h |  2 ++
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index f67e2ee..6647bfe 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4681,6 +4681,9 @@ static void intel_post_plane_update(struct intel_crtc 
*crtc)
if (crtc->atomic.update_wm_post)
intel_update_watermarks(>base);
 
+   if (atomic->enable_drrs)
+   intel_drrs_enable(crtc);
+
if (atomic->update_fbc)
intel_fbc_update(dev_priv);
 
@@ -4702,6 +4705,9 @@ static void intel_pre_plane_update(struct intel_crtc 
*crtc)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc_atomic_commit *atomic = >atomic;
 
+   if (crtc->atomic.disable_drrs)
+   intel_drrs_disable(crtc);
+
if (atomic->disable_fbc)
intel_fbc_disable_crtc(crtc);
 
@@ -11565,10 +11571,15 @@ int intel_plane_atomic_calc_changes(struct 
drm_crtc_state *crtc_state,
 */
intel_crtc->atomic.disable_ips = true;
 
+   intel_crtc->atomic.disable_drrs = true;
+
intel_crtc->atomic.disable_fbc = true;
 
intel_crtc->atomic.disable_psr = true;
}
+   if (visible && intel_crtc->config->has_drrs)
+   intel_crtc->atomic.enable_drrs = true;
+
if (visible && intel_crtc->config->ips_ready)
intel_crtc->atomic.enable_ips = true;
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 48f461f..bf5e77c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -529,6 +529,7 @@ struct intel_mmio_flip {
  */
 struct intel_crtc_atomic_commit {
/* Sleepable operations to perform before commit */
+   bool disable_drrs;
bool disable_fbc;
bool disable_ips;
bool disable_psr;
@@ -539,6 +540,7 @@ struct intel_crtc_atomic_commit {
/* Sleepable operations to perform after commit */
unsigned fb_bits;
bool wait_vblank;
+   bool enable_drrs;
bool update_fbc;
bool enable_ips;
bool enable_psr;
-- 
2.4.3

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[Intel-gfx] [PATCH 20/31] drm/i915: PSR: Let's rely more on frontbuffer tracking.

[Rodrigo Vivi]

Many reasons here:

- Hardware tracking also has hidden corner cases
- Frontbuffer tracking is mature and reliable now
- Our sw exit by unseting bit 31 is really fast and reliable.

Also frontbuffer tracking flush means invalidate and flush.

So, let's rely more and do the proper meaning of flush for
all cases without any workaround.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_psr.c | 22 +++---
 1 file changed, 3 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 8c9ba42..02d00d9 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -734,25 +734,9 @@ void intel_psr_flush(struct drm_device *dev,
frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
 
-   if (HAS_DDI(dev)) {
-   /*
-* By definition every flush should mean invalidate + flush,
-* however on core platforms let's minimize the
-* disable/re-enable so we can avoid the invalidate when flip
-* originated the flush.
-*/
-   if (frontbuffer_bits && origin != ORIGIN_FLIP)
-   intel_psr_exit(dev);
-   } else {
-   /*
-* On Valleyview and Cherryview we don't use hardware tracking
-* so any plane updates or cursor moves don't result in a PSR
-* invalidating. Which means we need to manually fake this in
-* software for all flushes.
-*/
-   if (frontbuffer_bits)
-   intel_psr_exit(dev);
-   }
+   /* By definition flush = invalidate + flush */
+   if (frontbuffer_bits)
+   intel_psr_exit(dev);
 
if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
schedule_delayed_work(_priv->psr.work,
-- 
2.4.3

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[Intel-gfx] [PATCH 21/31] drm/i915: PSR: Mask LPSP hw tracking back again.

[Rodrigo Vivi]

At the beginning it was masked to allow PSR at all.
Than it got removed later by my
commit 09108b90f040 ("drm/i915: PSR: Remove Low Power HW tracking mask.")
in order to trying fixing one case reported at intel-gfx mailing list
where we were missing screen updates when runtime_pm was enabled.

However I verified that other patch that makes flush to force
invalidate also fixes this issue by itself.
commit 169de1316c1e ("drm/i915: PSR: Flush means invalidate + flush")

Mainly now that we are relying more on frontbuffer tracking it is a
good idea to mask this hw tracking again.

But besides all this above it is important to hightligh that with LPSP
unmasked we started seeing some screen freezings as reported at fd.o.

v2: Update commit message since this patch by itself doesn't solve
the bugzilla entries.

Tested-by: Brian Norris 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_psr.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 02d00d9..da28f0c 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -419,9 +419,14 @@ int intel_psr_enable(struct intel_crtc *intel_crtc)
skl_psr_setup_su_vsc(intel_dp);
}
 
-   /* Avoid continuous PSR exit by masking memup and hpd */
+   /*
+* Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD.
+* Also mask LPSP to avoid dependency on other drivers that
+* might block runtime_pm besides preventing other hw tracking
+* issues now we can rely on frontbuffer tracking.
+*/
I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
-  EDP_PSR_DEBUG_MASK_HPD);
+  EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
 
/* Enable PSR on the panel */
hsw_psr_enable_sink(intel_dp);
-- 
2.4.3

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[Intel-gfx] [PATCH 06/31] drm/i915: Fix IPS disable sequence.

[Rodrigo Vivi]

We cannot let IPS enabled in the pipe if there is
no plane enabled so whenever disabling the primary
plane we check the state of other planes and disable
IPS if needed.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_display.c | 18 +++---
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_ips.c | 35 ++-
 3 files changed, 38 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index b2c5c55..a0e053e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4662,14 +4662,6 @@ intel_pre_disable_primary(struct drm_crtc *crtc)
dev_priv->wm.vlv.cxsr = false;
intel_wait_for_vblank(dev, pipe);
}
-
-   /*
-* FIXME IPS should be fine as long as one plane is
-* enabled, but in practice it seems to have problems
-* when going from primary only to sprite only and vice
-* versa.
-*/
-   intel_ips_disable(intel_crtc);
 }
 
 static void intel_post_plane_update(struct intel_crtc *crtc)
@@ -4711,7 +4703,7 @@ static void intel_pre_plane_update(struct intel_crtc 
*crtc)
intel_fbc_disable_crtc(crtc);
 
if (crtc->atomic.disable_ips)
-   intel_ips_disable(crtc);
+   intel_ips_disable_if_alone(crtc);
 
if (atomic->pre_disable_primary)
intel_pre_disable_primary(>base);
@@ -11562,12 +11554,8 @@ int intel_plane_atomic_calc_changes(struct 
drm_crtc_state *crtc_state,
 
if (turn_off) {
/*
-* FIXME: Actually if we will still have any other
-* plane enabled on the pipe we could let IPS enabled
-* still, but for now lets consider that when we make
-* primary invisible by setting DSPCNTR to 0 on
-* update_primary_plane function IPS needs to be
-* disable.
+* IPS disable_if_alone function will be called
+* in order to decide if IPS disable is really needed.
 */
intel_crtc->atomic.disable_ips = true;
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 92010f7..04c1fc4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1211,6 +1211,7 @@ bool intel_ips_ready(struct intel_crtc *crtc,
 struct intel_crtc_state *crtc_state);
 void intel_ips_enable(struct intel_crtc *crtc);
 void intel_ips_disable(struct intel_crtc *crtc);
+void intel_ips_disable_if_alone(struct intel_crtc *crtc);
 void intel_ips_init(struct drm_i915_private *dev_priv);
 
 /* intel_csr.c */
diff --git a/drivers/gpu/drm/i915/intel_ips.c b/drivers/gpu/drm/i915/intel_ips.c
index 1d0d8ff..b867aba 100644
--- a/drivers/gpu/drm/i915/intel_ips.c
+++ b/drivers/gpu/drm/i915/intel_ips.c
@@ -199,13 +199,46 @@ out:
 }
 
 /**
+ * intel_ips_disable_if_alone - Disable IPS if alone in the pipe.
+ * @crtc: intel crtc
+ *
+ * This function should be called when primary plane is being disabled.
+ * It checks if there is any other plane enabled on the pipe when primary is
+ * going to be disabled. In this case IPS can continue enabled, but it needs
+ * to be disabled otherwise.
+ */
+void intel_ips_disable_if_alone(struct intel_crtc *crtc)
+{
+   struct drm_device *dev = crtc->base.dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   bool ips_enabled;
+   struct intel_plane *intel_plane;
+
+   mutex_lock(_priv->display_ips.lock);
+   ips_enabled = dev_priv->display_ips.enabled;
+   mutex_unlock(_priv->display_ips.lock);
+
+   if (!ips_enabled)
+   return;
+
+   for_each_intel_plane_on_crtc(dev, crtc, intel_plane) {
+   enum plane plane = intel_plane->plane;
+
+   if (plane != PLANE_A &&
+   !!(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE))
+   return;
+   intel_ips_disable(crtc);
+   }
+}
+
+/**
  * intel_ips_init - Init IPS
  * @dev_priv: drm i915 private.
  *
  * This function should be called only once to initialize what ever needed
  * for IPS.
  */
-void intel_ips_init(struct drm_i915_private dev_priv)
+void intel_ips_init(struct drm_i915_private *dev_priv)
 {
mutex_init(_priv->display_ips.lock);
 }
-- 
2.4.3

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[Intel-gfx] [PATCH 18/31] drm/i915: Force PSR exit when IRQ_HPD is detected on eDP.

[Rodrigo Vivi]

According to VESA spec: "If a Source device receives and IRQ_HPD
while in a PSR active state, and cannot identify what caused the
IRQ_HPD to be generated, based on Sink device status registers,
the Source device can take implementation-specific action.
One such action can be to exit and then re-enter a PSR active
state."

Since we aren't checking for any sink status registers and we
 aren't looking for any other implementation-specific action,
in case we receive any IRQ_HPD and psr is active let's force
the exit and reschedule it back.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_dp.c  |  5 -
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_psr.c | 33 +
 3 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a421c17..4feb47e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4851,6 +4851,8 @@ intel_dp_hpd_pulse(struct intel_digital_port 
*intel_dig_port, bool long_hpd)
 
if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
+   else
+   intel_psr_irq_hpd(dev);
 
if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
/*
@@ -4859,8 +4861,9 @@ intel_dp_hpd_pulse(struct intel_digital_port 
*intel_dig_port, bool long_hpd)
 * would end up in an endless cycle of
 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
 */
-   DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
+   DRM_DEBUG_KMS("long hpd on eDP port %c\n",
  port_name(intel_dig_port->port));
+
return IRQ_HANDLED;
}
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 76e0805..baa560c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1418,6 +1418,7 @@ void intel_psr_flush(struct drm_device *dev,
 void intel_psr_init(struct drm_device *dev);
 void intel_psr_single_frame_update(struct drm_device *dev,
   unsigned frontbuffer_bits);
+void intel_psr_irq_hpd(struct drm_device *dev);
 
 /* intel_runtime_pm.c */
 int intel_power_domains_init(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 4ca682a..c49c6bd 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -764,6 +764,39 @@ void intel_psr_flush(struct drm_device *dev,
 }
 
 /**
+ * intel_psr_irq_hpd - Let PSR aware of IRQ_HPD
+ * @dev: DRM device
+ *
+ * This function is called when IRQ_HPD is received on eDP.
+ */
+void intel_psr_irq_hpd(struct drm_device *dev)
+{
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   int delay_ms = HAS_DDI(dev) ? 100 : 500;
+
+   mutex_lock(_priv->psr.lock);
+
+   /*
+* According to VESA spec "If a Source device receives and IRQ_HPD
+* while in a PSR active state, and cannot identify what caused the
+* IRQ_HPD to be generated, based on Sink device status registers,
+* the Source device can take implementation-specific action.
+* One such action can be to exit and then re-enter a PSR active
+* state." Since we aren't checking for any sink status registers
+* and we aren't looking for any other implementation-specific
+* action, in case we receive any IRQ_HPD and psr is active let's
+* force the exit and reschedule it back.
+*/
+   if (dev_priv->psr.active) {
+   intel_psr_exit(dev);
+   schedule_delayed_work(_priv->psr.work,
+ msecs_to_jiffies(delay_ms));
+   }
+
+   mutex_unlock(_priv->psr.lock);
+}
+
+/**
  * intel_psr_init - Init basic PSR work and mutex.
  * @dev: DRM device
  *
-- 
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[Intel-gfx] [PATCH 10/31] drm/i915: Detatch i915.enable_psr from psr_ready

[Rodrigo Vivi]

PSR will be enabled on every post primary update when it is
ready and parameter allows.
With this we allow test cases to continue using this parameter
for enabling disabling the feature.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_dp.c  | 2 +-
 drivers/gpu/drm/i915/intel_psr.c | 5 -
 2 files changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6ab127c..e154a2e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5334,7 +5334,7 @@ void intel_edp_drrs_enable(struct intel_dp *intel_dp)
return;
}
 
-   if (intel_crtc->config->psr_ready) {
+   if (intel_crtc->config->psr_ready && i915.enable_psr) {
DRM_DEBUG_KMS("DRRS: PSR will be enabled on this crtc\n");
return;
}
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 4a9d620..e690db3 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -314,11 +314,6 @@ bool intel_psr_ready(struct intel_dp *intel_dp,
return false;
}
 
-   if (!i915.enable_psr) {
-   DRM_DEBUG_KMS("PSR disable by flag\n");
-   return false;
-   }
-
if (IS_HASWELL(dev) &&
I915_READ(HSW_STEREO_3D_CTL(pipe_config->cpu_transcoder)) &
  S3D_ENABLE) {
-- 
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[Intel-gfx] [PATCH 27/31] drm/i915: Allow 1 vblank to let Sink CRC calculation to start or stop.

[Rodrigo Vivi]

According to VESA DP Spec, setting TEST_SINK_START (bit 0)
of TEST_SINK (00270h) "Stop/Start calculating CRC on the next frame"

So let's wait at least 1 vblank to really say the calculation
stopped or started.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_dp.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4feb47e..c0fa90a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3802,6 +3802,7 @@ intel_dp_probe_mst(struct intel_dp *intel_dp)
 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
 {
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+   struct drm_device *dev = dig_port->base.base.dev;
struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
u8 buf;
int ret = 0;
@@ -3819,6 +3820,7 @@ static int intel_dp_sink_crc_stop(struct intel_dp 
*intel_dp)
goto out;
}
 
+   intel_wait_for_vblank(dev, intel_crtc->pipe);
intel_dp->sink_crc.started = false;
  out:
intel_ips_enable(intel_crtc);
@@ -3828,6 +3830,7 @@ static int intel_dp_sink_crc_stop(struct intel_dp 
*intel_dp)
 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
 {
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+   struct drm_device *dev = dig_port->base.base.dev;
struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
u8 buf;
int ret;
@@ -3857,6 +3860,7 @@ static int intel_dp_sink_crc_start(struct intel_dp 
*intel_dp)
return -EIO;
}
 
+   intel_wait_for_vblank(dev, intel_crtc->pipe);
intel_dp->sink_crc.started = true;
return 0;
 }
-- 
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[Intel-gfx] [PATCH 07/31] drm/i915: IPS Sysfs interface.

[Rodrigo Vivi]

With the lock in place we can expose ips enabled/disable on sysfs
for developing, debugging and information purposes.

The main goal is to have an informative tab at powertop that expose
the current status of power features in our driver. So let's start
with this IPS one. Please remind that powertop has no access to drm
properties so sysfs will be used as it is currently used for RC6.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_sysfs.c | 83 +++
 drivers/gpu/drm/i915/intel_drv.h  |  4 +-
 drivers/gpu/drm/i915/intel_ips.c  | 25 +---
 3 files changed, 105 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
b/drivers/gpu/drm/i915/i915_sysfs.c
index 50ce9ce..2d092c1 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -35,6 +35,82 @@
 #define dev_to_drm_minor(d) dev_get_drvdata((d))
 
 #ifdef CONFIG_PM
+
+static ssize_t
+ips_show(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+   struct drm_minor *dminor = dev_to_drm_minor(kdev);
+   struct drm_device *dev = dminor->dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   ssize_t ret;
+
+   mutex_lock(_priv->display_ips.lock);
+   ret = snprintf(buf, PAGE_SIZE, "%s\n", dev_priv->display_ips.enabled ?
+  "enabled" : "disabled");
+   mutex_unlock(_priv->display_ips.lock);
+
+   return ret;
+}
+
+
+static ssize_t
+ips_toggle(struct device *kdev, struct device_attribute *attr,
+  const char *buf, size_t count)
+{
+   struct drm_minor *dminor = dev_to_drm_minor(kdev);
+   struct drm_device *dev = dminor->dev;
+   struct intel_connector *connector;
+   struct intel_encoder *encoder;
+   struct intel_crtc *crtc = NULL;
+   u32 val;
+   ssize_t ret;
+
+   ret = kstrtou32(buf, 0, );
+   if (ret)
+   return ret;
+
+   for_each_intel_connector(dev, connector) {
+   if (!connector->base.encoder)
+   continue;
+   encoder = to_intel_encoder(connector->base.encoder);
+   crtc = to_intel_crtc(encoder->base.crtc);
+   }
+
+   if (!crtc)
+   return -ENODEV;
+
+   switch (val) {
+   case 0:
+   ret = intel_ips_disable(crtc);
+   if (ret)
+   return ret;
+   break;
+   case 1:
+   ret = intel_ips_enable(crtc);
+   if (ret)
+   return ret;
+   break;
+   default:
+   return -EINVAL;
+   }
+
+   return count;
+
+
+}
+
+static DEVICE_ATTR(ips_enable, S_IRUGO | S_IWUSR, ips_show, ips_toggle);
+
+static struct attribute *ips_attrs[] = {
+   _attr_ips_enable.attr,
+   NULL
+};
+
+static struct attribute_group ips_attr_group = {
+   .name = power_group_name,
+   .attrs =  ips_attrs
+};
+
 static u32 calc_residency(struct drm_device *dev, const u32 reg)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -585,6 +661,12 @@ void i915_setup_sysfs(struct drm_device *dev)
int ret;
 
 #ifdef CONFIG_PM
+   if (HAS_IPS(dev)) {
+   ret = sysfs_merge_group(>primary->kdev->kobj,
+   _attr_group);
+   if (ret)
+   DRM_ERROR("IPS sysfs setup failed\n");
+   }
if (HAS_RC6(dev)) {
ret = sysfs_merge_group(>primary->kdev->kobj,
_attr_group);
@@ -641,6 +723,7 @@ void i915_teardown_sysfs(struct drm_device *dev)
device_remove_bin_file(dev->primary->kdev,  _attrs_1);
device_remove_bin_file(dev->primary->kdev,  _attrs);
 #ifdef CONFIG_PM
+   sysfs_unmerge_group(>primary->kdev->kobj, _attr_group);
sysfs_unmerge_group(>primary->kdev->kobj, _attr_group);
sysfs_unmerge_group(>primary->kdev->kobj, _attr_group);
 #endif
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 04c1fc4..6f0b359 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1209,8 +1209,8 @@ u32 skl_plane_ctl_rotation(unsigned int rotation);
 /* intel_ips.c */
 bool intel_ips_ready(struct intel_crtc *crtc,
 struct intel_crtc_state *crtc_state);
-void intel_ips_enable(struct intel_crtc *crtc);
-void intel_ips_disable(struct intel_crtc *crtc);
+int intel_ips_enable(struct intel_crtc *crtc);
+int intel_ips_disable(struct intel_crtc *crtc);
 void intel_ips_disable_if_alone(struct intel_crtc *crtc);
 void intel_ips_init(struct drm_i915_private *dev_priv);
 
diff --git a/drivers/gpu/drm/i915/intel_ips.c b/drivers/gpu/drm/i915/intel_ips.c
index b867aba..6bc5c55 100644
--- a/drivers/gpu/drm/i915/intel_ips.c
+++ b/drivers/gpu/drm/i915/intel_ips.c
@@ -105,18 +105,21 @@ bool intel_ips_ready(struct intel_crtc *crtc,
  * This function is called 

[Intel-gfx] [PATCH 30/31] drm/i915: Rely on TEST_SINK_START instead of tracking Sink CRC state on dev_priv.

[Rodrigo Vivi]

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_dp.c  | 14 ++
 drivers/gpu/drm/i915/intel_drv.h |  5 -
 2 files changed, 6 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 24d2bff..5e14f07 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3838,7 +3838,6 @@ static int intel_dp_sink_crc_stop(struct intel_dp 
*intel_dp)
ret = -ETIMEDOUT;
}
 
-   intel_dp->sink_crc.started = false;
  out:
intel_ips_enable(intel_crtc);
return ret;
@@ -3852,12 +3851,6 @@ static int intel_dp_sink_crc_start(struct intel_dp 
*intel_dp)
u8 buf;
int ret;
 
-   if (intel_dp->sink_crc.started) {
-   ret = intel_dp_sink_crc_stop(intel_dp);
-   if (ret)
-   return ret;
-   }
-
if (drm_dp_dpcd_readb(_dp->aux, DP_TEST_SINK_MISC, ) < 0)
return -EIO;
 
@@ -3867,6 +3860,12 @@ static int intel_dp_sink_crc_start(struct intel_dp 
*intel_dp)
if (drm_dp_dpcd_readb(_dp->aux, DP_TEST_SINK, ) < 0)
return -EIO;
 
+   if (buf & DP_TEST_SINK_START) {
+   ret = intel_dp_sink_crc_stop(intel_dp);
+   if (ret)
+   return ret;
+   }
+
intel_ips_disable(intel_crtc);
 
if (drm_dp_dpcd_writeb(_dp->aux, DP_TEST_SINK,
@@ -3876,7 +3875,6 @@ static int intel_dp_sink_crc_start(struct intel_dp 
*intel_dp)
}
 
intel_wait_for_vblank(dev, intel_crtc->pipe);
-   intel_dp->sink_crc.started = true;
return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index de2a8ff..c28f24a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -744,10 +744,6 @@ enum link_m_n_set {
M2_N2
 };
 
-struct sink_crc {
-   bool started;
-};
-
 struct intel_dp {
uint32_t output_reg;
uint32_t aux_ch_ctl_reg;
@@ -764,7 +760,6 @@ struct intel_dp {
/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
uint8_t num_sink_rates;
int sink_rates[DP_MAX_SUPPORTED_RATES];
-   struct sink_crc sink_crc;
struct drm_dp_aux aux;
uint8_t train_set[4];
int panel_power_up_delay;
-- 
2.4.3

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[Intel-gfx] [PATCH 01/31] drm/i915: Rename IPS ready variable at pipe config.

[Rodrigo Vivi]

This variable mostly doesn't reflect IPS enabled status
but its readiness.

This patch removes the only place where it was actually meaning ips
enabled, at crtc_load_lut workaround for Haswell only.
The actuall enabled will be properly implemented in a following patch.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_display.c | 19 +--
 drivers/gpu/drm/i915/intel_drv.h |  2 +-
 2 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 0811238..01da1c9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4534,7 +4534,7 @@ void hsw_enable_ips(struct intel_crtc *crtc)
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
 
-   if (!crtc->config->ips_enabled)
+   if (!crtc->config->ips_ready)
return;
 
/* We can only enable IPS after we enable a plane and wait for a vblank 
*/
@@ -4567,7 +4567,7 @@ void hsw_disable_ips(struct intel_crtc *crtc)
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
 
-   if (!crtc->config->ips_enabled)
+   if (!crtc->config->ips_ready)
return;
 
assert_plane_enabled(dev_priv, crtc->plane);
@@ -4611,7 +4611,8 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
/* Workaround : Do not read or write the pipe palette/gamma data while
 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
 */
-   if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
+   /* FIXME: This should be ips_enabled */
+   if (IS_HASWELL(dev) && intel_crtc->config->ips_ready &&
((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
 GAMMA_MODE_MODE_SPLIT)) {
hsw_disable_ips(intel_crtc);
@@ -6558,7 +6559,7 @@ static void hsw_compute_ips_config(struct intel_crtc 
*crtc,
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
 
-   pipe_config->ips_enabled = i915.enable_ips &&
+   pipe_config->ips_ready = i915.enable_ips &&
hsw_crtc_supports_ips(crtc) &&
pipe_config_supports_ips(dev_priv, pipe_config);
 }
@@ -9511,7 +9512,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state 
*state)
pixel_rate = ilk_pipe_pixel_rate(crtc_state);
 
/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
-   if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
+   if (IS_BROADWELL(state->dev) && crtc_state->ips_ready)
pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
 
max_pixel_rate = max(max_pixel_rate, pixel_rate);
@@ -9830,9 +9831,7 @@ static bool haswell_get_pipe_config(struct intel_crtc 
*crtc,
ironlake_get_pfit_config(crtc, pipe_config);
}
 
-   if (IS_HASWELL(dev))
-   pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
-   (I915_READ(IPS_CTL) & IPS_ENABLE);
+   pipe_config->ips_ready = hsw_crtc_supports_ips(crtc);
 
if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
pipe_config->pixel_multiplier =
@@ -12001,7 +12000,7 @@ static void intel_dump_pipe_config(struct intel_crtc 
*crtc,
  pipe_config->pch_pfit.pos,
  pipe_config->pch_pfit.size,
  pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
-   DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
+   DRM_DEBUG_KMS("ips ready: %i\n", pipe_config->ips_ready);
DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
 
if (IS_BROXTON(dev)) {
@@ -12553,7 +12552,7 @@ intel_pipe_config_compare(struct drm_device *dev,
 
/* BDW+ don't expose a synchronous way to read the state */
if (IS_HASWELL(dev))
-   PIPE_CONF_CHECK_I(ips_enabled);
+   PIPE_CONF_CHECK_I(ips_ready);
 
PIPE_CONF_CHECK_I(double_wide);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 92518b4..2aae219 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -476,7 +476,7 @@ struct intel_crtc_state {
int fdi_lanes;
struct intel_link_m_n fdi_m_n;
 
-   bool ips_enabled;
+   bool ips_ready;
 
bool double_wide;
 
-- 
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[Intel-gfx] [PATCH 15/31] drm/i915: Use intel_crtc instead of intel_dp on DRRS enable/disable functions.

[Rodrigo Vivi]

No functional changes at this point. Only using intel_crtc instead
of intel_dp to let DRRS enable/disable functions more flexible to be
moved around on a following patch.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_ddi.c  |  4 ++--
 drivers/gpu/drm/i915/intel_drrs.c | 34 +-
 drivers/gpu/drm/i915/intel_drv.h  |  4 ++--
 3 files changed, 25 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 972acef..92918cf 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2404,7 +2404,7 @@ static void intel_enable_ddi(struct intel_encoder 
*intel_encoder)
intel_dp_stop_link_train(intel_dp);
 
intel_edp_backlight_on(intel_dp);
-   intel_drrs_enable(intel_dp);
+   intel_drrs_enable(intel_crtc);
}
 
if (intel_crtc->config->has_audio) {
@@ -2430,7 +2430,7 @@ static void intel_disable_ddi(struct intel_encoder 
*intel_encoder)
if (type == INTEL_OUTPUT_EDP) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
-   intel_drrs_disable(intel_dp);
+   intel_drrs_disable(intel_crtc);
intel_edp_backlight_off(intel_dp);
}
 }
diff --git a/drivers/gpu/drm/i915/intel_drrs.c 
b/drivers/gpu/drm/i915/intel_drrs.c
index dce16ea..6287aee 100644
--- a/drivers/gpu/drm/i915/intel_drrs.c
+++ b/drivers/gpu/drm/i915/intel_drrs.c
@@ -162,17 +162,17 @@ static void intel_drrs_set_state(struct drm_device *dev, 
int refresh_rate)
 
 /**
  * intel_drrs_enable - init drrs struct if supported
- * @intel_dp: DP struct
+ * @intel_crtc: Intel CRTC
  *
  * Initializes frontbuffer_bits and drrs.dp
  */
-void intel_drrs_enable(struct intel_dp *intel_dp)
+void intel_drrs_enable(struct intel_crtc *intel_crtc)
 {
-   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-   struct drm_device *dev = dig_port->base.base.dev;
+   struct drm_device *dev = intel_crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
-   struct drm_crtc *crtc = dig_port->base.base.crtc;
-   struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+   struct drm_crtc *crtc = _crtc->base;
+   struct intel_encoder *intel_encoder;
+   struct intel_dp *intel_dp = NULL;
 
if (!intel_crtc->config->has_drrs) {
DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
@@ -190,6 +190,16 @@ void intel_drrs_enable(struct intel_dp *intel_dp)
goto unlock;
}
 
+   for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
+   if (intel_encoder->type == INTEL_OUTPUT_EDP)
+   intel_dp = enc_to_intel_dp(_encoder->base);
+   }
+
+   if (!intel_dp) {
+   DRM_DEBUG_KMS("No eDP found\n");
+   goto unlock;
+   }
+
dev_priv->drrs.busy_frontbuffer_bits = 0;
 
dev_priv->drrs.dp = intel_dp;
@@ -200,17 +210,14 @@ unlock:
 
 /**
  * intel_edp_drrs_disable - Disable DRRS
- * @intel_dp: DP struct
+ * @intel_crtc: Intel CRTC
  *
  */
-void intel_drrs_disable(struct intel_dp *intel_dp)
+void intel_drrs_disable(struct intel_crtc *intel_crtc)
 {
-   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-   struct drm_device *dev = dig_port->base.base.dev;
+   struct drm_device *dev = intel_crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
-   struct drm_crtc *crtc = dig_port->base.base.crtc;
-   struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-   struct intel_panel *panel = _dp->attached_connector->panel;
+   struct intel_panel *panel;
 
if (!intel_crtc->config->has_drrs)
return;
@@ -221,6 +228,7 @@ void intel_drrs_disable(struct intel_dp *intel_dp)
return;
}
 
+   panel = _priv->drrs.dp->attached_connector->panel;
if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
intel_drrs_set_state(dev_priv->dev,
 panel->fixed_mode->vrefresh);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 73406c3..48f461f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1210,8 +1210,8 @@ u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
 u32 skl_plane_ctl_rotation(unsigned int rotation);
 
 /* intel_drrs.c */
-void intel_drrs_enable(struct intel_dp *intel_dp);
-void intel_drrs_disable(struct intel_dp *intel_dp);
+void intel_drrs_enable(struct intel_crtc *intel_crtc);
+void intel_drrs_disable(struct intel_crtc *intel_crtc);
 void intel_drrs_invalidate(struct drm_device *dev,
unsigned frontbuffer_bits);
 void intel_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
-- 
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[Intel-gfx] [PATCH 04/31] drm/i915: Handle actual IPS enabled state.

[Rodrigo Vivi]

With this we know if IPS is actually enabled.
It might not be activated on BDW since Hardware take
the decision and do its transition. However we have
the visibility of the state on our driver what we didn't
had until this patch. At least on BDW.

Since ips_ready means that ips will be enabled and ips_disable()
checks for the state of our enabled/disabled state machine
we can remove that FIXME that was there for crtc_load_lut
workaround for Haswell.

With this state machine and ips being disabled from
different places and many times when testcases with sink_crtc
for instance it is better to have it protected with its own mutex lock.
Ohterwise we cannot guarantee consitent ips.enabled state with the
register bit.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_debugfs.c  | 12 
 drivers/gpu/drm/i915/i915_drv.h  |  9 -
 drivers/gpu/drm/i915/intel_display.c |  3 ++-
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_ips.c | 35 ---
 5 files changed, 47 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 391861d..f741f13 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1711,14 +1711,10 @@ static int i915_ips_status(struct seq_file *m, void 
*unused)
seq_printf(m, "Enabled by kernel parameter: %s\n",
   yesno(i915.enable_ips));
 
-   if (INTEL_INFO(dev)->gen >= 8) {
-   seq_puts(m, "Currently: unknown\n");
-   } else {
-   if (I915_READ(IPS_CTL) & IPS_ENABLE)
-   seq_puts(m, "Currently: enabled\n");
-   else
-   seq_puts(m, "Currently: disabled\n");
-   }
+   if (dev_priv->display_ips.enabled)
+   seq_puts(m, "Currently: enabled\n");
+   else
+   seq_puts(m, "Currently: disabled\n");
 
intel_runtime_pm_put(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d2a546a..516c0b1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -971,6 +971,11 @@ struct i915_psr {
bool aux_frame_sync;
 };
 
+struct i915_ips {
+   struct mutex lock;
+   bool enabled;
+};
+
 enum intel_pch {
PCH_NONE = 0,   /* No PCH present */
PCH_IBX,/* Ibexpeak PCH */
@@ -1850,12 +1855,14 @@ struct drm_i915_private {
 
/* ilk-only ips/rps state. Everything in here is protected by the global
 * mchdev_lock in intel_pm.c */
-   struct intel_ilk_power_mgmt ips;
+   struct intel_ilk_power_mgmt ips; /* Intelligent Power Sharing */
 
struct i915_power_domains power_domains;
 
struct i915_psr psr;
 
+   struct i915_ips display_ips; /* Intermediate Pixel Storage */
+
struct i915_gpu_error gpu_error;
 
struct drm_i915_gem_object *vlv_pctx;
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 197c608..e5c4056 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4537,7 +4537,6 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
/* Workaround : Do not read or write the pipe palette/gamma data while
 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
 */
-   /* FIXME: This should be ips_enabled */
if (IS_HASWELL(dev) && intel_crtc->config->ips_ready &&
((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
 GAMMA_MODE_MODE_SPLIT)) {
@@ -14190,6 +14189,8 @@ static void intel_setup_outputs(struct drm_device *dev)
 
intel_psr_init(dev);
 
+   intel_ips_init(dev_priv);
+
for_each_intel_encoder(dev, encoder) {
encoder->base.possible_crtcs = encoder->crtc_mask;
encoder->base.possible_clones =
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 41a88f7..cc08566 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1210,6 +1210,7 @@ bool intel_ips_ready(struct intel_crtc *crtc,
 struct intel_crtc_state *crtc_state);
 void intel_ips_enable(struct intel_crtc *crtc);
 void intel_ips_disable(struct intel_crtc *crtc);
+void intel_ips_init(struct drm_i915_private *dev_priv);
 
 /* intel_csr.c */
 void intel_csr_ucode_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_ips.c b/drivers/gpu/drm/i915/intel_ips.c
index 573bc31..1d0d8ff 100644
--- a/drivers/gpu/drm/i915/intel_ips.c
+++ b/drivers/gpu/drm/i915/intel_ips.c
@@ -113,6 +113,11 @@ void intel_ips_enable(struct intel_crtc *crtc)
if (!crtc->config->ips_ready)
return;
 
+   mutex_lock(_priv->display_ips.lock);
+
+   if (dev_priv->display_ips.enabled)
+   goto out;
+
/*
 * We 

[Intel-gfx] [PATCH 09/31] drm/i915: Only enable DRRS if PSR won't be enabled on this pipe.

[Rodrigo Vivi]

With PSR enabled being pre computed on pipe_config we can now
prevent DRRS to be enabled along with PSR.

v2: Rebase after changing previous patch

v3: Fix commit subject. No change in the already reviewed patch.

Signed-off-by: Rodrigo Vivi 
Reviewed-by: Ramalingam C 
---
 drivers/gpu/drm/i915/intel_dp.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e1c3e9a..6ab127c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5248,11 +5248,6 @@ static void intel_dp_set_drrs_state(struct drm_device 
*dev, int refresh_rate)
return;
}
 
-   /*
-* FIXME: This needs proper synchronization with psr state for some
-* platforms that cannot have PSR and DRRS enabled at the same time.
-*/
-
dig_port = dp_to_dig_port(intel_dp);
encoder = _port->base;
intel_crtc = to_intel_crtc(encoder->base.crtc);
@@ -5339,6 +5334,11 @@ void intel_edp_drrs_enable(struct intel_dp *intel_dp)
return;
}
 
+   if (intel_crtc->config->psr_ready) {
+   DRM_DEBUG_KMS("DRRS: PSR will be enabled on this crtc\n");
+   return;
+   }
+
mutex_lock(_priv->drrs.mutex);
if (WARN_ON(dev_priv->drrs.dp)) {
DRM_ERROR("DRRS already enabled\n");
-- 
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[Intel-gfx] [PATCH 23/31] drm/i915: Reduce PSR re-activation time for VLV/CHV.

[Rodrigo Vivi]

With 'commit 30886c5a ("drm/i915: VLV/CHV PSR: Increase wait delay
 time before active PSR.")' we fixed a blank screen when first
activation was happening immediately after PSR being enabled.
There we gave more time for idleness by increasing the delay
between re-activating sequences.

However, commit "drm/i915: Delay first PSR activation."
delay the first activation in a better way keeping a good PSR
residency. So, we can now reduce the delay on re-enable.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_psr.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 6e7e8e6..c090f38 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -738,7 +738,6 @@ void intel_psr_flush(struct drm_device *dev,
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_crtc *crtc;
enum pipe pipe;
-   int delay_ms = HAS_DDI(dev) ? 100 : 500;
 
mutex_lock(_priv->psr.lock);
if (!dev_priv->psr.enabled) {
@@ -759,7 +758,7 @@ void intel_psr_flush(struct drm_device *dev,
if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
if (!work_busy(_priv->psr.work.work))
schedule_delayed_work(_priv->psr.work,
- msecs_to_jiffies(delay_ms));
+ msecs_to_jiffies(100));
mutex_unlock(_priv->psr.lock);
 }
 
-- 
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[Intel-gfx] [PATCH 29/31] drm/i915: Stop tracking last calculated Sink CRC.

[Rodrigo Vivi]

It was created at 'commit aabc95dcf20 (drm/i915: Dont -ETIMEDOUT
on identical new and previous (count, crc).")' becase the counter
wasn't reliable.

Now that we properly wait for the counter to be reset we can rely
a bit more in the counter.

Also that patch stopped to return -ETIMEDOUT so the test case is
unable to skip when it is unreliable and end up in many fails
that should be skip instead.

So, with the counter more reliable we can remove
this hack that just makes things more confusing when test cases
are really expecting the same CRC and let test case skip if that's
not the case.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_dp.c  | 39 +--
 drivers/gpu/drm/i915/intel_drv.h |  2 --
 2 files changed, 9 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5d810cd..24d2bff 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3864,8 +3864,6 @@ static int intel_dp_sink_crc_start(struct intel_dp 
*intel_dp)
if (!(buf & DP_TEST_CRC_SUPPORTED))
return -ENOTTY;
 
-   intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK;
-
if (drm_dp_dpcd_readb(_dp->aux, DP_TEST_SINK, ) < 0)
return -EIO;
 
@@ -3890,7 +3888,6 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
u8 buf;
int count, ret;
int attempts = 6;
-   bool old_equal_new;
 
ret = intel_dp_sink_crc_start(intel_dp);
if (ret)
@@ -3906,35 +3903,17 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 
*crc)
}
count = buf & DP_TEST_COUNT_MASK;
 
-   /*
-* Count might be reset during the loop. In this case
-* last known count needs to be reset as well.
-*/
-   if (count == 0)
-   intel_dp->sink_crc.last_count = 0;
-
-   if (drm_dp_dpcd_read(_dp->aux, DP_TEST_CRC_R_CR, crc, 6) 
< 0) {
-   ret = -EIO;
-   goto stop;
-   }
-
-   old_equal_new = (count == intel_dp->sink_crc.last_count &&
-!memcmp(intel_dp->sink_crc.last_crc, crc,
-6 * sizeof(u8)));
-
-   } while (--attempts && (count == 0 || old_equal_new));
-
-   intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK;
-   memcpy(intel_dp->sink_crc.last_crc, crc, 6 * sizeof(u8));
+   } while (--attempts && count == 0);
 
if (attempts == 0) {
-   if (old_equal_new) {
-   DRM_DEBUG_KMS("Unreliable Sink CRC counter: Current 
returned CRC is identical to the previous one\n");
-   } else {
-   DRM_ERROR("Panel is unable to calculate any CRC after 6 
vblanks\n");
-   ret = -ETIMEDOUT;
-   goto stop;
-   }
+   DRM_ERROR("Panel is unable to calculate any CRC after 6 
vblanks\n");
+   ret = -ETIMEDOUT;
+   goto stop;
+   }
+
+   if (drm_dp_dpcd_read(_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
+   ret = -EIO;
+   goto stop;
}
 
 stop:
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index baa560c..de2a8ff 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -746,8 +746,6 @@ enum link_m_n_set {
 
 struct sink_crc {
bool started;
-   u8 last_crc[6];
-   int last_count;
 };
 
 struct intel_dp {
-- 
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[Intel-gfx] [PATCH 00/31] IPS/DRRS/PSR rework with PSR enabled by default

[Rodrigo Vivi]

Hi all,

The goal of this series is to Enable PSR by default, but in order to do
that first it was necessary to fix few display PM initialization that was
broken after fastboot got enabled by default. Also it was needed to make
sink crc more reliable.

So, divided by topic:

Patches 1-7: IPS reorg/rework
Patches 8-16: DRRS reorg and PSR and DRRS initialization rework.
Patches 17-26: PSR Fixes
Patches 27-30: Let Sink CRC more reliable
Patch 31: Enable PSR by default.

--- Why all in one single series ---

I didn't split the series in different series because there were dependencies
and because they were touching same part of the code. So the rebase in order
is less painful for me than if the patches started getting merged out of order.

--- Why sysfs toggles are here ---

There is a work in progress to add more sysfs interface but with the requirement
to let them organized and documented. But this sysfs toggles were helping me
during debugs and testings a lot so I decided to send them out even before we
finish the design review on the sysfs interfaces etc.
They also help to justify the ips mutex locks. ;)
But I totally understand if the aren't merged at this point.

--- Remaining Known issues ---

1. Features disabled after suspend: There is also a remaining known issue that
is the initilization of these features now rely on the atomic modeset and the
atomic modeset on resume is commiting a zeroed state so the features gets
disabled with suspend/resume and stays disabled until the next full modeset.
Anyway let's start the review and get this
merged and work to fix atomic commit after suspend/resume in parallel.

2. Automated tests as is in this series stil fail on SKL because the aux 
failure.
There is aux retries patches on the mailing list to work around this issue and
also an investigation in progress to see if aux mutex could help here.

3. Few kms_frontbuffer tests are failing even with PSR disabled so I'm just 
ignoring
psr-1p-primscrn-cur-indfb-* test results for now.


--- Validated Hardware ---

manual checks, kms_psr_sink_crc and kms_frontbuffer_tracking were used for 
validation
on different platforms with different kinds of panels:
- Lenovo Yoga 3 (BDW)
- Lenovo T450s (BDW)
- BDW SDP GT3
- BDW SDP ULT
- VLV/BYT
- SKL
- KBL

So I'm confident we can enable PSR back by default now.

All comments, ideas, suggestions and even bikesheddings are pretty welcome.

Thanks,
Rodrigo.

Rodrigo Vivi (31):
  drm/i915: Rename IPS ready variable at pipe config.
  drm/i915: Move IPS related stuff to intel_ips.c
  drm/i915: Add IPS DockBook.
  drm/i915: Handle actual IPS enabled state.
  drm/i915: Fix IPS initialization.
  drm/i915: Fix IPS disable sequence.
  drm/i915: IPS Sysfs interface.
  drm/i915: Add psr_ready on pipe_config
  drm/i915: Only enable DRRS if PSR won't be enabled on this pipe.
  drm/i915: Detatch i915.enable_psr from psr_ready
  drm/i915: Use intel_crtc instead of intel_dp on PSR enable/disable
functions.
  drm/i915: Fix PSR initialization.
  drm/i915: Organize Makefile new display pm group
  drm/i915: Create intel_drrs.c
  drm/i915: Use intel_crtc instead of intel_dp on DRRS enable/disable
functions.
  drm/i915: Fix DRRS initialization.
  drm/i915: Add sys PSR toggle interface.
  drm/i915: Force PSR exit when IRQ_HPD is detected on eDP.
  drm/i915: Remove duplicated dpcd write on hsw_psr_enable_sink.
  drm/i915: PSR: Let's rely more on frontbuffer tracking.
  drm/i915: PSR: Mask LPSP hw tracking back again.
  drm/i915: Delay first PSR activation.
  drm/i915: Reduce PSR re-activation time for VLV/CHV.
  drm/i915: PSR: Don't Skip aux handshake on DP_PSR_NO_TRAIN_ON_EXIT.
  drm/i915: Send TP1 TP2/3 even when panel claims no NO_TRAIN_ON_EXIT.
  drm/i915: Fix idle_frames counter.
  drm/i915: Allow 1 vblank to let Sink CRC calculation to start or stop.
  drm/i915: Make Sink crc calculation waiting for counter to reset.
  drm/i915: Stop tracking last calculated Sink CRC.
  drm/i915: Rely on TEST_SINK_START instead of tracking Sink CRC state
on dev_priv.
  drm/i915: Enable PSR by default.

 Documentation/DocBook/gpu.tmpl   |   5 +
 drivers/gpu/drm/i915/Makefile|   8 +-
 drivers/gpu/drm/i915/i915_debugfs.c  |  16 +-
 drivers/gpu/drm/i915/i915_drv.h  |   9 +-
 drivers/gpu/drm/i915/i915_params.c   |   4 +-
 drivers/gpu/drm/i915/i915_sysfs.c| 165 +++
 drivers/gpu/drm/i915/intel_ddi.c |   6 +-
 drivers/gpu/drm/i915/intel_display.c | 190 +++-
 drivers/gpu/drm/i915/intel_dp.c  | 477 +++
 drivers/gpu/drm/i915/intel_drrs.c| 416 +++
 drivers/gpu/drm/i915/intel_drv.h |  47 +--
 drivers/gpu/drm/i915/intel_frontbuffer.c |   4 +-
 drivers/gpu/drm/i915/intel_ips.c | 259 +
 drivers/gpu/drm/i915/intel_psr.c | 201 -
 14 files changed, 1116 insertions(+), 691 deletions(-)
 create mode 100644 

[Intel-gfx] [PATCH 11/31] drm/i915: Use intel_crtc instead of intel_dp on PSR enable/disable functions.

[Rodrigo Vivi]

This will give us the flexibility to move them to
post atomic modeset functions.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_ddi.c |  4 ++--
 drivers/gpu/drm/i915/intel_dp.c  |  5 +++--
 drivers/gpu/drm/i915/intel_drv.h |  4 ++--
 drivers/gpu/drm/i915/intel_psr.c | 38 --
 4 files changed, 31 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 06d3002..b8f8dee 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2404,7 +2404,7 @@ static void intel_enable_ddi(struct intel_encoder 
*intel_encoder)
intel_dp_stop_link_train(intel_dp);
 
intel_edp_backlight_on(intel_dp);
-   intel_psr_enable(intel_dp);
+   intel_psr_enable(intel_crtc);
intel_edp_drrs_enable(intel_dp);
}
 
@@ -2432,7 +2432,7 @@ static void intel_disable_ddi(struct intel_encoder 
*intel_encoder)
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
intel_edp_drrs_disable(intel_dp);
-   intel_psr_disable(intel_dp);
+   intel_psr_disable(intel_crtc);
intel_edp_backlight_off(intel_dp);
}
 }
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e154a2e..92f59cc 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2374,7 +2374,7 @@ static void intel_disable_dp(struct intel_encoder 
*encoder)
intel_audio_codec_disable(encoder);
 
if (HAS_PSR(dev) && !HAS_DDI(dev))
-   intel_psr_disable(intel_dp);
+   intel_psr_disable(crtc);
 
/* Make sure the panel is off before trying to change the mode. But also
 * ensure that we have vdd while we switch off the panel. */
@@ -2629,9 +2629,10 @@ static void g4x_enable_dp(struct intel_encoder *encoder)
 static void vlv_enable_dp(struct intel_encoder *encoder)
 {
struct intel_dp *intel_dp = enc_to_intel_dp(>base);
+   struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 
intel_edp_backlight_on(intel_dp);
-   intel_psr_enable(intel_dp);
+   intel_psr_enable(crtc);
 }
 
 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 06511d2..cafe4c1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1399,8 +1399,8 @@ void intel_backlight_unregister(struct drm_device *dev);
 /* intel_psr.c */
 bool intel_psr_ready(struct intel_dp *intel_dp,
 struct intel_crtc_state *pipe_config);
-void intel_psr_enable(struct intel_dp *intel_dp);
-void intel_psr_disable(struct intel_dp *intel_dp);
+void intel_psr_enable(struct intel_crtc *intel_crtc);
+void intel_psr_disable(struct intel_crtc *intel_crtc);
 void intel_psr_invalidate(struct drm_device *dev,
  unsigned frontbuffer_bits);
 void intel_psr_flush(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index e690db3..bcf2d9d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -371,18 +371,19 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
 
 /**
  * intel_psr_enable - Enable PSR
- * @intel_dp: Intel DP
+ * @intel_crtc: Intel CRTC
  *
  * This function can only be called after the pipe is fully trained and 
enabled.
  */
-void intel_psr_enable(struct intel_dp *intel_dp)
+void intel_psr_enable(struct intel_crtc *intel_crtc)
 {
-   struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-   struct drm_device *dev = intel_dig_port->base.base.dev;
+   struct drm_crtc *crtc = _crtc->base;
+   struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
-   struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
+   struct intel_encoder *intel_encoder;
+   struct intel_dp *intel_dp = NULL;
 
-   if (!crtc->config->psr_ready)
+   if (!intel_crtc->config->psr_ready)
return;
 
mutex_lock(_priv->psr.lock);
@@ -391,6 +392,16 @@ void intel_psr_enable(struct intel_dp *intel_dp)
goto unlock;
}
 
+   for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
+   if (intel_encoder->type == INTEL_OUTPUT_EDP)
+   intel_dp = enc_to_intel_dp(_encoder->base);
+   }
+
+   if (!intel_dp) {
+   DRM_DEBUG_KMS("No eDP found\n");
+   goto unlock;
+   }
+
dev_priv->psr.busy_frontbuffer_bits = 0;
 
if (HAS_DDI(dev)) {
@@ -398,8 +409,8 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 
if (dev_priv->psr.psr2_support) {
/* PSR2 is restricted to work with panel resolutions 

[Intel-gfx] [PATCH 03/31] drm/i915: Add IPS DockBook.

[Rodrigo Vivi]

Intermediate Pixel Storage documentation.

Signed-off-by: Rodrigo Vivi 
---
 Documentation/DocBook/gpu.tmpl   |  5 +
 drivers/gpu/drm/i915/intel_ips.c | 37 ++---
 2 files changed, 39 insertions(+), 3 deletions(-)

diff --git a/Documentation/DocBook/gpu.tmpl b/Documentation/DocBook/gpu.tmpl
index 54dfd28..e2e01cd 100644
--- a/Documentation/DocBook/gpu.tmpl
+++ b/Documentation/DocBook/gpu.tmpl
@@ -4002,6 +4002,11 @@ int num_ioctls;
 !Idrivers/gpu/drm/i915/intel_fbc.c
   
   
+   Intermediate Pixel Storage (IPS)
+!Pdrivers/gpu/drm/i915/intel_ips.c Intermediate Pixel Storage (IPS)
+!Idrivers/gpu/drm/i915/intel_ips.c
+  
+  
 Display Refresh Rate Switching (DRRS)
 !Pdrivers/gpu/drm/i915/intel_dp.c Display Refresh Rate Switching (DRRS)
 !Fdrivers/gpu/drm/i915/intel_dp.c intel_dp_set_drrs_state
diff --git a/drivers/gpu/drm/i915/intel_ips.c b/drivers/gpu/drm/i915/intel_ips.c
index 5c659a3..573bc31 100644
--- a/drivers/gpu/drm/i915/intel_ips.c
+++ b/drivers/gpu/drm/i915/intel_ips.c
@@ -21,12 +21,21 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-/* IPS only exists on ULT machines and is tied to pipe A. */
-
 #include "intel_drv.h"
 #include "i915_drv.h"
 
-
+/**
+ * DOC: Intermediate Pixel Storage (IPS)
+ *
+ * Haswell-ULT and Broadwell have support to IPS feature where pixel 
information
+ * can be stored in a special buffer in display that can allow memory to get
+ * into deeper power states and spend more time in low power states
+ *
+ * IPS is only supported on Pipe A with pipe pixel format 8:8:8 or less
+ * and when pixel rate is lesser than 95% of the CDCLK frequency.
+ *
+ * IPS cannot be enabled on the pipe when there is no plane enabled.
+ */
 static void assert_plane(struct drm_i915_private *dev_priv,
 enum plane plane, bool state)
 {
@@ -70,6 +79,14 @@ static bool pipe_config_supports_ips(struct drm_i915_private 
*dev_priv,
   dev_priv->max_cdclk_freq * 95 / 100;
 }
 
+/**
+ * intel_ips_ready - Is IPS Ready?
+ * @crtc: intel crtc
+ * @pipe_config: Pipe config
+ *
+ * This function is called to know if IPS is ready to be enabled
+ * on this pipe.
+ */
 bool intel_ips_ready(struct intel_crtc *crtc,
 struct intel_crtc_state *pipe_config)
 {
@@ -81,6 +98,13 @@ bool intel_ips_ready(struct intel_crtc *crtc,
   pipe_config_supports_ips(dev_priv, pipe_config);
 }
 
+/**
+ * intel_ips_enable - Enable IPS
+ * @crtc: intel crtc
+ *
+ * This function is called to enable IPS on certain pipe.
+ * All needed conditions should've checked already by intel_ips_ready.
+ */
 void intel_ips_enable(struct intel_crtc *crtc)
 {
struct drm_device *dev = crtc->base.dev;
@@ -121,6 +145,13 @@ void intel_ips_enable(struct intel_crtc *crtc)
}
 }
 
+/**
+ * intel_ips_disable - Disable IPS
+ * @crtc: intel crtc
+ *
+ * This function is called to disable IPS on certain pipe whenever it is needed
+ * to disable IPS on the pipe.
+ */
 void intel_ips_disable(struct intel_crtc *crtc)
 {
struct drm_device *dev = crtc->base.dev;
-- 
2.4.3

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[Intel-gfx] [PATCH 26/31] drm/i915: Fix idle_frames counter.

[Rodrigo Vivi]

'commit 97173eaf5 ("drm/i915: PSR: Increase idle_frames")' was a mistake.
The special case it tried to cover is already being covered by
the DP_PSR_NO_TRAIN_ON_EXIT. So let's remove this mistake instead of
start using 9 idle frames for that case.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_psr.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index ee426ea..4e3d315 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -249,12 +249,9 @@ static void hsw_psr_enable_source(struct intel_dp 
*intel_dp)
/* Lately it was identified that depending on panel idle frame count
 * calculated at HW can be off by 1. So let's use what came
 * from VBT + 1.
-* There are also other cases where panel demands at least 4
-* but VBT is not being set. To cover these 2 cases lets use
-* at least 5 when VBT isn't set to be on the safest side.
 */
uint32_t idle_frames = dev_priv->vbt.psr.idle_frames ?
-  dev_priv->vbt.psr.idle_frames + 1 : 5;
+  dev_priv->vbt.psr.idle_frames + 1 : 2;
uint32_t val = 0x0;
const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 
-- 
2.4.3

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[Intel-gfx] [PATCH 14/31] drm/i915: Create intel_drrs.c

[Rodrigo Vivi]

No functional change. Jusr organizing display pm features
in a standardized and uniform way.

This first step allow us to fix drrs initialization that
is broken with fastboot by default.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/Makefile|   3 +-
 drivers/gpu/drm/i915/intel_ddi.c |   4 +-
 drivers/gpu/drm/i915/intel_dp.c  | 386 +
 drivers/gpu/drm/i915/intel_drrs.c| 408 +++
 drivers/gpu/drm/i915/intel_drv.h |  15 +-
 drivers/gpu/drm/i915/intel_frontbuffer.c |   4 +-
 6 files changed, 426 insertions(+), 394 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_drrs.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5c92a47..da3d2cc 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -51,7 +51,8 @@ i915-y += intel_renderstate_gen6.o \
  intel_renderstate_gen9.o
 
 # display pm
-i915-y += intel_fbc.o \
+i915-y += intel_drrs.o \
+ intel_fbc.o \
  intel_ips.o \
  intel_psr.o
 
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 36db970..972acef 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2404,7 +2404,7 @@ static void intel_enable_ddi(struct intel_encoder 
*intel_encoder)
intel_dp_stop_link_train(intel_dp);
 
intel_edp_backlight_on(intel_dp);
-   intel_edp_drrs_enable(intel_dp);
+   intel_drrs_enable(intel_dp);
}
 
if (intel_crtc->config->has_audio) {
@@ -2430,7 +2430,7 @@ static void intel_disable_ddi(struct intel_encoder 
*intel_encoder)
if (type == INTEL_OUTPUT_EDP) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
-   intel_edp_drrs_disable(intel_dp);
+   intel_drrs_disable(intel_dp);
intel_edp_backlight_off(intel_dp);
}
 }
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f0ee497..a421c17 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5212,388 +5212,6 @@ intel_dp_init_panel_power_sequencer_registers(struct 
drm_device *dev,
  I915_READ(pp_div_reg));
 }
 
-/**
- * intel_dp_set_drrs_state - program registers for RR switch to take effect
- * @dev: DRM device
- * @refresh_rate: RR to be programmed
- *
- * This function gets called when refresh rate (RR) has to be changed from
- * one frequency to another. Switches can be between high and low RR
- * supported by the panel or to any other RR based on media playback (in
- * this case, RR value needs to be passed from user space).
- *
- * The caller of this function needs to take a lock on dev_priv->drrs.
- */
-static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
-{
-   struct drm_i915_private *dev_priv = dev->dev_private;
-   struct intel_encoder *encoder;
-   struct intel_digital_port *dig_port = NULL;
-   struct intel_dp *intel_dp = dev_priv->drrs.dp;
-   struct intel_crtc_state *config = NULL;
-   struct intel_crtc *intel_crtc = NULL;
-   enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
-
-   if (refresh_rate <= 0) {
-   DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
-   return;
-   }
-
-   if (intel_dp == NULL) {
-   DRM_DEBUG_KMS("DRRS not supported.\n");
-   return;
-   }
-
-   dig_port = dp_to_dig_port(intel_dp);
-   encoder = _port->base;
-   intel_crtc = to_intel_crtc(encoder->base.crtc);
-
-   if (!intel_crtc) {
-   DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
-   return;
-   }
-
-   config = intel_crtc->config;
-
-   if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
-   DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
-   return;
-   }
-
-   if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
-   refresh_rate)
-   index = DRRS_LOW_RR;
-
-   if (index == dev_priv->drrs.refresh_rate_type) {
-   DRM_DEBUG_KMS(
-   "DRRS requested for previously set RR...ignoring\n");
-   return;
-   }
-
-   if (!intel_crtc->active) {
-   DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
-   return;
-   }
-
-   if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
-   switch (index) {
-   case DRRS_HIGH_RR:
-   intel_dp_set_m_n(intel_crtc, M1_N1);
-   break;
-   case DRRS_LOW_RR:
-   intel_dp_set_m_n(intel_crtc, M2_N2);
-   break;
-   case DRRS_MAX_RR:
-   default:
-   

[Intel-gfx] [PATCH 24/31] drm/i915: PSR: Don't Skip aux handshake on DP_PSR_NO_TRAIN_ON_EXIT.

[Rodrigo Vivi]

Since the beginning there is a confusion on the meaning of this bit.

A previous patch had identified this already and fixed it partially:
'commit 3301d409 ("drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic")

DP_PSR_NO_TRAIN_ON_EXIT means the source doesn't need to do the
training, but it doesn't tell to avoid TP patterns or to skip
aux handshake.

This patch fixes the hard freeze reported.

Reference: https://bugs.freedesktop.org/show_bug.cgi?id=91436
Reference: https://bugs.freedesktop.org/show_bug.cgi?id=91437

Cc: Ivan Mitev 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_psr.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index c090f38..4e88e2e 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -263,7 +263,6 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
   send the minimal TP1 possible and skip TP2. */
val |= EDP_PSR_TP1_TIME_100us;
val |= EDP_PSR_TP2_TP3_TIME_0us;
-   val |= EDP_PSR_SKIP_AUX_EXIT;
/* Sink should be able to train with the 5 or 6 idle patterns */
idle_frames += 4;
}
-- 
2.4.3

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[Intel-gfx] [PATCH 13/31] drm/i915: Organize Makefile new display pm group

[Rodrigo Vivi]

No functional changes, just to organize the Makefile
by creating a new group for display pm since it doesn't
make sense to let them on core modeset group.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/Makefile | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7c1a86e..5c92a47 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -50,20 +50,22 @@ i915-y += intel_renderstate_gen6.o \
  intel_renderstate_gen8.o \
  intel_renderstate_gen9.o
 
+# display pm
+i915-y += intel_fbc.o \
+ intel_ips.o \
+ intel_psr.o
+
 # modesetting core code
 i915-y += intel_audio.o \
  intel_atomic.o \
  intel_atomic_plane.o \
  intel_bios.o \
  intel_display.o \
- intel_fbc.o \
  intel_fifo_underrun.o \
  intel_frontbuffer.o \
  intel_hotplug.o \
- intel_ips.o \
  intel_modes.o \
  intel_overlay.o \
- intel_psr.o \
  intel_sideband.o \
  intel_sprite.o
 i915-$(CONFIG_ACPI)+= intel_acpi.o intel_opregion.o
-- 
2.4.3

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[Intel-gfx] [PATCH 02/31] drm/i915: Move IPS related stuff to intel_ips.c

[Rodrigo Vivi]

We need to organize ips a bit in order to fix it initialization
So let's start by following other features by moving all relted
functions to its own file.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/Makefile|   1 +
 drivers/gpu/drm/i915/i915_debugfs.c  |   4 +-
 drivers/gpu/drm/i915/intel_display.c | 127 ++---
 drivers/gpu/drm/i915/intel_dp.c  |   6 +-
 drivers/gpu/drm/i915/intel_drv.h |   8 +-
 drivers/gpu/drm/i915/intel_ips.c | 151 +++
 6 files changed, 170 insertions(+), 127 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_ips.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0851de07..7c1a86e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -60,6 +60,7 @@ i915-y += intel_audio.o \
  intel_fifo_underrun.o \
  intel_frontbuffer.o \
  intel_hotplug.o \
+ intel_ips.o \
  intel_modes.o \
  intel_overlay.o \
  intel_psr.o \
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5659d4c..391861d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4034,7 +4034,7 @@ static int pipe_crc_set_source(struct drm_device *dev, 
enum pipe pipe,
 * user space can't make reliable use of the CRCs, so let's just
 * completely disable it.
 */
-   hsw_disable_ips(crtc);
+   intel_ips_disable(crtc);
 
spin_lock_irq(_crc->lock);
kfree(pipe_crc->entries);
@@ -4079,7 +4079,7 @@ static int pipe_crc_set_source(struct drm_device *dev, 
enum pipe pipe,
else if (IS_HASWELL(dev) && pipe == PIPE_A)
hsw_trans_edp_pipe_A_crc_wa(dev, false);
 
-   hsw_enable_ips(crtc);
+   intel_ips_disable(crtc);
}
 
return 0;
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 01da1c9..197c608 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1366,22 +1366,6 @@ void assert_pipe(struct drm_i915_private *dev_priv,
 pipe_name(pipe), state_string(state), state_string(cur_state));
 }
 
-static void assert_plane(struct drm_i915_private *dev_priv,
-enum plane plane, bool state)
-{
-   u32 val;
-   bool cur_state;
-
-   val = I915_READ(DSPCNTR(plane));
-   cur_state = !!(val & DISPLAY_PLANE_ENABLE);
-   I915_STATE_WARN(cur_state != state,
-"plane %c assertion failure (expected %s, current %s)\n",
-plane_name(plane), state_string(state), state_string(cur_state));
-}
-
-#define assert_plane_enabled(d, p) assert_plane(d, p, true)
-#define assert_plane_disabled(d, p) assert_plane(d, p, false)
-
 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
   enum pipe pipe)
 {
@@ -4529,64 +4513,6 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc)
}
 }
 
-void hsw_enable_ips(struct intel_crtc *crtc)
-{
-   struct drm_device *dev = crtc->base.dev;
-   struct drm_i915_private *dev_priv = dev->dev_private;
-
-   if (!crtc->config->ips_ready)
-   return;
-
-   /* We can only enable IPS after we enable a plane and wait for a vblank 
*/
-   intel_wait_for_vblank(dev, crtc->pipe);
-
-   assert_plane_enabled(dev_priv, crtc->plane);
-   if (IS_BROADWELL(dev)) {
-   mutex_lock(_priv->rps.hw_lock);
-   WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 
0xc000));
-   mutex_unlock(_priv->rps.hw_lock);
-   /* Quoting Art Runyan: "its not safe to expect any particular
-* value in IPS_CTL bit 31 after enabling IPS through the
-* mailbox." Moreover, the mailbox may return a bogus state,
-* so we need to just enable it and continue on.
-*/
-   } else {
-   I915_WRITE(IPS_CTL, IPS_ENABLE);
-   /* The bit only becomes 1 in the next vblank, so this wait here
-* is essentially intel_wait_for_vblank. If we don't have this
-* and don't wait for vblanks until the end of crtc_enable, then
-* the HW state readout code will complain that the expected
-* IPS_CTL value is not the one we read. */
-   if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
-   DRM_ERROR("Timed out waiting for IPS enable\n");
-   }
-}
-
-void hsw_disable_ips(struct intel_crtc *crtc)
-{
-   struct drm_device *dev = crtc->base.dev;
-   struct drm_i915_private *dev_priv = dev->dev_private;
-
-   if (!crtc->config->ips_ready)
-   return;
-
-   

[Intel-gfx] [PATCH 19/31] drm/i915: Remove duplicated dpcd write on hsw_psr_enable_sink.

[Rodrigo Vivi]

This is wrong since my commit (89251b17). The intention of that
commit was to remove this one here that is also wrong anyway,
but it was forgotten.

Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_psr.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index c49c6bd..8c9ba42 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -167,9 +167,6 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 
aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
 
-   drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG,
-  DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
-
/* Enable AUX frame sync at sink */
if (dev_priv->psr.aux_frame_sync)
drm_dp_dpcd_writeb(_dp->aux,
-- 
2.4.3

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[Intel-gfx] [PATCH 25/31] drm/i915: Send TP1 TP2/3 even when panel claims no NO_TRAIN_ON_EXIT.

[Rodrigo Vivi]

On the commit 3301d4092106 ("drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic")'
we already had identified that DP_PSR_NO_TRAIN_ON_EXIT
doesn't mean we shouldn't send TPS patterns, however we start sending the
minimal TP1 as possible and no TP2.

For most of the panels this is ok, but we found a reported case where
this is not true and panel keeps frozen without updating the screen for a while.

We could just get this case after patch "PSR: Don't Skip aux handshake on
DP_PSR_NO_TRAIN_ON_EXIT." is applied since that one fix the
hard freeze on this kind of panels.

Reference: https://bugs.freedesktop.org/show_bug.cgi?id=91436#c19

Cc: Ivan Mitev 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_psr.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 4e88e2e..ee426ea 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -259,10 +259,6 @@ static void hsw_psr_enable_source(struct intel_dp 
*intel_dp)
const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 
if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
-   /* It doesn't mean we shouldn't send TPS patters, so let's
-  send the minimal TP1 possible and skip TP2. */
-   val |= EDP_PSR_TP1_TIME_100us;
-   val |= EDP_PSR_TP2_TP3_TIME_0us;
/* Sink should be able to train with the 5 or 6 idle patterns */
idle_frames += 4;
}
-- 
2.4.3

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[Intel-gfx] [PATCH i-g-t 2/8] kms_frontbuffer_tracking: Skip on unreliable CRC.

[Rodrigo Vivi]

Even with all sink crc re-works we still have platforms
where after 6 vblanks it is unable to calculate the
sink crc. But if we don't get the sink crc it isn't true
that test failed, but that we have no ways to say test
passed or failed.

So let's print a message and move forward in case sink crc
cannot help us to know if the screen has been updated.

Signed-off-by: Rodrigo Vivi 
---
 tests/kms_frontbuffer_tracking.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index cd2879d..606d0a9 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -858,10 +858,17 @@ static bool psr_wait_until_enabled(void)
 
 static void get_sink_crc(sink_crc_t *crc)
 {
+   int rc, errno_;
+
lseek(sink_crc.fd, 0, SEEK_SET);
 
-   igt_assert(read(sink_crc.fd, crc->data, SINK_CRC_SIZE) ==
-  SINK_CRC_SIZE);
+   rc = read(sink_crc.fd, crc->data, SINK_CRC_SIZE);
+   errno_ = errno;
+
+   if (rc == -1 && errno_ == ETIMEDOUT)
+   igt_skip("Sink CRC is unreliable on this machine. Try running 
this test again individually\n");
+
+   igt_assert(rc == SINK_CRC_SIZE);
 }
 
 static bool sink_crc_equal(sink_crc_t *a, sink_crc_t *b)
-- 
2.4.3

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[Intel-gfx] [PATCH i-g-t 1/8] kms_frontbuffer_tracking: Increase the time we wait for PSR.

[Rodrigo Vivi]

With commit (drm/i915: Delay first PSR activation.) in kernel
PSR might take a bit longer to really activate after the modeset.

Signed-off-by: Rodrigo Vivi 
---
 tests/kms_frontbuffer_tracking.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 38ed662..cd2879d 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -848,7 +848,7 @@ static bool fbc_wait_until_enabled(void)
 
 static bool psr_wait_until_enabled(void)
 {
-   return igt_wait(psr_is_enabled(), 2000, 1);
+   return igt_wait(psr_is_enabled(), 5000, 1);
 }
 
 #define fbc_enable() igt_set_module_param_int("enable_fbc", 1)
-- 
2.4.3

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[Intel-gfx] [PATCH i-g-t 8/8] kms_psr_sink_crc: Add suspend/resume sub test.

[Rodrigo Vivi]

Also add a option to allow us to skip this test case in machines
where other suspend/resume issues would break the test exectution.

Signed-off-by: Rodrigo Vivi 
---
 tests/kms_psr_sink_crc.c | 38 +-
 1 file changed, 37 insertions(+), 1 deletion(-)

diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
index b2f88ea..e2ca988 100644
--- a/tests/kms_psr_sink_crc.c
+++ b/tests/kms_psr_sink_crc.c
@@ -31,6 +31,7 @@
 #include "intel_bufmgr.h"
 
 bool running_with_psr_disabled;
+bool no_suspend;
 
 #define CRC_BLACK ""
 
@@ -530,6 +531,9 @@ static int opt_handler(int opt, int opt_index, void *data)
case 'n':
running_with_psr_disabled = true;
break;
+   case 's':
+   no_suspend = true;
+   break;
default:
igt_assert(0);
}
@@ -540,9 +544,11 @@ static int opt_handler(int opt, int opt_index, void *data)
 int main(int argc, char *argv[])
 {
const char *help_str =
-  "  --no-psr\tRun test without PSR to check the CRC test logic.";
+   "  --no-psr\tRun test without PSR to check the CRC test logic."
+   "  --no-suspend\tDon't run suspend resume test cases.";
static struct option long_options[] = {
{"no-psr", 0, 0, 'n'},
+   {"no-suspend", 0, 0, 's'},
{ 0, 0, 0, 0 }
};
data_t data = {};
@@ -626,6 +632,36 @@ int main(int argc, char *argv[])
test_cleanup();
}
 
+   igt_subtest_f("suspend_psr_active") {
+
+   igt_skip_on(no_suspend);
+
+   data.test_plane = PRIMARY;
+   data.op = PAGE_FLIP;
+   setup_test_plane();
+   igt_assert(wait_psr_entry());
+
+   igt_system_suspend_autoresume();
+
+   run_test();
+   test_cleanup();
+   }
+
+   igt_subtest_f("suspend_psr_exit") {
+
+   igt_skip_on(no_suspend);
+
+   data.test_plane = CURSOR;
+   data.op = PLANE_ONOFF;
+   setup_test_plane();
+
+   igt_system_suspend_autoresume();
+
+   igt_assert(wait_psr_entry());
+   run_test();
+   test_cleanup();
+   }
+
igt_fixture {
drm_intel_bufmgr_destroy(data.bufmgr);
display_fini();
-- 
2.4.3

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[Intel-gfx] [PATCH i-g-t 3/8] kms_frontbuffer_tracking: Allow pipe crc or sink crc individually.

[Rodrigo Vivi]

Sink CRC should be enough by itself to validate PSR. Also sometimes
the error might be on the CRC calculations themselves. So let's give
the flexibility to use either individually.

Signed-off-by: Rodrigo Vivi 
---
 tests/kms_frontbuffer_tracking.c | 29 +++--
 1 file changed, 23 insertions(+), 6 deletions(-)

diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 606d0a9..d879493 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -232,7 +232,8 @@ struct draw_pattern_info pattern4;
 /* Command line parameters. */
 struct {
bool check_status;
-   bool check_crc;
+   bool check_pipe_crc;
+   bool check_sink_crc;
bool fbc_check_compression;
bool fbc_check_last_action;
bool no_edp;
@@ -244,7 +245,8 @@ struct {
int shared_fb_y_offset;
 } opt = {
.check_status = true,
-   .check_crc = true,
+   .check_pipe_crc = true,
+   .check_sink_crc = true,
.fbc_check_compression = true,
.fbc_check_last_action = true,
.no_edp = false,
@@ -1578,15 +1580,17 @@ static int adjust_assertion_flags(const struct 
test_mode *t, int flags)
int flags__ = (flags);  \
struct both_crcs crc_;  \
\
-   if (!opt.check_crc || (flags__ & DONT_ASSERT_CRC))  \
+   if (flags__ & DONT_ASSERT_CRC)  \
break;  \
\
collect_crcs(_);\
print_crc("Calculated CRC:", _);\
\
igt_assert(wanted_crc); \
-   igt_assert_crc_equal(_.pipe, _crc->pipe);\
-   assert_sink_crc_equal(_.sink, _crc->sink);   \
+   if (opt.check_pipe_crc) \
+   igt_assert_crc_equal(_.pipe, _crc->pipe);\
+   if (opt.check_sink_crc) \
+   assert_sink_crc_equal(_.sink, _crc->sink);   \
 } while (0)
 
 #define do_status_assertions(flags_) do {  \
@@ -2926,7 +2930,16 @@ static int opt_handler(int option, int option_index, 
void *data)
opt.check_status = false;
break;
case 'c':
-   opt.check_crc = false;
+   opt.check_pipe_crc = false;
+   opt.check_sink_crc = false;
+   break;
+   case 'S':
+   opt.check_pipe_crc = false;
+   opt.check_sink_crc = true;
+   break;
+   case 'P':
+   opt.check_pipe_crc = true;
+   opt.check_sink_crc = false;
break;
case 'o':
opt.fbc_check_compression = false;
@@ -2974,6 +2987,8 @@ static int opt_handler(int option, int option_index, void 
*data)
 const char *help_str =
 "  --no-status-check   Don't check for enable/disable status\n"
 "  --no-crc-check  Don't check for CRC values\n"
+"  --sink-crc-only Check for Sink CRC only. Don't check for Pipe 
CRC value\n"
+"  --pipe-crc-only Check for Pipe CRC only. Don't check for Sink 
CRC value\n"
 "  --no-fbc-compression-check  Don't check for the FBC compression status\n"
 "  --no-fbc-action-check   Don't check for the FBC last action\n"
 "  --no-edpDon't use eDP monitors\n"
@@ -3097,6 +3112,8 @@ int main(int argc, char *argv[])
struct option long_options[] = {
{ "no-status-check",  0, 0, 's'},
{ "no-crc-check", 0, 0, 'c'},
+   { "sink-crc-only",0, 0, 'S'},
+   { "pipe-crc-only",0, 0, 'P'},
{ "no-fbc-compression-check", 0, 0, 'o'},
{ "no-fbc-action-check",  0, 0, 'a'},
{ "no-edp",   0, 0, 'e'},
-- 
2.4.3

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[Intel-gfx] [PATCH i-g-t 4/8] kms_frontbuffer_tracking: Allow to skip suspend_resume sub test case.

[Rodrigo Vivi]

There are few platforms with other suspend resume bugs that breaks
the full execution. So let's provide a way to skip suspend resume case.

Signed-off-by: Rodrigo Vivi 
---
 tests/kms_frontbuffer_tracking.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index d879493..1cc1c9e 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -237,6 +237,7 @@ struct {
bool fbc_check_compression;
bool fbc_check_last_action;
bool no_edp;
+   bool no_suspend;
bool small_modes;
bool show_hidden;
int step;
@@ -250,6 +251,7 @@ struct {
.fbc_check_compression = true,
.fbc_check_last_action = true,
.no_edp = false,
+   .no_suspend = false,
.small_modes = false,
.show_hidden= false,
.step = 0,
@@ -2735,6 +2737,8 @@ static void suspend_subtest(const struct test_mode *t)
 {
struct modeset_params *params = pick_params(t);
 
+   igt_skip_on(opt.no_suspend);
+
prepare_subtest(t, NULL);
sleep(5);
igt_system_suspend_autoresume();
@@ -2950,6 +2954,9 @@ static int opt_handler(int option, int option_index, void 
*data)
case 'e':
opt.no_edp = true;
break;
+   case 'r':
+   opt.no_suspend = true;
+   break;
case 'm':
opt.small_modes = true;
break;
@@ -2992,6 +2999,7 @@ const char *help_str =
 "  --no-fbc-compression-check  Don't check for the FBC compression status\n"
 "  --no-fbc-action-check   Don't check for the FBC last action\n"
 "  --no-edpDon't use eDP monitors\n"
+"  --no-suspendDon't run Suspend/Resume test cases\n"
 "  --use-small-modes   Use smaller resolutions for the modes\n"
 "  --show-hidden   Show hidden subtests\n"
 "  --step  Stop on each step so you can check the screen\n"
@@ -3117,6 +3125,7 @@ int main(int argc, char *argv[])
{ "no-fbc-compression-check", 0, 0, 'o'},
{ "no-fbc-action-check",  0, 0, 'a'},
{ "no-edp",   0, 0, 'e'},
+   { "no-suspend",   0, 0, 'r'},
{ "use-small-modes",  0, 0, 'm'},
{ "show-hidden",  0, 0, 'i'},
{ "step", 0, 0, 't'},
-- 
2.4.3

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[Intel-gfx] [PATCH i-g-t 5/8] kms_frontbuffer_tracking: Add option to allow running tescases with PSR disabled.

[Rodrigo Vivi]

We need to be able to identify if the issue is feature related
or caused by another bug.

Also this feature allow users to have a visual feedback of what to
expect when running the test case for real.

Signed-off-by: Rodrigo Vivi 
---
 tests/kms_frontbuffer_tracking.c | 18 +++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 1cc1c9e..312c08e 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -238,6 +238,7 @@ struct {
bool fbc_check_last_action;
bool no_edp;
bool no_suspend;
+   bool psr_disabled;
bool small_modes;
bool show_hidden;
int step;
@@ -252,6 +253,7 @@ struct {
.fbc_check_last_action = true,
.no_edp = false,
.no_suspend = false,
+   .psr_disabled = false,
.small_modes = false,
.show_hidden= false,
.step = 0,
@@ -1617,7 +1619,7 @@ static int adjust_assertion_flags(const struct test_mode 
*t, int flags)
}   \
\
if (flags_ & ASSERT_PSR_ENABLED) {  \
-   if (!psr_wait_until_enabled()) {\
+   if (!opt.psr_disabled && !psr_wait_until_enabled()) {   \
psr_print_status(); \
igt_assert_f(false, "PSR disabled\n");  \
}   \
@@ -1717,8 +1719,13 @@ static void enable_features_for_test(const struct 
test_mode *t)
 {
if (t->feature & FEATURE_FBC)
fbc_enable();
-   if (t->feature & FEATURE_PSR)
-   psr_enable();
+   if (t->feature & FEATURE_PSR) {
+   if (opt.psr_disabled) {
+   igt_info("WARNING: Running with PSR disabled\n");
+   psr_disable();
+   } else
+   psr_enable();
+   }
 }
 
 static void check_test_requirements(const struct test_mode *t)
@@ -2957,6 +2964,9 @@ static int opt_handler(int option, int option_index, void 
*data)
case 'r':
opt.no_suspend = true;
break;
+   case 'R':
+   opt.psr_disabled = true;
+   break;
case 'm':
opt.small_modes = true;
break;
@@ -3000,6 +3010,7 @@ const char *help_str =
 "  --no-fbc-action-check   Don't check for the FBC last action\n"
 "  --no-edpDon't use eDP monitors\n"
 "  --no-suspendDon't run Suspend/Resume test cases\n"
+"  --psr-disabled  Dry-run. Run tests with PSR feature disabled.\n"
 "  --use-small-modes   Use smaller resolutions for the modes\n"
 "  --show-hidden   Show hidden subtests\n"
 "  --step  Stop on each step so you can check the screen\n"
@@ -3126,6 +3137,7 @@ int main(int argc, char *argv[])
{ "no-fbc-action-check",  0, 0, 'a'},
{ "no-edp",   0, 0, 'e'},
{ "no-suspend",   0, 0, 'r'},
+   { "psr-disabled", 0, 0, 'R'},
{ "use-small-modes",  0, 0, 'm'},
{ "show-hidden",  0, 0, 'i'},
{ "step", 0, 0, 't'},
-- 
2.4.3

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[Intel-gfx] [PATCH i-g-t 7/8] kms_psr_sink_crc: Fix no-psr option.

[Rodrigo Vivi]

commit 75b286e821 ("tests/kms_psr_sink_crc: test even
if PSR is disabled by default")' force PSR enabling without
respecting the no-psr (running-with-psr-disabled) option.

Signed-off-by: Rodrigo Vivi 
---
 tests/kms_psr_sink_crc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
index 387c615..b2f88ea 100644
--- a/tests/kms_psr_sink_crc.c
+++ b/tests/kms_psr_sink_crc.c
@@ -557,7 +557,8 @@ int main(int argc, char *argv[])
kmstest_set_vt_graphics_mode();
data.devid = intel_get_drm_devid(data.drm_fd);
 
-   igt_set_module_param_int("enable_psr", 1);
+   igt_set_module_param_int("enable_psr", 
running_with_psr_disabled ?
+0 : 1);
 
igt_skip_on(!psr_possible());
 
-- 
2.4.3

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[Intel-gfx] [PATCH i-g-t 6/8] kms_frontbuffer_tracking: Add option to allow running tescases with FBC disabled.

[Rodrigo Vivi]

We need to be able to identify if the issue is feature related
or caused by another bug.

Also this feature allow users to have a visual feedback of what to
expect when running the test case for real.

Signed-off-by: Rodrigo Vivi 
---
 tests/kms_frontbuffer_tracking.c | 16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 312c08e..891fab5 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -239,6 +239,7 @@ struct {
bool no_edp;
bool no_suspend;
bool psr_disabled;
+   bool fbc_disabled;
bool small_modes;
bool show_hidden;
int step;
@@ -254,6 +255,7 @@ struct {
.no_edp = false,
.no_suspend = false,
.psr_disabled = false,
+   .fbc_disabled = false,
.small_modes = false,
.show_hidden= false,
.step = 0,
@@ -1717,8 +1719,13 @@ static void set_sprite_for_test(const struct test_mode 
*t,
 
 static void enable_features_for_test(const struct test_mode *t)
 {
-   if (t->feature & FEATURE_FBC)
-   fbc_enable();
+   if (t->feature & FEATURE_FBC) {
+   if (opt.fbc_disabled) {
+   igt_info("WARNING: Running with PSR disabled\n");
+   fbc_disable();
+   } else
+   fbc_enable();
+   }
if (t->feature & FEATURE_PSR) {
if (opt.psr_disabled) {
igt_info("WARNING: Running with PSR disabled\n");
@@ -2967,6 +2974,9 @@ static int opt_handler(int option, int option_index, void 
*data)
case 'R':
opt.psr_disabled = true;
break;
+   case 'F':
+   opt.fbc_disabled = true;
+   break;
case 'm':
opt.small_modes = true;
break;
@@ -3011,6 +3021,7 @@ const char *help_str =
 "  --no-edpDon't use eDP monitors\n"
 "  --no-suspendDon't run Suspend/Resume test cases\n"
 "  --psr-disabled  Dry-run. Run tests with PSR feature disabled.\n"
+"  --fbc-disabled  Dry-run. Run tests with FBC feature disabled.\n"
 "  --use-small-modes   Use smaller resolutions for the modes\n"
 "  --show-hidden   Show hidden subtests\n"
 "  --step  Stop on each step so you can check the screen\n"
@@ -3138,6 +3149,7 @@ int main(int argc, char *argv[])
{ "no-edp",   0, 0, 'e'},
{ "no-suspend",   0, 0, 'r'},
{ "psr-disabled", 0, 0, 'R'},
+   { "fbc-disabled", 0, 0, 'F'},
{ "use-small-modes",  0, 0, 'm'},
{ "show-hidden",  0, 0, 'i'},
{ "step", 0, 0, 't'},
-- 
2.4.3

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Re: [Intel-gfx] [PATCH i-g-t 1/8] kms_frontbuffer_tracking: Increase the time we wait for PSR.

[Paulo Zanoni]

2015-11-05 16:53 GMT-02:00 Rodrigo Vivi :
> With commit (drm/i915: Delay first PSR activation.) in kernel
> PSR might take a bit longer to really activate after the modeset.

Can you please expand this commit message a little bit for Future
Paulo and Future Rodrigo? It would be nice to mention that the timeout
is going to be 5 times the panel power cycle delay, which is XYZms for
your machine, so the timeout needs to be a minimum of Xs, so 5s is the
safe value (we print the panel power cycle delay time on dmesg).

Also, maybe add a notice that since we do a lot of
assert(psr_disabled), this commit is increasing the time it takes to
run the whole set of PSR tests by a few minutes (check commit
f4db3b18841263f8f617a9f7f0aaf14fab7196d1 for an explanation).

Maybe you could also provide patch 9/8 adding a DONT_ASSERT_PSR_STATUS
flag and patch 10/8 that changes the callers of op_disables_psr(),
making them use DONT_ASSERT_PSR_STATUS so we won't eat the full 5s
timeout during every single GTT mmap test. This will make the time it
takes to run the full set of PSR tests even smaller than what it is
today (!!!).

With the improved commit message: Reviewed-by: Paulo Zanoni


>
> Signed-off-by: Rodrigo Vivi 
> ---
>  tests/kms_frontbuffer_tracking.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tests/kms_frontbuffer_tracking.c 
> b/tests/kms_frontbuffer_tracking.c
> index 38ed662..cd2879d 100644
> --- a/tests/kms_frontbuffer_tracking.c
> +++ b/tests/kms_frontbuffer_tracking.c
> @@ -848,7 +848,7 @@ static bool fbc_wait_until_enabled(void)
>
>  static bool psr_wait_until_enabled(void)
>  {
> -   return igt_wait(psr_is_enabled(), 2000, 1);
> +   return igt_wait(psr_is_enabled(), 5000, 1);
>  }
>
>  #define fbc_enable() igt_set_module_param_int("enable_fbc", 1)
> --
> 2.4.3
>
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-- 
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[Intel-gfx] Regression report] Weekly regression report WW45

[jairo . daniel . miramontes . caton]

WW45 Regression report.

This week's regressions
+---+---+++
| BugId | Summary   | Created on | Bisect |
+---+---+++
| 92718 | [REGRESSION] 4.3.0-rc7 - Multiple identical k | 2015-10-29 | No |
| 92737 | [SKL] [Regression] igt/gem_ctx_param_basic/in | 2015-10-30 | No |
+---+---+++



Older regressions
+---+---+++
| BugId | Summary   | Created on | Bisect |
+---+---+++
| 72782 | [945GM bisected] screen blank on S3 resume on | 2013-12-17 | Yes|
| 81537 | [snb dp regression] dp retry forever due to s | 2014-07-19 | No |
| 84855 | [ILK regression]igt kms_rotation_crc/sprite-r | 2014-10-10 | No |
| 84974 | [VLV eDP-LVDS bisected] powerdomains: Screen  | 2014-10-14 | Yes|
| 87131 | [PNV regression] igt/gem_exec_lut_handle take | 2014-12-09 | No |
| 87480 | [SNB/IVB/HSW/BYT bisected]igt/kms_force_conne | 2014-12-19 | Yes|
| 87662 | [ALL 3.18 Bisected] DVI --rotation inverted c | 2014-12-24 | Yes|
| 87725 | [BDW Bisected] OglBatch7 performance reduced  | 2014-12-26 | Yes|
| 87726 | [BDW Bisected] OglDrvCtx performance reduced  | 2014-12-26 | Yes|
| 88012 | [bisected BYT] complete freeze after: drm/i91 | 2015-01-04 | Yes|
| 88124 | i915: regression: after DP connected monitor  | 2015-01-06 | No |
| 88325 | screen brightness regression on resume| 2015-01-12 | No |
| 88439 | [BDW Bisected]igt/gem_reloc_vs_gpu/forked-fau | 2015-01-15 | Yes|
| 89334 | [945 regression] 4.0-rc1 kernel GPU hang:  ec | 2015-02-26 | No |
| 89629 | [i965 regression]igt/kms_rotation_crc/sprite- | 2015-03-18 | No |
| 89632 | [i965 regression]igt/kms_universal_plane/univ | 2015-03-18 | No |
| 89728 | [HSW/BDW/BSW/SKL bisected] igt/pm_rps/ subcas | 2015-03-23 | Yes|
| 89872 | [ HSW Bisected ] VGA was white screen when re | 2015-04-02 | Yes|
| 90112 | [BSW bisected] OglGSCloth/Lightsmark/CS/ Port | 2015-04-20 | Yes|
| 90134 | [BSW Bisected]GFXBench3_gl_driver/GFXBench3_g | 2015-04-22 | Yes|
| 90368 | [SNB bisected igt/kms_3d has hardcoded expect | 2015-05-08 | Yes|
| 90394 | [SNB Regression]igt/kms_plane/plane-position- | 2015-05-11 | No |
| 90461 | [SKL Regression]boot system causes WARNING: C | 2015-05-15 | No |
| 90546 | [BDW/BSW/SKL bisected]igt/pm_rpm/drm-resource | 2015-05-21 | Yes|
| 90732 | [BDW/BSW Bisected]igt/gem_reloc_vs_gpu/forked | 2015-05-29 | Yes|
| 90808 | [BDW Bisected]igt/gem_ctx_param_basic/invalid | 2015-06-02 | Yes|
| 90994 | [BDW regression] pm_rpm subtests fail and giv | 2015-06-16 | No |
| 91378 | [hsw dp regression] 06ea66b6 (5.4GHz link clo | 2015-07-17 | No |
| 91592 | [pnv regression] OOPS on boot | 2015-08-09 | No |
| 91844 | [HSW Regression] intel_do_flush_locked failed | 2015-09-02 | No |
| 91952 | [Bisected Regression] Blank screen from boot  | 2015-09-10 | Yes|
| 91959 | [865g 3.19 regression] Desktop image is disto | 2015-09-10 | No |
| 91974 | [bisected] unrecoverable black screen after k | 2015-09-11 | Yes|
| 92050 | [regression]/bug introduced by commit [0e572f | 2015-09-19 | No |
| 92083 | [regression] [git pull] drm for 4.3   | 2015-09-23 | No |
| 92096 | regression/bug introduced by commit [0e572fe7 | 2015-09-24 | No |
| 92097 | [regression] Linux 4.3-rc  i915: WARNING: int | 2015-09-24 | No |
| 92174 | PROBLEM: Intel VGA output busticated on 4.3-r | 2015-09-29 | No |
| 92211 | [All Regression] [IGT Basic] igt/pm_rpm/basic | 2015-10-01 | No |
| 92237 | Horrible noise (audio) via DisplayPort [regre | 2015-10-02 | No |
| 92355 | [SKL Regression] igt/kms_fbc_crc cause DUT cr | 2015-10-09 | No |
| 92414 | [Intel-gfx] As of kernel 4.3-rc1 system will  | 2015-10-10 | Yes|
| 92483 | [regression] Can only go to console (fbcon/fb | 2015-10-15 | No |
| 92502 | [SKL] [Regression] igt/kms_flip/2x-flip-vs-ex | 2015-10-16 | No |
| 92575 | [4.2 regression] Massive graphics corruption  | 2015-10-21 | No |
| 92655 | [i915] LVDS screen half garbled. unable to bi | 2015-10-23 | Yes|
| 92707 | [BSW] [IGT Basic] [Regression] igt / pm_backl | 2015-10-28 | No |
+---+---+++
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Re: [Intel-gfx] [PATCH] drm/i915/bxt: Force port A DDI to use 4 lanes

[Bob Paauwe]

On Thu, 5 Nov 2015 14:53:32 -0800
Matt Roper  wrote:

> The bspec indicates that DDI A using four lanes is the only valid
> configuration for Broxton (Broxton doesn't have a DDI E to split these
> lanes with); the DDI_A_4_LANES bit of port A's DDI_BUF_CTL should always
> be set by the BIOS.  However some BIOS versions seem to only be setting
> this bit if eDP is actually lit up at boot time; if the BIOS doesn't
> turn on the eDP panel because an external display is plugged in, then
> this bit is never properly initialized.  The end result of this is that
> we wind up calculating a lower max data rate than we should and may wind
> up rejecting the native mode for panels that we should be able to drive.
> 
> Let's workaround this BIOS bug by just turning the DDI_A_4_LANES bit on
> in our driver's internal state if we recognize that're running on BXT
> where it should have been on anyway.
> 
> Cc: Imre Deak 
> Cc: Bob Paauwe 
> Signed-off-by: Matt Roper 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 13 +
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index b164122..672b86c 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -3234,6 +3234,19 @@ void intel_ddi_init(struct drm_device *dev, enum port 
> port)
> (DDI_BUF_PORT_REVERSAL |
>  DDI_A_4_LANES);
>  
> + /*
> +  * Bspec says that DDI_A_4_LANES is the only supported configuration
> +  * for Broxton.  Yet some BIOS fail to set this bit on port A if eDP
> +  * wasn't lit up at boot.  Force this bit on in our internal
> +  * configuration so that we use the proper lane count for our
> +  * calculations.
> +  */
> + if (IS_BROXTON(dev) && port == PORT_A)
> + if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
> + DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; 
> fixing\n");
> + intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
> + }

The brace isn't lined up with the proper if.

> +
>   intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
>   intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
>   intel_encoder->cloneable = 0;

With the above formatting fixed.
Reviewed-by: Bob Paauwe 
Tested-by: Bob Paauwe 

-- 
--
Bob Paauwe  
bob.j.paa...@intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193

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Re: [Intel-gfx] [PATCH] drm/i915: get runtime PM reference around GEM set_caching IOCTL

[Imre Deak]

On Fri, 2015-11-06 at 00:57 +0200, Imre Deak wrote:
> On Thu, 2015-11-05 at 11:56 +, Chris Wilson wrote:
> > On Thu, Nov 05, 2015 at 01:28:32PM +0200, Imre Deak wrote:
> > > On ke, 2015-11-04 at 20:57 +, Chris Wilson wrote:
> > > > On Wed, Nov 04, 2015 at 09:25:32PM +0200, Imre Deak wrote:
> > > > > After Damien's D3 fix I started to get runtime suspend residency for 
> > > > > the
> > > > > first time and that revealed a breakage on the set_caching IOCTL path
> > > > > that accesses the HW but doesn't take an RPM ref. Fix this up.
> > > > 
> > > > Why here (and in so many random places) and not around the PTE write
> > > > itself?
> > > 
> > > Imo we should take the RPM ref outside of any of our locks. Otherwise we
> > > need hacks like we have currently in the runtime suspend handler to work
> > > around lock inversions. It works now, but we couldn't do the same trick
> > > if we needed to take struct_mutex for example in the resume handler too
> > > for some reason.
> > 
> > On the other hand, it leads to hard to track down bugs and improper
> > documentation. Neither solution is perfect.
> 
> I think I understand the documentation part, not sure how that could be
> solved. Perhaps RPM-held asserts right before the point where the HW
> needs to be on?
> 
> What do you mean by hard to track down bugs? Couldn't that also be
> tackled by asserts?
> 
> > Note since intel_runtime_suspend has ample barriers of its own, you can
> > avoid the struct_mutex if you have a dedicated dev_priv->mm.fault_list.
> > 
> > Something along the lines of:
> 
> Ok, looks interesting. But as you said we would have to then make
> callers of i915_gem_release_mmap() wake up the device, which isn't
> strictly necessary. (and imo as such goes somewhat against the
> documentation argument)

Actually, we could also use pm_runtime_get_noresume(). But I find this
would just complicate things without a real benefit.

> --Imre
> 
> 
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 86734be..fe91ce5 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -180,11 +180,11 @@ describe_obj(struct seq_file *m, struct 
> > drm_i915_gem_object *obj)
> > }
> > if (obj->stolen)
> > seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
> > -   if (obj->pin_display || obj->fault_mappable) {
> > +   if (obj->pin_display || !list_empty(>fault_link)) {
> > char s[3], *t = s;
> > if (obj->pin_display)
> > *t++ = 'p';
> > -   if (obj->fault_mappable)
> > +   if (!list_empty(>fault_link))
> > *t++ = 'f';
> > *t = '\0';
> > seq_printf(m, " (%s mappable)", s);
> > @@ -474,7 +474,7 @@ static int i915_gem_object_info(struct seq_file *m, 
> > void* data)
> >  
> > size = count = mappable_size = mappable_count = 0;
> > list_for_each_entry(obj, _priv->mm.bound_list, global_list) {
> > -   if (obj->fault_mappable) {
> > +   if (!list_empty(>fault_link)) {
> > size += i915_gem_obj_ggtt_size(obj);
> > ++count;
> > }
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c 
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index 1d88745..179594e 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -1447,28 +1447,10 @@ static int intel_runtime_suspend(struct device 
> > *device)
> > DRM_DEBUG_KMS("Suspending device\n");
> >  
> > /*
> > -* We could deadlock here in case another thread holding 
> > struct_mutex
> > -* calls RPM suspend concurrently, since the RPM suspend will wait
> > -* first for this RPM suspend to finish. In this case the concurrent
> > -* RPM resume will be followed by its RPM suspend counterpart. Still
> > -* for consistency return -EAGAIN, which will reschedule this 
> > suspend.
> > -*/
> > -   if (!mutex_trylock(>struct_mutex)) {
> > -   DRM_DEBUG_KMS("device lock contention, deffering 
> > suspend\n");
> > -   /*
> > -* Bump the expiration timestamp, otherwise the suspend 
> > won't
> > -* be rescheduled.
> > -*/
> > -   pm_runtime_mark_last_busy(device);
> > -
> > -   return -EAGAIN;
> > -   }
> > -   /*
> >  * We are safe here against re-faults, since the fault handler takes
> >  * an RPM reference.
> >  */
> > i915_gem_release_all_mmaps(dev_priv);
> > -   mutex_unlock(>struct_mutex);
> >  
> > intel_suspend_gt_powersave(dev);
> > intel_runtime_pm_disable_interrupts(dev_priv);
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h 
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 55611d8..5e4904a 100644
> > 

Re: [Intel-gfx] [PATCH] drm/i915: get runtime PM reference around GEM set_caching IOCTL

[Imre Deak]

On Thu, 2015-11-05 at 11:56 +, Chris Wilson wrote:
> On Thu, Nov 05, 2015 at 01:28:32PM +0200, Imre Deak wrote:
> > On ke, 2015-11-04 at 20:57 +, Chris Wilson wrote:
> > > On Wed, Nov 04, 2015 at 09:25:32PM +0200, Imre Deak wrote:
> > > > After Damien's D3 fix I started to get runtime suspend residency for the
> > > > first time and that revealed a breakage on the set_caching IOCTL path
> > > > that accesses the HW but doesn't take an RPM ref. Fix this up.
> > > 
> > > Why here (and in so many random places) and not around the PTE write
> > > itself?
> > 
> > Imo we should take the RPM ref outside of any of our locks. Otherwise we
> > need hacks like we have currently in the runtime suspend handler to work
> > around lock inversions. It works now, but we couldn't do the same trick
> > if we needed to take struct_mutex for example in the resume handler too
> > for some reason.
> 
> On the other hand, it leads to hard to track down bugs and improper
> documentation. Neither solution is perfect.

I think I understand the documentation part, not sure how that could be
solved. Perhaps RPM-held asserts right before the point where the HW
needs to be on?

What do you mean by hard to track down bugs? Couldn't that also be
tackled by asserts?

> Note since intel_runtime_suspend has ample barriers of its own, you can
> avoid the struct_mutex if you have a dedicated dev_priv->mm.fault_list.
> 
> Something along the lines of:

Ok, looks interesting. But as you said we would have to then make
callers of i915_gem_release_mmap() wake up the device, which isn't
strictly necessary. (and imo as such goes somewhat against the
documentation argument)

--Imre


> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 86734be..fe91ce5 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -180,11 +180,11 @@ describe_obj(struct seq_file *m, struct 
> drm_i915_gem_object *obj)
> }
> if (obj->stolen)
> seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
> -   if (obj->pin_display || obj->fault_mappable) {
> +   if (obj->pin_display || !list_empty(>fault_link)) {
> char s[3], *t = s;
> if (obj->pin_display)
> *t++ = 'p';
> -   if (obj->fault_mappable)
> +   if (!list_empty(>fault_link))
> *t++ = 'f';
> *t = '\0';
> seq_printf(m, " (%s mappable)", s);
> @@ -474,7 +474,7 @@ static int i915_gem_object_info(struct seq_file *m, void* 
> data)
>  
> size = count = mappable_size = mappable_count = 0;
> list_for_each_entry(obj, _priv->mm.bound_list, global_list) {
> -   if (obj->fault_mappable) {
> +   if (!list_empty(>fault_link)) {
> size += i915_gem_obj_ggtt_size(obj);
> ++count;
> }
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 1d88745..179594e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1447,28 +1447,10 @@ static int intel_runtime_suspend(struct device 
> *device)
> DRM_DEBUG_KMS("Suspending device\n");
>  
> /*
> -* We could deadlock here in case another thread holding struct_mutex
> -* calls RPM suspend concurrently, since the RPM suspend will wait
> -* first for this RPM suspend to finish. In this case the concurrent
> -* RPM resume will be followed by its RPM suspend counterpart. Still
> -* for consistency return -EAGAIN, which will reschedule this suspend.
> -*/
> -   if (!mutex_trylock(>struct_mutex)) {
> -   DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
> -   /*
> -* Bump the expiration timestamp, otherwise the suspend won't
> -* be rescheduled.
> -*/
> -   pm_runtime_mark_last_busy(device);
> -
> -   return -EAGAIN;
> -   }
> -   /*
>  * We are safe here against re-faults, since the fault handler takes
>  * an RPM reference.
>  */
> i915_gem_release_all_mmaps(dev_priv);
> -   mutex_unlock(>struct_mutex);
>  
> intel_suspend_gt_powersave(dev);
> intel_runtime_pm_disable_interrupts(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 55611d8..5e4904a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1268,6 +1268,8 @@ struct i915_gem_mm {
>  */
> struct list_head unbound_list;
>  
> +   struct list_head fault_list;
> +
> /** Usable portion of the GTT for GEM */
> unsigned long stolen_base; /* limited to low memory (32-bit) */
>  
> @@ -2025,6 +2027,8 @@ struct drm_i915_gem_object {
>  
> struct 

Re: [Intel-gfx] [PATCH i-g-t 4/8] kms_frontbuffer_tracking: Allow to skip suspend_resume sub test case.

[Ville Syrjälä]

On Thu, Nov 05, 2015 at 06:34:07PM -0200, Paulo Zanoni wrote:
> 2015-11-05 16:53 GMT-02:00 Rodrigo Vivi :
> > There are few platforms with other suspend resume bugs that breaks
> > the full execution. So let's provide a way to skip suspend resume case.
> 
> Well, I carry a local patch that completely disables suspend subtests
> for the tests that I usually run, so I really understand your pain.
> Suspend subtests take a long time to run, and they usually don't work
> on some of the preproduction machines I still use.
> 
> But since this problem is not specific to kms_frontbuffer_tracking,
> maybe we could adopt an igt-wide solution here? Thomas, any idea here?

-x suspend is what I tell piglit on one hsw I have here which hangs on s3.

> 
> >
> > Signed-off-by: Rodrigo Vivi 
> > ---
> >  tests/kms_frontbuffer_tracking.c | 9 +
> >  1 file changed, 9 insertions(+)
> >
> > diff --git a/tests/kms_frontbuffer_tracking.c 
> > b/tests/kms_frontbuffer_tracking.c
> > index d879493..1cc1c9e 100644
> > --- a/tests/kms_frontbuffer_tracking.c
> > +++ b/tests/kms_frontbuffer_tracking.c
> > @@ -237,6 +237,7 @@ struct {
> > bool fbc_check_compression;
> > bool fbc_check_last_action;
> > bool no_edp;
> > +   bool no_suspend;
> > bool small_modes;
> > bool show_hidden;
> > int step;
> > @@ -250,6 +251,7 @@ struct {
> > .fbc_check_compression = true,
> > .fbc_check_last_action = true,
> > .no_edp = false,
> > +   .no_suspend = false,
> > .small_modes = false,
> > .show_hidden= false,
> > .step = 0,
> > @@ -2735,6 +2737,8 @@ static void suspend_subtest(const struct test_mode *t)
> >  {
> > struct modeset_params *params = pick_params(t);
> >
> > +   igt_skip_on(opt.no_suspend);
> > +
> > prepare_subtest(t, NULL);
> > sleep(5);
> > igt_system_suspend_autoresume();
> > @@ -2950,6 +2954,9 @@ static int opt_handler(int option, int option_index, 
> > void *data)
> > case 'e':
> > opt.no_edp = true;
> > break;
> > +   case 'r':
> > +   opt.no_suspend = true;
> > +   break;
> > case 'm':
> > opt.small_modes = true;
> > break;
> > @@ -2992,6 +2999,7 @@ const char *help_str =
> >  "  --no-fbc-compression-check  Don't check for the FBC compression 
> > status\n"
> >  "  --no-fbc-action-check   Don't check for the FBC last action\n"
> >  "  --no-edpDon't use eDP monitors\n"
> > +"  --no-suspendDon't run Suspend/Resume test cases\n"
> >  "  --use-small-modes   Use smaller resolutions for the modes\n"
> >  "  --show-hidden   Show hidden subtests\n"
> >  "  --step  Stop on each step so you can check the 
> > screen\n"
> > @@ -3117,6 +3125,7 @@ int main(int argc, char *argv[])
> > { "no-fbc-compression-check", 0, 0, 'o'},
> > { "no-fbc-action-check",  0, 0, 'a'},
> > { "no-edp",   0, 0, 'e'},
> > +   { "no-suspend",   0, 0, 'r'},
> > { "use-small-modes",  0, 0, 'm'},
> > { "show-hidden",  0, 0, 'i'},
> > { "step", 0, 0, 't'},
> > --
> > 2.4.3
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Paulo Zanoni
> ___
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] [PATCH] drm/i915/bxt: Force port A DDI to use 4 lanes

[Matt Roper]

The bspec indicates that DDI A using four lanes is the only valid
configuration for Broxton (Broxton doesn't have a DDI E to split these
lanes with); the DDI_A_4_LANES bit of port A's DDI_BUF_CTL should always
be set by the BIOS.  However some BIOS versions seem to only be setting
this bit if eDP is actually lit up at boot time; if the BIOS doesn't
turn on the eDP panel because an external display is plugged in, then
this bit is never properly initialized.  The end result of this is that
we wind up calculating a lower max data rate than we should and may wind
up rejecting the native mode for panels that we should be able to drive.

Let's workaround this BIOS bug by just turning the DDI_A_4_LANES bit on
in our driver's internal state if we recognize that're running on BXT
where it should have been on anyway.

Cc: Imre Deak 
Cc: Bob Paauwe 
Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/intel_ddi.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index b164122..672b86c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3234,6 +3234,19 @@ void intel_ddi_init(struct drm_device *dev, enum port 
port)
  (DDI_BUF_PORT_REVERSAL |
   DDI_A_4_LANES);
 
+   /*
+* Bspec says that DDI_A_4_LANES is the only supported configuration
+* for Broxton.  Yet some BIOS fail to set this bit on port A if eDP
+* wasn't lit up at boot.  Force this bit on in our internal
+* configuration so that we use the proper lane count for our
+* calculations.
+*/
+   if (IS_BROXTON(dev) && port == PORT_A)
+   if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
+   DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; 
fixing\n");
+   intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
+   }
+
intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
intel_encoder->cloneable = 0;
-- 
2.1.4

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Re: [Intel-gfx] [PATCH i-g-t 2/8] kms_frontbuffer_tracking: Skip on unreliable CRC.

[Paulo Zanoni]

2015-11-05 16:53 GMT-02:00 Rodrigo Vivi :
> Even with all sink crc re-works we still have platforms
> where after 6 vblanks it is unable to calculate the
> sink crc. But if we don't get the sink crc it isn't true
> that test failed, but that we have no ways to say test
> passed or failed.
>
> So let's print a message and move forward in case sink crc
> cannot help us to know if the screen has been updated.

As much as I understand your reasoning here, "Try running this test
again" will be ignored by our future bots.

Instead of just skipping, isn't there something else we could do, such
as trying again 10 times? 60 frames doesn't seem expensive. If it
works at least sometimes, I'd say it's worth the try.

Besides, did we try the AUX_MUTEX register that was suggested here:
http://patchwork.freedesktop.org/patch/57693/ ? Maybe it would solve
all our sink CRCs problem.

Another comment: FBC doesn't really need sink CRC, but it's currently
checking sink CRC, so it may get SKIPs. Maybe instead of a SKIP for
failed sink CRC on FBC we could just ignore and move on? Maybe we
could pass some flags to collect_crcs() so it can know if sink CRCs
are ignorable.

Another problem is: what if we fail while getting the reference CRC?
We will leave garbage inside crc->data, and the other tests will
compare themselves against the garbage in case reading sink CRCs end
up working for them, so we'll have test failures that are not real
failures. Maybe we should pass some flag to collect_crtcs() signaling
that we're trying a reference CRC, so it can write something to
crtc->data, just like we have the "unsupported!" string. Then we'd
have to check this special string later.

You also probably need to fix setup_sink_crc(), because it currently
doesn't check for ETIMETDOUT.

I'm not blocking the patch, just starting the discussion :)

>
> Signed-off-by: Rodrigo Vivi 
> ---
>  tests/kms_frontbuffer_tracking.c | 11 +--
>  1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/tests/kms_frontbuffer_tracking.c 
> b/tests/kms_frontbuffer_tracking.c
> index cd2879d..606d0a9 100644
> --- a/tests/kms_frontbuffer_tracking.c
> +++ b/tests/kms_frontbuffer_tracking.c
> @@ -858,10 +858,17 @@ static bool psr_wait_until_enabled(void)
>
>  static void get_sink_crc(sink_crc_t *crc)
>  {
> +   int rc, errno_;
> +
> lseek(sink_crc.fd, 0, SEEK_SET);
>
> -   igt_assert(read(sink_crc.fd, crc->data, SINK_CRC_SIZE) ==
> -  SINK_CRC_SIZE);
> +   rc = read(sink_crc.fd, crc->data, SINK_CRC_SIZE);
> +   errno_ = errno;
> +
> +   if (rc == -1 && errno_ == ETIMEDOUT)
> +   igt_skip("Sink CRC is unreliable on this machine. Try running 
> this test again individually\n");
> +
> +   igt_assert(rc == SINK_CRC_SIZE);
>  }
>
>  static bool sink_crc_equal(sink_crc_t *a, sink_crc_t *b)
> --
> 2.4.3
>
> ___
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni
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Re: [Intel-gfx] [PATCH i-g-t 5/8] kms_frontbuffer_tracking: Add option to allow running tescases with PSR disabled.

[Paulo Zanoni]

2015-11-05 16:53 GMT-02:00 Rodrigo Vivi :
> We need to be able to identify if the issue is feature related
> or caused by another bug.
>
> Also this feature allow users to have a visual feedback of what to
> expect when running the test case for real.

We currently have --no-status-check that can be used when you don't
want the enable/disable checks.

We also have the "nop" subtests that appear when you use --show-hidden
(I don't want to waste QA's time with these since they're just for
debugging purposes, that's why they are hidden). So if you want to
debug, for example, subtest psr-1p-primscrn-pri-indfb-draw-mmap-cpu,
you can just run:

sudo ./kms_frontbuffer_tracking --show-hidden --run-subtest
nop-1p-primscrn-pri-indfb-draw-mmap-cpu

(notice that there's a patch on the list proposing to replace the
--show-hidden with --all)

Do any of the solutions above solve the problem that made you write
this patch and patch 6? If not, why?

>
> Signed-off-by: Rodrigo Vivi 
> ---
>  tests/kms_frontbuffer_tracking.c | 18 +++---
>  1 file changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/tests/kms_frontbuffer_tracking.c 
> b/tests/kms_frontbuffer_tracking.c
> index 1cc1c9e..312c08e 100644
> --- a/tests/kms_frontbuffer_tracking.c
> +++ b/tests/kms_frontbuffer_tracking.c
> @@ -238,6 +238,7 @@ struct {
> bool fbc_check_last_action;
> bool no_edp;
> bool no_suspend;
> +   bool psr_disabled;
> bool small_modes;
> bool show_hidden;
> int step;
> @@ -252,6 +253,7 @@ struct {
> .fbc_check_last_action = true,
> .no_edp = false,
> .no_suspend = false,
> +   .psr_disabled = false,
> .small_modes = false,
> .show_hidden= false,
> .step = 0,
> @@ -1617,7 +1619,7 @@ static int adjust_assertion_flags(const struct 
> test_mode *t, int flags)
> }   \
> \
> if (flags_ & ASSERT_PSR_ENABLED) {  \
> -   if (!psr_wait_until_enabled()) {\
> +   if (!opt.psr_disabled && !psr_wait_until_enabled()) {   \
> psr_print_status(); \
> igt_assert_f(false, "PSR disabled\n");  \
> }   \
> @@ -1717,8 +1719,13 @@ static void enable_features_for_test(const struct 
> test_mode *t)
>  {
> if (t->feature & FEATURE_FBC)
> fbc_enable();
> -   if (t->feature & FEATURE_PSR)
> -   psr_enable();
> +   if (t->feature & FEATURE_PSR) {
> +   if (opt.psr_disabled) {
> +   igt_info("WARNING: Running with PSR disabled\n");
> +   psr_disable();
> +   } else
> +   psr_enable();
> +   }
>  }
>
>  static void check_test_requirements(const struct test_mode *t)
> @@ -2957,6 +2964,9 @@ static int opt_handler(int option, int option_index, 
> void *data)
> case 'r':
> opt.no_suspend = true;
> break;
> +   case 'R':
> +   opt.psr_disabled = true;
> +   break;
> case 'm':
> opt.small_modes = true;
> break;
> @@ -3000,6 +3010,7 @@ const char *help_str =
>  "  --no-fbc-action-check   Don't check for the FBC last action\n"
>  "  --no-edpDon't use eDP monitors\n"
>  "  --no-suspendDon't run Suspend/Resume test cases\n"
> +"  --psr-disabled  Dry-run. Run tests with PSR feature 
> disabled.\n"
>  "  --use-small-modes   Use smaller resolutions for the modes\n"
>  "  --show-hidden   Show hidden subtests\n"
>  "  --step  Stop on each step so you can check the 
> screen\n"
> @@ -3126,6 +3137,7 @@ int main(int argc, char *argv[])
> { "no-fbc-action-check",  0, 0, 'a'},
> { "no-edp",   0, 0, 'e'},
> { "no-suspend",   0, 0, 'r'},
> +   { "psr-disabled", 0, 0, 'R'},
> { "use-small-modes",  0, 0, 'm'},
> { "show-hidden",  0, 0, 'i'},
> { "step", 0, 0, 't'},
> --
> 2.4.3
>
> ___
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
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