[Intel-gfx] [lkp-robot] [lib/rbtree, drm/mm] 3e6e51217d: WARNING:at_lib/stackdepot.c:#depot_save_stack
FYI, we noticed the following commit (built with gcc-7):
commit: 3e6e51217dd14dcda10d4bc9a38b1440e2d42c14 ("lib/rbtree,drm/mm: Add
rbtree_replace_node_cached()")
git://anongit.freedesktop.org/drm-intel topic/core-for-CI
in testcase: trinity
with following parameters:
runtime: 300s
test-description: Trinity is a linux system call fuzz tester.
test-url: http://codemonkey.org.uk/projects/trinity/
on test machine: qemu-system-x86_64 -enable-kvm -m 512M
caused below changes (please refer to attached dmesg/kmsg for entire
log/backtrace):
+---+++
| | 978de04a3c | 3e6e51217d |
+---+++
| boot_successes| 46 | 0 |
| boot_failures | 0 | 8 |
| WARNING:at_lib/stackdepot.c:#depot_save_stack | 0 | 8 |
| RIP:depot_save_stack | 0 | 8 |
| BUG:kernel_hang_in_test_stage | 0 | 4 |
+---+++
[ 278.198833] WARNING: CPU: 0 PID: 1 at lib/stackdepot.c:119
depot_save_stack+0x22e/0x353
[ 278.10] CPU: 0 PID: 1 Comm: swapper Not tainted
4.15.0-rc2-5-g3e6e512 #1
[ 278.10] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS
1.10.2-1 04/01/2014
[ 278.10] task: 9f2da405 task.stack: 18ee505d
[ 278.10] RIP: 0010:depot_save_stack+0x22e/0x353
[ 278.10] RSP: :88001f5bb9d8 EFLAGS: 00010086
[ 278.10] RAX: 0022 RBX: ae4fc5be RCX: 88001f5a8000
[ 278.10] RDX: 00221f5a8000 RSI: 810eb77c RDI: 0093
[ 278.10] RBP: 0020 R08: e272d5c3 R09: 0004
[ 278.10] R10: R11: 65e7cb07 R12: 000fc5be
[ 278.10] R13: 88001f5bba30 R14: R15: 0286
[ 278.10] FS: () GS:81e36000()
knlGS:
[ 278.10] CS: 0010 DS: ES: CR0: 80050033
[ 278.10] CR2: CR3: 01e11000 CR4: 06b0
[ 278.10] Call Trace:
[ 278.10] ? save_stack+0x7c/0x89
[ 278.10] ? drm_mm_interval_tree_add_node+0xf6/0x137
[ 278.10] ? drm_mm_interval_tree_add_node+0xf6/0x137
[ 278.10] ? add_hole+0x12d/0x155
[ 278.10] ? add_hole+0x12d/0x155
[ 278.10] ? drm_mm_interval_tree_add_node+0xf6/0x137
[ 278.10] ? add_hole+0x12d/0x155
[ 278.10] ? drm_mm_interval_tree_compute_subtree_last+0x54/0x5c
[ 278.10] ? drm_mm_interval_tree_augment_copy+0x18/0x18
[ 278.10] ? add_hole+0x12d/0x155
[ 278.10] ? drm_mm_reserve_node+0x13f/0x155
[ 278.10] ? evict_something+0x244/0x2d1
[ 278.10] ? drm_mm_interval_tree_add_node+0xf6/0x137
[ 278.10] ? drm_mm_interval_tree_compute_subtree_last+0x54/0x5c
[ 278.10] ? drm_mm_interval_tree_augment_copy+0x18/0x18
[ 278.10] ? add_hole+0x12d/0x155
[ 278.10] ? drm_mm_reserve_node+0x13f/0x155
[ 278.10] ? drm_mm_interval_tree_compute_subtree_last+0x54/0x5c
[ 278.10] ? drm_mm_interval_tree_augment_copy+0x18/0x18
[ 278.10] ? drm_mm_interval_tree_augment_rotate+0x23/0x2a
[ 278.10] ? drm_mm_interval_tree_compute_subtree_last+0x54/0x5c
[ 278.10] ? rb_erase+0x146/0x270
[ 278.10] ? drm_mm_interval_tree_add_node+0xf6/0x137
[ 278.10] ? add_hole+0x12d/0x155
[ 278.10] ? drm_mm_interval_tree_add_node+0xf6/0x137
[ 278.10] ? drm_mm_interval_tree_add_node+0xf6/0x137
[ 278.10] ? add_hole+0x12d/0x155
[ 278.10] ? drm_mm_reserve_node+0x13f/0x155
[ 278.10] ? evict_something+0x244/0x2d1
[ 278.10] ? igt_evict+0x63d/0x75f
[ 278.10] ? test_drm_mm_init+0xb5/0x111
[ 278.10] ? drm_fb_helper_modinit+0xd/0xd
[ 278.10] ? do_early_param+0xbe/0xbe
[ 278.10] ? drm_mm_reserve_node+0x13f/0x155
[ 278.10] ? evict_something+0x244/0x2d1
[ 278.10] ? igt_evict+0x63d/0x75f
[ 278.10] ? test_drm_mm_init+0xb5/0x111
[ 278.10] ? drm_fb_helper_modinit+0xd/0xd
[ 278.10] ? do_early_param+0xbe/0xbe
[ 278.10] ? do_one_initcall+0x9d/0x158
[ 278.10] ? do_early_param+0xbe/0xbe
[ 278.10] ? do_early_param+0xbe/0xbe
[ 278.10] ? kernel_init_freeable+0x11c/0x1cc
[ 278.10] ? rest_init+0xbb/0xbb
[ 278.10] ? kernel_init+0x10/0x13d
[ 278.10] ? rest_init+0xbb/0xbb
[ 278.10] ? ret_from_fork+0x24/0x30
[ 278.10] Code: 8d 50 01 81 fa ff 1f 00 00 7e 27 80 3d 52 04 c0 00 00 0f
85 fd 00 00 00 48 c7 c7 e2 9e d0 81 c6 05 3e 04 c0 00 01 e8 f1 53 d7 ff <0f> ff
e9 e3 00 00 00 83 c0 02 89 15 64 7c 6d 01 48 c7 05 4d 7c
[ 278.10] ---[ end trace 4dd271b4182c6be2 ]---
To reproduce:
git clon
[Intel-gfx] ✓ Fi.CI.BAT: success for overlay: fix debugfs path when debugfs mounted on path '/debug'
== Series Details == Series: overlay: fix debugfs path when debugfs mounted on path '/debug' URL : https://patchwork.freedesktop.org/series/35012/ State : success == Summary == IGT patchset tested on top of latest successful build 1db12466cb5ad8483cd469753d2e312a62d717b7 meson: build a full dependency for lib_igt_perf with latest DRM-Tip kernel build CI_DRM_3468 95f37eb3ebfd drm-tip: 2017y-12m-06d-21h-01m-04s UTC integration manifest No testlist changes. Test debugfs_test: Subgroup read_all_entries: dmesg-fail -> DMESG-WARN (fi-elk-e7500) fdo#103989 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: pass -> INCOMPLETE (fi-snb-2520m) fdo#103713 fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:442s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:386s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:525s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:284s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:509s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:511s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:492s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:475s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:269s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:537s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:387s fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:262s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:481s fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:444s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:525s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:480s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:534s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:591s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:462s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:547s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:571s fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:524s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:499s fi-snb-2520m total:245 pass:211 dwarn:0 dfail:0 fail:0 skip:33 fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:430s Blacklisted hosts: fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:626s fi-glk-dsi total:101 pass:58 dwarn:0 dfail:1 fail:0 skip:41 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_608/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 0/9] drm/i915: Implement HDCP
Sean, Could you please share the level of functional testing is done on this code? like with Receiver/Repeaters and port type tested (DP/HDMI/DP over USB TypeC ?) Whether Compliance test is attempted on this code? Thanks -Ram On Thursday 07 December 2017 05:30 AM, Sean Paul wrote: Welcome to version 4 of the patchset. I think we're nearing the finish line (hopefully) now. This set addresses the review feedback from v3. I applied some R-b's from v3 review, and converted others to Cc since other changes were made to the patch, and I didn't want to speak for reviewers. Thanks for all the review feedback! Sean Sean Paul (9): drm: Fix link-status kerneldoc line lengths drm/i915: Add more control to wait_for routines drm: Add Content Protection property drm: Add some HDCP related #defines drm/i915: Add HDCP framework + base implementation drm/i915: Make use of indexed write GMBUS feature drm/i915: Add function to output Aksv over GMBUS drm/i915: Implement HDCP for HDMI drm/i915: Implement HDCP for DisplayPort drivers/gpu/drm/drm_atomic.c | 8 + drivers/gpu/drm/drm_connector.c | 87 - drivers/gpu/drm/drm_sysfs.c | 1 + drivers/gpu/drm/i915/Makefile| 1 + drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 85 drivers/gpu/drm/i915/intel_atomic.c | 2 + drivers/gpu/drm/i915/intel_ddi.c | 36 ++ drivers/gpu/drm/i915/intel_display.c | 4 + drivers/gpu/drm/i915/intel_dp.c | 244 +++- drivers/gpu/drm/i915/intel_drv.h | 106 - drivers/gpu/drm/i915/intel_hdcp.c| 735 +++ drivers/gpu/drm/i915/intel_hdmi.c| 250 drivers/gpu/drm/i915/intel_i2c.c | 81 +++- drivers/gpu/drm/i915/intel_uncore.c | 23 +- drivers/gpu/drm/i915/intel_uncore.h | 14 +- include/drm/drm_connector.h | 16 + include/drm/drm_dp_helper.h | 17 + include/drm/drm_hdcp.h | 56 +++ include/uapi/drm/drm_mode.h | 4 + 20 files changed, 1728 insertions(+), 43 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_hdcp.c create mode 100644 include/drm/drm_hdcp.h ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 5/9] drm/i915: Add HDCP framework + base implementation
As v3 implementation removes the mode set from the path of HDCP state
change,
IMO that would have been preferred until we have the ville's changes
mentioned by daniel.
Now once again modeset is brought back :(
And have we already thought about holding the modeset lock for 5+ Sec
for HDCP authentication completion?
we might want to move the hdcp authentication itself to a deferred work,
just to return the atomic_commit_tail call soon...
Of course even if this change is preferred, can be planned for phase2 too...
With this change looks good to me.
Reviewed-by: Ramalingam C
--Ram
On Thursday 07 December 2017 05:30 AM, Sean Paul wrote:
This patch adds the framework required to add HDCP support to intel
connectors. It implements Aksv loading from fuse, and parts 1/2/3
of the HDCP authentication scheme.
Note that without shim implementations, this does not actually implement
HDCP. That will come in subsequent patches.
Changes in v2:
- Don't open code wait_fors (Chris)
- drm_hdcp.c under MIT license (Daniel)
- Move intel_hdcp_disable() call above ddi_disable (Ram)
- Fix // comments (I wore a cone of shame for 12 hours to atone) (Daniel)
- Justify intel_hdcp_shim with comments (Daniel)
- Fixed async locking issues by adding hdcp_mutex (Daniel)
- Don't alter connector_state in enable/disable (Daniel)
Changes in v3:
- Added hdcp_mutex/hdcp_value to make async reasonable
- Added hdcp_prop_work to separate link checking & property setting
- Added new helper for atomic_check state tracking (Daniel)
- Moved enable/disable into atomic_commit with matching helpers
- Moved intel_hdcp_check_link out of all locks when called from dp
- Bumped up ksv_fifo timeout (noticed failure on one of my dongles)
Changes in v4:
- Remove SKL_ prefix from most register names (Daniel)
- Move enable/disable back to modeset path (Daniel)
- s/get_random_long/get_random_u32/ (Daniel)
- Remove mode_config.mutex lock in prop_work (Daniel)
- Add intel_hdcp_init to handle init of conn components (Daniel)
- Actually check return value of attach_property
- Check Bksv is valid before trying to authenticate (Ram)
Cc: Chris Wilson
Cc: Ramalingam C
Reviewed-by: Daniel Vetter
Signed-off-by: Sean Paul
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/i915_reg.h | 83
drivers/gpu/drm/i915/intel_atomic.c | 2 +
drivers/gpu/drm/i915/intel_ddi.c | 7 +
drivers/gpu/drm/i915/intel_display.c | 4 +
drivers/gpu/drm/i915/intel_drv.h | 85
drivers/gpu/drm/i915/intel_hdcp.c| 735 +++
7 files changed, 917 insertions(+)
create mode 100644 drivers/gpu/drm/i915/intel_hdcp.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 42bc8bd4ff06..3facea4eefdb 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -107,6 +107,7 @@ i915-y += intel_audio.o \
intel_fbc.o \
intel_fifo_underrun.o \
intel_frontbuffer.o \
+ intel_hdcp.o \
intel_hotplug.o \
intel_modes.o \
intel_overlay.o \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 09bf043c1c2e..4d66651219e3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8034,6 +8034,7 @@ enum {
#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
+#define SKL_PCODE_LOAD_HDCP_KEYS 0x5
#define SKL_PCODE_CDCLK_CONTROL 0x7
#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
#define SKL_CDCLK_READY_FOR_CHANGE0x1
@@ -8335,6 +8336,88 @@ enum skl_power_gate {
#define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1)
#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
+
+/* HDCP Key Registers */
+#define HDCP_KEY_CONF _MMIO(0x66c00)
+#define HDCP_AKSV_SEND_TRIGGERBIT(31)
+#define HDCP_CLEAR_KEYS_TRIGGER BIT(30)
+#define HDCP_KEY_STATUS_MMIO(0x66c04)
+#define HDCP_FUSE_IN_PROGRESS BIT(7)
+#define HDCP_FUSE_ERROR BIT(6)
+#define HDCP_FUSE_DONEBIT(5)
+#define HDCP_KEY_LOAD_STATUS BIT(1)
+#define HDCP_KEY_LOAD_DONEBIT(0)
+#define HDCP_AKSV_LO _MMIO(0x66c10)
+#define HDCP_AKSV_HI _MMIO(0x66c14)
+
+/* HDCP Repeater Registers */
+#define HDCP_REP_CTL _MMIO(0x66d00)
+#define HDCP_DDIB_REP_PRESENT BIT(30)
+#define HDCP_DDIA_REP_PRESENT BIT(29)
+#define HDCP_DDIC_REP_PRESENT BIT(28)
+#define HDCP_DDID_REP_PRESENT BIT(27)
+#define HDCP_DDIF_REP_PRESENT BIT(26)
+#define HDCP_DDIE_REP_PRESENT BIT(25)
+#define HDCP_DDIB_SHA1_M0 (1 << 20)
+#define HDCP_DDIA_SHA1_M0 (2 << 20)
+#define HDCP_DDIC_SHA1_M0 (3 << 20)
+#define HDCP_DDID_SHA1_M0 (4 << 20)
+#define HDCP_DDIF_SHA1_M0
Re: [Intel-gfx] [PATCH v4 4/9] drm: Add some HDCP related #defines
Looks Good to me. Reviewed-by: Ramalingam C -Ram On Thursday 07 December 2017 05:30 AM, Sean Paul wrote: In preparation for implementing HDCP in i915, add some HDCP related register offsets and defines. The dpcd register offsets will go in drm_dp_helper.h whereas the ddc offsets along with generic HDCP stuff will get stuffed in drm_hdcp.h, which is new. Changes in v2: - drm_hdcp.h gets MIT license (Daniel) Changes in v3: - None Changes in v4: - None Cc: Daniel Vetter Signed-off-by: Sean Paul --- include/drm/drm_dp_helper.h | 17 ++ include/drm/drm_hdcp.h | 56 + 2 files changed, 73 insertions(+) create mode 100644 include/drm/drm_hdcp.h diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 8b9ac321c3bd..4b2640d54c70 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -815,6 +815,23 @@ #define DP_CEC_TX_MESSAGE_BUFFER 0x3020 #define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10 +#define DP_AUX_HDCP_BKSV 0x68000 +#define DP_AUX_HDCP_RI_PRIME 0x68005 +#define DP_AUX_HDCP_AKSV 0x68007 +#define DP_AUX_HDCP_AN 0x6800C +#define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4) +#define DP_AUX_HDCP_BCAPS 0x68028 +# define DP_BCAPS_REPEATER_PRESENT BIT(1) +# define DP_BCAPS_HDCP_CAPABLE BIT(0) +#define DP_AUX_HDCP_BSTATUS0x68029 +# define DP_BSTATUS_REAUTH_REQ BIT(3) +# define DP_BSTATUS_LINK_FAILURE BIT(2) +# define DP_BSTATUS_R0_PRIME_READY BIT(1) +# define DP_BSTATUS_READY BIT(0) +#define DP_AUX_HDCP_BINFO 0x6802A +#define DP_AUX_HDCP_KSV_FIFO 0x6802C +#define DP_AUX_HDCP_AINFO 0x6803B + /* DP 1.2 Sideband message defines */ /* peer device type - DP 1.2a Table 2-92 */ #define DP_PEER_DEVICE_NONE 0x0 diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h new file mode 100644 index ..c9b2484240d4 --- /dev/null +++ b/include/drm/drm_hdcp.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2017 Google, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Sean Paul + */ + +#ifndef _DRM_HDCP_H_INCLUDED_ +#define _DRM_HDCP_H_INCLUDED_ + +/* Period of hdcp checks (to ensure we're still authenticated) */ +#define DRM_HDCP_CHECK_PERIOD_MS (128 * 16) + +/* Shared lengths/masks between HDMI/DVI/DisplayPort */ +#define DRM_HDCP_AN_LEN8 +#define DRM_HDCP_BSTATUS_LEN 2 +#define DRM_HDCP_KSV_LEN 5 +#define DRM_HDCP_RI_LEN2 +#define DRM_HDCP_V_PRIME_PART_LEN 4 +#define DRM_HDCP_V_PRIME_NUM_PARTS 5 +#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x3f) + +/* Slave address for the HDCP registers in the receiver */ +#define DRM_HDCP_DDC_ADDR 0x3A + +/* HDCP register offsets for HDMI/DVI devices */ +#define DRM_HDCP_DDC_BKSV 0x00 +#define DRM_HDCP_DDC_RI_PRIME 0x08 +#define DRM_HDCP_DDC_AKSV 0x10 +#define DRM_HDCP_DDC_AN0x18 +#define DRM_HDCP_DDC_V_PRIME(h)(0x20 + h * 4) +#define DRM_HDCP_DDC_BCAPS 0x40 +#define DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT BIT(6) +#define DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY BIT(5) +#define DRM_HDCP_DDC_BSTATUS 0x41 +#define DRM_HDCP_DDC_KSV_FIFO 0x43 + +#endif ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] overlay: fix debugfs path when debugfs mounted on path '/debug'
From: Changbin Du
It mistakenly set debugfs root path to "/debug/dri", so correct it.
Signed-off-by: Changbin Du
---
overlay/debugfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/overlay/debugfs.c b/overlay/debugfs.c
index 9f3e5cc..5516949 100644
--- a/overlay/debugfs.c
+++ b/overlay/debugfs.c
@@ -40,7 +40,7 @@ int debugfs_init(void)
int n;
if (stat("/debug/dri", &st) == 0) {
- path = "/debug/dri";
+ path = "/debug";
goto find_minor;
}
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 8/9] drm/i915: Implement HDCP for HDMI
On Thursday 07 December 2017 05:30 AM, Sean Paul wrote:
This patch adds HDCP support for HDMI connectors by implementing
the intel_hdcp_shim.
Nothing too special, just a bunch of DDC reads/writes.
Changes in v2:
- Rebased on drm-intel-next
Changes in v3:
- Initialize new worker
Changes in v4:
- Remove SKL_ prefix from most register names (Daniel)
- Wrap sanity checks in WARN_ON (Daniel)
- Consolidate the enable/disable functions into one toggle fn
- Use intel_hdcp_init (Daniel)
Cc: Daniel Vetter
Signed-off-by: Sean Paul
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ddi.c | 29 +
drivers/gpu/drm/i915/intel_drv.h | 4 +
drivers/gpu/drm/i915/intel_hdmi.c | 250 ++
4 files changed, 284 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 35bcc6c308f3..8e4e810b81ef 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8450,6 +8450,7 @@ enum skl_power_gate {
#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
+#define TRANS_DDI_HDCP_SIGNALLING (1<<9)
#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC(1<<8)
#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1<<7)
#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1<<6)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ab727f0b2696..f181f5840268 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1615,6 +1615,35 @@ void intel_ddi_disable_transcoder_func(struct
drm_i915_private *dev_priv,
I915_WRITE(reg, val);
}
+int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
+bool enable)
+{
+ struct drm_device *dev = intel_encoder->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum pipe pipe = 0;
+ int ret = 0;
+ uint32_t tmp;
+
+ if (WARN_ON(!intel_display_power_get_if_enabled(dev_priv,
+ intel_encoder->power_domain)))
+ return -ENXIO;
+
+ if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
+ ret = -EIO;
+ goto out;
+ }
+
+ tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
+ if (enable)
+ tmp |= TRANS_DDI_HDCP_SIGNALLING;
+ else
+ tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
+ I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
+out:
+ intel_display_power_put(dev_priv, intel_encoder->power_domain);
+ return ret;
+}
+
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
{
struct drm_device *dev = intel_connector->base.dev;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3351785af867..3a5393866ed2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1379,6 +1379,10 @@ void intel_ddi_compute_min_voltage_level(struct
drm_i915_private *dev_priv,
u32 bxt_signal_levels(struct intel_dp *intel_dp);
uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
+int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
+bool enable);
+int intel_ddi_enable_hdcp_signalling(struct intel_encoder *intel_encoder);
+int intel_ddi_disable_hdcp_signalling(struct intel_encoder *intel_encoder);
Above two declarations are left over!? You might want to remove it..
unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
int plane, unsigned int height);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 9d5e72728475..382fd443fd0d 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -34,6 +34,7 @@
#include
#include
#include
+#include
#include
#include "intel_drv.h"
#include
@@ -873,6 +874,248 @@ void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi
*hdmi, bool enable)
adapter, enable);
}
+static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
+ unsigned int offset, void *buffer, size_t size)
+{
+ struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
+ struct drm_i915_private *dev_priv =
+ intel_dig_port->base.base.dev->dev_private;
+ struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
+ hdmi->ddc_bus);
+ int ret;
+ u8 start = offset & 0xff;
+ struct i2c_msg msgs[] = {
+ {
+ .addr = DRM_HDCP_DDC_ADDR,
+ .flags = 0,
+ .len = 1,
+
Re: [Intel-gfx] [PATCH v4 9/9] drm/i915: Implement HDCP for DisplayPort
Thanks for handling the reauth req from downstream.
you might want to fix the missed single occurance of "//"
On Thursday 07 December 2017 05:30 AM, Sean Paul wrote:
This patch adds HDCP support for DisplayPort connectors by implementing
the intel_hdcp_shim.
Most of this is straightforward read/write from/to DPCD registers. One
thing worth pointing out is the Aksv output bit. It wasn't easily
separable like it's HDMI counterpart, so it's crammed in with the rest
of it.
Changes in v2:
- Moved intel_hdcp_check_link out of intel_dp_check_link and only call
it on short pulse. Since intel_hdcp_check_link does its own locking,
this ensures we don't deadlock when intel_dp_check_link is called
holding connection_mutex.
- Rebased on drm-intel-next
Changes in v3:
- Initialize new worker
Changes in v4:
- Use intel_hdcp_init (Daniel)
- Check for reauth requests in check_link (Ram)
Cc: Daniel Vetter
Cc: Ramalingam C
Signed-off-by: Sean Paul
---
drivers/gpu/drm/i915/intel_dp.c | 244 ++--
1 file changed, 237 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c603d4c903e1..0ec8b23d0332 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -36,7 +36,9 @@
#include
#include
#include
+#include
#include
+#include
#include "intel_drv.h"
#include
#include "i915_drv.h"
@@ -1025,10 +1027,29 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp,
DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
}
+static uint32_t intel_dp_get_aux_send_ctl(struct intel_dp *intel_dp,
+ bool has_aux_irq,
+ int send_bytes,
+ uint32_t aux_clock_divider,
+ bool aksv_write)
+{
+ uint32_t val = 0;
+
+ if (aksv_write) {
+ send_bytes += 5;
+ val |= DP_AUX_CH_CTL_AUX_AKSV_SELECT;
+ }
+
+ return val | intel_dp->get_aux_send_ctl(intel_dp,
+ has_aux_irq,
+ send_bytes,
+ aux_clock_divider);
+}
+
static int
intel_dp_aux_ch(struct intel_dp *intel_dp,
const uint8_t *send, int send_bytes,
- uint8_t *recv, int recv_size)
+ uint8_t *recv, int recv_size, bool aksv_write)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv =
@@ -1088,10 +1109,11 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
}
while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
- u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
- has_aux_irq,
- send_bytes,
- aux_clock_divider);
+ u32 send_ctl = intel_dp_get_aux_send_ctl(intel_dp,
+has_aux_irq,
+send_bytes,
+aux_clock_divider,
+aksv_write);
/* Must try at least 3 times according to DP spec */
for (try = 0; try < 5; try++) {
@@ -1228,7 +1250,8 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct
drm_dp_aux_msg *msg)
if (msg->buffer)
memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
- ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
+ ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize,
+ false);
if (ret > 0) {
msg->reply = rxbuf[0] >> 4;
@@ -1250,7 +1273,8 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
if (WARN_ON(rxsize > 20))
return -E2BIG;
- ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
+ ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize,
+ false);
if (ret > 0) {
msg->reply = rxbuf[0] >> 4;
/*
@@ -4981,6 +5005,203 @@ void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder)
pps_unlock(intel_dp);
}
+static
+int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
+ u8 *an)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
+ uint8_t txbuf[4], rxbuf[2], reply = 0;
+ ssize_t dpcd_ret;
+ int ret;
+
+ /* Output An fir
[Intel-gfx] ✗ Fi.CI.BAT: failure for mmio save restore refine in vgpu switch
== Series Details == Series: mmio save restore refine in vgpu switch URL : https://patchwork.freedesktop.org/series/35011/ State : failure == Summary == CHK include/config/kernel.release CHK include/generated/uapi/linux/version.h CHK include/generated/utsrelease.h CHK include/generated/bounds.h CHK include/generated/timeconst.h CHK include/generated/asm-offsets.h CALLscripts/checksyscalls.sh DESCEND objtool CHK scripts/mod/devicetable-offsets.h CHK include/generated/compile.h CHK kernel/config_data.h CC [M] drivers/gpu/drm/i915/gvt/render.o drivers/gpu/drm/i915/gvt/render.c: In function ‘load_render_mocs’: drivers/gpu/drm/i915/gvt/render.c:178:1: error: no return statement in function returning non-void [-Werror=return-type] } ^ cc1: all warnings being treated as errors scripts/Makefile.build:310: recipe for target 'drivers/gpu/drm/i915/gvt/render.o' failed make[4]: *** [drivers/gpu/drm/i915/gvt/render.o] Error 1 scripts/Makefile.build:569: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:569: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:569: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1012: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] drm/i915/gvt: refine mocs save restore policy
Save and restore the mocs regs of one VM in GVT-g burning too much CPU
utilization. Add LRI command scan to monitor the change of mocs registers,
save the state in vreg, and use delta update policy to restore them.
It can obviously reduce the MMIO r/w count, and improve the performance
of context switch.
Signed-off-by: Weinan Li
---
drivers/gpu/drm/i915/gvt/cmd_parser.c | 19 +++
drivers/gpu/drm/i915/gvt/render.c | 33 ++---
2 files changed, 37 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c
b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 18c4573..be5c519b 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -825,6 +825,21 @@ static int force_nonpriv_reg_handler(struct
parser_exec_state *s,
return 0;
}
+static inline bool is_mocs_mmio(unsigned int offset)
+{
+ return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
+ ((offset >= 0xb020) && (offset <= 0xb0a0));
+}
+
+static int mocs_cmd_reg_handler(struct parser_exec_state *s,
+ unsigned int offset, unsigned int index)
+{
+ if (!is_mocs_mmio(offset))
+ return -EINVAL;
+ vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1);
+ return 0;
+}
+
static int cmd_reg_handler(struct parser_exec_state *s,
unsigned int offset, unsigned int index, char *cmd)
{
@@ -848,6 +863,10 @@ static int cmd_reg_handler(struct parser_exec_state *s,
return 0;
}
+ if (is_mocs_mmio(offset) &&
+ mocs_cmd_reg_handler(s, offset, index))
+ return -EINVAL;
+
if (is_force_nonpriv_mmio(offset) &&
force_nonpriv_reg_handler(s, offset, index))
return -EPERM;
diff --git a/drivers/gpu/drm/i915/gvt/render.c
b/drivers/gpu/drm/i915/gvt/render.c
index ec1e60d..724f10d 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -195,6 +195,8 @@ static void switch_mocs(struct intel_vgpu *pre, struct
intel_vgpu *next,
{
struct drm_i915_private *dev_priv;
i915_reg_t offset, l3_offset;
+ u32 old_v, new_v;
+
u32 regs[] = {
[RCS] = 0xc800,
[VCS] = 0xc900,
@@ -212,16 +214,17 @@ static void switch_mocs(struct intel_vgpu *pre, struct
intel_vgpu *next,
for (i = 0; i < 64; i++) {
if (pre)
- vgpu_vreg(pre, offset) =
- I915_READ_FW(offset);
+ old_v = vgpu_vreg(pre, offset);
else
- gen9_render_mocs[ring_id][i] =
- I915_READ_FW(offset);
-
+ old_v = gen9_render_mocs[ring_id][i]
+ = I915_READ_FW(offset);
if (next)
- I915_WRITE_FW(offset, vgpu_vreg(next, offset));
+ new_v = vgpu_vreg(next, offset);
else
- I915_WRITE_FW(offset, gen9_render_mocs[ring_id][i]);
+ new_v = gen9_render_mocs[ring_id][i];
+
+ if (old_v != new_v)
+ I915_WRITE_FW(offset, new_v);
offset.reg += 4;
}
@@ -230,17 +233,17 @@ static void switch_mocs(struct intel_vgpu *pre, struct
intel_vgpu *next,
l3_offset.reg = 0xb020;
for (i = 0; i < 32; i++) {
if (pre)
- vgpu_vreg(pre, l3_offset) =
- I915_READ_FW(l3_offset);
+ old_v = vgpu_vreg(pre, l3_offset);
else
- gen9_render_mocs_L3[i] =
- I915_READ_FW(l3_offset);
+ old_v = gen9_render_mocs_L3[i]
+ = I915_READ_FW(offset);
if (next)
- I915_WRITE_FW(l3_offset,
- vgpu_vreg(next, l3_offset));
+ new_v = vgpu_vreg(next, l3_offset);
else
- I915_WRITE_FW(l3_offset,
- gen9_render_mocs_L3[i]);
+ new_v = gen9_render_mocs_L3[i];
+
+ if (old_v != new_v)
+ I915_WRITE_FW(l3_offset, new_v);
l3_offset.reg += 4;
}
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] drm/i915/gvt: load host render mocs once in mocs switch
Load host render mocs registers once for delta update of mocs switch, it reduces
mmio read times obviously, then brings performance improvement during multi-vms
switch.
Signed-off-by: Weinan Li
---
drivers/gpu/drm/i915/gvt/render.c | 51 ---
1 file changed, 42 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/render.c
b/drivers/gpu/drm/i915/gvt/render.c
index 724f10d..13c3f01 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -141,8 +141,41 @@ struct render_mmio {
{RCS, _MMIO(0x20e4), 0x, false},
};
-static u32 gen9_render_mocs[I915_NUM_ENGINES][64];
-static u32 gen9_render_mocs_L3[32];
+static struct {
+ bool initialized;
+ u32 control_table[I915_NUM_ENGINES][64];
+ u32 l3cc_table[32];
+} gen9_render_mocs;
+
+static int load_render_mocs(struct drm_i915_private *dev_priv)
+{
+ i915_reg_t offset;
+ u32 regs[] = {
+ [RCS] = 0xc800,
+ [VCS] = 0xc900,
+ [VCS2] = 0xca00,
+ [BCS] = 0xcc00,
+ [VECS] = 0xcb00,
+ };
+ int ring_id, i;
+
+ for (ring_id = 0; ring_id < I915_NUM_ENGINES; ring_id++) {
+ offset.reg = regs[ring_id];
+ for (i = 0; i < 64; i++) {
+ gen9_render_mocs.control_table[ring_id][i] =
+ I915_READ_FW(offset);
+ offset.reg += 4;
+ }
+ }
+
+ offset.reg = 0xb020;
+ for (i = 0; i < 32; i++) {
+ gen9_render_mocs.l3cc_table[i] =
+ I915_READ_FW(offset);
+ offset.reg += 4;
+ }
+ gen9_render_mocs.initialized = true;
+}
static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
{
@@ -210,18 +243,19 @@ static void switch_mocs(struct intel_vgpu *pre, struct
intel_vgpu *next,
if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
return;
- offset.reg = regs[ring_id];
+ if (!pre && !gen9_render_mocs.initialized)
+ load_render_mocs(dev_priv);
+ offset.reg = regs[ring_id];
for (i = 0; i < 64; i++) {
if (pre)
old_v = vgpu_vreg(pre, offset);
else
- old_v = gen9_render_mocs[ring_id][i]
- = I915_READ_FW(offset);
+ old_v = gen9_render_mocs.control_table[ring_id][i];
if (next)
new_v = vgpu_vreg(next, offset);
else
- new_v = gen9_render_mocs[ring_id][i];
+ new_v = gen9_render_mocs.control_table[ring_id][i];
if (old_v != new_v)
I915_WRITE_FW(offset, new_v);
@@ -235,12 +269,11 @@ static void switch_mocs(struct intel_vgpu *pre, struct
intel_vgpu *next,
if (pre)
old_v = vgpu_vreg(pre, l3_offset);
else
- old_v = gen9_render_mocs_L3[i]
- = I915_READ_FW(offset);
+ old_v = gen9_render_mocs.l3cc_table[i];
if (next)
new_v = vgpu_vreg(next, l3_offset);
else
- new_v = gen9_render_mocs_L3[i];
+ new_v = gen9_render_mocs.l3cc_table[i];
if (old_v != new_v)
I915_WRITE_FW(l3_offset, new_v);
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/3] mmio save restore refine in vgpu switch
Merge switch_mmio_to_vgpu and switch_mmio_to_host, use delta update for mocs save restore, deal host mocs value as fixed, it won't be changed after initialization. These can save vgpu switch time to reduce CPU utilization and improve GPU performance in GVT-g with multi-VMs. Weinan Li (3): drm/i915/gvt: optimize for vGPU mmio switch drm/i915/gvt: refine mocs save restore policy drm/i915/gvt: load host render mocs once in mocs switch drivers/gpu/drm/i915/gvt/cmd_parser.c | 19 +++ drivers/gpu/drm/i915/gvt/render.c | 252 +- drivers/gpu/drm/i915/gvt/trace.h | 15 +- 3 files changed, 152 insertions(+), 134 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm/i915/gvt: optimize for vGPU mmio switch
now mmio switch between vGPUs need to switch to host first then to expected
vGPU, it waste one time mmio save/restore. r/w mmio usually is
time-consuming, and there are so many mocs registers need to save/restore
during vGPU switch. Combine the switch_to_host and switch_to_vgpu can
reduce 1 time mmio save/restore, it will reduce the CPU utilization and
performance while there is multi VMs with heavy work load.
Signed-off-by: Weinan Li
---
drivers/gpu/drm/i915/gvt/render.c | 212 --
drivers/gpu/drm/i915/gvt/trace.h | 15 +--
2 files changed, 95 insertions(+), 132 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/render.c
b/drivers/gpu/drm/i915/gvt/render.c
index dac12c2..ec1e60d 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -190,9 +190,10 @@ static void handle_tlb_pending_event(struct intel_vgpu
*vgpu, int ring_id)
gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
}
-static void load_mocs(struct intel_vgpu *vgpu, int ring_id)
+static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
+ int ring_id)
{
- struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+ struct drm_i915_private *dev_priv;
i915_reg_t offset, l3_offset;
u32 regs[] = {
[RCS] = 0xc800,
@@ -203,54 +204,44 @@ static void load_mocs(struct intel_vgpu *vgpu, int
ring_id)
};
int i;
+ dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
return;
offset.reg = regs[ring_id];
- for (i = 0; i < 64; i++) {
- gen9_render_mocs[ring_id][i] = I915_READ_FW(offset);
- I915_WRITE_FW(offset, vgpu_vreg(vgpu, offset));
- offset.reg += 4;
- }
-
- if (ring_id == RCS) {
- l3_offset.reg = 0xb020;
- for (i = 0; i < 32; i++) {
- gen9_render_mocs_L3[i] = I915_READ_FW(l3_offset);
- I915_WRITE_FW(l3_offset, vgpu_vreg(vgpu, l3_offset));
- l3_offset.reg += 4;
- }
- }
-}
-static void restore_mocs(struct intel_vgpu *vgpu, int ring_id)
-{
- struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
- i915_reg_t offset, l3_offset;
- u32 regs[] = {
- [RCS] = 0xc800,
- [VCS] = 0xc900,
- [VCS2] = 0xca00,
- [BCS] = 0xcc00,
- [VECS] = 0xcb00,
- };
- int i;
+ for (i = 0; i < 64; i++) {
+ if (pre)
+ vgpu_vreg(pre, offset) =
+ I915_READ_FW(offset);
+ else
+ gen9_render_mocs[ring_id][i] =
+ I915_READ_FW(offset);
- if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
- return;
+ if (next)
+ I915_WRITE_FW(offset, vgpu_vreg(next, offset));
+ else
+ I915_WRITE_FW(offset, gen9_render_mocs[ring_id][i]);
- offset.reg = regs[ring_id];
- for (i = 0; i < 64; i++) {
- vgpu_vreg(vgpu, offset) = I915_READ_FW(offset);
- I915_WRITE_FW(offset, gen9_render_mocs[ring_id][i]);
offset.reg += 4;
}
if (ring_id == RCS) {
l3_offset.reg = 0xb020;
for (i = 0; i < 32; i++) {
- vgpu_vreg(vgpu, l3_offset) = I915_READ_FW(l3_offset);
- I915_WRITE_FW(l3_offset, gen9_render_mocs_L3[i]);
+ if (pre)
+ vgpu_vreg(pre, l3_offset) =
+ I915_READ_FW(l3_offset);
+ else
+ gen9_render_mocs_L3[i] =
+ I915_READ_FW(l3_offset);
+ if (next)
+ I915_WRITE_FW(l3_offset,
+ vgpu_vreg(next, l3_offset));
+ else
+ I915_WRITE_FW(l3_offset,
+ gen9_render_mocs_L3[i]);
+
l3_offset.reg += 4;
}
}
@@ -258,78 +249,25 @@ static void restore_mocs(struct intel_vgpu *vgpu, int
ring_id)
#define CTX_CONTEXT_CONTROL_VAL0x03
-/* Switch ring mmio values (context) from host to a vgpu. */
-static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id)
-{
- struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
- struct intel_vgpu_submission *s = &vgpu->submission;
- u32 *reg_state = s->shadow_ctx->engine[ring_id].lrc_reg_state;
- u32 ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL];
- u32 inhibit_mask =
- _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [1/4] lib: copy intel_aub.h from libdrm
== Series Details == Series: series starting with [1/4] lib: copy intel_aub.h from libdrm URL : https://patchwork.freedesktop.org/series/34999/ State : warning == Summary == Test pm_rc6_residency: Subgroup rc6-accuracy: pass -> SKIP (shard-snb) Test gem_softpin: Subgroup noreloc-s3: pass -> SKIP (shard-snb) fdo#102365 Test kms_cursor_crc: Subgroup cursor-256x256-suspend: pass -> INCOMPLETE (shard-hsw) fdo#103375 Test gem_tiled_swapping: Subgroup non-threaded: pass -> INCOMPLETE (shard-snb) fdo#104009 +1 fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365 fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 fdo#104009 https://bugs.freedesktop.org/show_bug.cgi?id=104009 shard-hswtotal:2579 pass:1466 dwarn:1 dfail:0 fail:10 skip:1100 time:8861s shard-snbtotal:2607 pass:1259 dwarn:1 dfail:0 fail:13 skip:1333 time:7722s Blacklisted hosts: shard-apltotal:2679 pass:1679 dwarn:2 dfail:0 fail:21 skip:977 time:13622s shard-kbltotal:2679 pass:1784 dwarn:9 dfail:0 fail:26 skip:860 time:10930s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_607/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for igt/perf_pmu: Tweak wait_for_rc6, yet again
== Series Details == Series: igt/perf_pmu: Tweak wait_for_rc6, yet again URL : https://patchwork.freedesktop.org/series/34998/ State : success == Summary == Test kms_cursor_crc: Subgroup cursor-64x64-suspend: pass -> SKIP (shard-snb) fdo#102365 Test pm_rpm: Subgroup system-suspend-execbuf: pass -> SKIP (shard-hsw) fdo#103375 Test kms_frontbuffer_tracking: Subgroup fbc-1p-offscren-pri-shrfb-draw-blt: fail -> PASS (shard-snb) fdo#101623 fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365 fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623 shard-hswtotal:2679 pass:1535 dwarn:1 dfail:0 fail:10 skip:1133 time:9474s shard-snbtotal:2679 pass:1307 dwarn:1 dfail:0 fail:12 skip:1359 time:8054s Blacklisted hosts: shard-apltotal:2679 pass:1676 dwarn:3 dfail:0 fail:22 skip:977 time:13656s shard-kbltotal:2534 pass:1698 dwarn:3 dfail:0 fail:22 skip:808 time:9640s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_606/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 0/4] GPU/CPU timestamps correlation for relating OA samples with system events
On Thu, Dec 7, 2017 at 12:48 AM, Robert Bragg wrote: > > at least from what I wrote back then it looks like I was seeing a drift of > a few milliseconds per second on SKL. I vaguely recall it being much worse > given the frequency constants we had for Haswell. > Sorry I didn't actually re-read my own message properly before referencing it :) Apparently the 2ms per second drift was for Haswell, so presumably not quite so bad for SKL. - Robert ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 04/11] drm/exynos: Use drm_fb_helper_lastclose() and _poll_changed()
2017년 12월 06일 03:24에 Noralf Trønnes 이(가) 쓴 글:
> This driver can use drm_fb_helper_lastclose() as its .lastclose callback.
> It can also use drm_fb_helper_output_poll_changed() as its
> .output_poll_changed callback.
>
> Cc: Inki Dae
> Cc: Joonyoung Shim
> Cc: Seung-Woo Kim
> Cc: Kyungmin Park
> Signed-off-by: Noralf Trønnes
> Acked-by: Daniel Vetter
Seems you missed my ACK,
http://www.spinics.net/lists/intel-gfx/msg146188.html
Thanks,
Inki Dae
> ---
> drivers/gpu/drm/exynos/exynos_drm_drv.c | 8 ++--
> drivers/gpu/drm/exynos/exynos_drm_fb.c| 2 +-
> drivers/gpu/drm/exynos/exynos_drm_fbdev.c | 18 --
> drivers/gpu/drm/exynos/exynos_drm_fbdev.h | 2 --
> 4 files changed, 3 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c
> b/drivers/gpu/drm/exynos/exynos_drm_drv.c
> index 82b72425a42f..2f2bd6e37e62 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
> @@ -16,6 +16,7 @@
> #include
> #include
> #include
> +#include
>
> #include
>
> @@ -89,11 +90,6 @@ static void exynos_drm_postclose(struct drm_device *dev,
> struct drm_file *file)
> file->driver_priv = NULL;
> }
>
> -static void exynos_drm_lastclose(struct drm_device *dev)
> -{
> - exynos_drm_fbdev_restore_mode(dev);
> -}
> -
> static const struct vm_operations_struct exynos_drm_gem_vm_ops = {
> .fault = exynos_drm_gem_fault,
> .open = drm_gem_vm_open,
> @@ -140,7 +136,7 @@ static struct drm_driver exynos_drm_driver = {
> .driver_features= DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME
> | DRIVER_ATOMIC | DRIVER_RENDER,
> .open = exynos_drm_open,
> - .lastclose = exynos_drm_lastclose,
> + .lastclose = drm_fb_helper_lastclose,
> .postclose = exynos_drm_postclose,
> .gem_free_object_unlocked = exynos_drm_gem_free_object,
> .gem_vm_ops = &exynos_drm_gem_vm_ops,
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.c
> b/drivers/gpu/drm/exynos/exynos_drm_fb.c
> index 8208df56a88f..0faaf829f5bf 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_fb.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_fb.c
> @@ -205,7 +205,7 @@ static struct drm_mode_config_helper_funcs
> exynos_drm_mode_config_helpers = {
>
> static const struct drm_mode_config_funcs exynos_drm_mode_config_funcs = {
> .fb_create = exynos_user_fb_create,
> - .output_poll_changed = exynos_drm_output_poll_changed,
> + .output_poll_changed = drm_fb_helper_output_poll_changed,
> .atomic_check = exynos_atomic_check,
> .atomic_commit = drm_atomic_helper_commit,
> };
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
> b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
> index dfb66ecf417b..132dd52d0ac7 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
> @@ -270,24 +270,6 @@ void exynos_drm_fbdev_fini(struct drm_device *dev)
> private->fb_helper = NULL;
> }
>
> -void exynos_drm_fbdev_restore_mode(struct drm_device *dev)
> -{
> - struct exynos_drm_private *private = dev->dev_private;
> -
> - if (!private || !private->fb_helper)
> - return;
> -
> - drm_fb_helper_restore_fbdev_mode_unlocked(private->fb_helper);
> -}
> -
> -void exynos_drm_output_poll_changed(struct drm_device *dev)
> -{
> - struct exynos_drm_private *private = dev->dev_private;
> - struct drm_fb_helper *fb_helper = private->fb_helper;
> -
> - drm_fb_helper_hotplug_event(fb_helper);
> -}
> -
> void exynos_drm_fbdev_suspend(struct drm_device *dev)
> {
> struct exynos_drm_private *private = dev->dev_private;
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.h
> b/drivers/gpu/drm/exynos/exynos_drm_fbdev.h
> index 645d1bb7f665..b33847223a85 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.h
> +++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.h
> @@ -19,8 +19,6 @@
>
> int exynos_drm_fbdev_init(struct drm_device *dev);
> void exynos_drm_fbdev_fini(struct drm_device *dev);
> -void exynos_drm_fbdev_restore_mode(struct drm_device *dev);
> -void exynos_drm_output_poll_changed(struct drm_device *dev);
> void exynos_drm_fbdev_suspend(struct drm_device *drm);
> void exynos_drm_fbdev_resume(struct drm_device *drm);
>
>
___
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Re: [Intel-gfx] [RFC 0/4] GPU/CPU timestamps correlation for relating OA samples with system events
On Wed, Nov 15, 2017 at 12:13 PM, Sagar Arun Kamble <
sagar.a.kam...@intel.com> wrote:
> We can compute system time corresponding to GPU timestamp by taking a
> reference point (CPU monotonic time, GPU timestamp) and then adding
> delta time computed using timecounter/cyclecounter support in kernel.
> We have to configure cyclecounter with the GPU timestamp frequency.
> Earlier approach that was based on cross-timestamp is not needed. It
> was being used to approximate the frequency based on invalid assumptions
> (possibly drift was being seen in the time due to precision issue).
> The precision of time from GPU clocks is already in ns and timecounter
> takes care of it as verified over variable durations.
>
Hi Sagar,
I have some doubts about this analysis...
The intent behind Sourab's original approach was to be able to determine
the frequency at runtime empirically because the constants we have aren't
particularly accurate. Without a perfectly stable frequency that's known
very precisely then an interpolated correlation will inevitably drift. I
think the nature of HW implies we can't expect to have either of those.
Then the general idea had been to try and use existing kernel
infrastructure for a problem which isn't unique to GPU clocks.
That's not to say that a more limited, simpler solution based on frequent
re-correlation wouldn't be more than welcome if tracking an accurate
frequency is too awkward for now, but I think some things need to be
considered in that case:
- It would be good to quantify the kind of drift seen in practice to know
how frequently it's necessary to re-synchronize. It sounds like you've done
this ("as verified over variable durations") so I'm curious what kind of
drift you saw. I'd imagine you would see a significant drift over, say, one
second and it might not take much longer for the drift to even become
clearly visible to the user when plotted in a UI. For reference I once
updated the arb_timer_query test in piglit to give some insight into this
drift (
https://lists.freedesktop.org/archives/piglit/2016-September/020673.html)
and at least from what I wrote back then it looks like I was seeing a drift
of a few milliseconds per second on SKL. I vaguely recall it being much
worse given the frequency constants we had for Haswell.
- What guarantees will be promised about monotonicity of correlated system
timestamps? Will it be guaranteed that sequential reports must have
monotonically increasing timestamps? That might be fiddly if the gpu +
system clock are periodically re-correlated, so it might be good to be
clear in documentation that the correlation is best-effort only for the
sake of implementation simplicity. That would still be good for a lot of
UIs I think and there's freedom for the driver to start simple and
potentially improve later by measuring the gpu clock frequency empirically.
Currently only one correlated pair of timestamps is read when enabling the
stream and so a relatively long time is likely to pass before the stream is
disabled (seconds, minutes while a user is running a system profiler) . It
seems very likely to me that these clocks are going to drift significantly
without introducing some form of periodic re-synchronization based on some
understanding of the drift that's seen.
Br,
- Robert
> This series adds base timecounter/cyclecounter changes and changes to
> get GPU and CPU timestamps in OA samples.
>
> Sagar Arun Kamble (1):
> drm/i915/perf: Add support to correlate GPU timestamp with system time
>
> Sourab Gupta (3):
> drm/i915/perf: Add support for collecting 64 bit timestamps with OA
> reports
> drm/i915/perf: Extract raw GPU timestamps from OA reports
> drm/i915/perf: Send system clock monotonic time in perf samples
>
> drivers/gpu/drm/i915/i915_drv.h | 11
> drivers/gpu/drm/i915/i915_perf.c | 124 ++
> -
> drivers/gpu/drm/i915/i915_reg.h | 6 ++
> include/uapi/drm/i915_drm.h | 14 +
> 4 files changed, 154 insertions(+), 1 deletion(-)
>
> --
> 1.9.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [RFC,1/5] igt_dummyload: Wrap function parameters into struct
== Series Details == Series: series starting with [RFC,1/5] igt_dummyload: Wrap function parameters into struct URL : https://patchwork.freedesktop.org/series/34997/ State : failure == Summary == Test kms_flip: Subgroup wf_vblank: pass -> DMESG-WARN (shard-hsw) Subgroup blt-wf_vblank-vs-modeset: pass -> INCOMPLETE (shard-hsw) Test kms_cursor_crc: Subgroup cursor-size-change: pass -> FAIL (shard-hsw) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-c: pass -> INCOMPLETE (shard-hsw) fdo#103375 Test drv_hangman: Subgroup error-state-capture-render: pass -> FAIL (shard-snb) Subgroup error-state-capture-blt: pass -> FAIL (shard-snb) Test kms_frontbuffer_tracking: Subgroup fbc-1p-offscren-pri-shrfb-draw-blt: fail -> PASS (shard-snb) fdo#101623 Test pm_rc6_residency: Subgroup rc6-accuracy: pass -> SKIP (shard-snb) fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623 shard-hswtotal:2584 pass:1484 dwarn:2 dfail:0 fail:11 skip:1085 time:9233s shard-snbtotal:2679 pass:1305 dwarn:1 dfail:0 fail:14 skip:1359 time:8322s Blacklisted hosts: shard-apltotal:2657 pass:1654 dwarn:2 dfail:0 fail:22 skip:977 time:13445s shard-kbltotal:2554 pass:1703 dwarn:2 dfail:0 fail:21 skip:826 time:9936s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_605/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/2] CONTRIBUTING: Fix spelling mistake and line length
Noticed while I was reading it. Makes for a good first contribution, I guess. Changes in v2: - None Reviewed-by: Petri Latvala Signed-off-by: Sean Paul --- CONTRIBUTING | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/CONTRIBUTING b/CONTRIBUTING index 561c5dd8..ca2ed8a5 100644 --- a/CONTRIBUTING +++ b/CONTRIBUTING @@ -18,13 +18,13 @@ A short list of contribution guidelines: on its first invocation. -- intel-gpu-tools is MIT lincensed and we require contributions to follow the +- intel-gpu-tools is MIT licensed and we require contributions to follow the developer's certificate of origin: http://developercertificate.org/ - When submitting new testcases please follow the naming conventions documented - in the generated documentation. Also please make full use of all the helpers and - convenience macros provided by the igt library. The semantic patch lib/igt.cocci - can help with the more automatic conversions. + in the generated documentation. Also please make full use of all the helpers + and convenience macros provided by the igt library. The semantic patch + lib/igt.cocci can help with the more automatic conversions. - Patches need to be reviewed on the mailing list. Exceptions only apply for testcases and tooling for drivers with just a single contributor (e.g. vc4). -- 2.15.1.424.g9478a66081-goog ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/2] kms_content_protection: Add Content Protection test
Pretty simple test:
- initializes the output
- clears the content protection property
- verifies that it clears
- sets the content protection property to desired
- verifies that it transitions to enabled
Does this for both legacy and atomic.
Changes in v2:
- Don't check for i915 gen
- Skip test if Content Protection property is absent
Signed-off-by: Sean Paul
---
lib/igt_kms.c | 3 +-
lib/igt_kms.h | 1 +
tests/Makefile.sources | 1 +
tests/kms_content_protection.c | 129 +
tests/meson.build | 1 +
5 files changed, 134 insertions(+), 1 deletion(-)
create mode 100644 tests/kms_content_protection.c
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 125ecb19..907db694 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -190,7 +190,8 @@ const char
*igt_connector_prop_names[IGT_NUM_CONNECTOR_PROPS] = {
"scaling mode",
"CRTC_ID",
"DPMS",
- "Broadcast RGB"
+ "Broadcast RGB",
+ "Content Protection"
};
/*
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index 2a480bf3..93e59dc7 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -118,6 +118,7 @@ enum igt_atomic_connector_properties {
IGT_CONNECTOR_CRTC_ID,
IGT_CONNECTOR_DPMS,
IGT_CONNECTOR_BROADCAST_RGB,
+ IGT_CONNECTOR_CONTENT_PROTECTION,
IGT_NUM_CONNECTOR_PROPS
};
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 34ca71a0..e0466411 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -179,6 +179,7 @@ TESTS_progs = \
kms_chv_cursor_fail \
kms_color \
kms_concurrent \
+ kms_content_protection\
kms_crtc_background_color \
kms_cursor_crc \
kms_cursor_legacy \
diff --git a/tests/kms_content_protection.c b/tests/kms_content_protection.c
new file mode 100644
index ..5d61b257
--- /dev/null
+++ b/tests/kms_content_protection.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright © 2017 Google, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt.h"
+
+IGT_TEST_DESCRIPTION("Test content protection (HDCP)");
+
+typedef struct {
+ int drm_fd;
+ igt_display_t display;
+} data_t;
+
+static bool
+wait_for_prop_value(igt_output_t *output, uint64_t expected)
+{
+ uint64_t val;
+ int i;
+
+ for (i = 0; i < 2000; i++) {
+ val = igt_output_get_prop(output,
+ IGT_CONNECTOR_CONTENT_PROTECTION);
+ if (val == expected)
+ return true;
+ usleep(1000);
+ }
+ igt_info("prop_value mismatch %ld != %ld\n", val, expected);
+ return false;
+}
+
+static void
+test_pipe_output(igt_display_t *display, const enum pipe pipe,
+igt_output_t *output, enum igt_commit_style s)
+{
+ drmModeModeInfo mode;
+ igt_plane_t *primary;
+ struct igt_fb red;
+ bool ret;
+
+ igt_assert(kmstest_get_connector_default_mode(
+ display->drm_fd, output->config.connector, &mode));
+
+ igt_output_override_mode(output, &mode);
+ igt_output_set_pipe(output, pipe);
+
+ igt_create_color_fb(display->drm_fd, mode.hdisplay, mode.vdisplay,
+ DRM_FORMAT_XRGB, LOCAL_DRM_FORMAT_MOD_NONE,
+ 1.f, 0.f, 0.f, &red);
+ primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
+ igt_plane_set_fb(primary, &red);
+ igt_display_commit2(display, s);
+
+ igt_output_set_prop_value(output, IGT_CONNECTOR_CONTENT_PROTECTION, 0);
+ igt_display_commit2(display, s);
+
+ ret = wait_for_prop_value(output, 0);
+ igt_require_f(ret, "Content Protection not cleared\n");
+
+ igt_output_set_prop_value(output, IGT_CONNECTOR_CONTENT_PROTECTION, 1);
+ igt_display_commit
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Implement HDCP (rev4)
On Wed, Dec 6, 2017 at 7:08 PM, Patchwork wrote: > == Series Details == > > Series: drm/i915: Implement HDCP (rev4) > URL : https://patchwork.freedesktop.org/series/34671/ > State : failure > Ah, son of a beesting! I'll rebase on -tip and resend once people have time to provide feedback. Sean > == Summary == > > Applying: drm: Fix link-status kerneldoc line lengths > error: Failed to merge in the changes. > Using index info to reconstruct a base tree... > M drivers/gpu/drm/drm_connector.c > Falling back to patching base and 3-way merge... > Auto-merging drivers/gpu/drm/drm_connector.c > CONFLICT (content): Merge conflict in drivers/gpu/drm/drm_connector.c > Patch failed at 0001 drm: Fix link-status kerneldoc line lengths > The copy of the patch that failed is found in: .git/rebase-apply/patch > When you have resolved this problem, run "git am --continue". > If you prefer to skip this patch, run "git am --skip" instead. > To restore the original branch and stop patching, run "git am --abort". > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Implement HDCP (rev4)
== Series Details == Series: drm/i915: Implement HDCP (rev4) URL : https://patchwork.freedesktop.org/series/34671/ State : failure == Summary == Applying: drm: Fix link-status kerneldoc line lengths error: Failed to merge in the changes. Using index info to reconstruct a base tree... M drivers/gpu/drm/drm_connector.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/drm_connector.c CONFLICT (content): Merge conflict in drivers/gpu/drm/drm_connector.c Patch failed at 0001 drm: Fix link-status kerneldoc line lengths The copy of the patch that failed is found in: .git/rebase-apply/patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] lib: copy intel_aub.h from libdrm
== Series Details == Series: series starting with [1/4] lib: copy intel_aub.h from libdrm URL : https://patchwork.freedesktop.org/series/34999/ State : success == Summary == IGT patchset tested on top of latest successful build 1db12466cb5ad8483cd469753d2e312a62d717b7 meson: build a full dependency for lib_igt_perf with latest DRM-Tip kernel build CI_DRM_3468 95f37eb3ebfd drm-tip: 2017y-12m-06d-21h-01m-04s UTC integration manifest No testlist changes. Test debugfs_test: Subgroup read_all_entries: dmesg-fail -> DMESG-WARN (fi-elk-e7500) fdo#103989 Test gem_exec_reloc: Subgroup basic-write-gtt-active: pass -> FAIL (fi-gdg-551) fdo#102582 Test gem_mmap_gtt: Subgroup basic-small-bo-tiledx: fail -> PASS (fi-gdg-551) fdo#102575 fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582 fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:438s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:387s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:521s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:283s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:504s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:513s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:495s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:477s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:268s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:537s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:374s fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:259s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:476s fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:453s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:525s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:477s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:533s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:596s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:451s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:548s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:566s fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:519s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:501s fi-snb-2520m total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:547s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:419s Blacklisted hosts: fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:640s fi-glk-dsi total:216 pass:180 dwarn:0 dfail:1 fail:0 skip:34 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_607/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 9/9] drm/i915: Implement HDCP for DisplayPort
This patch adds HDCP support for DisplayPort connectors by implementing
the intel_hdcp_shim.
Most of this is straightforward read/write from/to DPCD registers. One
thing worth pointing out is the Aksv output bit. It wasn't easily
separable like it's HDMI counterpart, so it's crammed in with the rest
of it.
Changes in v2:
- Moved intel_hdcp_check_link out of intel_dp_check_link and only call
it on short pulse. Since intel_hdcp_check_link does its own locking,
this ensures we don't deadlock when intel_dp_check_link is called
holding connection_mutex.
- Rebased on drm-intel-next
Changes in v3:
- Initialize new worker
Changes in v4:
- Use intel_hdcp_init (Daniel)
- Check for reauth requests in check_link (Ram)
Cc: Daniel Vetter
Cc: Ramalingam C
Signed-off-by: Sean Paul
---
drivers/gpu/drm/i915/intel_dp.c | 244 ++--
1 file changed, 237 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c603d4c903e1..0ec8b23d0332 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -36,7 +36,9 @@
#include
#include
#include
+#include
#include
+#include
#include "intel_drv.h"
#include
#include "i915_drv.h"
@@ -1025,10 +1027,29 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp,
DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
}
+static uint32_t intel_dp_get_aux_send_ctl(struct intel_dp *intel_dp,
+ bool has_aux_irq,
+ int send_bytes,
+ uint32_t aux_clock_divider,
+ bool aksv_write)
+{
+ uint32_t val = 0;
+
+ if (aksv_write) {
+ send_bytes += 5;
+ val |= DP_AUX_CH_CTL_AUX_AKSV_SELECT;
+ }
+
+ return val | intel_dp->get_aux_send_ctl(intel_dp,
+ has_aux_irq,
+ send_bytes,
+ aux_clock_divider);
+}
+
static int
intel_dp_aux_ch(struct intel_dp *intel_dp,
const uint8_t *send, int send_bytes,
- uint8_t *recv, int recv_size)
+ uint8_t *recv, int recv_size, bool aksv_write)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv =
@@ -1088,10 +1109,11 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
}
while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp,
clock++))) {
- u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
- has_aux_irq,
- send_bytes,
- aux_clock_divider);
+ u32 send_ctl = intel_dp_get_aux_send_ctl(intel_dp,
+has_aux_irq,
+send_bytes,
+aux_clock_divider,
+aksv_write);
/* Must try at least 3 times according to DP spec */
for (try = 0; try < 5; try++) {
@@ -1228,7 +1250,8 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct
drm_dp_aux_msg *msg)
if (msg->buffer)
memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
- ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
+ ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize,
+ false);
if (ret > 0) {
msg->reply = rxbuf[0] >> 4;
@@ -1250,7 +1273,8 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct
drm_dp_aux_msg *msg)
if (WARN_ON(rxsize > 20))
return -E2BIG;
- ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
+ ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize,
+ false);
if (ret > 0) {
msg->reply = rxbuf[0] >> 4;
/*
@@ -4981,6 +5005,203 @@ void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder)
pps_unlock(intel_dp);
}
+static
+int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
+ u8 *an)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
+ uint8_t txbuf[4], rxbuf[2], reply = 0;
+ ssize_t dpcd_ret;
+ int ret;
+
+ /* Output An first, that's easy */
+ dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
+an, DRM_HDCP_AN_LEN);
+
[Intel-gfx] [PATCH v4 8/9] drm/i915: Implement HDCP for HDMI
This patch adds HDCP support for HDMI connectors by implementing
the intel_hdcp_shim.
Nothing too special, just a bunch of DDC reads/writes.
Changes in v2:
- Rebased on drm-intel-next
Changes in v3:
- Initialize new worker
Changes in v4:
- Remove SKL_ prefix from most register names (Daniel)
- Wrap sanity checks in WARN_ON (Daniel)
- Consolidate the enable/disable functions into one toggle fn
- Use intel_hdcp_init (Daniel)
Cc: Daniel Vetter
Signed-off-by: Sean Paul
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ddi.c | 29 +
drivers/gpu/drm/i915/intel_drv.h | 4 +
drivers/gpu/drm/i915/intel_hdmi.c | 250 ++
4 files changed, 284 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 35bcc6c308f3..8e4e810b81ef 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8450,6 +8450,7 @@ enum skl_power_gate {
#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
+#define TRANS_DDI_HDCP_SIGNALLING (1<<9)
#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8)
#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1<<7)
#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1<<6)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ab727f0b2696..f181f5840268 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1615,6 +1615,35 @@ void intel_ddi_disable_transcoder_func(struct
drm_i915_private *dev_priv,
I915_WRITE(reg, val);
}
+int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
+bool enable)
+{
+ struct drm_device *dev = intel_encoder->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum pipe pipe = 0;
+ int ret = 0;
+ uint32_t tmp;
+
+ if (WARN_ON(!intel_display_power_get_if_enabled(dev_priv,
+ intel_encoder->power_domain)))
+ return -ENXIO;
+
+ if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
+ ret = -EIO;
+ goto out;
+ }
+
+ tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
+ if (enable)
+ tmp |= TRANS_DDI_HDCP_SIGNALLING;
+ else
+ tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
+ I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
+out:
+ intel_display_power_put(dev_priv, intel_encoder->power_domain);
+ return ret;
+}
+
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
{
struct drm_device *dev = intel_connector->base.dev;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3351785af867..3a5393866ed2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1379,6 +1379,10 @@ void intel_ddi_compute_min_voltage_level(struct
drm_i915_private *dev_priv,
u32 bxt_signal_levels(struct intel_dp *intel_dp);
uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
+int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
+bool enable);
+int intel_ddi_enable_hdcp_signalling(struct intel_encoder *intel_encoder);
+int intel_ddi_disable_hdcp_signalling(struct intel_encoder *intel_encoder);
unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
int plane, unsigned int height);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 9d5e72728475..382fd443fd0d 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -34,6 +34,7 @@
#include
#include
#include
+#include
#include
#include "intel_drv.h"
#include
@@ -873,6 +874,248 @@ void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi
*hdmi, bool enable)
adapter, enable);
}
+static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
+ unsigned int offset, void *buffer, size_t size)
+{
+ struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
+ struct drm_i915_private *dev_priv =
+ intel_dig_port->base.base.dev->dev_private;
+ struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
+ hdmi->ddc_bus);
+ int ret;
+ u8 start = offset & 0xff;
+ struct i2c_msg msgs[] = {
+ {
+ .addr = DRM_HDCP_DDC_ADDR,
+ .flags = 0,
+ .len = 1,
+ .buf = &start,
+ },
+ {
+ .addr = DRM_HDCP_DDC_ADDR,
+ .flags = I2C_M_RD,
+
[Intel-gfx] [PATCH v4 4/9] drm: Add some HDCP related #defines
In preparation for implementing HDCP in i915, add some HDCP related register offsets and defines. The dpcd register offsets will go in drm_dp_helper.h whereas the ddc offsets along with generic HDCP stuff will get stuffed in drm_hdcp.h, which is new. Changes in v2: - drm_hdcp.h gets MIT license (Daniel) Changes in v3: - None Changes in v4: - None Cc: Daniel Vetter Signed-off-by: Sean Paul --- include/drm/drm_dp_helper.h | 17 ++ include/drm/drm_hdcp.h | 56 + 2 files changed, 73 insertions(+) create mode 100644 include/drm/drm_hdcp.h diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 8b9ac321c3bd..4b2640d54c70 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -815,6 +815,23 @@ #define DP_CEC_TX_MESSAGE_BUFFER 0x3020 #define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10 +#define DP_AUX_HDCP_BKSV 0x68000 +#define DP_AUX_HDCP_RI_PRIME 0x68005 +#define DP_AUX_HDCP_AKSV 0x68007 +#define DP_AUX_HDCP_AN 0x6800C +#define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4) +#define DP_AUX_HDCP_BCAPS 0x68028 +# define DP_BCAPS_REPEATER_PRESENT BIT(1) +# define DP_BCAPS_HDCP_CAPABLE BIT(0) +#define DP_AUX_HDCP_BSTATUS0x68029 +# define DP_BSTATUS_REAUTH_REQ BIT(3) +# define DP_BSTATUS_LINK_FAILURE BIT(2) +# define DP_BSTATUS_R0_PRIME_READY BIT(1) +# define DP_BSTATUS_READY BIT(0) +#define DP_AUX_HDCP_BINFO 0x6802A +#define DP_AUX_HDCP_KSV_FIFO 0x6802C +#define DP_AUX_HDCP_AINFO 0x6803B + /* DP 1.2 Sideband message defines */ /* peer device type - DP 1.2a Table 2-92 */ #define DP_PEER_DEVICE_NONE0x0 diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h new file mode 100644 index ..c9b2484240d4 --- /dev/null +++ b/include/drm/drm_hdcp.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2017 Google, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Sean Paul + */ + +#ifndef _DRM_HDCP_H_INCLUDED_ +#define _DRM_HDCP_H_INCLUDED_ + +/* Period of hdcp checks (to ensure we're still authenticated) */ +#define DRM_HDCP_CHECK_PERIOD_MS (128 * 16) + +/* Shared lengths/masks between HDMI/DVI/DisplayPort */ +#define DRM_HDCP_AN_LEN8 +#define DRM_HDCP_BSTATUS_LEN 2 +#define DRM_HDCP_KSV_LEN 5 +#define DRM_HDCP_RI_LEN2 +#define DRM_HDCP_V_PRIME_PART_LEN 4 +#define DRM_HDCP_V_PRIME_NUM_PARTS 5 +#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x3f) + +/* Slave address for the HDCP registers in the receiver */ +#define DRM_HDCP_DDC_ADDR 0x3A + +/* HDCP register offsets for HDMI/DVI devices */ +#define DRM_HDCP_DDC_BKSV 0x00 +#define DRM_HDCP_DDC_RI_PRIME 0x08 +#define DRM_HDCP_DDC_AKSV 0x10 +#define DRM_HDCP_DDC_AN0x18 +#define DRM_HDCP_DDC_V_PRIME(h)(0x20 + h * 4) +#define DRM_HDCP_DDC_BCAPS 0x40 +#define DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT BIT(6) +#define DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY BIT(5) +#define DRM_HDCP_DDC_BSTATUS 0x41 +#define DRM_HDCP_DDC_KSV_FIFO 0x43 + +#endif -- 2.15.1.424.g9478a66081-goog ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 5/9] drm/i915: Add HDCP framework + base implementation
This patch adds the framework required to add HDCP support to intel
connectors. It implements Aksv loading from fuse, and parts 1/2/3
of the HDCP authentication scheme.
Note that without shim implementations, this does not actually implement
HDCP. That will come in subsequent patches.
Changes in v2:
- Don't open code wait_fors (Chris)
- drm_hdcp.c under MIT license (Daniel)
- Move intel_hdcp_disable() call above ddi_disable (Ram)
- Fix // comments (I wore a cone of shame for 12 hours to atone) (Daniel)
- Justify intel_hdcp_shim with comments (Daniel)
- Fixed async locking issues by adding hdcp_mutex (Daniel)
- Don't alter connector_state in enable/disable (Daniel)
Changes in v3:
- Added hdcp_mutex/hdcp_value to make async reasonable
- Added hdcp_prop_work to separate link checking & property setting
- Added new helper for atomic_check state tracking (Daniel)
- Moved enable/disable into atomic_commit with matching helpers
- Moved intel_hdcp_check_link out of all locks when called from dp
- Bumped up ksv_fifo timeout (noticed failure on one of my dongles)
Changes in v4:
- Remove SKL_ prefix from most register names (Daniel)
- Move enable/disable back to modeset path (Daniel)
- s/get_random_long/get_random_u32/ (Daniel)
- Remove mode_config.mutex lock in prop_work (Daniel)
- Add intel_hdcp_init to handle init of conn components (Daniel)
- Actually check return value of attach_property
- Check Bksv is valid before trying to authenticate (Ram)
Cc: Chris Wilson
Cc: Ramalingam C
Reviewed-by: Daniel Vetter
Signed-off-by: Sean Paul
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/i915_reg.h | 83
drivers/gpu/drm/i915/intel_atomic.c | 2 +
drivers/gpu/drm/i915/intel_ddi.c | 7 +
drivers/gpu/drm/i915/intel_display.c | 4 +
drivers/gpu/drm/i915/intel_drv.h | 85
drivers/gpu/drm/i915/intel_hdcp.c| 735 +++
7 files changed, 917 insertions(+)
create mode 100644 drivers/gpu/drm/i915/intel_hdcp.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 42bc8bd4ff06..3facea4eefdb 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -107,6 +107,7 @@ i915-y += intel_audio.o \
intel_fbc.o \
intel_fifo_underrun.o \
intel_frontbuffer.o \
+ intel_hdcp.o \
intel_hotplug.o \
intel_modes.o \
intel_overlay.o \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 09bf043c1c2e..4d66651219e3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8034,6 +8034,7 @@ enum {
#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
+#define SKL_PCODE_LOAD_HDCP_KEYS 0x5
#define SKL_PCODE_CDCLK_CONTROL 0x7
#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
#define SKL_CDCLK_READY_FOR_CHANGE 0x1
@@ -8335,6 +8336,88 @@ enum skl_power_gate {
#define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1)
#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
+
+/* HDCP Key Registers */
+#define HDCP_KEY_CONF _MMIO(0x66c00)
+#define HDCP_AKSV_SEND_TRIGGERBIT(31)
+#define HDCP_CLEAR_KEYS_TRIGGER BIT(30)
+#define HDCP_KEY_STATUS_MMIO(0x66c04)
+#define HDCP_FUSE_IN_PROGRESS BIT(7)
+#define HDCP_FUSE_ERROR BIT(6)
+#define HDCP_FUSE_DONEBIT(5)
+#define HDCP_KEY_LOAD_STATUS BIT(1)
+#define HDCP_KEY_LOAD_DONEBIT(0)
+#define HDCP_AKSV_LO _MMIO(0x66c10)
+#define HDCP_AKSV_HI _MMIO(0x66c14)
+
+/* HDCP Repeater Registers */
+#define HDCP_REP_CTL _MMIO(0x66d00)
+#define HDCP_DDIB_REP_PRESENT BIT(30)
+#define HDCP_DDIA_REP_PRESENT BIT(29)
+#define HDCP_DDIC_REP_PRESENT BIT(28)
+#define HDCP_DDID_REP_PRESENT BIT(27)
+#define HDCP_DDIF_REP_PRESENT BIT(26)
+#define HDCP_DDIE_REP_PRESENT BIT(25)
+#define HDCP_DDIB_SHA1_M0 (1 << 20)
+#define HDCP_DDIA_SHA1_M0 (2 << 20)
+#define HDCP_DDIC_SHA1_M0 (3 << 20)
+#define HDCP_DDID_SHA1_M0 (4 << 20)
+#define HDCP_DDIF_SHA1_M0 (5 << 20)
+#define HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */
+#define HDCP_SHA1_BUSYBIT(16)
+#define HDCP_SHA1_READY BIT(17)
+#define HDCP_SHA1_COMPLETEBIT(18)
+#define HDCP_SHA1_V_MATCH BIT(19)
+#define HDCP_SHA1_TEXT_32 (1 << 1)
+#define HDCP_SHA1_COMPLETE_HASH (2 << 1)
+#define HDCP_SHA1_TEXT_24 (4 << 1)
+#define HDCP_SHA1_TEXT_16 (5 << 1)
+#define HDCP_SHA1_TEXT_8 (6 << 1)
+#define HDCP_SHA1_TEXT_0 (7 << 1)
+#define HDCP_SHA_V_PRIME_H0_MMIO(0x66d04)
+#define HDCP_SHA_V_PRIME_H1_MMIO(0x6
[Intel-gfx] [PATCH v4 6/9] drm/i915: Make use of indexed write GMBUS feature
This patch enables the indexed write feature of the GMBUS to concatenate
2 consecutive messages into one. The criteria for an indexed write is
that both messages are writes, the first is length == 1, and the second
is length > 0. The first message is sent out by the GMBUS as the slave
command, and the second one is sent via the GMBUS FIFO as usual.
Changes in v3:
- Added to series
Changes in v4:
- Combine indexed reads and writes (Ville)
Cc: Daniel Vetter
Suggested-by: Ville Syrjälä
Signed-off-by: Sean Paul
---
drivers/gpu/drm/i915/intel_i2c.c | 34 --
1 file changed, 20 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 49fdf09f9919..d78ce758fbfa 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -373,7 +373,8 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct
i2c_msg *msg,
static int
gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
- unsigned short addr, u8 *buf, unsigned int len)
+ unsigned short addr, u8 *buf, unsigned int len,
+ u32 gmbus1_index)
{
unsigned int chunk_size = len;
u32 val, loop;
@@ -386,7 +387,7 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
I915_WRITE_FW(GMBUS3, val);
I915_WRITE_FW(GMBUS1,
- GMBUS_CYCLE_WAIT |
+ gmbus1_index | GMBUS_CYCLE_WAIT |
(chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
(addr << GMBUS_SLAVE_ADDR_SHIFT) |
GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
@@ -409,7 +410,8 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
}
static int
-gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
+gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
+u32 gmbus1_index)
{
u8 *buf = msg->buf;
unsigned int tx_size = msg->len;
@@ -419,7 +421,8 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct
i2c_msg *msg)
do {
len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
- ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len);
+ ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
+gmbus1_index);
if (ret)
return ret;
@@ -431,21 +434,21 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv,
struct i2c_msg *msg)
}
/*
- * The gmbus controller can combine a 1 or 2 byte write with a read that
- * immediately follows it by using an "INDEX" cycle.
+ * The gmbus controller can combine a 1 or 2 byte write with another read/write
+ * that immediately follows it by using an "INDEX" cycle.
*/
static bool
-gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
+gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
{
return (i + 1 < num &&
msgs[i].addr == msgs[i + 1].addr &&
!(msgs[i].flags & I2C_M_RD) &&
(msgs[i].len == 1 || msgs[i].len == 2) &&
- (msgs[i + 1].flags & I2C_M_RD));
+ msgs[i + 1].len > 0);
}
static int
-gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
+gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
{
u32 gmbus1_index = 0;
u32 gmbus5 = 0;
@@ -462,7 +465,10 @@ gmbus_xfer_index_read(struct drm_i915_private *dev_priv,
struct i2c_msg *msgs)
if (gmbus5)
I915_WRITE_FW(GMBUS5, gmbus5);
- ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
+ if (msgs[1].flags & I2C_M_RD)
+ ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
+ else
+ ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index);
/* Clear GMBUS5 after each index transfer */
if (gmbus5)
@@ -486,13 +492,13 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg
*msgs, int num)
for (; i < num; i += inc) {
inc = 1;
- if (gmbus_is_index_read(msgs, i, num)) {
- ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
- inc = 2; /* an index read is two msgs */
+ if (gmbus_is_index_xfer(msgs, i, num)) {
+ ret = gmbus_index_xfer(dev_priv, &msgs[i]);
+ inc = 2; /* an index transmission is two msgs */
} else if (msgs[i].flags & I2C_M_RD) {
ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
} else {
- ret = gmbus_xfer_write(dev_priv, &msgs[i]);
+ ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);
}
if (!ret)
--
2.15.1.424.g9478a66081-goog
___
Intel-gfx mailing list
Intel-gfx
[Intel-gfx] [PATCH v4 7/9] drm/i915: Add function to output Aksv over GMBUS
Once the Aksv is available in the PCH, we need to get it on the wire to
the receiver via DDC. The hardware doesn't allow us to read the value
directly, so we need to tell GMBUS to source the Aksv internally and
send it to the right offset on the receiver.
The way we do this is to initiate an indexed write where the index is
the Aksv register offset. We write dummy values to GMBUS3 as if we were
sending the key, and the hardware slips in the "real" values when it
goes out.
Changes in v2:
- None
Changes in v3:
- Uses new index write feature (Ville)
Changes in v4:
- None
Cc: Ville Syrjälä
Reviewed-by: Daniel Vetter
Signed-off-by: Sean Paul
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_i2c.c | 47 +---
3 files changed, 46 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bddd65839f60..6b39081c5e53 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -4049,6 +4049,7 @@ extern int intel_setup_gmbus(struct drm_i915_private
*dev_priv);
extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
unsigned int pin);
+extern int intel_gmbus_output_aksv(struct i2c_adapter *adapter);
extern struct i2c_adapter *
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4d66651219e3..35bcc6c308f3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3043,6 +3043,7 @@ enum i915_power_well_id {
# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /*
clock/port select */
+#define GMBUS_AKSV_SELECT(1<<11)
#define GMBUS_RATE_100KHZ(0<<8)
#define GMBUS_RATE_50KHZ (1<<8)
#define GMBUS_RATE_400KHZ(2<<8) /* reserved on Pineview */
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index d78ce758fbfa..318a68ea577e 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -30,6 +30,7 @@
#include
#include
#include
+#include
#include "intel_drv.h"
#include
#include "i915_drv.h"
@@ -478,7 +479,8 @@ gmbus_index_xfer(struct drm_i915_private *dev_priv, struct
i2c_msg *msgs)
}
static int
-do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
+do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
+ u32 gmbus0_source)
{
struct intel_gmbus *bus = container_of(adapter,
struct intel_gmbus,
@@ -488,7 +490,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg
*msgs, int num)
int ret = 0;
retry:
- I915_WRITE_FW(GMBUS0, bus->reg0);
+ I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0);
for (; i < num; i += inc) {
inc = 1;
@@ -606,7 +608,7 @@ gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg
*msgs, int num)
if (ret < 0)
bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
} else {
- ret = do_gmbus_xfer(adapter, msgs, num);
+ ret = do_gmbus_xfer(adapter, msgs, num, 0);
if (ret == -EAGAIN)
bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
}
@@ -616,6 +618,45 @@ gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg
*msgs, int num)
return ret;
}
+int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
+{
+ struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus,
+ adapter);
+ struct drm_i915_private *dev_priv = bus->dev_priv;
+ int ret;
+ u8 cmd = DRM_HDCP_DDC_AKSV ;
+ u8 buf[DRM_HDCP_KSV_LEN] = { 0 };
+ struct i2c_msg msgs[] = {
+ {
+ .addr = DRM_HDCP_DDC_ADDR,
+ .flags = 0,
+ .len = sizeof(cmd),
+ .buf = &cmd,
+ },
+ {
+ .addr = DRM_HDCP_DDC_ADDR,
+ .flags = 0,
+ .len = sizeof(buf),
+ .buf = buf,
+ }
+ };
+
+ intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
+ mutex_lock(&dev_priv->gmbus_mutex);
+
+ /*
+* In order to output Aksv to the receiver, use an indexed write to
+* pass the i2c command, and tell GMBUS to use the HW-provided value
+* instead of sourcing GMBUS3 for the data.
+*/
+ ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
+
+ mutex_unlock(&dev_priv->gmbus_mutex);
+ intel_display_power_put(dev_priv, POWE
[Intel-gfx] [PATCH v4 2/9] drm/i915: Add more control to wait_for routines
This patch adds a little more control to a couple wait_for routines such
that we can avoid open-coding read/wait/timeout patterns which:
- need the value of the register after the wait_for
- run arbitrary operation for the read portion
This patch also chooses the correct sleep function (based on
timers-howto.txt) for the polling interval the caller specifies.
Changes in v2:
- Added to the series
Changes in v3:
- Rebased on drm-intel-next-queued and the new Wmin/max _wait_for
- Removed msleep option
Changes in v4:
- Removed ; for OP in _wait_for (Chris)
- Moved reg_value definition above ret (Chris)
Suggested-by: Chris Wilson
Reviewed-by: Daniel Vetter
Reviewed-by: Chris Wilson
Signed-off-by: Sean Paul
---
drivers/gpu/drm/i915/intel_drv.h| 17 ++---
drivers/gpu/drm/i915/intel_uncore.c | 23 ---
drivers/gpu/drm/i915/intel_uncore.h | 14 +-
3 files changed, 39 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 64426d3e078e..cbfe306cc5b7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -41,20 +41,21 @@
#include
/**
- * _wait_for - magic (register) wait macro
+ * __wait_for - magic wait macro
*
- * Does the right thing for modeset paths when run under kdgb or similar atomic
- * contexts. Note that it's important that we check the condition again after
- * having timed out, since the timeout could be due to preemption or similar
and
- * we've never had a chance to check the condition before the timeout.
+ * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
+ * important that we check the condition again after having timed out, since
the
+ * timeout could be due to preemption or similar and we've never had a chance
to
+ * check the condition before the timeout.
*/
-#define _wait_for(COND, US, Wmin, Wmax) ({ \
+#define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
int ret__; \
might_sleep(); \
for (;;) { \
bool expired__ = time_after(jiffies, timeout__);\
+ OP; \
if (COND) { \
ret__ = 0; \
break; \
@@ -70,7 +71,9 @@
ret__; \
})
-#define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
+#define _wait_for(COND, US, Wmin, Wmax)__wait_for(, (COND), (US),
(Wmin), \
+ (Wmax))
+#define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
/* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
#if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index b4621271e7a2..2a3a77d398a0 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1770,12 +1770,14 @@ int __intel_wait_for_register_fw(struct
drm_i915_private *dev_priv,
}
/**
- * intel_wait_for_register - wait until register matches expected state
+ * __intel_wait_for_register - wait until register matches expected state
* @dev_priv: the i915 device
* @reg: the register to read
* @mask: mask to apply to register value
* @value: expected value
- * @timeout_ms: timeout in millisecond
+ * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
+ * @slow_timeout_ms: slow timeout in millisecond
+ * @out_value: optional placeholder to hold registry value
*
* This routine waits until the target register @reg contains the expected
* @value after applying the @mask, i.e. it waits until ::
@@ -1786,14 +1788,17 @@ int __intel_wait_for_register_fw(struct
drm_i915_private *dev_priv,
*
* Returns 0 if the register matches the desired condition, or -ETIMEOUT.
*/
-int intel_wait_for_register(struct drm_i915_private *dev_priv,
+int __intel_wait_for_register(struct drm_i915_private *dev_priv,
i915_reg_t reg,
u32 mask,
u32 value,
- unsigned int timeout_ms)
+ unsigned int fast_timeout_us,
+ unsigned int slow_timeout_ms,
+ u32 *out_value)
{
unsigned fw =
intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
+ u32 reg_value;
[Intel-gfx] [PATCH v4 3/9] drm: Add Content Protection property
This patch adds a new optional connector property to allow userspace to enable
protection over the content it is displaying. This will typically be implemented
by the driver using HDCP.
The property is a tri-state with the following values:
- OFF: Self explanatory, no content protection
- DESIRED: Userspace requests that the driver enable protection
- ENABLED: Once the driver has authenticated the link, it sets this value
The driver is responsible for downgrading ENABLED to DESIRED if the link becomes
unprotected. The driver should also maintain the desiredness of protection
across hotplug/dpms/suspend.
If this looks familiar, I posted [1] this 3 years ago. We have been using this
in ChromeOS across exynos, mediatek, and rockchip over that time.
Changes in v2:
- Pimp kerneldoc for content_protection_property (Daniel)
- Drop sysfs attribute
Changes in v3:
- None
Changes in v4:
- Changed kerneldoc to recommend userspace polling (Daniel)
- Changed kerneldoc to briefly describe how to attach the property (Daniel)
Reviewed-by: Daniel Vetter
Signed-off-by: Sean Paul
[1] https://lists.freedesktop.org/archives/dri-devel/2014-December/073336.html
---
drivers/gpu/drm/drm_atomic.c| 8 +
drivers/gpu/drm/drm_connector.c | 78 +
drivers/gpu/drm/drm_sysfs.c | 1 +
include/drm/drm_connector.h | 16 +
include/uapi/drm/drm_mode.h | 4 +++
5 files changed, 107 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index c2da5585e201..676025d755b2 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -1196,6 +1196,12 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
state->picture_aspect_ratio = val;
} else if (property == connector->scaling_mode_property) {
state->scaling_mode = val;
+ } else if (property == connector->content_protection_property) {
+ if (val == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
+ DRM_DEBUG_KMS("only drivers can set CP Enabled\n");
+ return -EINVAL;
+ }
+ state->content_protection = val;
} else if (connector->funcs->atomic_set_property) {
return connector->funcs->atomic_set_property(connector,
state, property, val);
@@ -1275,6 +1281,8 @@ drm_atomic_connector_get_property(struct drm_connector
*connector,
*val = state->picture_aspect_ratio;
} else if (property == connector->scaling_mode_property) {
*val = state->scaling_mode;
+ } else if (property == connector->content_protection_property) {
+ *val = state->content_protection;
} else if (connector->funcs->atomic_get_property) {
return connector->funcs->atomic_get_property(connector,
state, property, val);
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index f14b48e6e839..769213cb53e3 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -698,6 +698,13 @@ static const struct drm_prop_enum_list
drm_tv_subconnector_enum_list[] = {
DRM_ENUM_NAME_FN(drm_get_tv_subconnector_name,
drm_tv_subconnector_enum_list)
+static struct drm_prop_enum_list drm_cp_enum_list[] = {
+{ DRM_MODE_CONTENT_PROTECTION_OFF, "Off" },
+{ DRM_MODE_CONTENT_PROTECTION_DESIRED, "Desired" },
+{ DRM_MODE_CONTENT_PROTECTION_ENABLED, "Enabled" },
+};
+DRM_ENUM_NAME_FN(drm_get_content_protection_name, drm_cp_enum_list)
+
/**
* DOC: standard connector properties
*
@@ -764,6 +771,41 @@ DRM_ENUM_NAME_FN(drm_get_tv_subconnector_name,
* after modeset, the kernel driver may set this to "BAD" and issue a
* hotplug uevent. Drivers should update this value using
* drm_mode_connector_set_link_status_property().
+ * Content Protection:
+ * This property is used by userspace to request the kernel protect future
+ * content communicated over the link. When requested, kernel will apply
+ * the appropriate means of protection (most often HDCP), and use the
+ * property to tell userspace the protection is active.
+ *
+ * Drivers can set this up by calling
+ * drm_connector_attach_content_protection_property() on initialization.
+ *
+ * The value of this property can be one of the following:
+ *
+ * - DRM_MODE_CONTENT_PROTECTION_OFF = 0
+ * The link is not protected, content is transmitted in the clear.
+ * - DRM_MODE_CONTENT_PROTECTION_DESIRED = 1
+ * Userspace has requested content protection, but the link is not
+ * currently protected. When in this state, kernel should enable
+ * Content Protection as soon as possible.
+ * - DRM_MODE_CONTENT_PROTECTION_ENABLED = 2
+ * Userspace has requested content protect
[Intel-gfx] [PATCH v4 0/9] drm/i915: Implement HDCP
Welcome to version 4 of the patchset. I think we're nearing the finish line (hopefully) now. This set addresses the review feedback from v3. I applied some R-b's from v3 review, and converted others to Cc since other changes were made to the patch, and I didn't want to speak for reviewers. Thanks for all the review feedback! Sean Sean Paul (9): drm: Fix link-status kerneldoc line lengths drm/i915: Add more control to wait_for routines drm: Add Content Protection property drm: Add some HDCP related #defines drm/i915: Add HDCP framework + base implementation drm/i915: Make use of indexed write GMBUS feature drm/i915: Add function to output Aksv over GMBUS drm/i915: Implement HDCP for HDMI drm/i915: Implement HDCP for DisplayPort drivers/gpu/drm/drm_atomic.c | 8 + drivers/gpu/drm/drm_connector.c | 87 - drivers/gpu/drm/drm_sysfs.c | 1 + drivers/gpu/drm/i915/Makefile| 1 + drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 85 drivers/gpu/drm/i915/intel_atomic.c | 2 + drivers/gpu/drm/i915/intel_ddi.c | 36 ++ drivers/gpu/drm/i915/intel_display.c | 4 + drivers/gpu/drm/i915/intel_dp.c | 244 +++- drivers/gpu/drm/i915/intel_drv.h | 106 - drivers/gpu/drm/i915/intel_hdcp.c| 735 +++ drivers/gpu/drm/i915/intel_hdmi.c| 250 drivers/gpu/drm/i915/intel_i2c.c | 81 +++- drivers/gpu/drm/i915/intel_uncore.c | 23 +- drivers/gpu/drm/i915/intel_uncore.h | 14 +- include/drm/drm_connector.h | 16 + include/drm/drm_dp_helper.h | 17 + include/drm/drm_hdcp.h | 56 +++ include/uapi/drm/drm_mode.h | 4 + 20 files changed, 1728 insertions(+), 43 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_hdcp.c create mode 100644 include/drm/drm_hdcp.h -- 2.15.1.424.g9478a66081-goog ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 1/9] drm: Fix link-status kerneldoc line lengths
I'm adding some stuff below it and it's killing my editor's vibe. Changes in v2: - Added to the series Changes in v3: - None Changes in v4: - None Cc: Manasi Navare Acked-by: Daniel Vetter Signed-off-by: Sean Paul --- drivers/gpu/drm/drm_connector.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c index 704fc8934616..f14b48e6e839 100644 --- a/drivers/gpu/drm/drm_connector.c +++ b/drivers/gpu/drm/drm_connector.c @@ -759,10 +759,11 @@ DRM_ENUM_NAME_FN(drm_get_tv_subconnector_name, * should update this value using drm_mode_connector_set_tile_property(). * Userspace cannot change this property. * link-status: - * Connector link-status property to indicate the status of link. The default - * value of link-status is "GOOD". If something fails during or after modeset, - * the kernel driver may set this to "BAD" and issue a hotplug uevent. Drivers - * should update this value using drm_mode_connector_set_link_status_property(). + * Connector link-status property to indicate the status of link. The + * default value of link-status is "GOOD". If something fails during or + * after modeset, the kernel driver may set this to "BAD" and issue a + * hotplug uevent. Drivers should update this value using + * drm_mode_connector_set_link_status_property(). * * Connectors also have one standardized atomic property: * -- 2.15.1.424.g9478a66081-goog ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/5] drm/i915: Introduce a non-blocking power domain for vblank interrupts
On Wed, Dec 06, 2017 at 10:47:40PM +, Dhinakaran Pandiyan wrote:
> When DC states are enabled and PSR is active, the hardware enters DC5/DC6
> states resulting in frame counter resets. The frame counter resets mess
> up the vblank counting logic. So in order to disable DC states when
> vblank interrupts are required and to disallow DC states when vblanks
> interrupts are already enabled, introduce a new power domain. Since this
> power domain reference needs to be acquired and released in atomic context,
> the corresponding _get() and _put() methods skip the power_domain mutex.
\o/
>
> Signed-off-by: Dhinakaran Pandiyan
> ---
> drivers/gpu/drm/i915/i915_drv.h | 5 ++
> drivers/gpu/drm/i915/intel_drv.h| 3 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 125
> +++-
> 3 files changed, 128 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 18d42885205b..ba9107ec1ed1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -397,6 +397,7 @@ enum intel_display_power_domain {
> POWER_DOMAIN_AUX_C,
> POWER_DOMAIN_AUX_D,
> POWER_DOMAIN_GMBUS,
> + POWER_DOMAIN_VBLANK,
> POWER_DOMAIN_MODESET,
> POWER_DOMAIN_INIT,
>
> @@ -1475,6 +1476,10 @@ struct i915_power_well {
> bool has_vga:1;
> bool has_fuses:1;
> } hsw;
> + struct {
> + spinlock_t lock;
> + bool was_disabled;
> + } dc_off;
what about a more generic name here?
something like
+ struct {
+ spinlock_t lock;
+ bool was_disabled;
+ } atomic;
+ is_atomic; //or needs_atomic
so...
> };
> const struct i915_power_well_ops *ops;
> };
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 30f791f89d64..93ca503f18bb 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1865,7 +1865,8 @@ void chv_phy_powergate_lanes(struct intel_encoder
> *encoder,
>bool override, unsigned int mask);
> bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy
> phy,
> enum dpio_channel ch, bool override);
> -
> +bool intel_display_power_vblank_get(struct drm_i915_private *dev_priv);
> +void intel_display_power_vblank_put(struct drm_i915_private *dev_priv);
>
> /* intel_pm.c */
> void intel_init_clock_gating(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index f88f2c070c5f..f1807bd74242 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -126,6 +126,8 @@ intel_display_power_domain_str(enum
> intel_display_power_domain domain)
> return "AUX_D";
> case POWER_DOMAIN_GMBUS:
> return "GMBUS";
> + case POWER_DOMAIN_VBLANK:
> + return "VBLANK";
> case POWER_DOMAIN_INIT:
> return "INIT";
> case POWER_DOMAIN_MODESET:
> @@ -196,10 +198,17 @@ bool __intel_display_power_is_enabled(struct
> drm_i915_private *dev_priv,
> if (power_well->always_on)
> continue;
>
> - if (!power_well->hw_enabled) {
> + if (power_well->id == SKL_DISP_PW_DC_OFF)
> + spin_lock(&power_well->dc_off.lock);
... instead of a specif pw check here you would have
+ if (power_well->is_atomic)
+ spin_lock(&power_well->atomic.lock)
> +
> + if (!power_well->hw_enabled)
> is_enabled = false;
> +
> + if (power_well->id == SKL_DISP_PW_DC_OFF)
> + spin_unlock(&power_well->dc_off.lock);
> +
> + if (!is_enabled)
> break;
> - }
> }
>
> return is_enabled;
> @@ -724,6 +733,7 @@ static void gen9_dc_off_power_well_disable(struct
> drm_i915_private *dev_priv,
> skl_enable_dc6(dev_priv);
> else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
> gen9_enable_dc5(dev_priv);
> + power_well->dc_off.was_disabled = true;
> }
>
> static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
> @@ -1441,6 +1451,77 @@ static void chv_pipe_power_well_disable(struct
> drm_i915_private *dev_priv,
> chv_set_pipe_power_well(dev_priv, power_well, false);
> }
>
> +/**
> + * intel_display_power_vblank_get - acquire a VBLANK power domain reference
> atomically
> + * @dev_priv: i915 device instance
> + *
> + * This function gets a POWER_DOMAIN_VBLANK reference without blocking and
> + * returns true if the DC_OFF power well was disabled since this function was
> + * called the last
[Intel-gfx] ✓ Fi.CI.BAT: success for igt/perf_pmu: Tweak wait_for_rc6, yet again
== Series Details == Series: igt/perf_pmu: Tweak wait_for_rc6, yet again URL : https://patchwork.freedesktop.org/series/34998/ State : success == Summary == IGT patchset tested on top of latest successful build 1db12466cb5ad8483cd469753d2e312a62d717b7 meson: build a full dependency for lib_igt_perf with latest DRM-Tip kernel build CI_DRM_3468 95f37eb3ebfd drm-tip: 2017y-12m-06d-21h-01m-04s UTC integration manifest No testlist changes. Test debugfs_test: Subgroup read_all_entries: dmesg-fail -> DMESG-WARN (fi-elk-e7500) fdo#103989 fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:441s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:383s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:522s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:282s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:511s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:506s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:494s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:480s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:270s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:549s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:377s fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:259s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:485s fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:449s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:530s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:478s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:537s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:592s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:454s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:544s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:572s fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:519s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:499s fi-snb-2520m total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:549s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:417s Blacklisted hosts: fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:622s fi-glk-dsi total:288 pass:257 dwarn:0 dfail:0 fail:1 skip:30 time:492s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_606/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [RFC,1/5] igt_dummyload: Wrap function parameters into struct
== Series Details == Series: series starting with [RFC,1/5] igt_dummyload: Wrap function parameters into struct URL : https://patchwork.freedesktop.org/series/34997/ State : success == Summary == IGT patchset tested on top of latest successful build 1db12466cb5ad8483cd469753d2e312a62d717b7 meson: build a full dependency for lib_igt_perf with latest DRM-Tip kernel build CI_DRM_3468 95f37eb3ebfd drm-tip: 2017y-12m-06d-21h-01m-04s UTC integration manifest No testlist changes. Test gem_mmap_gtt: Subgroup basic-small-bo-tiledx: fail -> PASS (fi-gdg-551) fdo#102575 fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:441s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:394s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:538s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:284s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:511s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:519s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:500s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:484s fi-elk-e7500 total:224 pass:163 dwarn:14 dfail:1 fail:0 skip:45 fi-gdg-551 total:288 pass:179 dwarn:1 dfail:0 fail:0 skip:108 time:271s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:543s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:393s fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:267s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:495s fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:459s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:530s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:480s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:534s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:592s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:462s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:549s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:572s fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:524s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:516s fi-snb-2520m total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:554s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:424s Blacklisted hosts: fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:638s fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:495s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_605/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC i-g-t 4/5] igt_dummyload: Add preemptible parameter to spin batch
Quoting Antonio Argenziano (2017-12-06 23:03:45)
> void emit_recursive_batch(igt_spin_t *spin, int fd, igt_spin_opt_t opts);
> diff --git a/lib/igt_gt.c b/lib/igt_gt.c
> index 9ec3b0f6..48d40e61 100644
> --- a/lib/igt_gt.c
> +++ b/lib/igt_gt.c
> @@ -293,7 +293,8 @@ igt_hang_t igt_hang_ctx(int fd, igt_hang_opt_t opts)
> if ((opts.flags & HANG_ALLOW_BAN) == 0)
> context_set_ban(fd, opts.ctx, 0);
>
> - emit_recursive_batch(&spin, fd, (igt_spin_opt_t){opts.ctx, opts.ring,
> 0});
> + emit_recursive_batch(&spin, fd,
> + (igt_spin_opt_t){opts.ctx, opts.ring, 0, false});
The fun you can do with this is
emit_recursive_batch(&spin, fd, (igt_spin_opt_t){
.ctx = opts.ctx,
.engine = opts.ring,
/* anything unset is zero */
});
which should make the changes much more palatable. Bonus points for
currying common patterns.
-Chris
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] drm/vblank: Do not update vblank counts if vblanks are already disabled.
== Series Details == Series: series starting with [1/5] drm/vblank: Do not update vblank counts if vblanks are already disabled. URL : https://patchwork.freedesktop.org/series/34996/ State : failure == Summary == Series 34996v1 series starting with [1/5] drm/vblank: Do not update vblank counts if vblanks are already disabled. https://patchwork.freedesktop.org/api/1.0/series/34996/revisions/1/mbox/ Test debugfs_test: Subgroup read_all_entries: dmesg-fail -> PASS (fi-elk-e7500) fdo#103989 +1 Test gem_exec_reloc: Subgroup basic-cpu-read-active: pass -> FAIL (fi-gdg-551) fdo#102582 +3 Test kms_pipe_crc_basic: Subgroup read-crc-pipe-a: pass -> FAIL (fi-skl-6700k) Subgroup suspend-read-crc-pipe-b: pass -> INCOMPLETE (fi-snb-2520m) fdo#103713 Test kms_psr_sink_crc: Subgroup psr_basic: pass -> DMESG-WARN (fi-skl-6600u) pass -> DMESG-WARN (fi-skl-6700hq) pass -> DMESG-WARN (fi-kbl-7560u) pass -> DMESG-WARN (fi-kbl-r) fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:438s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:385s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:522s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:280s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:505s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:511s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:491s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:472s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:174 dwarn:1 dfail:0 fail:5 skip:108 time:270s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:542s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:385s fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:260s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:484s fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:444s fi-kbl-7560u total:288 pass:268 dwarn:1 dfail:0 fail:0 skip:19 time:526s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:478s fi-kbl-r total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:531s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:595s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:456s fi-skl-6600u total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:547s fi-skl-6700hqtotal:288 pass:261 dwarn:1 dfail:0 fail:0 skip:26 time:561s fi-skl-6700k total:288 pass:263 dwarn:0 dfail:0 fail:1 skip:24 time:519s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:496s fi-snb-2520m total:245 pass:211 dwarn:0 dfail:0 fail:0 skip:33 fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:423s Blacklisted hosts: fi-cnl-y total:249 pass:224 dwarn:0 dfail:0 fail:0 skip:24 fi-glk-dsi total:288 pass:186 dwarn:1 dfail:4 fail:0 skip:97 time:397s 95f37eb3ebfd65f500e0e80c6788df200f4c2f99 drm-tip: 2017y-12m-06d-21h-01m-04s UTC integration manifest 2864dbfcc343 drm/i915: Use the vblank power domain disallow or disable DC states. b0c13977ae82 drm/i915: Introduce a non-blocking power domain for vblank interrupts c32242c2a8b1 drm/i915: Use an atomic_t array to track power domain use count. 6de634ba83cf drm/vblank: Restoring vblank counts after device runtime PM events. 43170fd34edb drm/vblank: Do not update vblank counts if vblanks are already disabled. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7432/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 2/4] tools/intel_aubdump: Set addr_bits before write_header
write_header() uses addr_bits, so do the initialization earlier.
Also set the gen to a non-zero value in case of unknown device,
for use by a later patch.
Signed-off-by: Scott D Phillips
Reviewed-by: Jordan Justen
---
tools/aubdump.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/tools/aubdump.c b/tools/aubdump.c
index 6ba3cb66..5def6947 100644
--- a/tools/aubdump.c
+++ b/tools/aubdump.c
@@ -417,6 +417,15 @@ dump_execbuffer2(int fd, struct drm_i915_gem_execbuffer2
*execbuffer2)
}
if (gen == 0) {
gen = intel_gen(device);
+
+ /* If we don't know the device gen, then it probably is a
+* newer device. Set gen to some arbitrarily high number.
+*/
+ if (gen == 0)
+ gen = ;
+
+ addr_bits = gen >= 8 ? 48 : 32;
+
write_header();
if (verbose)
@@ -425,11 +434,6 @@ dump_execbuffer2(int fd, struct drm_i915_gem_execbuffer2
*execbuffer2)
filename, device, gen);
}
- /* If we don't know the device gen, then it probably is a
-* newer device which uses 48-bit addresses.
-*/
- addr_bits = (gen >= 8 || gen == 0) ? 48 : 32;
-
if (verbose)
printf("Dumping execbuffer2:\n");
--
2.14.3
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[Intel-gfx] [PATCH igt] igt/perf_pmu: Tweak wait_for_rc6, yet again
Still CI remains obstinate that RC6 is not smoothly incrementing during
the sample period. Tweak the wait_for_rc6() to first wait for the
initial Evaluation Interval before polling.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/perf_pmu.c | 15 +++
tests/pm_rc6_residency.c | 15 +++
2 files changed, 22 insertions(+), 8 deletions(-)
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index ff6568221..917832d1b 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -1000,13 +1000,20 @@ static bool wait_for_rc6(int fd)
struct timespec tv = {};
uint64_t start, now;
- start = pmu_read_single(fd);
+ /* First wait for roughly an RC6 Evaluation Interval */
+ usleep(160 * 1000);
+
+ /* Then poll for RC6 to start ticking */
+ now = pmu_read_single(fd);
do {
- usleep(50);
+ start = now;
+ usleep(5000);
now = pmu_read_single(fd);
- } while (start == now && !igt_seconds_elapsed(&tv));
+ if (now - start > 2e6)
+ return true;
+ } while (!igt_seconds_elapsed(&tv));
- return start != now;
+ return false;
}
static void
diff --git a/tests/pm_rc6_residency.c b/tests/pm_rc6_residency.c
index 16f4b1421..7cc62dac8 100644
--- a/tests/pm_rc6_residency.c
+++ b/tests/pm_rc6_residency.c
@@ -170,13 +170,20 @@ static bool wait_for_rc6(void)
struct timespec tv = {};
unsigned long start, now;
- start = read_rc6_residency("rc6");
+ /* First wait for roughly an RC6 Evaluation Interval */
+usleep(160 * 1000);
+
+/* Then poll for RC6 to start ticking */
+ now = read_rc6_residency("rc6");
do {
- usleep(50);
+ start = now;
+ usleep(5000);
now = read_rc6_residency("rc6");
- } while (now == start && !igt_seconds_elapsed(&tv));
+ if (now - start > 2)
+ return true;
+ } while (!igt_seconds_elapsed(&tv));
- return now != start;
+ return false;
}
igt_main
--
2.15.1
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t v2 4/4] tools/intel_aubdump: Add ability to simulate execlist submission
Newer devices do not have the legacy ring buffer submission model,
so aub files generated using that model cannot be handled by some
internal tools. The execlist submission modeled by this change is
pretty simplistic, using GGTT only and synchronizing after every
batch.
v2:
- Move addr_bits init in separate patch (Jordan)
- Don't change GTT entries in gen < 10
Signed-off-by: Scott D Phillips
Reviewed-by: Jordan Justen
Tested-by: Jordan Justen
---
tools/aubdump.c | 405
1 file changed, 382 insertions(+), 23 deletions(-)
diff --git a/tools/aubdump.c b/tools/aubdump.c
index 5def6947..2a37c1a7 100644
--- a/tools/aubdump.c
+++ b/tools/aubdump.c
@@ -46,6 +46,177 @@
#define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0]))
#endif
+#ifndef ALIGN
+#define ALIGN(x, y) (((x) + (y)-1) & ~((y)-1))
+#endif
+
+#define min(a, b) ({ \
+ typeof(a) _a = (a); \
+ typeof(b) _b = (b); \
+ _a < _b ? _a : _b; \
+})
+
+#define HWS_PGA_RCSUNIT0x02080
+#define HWS_PGA_VCSUNIT0 0x12080
+#define HWS_PGA_BCSUNIT0x22080
+
+#define GFX_MODE_RCSUNIT 0x0229c
+#define GFX_MODE_VCSUNIT0 0x1229c
+#define GFX_MODE_BCSUNIT 0x2229c
+
+#define EXECLIST_SUBMITPORT_RCSUNIT0x02230
+#define EXECLIST_SUBMITPORT_VCSUNIT0 0x12230
+#define EXECLIST_SUBMITPORT_BCSUNIT0x22230
+
+#define EXECLIST_STATUS_RCSUNIT0x02234
+#define EXECLIST_STATUS_VCSUNIT0 0x12234
+#define EXECLIST_STATUS_BCSUNIT0x22234
+
+#define MEMORY_MAP_SIZE (64 /* MiB */ * 1024 * 1024)
+
+#define PTE_SIZE 4
+#define GEN8_PTE_SIZE 8
+
+#define NUM_PT_ENTRIES (ALIGN(MEMORY_MAP_SIZE, 4096) / 4096)
+#define PT_SIZE ALIGN(NUM_PT_ENTRIES * GEN8_PTE_SIZE, 4096)
+
+#define RING_SIZE (1 * 4096)
+#define PPHWSP_SIZE(1 * 4096)
+#define GEN10_LR_CONTEXT_RENDER_SIZE (19 * 4096)
+#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * 4096)
+
+#define STATIC_GGTT_MAP_START 0
+
+#define RENDER_RING_ADDR STATIC_GGTT_MAP_START
+#define RENDER_CONTEXT_ADDR (RENDER_RING_ADDR + RING_SIZE)
+
+#define BLITTER_RING_ADDR (RENDER_CONTEXT_ADDR + PPHWSP_SIZE +
GEN10_LR_CONTEXT_RENDER_SIZE)
+#define BLITTER_CONTEXT_ADDR (BLITTER_RING_ADDR + RING_SIZE)
+
+#define VIDEO_RING_ADDR (BLITTER_CONTEXT_ADDR + PPHWSP_SIZE +
GEN8_LR_CONTEXT_OTHER_SIZE)
+#define VIDEO_CONTEXT_ADDR (VIDEO_RING_ADDR + RING_SIZE)
+
+#define STATIC_GGTT_MAP_END (VIDEO_CONTEXT_ADDR + PPHWSP_SIZE +
GEN8_LR_CONTEXT_OTHER_SIZE)
+#define STATIC_GGTT_MAP_SIZE (STATIC_GGTT_MAP_END - STATIC_GGTT_MAP_START)
+
+#define CONTEXT_FLAGS (0x229) /* Normal Priority | L3-LLC Coherency |
+ Legacy Context with no 64 bit VA support | Valid */
+
+#define RENDER_CONTEXT_DESCRIPTOR ((uint64_t)1 << 32 | RENDER_CONTEXT_ADDR |
CONTEXT_FLAGS)
+#define BLITTER_CONTEXT_DESCRIPTOR ((uint64_t)2 << 32 | BLITTER_CONTEXT_ADDR |
CONTEXT_FLAGS)
+#define VIDEO_CONTEXT_DESCRIPTOR ((uint64_t)3 << 32 | VIDEO_CONTEXT_ADDR |
CONTEXT_FLAGS)
+
+static const uint32_t render_context_init[GEN10_LR_CONTEXT_RENDER_SIZE /
+ sizeof(uint32_t)] = {
+ 0 /* MI_NOOP */,
+ 0x1100101B /* MI_LOAD_REGISTER_IMM */,
+ 0x2244 /* CONTEXT_CONTROL */, 0x90009 /* Inhibit Synchronous
Context Switch | Engine Context Restore Inhibit */,
+ 0x2034 /* RING_HEAD */, 0,
+ 0x2030 /* RING_TAIL */, 0,
+ 0x2038 /* RING_BUFFER_START */, RENDER_RING_ADDR,
+ 0x203C /* RING_BUFFER_CONTROL */, (RING_SIZE - 4096) | 1 /*
Buffer Length | Ring Buffer Enable */,
+ 0x2168 /* BB_HEAD_U */, 0,
+ 0x2140 /* BB_HEAD_L */, 0,
+ 0x2110 /* BB_STATE */, 0,
+ 0x211C /* SECOND_BB_HEAD_U */, 0,
+ 0x2114 /* SECOND_BB_HEAD_L */, 0,
+ 0x2118 /* SECOND_BB_STATE */, 0,
+ 0x21C0 /* BB_PER_CTX_PTR */,0,
+ 0x21C4 /* RCS_INDIRECT_CTX */, 0,
+ 0x21C8 /* RCS_INDIRECT_CTX_OFFSET */, 0,
+ /* MI_NOOP */
+ 0, 0,
+
+ 0 /* MI_NOOP */,
+ 0x11001011 /* MI_LOAD_REGISTER_IMM */,
+ 0x23A8 /* CTX_TIMESTAMP */, 0,
+ 0x228C /* PDP3_UDW */, 0,
+ 0x2288 /* PDP3_LDW */, 0,
+ 0x2284 /* PDP2_UDW */, 0,
+ 0x2280 /* PDP2_LDW */, 0,
+ 0x227C /* PDP1_UDW */, 0,
+ 0x2278 /* PDP1_LDW */, 0,
+ 0x2274 /* PDP0_UDW */, 0,
+ 0x2270 /* PDP0_LDW */, 0,
+ /* MI_NOOP */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+ 0 /* MI_NOOP */,
+ 0x1101 /* MI_LOAD_REGISTER_IMM */,
+ 0x20C8 /* R_PWR_CLK_STATE */, 0x7FFF,
+ 0x0501 /* MI_BATCH_BUFFER_END */
+};
+
+static const uint32_t blitter_context_init[GEN8_LR_CONTEXT_OTHER_SIZE /
+
[Intel-gfx] [PATCH i-g-t 3/4] lib/intel_aub: Add new MEM_TRACE commands
The memtrace aub commands are similar to the existing ones, but different. Notably memtrace has commands for register write and poll. Signed-off-by: Scott D Phillips --- lib/intel_aub.h | 26 ++ 1 file changed, 26 insertions(+) diff --git a/lib/intel_aub.h b/lib/intel_aub.h index 5f0aba8e..9ca548ed 100644 --- a/lib/intel_aub.h +++ b/lib/intel_aub.h @@ -49,6 +49,12 @@ #define CMD_AUB(7 << 29) #define CMD_AUB_HEADER (CMD_AUB | (1 << 23) | (0x05 << 16)) + +#define CMD_MEM_TRACE_REGISTER_POLL(CMD_AUB | (0x2e << 23) | (0x02 << 16)) +#define CMD_MEM_TRACE_REGISTER_WRITE (CMD_AUB | (0x2e << 23) | (0x03 << 16)) +#define CMD_MEM_TRACE_MEMORY_WRITE (CMD_AUB | (0x2e << 23) | (0x06 << 16)) +#define CMD_MEM_TRACE_VERSION (CMD_AUB | (0x2e << 23) | (0x0e << 16)) + /* DW1 */ # define AUB_HEADER_MAJOR_SHIFT24 # define AUB_HEADER_MINOR_SHIFT16 @@ -92,8 +98,28 @@ #define AUB_TRACE_MEMTYPE_PCI (3 << 16) #define AUB_TRACE_MEMTYPE_GTT_ENTRY (4 << 16) +#define AUB_MEM_TRACE_VERSION_FILE_VERSION 1 + /* DW2 */ +#define AUB_MEM_TRACE_VERSION_DEVICE_MASK 0xff00 +#define AUB_MEM_TRACE_VERSION_DEVICE_CNL (15 << 8) + +#define AUB_MEM_TRACE_VERSION_METHOD_MASK 0x000c +#define AUB_MEM_TRACE_VERSION_METHOD_PHY (1 << 18) + +#define AUB_MEM_TRACE_REGISTER_SIZE_MASK 0x000f +#define AUB_MEM_TRACE_REGISTER_SIZE_DWORD (2 << 16) + +#define AUB_MEM_TRACE_REGISTER_SPACE_MASK 0xf000 +#define AUB_MEM_TRACE_REGISTER_SPACE_MMIO (0 << 28) + +/* DW3 */ + +#define AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_MASK0xf000 +#define AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_LOCAL (1 << 28) +#define AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_GGTT_ENTRY (4 << 28) + /** * aub_state_struct_type enum values are encoded with the top 16 bits * representing the type to be delivered to the .aub file, and the bottom 16 -- 2.14.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 1/4] lib: copy intel_aub.h from libdrm
No functionality related to aub is provided by libdrm aside from
intel_aub.h which somewhat defines the file format. Move the
header into this project to ease aub-related development.
Signed-off-by: Scott D Phillips
---
lib/Makefile.am | 1 -
lib/{stubs/drm => }/intel_aub.h | 0
lib/rendercopy_gen8.c | 2 +-
lib/rendercopy_gen9.c | 2 +-
lib/stubs/drm/README| 6 +++---
5 files changed, 5 insertions(+), 6 deletions(-)
rename lib/{stubs/drm => }/intel_aub.h (100%)
diff --git a/lib/Makefile.am b/lib/Makefile.am
index c19055ac..ab9eefe6 100644
--- a/lib/Makefile.am
+++ b/lib/Makefile.am
@@ -23,7 +23,6 @@ endif
if !HAVE_LIBDRM_INTEL
libintel_tools_la_SOURCES += \
-stubs/drm/intel_aub.h \
stubs/drm/intel_bufmgr.c \
stubs/drm/intel_bufmgr.h
endif
diff --git a/lib/stubs/drm/intel_aub.h b/lib/intel_aub.h
similarity index 100%
rename from lib/stubs/drm/intel_aub.h
rename to lib/intel_aub.h
diff --git a/lib/rendercopy_gen8.c b/lib/rendercopy_gen8.c
index a7fc2c48..fe3fedfa 100644
--- a/lib/rendercopy_gen8.c
+++ b/lib/rendercopy_gen8.c
@@ -22,7 +22,7 @@
#include "intel_reg.h"
#include "igt_aux.h"
-#include
+#include "intel_aub.h"
#define VERTEX_SIZE (3*4)
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 95374807..e646e97f 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -23,7 +23,7 @@
#include "intel_reg.h"
#include "igt_aux.h"
-#include
+#include "intel_aub.h"
#define VERTEX_SIZE (3*4)
diff --git a/lib/stubs/drm/README b/lib/stubs/drm/README
index 118837c3..79f2b5f6 100644
--- a/lib/stubs/drm/README
+++ b/lib/stubs/drm/README
@@ -1,4 +1,4 @@
-intel_bufmgr.h and intel_aub.h are a local copy of the files provided by
libdrm.
+intel_bufmgr.h is a local copy of the file provided by libdrm
(intel/intel_bufmgr.h).
-Before releasing i-g-t a current copy of the files should be copied into this
-directory of i-g-t.
+Before releasing i-g-t a current copy of intel_bufmgr.h should be copied into
+this directory of i-g-t.
--
2.14.3
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC i-g-t 3/5] lib/igt_hang_ctx: Use dummyload batch to hang ctx.
To hang a context we were effectively reimplementing a spinning batch
and never stopping it. This patch reuses the recursive batch from
igt_dummyload to hang a context.
Cc: Chris Wilson
Signed-off-by: Antonio Argenziano
---
lib/igt_dummyload.c | 4 +++-
lib/igt_dummyload.h | 2 ++
lib/igt_gt.c| 38 --
lib/igt_gt.h| 1 +
4 files changed, 10 insertions(+), 35 deletions(-)
diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index fee311f7..0bb02e5b 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -69,7 +69,7 @@ fill_reloc(struct drm_i915_gem_relocation_entry *reloc,
reloc->write_domain = write_domains;
}
-static void emit_recursive_batch(igt_spin_t *spin,
+void emit_recursive_batch(igt_spin_t *spin,
int fd, igt_spin_opt_t opts)
{
#define SCRATCH 0
@@ -168,6 +168,8 @@ static void emit_recursive_batch(igt_spin_t *spin,
execbuf.flags = engines[i];
gem_execbuf(fd, &execbuf);
}
+
+ spin->spinning_offset = obj->offset;
}
igt_spin_t *
diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
index 76ccd37a..2f3f2ebf 100644
--- a/lib/igt_dummyload.h
+++ b/lib/igt_dummyload.h
@@ -35,6 +35,7 @@ typedef struct igt_spin {
timer_t timer;
struct igt_list link;
uint32_t *batch;
+ uint64_t spinning_offset;
} igt_spin_t;
typedef struct igt_spin_opt {
@@ -43,6 +44,7 @@ typedef struct igt_spin_opt {
uint32_t dep;
} igt_spin_opt_t;
+void emit_recursive_batch(igt_spin_t *spin, int fd, igt_spin_opt_t opts);
igt_spin_t *__igt_spin_batch_new(int fd, igt_spin_opt_t opts);
igt_spin_t *igt_spin_batch_new(int fd, igt_spin_opt_t opts);
void igt_spin_batch_set_timeout(igt_spin_t *spin, int64_t ns);
diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index c9a2b508..9ec3b0f6 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -266,13 +266,9 @@ static bool has_ctx_exec(int fd, unsigned ring, uint32_t
ctx)
*/
igt_hang_t igt_hang_ctx(int fd, igt_hang_opt_t opts)
{
- struct drm_i915_gem_relocation_entry reloc;
- struct drm_i915_gem_execbuffer2 execbuf;
- struct drm_i915_gem_exec_object2 exec;
struct drm_i915_gem_context_param param;
- uint32_t b[16];
unsigned ban;
- unsigned len;
+ igt_spin_t spin;
igt_require_hang_ring(fd, opts.ring);
@@ -297,38 +293,12 @@ igt_hang_t igt_hang_ctx(int fd, igt_hang_opt_t opts)
if ((opts.flags & HANG_ALLOW_BAN) == 0)
context_set_ban(fd, opts.ctx, 0);
- memset(&reloc, 0, sizeof(reloc));
- memset(&exec, 0, sizeof(exec));
- memset(&execbuf, 0, sizeof(execbuf));
-
- exec.handle = gem_create(fd, 4096);
- exec.relocation_count = 1;
- exec.relocs_ptr = to_user_pointer(&reloc);
-
- memset(b, 0xc5, sizeof(b));
-
- len = 2;
- if (intel_gen(intel_get_drm_devid(fd)) >= 8)
- len++;
- b[0] = MI_BATCH_BUFFER_START | (len - 2);
- b[len] = MI_BATCH_BUFFER_END;
- b[len+1] = MI_NOOP;
- gem_write(fd, exec.handle, 0, b, sizeof(b));
-
- reloc.offset = sizeof(uint32_t);
- reloc.target_handle = exec.handle;
- reloc.read_domains = I915_GEM_DOMAIN_COMMAND;
-
- execbuf.buffers_ptr = to_user_pointer(&exec);
- execbuf.buffer_count = 1;
- execbuf.flags = opts.ring;
- i915_execbuffer2_set_context_id(execbuf, opts.ctx);
- gem_execbuf(fd, &execbuf);
+ emit_recursive_batch(&spin, fd, (igt_spin_opt_t){opts.ctx, opts.ring,
0});
if (opts.offset)
- *opts.offset = exec.offset;
+ *opts.offset = spin.spinning_offset;
- return (igt_hang_t){ exec.handle, opts.ctx, ban, opts.flags };
+ return (igt_hang_t){ spin.handle, opts.ctx, ban, opts.flags };
}
/**
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 55de04d5..3f3e2d96 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -26,6 +26,7 @@
#include "igt_debugfs.h"
#include "igt_core.h"
+#include "igt_dummyload.h"
void igt_require_hang_ring(int fd, int ring);
--
2.14.2
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC i-g-t 2/5] igt_hang_ctx: Wrap parameters into struct
This patch wraps the parameters for the function used to hang a context
(igt_hang_ctx) into a struct to cleanup the interface and make it easier
to add more parameters.
Cc: Chris Wilson
Signed-off-by: Antonio Argenziano
---
lib/igt_dummyload.c | 25 -
lib/igt_gt.c| 41 +++--
lib/igt_gt.h| 14 +-
tests/drv_hangman.c | 2 +-
tests/gem_reset_stats.c | 4 ++--
tests/gem_softpin.c | 2 +-
6 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 37ae5a03..fee311f7 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -70,8 +70,7 @@ fill_reloc(struct drm_i915_gem_relocation_entry *reloc,
}
static void emit_recursive_batch(igt_spin_t *spin,
-int fd, uint32_t ctx, unsigned engine,
-uint32_t dep)
+int fd, igt_spin_opt_t opts)
{
#define SCRATCH 0
#define BATCH 1
@@ -85,13 +84,13 @@ static void emit_recursive_batch(igt_spin_t *spin,
int i;
nengine = 0;
- if (engine == -1) {
- for_each_engine(fd, engine)
- if (engine)
- engines[nengine++] = engine;
+ if (opts.engine == -1) {
+ for_each_engine(fd, opts.engine)
+ if (opts.engine)
+ engines[nengine++] = opts.engine;
} else {
- gem_require_ring(fd, engine);
- engines[nengine++] = engine;
+ gem_require_ring(fd, opts.engine);
+ engines[nengine++] = opts.engine;
}
igt_require(nengine);
@@ -109,11 +108,11 @@ static void emit_recursive_batch(igt_spin_t *spin,
I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
execbuf.buffer_count++;
- if (dep) {
+ if (opts.dep) {
/* dummy write to dependency */
- obj[SCRATCH].handle = dep;
+ obj[SCRATCH].handle = opts.dep;
fill_reloc(&relocs[obj[BATCH].relocation_count++],
- dep, 1020,
+ opts.dep, 1020,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER);
execbuf.buffer_count++;
@@ -162,7 +161,7 @@ static void emit_recursive_batch(igt_spin_t *spin,
obj[BATCH].relocs_ptr = to_user_pointer(relocs);
execbuf.buffers_ptr = to_user_pointer(obj + (2 - execbuf.buffer_count));
- execbuf.rsvd1 = ctx;
+ execbuf.rsvd1 = opts.ctx;
for (i = 0; i < nengine; i++) {
execbuf.flags &= ~ENGINE_MASK;
@@ -179,7 +178,7 @@ __igt_spin_batch_new(int fd, igt_spin_opt_t opts)
spin = calloc(1, sizeof(struct igt_spin));
igt_assert(spin);
- emit_recursive_batch(spin, fd, opts.ctx, opts.engine, opts.dep);
+ emit_recursive_batch(spin, fd, opts);
igt_assert(gem_bo_busy(fd, spin->handle));
igt_list_add(&spin->link, &spin_list);
diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index 4a8f541f..c9a2b508 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -250,10 +250,11 @@ static bool has_ctx_exec(int fd, unsigned ring, uint32_t
ctx)
/**
* igt_hang_ring_ctx:
* @fd: open i915 drm file descriptor
- * @ctx: the contxt specifier
- * @ring: execbuf ring flag
- * @flags: set of flags to control execution
- * @offset: The resultant gtt offset of the exec obj
+ * @opts: struct wrapping paramters used in this function:
+ * - ctx: the context specifier
+ * - ring: execbuf ring flag
+ * - flags: set of flags to control execution
+ * - offset: The resultant gtt offset of the exec obj
*
* This helper function injects a hanging batch associated with @ctx into
@ring.
* It returns a #igt_hang_t structure which must be passed to
@@ -263,11 +264,7 @@ static bool has_ctx_exec(int fd, unsigned ring, uint32_t
ctx)
* Returns:
* Structure with helper internal state for igt_post_hang_ring().
*/
-igt_hang_t igt_hang_ctx(int fd,
- uint32_t ctx,
- int ring,
- unsigned flags,
- uint64_t *offset)
+igt_hang_t igt_hang_ctx(int fd, igt_hang_opt_t opts)
{
struct drm_i915_gem_relocation_entry reloc;
struct drm_i915_gem_execbuffer2 execbuf;
@@ -277,15 +274,15 @@ igt_hang_t igt_hang_ctx(int fd,
unsigned ban;
unsigned len;
- igt_require_hang_ring(fd, ring);
+ igt_require_hang_ring(fd, opts.ring);
/* check if non-default ctx submission is allowed */
- igt_require(ctx == 0 || has_ctx_exec(fd, ring, ctx));
+ igt_require(opts.ctx == 0 || has_ctx_exec(fd, opts.ring, opts.ctx));
- param.ctx_id = ctx;
+ param.ctx_id = opts.ctx;
param.size = 0;
- if ((flags &
[Intel-gfx] [RFC i-g-t 5/5] igt_hang_ctx: Add preemptible parameter
This patch adds a parameter to make the hanging context pre-emptible.
Cc: Chris Wilson
Signed-off-by: Antonio Argenziano
---
lib/igt_gt.c| 4 ++--
lib/igt_gt.h| 1 +
tests/drv_hangman.c | 2 +-
tests/gem_reset_stats.c | 2 +-
tests/gem_softpin.c | 2 +-
5 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index 48d40e61..bc33e087 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -294,7 +294,7 @@ igt_hang_t igt_hang_ctx(int fd, igt_hang_opt_t opts)
context_set_ban(fd, opts.ctx, 0);
emit_recursive_batch(&spin, fd,
- (igt_spin_opt_t){opts.ctx, opts.ring, 0, false});
+ (igt_spin_opt_t){opts.ctx, opts.ring, 0,
opts.preemptible});
if (opts.offset)
*opts.offset = spin.spinning_offset;
@@ -316,7 +316,7 @@ igt_hang_t igt_hang_ctx(int fd, igt_hang_opt_t opts)
*/
igt_hang_t igt_hang_ring(int fd, int ring)
{
- return igt_hang_ctx(fd, (igt_hang_opt_t){0, ring, 0, NULL});
+ return igt_hang_ctx(fd, (igt_hang_opt_t){0, ring, 0, NULL, false});
}
/**
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 3f3e2d96..17fcee33 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -42,6 +42,7 @@ typedef struct igt_hang_opt {
int ring;
unsigned flags;
uint64_t *offset;
+ bool preemptible;
} igt_hang_opt_t;
igt_hang_t igt_allow_hang(int fd, unsigned ctx, unsigned flags);
diff --git a/tests/drv_hangman.c b/tests/drv_hangman.c
index 75fb2364..e9227a84 100644
--- a/tests/drv_hangman.c
+++ b/tests/drv_hangman.c
@@ -187,7 +187,7 @@ static void test_error_state_capture(unsigned ring_id,
clear_error_state();
- hang = igt_hang_ctx(device, (igt_hang_opt_t){0, ring_id,
HANG_ALLOW_CAPTURE, &offset});
+ hang = igt_hang_ctx(device, (igt_hang_opt_t){0, ring_id,
HANG_ALLOW_CAPTURE, &offset, false});
batch = gem_mmap__cpu(device, hang.handle, 0, 4096, PROT_READ);
gem_set_domain(device, hang.handle, I915_GEM_DOMAIN_CPU, 0);
igt_post_hang_ring(device, hang);
diff --git a/tests/gem_reset_stats.c b/tests/gem_reset_stats.c
index 19174307..c5024157 100644
--- a/tests/gem_reset_stats.c
+++ b/tests/gem_reset_stats.c
@@ -161,7 +161,7 @@ static void inject_hang(int fd, uint32_t ctx,
clock_gettime(CLOCK_MONOTONIC, &ts_injected);
- hang = igt_hang_ctx(fd, (igt_hang_opt_t){ctx, e->exec_id | e->flags,
flags & BAN, NULL});
+ hang = igt_hang_ctx(fd, (igt_hang_opt_t){ctx, e->exec_id | e->flags,
flags & BAN, NULL, false});
if ((flags & ASYNC) == 0)
igt_post_hang_ring(fd, hang);
}
diff --git a/tests/gem_softpin.c b/tests/gem_softpin.c
index 9256138a..07b5712d 100644
--- a/tests/gem_softpin.c
+++ b/tests/gem_softpin.c
@@ -359,7 +359,7 @@ static void test_evict_hang(int fd)
execbuf.buffers_ptr = to_user_pointer(&object);
execbuf.buffer_count = 1;
- hang = igt_hang_ctx(fd, (igt_hang_opt_t){0, 0, 0, (uint64_t
*)&expected});
+ hang = igt_hang_ctx(fd, (igt_hang_opt_t){0, 0, 0, (uint64_t
*)&expected, false});
object.offset = expected;
object.flags = EXEC_OBJECT_PINNED;
--
2.14.2
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC i-g-t 4/5] igt_dummyload: Add preemptible parameter to spin batch
This patch adds a parameter that allows to make the spinning batch
pre-emptible by adding an arbitration point to the spinning loop.
Cc: Chris Wilson
Signed-off-by: Antonio Argenziano
---
lib/igt_dummyload.c | 4 ++--
lib/igt_dummyload.h | 1 +
lib/igt_gt.c | 3 ++-
tests/drv_missed_irq.c| 2 +-
tests/gem_busy.c | 10 +-
tests/gem_exec_fence.c| 14 +++---
tests/gem_exec_latency.c | 2 +-
tests/gem_exec_nop.c | 2 +-
tests/gem_exec_reloc.c| 6 +++---
tests/gem_exec_schedule.c | 8
tests/gem_exec_suspend.c | 2 +-
tests/gem_shrink.c| 4 ++--
tests/gem_spin_batch.c| 4 ++--
tests/gem_wait.c | 2 +-
tests/kms_busy.c | 6 +++---
tests/kms_cursor_legacy.c | 2 +-
tests/perf_pmu.c | 18 +-
tests/pm_rps.c| 2 +-
18 files changed, 47 insertions(+), 45 deletions(-)
diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 0bb02e5b..cf5b29d5 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -121,8 +121,8 @@ void emit_recursive_batch(igt_spin_t *spin,
spin->batch = batch;
spin->handle = obj[BATCH].handle;
- /* Allow ourselves to be preempted */
- *batch++ = MI_ARB_CHK;
+ if (opts.preemptible)
+ *batch++ = MI_ARB_CHK; /* Allow ourselves to be preempted */
/* Pad with a few nops so that we do not completely hog the system.
*
diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
index 2f3f2ebf..c285ece8 100644
--- a/lib/igt_dummyload.h
+++ b/lib/igt_dummyload.h
@@ -42,6 +42,7 @@ typedef struct igt_spin_opt {
uint32_t ctx;
unsigned engine;
uint32_t dep;
+ bool preemptible;
} igt_spin_opt_t;
void emit_recursive_batch(igt_spin_t *spin, int fd, igt_spin_opt_t opts);
diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index 9ec3b0f6..48d40e61 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -293,7 +293,8 @@ igt_hang_t igt_hang_ctx(int fd, igt_hang_opt_t opts)
if ((opts.flags & HANG_ALLOW_BAN) == 0)
context_set_ban(fd, opts.ctx, 0);
- emit_recursive_batch(&spin, fd, (igt_spin_opt_t){opts.ctx, opts.ring,
0});
+ emit_recursive_batch(&spin, fd,
+ (igt_spin_opt_t){opts.ctx, opts.ring, 0, false});
if (opts.offset)
*opts.offset = spin.spinning_offset;
diff --git a/tests/drv_missed_irq.c b/tests/drv_missed_irq.c
index db67367b..308b9b60 100644
--- a/tests/drv_missed_irq.c
+++ b/tests/drv_missed_irq.c
@@ -33,7 +33,7 @@ IGT_TEST_DESCRIPTION("Inject missed interrupts and make sure
they are caught");
static void trigger_missed_interrupt(int fd, unsigned ring)
{
- igt_spin_t *spin = __igt_spin_batch_new(fd, (igt_spin_opt_t){0, ring,
0});
+ igt_spin_t *spin = __igt_spin_batch_new(fd, (igt_spin_opt_t){0, ring,
0, true});
igt_fork(child, 1) {
/* We are now a low priority child on the *same* CPU as the
diff --git a/tests/gem_busy.c b/tests/gem_busy.c
index 119db4e2..b581a490 100644
--- a/tests/gem_busy.c
+++ b/tests/gem_busy.c
@@ -113,7 +113,7 @@ static void semaphore(int fd, unsigned ring, uint32_t flags)
/* Create a long running batch which we can use to hog the GPU */
handle[BUSY] = gem_create(fd, 4096);
- spin = igt_spin_batch_new(fd, (igt_spin_opt_t){0, ring, handle[BUSY]});
+ spin = igt_spin_batch_new(fd, (igt_spin_opt_t){0, ring, handle[BUSY],
true});
/* Queue a batch after the busy, it should block and remain "busy" */
igt_assert(exec_noop(fd, handle, ring | flags, false));
@@ -460,7 +460,7 @@ static void close_race(int fd)
for (i = 0; i < nhandles; i++) {
spin[i] = igt_spin_batch_new(fd, (igt_spin_opt_t){0,
-engines[rand() % nengine],
0});
+engines[rand() % nengine],
0, true});
handles[i] = spin[i]->handle;
}
@@ -469,7 +469,7 @@ static void close_race(int fd)
igt_spin_batch_free(fd, spin[i]);
spin[i] = igt_spin_batch_new(fd,
(igt_spin_opt_t){0,
engines[rand() %
nengine],
-0});
+0, true});
handles[i] = spin[i]->handle;
__sync_synchronize();
}
@@ -511,7 +511,7 @@ static bool has_semaphores(int fd)
static bool has_extended_busy_ioctl(int fd)
{
- igt_spin_t *spin = igt_spin_batch_new(fd, (igt_spin_opt_t){0,
I915_EXEC_RENDER, 0});
+ igt_spin_t *spin = igt_spin_batch_new(fd, (igt_spin_opt_t){0,
I915_EXEC_RENDER, 0, true});
uint32_t read, write;
[Intel-gfx] [RFC i-g-t 1/5] igt_dummyload: Wrap function parameters into struct
The intent of this patch is to clean-up the interface of the spinning batch
workload by grouping the parameters used to spawn it into a struct.
Cc: Chris Wilson
Signed-off-by: Antonio Argenziano
---
lib/igt_dummyload.c | 19 +++
lib/igt_dummyload.h | 16
tests/drv_missed_irq.c| 2 +-
tests/gem_busy.c | 14 +++---
tests/gem_exec_fence.c| 14 +++---
tests/gem_exec_latency.c | 2 +-
tests/gem_exec_nop.c | 2 +-
tests/gem_exec_reloc.c| 6 +++---
tests/gem_exec_schedule.c | 8
tests/gem_exec_suspend.c | 2 +-
tests/gem_shrink.c| 4 ++--
tests/gem_spin_batch.c| 4 ++--
tests/gem_sync.c | 4 ++--
tests/gem_wait.c | 2 +-
tests/kms_busy.c | 6 +++---
tests/kms_cursor_legacy.c | 6 +++---
tests/kms_flip.c | 8
tests/perf_pmu.c | 22 +++---
tests/pm_rps.c| 2 +-
19 files changed, 73 insertions(+), 70 deletions(-)
diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index bb2be557..37ae5a03 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -172,14 +172,14 @@ static void emit_recursive_batch(igt_spin_t *spin,
}
igt_spin_t *
-__igt_spin_batch_new(int fd, uint32_t ctx, unsigned engine, uint32_t dep)
+__igt_spin_batch_new(int fd, igt_spin_opt_t opts)
{
igt_spin_t *spin;
spin = calloc(1, sizeof(struct igt_spin));
igt_assert(spin);
- emit_recursive_batch(spin, fd, ctx, engine, dep);
+ emit_recursive_batch(spin, fd, opts.ctx, opts.engine, opts.dep);
igt_assert(gem_bo_busy(fd, spin->handle));
igt_list_add(&spin->link, &spin_list);
@@ -190,10 +190,13 @@ __igt_spin_batch_new(int fd, uint32_t ctx, unsigned
engine, uint32_t dep)
/**
* igt_spin_batch_new:
* @fd: open i915 drm file descriptor
- * @engine: Ring to execute batch OR'd with execbuf flags. If value is less
- * than 0, execute on all available rings.
- * @dep: handle to a buffer object dependency. If greater than 0, add a
- * relocation entry to this buffer within the batch.
+ * @opt: structure containing the parameters used by the call:
+ * - ctx: Context that will be used to submit spinning batch.
Provide 0
+ * to use default context.
+ * - engine: Ring to execute batch OR'd with execbuf flags. If
value
+ * is less than 0, execute on all
available rings.
+ * - dep: handle to a buffer object dependency. If greater than 0,
add a
+ * relocation entry to this buffer within the
batch.
*
* Start a recursive batch on a ring. Immediately returns a #igt_spin_t that
* contains the batch's handle that can be waited upon. The returned structure
@@ -203,11 +206,11 @@ __igt_spin_batch_new(int fd, uint32_t ctx, unsigned
engine, uint32_t dep)
* Structure with helper internal state for igt_spin_batch_free().
*/
igt_spin_t *
-igt_spin_batch_new(int fd, uint32_t ctx, unsigned engine, uint32_t dep)
+igt_spin_batch_new(int fd, igt_spin_opt_t opts)
{
igt_require_gem(fd);
- return __igt_spin_batch_new(fd, ctx, engine, dep);
+ return __igt_spin_batch_new(fd, opts);
}
static void notify(union sigval arg)
diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
index 215425f7..76ccd37a 100644
--- a/lib/igt_dummyload.h
+++ b/lib/igt_dummyload.h
@@ -37,14 +37,14 @@ typedef struct igt_spin {
uint32_t *batch;
} igt_spin_t;
-igt_spin_t *__igt_spin_batch_new(int fd,
-uint32_t ctx,
-unsigned engine,
-uint32_t dep);
-igt_spin_t *igt_spin_batch_new(int fd,
- uint32_t ctx,
- unsigned engine,
- uint32_t dep);
+typedef struct igt_spin_opt {
+ uint32_t ctx;
+ unsigned engine;
+ uint32_t dep;
+} igt_spin_opt_t;
+
+igt_spin_t *__igt_spin_batch_new(int fd, igt_spin_opt_t opts);
+igt_spin_t *igt_spin_batch_new(int fd, igt_spin_opt_t opts);
void igt_spin_batch_set_timeout(igt_spin_t *spin, int64_t ns);
void igt_spin_batch_end(igt_spin_t *spin);
void igt_spin_batch_free(int fd, igt_spin_t *spin);
diff --git a/tests/drv_missed_irq.c b/tests/drv_missed_irq.c
index 9326a5a6..db67367b 100644
--- a/tests/drv_missed_irq.c
+++ b/tests/drv_missed_irq.c
@@ -33,7 +33,7 @@ IGT_TEST_DESCRIPTION("Inject missed interrupts and make sure
they are caught");
static void trigger_missed_interrupt(int fd, unsigned ring)
{
- igt_spin_t *spin = __igt_spin_batch_new(fd, 0, ring, 0);
+ igt_spin_t *spin = __igt_spin_batch_new(fd, (igt_spin_opt_t){0, ring,
0});
igt_fork(child, 1) {
/* We are now a low priority child on the *same* CPU as the
diff --git a/tests/gem_busy.c b/tests/gem_busy.c
index 4ba23241..1
[Intel-gfx] [PATCH 4/5] drm/i915: Introduce a non-blocking power domain for vblank interrupts
When DC states are enabled and PSR is active, the hardware enters DC5/DC6
states resulting in frame counter resets. The frame counter resets mess
up the vblank counting logic. So in order to disable DC states when
vblank interrupts are required and to disallow DC states when vblanks
interrupts are already enabled, introduce a new power domain. Since this
power domain reference needs to be acquired and released in atomic context,
the corresponding _get() and _put() methods skip the power_domain mutex.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/i915_drv.h | 5 ++
drivers/gpu/drm/i915/intel_drv.h| 3 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 125 +++-
3 files changed, 128 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 18d42885205b..ba9107ec1ed1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -397,6 +397,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_AUX_D,
POWER_DOMAIN_GMBUS,
+ POWER_DOMAIN_VBLANK,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_INIT,
@@ -1475,6 +1476,10 @@ struct i915_power_well {
bool has_vga:1;
bool has_fuses:1;
} hsw;
+ struct {
+ spinlock_t lock;
+ bool was_disabled;
+ } dc_off;
};
const struct i915_power_well_ops *ops;
};
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 30f791f89d64..93ca503f18bb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1865,7 +1865,8 @@ void chv_phy_powergate_lanes(struct intel_encoder
*encoder,
bool override, unsigned int mask);
bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
enum dpio_channel ch, bool override);
-
+bool intel_display_power_vblank_get(struct drm_i915_private *dev_priv);
+void intel_display_power_vblank_put(struct drm_i915_private *dev_priv);
/* intel_pm.c */
void intel_init_clock_gating(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index f88f2c070c5f..f1807bd74242 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -126,6 +126,8 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
return "AUX_D";
case POWER_DOMAIN_GMBUS:
return "GMBUS";
+ case POWER_DOMAIN_VBLANK:
+ return "VBLANK";
case POWER_DOMAIN_INIT:
return "INIT";
case POWER_DOMAIN_MODESET:
@@ -196,10 +198,17 @@ bool __intel_display_power_is_enabled(struct
drm_i915_private *dev_priv,
if (power_well->always_on)
continue;
- if (!power_well->hw_enabled) {
+ if (power_well->id == SKL_DISP_PW_DC_OFF)
+ spin_lock(&power_well->dc_off.lock);
+
+ if (!power_well->hw_enabled)
is_enabled = false;
+
+ if (power_well->id == SKL_DISP_PW_DC_OFF)
+ spin_unlock(&power_well->dc_off.lock);
+
+ if (!is_enabled)
break;
- }
}
return is_enabled;
@@ -724,6 +733,7 @@ static void gen9_dc_off_power_well_disable(struct
drm_i915_private *dev_priv,
skl_enable_dc6(dev_priv);
else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
gen9_enable_dc5(dev_priv);
+ power_well->dc_off.was_disabled = true;
}
static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
@@ -1441,6 +1451,77 @@ static void chv_pipe_power_well_disable(struct
drm_i915_private *dev_priv,
chv_set_pipe_power_well(dev_priv, power_well, false);
}
+/**
+ * intel_display_power_vblank_get - acquire a VBLANK power domain reference
atomically
+ * @dev_priv: i915 device instance
+ *
+ * This function gets a POWER_DOMAIN_VBLANK reference without blocking and
+ * returns true if the DC_OFF power well was disabled since this function was
+ * called the last time.
+ */
+bool intel_display_power_vblank_get(struct drm_i915_private *dev_priv)
+{
+ struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_well *power_well;
+ bool needs_restore = false;
+
+ if (!HAS_CSR(dev_priv) || !dev_priv->psr.source_ok)
+ return false;
+
+ /* The corresponding CRTC should be active by the time driver turns on
+* vblank interrupts, which in turn means the enabled pipe power domain
+* would have acquired the device runtime pm reference.
+*/
+ intel_runtime_pm_get_if
[Intel-gfx] [PATCH 1/5] drm/vblank: Do not update vblank counts if vblanks are already disabled.
Updating the vblank counts requires register reads and these reads may not
return meaningful values after the vblank interrupts are disabled as the
device may go to low power state. An additional change would be to allow
the driver to save the vblank counts before entering a low power state, but
that's for the future.
Also, disable vblanks after reading the HW counter in the case where
_crtc_vblank_off() is disabling vblanks.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_vblank.c | 23 +--
1 file changed, 9 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
index 32d9bcf5be7f..7eee82c06ed8 100644
--- a/drivers/gpu/drm/drm_vblank.c
+++ b/drivers/gpu/drm/drm_vblank.c
@@ -347,23 +347,14 @@ void drm_vblank_disable_and_save(struct drm_device *dev,
unsigned int pipe)
spin_lock_irqsave(&dev->vblank_time_lock, irqflags);
/*
-* Only disable vblank interrupts if they're enabled. This avoids
-* calling the ->disable_vblank() operation in atomic context with the
-* hardware potentially runtime suspended.
-*/
- if (vblank->enabled) {
- __disable_vblank(dev, pipe);
- vblank->enabled = false;
- }
-
- /*
-* Always update the count and timestamp to maintain the
+* Update the count and timestamp to maintain the
* appearance that the counter has been ticking all along until
* this time. This makes the count account for the entire time
* between drm_crtc_vblank_on() and drm_crtc_vblank_off().
*/
drm_update_vblank_count(dev, pipe, false);
-
+ __disable_vblank(dev, pipe);
+ vblank->enabled = false;
spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags);
}
@@ -1122,8 +1113,12 @@ void drm_crtc_vblank_off(struct drm_crtc *crtc)
pipe, vblank->enabled, vblank->inmodeset);
/* Avoid redundant vblank disables without previous
-* drm_crtc_vblank_on(). */
- if (drm_core_check_feature(dev, DRIVER_ATOMIC) || !vblank->inmodeset)
+* drm_crtc_vblank_on() and only disable them if they're enabled. This
+* avoids calling the ->disable_vblank() operation in atomic context
+* with the hardware potentially runtime suspended.
+*/
+ if ((drm_core_check_feature(dev, DRIVER_ATOMIC) || !vblank->inmodeset)
&&
+ vblank->enabled)
drm_vblank_disable_and_save(dev, pipe);
wake_up(&vblank->queue);
--
2.11.0
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/5] drm/i915: Use the vblank power domain disallow or disable DC states.
Disable DC states before enabling vblank interrupts and conversely enable DC states after disabling. Since the frame counter may have got reset between disabling and enabling, use drm_crtc_vblank_restore() to compute the missed vblanks. Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/i915_irq.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 7cac07db89b9..c595b934e2dc 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2964,6 +2964,9 @@ static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe) struct drm_i915_private *dev_priv = to_i915(dev); unsigned long irqflags; + if (intel_display_power_vblank_get(dev_priv)) + drm_crtc_vblank_restore(dev, pipe); + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); @@ -3015,6 +3018,7 @@ static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe) spin_lock_irqsave(&dev_priv->irq_lock, irqflags); bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); + intel_display_power_vblank_put(dev_priv); } static void ibx_irq_reset(struct drm_i915_private *dev_priv) -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/5] drm/i915: Use an atomic_t array to track power domain use count.
Convert the power_domains->domain_use_count array that tracks per-domain
use count to atomic_t type. This is needed to be able to read/write the use
counts outside of the power domain mutex.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +--
3 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 28294470ae31..2a4ed54688d7 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2805,7 +2805,7 @@ static int i915_power_domain_info(struct seq_file *m,
void *unused)
for_each_power_domain(power_domain, power_well->domains)
seq_printf(m, " %-23s %d\n",
intel_display_power_domain_str(power_domain),
-power_domains->domain_use_count[power_domain]);
+
atomic_read(&power_domains->domain_use_count[power_domain]));
}
mutex_unlock(&power_domains->lock);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 594fd14e66c5..18d42885205b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1489,7 +1489,7 @@ struct i915_power_domains {
int power_well_count;
struct mutex lock;
- int domain_use_count[POWER_DOMAIN_NUM];
+ atomic_t domain_use_count[POWER_DOMAIN_NUM];
struct i915_power_well *power_wells;
};
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 8315499452dc..f88f2c070c5f 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1451,7 +1451,7 @@ __intel_display_power_get_domain(struct drm_i915_private
*dev_priv,
for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
intel_power_well_get(dev_priv, power_well);
- power_domains->domain_use_count[domain]++;
+ atomic_inc(&power_domains->domain_use_count[domain]);
}
/**
@@ -1537,10 +1537,9 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
mutex_lock(&power_domains->lock);
- WARN(!power_domains->domain_use_count[domain],
-"Use count on domain %s is already zero\n",
+ WARN(atomic_dec_return(&power_domains->domain_use_count[domain]) < 0,
+"Use count on domain %s was already zero\n",
intel_display_power_domain_str(domain));
- power_domains->domain_use_count[domain]--;
for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain))
intel_power_well_put(dev_priv, power_well);
@@ -3044,7 +3043,7 @@ static void intel_power_domains_dump_info(struct
drm_i915_private *dev_priv)
for_each_power_domain(domain, power_well->domains)
DRM_DEBUG_DRIVER(" %-23s %d\n",
intel_display_power_domain_str(domain),
-
power_domains->domain_use_count[domain]);
+
atomic_read(&power_domains->domain_use_count[domain]));
}
}
@@ -3087,7 +3086,7 @@ void intel_power_domains_verify_state(struct
drm_i915_private *dev_priv)
domains_count = 0;
for_each_power_domain(domain, power_well->domains)
- domains_count +=
power_domains->domain_use_count[domain];
+ domains_count +=
atomic_read(&power_domains->domain_use_count[domain]);
if (power_well->count != domains_count) {
DRM_ERROR("power well %s refcount/domain refcount
mismatch "
--
2.11.0
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[Intel-gfx] [PATCH 2/5] drm/vblank: Restoring vblank counts after device runtime PM events.
The HW frame counter can get reset when devices enters low power
states and this messes up any following vblank count updates. So, compute
the missed vblank interrupts for that low power state duration using time
stamps. This is similar to _crtc_vblank_on() except that it doesn't enable
vblank interrupts because this function is expected to be called from
the driver _enable_vblank() vfunc.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_vblank.c | 30 ++
include/drm/drm_vblank.h | 1 +
2 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
index 7eee82c06ed8..69d537cea149 100644
--- a/drivers/gpu/drm/drm_vblank.c
+++ b/drivers/gpu/drm/drm_vblank.c
@@ -1230,6 +1230,36 @@ void drm_crtc_vblank_on(struct drm_crtc *crtc)
}
EXPORT_SYMBOL(drm_crtc_vblank_on);
+void drm_crtc_vblank_restore(struct drm_device *dev, unsigned int pipe)
+{
+ ktime_t t_vblank;
+ struct drm_vblank_crtc *vblank;
+ int framedur_ns;
+ u64 diff_ns;
+ u32 cur_vblank, diff = 1;
+ int count = DRM_TIMESTAMP_MAXRETRIES;
+
+ if (WARN_ON(pipe >= dev->num_crtcs))
+ return;
+
+ vblank = &dev->vblank[pipe];
+ framedur_ns = vblank->framedur_ns;
+
+ do {
+ cur_vblank = __get_vblank_counter(dev, pipe);
+ drm_get_last_vbltimestamp(dev, pipe, &t_vblank, false);
+ } while (cur_vblank != __get_vblank_counter(dev, pipe) && --count > 0);
+
+ diff_ns = ktime_to_ns(ktime_sub(t_vblank, vblank->time));
+ if (framedur_ns)
+ diff = DIV_ROUND_CLOSEST_ULL(diff_ns, framedur_ns);
+
+ DRM_DEBUG_VBL("computing missed vblanks %lld/%d=%d after HW counter
reset hw_diff=%d\n",
+ diff_ns, framedur_ns, diff, cur_vblank - vblank->last);
+ store_vblank(dev, pipe, diff, t_vblank, cur_vblank);
+}
+EXPORT_SYMBOL(drm_crtc_vblank_restore);
+
static void drm_legacy_vblank_pre_modeset(struct drm_device *dev,
unsigned int pipe)
{
diff --git a/include/drm/drm_vblank.h b/include/drm/drm_vblank.h
index 848b463a0af5..aafcbef91bd7 100644
--- a/include/drm/drm_vblank.h
+++ b/include/drm/drm_vblank.h
@@ -180,6 +180,7 @@ void drm_crtc_vblank_off(struct drm_crtc *crtc);
void drm_crtc_vblank_reset(struct drm_crtc *crtc);
void drm_crtc_vblank_on(struct drm_crtc *crtc);
u32 drm_crtc_accurate_vblank_count(struct drm_crtc *crtc);
+void drm_crtc_vblank_restore(struct drm_device *dev, unsigned int pipe);
bool drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev,
unsigned int pipe, int *max_error,
--
2.11.0
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk" (rev2)
== Series Details == Series: Revert "drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk" (rev2) URL : https://patchwork.freedesktop.org/series/33969/ State : failure == Summary == Applying: Revert "drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk" error: Failed to merge in the changes. Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_reg.h M drivers/gpu/drm/i915/intel_pm.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/intel_pm.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_pm.c Patch failed at 0001 Revert "drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk" The copy of the patch that failed is found in: .git/rebase-apply/patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] Revert "drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk"
From: Radhakrishna Sripada
This reverts commit 8f067837c4b713ce2e69be95af7b2a5eb3bd7de8.
HSD says "WA withdrawn. It was causing corruption with some images.
WA is not strictly necessary since this bug just causes loss of FBC
compression with some sizes and images, but doesn't break anything."
Fixes: 8f067837c4b7 ("drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk")
Cc: Rodrigo Vivi
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Rodrigo Vivi
Link:
https://patchwork.freedesktop.org/patch/msgid/20171117010825.23118-1-radhakrishna.srip...@intel.com
(cherry picked from commit 0cfecb7c4b9b45ed1776162e132b43f92564f3f4)
---
drivers/gpu/drm/i915/i915_reg.h | 3 ---
drivers/gpu/drm/i915/intel_pm.c | 13 -
2 files changed, 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 68a58cce6ab1..3866c49bc390 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2951,9 +2951,6 @@ enum i915_power_well_id {
#define ILK_DPFC_CHICKEN _MMIO(0x43224)
#define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
#define ILK_DPFC_NUKE_ON_ANY_MODIFICATION(1<<23)
-#define GLK_SKIP_SEG_EN (1<<12)
-#define GLK_SKIP_SEG_COUNT_MASK (3<<10)
-#define GLK_SKIP_SEG_COUNT(x)((x)<<10)
#define ILK_FBC_RT_BASE_MMIO(0x2128)
#define ILK_FBC_RT_VALID (1<<0)
#define SNB_FBC_FRONT_BUFFER (1<<1)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f4a4e9496893..f0d0dbab4150 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -124,7 +124,6 @@ static void bxt_init_clock_gating(struct drm_i915_private
*dev_priv)
static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
{
- u32 val;
gen9_init_clock_gating(dev_priv);
/*
@@ -144,11 +143,6 @@ static void glk_init_clock_gating(struct drm_i915_private
*dev_priv)
I915_WRITE(CHICKEN_MISC_2, val);
}
- /* Display WA #1133: WaFbcSkipSegments:glk */
- val = I915_READ(ILK_DPFC_CHICKEN);
- val &= ~GLK_SKIP_SEG_COUNT_MASK;
- val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
- I915_WRITE(ILK_DPFC_CHICKEN, val);
}
static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
@@ -8517,7 +8511,6 @@ static void cnp_init_clock_gating(struct drm_i915_private
*dev_priv)
static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
{
- u32 val;
cnp_init_clock_gating(dev_priv);
/* This is not an Wa. Enable for better image quality */
@@ -8537,12 +8530,6 @@ static void cnl_init_clock_gating(struct
drm_i915_private *dev_priv)
I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
SARBUNIT_CLKGATE_DIS);
-
- /* Display WA #1133: WaFbcSkipSegments:cnl */
- val = I915_READ(ILK_DPFC_CHICKEN);
- val &= ~GLK_SKIP_SEG_COUNT_MASK;
- val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
- I915_WRITE(ILK_DPFC_CHICKEN, val);
}
static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
--
2.13.6
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[Intel-gfx] [PULL] drm-misc-fixes
Hi Dave, drm-misc-fixes-2017-12-06: Just the connector_iter corner-case regression fix. Enjoy your time off next week! Cheers, Daniel The following changes since commit ae64f9bd1d3621b5e60d7363bc20afb46aede215: Linux 4.15-rc2 (2017-12-03 11:01:47 -0500) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2017-12-06 for you to fetch changes up to a703c55004e1c5076d57e43771b3e7796ea0: drm: safely free connectors from connector_iter (2017-12-06 10:22:55 +0100) Just the connector_iter corner-case regression fix. Daniel Vetter (1): drm: safely free connectors from connector_iter drivers/gpu/drm/drm_connector.c | 28 ++-- drivers/gpu/drm/drm_mode_config.c | 2 ++ include/drm/drm_connector.h | 8 3 files changed, 36 insertions(+), 2 deletions(-) -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Use copy_from_user() in fence copying
There's no good reason to separate the access_ok() from the copy,
especially since the access_ok() size is hard-coded instead of using
sizeof(). Instead, just use copy_from_user() directly.
Fixes: cf6e7bac6357 ("drm/i915: Add support for drm syncobjs")
Cc: Jason Ekstrand
Cc: Chris Wilson
Signed-off-by: Kees Cook
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 435ed95df144..1da703213b17 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -2087,8 +2087,6 @@ get_fence_array(struct drm_i915_gem_execbuffer2 *args,
return ERR_PTR(-EINVAL);
user = u64_to_user_ptr(args->cliprects_ptr);
- if (!access_ok(VERIFY_READ, user, nfences * 2 * sizeof(u32)))
- return ERR_PTR(-EFAULT);
fences = kvmalloc_array(args->num_cliprects, sizeof(*fences),
__GFP_NOWARN | GFP_KERNEL);
@@ -2099,7 +2097,7 @@ get_fence_array(struct drm_i915_gem_execbuffer2 *args,
struct drm_i915_gem_exec_fence fence;
struct drm_syncobj *syncobj;
- if (__copy_from_user(&fence, user++, sizeof(fence))) {
+ if (copy_from_user(&fence, user++, sizeof(fence))) {
err = -EFAULT;
goto err;
}
--
2.7.4
--
Kees Cook
Pixel Security
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Re: [Intel-gfx] [RFC 0/4] GPU/CPU timestamps correlation for relating OA samples with system events
I've put together some trival IGT tests : https://github.com/djdeath/intel-gpu-tools/commits/wip/djdeath/cpu-timestamps With a few changes which I pointed in the review : https://github.com/djdeath/linux/commit/d0e4cf4d3f464491b4ffe97d112284d1ce73656d Put together it seems to work relatively well. There is still a small drift happening between the 2 timestamps. I've noticed over a 160ms of OA reports, there is a accumulated difference of ~35us between the GPU timestamp and cpu timestamps. I may be doing something wrong with the scaling in the tests, or maybe there is an issue in the kernel, or both. I'll build the GPUTop parts and see if the results make sense. Thanks!, - Lionel On 15/11/17 12:13, Sagar Arun Kamble wrote: We can compute system time corresponding to GPU timestamp by taking a reference point (CPU monotonic time, GPU timestamp) and then adding delta time computed using timecounter/cyclecounter support in kernel. We have to configure cyclecounter with the GPU timestamp frequency. Earlier approach that was based on cross-timestamp is not needed. It was being used to approximate the frequency based on invalid assumptions (possibly drift was being seen in the time due to precision issue). The precision of time from GPU clocks is already in ns and timecounter takes care of it as verified over variable durations. This series adds base timecounter/cyclecounter changes and changes to get GPU and CPU timestamps in OA samples. Sagar Arun Kamble (1): drm/i915/perf: Add support to correlate GPU timestamp with system time Sourab Gupta (3): drm/i915/perf: Add support for collecting 64 bit timestamps with OA reports drm/i915/perf: Extract raw GPU timestamps from OA reports drm/i915/perf: Send system clock monotonic time in perf samples drivers/gpu/drm/i915/i915_drv.h | 11 drivers/gpu/drm/i915/i915_perf.c | 124 ++- drivers/gpu/drm/i915/i915_reg.h | 6 ++ include/uapi/drm/i915_drm.h | 14 + 4 files changed, 154 insertions(+), 1 deletion(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 3/4] drm/i915/perf: Extract raw GPU timestamps from OA reports
On 15/11/17 12:13, Sagar Arun Kamble wrote:
From: Sourab Gupta
The OA reports contain the least significant 32 bits of the gpu timestamp.
This patch enables retrieval of the timestamp field from OA reports, to
forward as 64 bit raw gpu timestamps in the perf samples.
v2: Rebase w.r.t new timecounter support.
Signed-off-by: Sourab Gupta
Signed-off-by: Sagar Arun Kamble
Cc: Lionel Landwerlin
Cc: Chris Wilson
Cc: Sourab Gupta
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_perf.c | 26 +-
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e08bc85..5534cd2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2151,6 +2151,8 @@ struct i915_perf_stream {
*/
struct i915_oa_config *oa_config;
+ u64 last_gpu_ts;
+
/**
* System time correlation variables.
*/
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index f7e748c..3b721d7 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -575,6 +575,26 @@ static int append_oa_status(struct i915_perf_stream
*stream,
}
/**
+ * get_gpu_ts_from_oa_report - Retrieve absolute gpu timestamp from OA report
+ *
+ * Note: We are assuming that we're updating last_gpu_ts frequently enough so
+ * that it's never possible to see multiple overflows before we compare
+ * sample_ts to last_gpu_ts. Since this is significantly large duration
+ * (~6min for 80ns ts base), we can safely assume so.
+ */
+static u64 get_gpu_ts_from_oa_report(struct i915_perf_stream *stream,
+const u8 *report)
+{
+ u32 sample_ts = *(u32 *)(report + 4);
+ u32 delta;
+
+ delta = sample_ts - (u32)stream->last_gpu_ts;
+ stream->last_gpu_ts += delta;
+
+ return stream->last_gpu_ts;
+}
+
+/**
* append_oa_sample - Copies single OA report into userspace read() buffer.
* @stream: An i915-perf stream opened for OA metrics
* @buf: destination buffer given by userspace
@@ -622,7 +642,9 @@ static int append_oa_sample(struct i915_perf_stream *stream,
}
if (sample_flags & SAMPLE_GPU_TS) {
- /* Timestamp to be populated from OA report */
+ /* Timestamp populated from OA report */
+ gpu_ts = get_gpu_ts_from_oa_report(stream, report);
+
if (copy_to_user(buf, &gpu_ts, I915_PERF_TS_SAMPLE_SIZE))
return -EFAULT;
}
I think everything above this line should be merged int patch 2.
It's better to have a single functional patch.
@@ -2421,6 +2443,8 @@ static u64 i915_cyclecounter_read(const struct
cyclecounter *cc)
GEN7_TIMESTAMP_UDW);
intel_runtime_pm_put(dev_priv);
+ stream->last_gpu_ts = ts_count;
This doesn't look right. You're already adding a delta in
get_gpu_ts_from_oa_report().
This will produce incorrect timestamps. Since at the moment we won't
allow opening without PROP_SAMPLE_OA, I would just drop this line.
+
return ts_count;
}
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[Intel-gfx] ✓ Fi.CI.IGT: success for make stolen resource centric (rev5)
== Series Details == Series: make stolen resource centric (rev5) URL : https://patchwork.freedesktop.org/series/34256/ State : success == Summary == Warning: bzip CI_DRM_3466/shard-snb2/results25.json.bz2 wasn't in correct JSON format Test perf: Subgroup oa-exponents: pass -> FAIL (shard-hsw) fdo#102254 Test kms_pipe_crc_basic: Subgroup read-crc-pipe-b-frame-sequence: pass -> INCOMPLETE (shard-hsw) fdo#102332 Test kms_setmode: Subgroup basic: fail -> PASS (shard-hsw) fdo#99912 Test kms_frontbuffer_tracking: Subgroup fbc-1p-offscren-pri-shrfb-draw-blt: pass -> FAIL (shard-snb) fdo#101623 Test drv_selftest: Subgroup live_hangcheck: pass -> INCOMPLETE (shard-snb) fdo#103880 fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254 fdo#102332 https://bugs.freedesktop.org/show_bug.cgi?id=102332 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623 fdo#103880 https://bugs.freedesktop.org/show_bug.cgi?id=103880 shard-hswtotal:2623 pass:1505 dwarn:1 dfail:0 fail:10 skip:1106 time:9243s shard-snbtotal:2661 pass:1289 dwarn:1 dfail:0 fail:12 skip:1358 time:7965s Blacklisted hosts: shard-kbltotal:2614 pass:1747 dwarn:6 dfail:0 fail:24 skip:835 time:10178s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7430/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] e1000e: Taint a HW lockup
On Wed, 2017-12-06 at 10:47 +0100, Daniel Vetter wrote: > On Tue, Dec 5, 2017 at 7:05 PM, Chris Wilson k> wrote: > > Quoting Chris Wilson (2017-12-05 18:00:00) > > > When we see an e1000e HW lockup in CI, it is typically fatal with > > > the > > > hang repeating until the host is forcibly rebooted. Speed up that > > > process by tainting the kernel, which CI can trivially detect > > > (and is > > > being used to detect similarly fatal CI conditions) and reboot > > > soon > > > after. > > > > > > Signed-off-by: Chris Wilson > > > Cc: Daniel Vetter > > > Cc: Tomi Sarvela > > > > I'm not concerned on selling this to e1000e, but if it helps > > improving > > CI robustness, then topic/core-for-CI. Or maybe we should create a > > new > > topic, Daniel? topic/taints-for-CI? > > Sounds like a usable idea for CI. Would be especially interesting > because despite applying the suggested w/a, we still hit lockups. > Before we do that though I think we should get an ack from the e1000e > team. Jani S. maybe something you can driver? > > Adding more folks to cc. > -Daniel Please send any e1000e patches to the intel-wired-lan mailing list and make sure to CC Sasha Neftin , since he is the e1000e driver maintainer. signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for lib/igt_sysfs: Let igt_sysfs_read|write return -errno
== Series Details == Series: lib/igt_sysfs: Let igt_sysfs_read|write return -errno URL : https://patchwork.freedesktop.org/series/34989/ State : failure == Summary == IGT patchset tested on top of latest successful build 1db12466cb5ad8483cd469753d2e312a62d717b7 meson: build a full dependency for lib_igt_perf with latest DRM-Tip kernel build CI_DRM_3466 66be57731a40 drm-tip: 2017y-12m-06d-16h-12m-57s UTC integration manifest No testlist changes. Test debugfs_test: Subgroup read_all_entries: dmesg-warn -> PASS (fi-elk-e7500) fdo#103989 Test drv_hangman: Subgroup error-state-basic: pass -> INCOMPLETE (fi-gdg-551) pass -> INCOMPLETE (fi-blb-e6850) pass -> INCOMPLETE (fi-pnv-d510) pass -> INCOMPLETE (fi-bwr-2160) pass -> INCOMPLETE (fi-elk-e7500) pass -> INCOMPLETE (fi-snb-2520m) pass -> INCOMPLETE (fi-snb-2600) pass -> INCOMPLETE (fi-ivb-3520m) pass -> INCOMPLETE (fi-ivb-3770) pass -> INCOMPLETE (fi-byt-j1900) pass -> INCOMPLETE (fi-byt-n2820) pass -> INCOMPLETE (fi-hsw-4770) pass -> INCOMPLETE (fi-hsw-4770r) pass -> INCOMPLETE (fi-bdw-5557u) pass -> INCOMPLETE (fi-bsw-n3050) pass -> INCOMPLETE (fi-skl-6260u) pass -> INCOMPLETE (fi-skl-6600u) pass -> INCOMPLETE (fi-skl-6700hq) pass -> INCOMPLETE (fi-skl-6700k) pass -> INCOMPLETE (fi-skl-6770hq) pass -> INCOMPLETE (fi-bxt-dsi) pass -> INCOMPLETE (fi-bxt-j4205) pass -> INCOMPLETE (fi-kbl-7560u) pass -> INCOMPLETE (fi-kbl-7567u) pass -> INCOMPLETE (fi-kbl-r) pass -> INCOMPLETE (fi-glk-1) fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fi-bdw-5557u total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-blb-e6850 total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-bsw-n3050 total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-bwr-2160 total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-bxt-dsi total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-bxt-j4205 total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-byt-j1900 total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-byt-n2820 total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-elk-e7500 total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-gdg-551 total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-glk-1 total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-hsw-4770 total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-hsw-4770r total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-ivb-3520m total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-ivb-3770 total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-kbl-7560u total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-kbl-7567u total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-kbl-r total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-pnv-d510 total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-skl-6260u total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-skl-6600u total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-skl-6700hqtotal:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-skl-6700k total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-skl-6770hqtotal:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-snb-2520m total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-snb-2600 total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 Blacklisted hosts: fi-cfl-s2total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-cnl-y total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-glk-dsi total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_604/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] lib/igt_sysfs: Let igt_sysfs_read|write return -errno
Quoting Michal Wajdeczko (2017-12-06 19:00:22)
> In some cases debugfs or sysfs may return errors that we
> want to check. Return -errno from helper functions to make
> asserts easier.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> ---
> lib/igt_sysfs.c | 18 +-
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/lib/igt_sysfs.c b/lib/igt_sysfs.c
> index e7c67da..9e9fdde 100644
> --- a/lib/igt_sysfs.c
> +++ b/lib/igt_sysfs.c
> @@ -60,8 +60,8 @@ static int readN(int fd, char *buf, int len)
> if (ret < 0 && (errno == EINTR || errno == EAGAIN))
> continue;
>
> - if (ret <= 0)
> - return total ?: ret;
> + if (ret < 0)
> + return total ?: -errno;
We do need to keep the break on ret == 0; some fs will just keep on
reporting 0 bytes read for EOF.
How about
if (ret < 0) {
ret = -errno;
if (ret == -EINTR || ret == -EAGAIN)
continue;
}
if (ret <= 0)
return total ?: ret;
>
> total += ret;
> if (total == len)
> @@ -77,8 +77,8 @@ static int writeN(int fd, const char *buf, int len)
> if (ret < 0 && (errno == EINTR || errno == EAGAIN))
> continue;
>
> - if (ret <= 0)
> - return total ?: ret;
> + if (ret < 0)
> + return total ?: -errno;
Ditto.
Reviewed-by: Chris Wilson
-Chris
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[Intel-gfx] [PATCH i-g-t] lib/igt_sysfs: Let igt_sysfs_read|write return -errno
In some cases debugfs or sysfs may return errors that we
want to check. Return -errno from helper functions to make
asserts easier.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Joonas Lahtinen
---
lib/igt_sysfs.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/lib/igt_sysfs.c b/lib/igt_sysfs.c
index e7c67da..9e9fdde 100644
--- a/lib/igt_sysfs.c
+++ b/lib/igt_sysfs.c
@@ -60,8 +60,8 @@ static int readN(int fd, char *buf, int len)
if (ret < 0 && (errno == EINTR || errno == EAGAIN))
continue;
- if (ret <= 0)
- return total ?: ret;
+ if (ret < 0)
+ return total ?: -errno;
total += ret;
if (total == len)
@@ -77,8 +77,8 @@ static int writeN(int fd, const char *buf, int len)
if (ret < 0 && (errno == EINTR || errno == EAGAIN))
continue;
- if (ret <= 0)
- return total ?: ret;
+ if (ret < 0)
+ return total ?: -errno;
total += ret;
if (total == len)
@@ -238,7 +238,7 @@ int igt_sysfs_open_parameters(int device)
* This writes @len bytes from @data to the sysfs file.
*
* Returns:
- * The number of bytes written, or -1 on error.
+ * The number of bytes written, or -errno on error.
*/
int igt_sysfs_write(int dir, const char *attr, const void *data, int len)
{
@@ -246,7 +246,7 @@ int igt_sysfs_write(int dir, const char *attr, const void
*data, int len)
fd = openat(dir, attr, O_WRONLY);
if (fd < 0)
- return false;
+ return -errno;
len = writeN(fd, data, len);
close(fd);
@@ -264,7 +264,7 @@ int igt_sysfs_write(int dir, const char *attr, const void
*data, int len)
* This reads @len bytes from the sysfs file to @data
*
* Returns:
- * The length read, -1 on failure.
+ * The length read, -errno on failure.
*/
int igt_sysfs_read(int dir, const char *attr, void *data, int len)
{
@@ -272,7 +272,7 @@ int igt_sysfs_read(int dir, const char *attr, void *data,
int len)
fd = openat(dir, attr, O_RDONLY);
if (fd < 0)
- return false;
+ return -errno;
len = readN(fd, data, len);
close(fd);
@@ -338,7 +338,7 @@ char *igt_sysfs_get(int dir, const char *attr)
rem = len - offset - 1;
}
- if (ret != -1)
+ if (ret > 0)
offset += ret;
buf[offset] = '\0';
while (offset > 0 && buf[offset-1] == '\n')
--
2.7.4
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[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [1/2] lib: Export kmsg()
== Series Details == Series: series starting with [1/2] lib: Export kmsg() URL : https://patchwork.freedesktop.org/series/34974/ State : warning == Summary == Warning: bzip CI_DRM_3466/shard-snb2/results25.json.bz2 wasn't in correct JSON format Test drv_module_reload: Subgroup basic-no-display: pass -> DMESG-WARN (shard-snb) fdo#102707 Test kms_frontbuffer_tracking: Subgroup fbc-1p-offscren-pri-shrfb-draw-render: pass -> FAIL (shard-snb) fdo#101623 +1 Test drv_suspend: Subgroup forcewake: pass -> SKIP (shard-hsw) Test pm_rps: Subgroup waitboost: pass -> FAIL (shard-hsw) fdo#102250 Test kms_plane: Subgroup plane-panning-bottom-right-suspend-pipe-a-planes: pass -> SKIP (shard-snb) fdo#102365 fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707 fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623 fdo#102250 https://bugs.freedesktop.org/show_bug.cgi?id=102250 fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365 shard-hswtotal:2679 pass:1534 dwarn:1 dfail:0 fail:11 skip:1133 time:9457s shard-snbtotal:2679 pass:1305 dwarn:2 dfail:0 fail:13 skip:1359 time:8053s Blacklisted hosts: shard-apltotal:2679 pass:1677 dwarn:2 dfail:0 fail:22 skip:977 time:13579s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_603/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/10] x86/early-quirks: Extend Intel graphics stolen memory placement to 64bit
Quoting Matthew Auld (2017-12-06 18:17:21)
> From: Joonas Lahtinen
>
> To give upcoming SKU BIOSes more flexibility in placing the Intel
> graphics stolen memory, make all variables storing the placement or size
> compatible with full 64 bit range. Also by exporting the stolen region
> as a resource, we can then nuke the duplicated stolen discovery in i915.
>
> v2: export the stolen region as a resource
> fix u16 << 16 (Chris)
> v3: actually fix u16 << 16
>
> Signed-off-by: Joonas Lahtinen
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Ville Syrjälä
> Cc: Chris Wilson
> Cc: Paulo Zanoni
> Cc: Thomas Gleixner
> Cc: Ingo Molnar
> Cc: H. Peter Anvin
> Cc: x...@kernel.org
> Cc: linux-ker...@vger.kernel.org
> Reviewed-by: Chris Wilson #v1
> ---
> +static resource_size_t __init i865_stolen_base(int num, int slot, int func,
> + resource_size_t stolen_size)
> {
> u16 toud = 0;
>
> toud = read_pci_config_16(0, 0, 0, I865_TOUD);
>
> - return (phys_addr_t)(toud << 16) + i845_tseg_size();
> + return (toud * KB(64)) + i845_tseg_size();
Overkill on the brackets.
Reviewed-by: Chris Wilson
-Chris
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Re: [Intel-gfx] [PATCH 10/10] drm/i915: prefer stolen_usable_size for the range sanity check
Quoting Matthew Auld (2017-12-06 18:17:30) > In i915_pages_create_for_stolen it probably makes more sense to check if > the range overflows the stolen_usable_size, since the size of dsm will also > include the reserved portion which we can't touch. > > Signed-off-by: Matthew Auld > Cc: Joonas Lahtinen > Cc: Chris Wilson > Cc: Paulo Zanoni > --- > drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c > b/drivers/gpu/drm/i915/i915_gem_stolen.c > index 2267af68c3e1..f8c9f0446712 100644 > --- a/drivers/gpu/drm/i915/i915_gem_stolen.c > +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c > @@ -430,7 +430,7 @@ i915_pages_create_for_stolen(struct drm_device *dev, > struct sg_table *st; > struct scatterlist *sg; > > - GEM_BUG_ON(range_overflows(offset, size, > resource_size(&dev_priv->dsm))); > + GEM_BUG_ON(range_overflows(offset, size, > dev_priv->stolen_usable_size)); I'm not sold. The usable size is a restriction placed on the drm_mm range manager that not everyone may be privy to; certainly when coming from HW that knows only about the stolen region. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 09/10] drm/i915: prefer resource_size_t for everything stolen
Quoting Matthew Auld (2017-12-06 18:17:29)
> Keeps things consistent now that we make use of struct resource. This
> should keep us covered in case we ever get huge amounts of stolen
> memory.
>
> v2: bunch of missing conversions (Chris)
>
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Chris Wilson
> Cc: Paulo Zanoni
> ---
> @@ -3464,7 +3464,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private
> *dev_priv)
> */
> if (USES_GUC(dev_priv)) {
> ggtt->base.total = min_t(u64, ggtt->base.total, GUC_GGTT_TOP);
> - ggtt->mappable_end = min(ggtt->mappable_end,
> ggtt->base.total);
> + ggtt->mappable_end = min_t(u64, ggtt->mappable_end,
> ggtt->base.total);
> }
>
> if ((ggtt->base.total - 1) >> 32) {
> @@ -3472,13 +3472,13 @@ int i915_ggtt_probe_hw(struct drm_i915_private
> *dev_priv)
> " of address space! Found %lldM!\n",
> ggtt->base.total >> 20);
> ggtt->base.total = 1ULL << 32;
> - ggtt->mappable_end = min(ggtt->mappable_end,
> ggtt->base.total);
> + ggtt->mappable_end = min_t(u64, ggtt->mappable_end,
> ggtt->base.total);
> }
Hmm. Not pretty, but I have no better alternative (other than plain old
if()).
Reviewed-by: Chris Wilson
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for make stolen resource centric (rev5)
== Series Details == Series: make stolen resource centric (rev5) URL : https://patchwork.freedesktop.org/series/34256/ State : success == Summary == Series 34256v5 make stolen resource centric https://patchwork.freedesktop.org/api/1.0/series/34256/revisions/5/mbox/ Test gem_mmap_gtt: Subgroup basic-small-bo-tiledx: pass -> FAIL (fi-gdg-551) fdo#102575 fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:445s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:385s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:515s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:282s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:500s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:508s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:489s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:471s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:270s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:538s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:373s fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:257s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:474s fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:446s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:531s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:477s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:535s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:597s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:453s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:546s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:568s fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:518s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:497s fi-snb-2520m total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:547s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:413s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:614s fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:615s fi-glk-dsi total:196 pass:182 dwarn:0 dfail:0 fail:0 skip:13 66be57731a40b46c8588811fbf4ca4d817122c20 drm-tip: 2017y-12m-06d-16h-12m-57s UTC integration manifest 9bb33f1c99b6 drm/i915: prefer stolen_usable_size for the range sanity check 0afe9f77b0b0 drm/i915: prefer resource_size_t for everything stolen 6a28f842f3b0 drm/i915: give stolen_usable_size a more suitable home 7d77e9211779 drm/i915: make mappable struct resource centric 8b10a2867a4e drm/i915: make reserved struct resource centric 6dd6ac3525eb drm/i915: make dsm struct resource centric 87069582c4f4 drm/i915: nuke the duplicated stolen discovery 78fce6ff81d4 x86/early-quirks: reverse the if ladders ba05ce7b8e5b x86/early-quirks: replace the magical increment start values 289f2f0e9ae0 x86/early-quirks: Extend Intel graphics stolen memory placement to 64bit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7430/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: warning for lib/rendercopy: Refactoring rendercopy libraries
== Series Details == Series: lib/rendercopy: Refactoring rendercopy libraries URL : https://patchwork.freedesktop.org/series/34972/ State : warning == Summary == Warning: bzip CI_DRM_3466/shard-snb2/results25.json.bz2 wasn't in correct JSON format Test kms_flip: Subgroup vblank-vs-suspend-interruptible: pass -> INCOMPLETE (shard-hsw) fdo#100368 Test kms_frontbuffer_tracking: Subgroup fbc-1p-offscren-pri-shrfb-draw-blt: pass -> FAIL (shard-snb) fdo#101623 Test gem_eio: Subgroup in-flight: pass -> DMESG-WARN (shard-snb) fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623 shard-hswtotal:2614 pass:1498 dwarn:1 dfail:0 fail:9 skip:1105 time:8892s shard-snbtotal:2679 pass:1307 dwarn:2 dfail:0 fail:12 skip:1358 time:8137s Blacklisted hosts: shard-kbltotal:2679 pass:1781 dwarn:14 dfail:0 fail:25 skip:859 time:10913s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_602/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/10] drm/i915: give stolen_usable_size a more suitable home
Quoting Matthew Auld (2017-12-06 18:17:28)
> Kick it out of i915_ggtt and keep it grouped with dsm and dsm_reserved,
> where it makes the most sense.
>
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Chris Wilson
> Cc: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/i915_drv.h| 12 +++-
> drivers/gpu/drm/i915/i915_gem_gtt.h| 10 --
> drivers/gpu/drm/i915/i915_gem_stolen.c | 5 ++---
> drivers/gpu/drm/i915/intel_display.c | 3 +--
> drivers/gpu/drm/i915/intel_fbdev.c | 3 +--
> 5 files changed, 15 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 40171a7da9d9..2c3e1d715c11 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2253,7 +2253,7 @@ struct drm_i915_private {
> /**
> * Data Stolen Memory - aka "i915 stolen memory" gives us the start
> and
> * end of stolen which we can optionally use to create GEM objects
> -* backed by stolen memory. Note that ggtt->stolen_usable_size tells
> us
> +* backed by stolen memory. Note that stolen_usable_size tells us
> * exactly how much of this we are actually allowed to use, given that
> * some portion of it is in fact reserved for use by hardware
> functions.
> */
> @@ -2263,6 +2263,16 @@ struct drm_i915_private {
> */
> struct resource dsm_reserved;
>
> + /* Stolen memory is segmented in hardware with different portions
/*
* Stolen...
*/
Reviewed-by: Chris Wilson
-Chris
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Re: [Intel-gfx] [PATCH 05/10] drm/i915: make dsm struct resource centric
Quoting Matthew Auld (2017-12-06 18:17:25)
> Now that we are using struct resource to track the stolen region, it is
> more convenient if we track dsm in a resource as well.
>
> v2: check range_overflow when writing to 32b registers (Chris)
> pepper in some comments (Chris)
> v3: refit i915_stolen_to_dma()
> v4: kill ggtt->stolen_size
>
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Chris Wilson
> Cc: Paulo Zanoni
> ---
> -static dma_addr_t i915_stolen_to_dma(struct drm_i915_private *dev_priv)
> +static int i915_adjust_stolen(struct drm_i915_private *dev_priv,
> + struct resource *dsm)
> {
> struct i915_ggtt *ggtt = &dev_priv->ggtt;
> - dma_addr_t base = intel_graphics_stolen_res.start;
> struct resource *r;
>
> - GEM_BUG_ON(overflows_type(intel_graphics_stolen_res.start, base));
> + if (dsm->start == 0 || add_overflows(dsm->start, resource_size(dsm)))
Now s/add_overflows/dsm->end <= dsm->start/
> + return -EINVAL;
>
> - if (base == 0 || add_overflows(base, ggtt->stolen_size))
> - return 0;
> -
> - /* make sure we don't clobber the GTT if it's within stolen memory */
> + /* Make sure we don't clobber the GTT if it's within stolen memory */
> if (INTEL_GEN(dev_priv) <= 4 &&
> !IS_G33(dev_priv) && !IS_PINEVIEW(dev_priv) && !IS_G4X(dev_priv))
> {
> - struct {
> - dma_addr_t start, end;
> - } stolen[2] = {
> - { .start = base, .end = base + ggtt->stolen_size, },
> - { .start = base, .end = base + ggtt->stolen_size, },
> + struct resource stolen[2] = {
> + DEFINE_RES_MEM(dsm->start, resource_size(dsm)),
> + DEFINE_RES_MEM(dsm->start, resource_size(dsm)),
struct resource stolen[2] = { *dsm, *dsm } ?
> };
> - u64 ggtt_start, ggtt_end;
> + struct resource ggtt_res;
> + u64 ggtt_start;
> /* Verify that nothing else uses this physical address. Stolen
> * memory should be reserved by the BIOS and hidden from the
> * kernel. So if the region is already marked as busy, something
> * is seriously wrong.
> */
> - r = devm_request_mem_region(dev_priv->drm.dev, base,
> ggtt->stolen_size,
> + r = devm_request_mem_region(dev_priv->drm.dev, dsm->start,
> + resource_size(dsm),
> "Graphics Stolen Memory");
A future task is that we really don't need the allocation here anymore,
and should be able to reserve the resource directly.
> @@ -351,14 +339,18 @@ int i915_gem_init_stolen(struct drm_i915_private
> *dev_priv)
> return 0;
> }
>
> - if (ggtt->stolen_size == 0)
> + if (resource_size(&intel_graphics_stolen_res) == 0)
> return 0;
>
> - dev_priv->mm.stolen_base = i915_stolen_to_dma(dev_priv);
> - if (dev_priv->mm.stolen_base == 0)
> + dev_priv->dsm = intel_graphics_stolen_res;
> +
> + if (i915_adjust_stolen(dev_priv, &dev_priv->dsm))
> return 0;
>
> - stolen_top = dev_priv->mm.stolen_base + ggtt->stolen_size;
> + GEM_BUG_ON(dev_priv->dsm.start == 0);
> + GEM_BUG_ON(resource_size(&dev_priv->dsm) == 0);
GEM_BUG_ON(dsm.end <= dsm.start); instead of size == 0
> +
> + stolen_top = dev_priv->dsm.end + 1;
> reserved_base = 0;
> reserved_size = 0;
>
> @@ -399,12 +391,12 @@ int i915_gem_init_stolen(struct drm_i915_private
> *dev_priv)
> reserved_base = stolen_top;
> }
>
> - if (reserved_base < dev_priv->mm.stolen_base ||
> + if (reserved_base < dev_priv->dsm.start ||
> reserved_base + reserved_size > stolen_top) {
> dma_addr_t reserved_top = reserved_base + reserved_size;
> DRM_ERROR("Stolen reserved area [%pad - %pad] outside stolen
> memory [%pad - %pad]\n",
> &reserved_base, &reserved_top,
> - &dev_priv->mm.stolen_base, &stolen_top);
> + &dev_priv->dsm.start, &stolen_top);
%pR here?
Reviewed-by: Chris Wilson
-Chris
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Re: [Intel-gfx] [PATCH i-g-t v8] tests/kms_frontbuffer_tracking: Including DRRS test coverage
Em Qua, 2017-12-06 às 20:43 +0530, Lohith BS escreveu:
> Dynamic Refresh Rate Switch(DRRS) is used to switch the panel's
> refresh rate to the lowest vrefresh supported by panel, when frame is
> not flipped for more than a Sec.
>
> In kernel, DRRS uses the front buffer tracking infrastructure.
> Hence DRRS test coverage is added along with other frontbuffer
> tracking
> based features such as FBC and PSR tests.
>
> Here, we are testing DRRS with other features in all possible
> combinations, in all required test cases, to capture any possible
> regression.
>
> v2: Addressed the comments and suggestions from Vlad, Marius.
> The signoff details from the earlier work are also included.
>
> v3: Modified vblank rate calculation by using reply-sequence,
> provided by drmWaitVBlank, as suggested by Chris Wilson.
>
> v4: As suggested from Chris Wilson and Daniel Vetter
> 1) Avoided using pthread for calculating vblank refresh rate,
> instead used drmWaitVBlank reply sequence.
> 2) Avoided using kernel-specific info like transitional delays,
> instead polling mechanism with timeout is used.
> 3) Included edp-DRRS as a subtest in kms_frontbuffer_tracking.c,
> instead of having a separate test.
>
> v5: This patch adds DRRS as a new feature in the
> kms_frontbuffer_tracking IGT.
> DRRS switch to lower vrefresh rate is tested at slow-draw
> subtest.
>
> Note:
> 1) Currently kernel doesn't have support to enable and disable
> the DRRS feature dynamically(as in case of PSR). Hence if the
> panel supports DRRS it will be enabled by default.
>
> This is in continuation of last patch
> "https://patchwork.freedesktop.org/patch/162726/";
>
> v6: This patch adds runtime enable and disable feature for testing
> DRRS
>
> v7: This patch adds runtime enable and disable feature for testing
> DRRS
> through debugfs entry "i915_drrs_ctl".
>
> v8: Commit message is updated to reflect current implementation.
Not a full review, but: coding style and indentation needs to be fixed.
There are a few chunks where the only thing the patch does is make
indentation wrong.
There are chunks that only add blank lines.
There are chunks that leave functions without empty lines between them.
There are chunks that add code that do not follow the coding style used
by the rest of the file (which is the same style used by the Kernel).
There are chunks that use white spaces in places where tabs should be
used.
Please review your own patch before we can review it.
FEATURE_COUNT needs to be 8. Any undesired combinations need explicit
code to avoid them with a nice comment explaining why.
>
> Signed-off-by: Lohith BS
> Signed-off-by: aknautiy
> ---
> tests/kms_frontbuffer_tracking.c | 166
> +++
> 1 file changed, 151 insertions(+), 15 deletions(-)
>
> diff --git a/tests/kms_frontbuffer_tracking.c
> b/tests/kms_frontbuffer_tracking.c
> index a068c8a..b06d304 100644
> --- a/tests/kms_frontbuffer_tracking.c
> +++ b/tests/kms_frontbuffer_tracking.c
> @@ -34,7 +34,7 @@
>
>
> IGT_TEST_DESCRIPTION("Test the Kernel's frontbuffer tracking
> mechanism and "
> - "its related features: FBC and PSR");
> + "its related features: FBC, DRRS and PSR");
>
> /*
> * One of the aspects of this test is that, for every subtest, we
> try different
> @@ -105,8 +105,9 @@ struct test_mode {
> FEATURE_NONE = 0,
> FEATURE_FBC = 1,
> FEATURE_PSR = 2,
> - FEATURE_COUNT = 4,
> - FEATURE_DEFAULT = 4,
> + FEATURE_DRRS = 4,
> + FEATURE_COUNT = 6,
> + FEATURE_DEFAULT = 6,
> } feature;
>
> /* Possible pixel formats. We just use FORMAT_DEFAULT for
> most tests and
> @@ -156,6 +157,7 @@ struct rect {
> struct {
> int fd;
> int debugfs;
> + int drrs_debugfs_fd;
> drmModeResPtr res;
> drmModeConnectorPtr connectors[MAX_CONNECTORS];
> drmModeEncoderPtr encoders[MAX_ENCODERS];
> @@ -178,10 +180,8 @@ struct {
>
> struct {
> bool can_test;
> -} psr = {
> - .can_test = false,
> -};
> -
> +} psr = { .can_test = false,},
> +drrs = { .can_test = false,};
>
> #define SINK_CRC_SIZE 12
> typedef struct {
> @@ -775,8 +775,8 @@ static bool set_mode_for_params(struct
> modeset_params *params)
> int rc;
>
> rc = drmModeSetCrtc(drm.fd, params->crtc_id, params->fb.fb-
> >fb_id,
> - params->fb.x, params->fb.y,
> - ¶ms->connector_id, 1, params->mode);
> + params->fb.x, params->fb.y,
> + ¶ms->connector_id, 1, params-
> >mode);
> return (rc == 0);
> }
>
> @@ -822,6 +822,63 @@ static void psr_print_status(void)
> igt_info("PSR status:\n%s\n", buf);
> }
>
> +void drrs_set(unsigned int val)
> +{
> + char buf[16];
> +
> +
[Intel-gfx] [PATCH 04/10] drm/i915: nuke the duplicated stolen discovery
We duplicate the stolen discovery code in early-quirks and in i915,
however now that the stolen region is exported as a resource from
early-quirks we can nuke the duplication.
v2: check overflows_type
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Paulo Zanoni
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c| 51 +--
drivers/gpu/drm/i915/i915_gem_stolen.c | 109 +
2 files changed, 5 insertions(+), 155 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 209bb111f652..036a79fe252d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2949,50 +2949,6 @@ static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
return 0;
}
-static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
-{
- snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
- snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
- return (size_t)snb_gmch_ctl << 25; /* 32 MB units */
-}
-
-static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
-{
- bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
- bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
- return (size_t)bdw_gmch_ctl << 25; /* 32 MB units */
-}
-
-static size_t chv_get_stolen_size(u16 gmch_ctrl)
-{
- gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
- gmch_ctrl &= SNB_GMCH_GMS_MASK;
-
- /*
-* 0x0 to 0x10: 32MB increments starting at 0MB
-* 0x11 to 0x16: 4MB increments starting at 8MB
-* 0x17 to 0x1d: 4MB increments start at 36MB
-*/
- if (gmch_ctrl < 0x11)
- return (size_t)gmch_ctrl << 25;
- else if (gmch_ctrl < 0x17)
- return (size_t)(gmch_ctrl - 0x11 + 2) << 22;
- else
- return (size_t)(gmch_ctrl - 0x17 + 9) << 22;
-}
-
-static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
-{
- gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
- gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
-
- if (gen9_gmch_ctl < 0xf0)
- return (size_t)gen9_gmch_ctl << 25; /* 32 MB units */
- else
- /* 4MB increments starting at 0xf0 for 4MB */
- return (size_t)(gen9_gmch_ctl - 0xf0 + 1) << 22;
-}
-
static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
{
struct drm_i915_private *dev_priv = ggtt->base.i915;
@@ -3343,14 +3299,13 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
+ ggtt->stolen_size = resource_size(&intel_graphics_stolen_res);
+
if (INTEL_GEN(dev_priv) >= 9) {
- ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl);
size = gen8_get_total_gtt_size(snb_gmch_ctl);
} else if (IS_CHERRYVIEW(dev_priv)) {
- ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl);
size = chv_get_total_gtt_size(snb_gmch_ctl);
} else {
- ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl);
size = gen8_get_total_gtt_size(snb_gmch_ctl);
}
@@ -3408,7 +3363,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err);
pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
- ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl);
+ ggtt->stolen_size = resource_size(&intel_graphics_stolen_res);
size = gen6_get_total_gtt_size(snb_gmch_ctl);
ggtt->base.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 1877ae9a1d9b..f8ac1438c35d 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -30,9 +30,6 @@
#include
#include "i915_drv.h"
-#define KB(x) ((x) * 1024)
-#define MB(x) (KB(x) * 1024)
-
/*
* The BIOS typically reserves some of the system's memory for the exclusive
* use of the integrated graphics. This memory is no longer available for
@@ -81,113 +78,11 @@ void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv,
static dma_addr_t i915_stolen_to_dma(struct drm_i915_private *dev_priv)
{
- struct pci_dev *pdev = dev_priv->drm.pdev;
struct i915_ggtt *ggtt = &dev_priv->ggtt;
+ dma_addr_t base = intel_graphics_stolen_res.start;
struct resource *r;
- dma_addr_t base;
-
- /* Almost universally we can find the Graphics Base of Stolen Memory
-* at register BSM (0x5c) in the igfx configuration space. On a few
-* (desktop) machines this is also mirrored in the bridge device at
-* different locations, or in the MCHBAR.
-*
-* On 865 we just check the TOUD register.
-*
-* On 830/845/85x the stolen memory base isn't available in any
-* register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
-*
-*/
- base = 0;
- i
[Intel-gfx] [PATCH 10/10] drm/i915: prefer stolen_usable_size for the range sanity check
In i915_pages_create_for_stolen it probably makes more sense to check if the range overflows the stolen_usable_size, since the size of dsm will also include the reserved portion which we can't touch. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Chris Wilson Cc: Paulo Zanoni --- drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c index 2267af68c3e1..f8c9f0446712 100644 --- a/drivers/gpu/drm/i915/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c @@ -430,7 +430,7 @@ i915_pages_create_for_stolen(struct drm_device *dev, struct sg_table *st; struct scatterlist *sg; - GEM_BUG_ON(range_overflows(offset, size, resource_size(&dev_priv->dsm))); + GEM_BUG_ON(range_overflows(offset, size, dev_priv->stolen_usable_size)); /* We hide that we have no struct page backing our stolen object * by wrapping the contiguous physical allocation with a fake -- 2.14.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/10] x86/early-quirks: reverse the if ladders
Makes things a little easier to follow.
Suggested-by: Ville Syrjälä
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Ville Syrjälä
Cc: Chris Wilson
Cc: Paulo Zanoni
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: H. Peter Anvin
Cc: x...@kernel.org
Cc: linux-ker...@vger.kernel.org
Reviewed-by: Ville Syrjälä
---
arch/x86/kernel/early-quirks.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index b5b912f3dce8..ba6e96381bfc 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -425,12 +425,12 @@ static resource_size_t __init chv_stolen_size(int num,
int slot, int func)
* 0x11 to 0x16: 4MB increments starting at 8MB
* 0x17 to 0x1d: 4MB increments start at 36MB
*/
- if (gms < 0x11)
- return gms * MB(32);
- else if (gms < 0x17)
+ if (gms >= 0x17)
+ return (gms - 0x17) * MB(4) + MB(36);
+ else if (gms >= 0x11)
return (gms - 0x11) * MB(4) + MB(8);
else
- return (gms - 0x17) * MB(4) + MB(36);
+ return gms * MB(32);
}
static resource_size_t __init gen9_stolen_size(int num, int slot, int func)
@@ -443,10 +443,10 @@ static resource_size_t __init gen9_stolen_size(int num,
int slot, int func)
/* 0x0 to 0xef: 32MB increments starting at 0MB */
/* 0xf0 to 0xfe: 4MB increments starting at 4MB */
- if (gms < 0xf0)
- return gms * MB(32);
- else
+ if (gms >= 0xf0)
return (gms - 0xf0) * MB(4) + MB(4);
+ else
+ return gms * MB(32);
}
struct intel_early_ops {
--
2.14.3
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[Intel-gfx] [PATCH 09/10] drm/i915: prefer resource_size_t for everything stolen
Keeps things consistent now that we make use of struct resource. This
should keep us covered in case we ever get huge amounts of stolen
memory.
v2: bunch of missing conversions (Chris)
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Paulo Zanoni
---
drivers/char/agp/intel-gtt.c | 12 +-
drivers/gpu/drm/i915/i915_debugfs.c| 4 ++--
drivers/gpu/drm/i915/i915_drv.h| 11 +-
drivers/gpu/drm/i915/i915_gem_gtt.c| 10 -
drivers/gpu/drm/i915/i915_gem_gtt.h| 2 +-
drivers/gpu/drm/i915/i915_gem_stolen.c | 40 +-
drivers/gpu/drm/i915/intel_pm.c| 10 -
include/drm/intel-gtt.h| 2 +-
8 files changed, 46 insertions(+), 45 deletions(-)
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 050708e4562e..b1c0859ed68b 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -80,7 +80,7 @@ static struct _intel_private {
unsigned int needs_dmar : 1;
phys_addr_t gma_bus_addr;
/* Size of memory reserved for graphics by the BIOS */
- unsigned int stolen_size;
+ resource_size_t stolen_size;
/* Total number of gtt entries. */
unsigned int gtt_total_entries;
/* Part of the gtt that is mappable by the cpu, for those chips where
@@ -333,13 +333,13 @@ static void i810_write_entry(dma_addr_t addr, unsigned
int entry,
writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
}
-static unsigned int intel_gtt_stolen_size(void)
+static resource_size_t intel_gtt_stolen_size(void)
{
u16 gmch_ctrl;
u8 rdct;
int local = 0;
static const int ddt[4] = { 0, 16, 32, 64 };
- unsigned int stolen_size = 0;
+ resource_size_t stolen_size = 0;
if (INTEL_GTT_GEN == 1)
return 0; /* no stolen mem on i81x */
@@ -417,8 +417,8 @@ static unsigned int intel_gtt_stolen_size(void)
}
if (stolen_size > 0) {
- dev_info(&intel_private.bridge_dev->dev, "detected %dK %s
memory\n",
- stolen_size / KB(1), local ? "local" : "stolen");
+ dev_info(&intel_private.bridge_dev->dev, "detected %lluK %s
memory\n",
+ (u64)stolen_size / KB(1), local ? "local" : "stolen");
} else {
dev_info(&intel_private.bridge_dev->dev,
"no pre-allocated video memory detected\n");
@@ -1423,7 +1423,7 @@ EXPORT_SYMBOL(intel_gmch_probe);
void intel_gtt_get(u64 *gtt_total,
phys_addr_t *mappable_base,
- u64 *mappable_end)
+ resource_size_t *mappable_end)
{
*gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT;
*mappable_base = intel_private.gma_bus_addr;
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 28294470ae31..fad4116f61c5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -522,8 +522,8 @@ static int i915_gem_object_info(struct seq_file *m, void
*data)
seq_printf(m, "%u display objects (globally pinned), %llu bytes\n",
dpy_count, dpy_size);
- seq_printf(m, "%llu [%llu] gtt total\n",
- ggtt->base.total, ggtt->mappable_end);
+ seq_printf(m, "%llu [%pa] gtt total\n",
+ ggtt->base.total, &ggtt->mappable_end);
seq_printf(m, "Supported page sizes: %s\n",
stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes,
buf, sizeof(buf)));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2c3e1d715c11..66bde0210b80 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2271,7 +2271,7 @@ struct drm_i915_private {
* avoid the first page! The upper end of stolen memory is reserved for
* hardware functions and similarly removed from the accessible range.
*/
- u32 stolen_usable_size; /* Total size minus reserved ranges */
+ resource_size_t stolen_usable_size; /* Total size minus reserved
ranges */
void __iomem *regs;
@@ -3928,12 +3928,13 @@ void i915_gem_stolen_remove_node(struct
drm_i915_private *dev_priv,
int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_stolen(struct drm_device *dev);
struct drm_i915_gem_object *
-i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
+i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
+ resource_size_t size);
struct drm_i915_gem_object *
i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private
*dev_priv,
- u32 stolen_offset,
- u32 gtt_offset,
-
[Intel-gfx] [PATCH 05/10] drm/i915: make dsm struct resource centric
Now that we are using struct resource to track the stolen region, it is
more convenient if we track dsm in a resource as well.
v2: check range_overflow when writing to 32b registers (Chris)
pepper in some comments (Chris)
v3: refit i915_stolen_to_dma()
v4: kill ggtt->stolen_size
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Paulo Zanoni
---
drivers/char/agp/intel-gtt.c | 2 -
drivers/gpu/drm/i915/i915_drv.h| 12 +++-
drivers/gpu/drm/i915/i915_gem_gtt.c| 8 +--
drivers/gpu/drm/i915/i915_gem_gtt.h| 1 -
drivers/gpu/drm/i915/i915_gem_stolen.c | 111 +++--
drivers/gpu/drm/i915/intel_fbc.c | 13 ++--
drivers/gpu/drm/i915/intel_pm.c| 15 +++--
include/drm/intel-gtt.h| 1 -
8 files changed, 81 insertions(+), 82 deletions(-)
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 9b6b6023193b..050708e4562e 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1422,12 +1422,10 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev,
struct pci_dev *gpu_pdev,
EXPORT_SYMBOL(intel_gmch_probe);
void intel_gtt_get(u64 *gtt_total,
- u32 *stolen_size,
phys_addr_t *mappable_base,
u64 *mappable_end)
{
*gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT;
- *stolen_size = intel_private.stolen_size;
*mappable_base = intel_private.gma_bus_addr;
*mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 02551c781f0a..e88fab552278 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1537,9 +1537,6 @@ struct i915_gem_mm {
*/
struct pagevec wc_stash;
- /** Usable portion of the GTT for GEM */
- dma_addr_t stolen_base; /* limited to low memory (32-bit) */
-
/**
* tmpfs instance used for shmem backed objects
*/
@@ -2253,6 +2250,15 @@ struct drm_i915_private {
const struct intel_device_info info;
+ /**
+* Data Stolen Memory - aka "i915 stolen memory" gives us the start and
+* end of stolen which we can optionally use to create GEM objects
+* backed by stolen memory. Note that ggtt->stolen_usable_size tells us
+* exactly how much of this we are actually allowed to use, given that
+* some portion of it is in fact reserved for use by hardware functions.
+*/
+ struct resource dsm;
+
void __iomem *regs;
struct intel_uncore uncore;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 036a79fe252d..62dd90e00c3a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3299,8 +3299,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
- ggtt->stolen_size = resource_size(&intel_graphics_stolen_res);
-
if (INTEL_GEN(dev_priv) >= 9) {
size = gen8_get_total_gtt_size(snb_gmch_ctl);
} else if (IS_CHERRYVIEW(dev_priv)) {
@@ -3363,8 +3361,6 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err);
pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
- ggtt->stolen_size = resource_size(&intel_graphics_stolen_res);
-
size = gen6_get_total_gtt_size(snb_gmch_ctl);
ggtt->base.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
@@ -3410,7 +3406,6 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt)
}
intel_gtt_get(&ggtt->base.total,
- &ggtt->stolen_size,
&ggtt->mappable_base,
&ggtt->mappable_end);
@@ -3482,7 +3477,8 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
DRM_INFO("Memory usable by graphics device = %lluM\n",
ggtt->base.total >> 20);
DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt->mappable_end >> 20);
- DRM_DEBUG_DRIVER("GTT stolen size = %uM\n", ggtt->stolen_size >> 20);
+ DRM_DEBUG_DRIVER("GTT stolen size = %lluM\n",
+(u64)resource_size(&intel_graphics_stolen_res) >> 20);
if (intel_vtd_active())
DRM_INFO("VT-d active for gfx access\n");
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 93211a96fdad..30a2920b1291 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -381,7 +381,6 @@ struct i915_ggtt {
* avoid the first page! The upper end of stolen memory is reserved for
* hardware functions and similarly removed from the accessible range.
*/
- u32 stolen_size;/* Total size of stolen memory */
[Intel-gfx] [PATCH 06/10] drm/i915: make reserved struct resource centric
Now that we are using struct resource to track the stolen region, it is
more convenient if we track the reserved portion of that region in a
resource as well.
v2: s/<= end + 1/< end/ (Chris)
v3: prefer DEFINE_RES_MEM
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Paulo Zanoni
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h| 4
drivers/gpu/drm/i915/i915_gem_gtt.h| 2 --
drivers/gpu/drm/i915/i915_gem_stolen.c | 15 ++-
drivers/gpu/drm/i915/intel_pm.c| 6 ++
4 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e88fab552278..40171a7da9d9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2258,6 +2258,10 @@ struct drm_i915_private {
* some portion of it is in fact reserved for use by hardware functions.
*/
struct resource dsm;
+ /**
+* Reseved portion of Data Stolen Memory
+*/
+ struct resource dsm_reserved;
void __iomem *regs;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 30a2920b1291..db20c72ecfc8 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -382,8 +382,6 @@ struct i915_ggtt {
* hardware functions and similarly removed from the accessible range.
*/
u32 stolen_usable_size; /* Total size minus reserved ranges */
- u32 stolen_reserved_base;
- u32 stolen_reserved_size;
/** "Graphics Stolen Memory" holds the global PTEs */
void __iomem *gsm;
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index f2ef5c3788b9..18d8e4556b11 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -391,18 +391,15 @@ int i915_gem_init_stolen(struct drm_i915_private
*dev_priv)
reserved_base = stolen_top;
}
- if (reserved_base < dev_priv->dsm.start ||
- reserved_base + reserved_size > stolen_top) {
- dma_addr_t reserved_top = reserved_base + reserved_size;
- DRM_ERROR("Stolen reserved area [%pad - %pad] outside stolen
memory [%pad - %pad]\n",
- &reserved_base, &reserved_top,
- &dev_priv->dsm.start, &stolen_top);
+ dev_priv->dsm_reserved =
+ (struct resource) DEFINE_RES_MEM(reserved_base, reserved_size);
+
+ if (!resource_contains(&dev_priv->dsm, &dev_priv->dsm_reserved)) {
+ DRM_ERROR("Stolen reserved area %pR outside stolen memory
%pR\n",
+ &dev_priv->dsm_reserved, &dev_priv->dsm);
return 0;
}
- ggtt->stolen_reserved_base = reserved_base;
- ggtt->stolen_reserved_size = reserved_size;
-
/* It is possible for the reserved area to end before the end of stolen
* memory, so just consider the start. */
reserved_total = stolen_top - reserved_base;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 79b3fd617de0..57dcf8e1ff30 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6416,7 +6416,6 @@ static void valleyview_disable_rps(struct
drm_i915_private *dev_priv)
static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
{
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
bool enable_rc6 = true;
unsigned long rc6_ctx_base;
u32 rc_ctl;
@@ -6441,9 +6440,8 @@ static bool bxt_check_bios_rc6_setup(struct
drm_i915_private *dev_priv)
* for this check.
*/
rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
- if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
- (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
- ggtt->stolen_reserved_size))) {
+ if (!((rc6_ctx_base >= dev_priv->dsm_reserved.start) &&
+ (rc6_ctx_base + PAGE_SIZE < dev_priv->dsm_reserved.end))) {
DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
enable_rc6 = false;
}
--
2.14.3
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/10] drm/i915: give stolen_usable_size a more suitable home
Kick it out of i915_ggtt and keep it grouped with dsm and dsm_reserved,
where it makes the most sense.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.h| 12 +++-
drivers/gpu/drm/i915/i915_gem_gtt.h| 10 --
drivers/gpu/drm/i915/i915_gem_stolen.c | 5 ++---
drivers/gpu/drm/i915/intel_display.c | 3 +--
drivers/gpu/drm/i915/intel_fbdev.c | 3 +--
5 files changed, 15 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 40171a7da9d9..2c3e1d715c11 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2253,7 +2253,7 @@ struct drm_i915_private {
/**
* Data Stolen Memory - aka "i915 stolen memory" gives us the start and
* end of stolen which we can optionally use to create GEM objects
-* backed by stolen memory. Note that ggtt->stolen_usable_size tells us
+* backed by stolen memory. Note that stolen_usable_size tells us
* exactly how much of this we are actually allowed to use, given that
* some portion of it is in fact reserved for use by hardware functions.
*/
@@ -2263,6 +2263,16 @@ struct drm_i915_private {
*/
struct resource dsm_reserved;
+ /* Stolen memory is segmented in hardware with different portions
+* offlimits to certain functions.
+*
+* The drm_mm is initialised to the total accessible range, as found
+* from the PCI config. On Broadwell+, this is further restricted to
+* avoid the first page! The upper end of stolen memory is reserved for
+* hardware functions and similarly removed from the accessible range.
+*/
+ u32 stolen_usable_size; /* Total size minus reserved ranges */
+
void __iomem *regs;
struct intel_uncore uncore;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 4a17ce36281a..e5aa07ceb627 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -373,16 +373,6 @@ struct i915_ggtt {
struct resource gmadr; /* GMADR resource */
u64 mappable_end; /* End offset that we can CPU map */
- /* Stolen memory is segmented in hardware with different portions
-* offlimits to certain functions.
-*
-* The drm_mm is initialised to the total accessible range, as found
-* from the PCI config. On Broadwell+, this is further restricted to
-* avoid the first page! The upper end of stolen memory is reserved for
-* hardware functions and similarly removed from the accessible range.
-*/
- u32 stolen_usable_size; /* Total size minus reserved ranges */
-
/** "Graphics Stolen Memory" holds the global PTEs */
void __iomem *gsm;
void (*invalidate)(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 18d8e4556b11..c3a09d665047 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -322,7 +322,6 @@ static void bdw_get_stolen_reserved(struct drm_i915_private
*dev_priv,
int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
{
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
dma_addr_t reserved_base, stolen_top;
u32 reserved_total, reserved_size;
u32 stolen_usable_start;
@@ -413,12 +412,12 @@ int i915_gem_init_stolen(struct drm_i915_private
*dev_priv)
if (INTEL_GEN(dev_priv) >= 8)
stolen_usable_start = 4096;
- ggtt->stolen_usable_size =
+ dev_priv->stolen_usable_size =
resource_size(&dev_priv->dsm) - reserved_total -
stolen_usable_start;
/* Basic memrange allocator for stolen space. */
drm_mm_init(&dev_priv->mm.stolen, stolen_usable_start,
- ggtt->stolen_usable_size);
+ dev_priv->stolen_usable_size);
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 0098738d3740..f1e0e838b2a7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2639,7 +2639,6 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
struct drm_i915_gem_object *obj = NULL;
struct drm_mode_fb_cmd2 mode_cmd = { 0 };
struct drm_framebuffer *fb = &plane_config->fb->base;
@@ -2655,7 +2654,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
/* If the FB is too big, just don't use it since fbdev is not very
* important and we should probably use that space with FBC or other
* features. */
[Intel-gfx] [PATCH 07/10] drm/i915: make mappable struct resource centric
Now that we are using struct resource to track the stolen region, it is
more convenient if we track the mappable region in a resource as well.
v2: prefer iomap and gmadr naming scheme
prefer DEFINE_RES_MEM
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Paulo Zanoni
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gvt/gvt.h| 2 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 8
drivers/gpu/drm/i915/i915_gem_execbuffer.c| 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 29 ++-
drivers/gpu/drm/i915/i915_gem_gtt.h | 4 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_overlay.c | 4 ++--
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 ++--
drivers/gpu/drm/i915/selftests/mock_gtt.c | 4 ++--
12 files changed, 37 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 77df9bad5dea..103910a24e4b 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -348,7 +348,7 @@ int intel_gvt_load_firmware(struct intel_gvt *gvt);
/* Aperture/GM space definitions for GVT device */
#define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end)
-#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base)
+#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.gmadr.start)
#define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.base.total)
#define gvt_ggtt_sz(gvt) \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5b1fd5f1defb..54a8fca7e7b2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -726,7 +726,7 @@ static int i915_kick_out_firmware_fb(struct
drm_i915_private *dev_priv)
if (!ap)
return -ENOMEM;
- ap->ranges[0].base = ggtt->mappable_base;
+ ap->ranges[0].base = ggtt->gmadr.start;
ap->ranges[0].size = ggtt->mappable_end;
primary =
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 80b78fb5daac..ff62e2458dfe 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1099,7 +1099,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
page_base += offset & PAGE_MASK;
}
- if (gtt_user_read(&ggtt->mappable, page_base, page_offset,
+ if (gtt_user_read(&ggtt->iomap, page_base, page_offset,
user_data, page_length)) {
ret = -EFAULT;
break;
@@ -1307,7 +1307,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
* If the object is non-shmem backed, we retry again with the
* path that handles page fault.
*/
- if (ggtt_write(&ggtt->mappable, page_base, page_offset,
+ if (ggtt_write(&ggtt->iomap, page_base, page_offset,
user_data, page_length)) {
ret = -EFAULT;
break;
@@ -1953,9 +1953,9 @@ int i915_gem_fault(struct vm_fault *vmf)
/* Finally, remap it using the new GTT offset */
ret = remap_io_mapping(area,
area->vm_start + (vma->ggtt_view.partial.offset
<< PAGE_SHIFT),
- (ggtt->mappable_base + vma->node.start) >>
PAGE_SHIFT,
+ (ggtt->gmadr.start + vma->node.start) >>
PAGE_SHIFT,
min_t(u64, vma->size, area->vm_end -
area->vm_start),
- &ggtt->mappable);
+ &ggtt->iomap);
if (ret)
goto err_fence;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 70ccd63cbf8e..4401068ff468 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1012,7 +1012,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj,
offset += page << PAGE_SHIFT;
}
- vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->mappable,
+ vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->iomap,
offset);
cache->page = page;
cache->vaddr = (unsigned long)vaddr;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 62dd90e00c3a..09c425e35b56 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2912,7 +2912,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private
*dev_priv)
mutex_unlock(&dev_priv->drm.struct_mutex);
[Intel-gfx] [PATCH 01/10] x86/early-quirks: Extend Intel graphics stolen memory placement to 64bit
From: Joonas Lahtinen
To give upcoming SKU BIOSes more flexibility in placing the Intel
graphics stolen memory, make all variables storing the placement or size
compatible with full 64 bit range. Also by exporting the stolen region
as a resource, we can then nuke the duplicated stolen discovery in i915.
v2: export the stolen region as a resource
fix u16 << 16 (Chris)
v3: actually fix u16 << 16
Signed-off-by: Joonas Lahtinen
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Ville Syrjälä
Cc: Chris Wilson
Cc: Paulo Zanoni
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: H. Peter Anvin
Cc: x...@kernel.org
Cc: linux-ker...@vger.kernel.org
Reviewed-by: Chris Wilson #v1
---
arch/x86/kernel/early-quirks.c | 86 +++---
include/drm/i915_drm.h | 3 ++
2 files changed, 50 insertions(+), 39 deletions(-)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 1e82f787c160..d7236e2f5eed 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -243,7 +243,7 @@ static void __init intel_remapping_check(int num, int slot,
int func)
#define KB(x) ((x) * 1024UL)
#define MB(x) (KB (KB (x)))
-static size_t __init i830_tseg_size(void)
+static resource_size_t __init i830_tseg_size(void)
{
u8 esmramc = read_pci_config_byte(0, 0, 0, I830_ESMRAMC);
@@ -256,7 +256,7 @@ static size_t __init i830_tseg_size(void)
return KB(512);
}
-static size_t __init i845_tseg_size(void)
+static resource_size_t __init i845_tseg_size(void)
{
u8 esmramc = read_pci_config_byte(0, 0, 0, I845_ESMRAMC);
u8 tseg_size = esmramc & I845_TSEG_SIZE_MASK;
@@ -273,7 +273,7 @@ static size_t __init i845_tseg_size(void)
return 0;
}
-static size_t __init i85x_tseg_size(void)
+static resource_size_t __init i85x_tseg_size(void)
{
u8 esmramc = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC);
@@ -283,12 +283,12 @@ static size_t __init i85x_tseg_size(void)
return MB(1);
}
-static size_t __init i830_mem_size(void)
+static resource_size_t __init i830_mem_size(void)
{
return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32);
}
-static size_t __init i85x_mem_size(void)
+static resource_size_t __init i85x_mem_size(void)
{
return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32);
}
@@ -297,36 +297,36 @@ static size_t __init i85x_mem_size(void)
* On 830/845/85x the stolen memory base isn't available in any
* register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
*/
-static phys_addr_t __init i830_stolen_base(int num, int slot, int func,
- size_t stolen_size)
+static resource_size_t __init i830_stolen_base(int num, int slot, int func,
+ resource_size_t stolen_size)
{
- return (phys_addr_t)i830_mem_size() - i830_tseg_size() - stolen_size;
+ return i830_mem_size() - i830_tseg_size() - stolen_size;
}
-static phys_addr_t __init i845_stolen_base(int num, int slot, int func,
- size_t stolen_size)
+static resource_size_t __init i845_stolen_base(int num, int slot, int func,
+ resource_size_t stolen_size)
{
- return (phys_addr_t)i830_mem_size() - i845_tseg_size() - stolen_size;
+ return i830_mem_size() - i845_tseg_size() - stolen_size;
}
-static phys_addr_t __init i85x_stolen_base(int num, int slot, int func,
- size_t stolen_size)
+static resource_size_t __init i85x_stolen_base(int num, int slot, int func,
+ resource_size_t stolen_size)
{
- return (phys_addr_t)i85x_mem_size() - i85x_tseg_size() - stolen_size;
+ return i85x_mem_size() - i85x_tseg_size() - stolen_size;
}
-static phys_addr_t __init i865_stolen_base(int num, int slot, int func,
- size_t stolen_size)
+static resource_size_t __init i865_stolen_base(int num, int slot, int func,
+ resource_size_t stolen_size)
{
u16 toud = 0;
toud = read_pci_config_16(0, 0, 0, I865_TOUD);
- return (phys_addr_t)(toud << 16) + i845_tseg_size();
+ return (toud * KB(64)) + i845_tseg_size();
}
-static phys_addr_t __init gen3_stolen_base(int num, int slot, int func,
- size_t stolen_size)
+static resource_size_t __init gen3_stolen_base(int num, int slot, int func,
+ resource_size_t stolen_size)
{
u32 bsm;
@@ -337,10 +337,10 @@ static phys_addr_t __init gen3_stolen_base(int num, int
slot, int func,
*/
bsm = read_pci_config(num, slot, func, INTEL_BSM);
- return (phys_addr_t)bsm & INTEL_BSM_MASK;
+ return bsm & INTEL_BSM_MASK;
}
-static size_t __init i830_stolen_size(int num, int sl
[Intel-gfx] [PATCH 00/10] make stolen resource centric
Continuation of Paulo' stolen series[1], addressing the feedback from Joonas and Chris. [1] https://patchwork.freedesktop.org/series/30923/ Joonas Lahtinen (1): x86/early-quirks: Extend Intel graphics stolen memory placement to 64bit Matthew Auld (9): x86/early-quirks: replace the magical increment start values x86/early-quirks: reverse the if ladders drm/i915: nuke the duplicated stolen discovery drm/i915: make dsm struct resource centric drm/i915: make reserved struct resource centric drm/i915: make mappable struct resource centric drm/i915: give stolen_usable_size a more suitable home drm/i915: prefer resource_size_t for everything stolen drm/i915: prefer stolen_usable_size for the range sanity check arch/x86/kernel/early-quirks.c| 92 + drivers/char/agp/intel-gtt.c | 14 +- drivers/gpu/drm/i915/gvt/gvt.h| 2 +- drivers/gpu/drm/i915/i915_debugfs.c | 4 +- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 35 +++- drivers/gpu/drm/i915/i915_gem.c | 8 +- drivers/gpu/drm/i915/i915_gem_execbuffer.c| 2 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 92 +++-- drivers/gpu/drm/i915/i915_gem_gtt.h | 19 +- drivers/gpu/drm/i915/i915_gem_stolen.c| 264 -- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- drivers/gpu/drm/i915/i915_vma.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 5 +- drivers/gpu/drm/i915/intel_fbc.c | 13 +- drivers/gpu/drm/i915/intel_fbdev.c| 3 +- drivers/gpu/drm/i915/intel_overlay.c | 4 +- drivers/gpu/drm/i915/intel_pm.c | 31 +-- drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 +- drivers/gpu/drm/i915/selftests/mock_gtt.c | 4 +- include/drm/i915_drm.h| 3 + include/drm/intel-gtt.h | 3 +- 22 files changed, 236 insertions(+), 372 deletions(-) -- 2.14.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/10] x86/early-quirks: replace the magical increment start values
Replace the magical +2, +9 etc. with +MB, which is far easier to read.
Suggested-by: Ville Syrjälä
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Ville Syrjälä
Cc: Chris Wilson
Cc: Paulo Zanoni
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: H. Peter Anvin
Cc: x...@kernel.org
Cc: linux-ker...@vger.kernel.org
Reviewed-by: Ville Syrjälä
---
arch/x86/kernel/early-quirks.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index d7236e2f5eed..b5b912f3dce8 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -428,9 +428,9 @@ static resource_size_t __init chv_stolen_size(int num, int
slot, int func)
if (gms < 0x11)
return gms * MB(32);
else if (gms < 0x17)
- return (gms - 0x11 + 2) * MB(4);
+ return (gms - 0x11) * MB(4) + MB(8);
else
- return (gms - 0x17 + 9) * MB(4);
+ return (gms - 0x17) * MB(4) + MB(36);
}
static resource_size_t __init gen9_stolen_size(int num, int slot, int func)
@@ -446,7 +446,7 @@ static resource_size_t __init gen9_stolen_size(int num, int
slot, int func)
if (gms < 0xf0)
return gms * MB(32);
else
- return (gms - 0xf0 + 1) * MB(4);
+ return (gms - 0xf0) * MB(4) + MB(4);
}
struct intel_early_ops {
--
2.14.3
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Re: [Intel-gfx] HDCP as a Kconfig option
-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 On 04/12/17 15:24, Daniel Vetter wrote: > Hi, > > I understand there there's concerns about the content protection > stuff, but please note: > > - The patches under discussion enforce nothing, they only allow you > to enable HDCP if you chose to do so. For real content protection > you need a complete system, locked down with secure boot or > similar. I think any user concerned about their software freedoms > knows to avoid such systems like the plague. I am glad to learn this, as I am sure many others are. > - Second, the code doesn't run by default at all. You can try to > enable HDCP only by explicitly requesting content protection > through a drm property (which I think should be exposed to xrandr > by default at least for the modesetting driver). Enterprising users > can try out what happens if they want to, but by default nothing at > all happens. So no risk of random breakage due to this. Okay, this is truly the important part. Giving the users the freedom to choose what they want to do is ideal. The risk of random breakage was my main concern, especially after having dealt with some pretty nasty HDCP surprises with Apple drivers for Intel GPUs. Is this something that must be configured by the user then; i.e. software cannot itself tell the DRM layer to enable it, it must be set as an xorg.conf property (or similar)? Or can any software request it via xrandr once it's stable? I would be able to see both sides of the argument, as you don't want end users to have to play with xorg.conf just to make (ex.) streaming work, but I also would be concerned that users don't know their freedoms are being taken from them if HDCP was something that software could silently enable. Perhaps a property to force off / default off / default on / force on might be useful for the driver. I'm afraid I am not sure how feasible that would be, but it might be something to consider down the line. Then distros and users could determine what works best for them, and it could be changed at any time without recompiling the kernel. > Given those two reasons I don't think we need a Kconfig option to > disable the code even harder. I hope that explains the situation, > and why the patches don't have a Kconfig option from the start. Yes, this explanation is great. I really appreciate your prompt response and the clarity you've provided. :) > Also thanks very much for reaching out to developers instead of > everyone else who just panics on forums and passes around silly > conspiracy theories. We definitely don't want to merge code which > would hurt our users, that would kinda defeat the point of doing > an open source driver. I don't think this is the case here. After understanding this further (trying to read the code itself was a bit gnarly, as the DRM layer is in general for me, so I admit I couldn't tell whether or not it was on by default), I agree that this isn't the case. Again, thank you so much for offering your time to clear up the situation. We (the Adélie team, and the Linux user base in general) appreciate the work you do, and your time in clearing this up. All the best to you and yours, - --arw - -- A. Wilcox (awilfox) Project Lead, Adélie Linux http://adelielinux.org -BEGIN PGP SIGNATURE- Version: GnuPG v2 iQIcBAEBCAAGBQJaJ0XHAAoJEMspy1GSK50UswEP/Rl3mZPVx/FXj/G4ITV7XkEO dfvQMBjkWq7SehbRrQH9KV+4TUBffi2bV/X3RZaeGrgdWVix3vAiyPbfWYaTP/Dv VTDonhCFrpg7MZ530H+w+2huKEHTHrZ5lo8lajzGAcmLjYKoFjqWP1EsO3vS34oy ZgGtU8kJSitnDDp0/qUKzVWf374zpuXoHSXEXHlEpslJZiyNTCiNhACnW//2VUq7 c7CSl9UqEaHnqIN54QNQVZ+ORqdNHMJv9XCCoL7BV+RwD8rkKCE+5+nSuUc3E5vg VbYpwc7fIKH834+1CaWnfYb5Qr10hFKGdFKHu+R7HRAR4YWDHSdjEGZFsZ3v6c6X 8Klf1nywwdaycHeNikf/1dSi8Su/I9jHsRv2wcJJJgRFxx9yz7i7RTtrmagi1OSP tHV4306/KbQVS8VYeBYaygJz1k4Yk+pE26g1G/EXeo6YWnPj7Ev2nML+3wUnP7nP mXgTLMuFRT51tM+WxMy8o2usWwnF/bB70mafRuQIyKZqJbhO5quBdno4qqAVUcvL ppcNCoS6bf1A71D19iaBQUarkD8mE2dUG5rFuAoMWLgPOua5kxatrvA9WJxAMC9I vgXW6+czx7X/ZqO8JpKnlDdmqeEtY76knT3uVRwHHFwN+46HIeJ7iWjZXwCmopeH yaatW4/va//jPmW1ilBd =M9bh -END PGP SIGNATURE- ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Prevent machine hang from Broxton's vtd w/a and error capture (rev2)
== Series Details == Series: drm/i915: Prevent machine hang from Broxton's vtd w/a and error capture (rev2) URL : https://patchwork.freedesktop.org/series/34969/ State : success == Summary == Test kms_frontbuffer_tracking: Subgroup fbc-1p-offscren-pri-shrfb-draw-render: pass -> FAIL (shard-snb) fdo#101623 Test kms_flip: Subgroup vblank-vs-dpms-suspend-interruptible: incomplete -> PASS (shard-hsw) fdo#103706 +1 Subgroup vblank-vs-modeset-suspend: skip -> PASS (shard-hsw) Test kms_setmode: Subgroup basic: pass -> FAIL (shard-hsw) fdo#99912 fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623 fdo#103706 https://bugs.freedesktop.org/show_bug.cgi?id=103706 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 shard-hswtotal:2527 pass:1455 dwarn:1 dfail:0 fail:10 skip:1061 time:8932s shard-snbtotal:2679 pass:1308 dwarn:1 dfail:0 fail:12 skip:1358 time:8101s Blacklisted hosts: shard-apltotal:2679 pass:1676 dwarn:2 dfail:0 fail:24 skip:977 time:13526s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7429/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] lib: Export kmsg()
== Series Details == Series: series starting with [1/2] lib: Export kmsg() URL : https://patchwork.freedesktop.org/series/34974/ State : success == Summary == IGT patchset tested on top of latest successful build 1db12466cb5ad8483cd469753d2e312a62d717b7 meson: build a full dependency for lib_igt_perf with latest DRM-Tip kernel build CI_DRM_3466 66be57731a40 drm-tip: 2017y-12m-06d-16h-12m-57s UTC integration manifest No testlist changes. Test debugfs_test: Subgroup read_all_entries: dmesg-warn -> PASS (fi-elk-e7500) fdo#103989 +1 Test gem_mmap_gtt: Subgroup basic-small-bo-tiledx: pass -> FAIL (fi-gdg-551) fdo#102575 fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:442s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:390s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:528s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:283s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:509s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:509s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:491s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:476s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:273s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:542s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:375s fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:267s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:484s fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:450s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:530s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:474s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:530s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:589s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:455s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:542s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:569s fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:517s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:506s fi-snb-2520m total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:548s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:420s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:603s fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:640s fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:498s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_603/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Prevent machine hang from Broxton's vtd w/a and error capture
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Bloomfield, Jon
> Sent: Wednesday, December 6, 2017 9:01 AM
> To: Chris Wilson ; intel-gfx@lists.freedesktop.org
> Cc: Daniel Vetter
> Subject: Re: [Intel-gfx] [PATCH v2] drm/i915: Prevent machine hang from
> Broxton's vtd w/a and error capture
>
> > -Original Message-
> > From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> > Sent: Wednesday, December 6, 2017 7:38 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Chris Wilson ; Bloomfield, Jon
> > ; Harrison, John C
> ;
> > Ursulin, Tvrtko ; Joonas Lahtinen
> > ; Daniel Vetter
> > Subject: [PATCH v2] drm/i915: Prevent machine hang from Broxton's vtd
> w/a
> > and error capture
> >
> > Since capturing the error state requires fiddling around with the GGTT
> > to read arbitrary buffers and is itself run under stop_machine(), it
> > deadlocks the machine (effectively a hard hang) when run in conjunction
> > with Broxton's VTd workaround to serialize GGTT access.
> >
> > v2: Store the ERR_PTR in first_error so that the error can be reported
> > to the user via sysfs.
> >
> > Fixes: 0ef34ad6222a ("drm/i915: Serialize GTT/Aperture accesses on BXT")
> > Signed-off-by: Chris Wilson
> > Cc: Jon Bloomfield
> > Cc: John Harrison
> > Cc: Tvrtko Ursulin
> > Cc: Joonas Lahtinen
> > Cc: Daniel Vetter
>
> It's a real shame to lose error capture on BXT. Can we wrap stop_machine to
> make it recursive ?
>
> Something like...
>
> static cpumask_t sm_mask;
>
> struct sm_args {
> cpu_stop_fn_t *fn;
> void *data;
> };
>
> void do_recursive_stop(void *sm_arg_data)
> {
> struct sm_arg *args = sm_arg_data;
>
> /* We're stopped - flag the fact to prevent recursion */
> cpumask_set_cpu(smp_processor_id(), &sm_mask);
>
> args->fn(args->data);
>
> /* Re-enable recursion */
> cpumask_clear_cpu(smp_processor_id(), &sm_mask);
> }
>
> void recursive_stop_machine(cpu_stop_fn_t fn, void *data)
> {
> if (cpumask_test_cpu(smp_processor_id(), &sm_mask)) {
> /* We were already stopped, so can just call directly */
> fn(data);
> }
> else {
> /* Our CPU is not currently stopped */
> struct sm_args *args = {fn, data};
> stop_machine(do_recursive_stop, args, NULL);
> }
> }
... I think a single bool is sufficient in place of the cpumask, since it is
set and cleared
within stop_machine - I started out trying to set/clear outside.
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[Intel-gfx] ✓ Fi.CI.BAT: success for lib/rendercopy: Refactoring rendercopy libraries
== Series Details == Series: lib/rendercopy: Refactoring rendercopy libraries URL : https://patchwork.freedesktop.org/series/34972/ State : success == Summary == IGT patchset tested on top of latest successful build 1db12466cb5ad8483cd469753d2e312a62d717b7 meson: build a full dependency for lib_igt_perf with latest DRM-Tip kernel build CI_DRM_3466 66be57731a40 drm-tip: 2017y-12m-06d-16h-12m-57s UTC integration manifest No testlist changes. Test gem_mmap_gtt: Subgroup basic-small-bo-tiledx: pass -> FAIL (fi-gdg-551) fdo#102575 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: pass -> INCOMPLETE (fi-snb-2520m) fdo#103713 fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:440s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:386s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:519s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:283s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:510s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:511s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:496s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:478s fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45 fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:273s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:543s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:363s fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:261s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:482s fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:443s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:530s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:480s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:537s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:594s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:457s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:543s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:565s fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:526s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:504s fi-snb-2520m total:245 pass:211 dwarn:0 dfail:0 fail:0 skip:33 fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:416s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:611s fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:632s fi-glk-dsi total:288 pass:180 dwarn:1 dfail:4 fail:0 skip:103 time:366s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_602/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH igt 2/2] igt/debugfs_tests: Record which file is being opened in kmsg
Quoting Tvrtko Ursulin (2017-12-06 17:04:40)
>
> On 06/12/2017 17:02, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2017-12-06 16:51:24)
> >>
> >> On 06/12/2017 16:38, Chris Wilson wrote:
> >>> When tracking down the cause of a particular kernel warning, knowing
> >>> which file it is associated with can be a big clue. So write the
> >>> filename into the kernel message log prior to opening it.
> >>>
> >>> Signed-off-by: Chris Wilson
> >>> ---
> >>>tests/debugfs_test.c | 3 ++-
> >>>1 file changed, 2 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/tests/debugfs_test.c b/tests/debugfs_test.c
> >>> index 268d6e78f..2e87e4420 100644
> >>> --- a/tests/debugfs_test.c
> >>> +++ b/tests/debugfs_test.c
> >>> @@ -61,8 +61,9 @@ static void read_and_discard_sysfs_entries(int path_fd,
> >>> int indent)
> >>>int sub_fd;
> >>>ssize_t ret;
> >>>
> >>> - igt_set_timeout(5, "reading sysfs entry");
> >>> + igt_kmsg(KMSG_DEBUG "Reading file \"%s\"\n",
> >>> dirent->d_name);
> >>>igt_debug("%sReading file \"%s\"\n", tabs,
> >>> dirent->d_name);
> >>> + igt_set_timeout(5, "reading sysfs entry");
> >>>
> >>>sub_fd = openat(path_fd, dirent->d_name, O_RDONLY);
> >>>if (sub_fd == -1) {
> >>>
> >>
> >> If I may suggest an alternative - timestamp igt messages and write a log
> >> interleaver to be used with kernel log and igt log as inputs?
> >
> > How do you get igt_log over netconsole?
>
> Hm, ok. But should we then just send igt logs to two places? Stdout/err
> and kmsg? Could be an environment option or something if required.
There are quite a few igt logs that would be nice in the kernel log,
pretty much anything info+. Maybe debug+ if we push some of the noise
out of debug and down into even lower-priority-debug.
-Chris
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Re: [Intel-gfx] [PATCH igt 2/2] igt/debugfs_tests: Record which file is being opened in kmsg
On 06/12/2017 17:02, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2017-12-06 16:51:24)
On 06/12/2017 16:38, Chris Wilson wrote:
When tracking down the cause of a particular kernel warning, knowing
which file it is associated with can be a big clue. So write the
filename into the kernel message log prior to opening it.
Signed-off-by: Chris Wilson
---
tests/debugfs_test.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/debugfs_test.c b/tests/debugfs_test.c
index 268d6e78f..2e87e4420 100644
--- a/tests/debugfs_test.c
+++ b/tests/debugfs_test.c
@@ -61,8 +61,9 @@ static void read_and_discard_sysfs_entries(int path_fd, int
indent)
int sub_fd;
ssize_t ret;
- igt_set_timeout(5, "reading sysfs entry");
+ igt_kmsg(KMSG_DEBUG "Reading file \"%s\"\n",
dirent->d_name);
igt_debug("%sReading file \"%s\"\n", tabs,
dirent->d_name);
+ igt_set_timeout(5, "reading sysfs entry");
sub_fd = openat(path_fd, dirent->d_name, O_RDONLY);
if (sub_fd == -1) {
If I may suggest an alternative - timestamp igt messages and write a log
interleaver to be used with kernel log and igt log as inputs?
How do you get igt_log over netconsole?
Hm, ok. But should we then just send igt logs to two places? Stdout/err
and kmsg? Could be an environment option or something if required.
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH igt 2/2] igt/debugfs_tests: Record which file is being opened in kmsg
Quoting Tvrtko Ursulin (2017-12-06 16:51:24)
>
> On 06/12/2017 16:38, Chris Wilson wrote:
> > When tracking down the cause of a particular kernel warning, knowing
> > which file it is associated with can be a big clue. So write the
> > filename into the kernel message log prior to opening it.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > tests/debugfs_test.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/tests/debugfs_test.c b/tests/debugfs_test.c
> > index 268d6e78f..2e87e4420 100644
> > --- a/tests/debugfs_test.c
> > +++ b/tests/debugfs_test.c
> > @@ -61,8 +61,9 @@ static void read_and_discard_sysfs_entries(int path_fd,
> > int indent)
> > int sub_fd;
> > ssize_t ret;
> >
> > - igt_set_timeout(5, "reading sysfs entry");
> > + igt_kmsg(KMSG_DEBUG "Reading file \"%s\"\n",
> > dirent->d_name);
> > igt_debug("%sReading file \"%s\"\n", tabs,
> > dirent->d_name);
> > + igt_set_timeout(5, "reading sysfs entry");
> >
> > sub_fd = openat(path_fd, dirent->d_name, O_RDONLY);
> > if (sub_fd == -1) {
> >
>
> If I may suggest an alternative - timestamp igt messages and write a log
> interleaver to be used with kernel log and igt log as inputs?
How do you get igt_log over netconsole?
-Chris
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Re: [Intel-gfx] [PATCH v2] drm/i915: Prevent machine hang from Broxton's vtd w/a and error capture
> -Original Message-
> From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> Sent: Wednesday, December 6, 2017 7:38 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Chris Wilson ; Bloomfield, Jon
> ; Harrison, John C ;
> Ursulin, Tvrtko ; Joonas Lahtinen
> ; Daniel Vetter
> Subject: [PATCH v2] drm/i915: Prevent machine hang from Broxton's vtd w/a
> and error capture
>
> Since capturing the error state requires fiddling around with the GGTT
> to read arbitrary buffers and is itself run under stop_machine(), it
> deadlocks the machine (effectively a hard hang) when run in conjunction
> with Broxton's VTd workaround to serialize GGTT access.
>
> v2: Store the ERR_PTR in first_error so that the error can be reported
> to the user via sysfs.
>
> Fixes: 0ef34ad6222a ("drm/i915: Serialize GTT/Aperture accesses on BXT")
> Signed-off-by: Chris Wilson
> Cc: Jon Bloomfield
> Cc: John Harrison
> Cc: Tvrtko Ursulin
> Cc: Joonas Lahtinen
> Cc: Daniel Vetter
It's a real shame to lose error capture on BXT. Can we wrap stop_machine to
make it recursive ?
Something like...
static cpumask_t sm_mask;
struct sm_args {
cpu_stop_fn_t *fn;
void *data;
};
void do_recursive_stop(void *sm_arg_data)
{
struct sm_arg *args = sm_arg_data;
/* We're stopped - flag the fact to prevent recursion */
cpumask_set_cpu(smp_processor_id(), &sm_mask);
args->fn(args->data);
/* Re-enable recursion */
cpumask_clear_cpu(smp_processor_id(), &sm_mask);
}
void recursive_stop_machine(cpu_stop_fn_t fn, void *data)
{
if (cpumask_test_cpu(smp_processor_id(), &sm_mask)) {
/* We were already stopped, so can just call directly */
fn(data);
}
else {
/* Our CPU is not currently stopped */
struct sm_args *args = {fn, data};
stop_machine(do_recursive_stop, args, NULL);
}
}
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Re: [Intel-gfx] [PATCH igt 2/2] igt/debugfs_tests: Record which file is being opened in kmsg
On 06/12/2017 16:38, Chris Wilson wrote:
When tracking down the cause of a particular kernel warning, knowing
which file it is associated with can be a big clue. So write the
filename into the kernel message log prior to opening it.
Signed-off-by: Chris Wilson
---
tests/debugfs_test.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/debugfs_test.c b/tests/debugfs_test.c
index 268d6e78f..2e87e4420 100644
--- a/tests/debugfs_test.c
+++ b/tests/debugfs_test.c
@@ -61,8 +61,9 @@ static void read_and_discard_sysfs_entries(int path_fd, int
indent)
int sub_fd;
ssize_t ret;
- igt_set_timeout(5, "reading sysfs entry");
+ igt_kmsg(KMSG_DEBUG "Reading file \"%s\"\n",
dirent->d_name);
igt_debug("%sReading file \"%s\"\n", tabs,
dirent->d_name);
+ igt_set_timeout(5, "reading sysfs entry");
sub_fd = openat(path_fd, dirent->d_name, O_RDONLY);
if (sub_fd == -1) {
If I may suggest an alternative - timestamp igt messages and write a log
interleaver to be used with kernel log and igt log as inputs?
That would avoid having to sprinkle igt_kmsg over igt code base as more
interesting scenarios are discovered.
Regards,
Tvrtko
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[Intel-gfx] [PATCH igt 2/2] igt/debugfs_tests: Record which file is being opened in kmsg
When tracking down the cause of a particular kernel warning, knowing
which file it is associated with can be a big clue. So write the
filename into the kernel message log prior to opening it.
Signed-off-by: Chris Wilson
---
tests/debugfs_test.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/debugfs_test.c b/tests/debugfs_test.c
index 268d6e78f..2e87e4420 100644
--- a/tests/debugfs_test.c
+++ b/tests/debugfs_test.c
@@ -61,8 +61,9 @@ static void read_and_discard_sysfs_entries(int path_fd, int
indent)
int sub_fd;
ssize_t ret;
- igt_set_timeout(5, "reading sysfs entry");
+ igt_kmsg(KMSG_DEBUG "Reading file \"%s\"\n",
dirent->d_name);
igt_debug("%sReading file \"%s\"\n", tabs,
dirent->d_name);
+ igt_set_timeout(5, "reading sysfs entry");
sub_fd = openat(path_fd, dirent->d_name, O_RDONLY);
if (sub_fd == -1) {
--
2.15.1
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[Intel-gfx] [PATCH igt 1/2] lib: Export kmsg()
Export the kmsg() function for use by tests to write into the kernel
message log, useful for tests to inline their progress with kernel error
messages.
Signed-off-by: Chris Wilson
---
lib/igt_core.c | 20 ++--
lib/igt_core.h | 17 +
2 files changed, 23 insertions(+), 14 deletions(-)
diff --git a/lib/igt_core.c b/lib/igt_core.c
index 777687b5f..cec5f066b 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -385,16 +385,7 @@ void igt_log_buffer_inspect(igt_buffer_log_handler_t
check, void *data)
pthread_mutex_unlock(&log_buffer_mutex);
}
-__attribute__((format(printf, 1, 2)))
-static void kmsg(const char *format, ...)
-#define KERN_EMER "<0>"
-#define KERN_ALERT "<1>"
-#define KERN_CRIT "<2>"
-#define KERN_ERR "<3>"
-#define KERN_WARNING "<4>"
-#define KERN_NOTICE"<5>"
-#define KERN_INFO "<6>"
-#define KERN_DEBUG "<7>"
+void igt_kmsg(const char *format, ...)
{
va_list ap;
FILE *file;
@@ -810,7 +801,7 @@ out:
if (!list_subtests) {
kick_fbcon(false);
- kmsg(KERN_INFO "[IGT] %s: executing\n", command_str);
+ igt_kmsg(KMSG_INFO "%s: executing\n", command_str);
print_version();
sync();
@@ -937,7 +928,8 @@ bool __igt_run_subtest(const char *subtest_name)
return false;
}
- kmsg(KERN_INFO "[IGT] %s: starting subtest %s\n", command_str,
subtest_name);
+ igt_kmsg(KMSG_INFO "%s: starting subtest %s\n",
+command_str, subtest_name);
igt_debug("Starting subtest: %s\n", subtest_name);
_igt_log_buffer_reset();
@@ -1444,8 +1436,8 @@ void igt_exit(void)
}
if (command_str)
- kmsg(KERN_INFO "[IGT] %s: exiting, ret=%d\n",
-command_str, igt_exitcode);
+ igt_kmsg(KMSG_INFO "%s: exiting, ret=%d\n",
+command_str, igt_exitcode);
igt_debug("Exiting with status code %d\n", igt_exitcode);
for (int c = 0; c < num_test_children; c++)
diff --git a/lib/igt_core.h b/lib/igt_core.h
index f8543d658..7af2b4c10 100644
--- a/lib/igt_core.h
+++ b/lib/igt_core.h
@@ -932,4 +932,21 @@ int igt_system_quiet(const char *command);
free(buf); \
} while (0)
+/**
+ * igt_kmsg:
+ * @format: printf-style format string with optional args
+ *
+ * Writes a message into the kernel log file (/dev/kmsg).
+ */
+__attribute__((format(printf, 1, 2)))
+void igt_kmsg(const char *format, ...);
+#define KMSG_EMER "<0>[IGT] "
+#define KMSG_ALERT "<1>[IGT] "
+#define KMSG_CRIT "<2>[IGT] "
+#define KMSG_ERR "<3>[IGT] "
+#define KMSG_WARNING "<4>[IGT] "
+#define KMSG_NOTICE"<5>[IGT] "
+#define KMSG_INFO "<6>[IGT] "
+#define KMSG_DEBUG "<7>[IGT] "
+
#endif /* IGT_CORE_H */
--
2.15.1
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[Intel-gfx] ✗ Fi.CI.BAT: warning for tests/kms_frontbuffer_tracking: Idleness DRRS coverage (rev3)
== Series Details == Series: tests/kms_frontbuffer_tracking: Idleness DRRS coverage (rev3) URL : https://patchwork.freedesktop.org/series/32888/ State : warning == Summary == IGT patchset tested on top of latest successful build 1db12466cb5ad8483cd469753d2e312a62d717b7 meson: build a full dependency for lib_igt_perf with latest DRM-Tip kernel build CI_DRM_3465 01b30547063a drm-tip: 2017y-12m-06d-15h-18m-33s UTC integration manifest Testlist changes: +++ 285 lines --- 0 lines Test debugfs_test: Subgroup read_all_entries: dmesg-warn -> DMESG-FAIL (fi-elk-e7500) fdo#103989 +1 Test kms_frontbuffer_tracking: Subgroup basic: pass -> SKIP (fi-snb-2520m) pass -> SKIP (fi-snb-2600) pass -> SKIP (fi-ivb-3520m) pass -> SKIP (fi-ivb-3770) pass -> SKIP (fi-byt-j1900) pass -> SKIP (fi-byt-n2820) pass -> SKIP (fi-hsw-4770) pass -> SKIP (fi-bdw-5557u) fdo#102473 pass -> SKIP (fi-bsw-n3050) pass -> SKIP (fi-skl-6260u) pass -> SKIP (fi-skl-6600u) pass -> SKIP (fi-skl-6700hq) pass -> SKIP (fi-skl-6700k) fdo#103735 pass -> SKIP (fi-skl-6770hq) pass -> SKIP (fi-bxt-dsi) pass -> SKIP (fi-bxt-j4205) pass -> SKIP (fi-kbl-7560u) pass -> SKIP (fi-kbl-7567u) pass -> SKIP (fi-kbl-r) pass -> SKIP (fi-glk-1) fdo#103167 Test kms_pipe_crc_basic: Subgroup hang-read-crc-pipe-a: notrun -> INCOMPLETE (fi-elk-e7500) Subgroup suspend-read-crc-pipe-b: pass -> INCOMPLETE (fi-snb-2520m) fdo#103713 fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fdo#102473 https://bugs.freedesktop.org/show_bug.cgi?id=102473 fdo#103735 https://bugs.freedesktop.org/show_bug.cgi?id=103735 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fi-bdw-5557u total:288 pass:266 dwarn:0 dfail:0 fail:0 skip:22 time:439s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:392s fi-bsw-n3050 total:288 pass:241 dwarn:0 dfail:0 fail:0 skip:47 time:519s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:284s fi-bxt-dsi total:288 pass:257 dwarn:0 dfail:0 fail:0 skip:31 time:508s fi-bxt-j4205 total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:510s fi-byt-j1900 total:288 pass:252 dwarn:0 dfail:0 fail:0 skip:36 time:488s fi-byt-n2820 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:477s fi-elk-e7500 total:229 pass:167 dwarn:14 dfail:1 fail:0 skip:46 fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:269s fi-glk-1 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:530s fi-hsw-4770 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:369s fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:260s fi-ivb-3520m total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:479s fi-ivb-3770 total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:455s fi-kbl-7560u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:523s fi-kbl-7567u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:475s fi-kbl-r total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:530s fi-skl-6260u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:458s fi-skl-6600u total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:539s fi-skl-6700hqtotal:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:554s fi-skl-6700k total:288 pass:263 dwarn:0 dfail:0 fail:0 skip:25 time:513s fi-skl-6770hqtotal:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:493s fi-snb-2520m total:245 pass:210 dwarn:0 dfail:0 fail:0 skip:34 fi-snb-2600 total:288 pass:247 dwarn:0 dfail:0 fail:0 skip:41 time:424s Blacklisted hosts: fi-cfl-s2total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:611s fi-cnl-y total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:615s fi-glk-dsi total:288 pass:257 dwarn:0 dfail:0 fail:0 skip:31 time:490s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_601/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freede
Re: [Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [v4,1/7] drm/i915/huc: Move firmware selection to init_early
Quoting Patchwork (2017-12-06 16:09:04) > == Series Details == > > Series: series starting with [v4,1/7] drm/i915/huc: Move firmware selection > to init_early > URL : https://patchwork.freedesktop.org/series/34968/ > State : warning > > == Summary == > > Test kms_frontbuffer_tracking: > Subgroup fbc-1p-offscren-pri-shrfb-draw-render: > fail -> PASS (shard-snb) fdo#101623 > Test perf: > Subgroup oa-exponents: > fail -> PASS (shard-hsw) fdo#102254 > Subgroup polling: > pass -> FAIL (shard-hsw) fdo#102252 > Test pm_rpm: > Subgroup system-suspend-modeset: > pass -> SKIP (shard-hsw) > Test kms_plane: > Subgroup plane-position-covered-pipe-c-planes: > skip -> PASS (shard-hsw) > Test kms_flip: > Subgroup vblank-vs-suspend-interruptible: > incomplete -> PASS (shard-hsw) fdo#100368 > Test gem_eio: > Subgroup in-flight: > pass -> DMESG-WARN (shard-snb) And applied, thanks for the patches and review. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Prevent machine hang from Broxton's vtd w/a and error capture (rev2)
== Series Details == Series: drm/i915: Prevent machine hang from Broxton's vtd w/a and error capture (rev2) URL : https://patchwork.freedesktop.org/series/34969/ State : success == Summary == Series 34969v2 drm/i915: Prevent machine hang from Broxton's vtd w/a and error capture https://patchwork.freedesktop.org/api/1.0/series/34969/revisions/2/mbox/ Test debugfs_test: Subgroup read_all_entries: dmesg-warn -> DMESG-FAIL (fi-elk-e7500) fdo#103989 Test gem_mmap_gtt: Subgroup basic-small-bo-tiledx: fail -> PASS (fi-gdg-551) fdo#102575 fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989 fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:438s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:383s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:513s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:281s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:501s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:509s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:489s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:472s fi-elk-e7500 total:224 pass:163 dwarn:14 dfail:1 fail:0 skip:45 fi-gdg-551 total:288 pass:179 dwarn:1 dfail:0 fail:0 skip:108 time:272s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:538s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:383s fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:261s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:480s fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:451s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:531s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:476s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:529s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:448s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:544s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:567s fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:517s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:499s fi-snb-2520m total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:550s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:419s Blacklisted hosts: fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:631s fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:619s fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:491s 01b30547063a8ba25114041e6caf41fc98ea7ddb drm-tip: 2017y-12m-06d-15h-18m-33s UTC integration manifest fce7cec98532 drm/i915: Prevent machine hang from Broxton's vtd w/a and error capture == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7429/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
