Re: [Intel-gfx] [PATCH 00/10] Enabling VDSC in i915 driver for GLK
On 2/24/2018 4:23 AM, Manasi Navare wrote: Thanks for the patches. I am working on the DSC support on i915 for eDP/DP as well. Looking at the patches below, this is specific to VDSC enabling for eDP panels and not for the external DP. So please mention that specifically in the cover letter as well. Since most of the VDSC functionality will be same across EDP and DP, i mentioned DP in generic terms. But no worries, i will mention EDP explicitly in the next patch set while fixing the review comments. On Fri, Feb 23, 2018 at 09:25:43PM +0530, Gaurav K Singh wrote: Display manufacturers are turning to higher-resolution displays to differentiate their products. The increased pixel counts have required increased bandwidth over the links that drive these displays. However, advances in physical layer technology have not kept up with the increases in pixel counts. These factors have created a need for compression on display links. The Video Electronics Standards Association(VESA),in liaison with the MIPI Alliance, has developed an industry standard Display Stream Compression(DSC) for interoperable, visually lossless compression over display links. These patches enable VDSC in i915 gfx driver for Gen9,Gen10 platforms Please specify that this enables VDSC for eDp in i915 gfx driver. Sure, will take care. and provide basic code for future platforms. Testing: Did testing on GLK RVP. By default GLK RVP has non-DSC EDP panel, there was no regression with these patches. BA Chrome Team (OTC) do not have EDP panel which supports DSC. Trying to arrrage DSC EDP panel from other teams in BA, hopeful to get it in few weeks. I do have a DSC eDP panel here in Oregon and can volunteer for testing your patches with that on GLK RVP. Manasi I am hopeful to get the panel sometime late next week. If i am not able to get it, I would surely take your help to test my patches. Dropping the patches to get the review started. Gaurav K Singh (10): drm: i915: Defining Compression Capabilities drm: i915: Get DSC capability from DP sink drm: i915: Enable/Disable DSC in DP sink drm: i915: Compute RC & DSC parameters drm: i915: Define Picture Parameter Set drm/i915: Populate PPS Secondary Data Pkt for Sink drm: i915: Define VDSC regs and DSC params drm: i915: Enable VDSC in Source drm: i915: Disable VDSC from Source drm/i915: Encoder enable/disable seq wrt DSC drivers/gpu/drm/i915/Makefile|1 + drivers/gpu/drm/i915/i915_drv.h | 589 drivers/gpu/drm/i915/i915_reg.h | 451 drivers/gpu/drm/i915/intel_ddi.c |4 + drivers/gpu/drm/i915/intel_display.c | 20 + drivers/gpu/drm/i915/intel_dp.c | 182 + drivers/gpu/drm/i915/intel_drv.h | 64 ++ drivers/gpu/drm/i915/intel_vdsc.c| 1243 ++ include/drm/drm_dp_helper.h |3 + 9 files changed, 2557 insertions(+) create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: add schedule out notification of preempted but completed request
== Series Details == Series: drm/i915: add schedule out notification of preempted but completed request URL : https://patchwork.freedesktop.org/series/38903/ State : success == Summary == Test kms_sysfs_edid_timing: pass -> WARN (shard-apl) fdo#100047 Test kms_cursor_crc: Subgroup cursor-256x256-suspend: pass -> INCOMPLETE (shard-hsw) fdo#103375 Subgroup cursor-64x64-suspend: pass -> INCOMPLETE (shard-hsw) fdo#103540 Test kms_plane: Subgroup plane-position-hole-dpms-pipe-b-planes: fail -> PASS (shard-apl) Test kms_chv_cursor_fail: Subgroup pipe-a-64x64-top-edge: fail -> PASS (shard-apl) Test drv_suspend: Subgroup fence-restore-tiled2untiled: skip -> PASS (shard-hsw) Test kms_flip: Subgroup plain-flip-ts-check-interruptible: pass -> FAIL (shard-hsw) fdo#100368 fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047 fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 shard-apltotal:3563 pass:1870 dwarn:1 dfail:0 fail:14 skip:1677 time:12597s shard-hswtotal:3292 pass:1673 dwarn:1 dfail:0 fail:3 skip:1612 time:10822s shard-snbtotal:3465 pass:1358 dwarn:1 dfail:0 fail:2 skip:2104 time:6636s Blacklisted hosts: shard-kbltotal:3386 pass:1919 dwarn:1 dfail:0 fail:14 skip:1451 time:9302s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8153/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: add schedule out notification of preempted but completed request
== Series Details == Series: drm/i915: add schedule out notification of preempted but completed request URL : https://patchwork.freedesktop.org/series/38903/ State : success == Summary == Series 38903v1 drm/i915: add schedule out notification of preempted but completed request https://patchwork.freedesktop.org/api/1.0/series/38903/revisions/1/mbox/ Test kms_chamelium: Subgroup dp-edid-read: fail -> PASS (fi-kbl-7500u) fdo#102505 Test kms_force_connector_basic: Subgroup force-connector-state: skip -> PASS (fi-snb-2520m) Subgroup force-edid: skip -> PASS (fi-snb-2520m) Subgroup force-load-detect: skip -> PASS (fi-snb-2520m) Subgroup prune-stale-modes: skip -> PASS (fi-snb-2520m) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-c: incomplete -> PASS (fi-bxt-dsi) fdo#103927 fdo#102505 https://bugs.freedesktop.org/show_bug.cgi?id=102505 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:417s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:432s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:373s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:488s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:285s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:481s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:487s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:466s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:459s fi-cfl-8700k total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:394s fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:563s fi-cnl-y3total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:578s fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:416s fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:289s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:513s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:386s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:410s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:448s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:410s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:449s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:493s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:451s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:496s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:585s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:431s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:502s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:520s fi-skl-6700k2total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:485s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:472s fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:405s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:435s fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:520s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:393s 316ba650abe6c1e8ac2f812ff21eee5771546ba1 drm-tip: 2018y-02m-23d-16h-41m-52s UTC integration manifest d9aa326c5adb drm/i915: add schedule out notification of preempted but completed request == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8153/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/5] drm/i915/frontbuffer: Remove early frontbuffer flush in prepare_plane_fb()
On Mon, 2018-02-19 at 10:07 +0100, Maarten Lankhorst wrote: > Op 16-02-18 om 20:27 schreef Pandiyan, Dhinakaran: > > On Fri, 2018-02-16 at 08:55 +, Chris Wilson wrote: > >> Quoting Dhinakaran Pandiyan (2018-02-16 04:33:21) > >>> Preparing a framebuffer should not require a flush. _post_plane_update() > >>> takes care of flushing when a flip is scheduled, this should be > >>> sufficient for PSR and FBC. > >> Makes sense. > >> > > I also think this might speed up the flips a bit by avoiding flushes. > > > >>> Cc: Paulo Zanoni > >>> Cc: Ville Syrjälä > >>> Cc: Chris Wilson > >>> Signed-off-by: Dhinakaran Pandiyan > >> Also > >> Cc: Maarten Lankhorst > >> to validate the flow through atomic. > >> -Chris > >> > Page flips used to do intel_frontbuffer_flip_prepare here, followed by > intel_frontbuffer_flip_complete. I think it would make sense to change the > patch to do that? > I have no context why it was removed, I'll have to understand that change and get back to you. > > Then again, seems like frontbuffer tracking should be done per crtc.. > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/1] drm/i915/skl+: Add and enable DP AUX CH mutex
On Fri, 2018-02-23 at 17:51 -0800, José Roberto de Souza wrote:
> When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
> self, so lets use the mutex register that is available in gen9+ to
> avoid concurrent access by hardware and driver.
> Older gen handling will be done separated.
>
> Reference:
> https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol12-display.pdf
> Page 198 - AUX programming sequence
>
> Cc: Rodrigo Vivi
> Cc: Jani Nikula
> Cc: Dhinakaran Pandiyan
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_reg.h | 9 ++
> drivers/gpu/drm/i915/intel_dp.c | 67
>
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 3 files changed, 77 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index eea5b2c537d4..f36e839b4b4f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5385,6 +5385,15 @@ enum {
> #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
> #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
>
> +#define _DPA_AUX_CH_MUTEX(dev_priv->info.display_mmio_offset + 0x6402C)
> +#define _DPB_AUX_CH_MUTEX(dev_priv->info.display_mmio_offset + 0x6412C)
> +#define _DPC_AUX_CH_MUTEX(dev_priv->info.display_mmio_offset + 0x6422C)
> +#define _DPD_AUX_CH_MUTEX(dev_priv->info.display_mmio_offset + 0x6432C)
> +#define _DPF_AUX_CH_MUTEX(dev_priv->info.display_mmio_offset + 0x6452C)
> +#define DP_AUX_CH_MUTEX(port)_MMIO_PORT(port, _DPA_AUX_CH_MUTEX,
> _DPB_AUX_CH_MUTEX)
^aux_ch similar to ctl and data.
> +#define DP_AUX_CH_MUTEX_ENABLE (1 << 31)
> +#define DP_AUX_CH_MUTEX_STATUS (1 << 30)
> +
> /*
> * Computing GMCH M and N values for the Display Port link
> *
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 2c3eb90b9499..7be2fec51651 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1081,6 +1081,45 @@ static uint32_t intel_dp_get_aux_send_ctl(struct
> intel_dp *intel_dp,
> aux_clock_divider);
> }
>
> +static bool intel_dp_aux_ch_trylock(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> + struct drm_i915_private *dev_priv =
> + to_i915(intel_dig_port->base.base.dev);
> + i915_reg_t ch_mutex;
> +
> + if (!intel_dp->aux_ch_mutex_reg)
> + return true;
> +
> + ch_mutex = intel_dp->aux_ch_mutex_reg(intel_dp);
> + I915_WRITE(ch_mutex, DP_AUX_CH_MUTEX_ENABLE);
> > >
> > > You might be touching bits. We don't know if HW is using the
> > > reserved
> > > bits or not.
> > > So RMW |= bit 31 here is a good idea.
> >
> > As a read in this register request the mutex lock is better avoid
> > any
> > read that is not meant to request it.
>
> ok... I accept the fact that read that is locking
> so you are right here.
>
I do not agree with the interpretation here, reading the register
*after* the mutex is enabled == request for locking. You can read the
register before enabling, and you have to read so that you don't
overwrite any other bit.
Ref: "Sticky bit set to 1 after a read to this register when Mutex is
enabled."
> +
> + /* Spec says that mutex is acquired when status bit is read as unset,
> + * here waiting for 2msec or 4 tries before give up.
2 ms.^ this is not true
> + */
> + if (intel_wait_for_register(dev_priv, ch_mutex, DP_AUX_CH_MUTEX_STATUS,
> + 0, 2)) {
> + DRM_WARN("dp_aux_ch port locked for too long");
DRM_DEBUG_KMS("aux channel %c locked for 2 ms, timing out\n");
1. DRM_DEBUG_KMS is the convention in this file and most parts of the
driver for things like this.
2. I prefer to add details like port/channel/pipe/connector when
printing debug messages if it doesn't cost any extra space.
> + return false;
> + }
> +
> + return true;
> +}
> +
> +static void intel_dp_aux_ch_unlock(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> + struct drm_i915_private *dev_priv =
> + to_i915(intel_dig_port->base.base.dev);
> +
> + if (!intel_dp->aux_ch_mutex_reg)
> + return;
> +
> + /* setting the status bit releases the mutex + keep mutex enabled */
> + I915_WRITE(intel_dp->aux_ch_mutex_reg(intel_dp),
> +DP_AUX_CH_MUTEX_ENABLE | DP_AUX_CH_MUTEX_STATUS);
If you are leaving the mutex enabled, you don't have to enable it for
the second transaction onwards. In that case, why not move the mutex
enabling step to intel_dp_aux_init() after checking for PSR support or
enable the mutex just before intel_psr_ena
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Add and enable DP AUX CH mutex (rev2)
== Series Details == Series: drm/i915: Add and enable DP AUX CH mutex (rev2) URL : https://patchwork.freedesktop.org/series/38655/ State : success == Summary == Test kms_flip: Subgroup modeset-vs-vblank-race: pass -> FAIL (shard-hsw) fdo#103060 Subgroup plain-flip-ts-check: pass -> FAIL (shard-hsw) fdo#100368 Test kms_chv_cursor_fail: Subgroup pipe-a-64x64-top-edge: fail -> PASS (shard-apl) Test drv_suspend: Subgroup fence-restore-tiled2untiled: skip -> PASS (shard-hsw) Test gem_eio: Subgroup in-flight: pass -> INCOMPLETE (shard-apl) fdo#104945 Test kms_plane: Subgroup plane-position-hole-dpms-pipe-b-planes: fail -> PASS (shard-apl) Test kms_sysfs_edid_timing: pass -> WARN (shard-apl) fdo#100047 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#104945 https://bugs.freedesktop.org/show_bug.cgi?id=104945 fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047 shard-apltotal:3457 pass:1816 dwarn:1 dfail:0 fail:12 skip:1626 time:11859s shard-hswtotal:3465 pass:1766 dwarn:1 dfail:0 fail:4 skip:1693 time:11804s shard-snbtotal:3465 pass:1358 dwarn:1 dfail:0 fail:2 skip:2104 time:6661s Blacklisted hosts: shard-kbltotal:3386 pass:1908 dwarn:10 dfail:0 fail:14 skip:1452 time:9221s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8151/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: add schedule out notification of preempted but completed request
There is one corner case missing schedule out notification of the preempted
request. The preempted request is just completed when preemption happen,
then it will be canceled and won't be resubmitted later, GVT-g will lost
the schedule out notification.
Here add schedule out notification if found the preempted request has been
completed.
v2:
- refine description, add completed check and notification in
execlists_cancel_port_requests. (Chris)
Cc: Chris Wilson
Signed-off-by: Weinan Li
Signed-off-by: Zhenyu Wang
---
drivers/gpu/drm/i915/intel_lrc.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e781c91..24a6e68 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -657,10 +657,16 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
while (num_ports-- && port_isset(port)) {
struct i915_request *rq = port_request(port);
+ unsigned int notify;
GEM_BUG_ON(!execlists->active);
intel_engine_context_out(rq->engine);
- execlists_context_status_change(rq,
INTEL_CONTEXT_SCHEDULE_PREEMPTED);
+
+ notify = INTEL_CONTEXT_SCHEDULE_PREEMPTED;
+ if (i915_request_completed(rq))
+ notify = INTEL_CONTEXT_SCHEDULE_OUT;
+ execlists_context_status_change(rq, notify);
+
i915_request_put(rq);
memset(port, 0, sizeof(*port));
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/6] drm/i915/skl+: Add and enable DP AUX CH mutex
== Series Details == Series: series starting with [1/6] drm/i915/skl+: Add and enable DP AUX CH mutex URL : https://patchwork.freedesktop.org/series/38902/ State : failure == Summary == Series 38902v1 series starting with [1/6] drm/i915/skl+: Add and enable DP AUX CH mutex https://patchwork.freedesktop.org/api/1.0/series/38902/revisions/1/mbox/ Test gem_exec_suspend: Subgroup basic-s3: pass -> FAIL (fi-skl-guc) Test kms_busy: Subgroup basic-flip-a: pass -> DMESG-WARN (fi-skl-6700k2) Test kms_force_connector_basic: Subgroup force-connector-state: skip -> PASS (fi-snb-2520m) Subgroup force-edid: skip -> PASS (fi-snb-2520m) Subgroup force-load-detect: skip -> PASS (fi-snb-2520m) Subgroup prune-stale-modes: skip -> PASS (fi-snb-2520m) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-c: incomplete -> PASS (fi-bxt-dsi) fdo#103927 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:406s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:423s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:373s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:440s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:283s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:476s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:485s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:424s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:417s fi-cfl-8700k total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:393s fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:565s fi-cnl-y3total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:576s fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:419s fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:283s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:508s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:384s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:407s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:452s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:412s fi-kbl-7500u total:288 pass:262 dwarn:1 dfail:0 fail:1 skip:24 time:439s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:491s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:444s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:494s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:591s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:428s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:502s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:517s fi-skl-6700k2total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:478s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:458s fi-skl-guc total:288 pass:259 dwarn:0 dfail:0 fail:1 skip:28 time:404s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:430s fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:523s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:392s 316ba650abe6c1e8ac2f812ff21eee5771546ba1 drm-tip: 2018y-02m-23d-16h-41m-52s UTC integration manifest ef1e257d5daa drm/i915/psr/hsw+: Enable CRC check in the static frame on the sink side 5c88fa2403cd drm/i915/psr: Handle PSR RFB storage error 44e795fcba6e drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink 7ff88cb1e65b drm/i915: Exit PSR before do a aux transaction in gen < 9 c796fc99157a drm/i915/psr: Share the common code between PSR exit and disable daa39e989d5f drm/i915/skl+: Add and enable DP AUX CH mutex == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8152/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add and enable DP AUX CH mutex (rev2)
== Series Details == Series: drm/i915: Add and enable DP AUX CH mutex (rev2) URL : https://patchwork.freedesktop.org/series/38655/ State : success == Summary == Series 38655v2 drm/i915: Add and enable DP AUX CH mutex https://patchwork.freedesktop.org/api/1.0/series/38655/revisions/2/mbox/ Test kms_chamelium: Subgroup dp-edid-read: fail -> PASS (fi-kbl-7500u) fdo#102505 Test kms_force_connector_basic: Subgroup force-connector-state: skip -> PASS (fi-snb-2520m) Subgroup force-edid: skip -> PASS (fi-snb-2520m) Subgroup force-load-detect: skip -> PASS (fi-snb-2520m) Subgroup prune-stale-modes: skip -> PASS (fi-snb-2520m) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-c: incomplete -> PASS (fi-bxt-dsi) fdo#103927 fdo#102505 https://bugs.freedesktop.org/show_bug.cgi?id=102505 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:414s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:438s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:375s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:490s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:285s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:486s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:481s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:469s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:466s fi-cfl-8700k total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:391s fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:568s fi-cnl-y3total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:573s fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:416s fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:286s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:505s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:386s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:410s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:450s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:412s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:453s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:494s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:447s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:491s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:595s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:425s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:502s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:522s fi-skl-6700k2total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:491s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:468s fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:407s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:433s fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:509s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:391s 316ba650abe6c1e8ac2f812ff21eee5771546ba1 drm-tip: 2018y-02m-23d-16h-41m-52s UTC integration manifest 41b1cc01d6ec drm/i915/skl+: Add and enable DP AUX CH mutex == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8151/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/6] drm/i915/psr: Share the common code between PSR exit and disable
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 199 +++
2 files changed, 96 insertions(+), 104 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 82a106b1bdbc..44b551f1576d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -780,6 +780,7 @@ struct i915_psr {
void (*enable_sink)(struct intel_dp *);
void (*activate)(struct intel_dp *);
void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *);
+ void (*exit)(struct intel_dp *intel_dp, bool wait_exit);
};
enum intel_pch {
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2ef374f936b9..e8c32c3afb0e 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -551,25 +551,12 @@ static void vlv_psr_disable(struct intel_dp *intel_dp,
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
uint32_t val;
- if (dev_priv->psr.active) {
- /* Put VLV PSR back to PSR_state 0 (disabled). */
- if (intel_wait_for_register(dev_priv,
- VLV_PSRSTAT(crtc->pipe),
- VLV_EDP_PSR_IN_TRANS,
- 0,
- 1))
- WARN(1, "PSR transition took longer than expected\n");
+ dev_priv->psr.exit(intel_dp, true);
- val = I915_READ(VLV_PSRCTL(crtc->pipe));
- val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
- val &= ~VLV_EDP_PSR_ENABLE;
- val &= ~VLV_EDP_PSR_MODE_MASK;
- I915_WRITE(VLV_PSRCTL(crtc->pipe), val);
-
- dev_priv->psr.active = false;
- } else {
- WARN_ON(vlv_is_psr_active_on_pipe(dev, crtc->pipe));
- }
+ val = I915_READ(VLV_PSRCTL(crtc->pipe));
+ val &= ~VLV_EDP_PSR_ENABLE;
+ val &= ~VLV_EDP_PSR_MODE_MASK;
+ I915_WRITE(VLV_PSRCTL(crtc->pipe), val);
}
static void hsw_psr_disable(struct intel_dp *intel_dp,
@@ -579,44 +566,100 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- if (dev_priv->psr.active) {
- i915_reg_t psr_status;
- u32 psr_status_mask;
-
- if (dev_priv->psr.aux_frame_sync)
- drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
- 0);
+ dev_priv->psr.exit(intel_dp, true);
+}
- if (dev_priv->psr.psr2_support) {
- psr_status = EDP_PSR2_STATUS;
- psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
+static void hsw_psr_exit(struct intel_dp *intel_dp, bool wait_exit)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ i915_reg_t psr_status;
+ u32 psr_status_mask;
- I915_WRITE(EDP_PSR2_CTL,
- I915_READ(EDP_PSR2_CTL) &
- ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE));
+ if (!dev_priv->psr.active) {
+ if (dev_priv->psr.psr2_support)
+ WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
+ else
+ WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
+ return;
+ }
- } else {
- psr_status = EDP_PSR_STATUS;
- psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
+ if (dev_priv->psr.aux_frame_sync)
+ drm_dp_dpcd_writeb(&intel_dp->aux,
+ DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF, 0);
- I915_WRITE(EDP_PSR_CTL,
- I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
- }
+ if (dev_priv->psr.psr2_support) {
+ psr_status = EDP_PSR2_STATUS;
+ psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
- /* Wait till PSR is idle */
- if (intel_wait_for_register(dev_priv,
- psr_status, psr_status_mask, 0,
- 2000))
- DRM_ERROR("Timed out waiting for PSR Idle State\n");
+ I915_WRITE(EDP_PSR2_CTL,
+ I915_READ(EDP_PSR2_CTL) &
+ ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE));
- dev_priv->psr.active = false;
} else {
- if (dev_priv->psr.psr2_su
[Intel-gfx] [PATCH 6/6] drm/i915/psr/hsw+: Enable CRC check in the static frame on the sink side
Sink can be configured to calculate the CRC over the static frame and
compare with the CRC calculated and transmited in the VSC SDP by
source, if there is a mismatch sink will do a short pulse in HPD
and set DP_PSR_LINK_CRC_ERROR on DP_PSR_ERROR_STATUS.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 15 +++
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f36e839b4b4f..ca68eef8d90a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4122,6 +4122,7 @@ enum {
#define EDP_PSR_SKIP_AUX_EXIT(1<<12)
#define EDP_PSR_TP1_TP2_SEL (0<<11)
#define EDP_PSR_TP1_TP3_SEL (1<<11)
+#define EDP_PSR_CRC_ENABLE (1<<10)
#define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
#define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
#define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 4e73edf1ea5b..f6af8e8039c9 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -160,6 +160,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
enum port port = dig_port->base.port;
u32 aux_ctl;
int i;
+ uint8_t val;
BUILD_BUG_ON(sizeof(aux_msg) > 20);
@@ -175,12 +176,10 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
drm_dp_dpcd_writeb(&intel_dp->aux,
DP_RECEIVER_ALPM_CONFIG,
DP_ALPM_ENABLE);
+ val = DP_PSR_ENABLE | DP_PSR_CRC_VERIFICATION;
if (dev_priv->psr.link_standby)
- drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
- DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
- else
- drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
- DP_PSR_ENABLE);
+ val |= DP_PSR_MAIN_LINK_ACTIVE;
+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val);
aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port);
@@ -241,7 +240,7 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
* with the 5 or 6 idle patterns.
*/
uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
- uint32_t val = EDP_PSR_ENABLE;
+ uint32_t val = EDP_PSR_ENABLE | EDP_PSR_CRC_ENABLE;
val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
@@ -1015,12 +1014,12 @@ void intel_psr_hpd_short_pulse_handle(struct intel_dp
*intel_dp)
goto dpcd_read_error;
}
- if (val & DP_PSR_RFB_STORAGE_ERROR)
+ if (val & (DP_PSR_RFB_STORAGE_ERROR | DP_PSR_LINK_CRC_ERROR))
dev_priv->psr.exit(intel_dp, false);
/* clear status register */
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);
- /* TODO: handle other PSR/PSR2 errors */
+ /* TODO: handle PSR2 errors */
dpcd_read_error:
intel_psr_active_schedule(psr, PSR_ACTIVE_DELAY_MSEC);
out:
--
2.16.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/6] drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink
Sink device will do a short pulse in HPD line when there is some
PSR/PSR2 error that needs to be handled by source, this is handling
the first and most simples error: DP_PSR_SINK_INTERNAL_ERROR.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_dp.c | 2 ++
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 31 +++
3 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index dacdd98bbb2e..955bf85e9b20 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4549,6 +4549,8 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
intel_dp_check_link_status(intel_dp);
+ intel_psr_hpd_short_pulse_handle(intel_dp);
+
if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
/* Send a Hotplug Uevent to userspace to start modeset */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7adcd5955d1b..a0bd00787a98 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1890,6 +1890,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
* It will also schedule a work to try to active PSR again.
*/
void intel_psr_exit(struct intel_dp *intel_dp, bool wait_exit);
+void intel_psr_hpd_short_pulse_handle(struct intel_dp *intel_dp);
/* intel_runtime_pm.c */
int intel_power_domains_init(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 0b889c85e8da..ab3713c2582b 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -985,3 +985,34 @@ void intel_psr_exit(struct intel_dp *intel_dp, bool
wait_exit)
out:
mutex_unlock(&dev_priv->psr.lock);
}
+
+void intel_psr_hpd_short_pulse_handle(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct i915_psr *psr = &dev_priv->psr;
+ uint8_t val;
+
+ if (!HAS_PSR(dev_priv))
+ return;
+
+ mutex_lock(&psr->lock);
+
+ if (psr->enabled != intel_dp)
+ goto out;
+
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val) != 1) {
+ DRM_DEBUG_KMS("PSR_STATUS read failed\n");
+ goto dpcd_read_error;
+ }
+
+ if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR)
+ psr->exit(intel_dp, false);
+
+ /* TODO: handle other PSR/PSR2 errors */
+dpcd_read_error:
+ intel_psr_active_schedule(psr, PSR_ACTIVE_DELAY_MSEC);
+out:
+ mutex_unlock(&psr->lock);
+}
--
2.16.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/6] drm/i915/psr: Handle PSR RFB storage error
Sink will interrupt source when it have any problem saving or reading
the remote frame buffer.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index ab3713c2582b..4e73edf1ea5b 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -1010,6 +1010,16 @@ void intel_psr_hpd_short_pulse_handle(struct intel_dp
*intel_dp)
if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR)
psr->exit(intel_dp, false);
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ERROR_STATUS, &val) != 1) {
+ DRM_DEBUG_KMS("PSR_ERROR_STATUS read failed\n");
+ goto dpcd_read_error;
+ }
+
+ if (val & DP_PSR_RFB_STORAGE_ERROR)
+ dev_priv->psr.exit(intel_dp, false);
+ /* clear status register */
+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);
+
/* TODO: handle other PSR/PSR2 errors */
dpcd_read_error:
intel_psr_active_schedule(psr, PSR_ACTIVE_DELAY_MSEC);
--
2.16.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/6] drm/i915: Exit PSR before do a aux transaction in gen < 9
As gen < 9 hardware don't have the aux ch mutex, we need to exit PSR
and wait until it is back to inactive state before do any aux ch
transaction.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_dp.c | 8 +++-
drivers/gpu/drm/i915/intel_drv.h | 9 +
drivers/gpu/drm/i915/intel_psr.c | 42 ++--
3 files changed, 52 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7be2fec51651..dacdd98bbb2e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1088,8 +1088,14 @@ static bool intel_dp_aux_ch_trylock(struct intel_dp
*intel_dp)
to_i915(intel_dig_port->base.base.dev);
i915_reg_t ch_mutex;
- if (!intel_dp->aux_ch_mutex_reg)
+ if (!intel_dp->aux_ch_mutex_reg) {
+ /* As gen < 9 hardware don't have the aux ch mutex, we need to
+* exit PSR and wait until it is back to inactive state before
+* do any aux ch transaction
+*/
+ intel_psr_exit(intel_dp, true);
return true;
+ }
ch_mutex = intel_dp->aux_ch_mutex_reg(intel_dp);
I915_WRITE(ch_mutex, DP_AUX_CH_MUTEX_ENABLE);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 267cc6c5a89f..7adcd5955d1b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1881,6 +1881,15 @@ void intel_psr_single_frame_update(struct
drm_i915_private *dev_priv,
unsigned frontbuffer_bits);
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state);
+/**
+ * Exit PSR in the given DisplayPort.
+ * @intel_dp: DisplayPort which PSR should be exit if running
+ * @wait_exit: if true it will wait until PSR have changed to inactive state,
+ * otherwise there is not wait.
+ *
+ * It will also schedule a work to try to active PSR again.
+ */
+void intel_psr_exit(struct intel_dp *intel_dp, bool wait_exit);
/* intel_runtime_pm.c */
int intel_power_domains_init(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index e8c32c3afb0e..0b889c85e8da 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -56,6 +56,8 @@
#include "intel_drv.h"
#include "i915_drv.h"
+#define PSR_ACTIVE_DELAY_MSEC 100
+
static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
{
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -486,6 +488,16 @@ static void hsw_psr_enable_source(struct intel_dp
*intel_dp,
}
}
+static void intel_psr_active_schedule(struct i915_psr *psr,
+ unsigned int msec_delay)
+{
+ if (psr->active || psr->busy_frontbuffer_bits)
+ return;
+
+ if (!work_busy(&psr->work.work))
+ schedule_delayed_work(&psr->work, msecs_to_jiffies(msec_delay));
+}
+
/**
* intel_psr_enable - Enable PSR
* @intel_dp: Intel DP
@@ -534,8 +546,9 @@ void intel_psr_enable(struct intel_dp *intel_dp,
* - On HSW/BDW we get a recoverable frozen screen until
* next exit-activate sequence.
*/
- schedule_delayed_work(&dev_priv->psr.work,
-
msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
+ intel_psr_active_schedule(&dev_priv->psr,
+ intel_dp->panel_power_cycle_delay
+ * 5);
}
unlock:
@@ -886,10 +899,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
if (frontbuffer_bits)
dev_priv->psr.exit(dev_priv->psr.enabled, false);
- if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
- if (!work_busy(&dev_priv->psr.work.work))
- schedule_delayed_work(&dev_priv->psr.work,
- msecs_to_jiffies(100));
+ intel_psr_active_schedule(&dev_priv->psr, PSR_ACTIVE_DELAY_MSEC);
mutex_unlock(&dev_priv->psr.lock);
}
@@ -955,3 +965,23 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
dev_priv->psr.exit = hsw_psr_exit;
}
}
+
+void intel_psr_exit(struct intel_dp *intel_dp, bool wait_exit)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ if (!HAS_PSR(dev_priv))
+ return;
+
+ mutex_lock(&dev_priv->psr.lock);
+
+ if (dev_priv->psr.enabled != intel_dp)
+ goto out;
+
+ dev_priv->psr.exit(intel_dp, wait_exit);
+ intel_psr_active_schedule(&dev_priv->psr, PSR_ACTIV
[Intel-gfx] [PATCH 1/6] drm/i915/skl+: Add and enable DP AUX CH mutex
***
Please do not send review to this patch here, it was sent separated
https://lists.freedesktop.org/archives/intel-gfx/2018-February/156921.html
it is only included here to avoid concurrency access when reading
sink PSR status and errors registers
***
When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
self, so lets use the mutex register that is available in gen9+ to
avoid concurrent access by hardware and driver.
Older gen handling will be done separated.
Reference:
https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol12-display.pdf
Page 198 - AUX programming sequence
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 9 ++
drivers/gpu/drm/i915/intel_dp.c | 67
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 77 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eea5b2c537d4..f36e839b4b4f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5385,6 +5385,15 @@ enum {
#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
+#define _DPA_AUX_CH_MUTEX (dev_priv->info.display_mmio_offset + 0x6402C)
+#define _DPB_AUX_CH_MUTEX (dev_priv->info.display_mmio_offset + 0x6412C)
+#define _DPC_AUX_CH_MUTEX (dev_priv->info.display_mmio_offset + 0x6422C)
+#define _DPD_AUX_CH_MUTEX (dev_priv->info.display_mmio_offset + 0x6432C)
+#define _DPF_AUX_CH_MUTEX (dev_priv->info.display_mmio_offset + 0x6452C)
+#define DP_AUX_CH_MUTEX(port) _MMIO_PORT(port, _DPA_AUX_CH_MUTEX,
_DPB_AUX_CH_MUTEX)
+#define DP_AUX_CH_MUTEX_ENABLE (1 << 31)
+#define DP_AUX_CH_MUTEX_STATUS (1 << 30)
+
/*
* Computing GMCH M and N values for the Display Port link
*
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2c3eb90b9499..7be2fec51651 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1081,6 +1081,45 @@ static uint32_t intel_dp_get_aux_send_ctl(struct
intel_dp *intel_dp,
aux_clock_divider);
}
+static bool intel_dp_aux_ch_trylock(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *dev_priv =
+ to_i915(intel_dig_port->base.base.dev);
+ i915_reg_t ch_mutex;
+
+ if (!intel_dp->aux_ch_mutex_reg)
+ return true;
+
+ ch_mutex = intel_dp->aux_ch_mutex_reg(intel_dp);
+ I915_WRITE(ch_mutex, DP_AUX_CH_MUTEX_ENABLE);
+
+ /* Spec says that mutex is acquired when status bit is read as unset,
+* here waiting for 2msec or 4 tries before give up.
+*/
+ if (intel_wait_for_register(dev_priv, ch_mutex, DP_AUX_CH_MUTEX_STATUS,
+ 0, 2)) {
+ DRM_WARN("dp_aux_ch port locked for too long");
+ return false;
+ }
+
+ return true;
+}
+
+static void intel_dp_aux_ch_unlock(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *dev_priv =
+ to_i915(intel_dig_port->base.base.dev);
+
+ if (!intel_dp->aux_ch_mutex_reg)
+ return;
+
+ /* setting the status bit releases the mutex + keep mutex enabled */
+ I915_WRITE(intel_dp->aux_ch_mutex_reg(intel_dp),
+ DP_AUX_CH_MUTEX_ENABLE | DP_AUX_CH_MUTEX_STATUS);
+}
+
static int
intel_dp_aux_ch(struct intel_dp *intel_dp,
const uint8_t *send, int send_bytes,
@@ -1119,6 +1158,11 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
intel_dp_check_edp(intel_dp);
+ if (!intel_dp_aux_ch_trylock(intel_dp)) {
+ ret = -EBUSY;
+ goto out_locked;
+ }
+
/* Try to wait for any previous AUX channel activity */
for (try = 0; try < 3; try++) {
status = I915_READ_NOTRACE(ch_ctl);
@@ -1248,6 +1292,8 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
ret = recv_bytes;
out:
+ intel_dp_aux_ch_unlock(intel_dp);
+out_locked:
pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
if (vdd)
@@ -1504,6 +1550,24 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp
*intel_dp, int index)
}
}
+static i915_reg_t skl_aux_mutex_reg(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
+ enum aux_ch aux_ch = intel_dp->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ case AUX_CH_B:
+ case AUX_CH_C:
+ case AUX_CH_D:
+ case AUX_CH_F:
+ return DP_AUX_CH_MUTEX(aux_ch);
+ default:
+ MISSING_CASE(aux_ch);
+ return DP_AUX_CH_MUTEX(AUX_CH_A);
+
[Intel-gfx] [PATCH 1/1] drm/i915/skl+: Add and enable DP AUX CH mutex
When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
self, so lets use the mutex register that is available in gen9+ to
avoid concurrent access by hardware and driver.
Older gen handling will be done separated.
Reference:
https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol12-display.pdf
Page 198 - AUX programming sequence
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Dhinakaran Pandiyan
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 9 ++
drivers/gpu/drm/i915/intel_dp.c | 67
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 77 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eea5b2c537d4..f36e839b4b4f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5385,6 +5385,15 @@ enum {
#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
+#define _DPA_AUX_CH_MUTEX (dev_priv->info.display_mmio_offset + 0x6402C)
+#define _DPB_AUX_CH_MUTEX (dev_priv->info.display_mmio_offset + 0x6412C)
+#define _DPC_AUX_CH_MUTEX (dev_priv->info.display_mmio_offset + 0x6422C)
+#define _DPD_AUX_CH_MUTEX (dev_priv->info.display_mmio_offset + 0x6432C)
+#define _DPF_AUX_CH_MUTEX (dev_priv->info.display_mmio_offset + 0x6452C)
+#define DP_AUX_CH_MUTEX(port) _MMIO_PORT(port, _DPA_AUX_CH_MUTEX,
_DPB_AUX_CH_MUTEX)
+#define DP_AUX_CH_MUTEX_ENABLE (1 << 31)
+#define DP_AUX_CH_MUTEX_STATUS (1 << 30)
+
/*
* Computing GMCH M and N values for the Display Port link
*
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2c3eb90b9499..7be2fec51651 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1081,6 +1081,45 @@ static uint32_t intel_dp_get_aux_send_ctl(struct
intel_dp *intel_dp,
aux_clock_divider);
}
+static bool intel_dp_aux_ch_trylock(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *dev_priv =
+ to_i915(intel_dig_port->base.base.dev);
+ i915_reg_t ch_mutex;
+
+ if (!intel_dp->aux_ch_mutex_reg)
+ return true;
+
+ ch_mutex = intel_dp->aux_ch_mutex_reg(intel_dp);
+ I915_WRITE(ch_mutex, DP_AUX_CH_MUTEX_ENABLE);
+
+ /* Spec says that mutex is acquired when status bit is read as unset,
+* here waiting for 2msec or 4 tries before give up.
+*/
+ if (intel_wait_for_register(dev_priv, ch_mutex, DP_AUX_CH_MUTEX_STATUS,
+ 0, 2)) {
+ DRM_WARN("dp_aux_ch port locked for too long");
+ return false;
+ }
+
+ return true;
+}
+
+static void intel_dp_aux_ch_unlock(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *dev_priv =
+ to_i915(intel_dig_port->base.base.dev);
+
+ if (!intel_dp->aux_ch_mutex_reg)
+ return;
+
+ /* setting the status bit releases the mutex + keep mutex enabled */
+ I915_WRITE(intel_dp->aux_ch_mutex_reg(intel_dp),
+ DP_AUX_CH_MUTEX_ENABLE | DP_AUX_CH_MUTEX_STATUS);
+}
+
static int
intel_dp_aux_ch(struct intel_dp *intel_dp,
const uint8_t *send, int send_bytes,
@@ -1119,6 +1158,11 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
intel_dp_check_edp(intel_dp);
+ if (!intel_dp_aux_ch_trylock(intel_dp)) {
+ ret = -EBUSY;
+ goto out_locked;
+ }
+
/* Try to wait for any previous AUX channel activity */
for (try = 0; try < 3; try++) {
status = I915_READ_NOTRACE(ch_ctl);
@@ -1248,6 +1292,8 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
ret = recv_bytes;
out:
+ intel_dp_aux_ch_unlock(intel_dp);
+out_locked:
pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
if (vdd)
@@ -1504,6 +1550,24 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp
*intel_dp, int index)
}
}
+static i915_reg_t skl_aux_mutex_reg(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
+ enum aux_ch aux_ch = intel_dp->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ case AUX_CH_B:
+ case AUX_CH_C:
+ case AUX_CH_D:
+ case AUX_CH_F:
+ return DP_AUX_CH_MUTEX(aux_ch);
+ default:
+ MISSING_CASE(aux_ch);
+ return DP_AUX_CH_MUTEX(AUX_CH_A);
+ }
+}
+
static void
intel_dp_aux_fini(struct intel_dp *intel_dp)
{
@@ -1544,6 +1608,9 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
else
intel_dp->
Re: [Intel-gfx] [PATCH 2/3] drm/i915: Replace magic number with macro defined by drm
On Tue, 2018-02-20 at 18:18 -0800, José Roberto de Souza wrote:
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_psr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 71801a25a2b3..3fc1bdd65b14 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -90,7 +90,7 @@ static void hsw_psr_setup_vsc(struct intel_dp *intel_dp,
>
> memset(&psr_vsc, 0, sizeof(psr_vsc));
> psr_vsc.sdp_header.HB0 = 0;
> - psr_vsc.sdp_header.HB1 = 0x7;
> + psr_vsc.sdp_header.HB1 = DP_SDP_VSC;
>
Do you mind rebasing this without Patch 1?
> if (dev_priv->psr.psr2_support) {
> /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 0/1] drm/i915: Add and enable DP AUX CH mutex
v2 - removed the PSR dependency, now getting lock all the times when available - renamed functions to avoid nested calls - moved register bits right after the DP_AUX_CH_MUTEX() - removed 'drm/i915: keep AUX powered while PSR is enabled' Dhinakaran Pandiyan will sent a better and final version v3 - rebased on top of Ville's AUX series - moved port registers to above DP_AUX_CH_MUTEX() - using intel_wait_for_register() instead of the internal version José Roberto de Souza (1): drm/i915/skl+: Add and enable DP AUX CH mutex drivers/gpu/drm/i915/i915_reg.h | 9 ++ drivers/gpu/drm/i915/intel_dp.c | 67 drivers/gpu/drm/i915/intel_drv.h | 1 + 3 files changed, 77 insertions(+) -- 2.16.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Share PSR and PSR2 VSC setup
On Tue, 2018-02-20 at 18:18 -0800, José Roberto de Souza wrote:
> Just share the common code in PSR and PSR2.
>
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_psr.c | 10 --
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 2ef374f936b9..71801a25a2b3 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -88,11 +88,12 @@ static void hsw_psr_setup_vsc(struct intel_dp *intel_dp,
> struct drm_i915_private *dev_priv =
> to_i915(intel_dig_port->base.base.dev);
> struct edp_vsc_psr psr_vsc;
>
> + memset(&psr_vsc, 0, sizeof(psr_vsc));
> + psr_vsc.sdp_header.HB0 = 0;
> + psr_vsc.sdp_header.HB1 = 0x7;
> +
>
I don't think this is very useful, the original version is easier to
read IMO.
> if (dev_priv->psr.psr2_support) {
> /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
> - memset(&psr_vsc, 0, sizeof(psr_vsc));
> - psr_vsc.sdp_header.HB0 = 0;
> - psr_vsc.sdp_header.HB1 = 0x7;
> if (dev_priv->psr.colorimetry_support &&
> dev_priv->psr.y_cord_support) {
> psr_vsc.sdp_header.HB2 = 0x5;
> @@ -106,9 +107,6 @@ static void hsw_psr_setup_vsc(struct intel_dp *intel_dp,
> }
> } else {
> /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
> - memset(&psr_vsc, 0, sizeof(psr_vsc));
> - psr_vsc.sdp_header.HB0 = 0;
> - psr_vsc.sdp_header.HB1 = 0x7;
> psr_vsc.sdp_header.HB2 = 0x2;
> psr_vsc.sdp_header.HB3 = 0x8;
> }
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Remove unused variable in hsw_write_infoframe()
On Tue, 2018-02-20 at 18:18 -0800, José Roberto de Souza wrote: > Signed-off-by: José Roberto de Souza > --- > drivers/gpu/drm/i915/intel_hdmi.c | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c > b/drivers/gpu/drm/i915/intel_hdmi.c > index f5d7bfb43006..fe4bef081dae 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -381,14 +381,11 @@ static void hsw_write_infoframe(struct drm_encoder > *encoder, > struct drm_i915_private *dev_priv = to_i915(dev); > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); > - i915_reg_t data_reg; > int data_size = type == DP_SDP_VSC ? > VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE; > int i; > u32 val = I915_READ(ctl_reg); > > - data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0); > - Don't see any use for data_reg. hsw_dip_data_reg() is somewhat useful as it warns if 'type' happens to be invalid. But hsw_dip_data_reg() following this hunk should take care of the warning. Reviewed-by: Dhinakaran Pandiyan > val &= ~hsw_infoframe_enable(type); > I915_WRITE(ctl_reg, val); > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/5] drm/i915/psr: Display WA #1110
On Fri, 2018-02-23 at 16:59 -0800, Dhinakaran Pandiyan wrote: > On Tue, 2018-02-13 at 15:26 -0800, Rodrigo Vivi wrote: > > Missing flips when FBC is enabled with PSR > > link off/PSR2 deep sleep scenarios. > > > > I am wary of this. Is there a test to compare flip misses before/after > this workaround? We also have to confirm disabling FBC has the same > effect of not having this workaround. *having ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 5/5] drm/i915/psr: Display WA #1130: bxt, glk
On Tue, 2018-02-13 at 15:26 -0800, Rodrigo Vivi wrote:
> Host/Render modifications do not trigger PSR exit
> or Wireless quick capture exit correctly.
>
I don't get this workaround either. The wording indicates frontbuffer
modifications are expected to trigger PSR exit in HW. But we rely on the
driver's frontbuffer tracking to do that for us.
> WA: Set MMIO register 0x4653C bit 31 = 1b.
>
> Cc: Dhinakaran Pandiyan
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 7 +++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0f423cd52983..8a4cd8b4bd7c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3924,6 +3924,7 @@ enum {
> #define PWM1_GATING_DIS(1 << 13)
>
> #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
> +#define BXT_DCIPH_GATING_DIS (1 << 31)
> #define BXT_GMBUS_GATING_DIS (1 << 14)
>
> #define _CLKGATE_DIS_PSL_A 0x46520
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7e15b261821d..a0a6b4b7c47b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -114,6 +114,10 @@ static void bxt_init_clock_gating(struct
> drm_i915_private *dev_priv)
>*/
> I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
> PWM1_GATING_DIS | PWM2_GATING_DIS);
> +
> + /* Display WA #1130:bxt */
> + I915_WRITE(GEN9_CLKGATE_DIS_4, I915_READ(GEN9_CLKGATE_DIS_4) |
> +BXT_DCIPH_GATING_DIS);
> }
>
> static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
> @@ -137,6 +141,9 @@ static void glk_init_clock_gating(struct drm_i915_private
> *dev_priv)
> I915_WRITE(CHICKEN_MISC_2, val);
> }
>
> + /* Display WA #1130:glk */
> + I915_WRITE(GEN9_CLKGATE_DIS_4, I915_READ(GEN9_CLKGATE_DIS_4) |
> +BXT_DCIPH_GATING_DIS);
> }
>
> static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/5] drm/i915/psr: Display WA #1110
On Tue, 2018-02-13 at 15:26 -0800, Rodrigo Vivi wrote:
> Missing flips when FBC is enabled with PSR
> link off/PSR2 deep sleep scenarios.
>
I am wary of this. Is there a test to compare flip misses before/after
this workaround? We also have to confirm disabling FBC has the same
effect of not having this workaround.
+Ville
+Chris
any idea on how to quantitatively test if this workaround improves
anything?
> WA: When FBC is enabled with PSR/PSR2,
> set bit 30 of MMIO register 0x420CC to 1b.
>
> Cc: Dhinakaran Pandiyan
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_psr.c | 8 +++-
> 2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ac09d17cd835..0f423cd52983 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7153,6 +7153,7 @@ enum {
> #define CHICKEN_TRANS_A 0x420c0
> #define CHICKEN_TRANS_B 0x420c4
> #define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A,
> CHICKEN_TRANS_B)
> +#define DDI_MASK_INTERRUPTS_PSR (1<<30)
> #define DDI_TRAINING_OVERRIDE_ENABLE(1<<19)
> #define DDI_TRAINING_OVERRIDE_VALUE (1<<18)
> #define DDIE_TRAINING_OVERRIDE_ENABLE (1<<17) /* CHICKEN_TRANS_A only
> */
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 49554036ffb8..43c702b70519 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -481,7 +481,7 @@ static void hsw_psr_enable_source(struct intel_dp
> *intel_dp,
> struct drm_device *dev = dig_port->base.base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> - u32 chicken;
> + u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));
>
> if (dev_priv->psr.psr2_support) {
> chicken = PSR2_VSC_ENABLE_PROG_HEADER;
> @@ -508,6 +508,12 @@ static void hsw_psr_enable_source(struct intel_dp
> *intel_dp,
> EDP_PSR_DEBUG_MASK_HPD |
> EDP_PSR_DEBUG_MASK_LPSP);
> }
> +
> + /* Display WA #1110: skl,kbl,cfl,bxt */
> + if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) {
> + chicken |= DDI_MASK_INTERRUPTS_PSR;
> + I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
> + }
> }
>
> /**
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 02/10] drm: i915: Get DSC capability from DP sink
On Fri, Feb 23, 2018 at 09:25:45PM +0530, Gaurav K Singh wrote:
> Get decompression capabilities from DP sink by doing
> DPCD reads of different offsets as per eDP/DP specs.
>
> Signed-off-by: Gaurav K Singh
> ---
> drivers/gpu/drm/i915/intel_dp.c | 167
>
> 1 file changed, 167 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 1868f73f730c..f494a851ff89 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5883,6 +5883,149 @@ void intel_edp_drrs_flush(struct drm_i915_private
> *dev_priv,
> return downclock_mode;
> }
>
> +static void intel_dp_sink_get_dsc_capability(struct intel_dp *intel_dp,
> + struct dp_sink_dsc_caps *dp_dsc_caps)
> +{
> + u8 rcbuffer_blocksize;
> + u8 fec_dpcd;
> + unsigned long line_buffer_bit_depth, sink_support_max_bpp_msb;
> +
Clear the previously cached dsc_dpcd before caching them again since it might
still
have those from previous edp > 1.4 but we might not need them if current edp <
1.4
> + /* VDSC is supported only for eDp v1.4 or higher, DPCD 0x00700 offset */
> + if (intel_dp->edp_dpcd[0] < 0x03)
Use the #define DP_EDP_14 for the eDP version check of 1.4
> + return;
> +
> + /* Read DPCD 0x060 to 0x06a */
> + if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT, intel_dp->dsc_dpcd,
> + sizeof(intel_dp->dsc_dpcd)) < 0)
> + return;
> +
> + dp_dsc_caps->is_dsc_supported = intel_dp->dsc_dpcd[0] &
> + DP_DSC_DECOMPRESSION_IS_SUPPORTED;
Like I mentioned on patch 1/10 from the reviews I had got on my DSC patches,
no need to have is_dsc_supported field or dp_dsc_caps since the entire set of
DPCD registers is cached, this can be computed on the fly when needed.
> +
> + if (!dp_dsc_caps->is_dsc_supported)
> + return;
> +
> + drm_dp_dpcd_readb(&intel_dp->aux, 0x090, &fec_dpcd);
> + intel_dp->fec_dpcd = fec_dpcd;
> +
> + /* For DP DSC, FEC support is must */
FEC support is only needed for DP DSC not eDP, but looks like currently this
function is only getting called on eDP init connector and not on all DP
hotplug processing. If its for DP then, even DP 1.4 version check needed.
Since here its only eDP, FEC is not mandatory infact no FEC support on eDP 1.4.
> + if (!(intel_dp->fec_dpcd & 0x1))
> + return;
> +
> + /* No VDSC support for less than 8 BPC */
> + if (intel_dp->dsc_dpcd[0xa] < DP_DSC_8_BPC)
Use some #define instead of 0xa ( I had used intel_dp->dsc_dpcd[DP_DSC_BPC -
DP_DSC_SUPPORT])
> + return;
What happens to the cached values when you return from this function in case of
no VDSC support. Shouldnt they be reset now that it cannot be implemented.
> +
> + if (intel_dp->dsc_dpcd[0xa] & DP_DSC_8_BPC)
> + DRM_INFO("8 Bits per color support\n");
> + if (intel_dp->dsc_dpcd[0xa] & DP_DSC_10_BPC)
> + DRM_INFO("10 Bits per color support\n");
> + if (intel_dp->dsc_dpcd[0xa] & DP_DSC_12_BPC)
> + DRM_INFO("12 Bits per color support\n");
> +
> + dp_dsc_caps->dsc_major_ver = intel_dp->dsc_dpcd[1] & DP_DSC_MAJOR_MASK;
> + dp_dsc_caps->dsc_minor_ver = (intel_dp->dsc_dpcd[1] &
> + DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT;
> +
> + rcbuffer_blocksize = intel_dp->dsc_dpcd[2] & 0x3;
> +
> + switch (rcbuffer_blocksize) {
> + case 0:
> + dp_dsc_caps->rcbuffer_blocksize = 1;
> + break;
> + case 1:
> + dp_dsc_caps->rcbuffer_blocksize = 4;
> + break;
> + case 2:
> + dp_dsc_caps->rcbuffer_blocksize = 16;
> + break;
> + case 3:
> + dp_dsc_caps->rcbuffer_blocksize = 64;
> + break;
> + default:
> + break;
> +
> + }
> + dp_dsc_caps->rcbuffer_size_in_blocks = intel_dp->dsc_dpcd[3] + 1;
> +
> + dp_dsc_caps->rcbuffer_size =
> + dp_dsc_caps->rcbuffer_size_in_blocks *
> + dp_dsc_caps->rcbuffer_blocksize * 1024 * 8;
> +
Move this rc buffer computation to a helper. (refer to my patch)
> + dp_dsc_caps->slice_caps = intel_dp->dsc_dpcd[4];
get this again in a helper. Refer to my patch.
> + line_buffer_bit_depth = intel_dp->dsc_dpcd[5];
> +
> + if (line_buffer_bit_depth == 8)
> + dp_dsc_caps->line_buffer_bit_depth = intel_dp->dsc_dpcd[5];
> + else
> + dp_dsc_caps->line_buffer_bit_depth = intel_dp->dsc_dpcd[5] + 9;
Move these above to helpers and use #defines for these numerical values making
it
more readable.
> +
> + dp_dsc_caps->is_block_pred_supported = intel_dp->dsc_dpcd[6] &
> + DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
> +
> + dp_dsc_caps->sink_support_max_bpp = intel_dp->dsc_dpcd[7];
> +
Re: [Intel-gfx] [PATCH 3/5] drm/i915/psr: Display WA 0884 applied broadly for more HW tracking.
On Tue, 2018-02-13 at 15:26 -0800, Rodrigo Vivi wrote:
> WA 0884:bxt:all,cnl:*:A - "When FBC is enabled with eDP PSR,
> the CPU host modify writes may not get updated on the Display
> as expected.
> WA: Write 0x to CUR_SURFLIVE_A with every CPU
> host modify write to trigger PSR exit."
>
> We can also find on spec other cases where they describe
> bogus writes to cursor registers to force PSR exit with
> HW tracking. And it was confirmed by HW engineers that
> this Wa can be safely applied for any frontbuffer activity.
>
So the idea is to do a dummy MMIO write to trigger PSR exit.
> So let's use this more and more here instead of forcibly
> disable and re-enable PSR everytime that we have a simple
> reliable flush case.
>
> Other commits improve the fbcon/fbdev use a lot, but this
> approach is the only when where we can get a fully reliable
> console with no slowness or missed frames and PSR still
> enabled and active.
>
> Cc: Dhinakaran Pandiyan
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_psr.c | 15 +--
> 2 files changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f6afa5e5e7c1..ac09d17cd835 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6007,6 +6007,9 @@ enum {
> #define IVB_CURSOR_B_OFFSET 0x71080
> #define IVB_CURSOR_C_OFFSET 0x72080
>
> +#define _CUR_SURLIVE 0x700AC
> +#define CUR_SURLIVE(pipe)_CURSOR2(pipe, _CUR_SURLIVE)
Register address is correct.
This is a *status* register that provides current surface base address.
We aren't reading this register anywhere, so writing to it should be
fine.
> +
> /* Display A control */
> #define _DSPACNTR0x70180
> #define DISPLAY_PLANE_ENABLE (1<<31)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 13409c6301e8..49554036ffb8 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -946,8 +946,19 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
>
> /* By definition flush = invalidate + flush */
> - if (frontbuffer_bits)
> - intel_psr_exit(dev_priv);
> + if (frontbuffer_bits) {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> + intel_psr_exit(dev_priv);
> + } else {
> + /*
> + * Display WA #0884: all
> + * This documented WA for bxt can be safely applied
> + * broadly so we can force HW tracking to exit PSR
> + * instead of disabling and re-enabling.
> + */
> + I915_WRITE(CUR_SURLIVE(pipe), 0);
The workaround asks 0 to be written to CUR_SURFLIVE_A. But I think
writing to the active pipe register makes sense.Can you add that to the
comment since the patch deviates from the workaround?
> + }
> + }
>
> if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) {
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
There is a psr_activate that follows, you should remove that too. HW
should be able to activate PSR by itself.
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/5] drm/i915: Improve PSR activation timing
On Tue, Feb 13, 2018 at 11:26 PM, Rodrigo Vivi wrote: > From: Andy Lutomirski > > + > + dev_priv->psr.activate_timer.expires = jiffies - 1; That can't possibly be okay. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/10] drm: i915: Defining Compression Capabilities
On Fri, Feb 23, 2018 at 09:25:44PM +0530, Gaurav K Singh wrote:
> For Vesa Display Stream compression, defining structures for
> compression capabilities to be stored in encoder.
>
> Signed-off-by: Gaurav K Singh
> ---
> drivers/gpu/drm/i915/i915_drv.h | 125
> +++
> drivers/gpu/drm/i915/intel_drv.h | 62 +++
> include/drm/drm_dp_helper.h | 1 +
> 3 files changed, 188 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0d8cb74e7d02..4b1c323c0925 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -780,6 +780,131 @@ struct i915_psr {
> void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *);
> };
>
> +/* DSC Configuration structure */
> +#define NUM_BUF_RANGES 15
> +
> +/* Configuration for a single Rate Control model range */
> +struct rc_range_parameters {
> + /* Min Quantization Parameters allowed for this range */
> + unsigned long range_min_qp;
Its only a 5 bit value, so uint_8 should be good, why have a unsigned long.
Same for max_qp which is 5 bits and bpg_offset which is 6 bits.
Please consider these for the parameters below.
> + /* Max Quantization Parameters allowed for this range */
> + unsigned long range_max_qp;
> + /* Bits/group offset to apply to target for this group */
> + unsigned long range_bpg_offset;
> +};
> +
> +struct vdsc_config {
> + /* Bits / component for previous reconstructed line buffer */
> + unsigned long line_buf_depth;
> + /*
> + * Rate control buffer size (in bits); not in PPS,
> + * used only in C model for checking overflow
> + */
> + unsigned long rc_bits;
> + /* Bits per component to code (must be 8, 10, or 12) */
> + unsigned long bits_per_component;
> + /*
> + * Flag indicating to do RGB - YCoCg conversion
> + * and back (should be 1 for RGB input)
> + */
> + bool convert_rgb;
> + unsigned long slice_count;
For eDP, it can be max 4, why unsigned long?
> + /* Slice Width */
> + unsigned long slice_width;
> + /* Slice Height */
> + unsigned long slice_height;
> + /*
> + * 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
> + * outside of DSC encode/decode algorithm)
> + */
> + bool enable422;
> + /* Picture Width */
> + unsigned long pic_width;
> + /* Picture Height */
> + unsigned long pic_height;
> + /* Offset to bits/group used by RC to determine QP adjustment */
> + unsigned long rc_tgt_offset_high;
> + /* Offset to bits/group used by RC to determine QP adjustment */
> + unsigned long rc_tgt_offset_low;
> + /* Bits/pixel target << 4 (ie., 4 fractional bits) */
> + unsigned long bits_per_pixel;
> + /*
> + * Factor to determine if an edge is present based
> + * on the bits produced
> + */
> + unsigned long rc_edge_factor;
> + /* Slow down incrementing once the range reaches this value */
> + unsigned long rc_quant_incr_limit1;
> + /* Slow down incrementing once the range reaches this value */
> + unsigned long rc_quant_incr_limit0;
> + /* Number of pixels to delay the initial transmission */
> + unsigned long initial_xmit_delay;
> + /* Number of pixels to delay the VLD on the decoder,not including SSM */
> + unsigned long initial_dec_delay;
> + /* Block prediction range (in pixels) */
> + bool block_pred_enable;
> + /* Bits/group offset to use for first line of the slice */
> + unsigned long first_line_bpg_Ofs;
> + /* Value to use for RC model offset at slice start */
> + unsigned long initial_offset;
> + /* X position in the picture of top-left corner of slice */
> + unsigned long x_start;
> + /* Y position in the picture of top-left corner of slice */
> + unsigned long y_start;
> + /* Thresholds defining each of the buffer ranges */
> + unsigned long rc_buf_thresh[NUM_BUF_RANGES - 1];
> + /* Parameters for each of the RC ranges */
> + struct rc_range_parameters rc_range_params[NUM_BUF_RANGES];
> + /* Total size of RC model */
> + unsigned long rc_model_size;
> + /* Minimum QP where flatness information is sent */
> + unsigned long flatness_minQp;
> + /* Maximum QP where flatness information is sent */
> + unsigned long flatness_maxQp;
> + /*
> + * MAX-MIN for all components is required to
> + * be <= this value for flatness to be used
> + */
> + unsigned long flatness_det_thresh;
> + /* Initial value for scale factor */
> + unsigned long initial_scale_value;
> + /* Decrement scale factor every scale_decrement_interval groups */
> + unsigned long scale_decrement_interval;
> + /* Increment scale factor every scale_increment_interval groups */
> + unsigned long scale_increment_interval;
> + /* Non-first line BPG offset
Re: [Intel-gfx] [PATCH 2/5] drm/i915/psr: Kill scheduled work for Core platforms.
On Tue, 2018-02-13 at 15:26 -0800, Rodrigo Vivi wrote:
> It is a fact that scheduled work is now improved.
>
> But it is also a fact that on core platforms that shouldn't
> be needed. We only need to actually wait on VLV/CHV.
>
> The immediate enabling is actually not an issue for the
> HW perspective for core platforms that have HW tracking.
> HW will wait few identical idle frames before transitioning
> to actual psr active anyways.
>
> Note that this patch also remove the delayed activation
> on HSW and BDW introduced by commit 'd0ac896a477d
> ("drm/i915: Delay first PSR activation.")'. This was
> introduced to fix a blank screen on VLV/CHV and also
> masked some frozen screens on other core platforms.
> Probably the same that we are now properly hunting and fixing.
>
> Furthermore, if we stop using delayed activation on core
> platforms we will be able, on following up patches,
> to use available workarounds to make HW tracking properly
> exit PSR instead of the big nuke of disabling psr and
> re-enable on exit and activate respectively.
> At least on few reliable cases.
>
> Cc: Dhinakaran Pandiyan
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 14 +++---
> drivers/gpu/drm/i915/intel_psr.c| 27 +++
> 2 files changed, 26 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index da80ee16a3cf..541290c307c7 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2522,18 +2522,18 @@ static int i915_edp_psr_status(struct seq_file *m,
> void *data)
> seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
> dev_priv->psr.busy_frontbuffer_bits);
>
> - if (timer_pending(&dev_priv->psr.activate_timer))
> - seq_printf(m, "Activate scheduled: yes, in %dms\n",
> -
> jiffies_to_msecs(dev_priv->psr.activate_timer.expires - jiffies));
> - else
> - seq_printf(m, "Activate scheduled: no\n");
> -
> - if (HAS_DDI(dev_priv)) {
> + if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
I don't get this change, it is better to retain HAS_DDI().
> if (dev_priv->psr.psr2_support)
> enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
> else
> enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
> } else {
> + if (timer_pending(&dev_priv->psr.activate_timer))
> + seq_printf(m, "Activate scheduled: yes, in %dms\n",
> +
> jiffies_to_msecs(dev_priv->psr.activate_timer.expires - jiffies));
> + else
> + seq_printf(m, "Activate scheduled: no\n");
> +
> for_each_pipe(dev_priv, pipe) {
> enum transcoder cpu_transcoder =
> intel_pipe_to_cpu_transcoder(dev_priv, pipe);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 826b480841ac..13409c6301e8 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -455,6 +455,8 @@ static void intel_psr_schedule(struct drm_i915_private
> *i915,
> {
> unsigned long next;
>
> + WARN_ON(!IS_VALLEYVIEW(i915) && !IS_CHERRYVIEW(i915));
> +
How about using only !(IS_VLV() || IS_CHV) in this file.
I think this is a reasonable check to have, please add a return too.
WARN_ON(!(IS_VLV() || IS_CHV())
return;
> lockdep_assert_held(&i915->psr.lock);
>
> /*
> @@ -543,7 +545,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
> dev_priv->psr.enable_source(intel_dp, crtc_state);
> dev_priv->psr.enabled = intel_dp;
>
> - if (INTEL_GEN(dev_priv) >= 9) {
> + if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
How about inverting this?
if (IS_VLV() || IS_CHV())
intel_psr_schedule()
else
intel_psr_activate()
is easier to follow IMO.
What is the reason to not use HAS_DDI() ?
> intel_psr_activate(intel_dp);
> } else {
> /*
> @@ -553,8 +555,6 @@ void intel_psr_enable(struct intel_dp *intel_dp,
>* However on some platforms we face issues when first
>* activation follows a modeset so quickly.
>* - On VLV/CHV we get bank screen on first activation
> - * - On HSW/BDW we get a recoverable frozen screen until
> - * next exit-activate sequence.
>*/
> intel_psr_schedule(dev_priv,
> intel_dp->panel_power_cycle_delay * 5);
> @@ -687,6 +687,8 @@ static void intel_psr_work(struct work_struct *work)
> struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
> enum pipe pipe = to_intel_crtc(crtc)->pipe;
>
> + WARN_ON(!IS_VALLEYVIEW
[Intel-gfx] [PATCH v3] drm/i915: Disable SAGV on pre plane update.
According to Spec "Requirement before plane enabling or
configuration change: Disable SAGV if any enabled plane will not
be able to enable watermarks for memory latency >= SAGV block
time, or any transcoder is interlaced. Else, enable SAGV."
Currently we are only enabling and disabling SAGV on full
modeset. If we end up changing plane configurations and
sagv remains enabled when latency is higher than sagv block
time the machine can hang.
Also we are computing the latency values in different places
and following different conditions/rules. So let's move the
the sagv block time limit check to be inside skl_compute_wm
and, if necessary, disable SAGV on pre plane updates.
SAGV defaults to enabled by the BIOS, so we need to be more
careful and disable everytime we see a mismatch on its
conditions.
v2: - Consider only highest enabled wm level for SAGV block
time limitation.
- Handle sagv bool in a way that we properly consider all
the planes. So we don't end up always disabling SAGV.
- (Ville) Don't enabled on post_plane update, otherwise one
pipe ends up enabling without checking for others. So keep
the old enable/disable solution on atomic commit tail
so we continue following the spec to disable on multiple
pipe or interlaced and re-enable on modeset of a single
pipe non interlaced. Always respecting the latency.
v3: Remove unused dev and dev_priv. Forgot from v1 on v2.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104975
Cc: Maarten Lankhorst
Cc: Azhar Shaikh
Cc: Ville Syrjälä
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_display.c | 25 +++-
drivers/gpu/drm/i915/intel_drv.h | 2 +
drivers/gpu/drm/i915/intel_pm.c | 108 +--
3 files changed, 78 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 65c8487be7c7..7b3af459860a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5098,10 +5098,14 @@ static void intel_post_plane_update(struct
intel_crtc_state *old_crtc_state)
struct drm_plane_state *old_pri_state =
drm_atomic_get_existing_plane_state(old_state, primary);
+ DRM_ERROR("I915-DEBUG: %s %d\n", __FUNCTION__, __LINE__);
+
intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
- if (pipe_config->update_wm_post && pipe_config->base.active)
+ if (pipe_config->update_wm_post && pipe_config->base.active) {
+ DRM_ERROR("I915-DEBUG: %s %d - Update WM post \n",
__FUNCTION__, __LINE__);
intel_update_watermarks(crtc);
+ }
if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
hsw_enable_ips(pipe_config);
@@ -5203,8 +5207,14 @@ static void intel_pre_plane_update(struct
intel_crtc_state *old_crtc_state,
if (dev_priv->display.initial_watermarks != NULL)
dev_priv->display.initial_watermarks(old_intel_state,
pipe_config);
- else if (pipe_config->update_wm_pre)
+ else if (pipe_config->update_wm_pre) {
+ DRM_ERROR("I915-DEBUG: %s %d - Update WM pre?\n", __FUNCTION__,
__LINE__);
intel_update_watermarks(crtc);
+ }
+
+ if (!pipe_config->sagv)
+ intel_disable_sagv(dev_priv);
+ DRM_ERROR("I915-DEBUG: %s %d\n", __FUNCTION__, __LINE__);
}
static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned
plane_mask)
@@ -5214,6 +5224,7 @@ static void intel_crtc_disable_planes(struct drm_crtc
*crtc, unsigned plane_mask
struct drm_plane *p;
int pipe = intel_crtc->pipe;
+ DRM_ERROR("I915-DEBUG: %s %d\n", __FUNCTION__, __LINE__);
intel_crtc_dpms_overlay_disable(intel_crtc);
drm_for_each_plane_mask(p, dev, plane_mask)
@@ -12152,6 +12163,7 @@ static void intel_update_crtc(struct drm_crtc *crtc,
update_scanline_offset(intel_crtc);
dev_priv->display.crtc_enable(pipe_config, state);
} else {
+ DRM_ERROR("I915-DEBUG: %s %d\n", __FUNCTION__, __LINE__);
intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
pipe_config);
}
@@ -12171,6 +12183,8 @@ static void intel_update_crtcs(struct drm_atomic_state
*state)
struct drm_crtc_state *old_crtc_state, *new_crtc_state;
int i;
+ DRM_ERROR("I915-DEBUG: %s %d\n", __FUNCTION__, __LINE__);
+
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
if (!new_crtc_state->active)
continue;
@@ -12326,10 +12340,12 @@ static void intel_atomic_commit_tail(struct
drm_atomic_state *state)
if (!needs_modeset(new_crtc_state))
continue;
+ DRM_ERROR("I915-DEBUG: %
Re: [Intel-gfx] [PATCH 1/5] drm/i915: Improve PSR activation timing
"Pandiyan, Dhinakaran" writes:
> On Tue, 2018-02-13 at 15:26 -0800, Rodrigo Vivi wrote:
>> From: Andy Lutomirski
>>
>> The current PSR code has a two call sites that each schedule delayed
>> work to activate PSR. As far as I can tell, each call site intends
>> to keep PSR inactive for the given amount of time and then allow it
>> to be activated.
>>
>> The call sites are:
>>
>> - intel_psr_enable(), which explicitly states in a comment that
>>it's trying to keep PSR off a short time after the dispay is
>>initialized as a workaround.
>>
>> - intel_psr_flush(). There isn't an explcit explanation, but the
>>intent is presumably to keep PSR off until the display has been
>>idle for 100ms.
>>
>> The current code doesn't actually accomplish either of these goals.
>> Rather than keeping PSR inactive for the given amount of time, it
>> will schedule PSR for activation after the given time, with the
>> earliest target time in such a request winning.
>>
>> In other words, if intel_psr_enable() is immediately followed by
>> intel_psr_flush(), then PSR will be activated after 100ms even if
>> intel_psr_enable() wanted a longer delay. And, if the screen is
>> being constantly updated so that intel_psr_flush() is called once
>> per frame at 60Hz, PSR will still be activated once every 100ms.
>>
>> Rewrite the code so that it does what was intended. This adds
>> a new function intel_psr_schedule(), which will enable PSR after
>> the requested time but no sooner.
>>
>> Signed-off-by: Andy Lutomirski
>> Tested-by: Rodrigo Vivi
>> Acked-by: Rodrigo Vivi
>> Signed-off-by: Rodrigo Vivi
>>
>> ---
>> drivers/gpu/drm/i915/i915_debugfs.c | 8 +++--
>> drivers/gpu/drm/i915/i915_drv.h | 3 +-
>> drivers/gpu/drm/i915/intel_psr.c| 66
>> -
>> 3 files changed, 66 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
>> b/drivers/gpu/drm/i915/i915_debugfs.c
>> index 960302668649..da80ee16a3cf 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -2521,8 +2521,12 @@ static int i915_edp_psr_status(struct seq_file *m,
>> void *data)
>> seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
>> seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
>> dev_priv->psr.busy_frontbuffer_bits);
>> -seq_printf(m, "Re-enable work scheduled: %s\n",
>> - yesno(work_busy(&dev_priv->psr.work.work)));
>> +
>> +if (timer_pending(&dev_priv->psr.activate_timer))
>> +seq_printf(m, "Activate scheduled: yes, in %dms\n",
>> +
>> jiffies_to_msecs(dev_priv->psr.activate_timer.expires - jiffies));
>> +else
>> +seq_printf(m, "Activate scheduled: no\n");
>>
>> if (HAS_DDI(dev_priv)) {
>> if (dev_priv->psr.psr2_support)
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index c06d4126c447..2afa5c05a79b 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -762,7 +762,8 @@ struct i915_psr {
>> bool sink_support;
>> struct intel_dp *enabled;
>> bool active;
>> -struct delayed_work work;
>> +struct timer_list activate_timer;
>> +struct work_struct activate_work;
>> unsigned busy_frontbuffer_bits;
>> bool psr2_support;
>> bool aux_frame_sync;
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c
>> b/drivers/gpu/drm/i915/intel_psr.c
>> index 2ef374f936b9..826b480841ac 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -450,6 +450,28 @@ static void intel_psr_activate(struct intel_dp
>> *intel_dp)
>> dev_priv->psr.active = true;
>> }
>>
>> +static void intel_psr_schedule(struct drm_i915_private *i915,
>> + unsigned long min_wait_ms)
>> +{
>> +unsigned long next;
>> +
>> +lockdep_assert_held(&i915->psr.lock);
>> +
>> +/*
>> + * We update next enable and call mod_timer() because it's
>> + * possible that intel_psr_wrk() has already been called and is
>> + * waiting for psr.lock. If that's the case, we don't want it
>> + * to immediately enable PSR.
>> + *
>> + * We also need to make sure that PSR is never activated earlier
>> + * than requested to avoid breaking intel_psr_enable()'s workaround
>> + * for pre-gen9 hardware.
>> + */
>> +next = jiffies + msecs_to_jiffies(min_wait_ms);
>> +if (time_after(next, i915->psr.activate_timer.expires))
>
> .expires is an internal member, does not seem like a good idea to read
> it outside of the exported interfaces.
Chris I believe this question is for you.
I just ignored for a while because I thought it was for Andy,
but now I saw that you modified the original patch on exactly this point.
Btw I believe this is a modification that should had been clear
highlighted when you sent and with your Signed-o
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Disable SAGV on pre plane update. (rev2)
== Series Details == Series: drm/i915: Disable SAGV on pre plane update. (rev2) URL : https://patchwork.freedesktop.org/series/38806/ State : failure == Summary == CHK include/config/kernel.release CHK include/generated/uapi/linux/version.h CHK include/generated/utsrelease.h CHK include/generated/bounds.h CHK include/generated/timeconst.h CHK include/generated/asm-offsets.h CALLscripts/checksyscalls.sh DESCEND objtool CHK scripts/mod/devicetable-offsets.h CHK include/generated/compile.h CHK kernel/config_data.h CC [M] drivers/gpu/drm/i915/intel_display.o drivers/gpu/drm/i915/intel_display.c: In function ‘intel_post_plane_update’: drivers/gpu/drm/i915/intel_display.c:5094:27: error: unused variable ‘dev_priv’ [-Werror=unused-variable] struct drm_i915_private *dev_priv = to_i915(dev); ^~~~ cc1: all warnings being treated as errors scripts/Makefile.build:316: recipe for target 'drivers/gpu/drm/i915/intel_display.o' failed make[4]: *** [drivers/gpu/drm/i915/intel_display.o] Error 1 scripts/Makefile.build:575: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:575: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:575: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1048: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: Disable SAGV on pre plane update.
According to Spec "Requirement before plane enabling or
configuration change: Disable SAGV if any enabled plane will not
be able to enable watermarks for memory latency >= SAGV block
time, or any transcoder is interlaced. Else, enable SAGV."
Currently we are only enabling and disabling SAGV on full
modeset. If we end up changing plane configurations and
sagv remains enabled when latency is higher than sagv block
time the machine can hang.
Also we are computing the latency values in different places
and following different conditions/rules. So let's move the
the sagv block time limit check to be inside skl_compute_wm
and, if necessary, disable SAGV on pre plane updates.
SAGV defaults to enabled by the BIOS, so we need to be more
careful and disable everytime we see a mismatch on its
conditions.
v2: - Consider only highest enabled wm level for SAGV block
time limitation.
- Handle sagv bool in a way that we properly consider all
the planes. So we don't end up always disabling SAGV.
- (Ville) Don't enabled on post_plane update, otherwise one
pipe ends up enabling without checking for others. So keep
the old enable/disable solution on atomic commit tail
so we continue following the spec to disable on multiple
pipe or interlaced and re-enable on modeset of a single
pipe non interlaced. Always respecting the latency.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104975
Cc: Maarten Lankhorst
Cc: Azhar Shaikh
Cc: Ville Syrjälä
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_display.c | 6 +-
drivers/gpu/drm/i915/intel_drv.h | 2 +
drivers/gpu/drm/i915/intel_pm.c | 107 +--
3 files changed, 60 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 65c8487be7c7..d98ff5916c85 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5090,6 +5090,8 @@ static bool hsw_post_update_enable_ips(const struct
intel_crtc_state *old_crtc_s
static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_atomic_state *old_state = old_crtc_state->base.state;
struct intel_crtc_state *pipe_config =
intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
@@ -5205,6 +5207,9 @@ static void intel_pre_plane_update(struct
intel_crtc_state *old_crtc_state,
pipe_config);
else if (pipe_config->update_wm_pre)
intel_update_watermarks(crtc);
+
+ if (!pipe_config->sagv)
+ intel_disable_sagv(dev_priv);
}
static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned
plane_mask)
@@ -12372,7 +12377,6 @@ static void intel_atomic_commit_tail(struct
drm_atomic_state *state)
*/
if (!intel_can_enable_sagv(state))
intel_disable_sagv(dev_priv);
-
intel_modeset_verify_disabled(dev, state);
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1535bfb7ea40..294b6ac6c72c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -712,6 +712,7 @@ struct intel_crtc_state {
bool update_pipe; /* can a fast modeset be performed? */
bool disable_cxsr;
bool update_wm_pre, update_wm_post; /* watermarks are updated */
+ bool sagv; /* Disable SAGV on any latency higher than its block time */
bool fb_changed; /* fb on any of the planes is changed */
bool fifo_changed; /* FIFO split is changed */
@@ -2002,6 +2003,7 @@ void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
bool intel_can_enable_sagv(struct drm_atomic_state *state);
+u8 intel_sagv_block_time(const struct drm_i915_private *dev_priv);
int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
bool skl_wm_level_equals(const struct skl_wm_level *l1,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 21dac6ebc202..0bf3bf386def 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3687,22 +3687,12 @@ bool intel_can_enable_sagv(struct drm_atomic_state
*state)
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
struct intel_crtc *crtc;
- struct intel_plane *plane;
struct intel_crtc_state *cstate;
enum pipe pipe;
- int level, latency;
- int sagv_block_time_us;
Re: [Intel-gfx] [PATCH 00/10] Enabling VDSC in i915 driver for GLK
Thanks for the patches. I am working on the DSC support on i915 for eDP/DP as well. Looking at the patches below, this is specific to VDSC enabling for eDP panels and not for the external DP. So please mention that specifically in the cover letter as well. On Fri, Feb 23, 2018 at 09:25:43PM +0530, Gaurav K Singh wrote: > Display manufacturers are turning to higher-resolution displays > to differentiate their products. The increased pixel counts have > required increased bandwidth over the links that drive these displays. > However, advances in physical layer technology have not kept up > with the increases in pixel counts. > > These factors have created a need for compression on display links. > The Video Electronics Standards Association(VESA),in liaison with the > MIPI Alliance, has developed an industry standard Display Stream > Compression(DSC) > for interoperable, visually lossless compression over display links. > > These patches enable VDSC in i915 gfx driver for Gen9,Gen10 platforms Please specify that this enables VDSC for eDp in i915 gfx driver. > and provide basic code for future platforms. > > Testing: > Did testing on GLK RVP. By default GLK RVP has non-DSC EDP panel, there was > no regression with these patches. > > BA Chrome Team (OTC) do not have EDP panel which supports DSC. > Trying to arrrage DSC EDP panel from other teams in BA, hopeful to get it in > few weeks. > I do have a DSC eDP panel here in Oregon and can volunteer for testing your patches with that on GLK RVP. Manasi > Dropping the patches to get the review started. > > Gaurav K Singh (10): > drm: i915: Defining Compression Capabilities > drm: i915: Get DSC capability from DP sink > drm: i915: Enable/Disable DSC in DP sink > drm: i915: Compute RC & DSC parameters > drm: i915: Define Picture Parameter Set > drm/i915: Populate PPS Secondary Data Pkt for Sink > drm: i915: Define VDSC regs and DSC params > drm: i915: Enable VDSC in Source > drm: i915: Disable VDSC from Source > drm/i915: Encoder enable/disable seq wrt DSC > > drivers/gpu/drm/i915/Makefile|1 + > drivers/gpu/drm/i915/i915_drv.h | 589 > drivers/gpu/drm/i915/i915_reg.h | 451 > drivers/gpu/drm/i915/intel_ddi.c |4 + > drivers/gpu/drm/i915/intel_display.c | 20 + > drivers/gpu/drm/i915/intel_dp.c | 182 + > drivers/gpu/drm/i915/intel_drv.h | 64 ++ > drivers/gpu/drm/i915/intel_vdsc.c| 1243 > ++ > include/drm/drm_dp_helper.h |3 + > 9 files changed, 2557 insertions(+) > create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c > > -- > 1.9.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [CI,1/6] drm/i915/psr: New power domain for AUX IO.
== Series Details == Series: series starting with [CI,1/6] drm/i915/psr: New power domain for AUX IO. URL : https://patchwork.freedesktop.org/series/38892/ State : warning == Summary == Series 38892v1 series starting with [CI,1/6] drm/i915/psr: New power domain for AUX IO. https://patchwork.freedesktop.org/api/1.0/series/38892/revisions/1/mbox/ Test kms_chamelium: Subgroup dp-edid-read: fail -> PASS (fi-kbl-7500u) fdo#102505 Subgroup common-hpd-after-suspend: pass -> DMESG-WARN (fi-skl-6700k2) Test kms_force_connector_basic: Subgroup force-connector-state: skip -> PASS (fi-snb-2520m) Subgroup force-edid: skip -> PASS (fi-snb-2520m) Subgroup force-load-detect: skip -> PASS (fi-snb-2520m) Subgroup prune-stale-modes: skip -> PASS (fi-snb-2520m) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-c: incomplete -> PASS (fi-bxt-dsi) fdo#103927 fdo#102505 https://bugs.freedesktop.org/show_bug.cgi?id=102505 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:416s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:422s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:372s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:483s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:285s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:476s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:481s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:462s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:452s fi-cfl-8700k total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:395s fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:561s fi-cnl-y3total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:572s fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:413s fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:282s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:507s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:384s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:407s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:454s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:411s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:447s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:493s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:448s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:493s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:590s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:428s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:497s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:516s fi-skl-6700k2total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:482s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:479s fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:410s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:427s fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:510s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:387s 316ba650abe6c1e8ac2f812ff21eee5771546ba1 drm-tip: 2018y-02m-23d-16h-41m-52s UTC integration manifest 4b1e8f46a5ea drm/i915/dp: Move comment about hw timeout to the right place. 690a3b160e7f drm/i915/dp: Remove redundant sleep after AUX transaction length check. eba885892c9b drm/i915/psr: Check for the specific AUX_FRAME_SYNC cap bit. 35774af3a8e7 drm/i915/psr: Extract PSR DPCD initialization and move it to intel_psr.c b38d36c230a3 drm/i915/frontbuffer: Mark frontbuffer flush and invalidate with might_sleep() 2555970971c7 drm/i915/psr: New power domain for AUX IO. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8148/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [v5,1/2] drm/i915: Move a bunch of workaround-related code to its own file
== Series Details == Series: series starting with [v5,1/2] drm/i915: Move a bunch of workaround-related code to its own file URL : https://patchwork.freedesktop.org/series/38891/ State : warning == Summary == Series 38891v1 series starting with [v5,1/2] drm/i915: Move a bunch of workaround-related code to its own file https://patchwork.freedesktop.org/api/1.0/series/38891/revisions/1/mbox/ Test gem_ringfill: Subgroup basic-default-forked: pass -> SKIP (fi-bsw-n3050) Test kms_chamelium: Subgroup dp-edid-read: fail -> PASS (fi-kbl-7500u) fdo#102505 Test kms_force_connector_basic: Subgroup force-connector-state: skip -> PASS (fi-snb-2520m) Subgroup force-edid: skip -> PASS (fi-snb-2520m) Subgroup force-load-detect: skip -> PASS (fi-snb-2520m) Subgroup prune-stale-modes: skip -> PASS (fi-snb-2520m) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: pass -> INCOMPLETE (fi-snb-2520m) fdo#103713 Subgroup suspend-read-crc-pipe-c: incomplete -> PASS (fi-bxt-dsi) fdo#103927 fdo#102505 https://bugs.freedesktop.org/show_bug.cgi?id=102505 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:417s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:426s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:376s fi-bsw-n3050 total:288 pass:241 dwarn:0 dfail:0 fail:0 skip:47 time:493s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:284s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:481s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:485s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:470s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:469s fi-cfl-8700k total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:389s fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:571s fi-cnl-y3total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:570s fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:419s fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:301s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:510s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:385s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:411s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:457s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:412s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:451s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:491s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:451s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:495s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:590s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:435s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:502s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:522s fi-skl-6700k2total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:492s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:473s fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:408s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:431s fi-snb-2520m total:245 pass:211 dwarn:0 dfail:0 fail:0 skip:33 fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:395s 316ba650abe6c1e8ac2f812ff21eee5771546ba1 drm-tip: 2018y-02m-23d-16h-41m-52s UTC integration manifest 94ee8276639b drm/i915: Split out functions for different kinds of workarounds 37fc8c70864a drm/i915: Move a bunch of workaround-related code to its own file == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8147/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 2/6] drm/i915/frontbuffer: Mark frontbuffer flush and invalidate with might_sleep()
From: "Dhinakaran Pandiyan" Frontbuffer flush and invalidate call psr, fbc and drrs functions that use mutexes but they can be called in atomic contexts in the fbdev path. The point where the spinlocks are acquired is up in the call stack that is not entirely easy to spot, so annotate with might_sleep(). Cc: Rodrigo Vivi Signed-off-by: Dhinakaran Pandiyan Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_frontbuffer.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_frontbuffer.c b/drivers/gpu/drm/i915/intel_frontbuffer.c index fcfc217e754e..3a8d3d06c26a 100644 --- a/drivers/gpu/drm/i915/intel_frontbuffer.c +++ b/drivers/gpu/drm/i915/intel_frontbuffer.c @@ -79,6 +79,7 @@ void __intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, spin_unlock(&dev_priv->fb_tracking.lock); } + might_sleep(); intel_psr_invalidate(dev_priv, frontbuffer_bits); intel_edp_drrs_invalidate(dev_priv, frontbuffer_bits); intel_fbc_invalidate(dev_priv, frontbuffer_bits, origin); @@ -108,6 +109,7 @@ static void intel_frontbuffer_flush(struct drm_i915_private *dev_priv, if (!frontbuffer_bits) return; + might_sleep(); intel_edp_drrs_flush(dev_priv, frontbuffer_bits); intel_psr_flush(dev_priv, frontbuffer_bits, origin); intel_fbc_flush(dev_priv, frontbuffer_bits, origin); -- 2.14.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 5/6] drm/i915/dp: Remove redundant sleep after AUX transaction length check.
From: "Dhinakaran Pandiyan"
The core already takes care of the delay before retrying. The delay now
changes to (500, 600)us instead of (500 + 1000, 600 + 1500)us.
Cc: Rodrigo Vivi
Signed-off-by: Dhinakaran Pandiyan
Reviewed-by: David Weinehall
---
drivers/gpu/drm/i915/intel_dp.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 121ea34bc927..adbbe530520d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1227,14 +1227,6 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
if (recv_bytes == 0 || recv_bytes > 20) {
DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
recv_bytes);
- /*
-* FIXME: This patch was created on top of a series that
-* organize the retries at drm level. There EBUSY should
-* also take care for 1ms wait before retrying.
-* That aux retries re-org is still needed and after that is
-* merged we remove this sleep from here.
-*/
- usleep_range(1000, 1500);
ret = -EBUSY;
goto out;
}
--
2.14.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 3/6] drm/i915/psr: Extract PSR DPCD initialization and move it to intel_psr.c
From: "Dhinakaran Pandiyan"
intel_edp_init_dpcd() is cluttered with PSR specific DPCD checks and
intel_dp.c is huge.
No functional change intended.
v2: Rebased.
Cc: Rodrigo Vivi
Signed-off-by: Dhinakaran Pandiyan
Reviewed-by: David Weinehall
Acked-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 64 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 68
3 files changed, 70 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2c3eb90b9499..121ea34bc927 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3206,35 +3206,6 @@ intel_dp_get_link_status(struct intel_dp *intel_dp,
uint8_t link_status[DP_LINK_
DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
}
-static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
-{
- uint8_t psr_caps = 0;
-
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1)
- return false;
- return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
-}
-
-static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
-{
- uint8_t dprx = 0;
-
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
- &dprx) != 1)
- return false;
- return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
-}
-
-static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
-{
- uint8_t alpm_caps = 0;
-
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
- &alpm_caps) != 1)
- return false;
- return alpm_caps & DP_ALPM_CAP;
-}
-
/* These are source-specific values. */
uint8_t
intel_dp_voltage_max(struct intel_dp *intel_dp)
@@ -3785,40 +3756,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
- /* Check if the panel supports PSR */
- drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
-intel_dp->psr_dpcd,
-sizeof(intel_dp->psr_dpcd));
- if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
- dev_priv->psr.sink_support = true;
- DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
- }
-
- if (INTEL_GEN(dev_priv) >= 9 &&
- (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
- uint8_t frame_sync_cap;
-
- dev_priv->psr.sink_support = true;
- if (drm_dp_dpcd_readb(&intel_dp->aux,
- DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
- &frame_sync_cap) != 1)
- frame_sync_cap = 0;
- dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
- /* PSR2 needs frame sync as well */
- dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
- DRM_DEBUG_KMS("PSR2 %s on sink",
- dev_priv->psr.psr2_support ? "supported" : "not
supported");
-
- if (dev_priv->psr.psr2_support) {
- dev_priv->psr.y_cord_support =
- intel_dp_get_y_cord_status(intel_dp);
- dev_priv->psr.colorimetry_support =
- intel_dp_get_colorimetry_status(intel_dp);
- dev_priv->psr.alpm =
- intel_dp_get_alpm_status(intel_dp);
- }
-
- }
+ intel_psr_init_dpcd(intel_dp);
/*
* Read the eDP display control registers.
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8f38e584d375..652b11e788cc 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1866,6 +1866,7 @@ bool is_hdcp_supported(struct drm_i915_private *dev_priv,
enum port port);
/* intel_psr.c */
#define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
+void intel_psr_init_dpcd(struct intel_dp *intel_dp);
void intel_psr_enable(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
void intel_psr_disable(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 04430d4c99c9..8f8bcffd8d49 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -93,6 +93,74 @@ static void psr_aux_io_power_put(struct intel_dp *intel_dp)
intel_display_power_put(dev_priv, psr_aux_domain(intel_dp));
}
+static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
+{
+ uint8_t psr_caps = 0;
+
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1)
+ return fal
[Intel-gfx] [CI 1/6] drm/i915/psr: New power domain for AUX IO.
From: "Dhinakaran Pandiyan"
PSR on CNL requires AUX IO wells to be kept on and the existing AUX domain
for AUX-A enables DC_OFF well too. This is not required, so add a new
AUX_IO_A domain for AUX-A to allow DC states to remain enabled. Other AUX
channels re-use the existing AUX domains.
v4: Reword comment (Rodrigo and Ville)
Rename _get and _put functions to include aux_io substring(Rodrigo)
Remove unnecessary diff that got included.
v3: Extract aux domain selection into a function (Ville)
v2: Add AUX IO domain only for AUX-A
Rebased on top of Ville's AUX series.
Cc: Imre Deak
Cc: Rodrigo Vivi
Cc: Ville Syrjälä
Suggested-by: Imre Deak
Signed-off-by: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_display.h| 1 +
drivers/gpu/drm/i915/intel_psr.c| 41 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
3 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.h
b/drivers/gpu/drm/i915/intel_display.h
index f5733a2576e7..4e7418b345bc 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -186,6 +186,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_AUX_D,
POWER_DOMAIN_AUX_F,
+ POWER_DOMAIN_AUX_IO_A,
POWER_DOMAIN_GMBUS,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_GT_IRQ,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2ef374f936b9..04430d4c99c9 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -56,6 +56,43 @@
#include "intel_drv.h"
#include "i915_drv.h"
+static inline enum intel_display_power_domain
+psr_aux_domain(struct intel_dp *intel_dp)
+{
+ /* CNL HW requires corresponding AUX IOs to be powered up for PSR.
+* However, for non-A AUX ports the corresponding non-EDP transcoders
+* would have already enabled power well 2 and DC_OFF. This means we can
+* acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
+* specific AUX_IO reference without powering up any extra wells.
+* Note that PSR is enabled only on Port A even though this function
+* returns the correct domain for other ports too.
+*/
+ return intel_dp->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
+ intel_dp->aux_power_domain;
+}
+
+static void psr_aux_io_power_get(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *dev_priv =
to_i915(intel_dig_port->base.base.dev);
+
+ if (INTEL_GEN(dev_priv) < 10)
+ return;
+
+ intel_display_power_get(dev_priv, psr_aux_domain(intel_dp));
+}
+
+static void psr_aux_io_power_put(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *dev_priv =
to_i915(intel_dig_port->base.base.dev);
+
+ if (INTEL_GEN(dev_priv) < 10)
+ return;
+
+ intel_display_power_put(dev_priv, psr_aux_domain(intel_dp));
+}
+
static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
{
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -459,6 +496,8 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
u32 chicken;
+ psr_aux_io_power_get(intel_dp);
+
if (dev_priv->psr.psr2_support) {
chicken = PSR2_VSC_ENABLE_PROG_HEADER;
if (dev_priv->psr.y_cord_support)
@@ -617,6 +656,8 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
else
WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
}
+
+ psr_aux_io_power_put(intel_dp);
}
/**
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index b7924feb9f27..53ea564f971e 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -130,6 +130,8 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
return "AUX_D";
case POWER_DOMAIN_AUX_F:
return "AUX_F";
+ case POWER_DOMAIN_AUX_IO_A:
+ return "AUX_IO_A";
case POWER_DOMAIN_GMBUS:
return "GMBUS";
case POWER_DOMAIN_INIT:
@@ -1853,6 +1855,7 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
BIT_ULL(POWER_DOMAIN_INIT))
#define CNL_DISPLAY_AUX_A_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_AUX_IO_A) |\
BIT_ULL(POWER_DOMAIN_INIT))
#define CNL_DISPLAY_AUX_B_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
--
2.14.1
[Intel-gfx] [CI 6/6] drm/i915/dp: Move comment about hw timeout to the right place.
From: "Dhinakaran Pandiyan"
No functional change.
Signed-off-by: Dhinakaran Pandiyan
Reviewed-by: David Weinehall
---
drivers/gpu/drm/i915/intel_dp.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index adbbe530520d..debcbd868f5e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1174,14 +1174,14 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
DP_AUX_CH_CTL_TIME_OUT_ERROR |
DP_AUX_CH_CTL_RECEIVE_ERROR);
- if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
- continue;
-
/* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
* 400us delay required for errors and timeouts
* Timeout errors from the HW already meet this
* requirement so skip to next iteration
*/
+ if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
+ continue;
+
if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
usleep_range(400, 500);
continue;
--
2.14.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 4/6] drm/i915/psr: Check for the specific AUX_FRAME_SYNC cap bit.
From: "Dhinakaran Pandiyan"
The cap check should be specifically for bit 0 instead of any bit.
Cc: Rodrigo Vivi
Signed-off-by: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
Fixes: 474d1ec4a3d7 ("drm/i915/skl: Enabling PSR2 SU with frame sync")
---
drivers/gpu/drm/i915/intel_psr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 8f8bcffd8d49..b7cc6dd45c9e 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -144,7 +144,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
&frame_sync_cap) != 1)
frame_sync_cap = 0;
- dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
+ dev_priv->psr.aux_frame_sync = frame_sync_cap &
DP_AUX_FRAME_SYNC_CAP;
/* PSR2 needs frame sync as well */
dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
DRM_DEBUG_KMS("PSR2 %s on sink",
--
2.14.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v5,1/2] drm/i915: Move a bunch of workaround-related code to its own file
== Series Details == Series: series starting with [v5,1/2] drm/i915: Move a bunch of workaround-related code to its own file URL : https://patchwork.freedesktop.org/series/38891/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Move a bunch of workaround-related code to its own file +drivers/gpu/drm/i915/intel_workarounds.c:684:1: warning: no newline at end of file Commit: drm/i915: Split out functions for different kinds of workarounds -O:drivers/gpu/drm/i915/intel_workarounds.c:684:1: warning: no newline at end of file + ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 1/2] drm/i915: Move a bunch of workaround-related code to its own file
This has grown to be a sizable amount of code, so move it to
its own file before we try to refactor anything. For the moment,
we are leaving behind the WA BB code and the WAs that get applied
(incorrectly) in init_clock_gating, but we will deal with it later.
v2: Use intel_ prefix for code that deals with the hardware (Chris)
v3: Rebased
v4:
- Rebased
- New license header
v5:
- Rebased
- Added some organisational notes to the file (Chris)
Signed-off-by: Oscar Mateo
Cc: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 634
drivers/gpu/drm/i915/intel_lrc.c | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 3 -
drivers/gpu/drm/i915/intel_workarounds.c | 684 +++
drivers/gpu/drm/i915/intel_workarounds.h | 13 +
7 files changed, 701 insertions(+), 638 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_workarounds.c
create mode 100644 drivers/gpu/drm/i915/intel_workarounds.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 881d712..3b7330b 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -43,7 +43,8 @@ i915-y := i915_drv.o \
intel_csr.o \
intel_device_info.o \
intel_pm.o \
- intel_runtime_pm.o
+ intel_runtime_pm.o \
+ intel_workarounds.o
i915-$(CONFIG_COMPAT) += i915_ioc32.o
i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index ce7fcf5..88c41d4 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -826,640 +826,6 @@ void intel_engine_get_instdone(struct intel_engine_cs
*engine,
}
}
-static int wa_add(struct drm_i915_private *dev_priv,
- i915_reg_t addr,
- const u32 mask, const u32 val)
-{
- const u32 idx = dev_priv->workarounds.count;
-
- if (WARN_ON(idx >= I915_MAX_WA_REGS))
- return -ENOSPC;
-
- dev_priv->workarounds.reg[idx].addr = addr;
- dev_priv->workarounds.reg[idx].value = val;
- dev_priv->workarounds.reg[idx].mask = mask;
-
- dev_priv->workarounds.count++;
-
- return 0;
-}
-
-#define WA_REG(addr, mask, val) do { \
- const int r = wa_add(dev_priv, (addr), (mask), (val)); \
- if (r) \
- return r; \
- } while (0)
-
-#define WA_SET_BIT_MASKED(addr, mask) \
- WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
-
-#define WA_CLR_BIT_MASKED(addr, mask) \
- WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
-
-#define WA_SET_FIELD_MASKED(addr, mask, value) \
- WA_REG(addr, mask, _MASKED_FIELD(mask, value))
-
-static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
-i915_reg_t reg)
-{
- struct drm_i915_private *dev_priv = engine->i915;
- struct i915_workarounds *wa = &dev_priv->workarounds;
- const uint32_t index = wa->hw_whitelist_count[engine->id];
-
- if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
- return -EINVAL;
-
- I915_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
- i915_mmio_reg_offset(reg));
- wa->hw_whitelist_count[engine->id]++;
-
- return 0;
-}
-
-static int gen8_init_workarounds(struct intel_engine_cs *engine)
-{
- struct drm_i915_private *dev_priv = engine->i915;
-
- WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
-
- /* WaDisableAsyncFlipPerfMode:bdw,chv */
- WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
-
- /* WaDisablePartialInstShootdown:bdw,chv */
- WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
- PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
-
- /* Use Force Non-Coherent whenever executing a 3D context. This is a
-* workaround for for a possible hang in the unlikely event a TLB
-* invalidation occurs during a PSD flush.
-*/
- /* WaForceEnableNonCoherent:bdw,chv */
- /* WaHdcDisableFetchWhenMasked:bdw,chv */
- WA_SET_BIT_MASKED(HDC_CHICKEN0,
- HDC_DONOT_FETCH_MEM_WHEN_MASKED |
- HDC_FORCE_NON_COHERENT);
-
- /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
-* "The Hierarchical Z RAW Stall Optimization allows non-overlapping
-* polygons in the same 8x4 pixel/sample area to be processed without
-* stalling waiting for the earlier ones to write to Hierarchical Z
-* buffer."
-*
-* This optimization is off by default for BDW and CHV; turn it on.
-*/
- WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
-
- /* Wa4x4STCOptimizationDisable:bdw,chv */
- WA_SET_
[Intel-gfx] [PATCH v5 2/2] drm/i915: Split out functions for different kinds of workarounds
There are different kind of workarounds (those that modify registers that
live in the context image, those that modify global registers, those that
whitelist registers, etc...) and they have different requirements in terms
of where they are applied and how. Also, by splitting them apart, it should
be easier to decide where a new workaround should go.
v2:
- Add multiple MISSING_CASE
- Rebased
v3:
- Rename mmio_workarounds to gt_workarounds (Chris, Mika)
- Create empty placeholders for BDW and CHV GT WAs
- Rebased
v4: Rebased
v5:
- Rebased
- FORCE_TO_NONPRIV register exists since BDW, so make a path
for it to achieve universality, even if empty (Chris)
Signed-off-by: Oscar Mateo
Cc: Chris Wilson
Cc: Mika Kuoppala
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_gem.c | 3 +
drivers/gpu/drm/i915/i915_gem_context.c | 6 +
drivers/gpu/drm/i915/intel_lrc.c | 14 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 8 +-
drivers/gpu/drm/i915/intel_workarounds.c | 636 +++
drivers/gpu/drm/i915/intel_workarounds.h | 8 +-
6 files changed, 433 insertions(+), 242 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 14c855b..a702d57 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -35,6 +35,7 @@
#include "intel_drv.h"
#include "intel_frontbuffer.h"
#include "intel_mocs.h"
+#include "intel_workarounds.h"
#include "i915_gemfs.h"
#include
#include
@@ -5100,6 +5101,8 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
}
}
+ intel_gt_workarounds_apply(dev_priv);
+
i915_gem_init_swizzling(dev_priv);
/*
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index a73340ae..64df19d 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -90,6 +90,7 @@
#include
#include "i915_drv.h"
#include "i915_trace.h"
+#include "intel_workarounds.h"
#define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
@@ -452,11 +453,16 @@ static bool needs_preempt_context(struct drm_i915_private
*i915)
int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
{
struct i915_gem_context *ctx;
+ int ret;
/* Reassure ourselves we are only called once */
GEM_BUG_ON(dev_priv->kernel_context);
GEM_BUG_ON(dev_priv->preempt_context);
+ ret = intel_ctx_workarounds_init(dev_priv);
+ if (ret)
+ return ret;
+
INIT_LIST_HEAD(&dev_priv->contexts.list);
INIT_WORK(&dev_priv->contexts.free_work, contexts_free_worker);
init_llist_head(&dev_priv->contexts.free_list);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 2f372a0..f3cf7d7 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1555,6 +1555,10 @@ static int gen8_init_render_ring(struct intel_engine_cs
*engine)
if (ret)
return ret;
+ ret = intel_whitelist_workarounds_apply(engine);
+ if (ret)
+ return ret;
+
/* We need to disable the AsyncFlip performance optimisations in order
* to use MI_WAIT_FOR_EVENT within the CS. It should already be
* programmed to '1' on all products.
@@ -1565,7 +1569,7 @@ static int gen8_init_render_ring(struct intel_engine_cs
*engine)
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
- return init_workarounds_ring(engine);
+ return 0;
}
static int gen9_init_render_ring(struct intel_engine_cs *engine)
@@ -1576,7 +1580,11 @@ static int gen9_init_render_ring(struct intel_engine_cs
*engine)
if (ret)
return ret;
- return init_workarounds_ring(engine);
+ ret = intel_whitelist_workarounds_apply(engine);
+ if (ret)
+ return ret;
+
+ return 0;
}
static void reset_irq(struct intel_engine_cs *engine)
@@ -1924,7 +1932,7 @@ static int gen8_init_rcs_context(struct i915_request *rq)
{
int ret;
- ret = intel_ring_workarounds_emit(rq);
+ ret = intel_ctx_workarounds_emit(rq);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 36a00f2..c28c442 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -600,7 +600,7 @@ static int intel_rcs_ctx_init(struct i915_request *rq)
{
int ret;
- ret = intel_ring_workarounds_emit(rq);
+ ret = intel_ctx_workarounds_emit(rq);
if (ret != 0)
return ret;
@@ -618,6 +618,10 @@ static int init_render_ring(struct intel_engine_cs *engine)
if (ret)
return ret;
+ ret = intel_whitelist_workarounds_apply(engine);
+ if (ret)
+ return ret;
+
/* WaTime
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/6] Revert "drm: Use a flexible array member for blob property data"
== Series Details == Series: series starting with [1/6] Revert "drm: Use a flexible array member for blob property data" URL : https://patchwork.freedesktop.org/series/38886/ State : success == Summary == Test kms_plane: Subgroup plane-position-hole-dpms-pipe-b-planes: fail -> PASS (shard-apl) Test kms_vblank: Subgroup pipe-a-accuracy-idle: pass -> FAIL (shard-hsw) fdo#102583 Test kms_chv_cursor_fail: Subgroup pipe-a-64x64-top-edge: fail -> PASS (shard-apl) Test drv_suspend: Subgroup fence-restore-tiled2untiled: skip -> PASS (shard-hsw) Test perf: Subgroup oa-exponents: pass -> INCOMPLETE (shard-apl) fdo#102254 fdo#102583 https://bugs.freedesktop.org/show_bug.cgi?id=102583 fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254 shard-apltotal:3372 pass:1778 dwarn:1 dfail:0 fail:12 skip:1580 time:11945s shard-hswtotal:3465 pass:1767 dwarn:1 dfail:0 fail:3 skip:1693 time:11808s shard-snbtotal:3465 pass:1358 dwarn:1 dfail:0 fail:2 skip:2104 time:6669s Blacklisted hosts: shard-kbltotal:3368 pass:1890 dwarn:9 dfail:0 fail:14 skip:1452 time:8873s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8146/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] Revert "drm: Use a flexible array member for blob property data"
== Series Details == Series: series starting with [1/6] Revert "drm: Use a flexible array member for blob property data" URL : https://patchwork.freedesktop.org/series/38886/ State : success == Summary == Series 38886v1 series starting with [1/6] Revert "drm: Use a flexible array member for blob property data" https://patchwork.freedesktop.org/api/1.0/series/38886/revisions/1/mbox/ Test kms_chamelium: Subgroup dp-edid-read: fail -> PASS (fi-kbl-7500u) fdo#102505 Test kms_force_connector_basic: Subgroup force-connector-state: skip -> PASS (fi-snb-2520m) Subgroup force-edid: skip -> PASS (fi-snb-2520m) Subgroup force-load-detect: skip -> PASS (fi-snb-2520m) Subgroup prune-stale-modes: skip -> PASS (fi-snb-2520m) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: pass -> INCOMPLETE (fi-snb-2520m) fdo#103713 fdo#102505 https://bugs.freedesktop.org/show_bug.cgi?id=102505 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:413s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:425s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:374s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:492s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:283s fi-bxt-dsi total:246 pass:219 dwarn:0 dfail:0 fail:0 skip:26 fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:480s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:464s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:458s fi-cfl-8700k total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:395s fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:556s fi-cnl-y3total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:585s fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:421s fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:280s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:511s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:386s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:410s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:453s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:411s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:450s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:490s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:450s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:494s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:589s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:425s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:504s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:521s fi-skl-6700k2total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:486s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:467s fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:408s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:429s fi-snb-2520m total:245 pass:211 dwarn:0 dfail:0 fail:0 skip:33 fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:388s 316ba650abe6c1e8ac2f812ff21eee5771546ba1 drm-tip: 2018y-02m-23d-16h-41m-52s UTC integration manifest 3d63de51ea1c drm/i915: Use drm_color_lut_size() c6dfc36578ff drm/i915: Remove the blob->data casts 94f4747acf8b drm: Introduce drm_color_lut_size() 94c2358600da drm: Verify gamma/degamma LUT size 01ecd2176c1f drm: Remove now pointelss blob->data casts fc76a0f5d1c0 Revert "drm: Use a flexible array member for blob property data" == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8146/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/6] drm: Remove now pointelss blob->data casts
From: Ville Syrjälä
Now that blob->data is void* again we don't need the casts anymore.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_atomic.c| 3 +--
drivers/gpu/drm/drm_atomic_helper.c | 2 +-
drivers/gpu/drm/drm_edid.c | 3 +--
drivers/gpu/drm/drm_fb_helper.c | 2 +-
drivers/gpu/drm/drm_plane.c | 2 +-
5 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 46733d534587..8945357212ba 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -391,8 +391,7 @@ int drm_atomic_set_mode_prop_for_crtc(struct drm_crtc_state
*state,
if (blob) {
if (blob->length != sizeof(struct drm_mode_modeinfo) ||
drm_mode_convert_umode(state->crtc->dev, &state->mode,
- (const struct drm_mode_modeinfo *)
- blob->data))
+ blob->data))
return -EINVAL;
state->mode_blob = drm_property_blob_get(blob);
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm/drm_atomic_helper.c
index ae3cbfe9e01c..6211a1b20405 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -3816,7 +3816,7 @@ int drm_atomic_helper_legacy_gamma_set(struct drm_crtc
*crtc,
}
/* Prepare GAMMA_LUT with the legacy values. */
- blob_data = (struct drm_color_lut *) blob->data;
+ blob_data = blob->data;
for (i = 0; i < size; i++) {
blob_data[i].red = red[i];
blob_data[i].green = green[i];
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 788fee4b4bf9..134069f36482 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1575,8 +1575,7 @@ struct edid *drm_do_get_edid(struct drm_connector
*connector,
struct edid *override = NULL;
if (connector->override_edid)
- override = drm_edid_duplicate((const struct edid *)
- connector->edid_blob_ptr->data);
+ override = drm_edid_duplicate(connector->edid_blob_ptr->data);
if (!override)
override = drm_load_edid_firmware(connector);
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 035784ddd133..0646b108030b 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -1351,7 +1351,7 @@ static struct drm_property_blob
*setcmap_new_gamma_lut(struct drm_crtc *crtc,
if (IS_ERR(gamma_lut))
return gamma_lut;
- lut = (struct drm_color_lut *)gamma_lut->data;
+ lut = gamma_lut->data;
if (cmap->start || cmap->len != size) {
u16 *r = crtc->gamma_store;
u16 *g = r + crtc->gamma_size;
diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index 09de6ecb3968..9851616cf0f3 100644
--- a/drivers/gpu/drm/drm_plane.c
+++ b/drivers/gpu/drm/drm_plane.c
@@ -104,7 +104,7 @@ static int create_in_format_blob(struct drm_device *dev,
struct drm_plane *plane
if (IS_ERR(blob))
return -1;
- blob_data = (struct drm_format_modifier_blob *)blob->data;
+ blob_data = blob->data;
blob_data->version = FORMAT_BLOB_CURRENT;
blob_data->count_formats = plane->format_count;
blob_data->formats_offset = sizeof(struct drm_format_modifier_blob);
--
2.13.6
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 6/6] drm/i915: Use drm_color_lut_size()
From: Ville Syrjälä Avoid all the sizeof(drm_color_lut) business by using drm_color_lut_size() to convert the blob length into number of LUT entries. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_color.c | 14 ++ 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index e8ede69754a9..029c2c931fab 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -39,7 +39,7 @@ #define CTM_COEFF_NEGATIVE(coeff) (((coeff) & CTM_COEFF_SIGN) != 0) #define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1)) -#define LEGACY_LUT_LENGTH (sizeof(struct drm_color_lut) * 256) +#define LEGACY_LUT_LENGTH 256 /* Post offset values for RGB->YCBCR conversion */ #define POSTOFF_RGB_TO_YUV_HI 0x800 @@ -79,7 +79,7 @@ static bool crtc_state_is_legacy_gamma(struct drm_crtc_state *state) return !state->degamma_lut && !state->ctm && state->gamma_lut && - state->gamma_lut->length == LEGACY_LUT_LENGTH; + drm_color_lut_size(state->gamma_lut) == LEGACY_LUT_LENGTH; } /* @@ -611,19 +611,17 @@ int intel_color_check(struct drm_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(crtc->dev); size_t gamma_length, degamma_length; - degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size * - sizeof(struct drm_color_lut); - gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size * - sizeof(struct drm_color_lut); + degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size; + gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size; /* * We allow both degamma & gamma luts at the right size or * NULL. */ if ((!crtc_state->degamma_lut || -crtc_state->degamma_lut->length == degamma_length) && +drm_color_lut_size(crtc_state->degamma_lut) == degamma_length) && (!crtc_state->gamma_lut || -crtc_state->gamma_lut->length == gamma_length)) +drm_color_lut_size(crtc_state->gamma_lut) == gamma_length)) return 0; /* -- 2.13.6 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/6] drm: Introduce drm_color_lut_size()
From: Ville Syrjälä
Provide a small helper to convert the blob length in bytes
to the number of LUT entries.
Signed-off-by: Ville Syrjälä
---
include/drm/drm_color_mgmt.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
index 03a59cbce621..7ddf4457f3c1 100644
--- a/include/drm/drm_color_mgmt.h
+++ b/include/drm/drm_color_mgmt.h
@@ -37,4 +37,9 @@ void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
int drm_mode_crtc_set_gamma_size(struct drm_crtc *crtc,
int gamma_size);
+static inline int drm_color_lut_size(const struct drm_property_blob *blob)
+{
+ return blob->length / sizeof(struct drm_color_lut);
+}
+
#endif
--
2.13.6
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/6] drm/i915: Remove the blob->data casts
From: Ville Syrjälä
Now that blob->data is void* again we don't need to cast it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_color.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index a383d993b844..e8ede69754a9 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -144,8 +144,7 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state
*crtc_state)
i9xx_load_ycbcr_conversion_matrix(intel_crtc);
return;
} else if (crtc_state->ctm) {
- struct drm_color_ctm *ctm =
- (struct drm_color_ctm *)crtc_state->ctm->data;
+ struct drm_color_ctm *ctm = crtc_state->ctm->data;
uint64_t input[9] = { 0, };
if (intel_crtc_state->limited_color_range) {
@@ -254,8 +253,7 @@ static void cherryview_load_csc_matrix(struct
drm_crtc_state *state)
uint32_t mode;
if (state->ctm) {
- struct drm_color_ctm *ctm =
- (struct drm_color_ctm *) state->ctm->data;
+ struct drm_color_ctm *ctm = state->ctm->data;
uint16_t coeffs[9] = { 0, };
int i;
@@ -322,7 +320,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
}
if (blob) {
- struct drm_color_lut *lut = (struct drm_color_lut *) blob->data;
+ struct drm_color_lut *lut = blob->data;
for (i = 0; i < 256; i++) {
uint32_t word =
(drm_color_lut_extract(lut[i].red, 8) << 16) |
@@ -392,8 +390,7 @@ static void bdw_load_degamma_lut(struct drm_crtc_state
*state)
PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
if (state->degamma_lut) {
- struct drm_color_lut *lut =
- (struct drm_color_lut *) state->degamma_lut->data;
+ struct drm_color_lut *lut = state->degamma_lut->data;
for (i = 0; i < lut_size; i++) {
uint32_t word =
@@ -427,8 +424,7 @@ static void bdw_load_gamma_lut(struct drm_crtc_state
*state, u32 offset)
offset);
if (state->gamma_lut) {
- struct drm_color_lut *lut =
- (struct drm_color_lut *) state->gamma_lut->data;
+ struct drm_color_lut *lut = state->gamma_lut->data;
for (i = 0; i < lut_size; i++) {
uint32_t word =
@@ -560,7 +556,7 @@ static void cherryview_load_luts(struct drm_crtc_state
*state)
}
if (state->degamma_lut) {
- lut = (struct drm_color_lut *) state->degamma_lut->data;
+ lut = state->degamma_lut->data;
lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
for (i = 0; i < lut_size; i++) {
/* Write LUT in U0.14 format. */
@@ -575,7 +571,7 @@ static void cherryview_load_luts(struct drm_crtc_state
*state)
}
if (state->gamma_lut) {
- lut = (struct drm_color_lut *) state->gamma_lut->data;
+ lut = state->gamma_lut->data;
lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
for (i = 0; i < lut_size; i++) {
/* Write LUT in U0.10 format. */
--
2.13.6
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/6] drm: Verify gamma/degamma LUT size
From: Ville Syrjälä
While we want to potentially support multiple different gamma/degamma
LUT sizes we can (and should) at least check that the blob length
is a multiple of the LUT entry size.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_atomic.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 8945357212ba..933edec0299d 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -413,6 +413,7 @@ drm_atomic_replace_property_blob_from_id(struct drm_device
*dev,
struct drm_property_blob **blob,
uint64_t blob_id,
ssize_t expected_size,
+ssize_t expected_size_mod,
bool *replaced)
{
struct drm_property_blob *new_blob = NULL;
@@ -422,7 +423,13 @@ drm_atomic_replace_property_blob_from_id(struct drm_device
*dev,
if (new_blob == NULL)
return -EINVAL;
- if (expected_size > 0 && expected_size != new_blob->length) {
+ if (expected_size > 0 &&
+ new_blob->length != expected_size) {
+ drm_property_blob_put(new_blob);
+ return -EINVAL;
+ }
+ if (expected_size_mod > 0 &&
+ new_blob->length % expected_size_mod != 0) {
drm_property_blob_put(new_blob);
return -EINVAL;
}
@@ -470,7 +477,7 @@ int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
ret = drm_atomic_replace_property_blob_from_id(dev,
&state->degamma_lut,
val,
- -1,
+ -1, sizeof(struct drm_color_lut),
&replaced);
state->color_mgmt_changed |= replaced;
return ret;
@@ -478,7 +485,7 @@ int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
ret = drm_atomic_replace_property_blob_from_id(dev,
&state->ctm,
val,
- sizeof(struct drm_color_ctm),
+ sizeof(struct drm_color_ctm), -1,
&replaced);
state->color_mgmt_changed |= replaced;
return ret;
@@ -486,7 +493,7 @@ int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
ret = drm_atomic_replace_property_blob_from_id(dev,
&state->gamma_lut,
val,
- -1,
+ -1, sizeof(struct drm_color_lut),
&replaced);
state->color_mgmt_changed |= replaced;
return ret;
--
2.13.6
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/6] Revert "drm: Use a flexible array member for blob property data"
From: Ville Syrjälä
Using a flexible array for the blob data was a mistake by me. It
forces all users of the blob data to cast blob->data to something
else. void* is clearly superior so let's go back to the original
scheme.
Not a clean revert as the code has moved.
This reverts commit d63f5e6bf6f2a1573ea39c9937cdf5ab0b3a4b77.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_property.c | 1 +
include/drm/drm_property.h | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_property.c b/drivers/gpu/drm/drm_property.c
index bae50e6b819d..0f6620fea3de 100644
--- a/drivers/gpu/drm/drm_property.c
+++ b/drivers/gpu/drm/drm_property.c
@@ -550,6 +550,7 @@ drm_property_create_blob(struct drm_device *dev, size_t
length,
/* This must be explicitly initialised, so we can safely call list_del
* on it in the removal handler, even if it isn't in a file list. */
INIT_LIST_HEAD(&blob->head_file);
+ blob->data = (void *)blob + sizeof(*blob);
blob->length = length;
blob->dev = dev;
diff --git a/include/drm/drm_property.h b/include/drm/drm_property.h
index 8a522b4bed40..265fd1f2e112 100644
--- a/include/drm/drm_property.h
+++ b/include/drm/drm_property.h
@@ -209,7 +209,7 @@ struct drm_property_blob {
struct list_head head_global;
struct list_head head_file;
size_t length;
- unsigned char data[];
+ void *data;
};
struct drm_prop_enum_list {
--
2.13.6
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [igt CI] Iterate over physical engines
We current have a single for_each_engine() iterator which we use to
generate both a set of uABI engines and a set of physical engines.
Determining what uABI ring-id corresponds to an actual HW engine is
tricky, so pull that out to a library function and introduce
for_each_physical_engine() for cases where we want to issue requests
once on each HW ring (avoiding aliasing issues).
v2: Remember can_store_dword for gem_sync
v3: Find more open-coded for_each_physical
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
lib/igt_gt.c | 23 +
lib/igt_gt.h | 9
tests/amdgpu/amd_prime.c | 6 +--
tests/drv_hangman.c| 20 ++--
tests/gem_busy.c | 31 ++--
tests/gem_concurrent_all.c | 2 +-
tests/gem_ctx_create.c | 5 +-
tests/gem_ctx_thrash.c | 61 +++---
tests/gem_exec_async.c | 15 +++---
tests/gem_exec_await.c | 17 +--
tests/gem_exec_capture.c | 2 +-
tests/gem_exec_create.c| 17 +--
tests/gem_exec_fence.c | 16 ++
tests/gem_exec_gttfill.c | 16 +-
tests/gem_exec_latency.c | 19 +++
tests/gem_exec_nop.c | 32 ++--
tests/gem_exec_parallel.c | 15 +-
tests/gem_exec_reloc.c | 2 +-
tests/gem_exec_schedule.c | 31
tests/gem_exec_store.c | 2 +-
tests/gem_exec_suspend.c | 20 ++--
tests/gem_exec_whisper.c | 15 +-
tests/gem_ring_sync_loop.c | 2 +-
tests/gem_spin_batch.c | 5 +-
tests/gem_sync.c | 123 -
25 files changed, 124 insertions(+), 382 deletions(-)
diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index f70fcb92..e630550b 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -660,3 +660,26 @@ bool gem_has_engine(int gem_fd,
gem_class_instance_to_eb_flags(gem_fd, class,
instance));
}
+
+bool gem_ring_is_physical_engine(int fd, unsigned ring)
+{
+ if (ring == I915_EXEC_DEFAULT)
+ return false;
+
+ /* BSD uses an extra flag to chose between aliasing modes */
+ if ((ring & 63) == I915_EXEC_BSD) {
+ bool explicit_bsd = ring & (3 << 13);
+ bool has_bsd2 = gem_has_bsd2(fd);
+ return explicit_bsd ? has_bsd2 : !has_bsd2;
+ }
+
+ return true;
+}
+
+bool gem_ring_has_physical_engine(int fd, unsigned ring)
+{
+ if (!gem_ring_is_physical_engine(fd, ring))
+ return false;
+
+ return gem_has_ring(fd, ring);
+}
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 68592410..4d9d1aa0 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -81,6 +81,15 @@ extern const struct intel_execution_engine {
e__++) \
for_if (gem_has_ring(fd__, flags__ = e__->exec_id | e__->flags))
+#define for_each_physical_engine(fd__, flags__) \
+ for (const struct intel_execution_engine *e__ =
intel_execution_engines;\
+e__->name; \
+e__++) \
+ for_if (gem_ring_has_physical_engine(fd__, flags__ =
e__->exec_id | e__->flags))
+
+bool gem_ring_is_physical_engine(int fd, unsigned int ring);
+bool gem_ring_has_physical_engine(int fd, unsigned int ring);
+
bool gem_can_store_dword(int fd, unsigned int engine);
extern const struct intel_execution_engine2 {
diff --git a/tests/amdgpu/amd_prime.c b/tests/amdgpu/amd_prime.c
index b2f326b4..bb68ccf3 100644
--- a/tests/amdgpu/amd_prime.c
+++ b/tests/amdgpu/amd_prime.c
@@ -179,12 +179,8 @@ static void i915_to_amd(int i915, int amd,
amdgpu_device_handle device)
struct cork c;
nengine = 0;
- for_each_engine(i915, engine) {
- if (engine == 0)
- continue;
-
+ for_each_physical_engine(i915, engine)
engines[nengine++] = engine;
- }
igt_require(nengine);
memset(obj, 0, sizeof(obj));
diff --git a/tests/drv_hangman.c b/tests/drv_hangman.c
index 40c82257..38cb20c3 100644
--- a/tests/drv_hangman.c
+++ b/tests/drv_hangman.c
@@ -183,8 +183,6 @@ static void test_error_state_capture(unsigned ring_id,
igt_hang_t hang;
uint64_t offset;
- igt_require(gem_has_ring(device, ring_id));
-
clear_error_state();
hang = igt_hang_ctx(device, 0, ring_id, HANG_ALLOW_CAPTURE, &offset);
@@ -255,23 +253,11 @@ igt_main
if (e->exec_id == 0)
continue;
- /*
-* If the device has 2 BSD rings then due to obtuse aliasing
-* in the API, we can not determine which ring I915_EXEC_BSD
-* will map to, and so must skip the test; as the matching name
-* may be either bsd or bsd2 depending on the kernel/test
-* ordering.
-*
-* Here we are not checking that executing on every ABI engine
-
[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/perf: fix b counter register whitelist on haswell
== Series Details == Series: drm/i915/perf: fix b counter register whitelist on haswell URL : https://patchwork.freedesktop.org/series/38875/ State : warning == Summary == Test drv_suspend: Subgroup fence-restore-tiled2untiled: pass -> SKIP (shard-snb) Test kms_flip: Subgroup plain-flip-ts-check: fail -> PASS (shard-hsw) fdo#100368 +1 Test perf: Subgroup blocking: fail -> PASS (shard-hsw) fdo#102252 Test kms_chv_cursor_fail: Subgroup pipe-b-64x64-bottom-edge: dmesg-warn -> PASS (shard-snb) fdo#105185 Test kms_pipe_crc_basic: Subgroup nonblocking-crc-pipe-b-frame-sequence: fail -> PASS (shard-apl) fdo#103481 Test kms_sysfs_edid_timing: pass -> WARN (shard-apl) fdo#100047 fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#105185 https://bugs.freedesktop.org/show_bug.cgi?id=105185 fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481 fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047 shard-apltotal:3465 pass:1820 dwarn:1 dfail:0 fail:12 skip:1631 time:12231s shard-hswtotal:3465 pass:1767 dwarn:1 dfail:0 fail:3 skip:1693 time:11782s shard-snbtotal:3465 pass:1357 dwarn:1 dfail:0 fail:2 skip:2105 time:6622s Blacklisted hosts: shard-kbltotal:3386 pass:1917 dwarn:1 dfail:0 fail:14 skip:1452 time:9103s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8145/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/uc: Start preparing GuC/HuC for reset
On 23/02/18 06:04, Michal Wajdeczko wrote:
Right after GPU reset there will be a small window of time during which
some of GuC/HuC fields will still show state before reset. Let's start
to fix that by sanitizing firmware status as we will use it shortly.
v2: s/reset_prepare/prepare_to_reset (Michel)
don't forget about gem_sanitize path (Daniele)
Suggested-by: Daniele Ceraolo Spurio
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Sagar Arun Kamble
Cc: Chris Wilson
Cc: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem.c| 5 -
drivers/gpu/drm/i915/intel_guc.h | 5 +
drivers/gpu/drm/i915/intel_huc.h | 5 +
drivers/gpu/drm/i915/intel_uc.c| 14 ++
drivers/gpu/drm/i915/intel_uc.h| 1 +
drivers/gpu/drm/i915/intel_uc_fw.h | 6 ++
6 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 14c855b..ae2c4ba 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2981,6 +2981,7 @@ int i915_gem_reset_prepare(struct drm_i915_private
*dev_priv)
}
i915_gem_revoke_fences(dev_priv);
+ intel_uc_prepare_to_reset(dev_priv);
return err;
}
@@ -4881,8 +4882,10 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
* it may impact the display and we are uncertain about the stability
* of the reset, so this could be applied to even earlier gen.
*/
- if (INTEL_GEN(i915) >= 5 && intel_has_gpu_reset(i915))
+ if (INTEL_GEN(i915) >= 5 && intel_has_gpu_reset(i915)) {
+ intel_uc_prepare_to_reset(i915);
This leaves the status with an incorrect value if we boot with
i915.reset=0, but I think this is still the right place to add this in.
There are several things with GuC that are going to break if we use
reset=0 (e.g. doorbell cleanup) so I wouldn't consider this a
regression, but we might want to start sanitizing the modparams to not
allow reset=0 with GuC.
Reviewed-by: Daniele Ceraolo Spurio
Daniele
WARN_ON(intel_gpu_reset(i915, ALL_ENGINES));
+ }
}
int i915_gem_suspend(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 52856a9..0f6adb1 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -132,4 +132,9 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)
struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
+static inline void intel_guc_prepare_to_reset(struct intel_guc *guc)
+{
+ intel_uc_fw_prepare_to_reset(&guc->fw);
+}
+
#endif
diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
index 40039db..96e24f9 100644
--- a/drivers/gpu/drm/i915/intel_huc.h
+++ b/drivers/gpu/drm/i915/intel_huc.h
@@ -38,4 +38,9 @@ struct intel_huc {
int intel_huc_init_hw(struct intel_huc *huc);
int intel_huc_auth(struct intel_huc *huc);
+static inline void intel_huc_prepare_to_reset(struct intel_huc *huc)
+{
+ intel_uc_fw_prepare_to_reset(&huc->fw);
+}
+
#endif
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 9f1bac6..8042d4b 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -445,3 +445,17 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
if (USES_GUC_SUBMISSION(dev_priv))
gen9_disable_guc_interrupts(dev_priv);
}
+
+void intel_uc_prepare_to_reset(struct drm_i915_private *i915)
+{
+ struct intel_huc *huc = &i915->huc;
+ struct intel_guc *guc = &i915->guc;
+
+ if (!USES_GUC(i915))
+ return;
+
+ GEM_BUG_ON(!HAS_GUC(i915));
+
+ intel_huc_prepare_to_reset(huc);
+ intel_guc_prepare_to_reset(guc);
+}
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index f2984e0..7a8ae58 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -39,6 +39,7 @@
void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
int intel_uc_init(struct drm_i915_private *dev_priv);
void intel_uc_fini(struct drm_i915_private *dev_priv);
+void intel_uc_prepare_to_reset(struct drm_i915_private *dev_priv);
static inline bool intel_uc_is_using_guc(void)
{
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h
b/drivers/gpu/drm/i915/intel_uc_fw.h
index d5fd460..f1ee653 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.h
+++ b/drivers/gpu/drm/i915/intel_uc_fw.h
@@ -115,6 +115,12 @@ static inline bool intel_uc_fw_is_selected(struct
intel_uc_fw *uc_fw)
return uc_fw->path != NULL;
}
+static inline void intel_uc_fw_prepare_to_reset(struct intel_uc_fw *uc_fw)
+{
+ if (uc_fw->load_status == INTEL_UC_FIRMWARE_SUCCESS)
+ uc_fw->load_status = INTEL_UC_FIRMWARE_PENDING;
+}
+
void intel_uc_fw_fetch(s
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/perf: fix b counter register whitelist on haswell
== Series Details == Series: drm/i915/perf: fix b counter register whitelist on haswell URL : https://patchwork.freedesktop.org/series/38875/ State : success == Summary == Series 38875v1 drm/i915/perf: fix b counter register whitelist on haswell https://patchwork.freedesktop.org/api/1.0/series/38875/revisions/1/mbox/ Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-c: incomplete -> PASS (fi-bxt-dsi) fdo#103927 Test prime_vgem: Subgroup basic-fence-flip: fail -> PASS (fi-skl-6260u) fdo#104008 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:418s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:423s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:371s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:482s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:283s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:478s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:484s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:463s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:455s fi-cfl-8700k total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:393s fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:572s fi-cnl-y3total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:579s fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:416s fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:283s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:508s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:385s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:409s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:445s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:410s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:448s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:488s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:451s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:491s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:586s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:422s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:501s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:516s fi-skl-6700k2total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:487s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:477s fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:405s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:429s fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:517s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:388s 7809e95bb1b76402415b21fc14b6ba9e5f98fd76 drm-tip: 2018y-02m-23d-15h-30m-27s UTC integration manifest 3f6d67d8c014 drm/i915/perf: fix b counter register whitelist on haswell == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8145/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] drm/uapi: The ctm matrix uses sign-magnitude representation
On Fri, Feb 23, 2018 at 11:26:41AM -0500, Harry Wentland wrote:
> On 2018-02-22 04:42 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The documentation for the ctm matrix suggests a two's complement
> > format, but at least the i915 implementation is using sign-magnitude
> > instead. And looks like malidp is doing the same. Change the docs
> > to match the current implementation, and change the type from __s64
> > to __u64 to drive the point home.
> >
> > Cc: dri-de...@lists.freedesktop.org
> > Cc: Mihail Atanassov
> > Cc: Liviu Dudau
> > Cc: Brian Starkey
> > Cc: Mali DP Maintainers
> > Cc: Johnson Lin
> > Cc: Uma Shankar
> > Cc: Shashank Sharma
> > Signed-off-by: Ville Syrjälä
>
> Good clarification. Our new CTM implementation (1) actually assumed two's
> complement but nobody's using it yet, so we'll patch it to convert.
Nice. Looks like we caught this just in time.
>
> Reviewed-by: Harry Wentland
>
> (1) https://patchwork.freedesktop.org/patch/204005/
>
> Harry
>
> > ---
> > include/uapi/drm/drm_mode.h | 7 +--
> > 1 file changed, 5 insertions(+), 2 deletions(-)
> >
> > diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
> > index 2c575794fb52..b5d7d9e0eff5 100644
> > --- a/include/uapi/drm/drm_mode.h
> > +++ b/include/uapi/drm/drm_mode.h
> > @@ -598,8 +598,11 @@ struct drm_mode_crtc_lut {
> > };
> >
> > struct drm_color_ctm {
> > - /* Conversion matrix in S31.32 format. */
> > - __s64 matrix[9];
> > + /*
> > +* Conversion matrix in S31.32 sign-magnitude
> > +* (not two's complement!) format.
> > +*/
> > + __u64 matrix[9];
> > };
> >
> > struct drm_color_lut {
> >
--
Ville Syrjälä
Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/preemption: Allow preemption between submission ports
Quoting Mika Kuoppala (2018-02-23 15:18:17) > Chris Wilson writes: > > > Sometimes we need to boost the priority of an in-flight request, which > > may lead to the situation where the second submission port then contains > > a higher priority context than the first and so we need to inject a > > preemption event. To do so we must always check inside > > execlists_dequeue() whether there is a priority inversion between the > > ports themselves as well as the head of the priority sorted queue, and we > > cannot just skip dequeuing if the queue is empty. > > > > Signed-off-by: Chris Wilson > > Cc: Michał Winiarski > > Cc: Michel Thierry > > Cc: Mika Kuoppala > > Cc: Tvrtko Ursulin > > Reviewed-by: Mika Kuoppala Added detail to @queue_priority and pushed. Thanks for the review! -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] drm/uapi: The ctm matrix uses sign-magnitude representation
On 2018-02-22 04:42 PM, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The documentation for the ctm matrix suggests a two's complement
> format, but at least the i915 implementation is using sign-magnitude
> instead. And looks like malidp is doing the same. Change the docs
> to match the current implementation, and change the type from __s64
> to __u64 to drive the point home.
>
> Cc: dri-de...@lists.freedesktop.org
> Cc: Mihail Atanassov
> Cc: Liviu Dudau
> Cc: Brian Starkey
> Cc: Mali DP Maintainers
> Cc: Johnson Lin
> Cc: Uma Shankar
> Cc: Shashank Sharma
> Signed-off-by: Ville Syrjälä
Good clarification. Our new CTM implementation (1) actually assumed two's
complement but nobody's using it yet, so we'll patch it to convert.
Reviewed-by: Harry Wentland
(1) https://patchwork.freedesktop.org/patch/204005/
Harry
> ---
> include/uapi/drm/drm_mode.h | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
> index 2c575794fb52..b5d7d9e0eff5 100644
> --- a/include/uapi/drm/drm_mode.h
> +++ b/include/uapi/drm/drm_mode.h
> @@ -598,8 +598,11 @@ struct drm_mode_crtc_lut {
> };
>
> struct drm_color_ctm {
> - /* Conversion matrix in S31.32 format. */
> - __s64 matrix[9];
> + /*
> + * Conversion matrix in S31.32 sign-magnitude
> + * (not two's complement!) format.
> + */
> + __u64 matrix[9];
> };
>
> struct drm_color_lut {
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/perf: fix b counter register whitelist on haswell
This register is incorrectly listed as SNB/IVB only in the documentation. It turns out it's useful for one configuration on HSW (Compute Metrics Basic). Fixes: f89823c2122 "drm/i915/perf: Implement I915_PERF_ADD/REMOVE_CONFIG interface" Cc: Stable Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_perf.c | 3 ++- drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 2741b1bc7095..fbe3ac1e3e86 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -3019,7 +3019,8 @@ static bool gen7_is_valid_b_counter_addr(struct drm_i915_private *dev_priv, u32 (addr >= i915_mmio_reg_offset(OAREPORTTRIG1) && addr <= i915_mmio_reg_offset(OAREPORTTRIG8)) || (addr >= i915_mmio_reg_offset(OACEC0_0) && -addr <= i915_mmio_reg_offset(OACEC7_1)); +addr <= i915_mmio_reg_offset(OACEC7_1)) || + addr == i915_mmio_reg_offset(NOASELECT); } static bool gen7_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8c12ee2f89a9..4e991b69b117 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1155,6 +1155,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define HSW_MBVID2_MISR0 _MMIO(0x9EC0) +#define NOASELECT _MMIO(0x236C) + /* NOA (Gen8+) */ #define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4) -- 2.16.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for Enabling VDSC in i915 driver for GLK
== Series Details == Series: Enabling VDSC in i915 driver for GLK URL : https://patchwork.freedesktop.org/series/38874/ State : failure == Summary == CHK include/config/kernel.release CHK include/generated/uapi/linux/version.h CHK include/generated/utsrelease.h CHK include/generated/bounds.h CHK include/generated/timeconst.h CHK include/generated/asm-offsets.h CALLscripts/checksyscalls.sh DESCEND objtool CHK scripts/mod/devicetable-offsets.h CHK include/generated/compile.h CHK kernel/config_data.h CC [M] drivers/gpu/drm/i915/intel_vdsc.o drivers/gpu/drm/i915/intel_vdsc.c: In function ‘intel_dsc_enable’: drivers/gpu/drm/i915/intel_vdsc.c:1164:3: error: ‘dsc_type2’ may be used uninitialized in this function [-Werror=maybe-uninitialized] configure_dsc_params_for_dsc_controller(encoder, pipe_config, ^ &dsc_regs, dsc_type2); ~ drivers/gpu/drm/i915/intel_vdsc.c:1160:2: error: ‘dsc_type1’ may be used uninitialized in this function [-Werror=maybe-uninitialized] configure_dsc_params_for_dsc_controller(encoder, pipe_config, ^ &dsc_regs, dsc_type1); ~ cc1: all warnings being treated as errors scripts/Makefile.build:316: recipe for target 'drivers/gpu/drm/i915/intel_vdsc.o' failed make[4]: *** [drivers/gpu/drm/i915/intel_vdsc.o] Error 1 scripts/Makefile.build:575: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:575: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:575: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1048: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/uc: Introduce intel_uc_suspend|resume
== Series Details == Series: series starting with [1/2] drm/i915/uc: Introduce intel_uc_suspend|resume URL : https://patchwork.freedesktop.org/series/38867/ State : failure == Summary == Test kms_cursor_crc: Subgroup cursor-64x64-suspend: incomplete -> PASS (shard-hsw) fdo#103540 Test gem_exec_schedule: Subgroup smoketest-render: pass -> FAIL (shard-apl) Subgroup smoketest-all: pass -> FAIL (shard-apl) Test drv_selftest: Subgroup live_guc: pass -> DMESG-WARN (shard-apl) Test drv_missed_irq: pass -> SKIP (shard-apl) Test kms_flip: Subgroup 2x-modeset-vs-vblank-race-interruptible: fail -> PASS (shard-hsw) fdo#103060 +1 Test drv_suspend: Subgroup debugfs-reader: pass -> SKIP (shard-snb) fdo#102365 pass -> SKIP (shard-hsw) Test kms_chv_cursor_fail: Subgroup pipe-b-256x256-left-edge: pass -> DMESG-WARN (shard-snb) fdo#105185 Test gem_exec_suspend: Subgroup basic-s3-devices: pass -> INCOMPLETE (shard-apl) Test perf: Subgroup gen8-unprivileged-single-ctx-counters: pass -> FAIL (shard-apl) fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365 fdo#105185 https://bugs.freedesktop.org/show_bug.cgi?id=105185 shard-apltotal:3334 pass:1749 dwarn:2 dfail:0 fail:19 skip:1561 time:11975s shard-hswtotal:3465 pass:1767 dwarn:1 dfail:0 fail:2 skip:1694 time:11670s shard-snbtotal:3465 pass:1355 dwarn:2 dfail:0 fail:3 skip:2105 time:6607s Blacklisted hosts: shard-kbltotal:3400 pass:1901 dwarn:2 dfail:1 fail:29 skip:1465 time:9367s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8143/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC] perf: Allow fine-grained PMU access control
Hi, On 19/01/2018 17:10, Tvrtko Ursulin wrote: Hi, On 19/01/2018 16:45, Peter Zijlstra wrote: On Thu, Jan 18, 2018 at 06:40:07PM +, Tvrtko Ursulin wrote: From: Tvrtko Ursulin For situations where sysadmins might want to allow different level of of access control for different PMUs, we start creating per-PMU perf_event_paranoid controls in sysfs. You've completely and utterly failed to explain why. On an abstract level, if there is a desire to decrease the security knob on one particular PMU provider, it is better to be able to do it just for the one, rather for the whole system. On a more concrete level, we have customers who want to look at certain i915 metrics, most probably engine utilization or queue depth, in order to make load-balancing decisions. (The two would be roughly analogous to CPU usage and load.) This data needs to be available to their userspaces dynamically and would be used to pick a best GPU engine (mostly analogous to a CPU core) to run a particular packet of work. It would be impossible to run their product as root, and while one option could be to write a proxy daemon which would allow unprivileged queries, it is also a significant complication which introduces a time shift problem on the PMU data as well. So my thinking was that a per-PMU paranoid control should not be a problematic concept in general. And my gut feeling anyway was that not all PMU providers are the same class data, security wise, which was another reason I thought per-PMU controls would be fine. There is one more way of thinking about it, and that is that the access control could even be extended to be per-event, and not just per-PMU. That would allow registered PMUs to let the core know which counters are potentially security sensitive, and which are not. I've sent another RFC along those lines some time ago, but afterwards I've changed my mind and thought the approach from this patch should be less controversial since it retains all control fully in the perf core and in the hands of sysadmins. Any thoughts on this one? Is the approach acceptable? Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/10] drm/i915: Encoder enable/disable seq wrt DSC
1. Send PPS and enable DSC after decompression is enabled in DP sink
2. Enable DSC in Source before enabling pipe
3. Disabling compression after disabling pipe, but before disabling port
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/intel_display.c | 20
2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4073c98a267f..0e0034f7ad67 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -4318,6 +4318,11 @@ extern bool intel_set_memory_cxsr(struct
drm_i915_private *dev_priv,
bool enable);
extern void intel_dp_compute_dsc_parameters(struct intel_dp *dp);
+extern void intel_dsc_enable(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state);
+extern void intel_dsc_disable(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state);
+
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3c479e3fd553..812dcf8a15c4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5226,6 +5226,11 @@ static void intel_encoders_pre_enable(struct drm_crtc
*crtc,
if (encoder->pre_enable)
encoder->pre_enable(encoder, crtc_state, conn_state);
+ /*
+* Send PPS and Enable DSC after decompression is
+* enabled in DP sink
+*/
+ intel_dsc_enable(encoder, crtc_state);
}
}
@@ -5623,7 +5628,10 @@ static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state,
struct drm_crtc *crtc = old_crtc_state->base.crtc;
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct drm_connector_state *conn_state;
+ struct drm_connector *conn;
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
+ int i;
intel_encoders_disable(crtc, old_crtc_state, old_state);
@@ -5640,6 +5648,18 @@ static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state,
if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
+ /* Invoke intel_dsc_disable */
+ for_each_new_connector_in_state(old_state, conn, conn_state, i) {
+ struct intel_encoder *encoder =
+ to_intel_encoder(conn_state->best_encoder);
+
+ if (conn_state->crtc != crtc)
+ continue;
+
+ /* Disable DSC if supported by platform and panel */
+ intel_dsc_disable(encoder, old_crtc_state);
+ }
+
if (INTEL_GEN(dev_priv) >= 9)
skylake_scaler_disable(intel_crtc);
else
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 09/10] drm: i915: Disable VDSC from Source
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_vdsc.c | 51 +++
2 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7d0574cf6e94..bd2c0832a4dc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9676,11 +9676,14 @@ enum skl_power_gate {
#define DSS_CONTROL1 _MMIO(0x67400)
#define JOINER_ENABLE (1 << 30)
+#define JOINER_DISABLE (0 << 30)
#define SPLITTER_ENABLE(1 << 31)
#define DSS_CONTROL2 _MMIO(0x67404)
#define LEFT_BRANCH_VDSC_ENABLE(1 << 31)
+#define LEFT_BRANCH_VDSC_DISABLE (0 << 31)
#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
+#define RIGHT_BRANCH_VDSC_DISABLE (0 << 15)
#define PIPE_DSS_CTL1_PB _MMIO(0x78200)
#define PIPE_DSS_CTL2_PB _MMIO(0x78204)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 16f84044f47b..86b2d17df3a8 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -1190,3 +1190,54 @@ void intel_dsc_enable(struct intel_encoder *encoder,
I915_WRITE(dsc_regs.dss_ctrl2_reg, dss_ctrl2_value);
}
}
+
+void intel_dsc_disable(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsc_regs dsc_regs;
+ struct drm_crtc *crtc = pipe_config->base.crtc;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc->pipe;
+ int type = encoder->type;
+ unsigned int dss_ctrl1_value = 0;
+ unsigned int dss_ctrl2_value = 0;
+
+ if ((INTEL_GEN(dev_priv) < 9) ||
+ !intel_dp->compr_params.compression_support)
+ return;
+
+ if (type == INTEL_OUTPUT_EDP) {
+ dsc_regs.dss_ctrl1_reg = DSS_CONTROL1;
+ dsc_regs.dss_ctrl2_reg = DSS_CONTROL2;
+ } else if (type == INTEL_OUTPUT_DP) {
+ switch (pipe) {
+ case PIPE_A:
+ dsc_regs.dss_ctrl1_reg = PIPE_DSS_CTL1_PB;
+ dsc_regs.dss_ctrl2_reg = PIPE_DSS_CTL2_PB;
+ break;
+ case PIPE_B:
+ dsc_regs.dss_ctrl1_reg = PIPE_DSS_CTL1_PC;
+ dsc_regs.dss_ctrl2_reg = PIPE_DSS_CTL2_PC;
+ break;
+ default:
+ return;
+ }
+ } else {
+ DRM_ERROR("Func:%s Unsupported port:%d\n", __func__, type);
+ }
+
+ dss_ctrl1_value = I915_READ(dsc_regs.dss_ctrl1_reg);
+ dss_ctrl2_value = I915_READ(dsc_regs.dss_ctrl2_reg);
+
+ if ((dss_ctrl2_value & LEFT_BRANCH_VDSC_ENABLE) ||
+ (dss_ctrl2_value & RIGHT_BRANCH_VDSC_ENABLE))
+ dss_ctrl2_value &= LEFT_BRANCH_VDSC_DISABLE &
+ RIGHT_BRANCH_VDSC_DISABLE;
+ I915_WRITE(dsc_regs.dss_ctrl2_reg, dss_ctrl2_value);
+
+ if (dss_ctrl1_value & JOINER_ENABLE)
+ dss_ctrl1_value &= JOINER_DISABLE;
+ I915_WRITE(dsc_regs.dss_ctrl1_reg, dss_ctrl1_value);
+}
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/10] drm: i915: Enable VDSC in Source
Below are the things being taken care as part of this patch:
1. Program Picture Parameter Set(PPS) MMIO regs and Rate Control
params regs in DSC Controller.
Depending on the no of VDSC engines, program the above regs.
2. Populate PPS Secondary Data Packet for Sink device
3. Data is send only to Sink device once DIP PPS is enabled in DIP
ctrl reg
4. DSC is only enabled only after Gen9 onwards
5. DSC capability should be supported from Sink side before programming
the source side.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_vdsc.c | 425 +-
1 file changed, 424 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 536f417624cb..16f84044f47b 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -596,7 +596,8 @@ void populate_pps_sdp_for_sink(struct intel_encoder
*encoder,
pps_params->bpp_high = (unsigned short)(vdsc_cfg->bits_per_pixel &
0xFF);
- /* The PPS structure is stored as per our hardware registers which
+ /*
+* The PPS structure is stored as per our hardware registers which
* are in little endian. When a value is assigned to a variable,
* Intel systems stores data in little endian.
* For e.g UINT16 a = 0x1234;
@@ -767,3 +768,425 @@ void populate_pps_sdp_for_sink(struct intel_encoder
*encoder,
pps_params->rc_range_parameter14 =
SWAP_TWO_BYTES(rc_range_parameters[14]);
}
+
+void intel_dsc_regs_init(struct intel_encoder *encoder,
+ struct intel_dsc_regs *dsc_regs, int dsc_type)
+{
+ switch (dsc_type) {
+ case DSC_A:
+ dsc_regs->dsc_picture_params0 = DSCA_PICTURE_PARAMETER_SET_0;
+ dsc_regs->dsc_picture_params1 = DSCA_PICTURE_PARAMETER_SET_1;
+ dsc_regs->dsc_picture_params2 = DSCA_PICTURE_PARAMETER_SET_2;
+ dsc_regs->dsc_picture_params3 = DSCA_PICTURE_PARAMETER_SET_3;
+ dsc_regs->dsc_picture_params4 = DSCA_PICTURE_PARAMETER_SET_4;
+ dsc_regs->dsc_picture_params5 = DSCA_PICTURE_PARAMETER_SET_5;
+ dsc_regs->dsc_picture_params6 = DSCA_PICTURE_PARAMETER_SET_6;
+ dsc_regs->dsc_picture_params7 = DSCA_PICTURE_PARAMETER_SET_7;
+ dsc_regs->dsc_picture_params8 = DSCA_PICTURE_PARAMETER_SET_8;
+ dsc_regs->dsc_picture_params9 = DSCA_PICTURE_PARAMETER_SET_9;
+ dsc_regs->dsc_picture_params10 = DSCA_PICTURE_PARAMETER_SET_10;
+ dsc_regs->dsc_picture_params16 = DSCA_PICTURE_PARAMETER_SET_16;
+ dsc_regs->dsc_rc_buff_thresh0_0 = DSCA_RC_BUF_THRESH_0_0;
+ dsc_regs->dsc_rc_buff_thresh0_1 = DSCA_RC_BUF_THRESH_0_1;
+ dsc_regs->dsc_rc_buff_thresh1_0 = DSCA_RC_BUF_THRESH_1_0;
+ dsc_regs->dsc_rc_buff_thresh1_1 = DSCA_RC_BUF_THRESH_1_1;
+ dsc_regs->dsc_rc_range0_0 = DSCA_RC_RANGE_PARAMETERS_0_0;
+ dsc_regs->dsc_rc_range0_1 = DSCA_RC_RANGE_PARAMETERS_0_1;
+ dsc_regs->dsc_rc_range1_0 = DSCA_RC_RANGE_PARAMETERS_1_0;
+ dsc_regs->dsc_rc_range1_1 = DSCA_RC_RANGE_PARAMETERS_1_1;
+ dsc_regs->dsc_rc_range2_0 = DSCA_RC_RANGE_PARAMETERS_2_0;
+ dsc_regs->dsc_rc_range2_1 = DSCA_RC_RANGE_PARAMETERS_2_1;
+ dsc_regs->dsc_rc_range3_0 = DSCA_RC_RANGE_PARAMETERS_3_0;
+ dsc_regs->dsc_rc_range3_1 = DSCA_RC_RANGE_PARAMETERS_3_1;
+ break;
+ case DSC_C:
+ dsc_regs->dsc_picture_params0 = DSCC_PICTURE_PARAMETER_SET_0;
+ dsc_regs->dsc_picture_params1 = DSCC_PICTURE_PARAMETER_SET_1;
+ dsc_regs->dsc_picture_params2 = DSCC_PICTURE_PARAMETER_SET_2;
+ dsc_regs->dsc_picture_params3 = DSCC_PICTURE_PARAMETER_SET_3;
+ dsc_regs->dsc_picture_params4 = DSCC_PICTURE_PARAMETER_SET_4;
+ dsc_regs->dsc_picture_params5 = DSCC_PICTURE_PARAMETER_SET_5;
+ dsc_regs->dsc_picture_params6 = DSCC_PICTURE_PARAMETER_SET_6;
+ dsc_regs->dsc_picture_params7 = DSCC_PICTURE_PARAMETER_SET_7;
+ dsc_regs->dsc_picture_params8 = DSCC_PICTURE_PARAMETER_SET_8;
+ dsc_regs->dsc_picture_params9 = DSCC_PICTURE_PARAMETER_SET_9;
+ dsc_regs->dsc_picture_params10 = DSCC_PICTURE_PARAMETER_SET_10;
+ dsc_regs->dsc_picture_params16 = DSCC_PICTURE_PARAMETER_SET_16;
+ dsc_regs->dsc_rc_buff_thresh0_0 = DSCC_RC_BUF_THRESH_0_0;
+ dsc_regs->dsc_rc_buff_thresh0_1 = DSCC_RC_BUF_THRESH_0_1;
+ dsc_regs->dsc_rc_buff_thresh1_0 = DSCC_RC_BUF_THRESH_1_0;
+ dsc_regs->dsc_rc_buff_thresh1_1 = DSCC_RC_BUF_THRESH_1_1;
+ dsc_regs->dsc_rc_range0_0 = DSCC_RC_RANGE_PARAMETERS_
[Intel-gfx] [PATCH 01/10] drm: i915: Defining Compression Capabilities
For Vesa Display Stream compression, defining structures for
compression capabilities to be stored in encoder.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_drv.h | 125 +++
drivers/gpu/drm/i915/intel_drv.h | 62 +++
include/drm/drm_dp_helper.h | 1 +
3 files changed, 188 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0d8cb74e7d02..4b1c323c0925 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -780,6 +780,131 @@ struct i915_psr {
void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *);
};
+/* DSC Configuration structure */
+#define NUM_BUF_RANGES 15
+
+/* Configuration for a single Rate Control model range */
+struct rc_range_parameters {
+ /* Min Quantization Parameters allowed for this range */
+ unsigned long range_min_qp;
+ /* Max Quantization Parameters allowed for this range */
+ unsigned long range_max_qp;
+ /* Bits/group offset to apply to target for this group */
+ unsigned long range_bpg_offset;
+};
+
+struct vdsc_config {
+ /* Bits / component for previous reconstructed line buffer */
+ unsigned long line_buf_depth;
+ /*
+* Rate control buffer size (in bits); not in PPS,
+* used only in C model for checking overflow
+*/
+ unsigned long rc_bits;
+ /* Bits per component to code (must be 8, 10, or 12) */
+ unsigned long bits_per_component;
+ /*
+* Flag indicating to do RGB - YCoCg conversion
+* and back (should be 1 for RGB input)
+*/
+ bool convert_rgb;
+ unsigned long slice_count;
+ /* Slice Width */
+ unsigned long slice_width;
+ /* Slice Height */
+ unsigned long slice_height;
+ /*
+* 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
+* outside of DSC encode/decode algorithm)
+*/
+ bool enable422;
+ /* Picture Width */
+ unsigned long pic_width;
+ /* Picture Height */
+ unsigned long pic_height;
+ /* Offset to bits/group used by RC to determine QP adjustment */
+ unsigned long rc_tgt_offset_high;
+ /* Offset to bits/group used by RC to determine QP adjustment */
+ unsigned long rc_tgt_offset_low;
+ /* Bits/pixel target << 4 (ie., 4 fractional bits) */
+ unsigned long bits_per_pixel;
+ /*
+* Factor to determine if an edge is present based
+* on the bits produced
+*/
+ unsigned long rc_edge_factor;
+ /* Slow down incrementing once the range reaches this value */
+ unsigned long rc_quant_incr_limit1;
+ /* Slow down incrementing once the range reaches this value */
+ unsigned long rc_quant_incr_limit0;
+ /* Number of pixels to delay the initial transmission */
+ unsigned long initial_xmit_delay;
+ /* Number of pixels to delay the VLD on the decoder,not including SSM */
+ unsigned long initial_dec_delay;
+ /* Block prediction range (in pixels) */
+ bool block_pred_enable;
+ /* Bits/group offset to use for first line of the slice */
+ unsigned long first_line_bpg_Ofs;
+ /* Value to use for RC model offset at slice start */
+ unsigned long initial_offset;
+ /* X position in the picture of top-left corner of slice */
+ unsigned long x_start;
+ /* Y position in the picture of top-left corner of slice */
+ unsigned long y_start;
+ /* Thresholds defining each of the buffer ranges */
+ unsigned long rc_buf_thresh[NUM_BUF_RANGES - 1];
+ /* Parameters for each of the RC ranges */
+ struct rc_range_parameters rc_range_params[NUM_BUF_RANGES];
+ /* Total size of RC model */
+ unsigned long rc_model_size;
+ /* Minimum QP where flatness information is sent */
+ unsigned long flatness_minQp;
+ /* Maximum QP where flatness information is sent */
+ unsigned long flatness_maxQp;
+ /*
+* MAX-MIN for all components is required to
+* be <= this value for flatness to be used
+*/
+ unsigned long flatness_det_thresh;
+ /* Initial value for scale factor */
+ unsigned long initial_scale_value;
+ /* Decrement scale factor every scale_decrement_interval groups */
+ unsigned long scale_decrement_interval;
+ /* Increment scale factor every scale_increment_interval groups */
+ unsigned long scale_increment_interval;
+ /* Non-first line BPG offset to use */
+ unsigned long nfl_bpg_offset;
+ /* BPG offset used to enforce slice bit */
+ unsigned long slice_bpg_offset;
+ /* Final RC linear transformation offset value */
+ unsigned long final_offset;
+ /* Enable on-off VBR (ie., disable stuffing bits) */
+ bool vbr_enable;
+ /* Mux word size (in bits) for S
[Intel-gfx] [PATCH 03/10] drm: i915: Enable/Disable DSC in DP sink
Below changes are being taken care in this patch:
1. If there is no DSC support from DPCD offset 0x60, just return
2. If DSC support is there, disable decompression in DPCD offset
0x160 during DP encoder disable sequence.
3. If DSC support is there, enable decompression in DPCD offset
0x160 during DP encoder enable sequence before sending PPS.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_ddi.c | 4
drivers/gpu/drm/i915/intel_dp.c | 14 ++
drivers/gpu/drm/i915/intel_drv.h | 2 ++
include/drm/drm_dp_helper.h | 2 ++
4 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index db92a2691206..693061444d4b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2177,6 +2177,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
intel_ddi_init_dp_buf_reg(encoder);
if (!is_mst)
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+ /* Enable Decompression in DP Sink at DPCD offset 0x00160 offset */
+ intel_dp_sink_set_decompression_state(intel_dp, DECOMPRESSION_ENABLE);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
@@ -2480,6 +2482,8 @@ static void intel_disable_ddi_dp(struct intel_encoder
*encoder,
intel_edp_drrs_disable(intel_dp, old_crtc_state);
intel_psr_disable(intel_dp, old_crtc_state);
intel_edp_backlight_off(old_conn_state);
+ /* Disable Decompression in DP Sink at DPCD offset 0x00160 offset */
+ intel_dp_sink_set_decompression_state(intel_dp, DECOMPRESSION_DISABLE);
}
static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f494a851ff89..c3b48b214e8f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2538,6 +2538,20 @@ static bool downstream_hpd_needs_d0(struct intel_dp
*intel_dp)
intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
}
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+ int decomp_state)
+{
+ int ret;
+
+ if (!intel_dp->compr_params.compression_support)
+ return;
+
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE, decomp_state);
+ if (ret < 0)
+ DRM_ERROR("DCPD write fail offset:0x%x for decompr state:%d\n",
+ DP_DSC_ENABLE, decomp_state);
+}
+
/* If the sink supports it, try to set the power state appropriately */
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
{
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6e1b907990bf..8d8d4486773a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1595,6 +1595,8 @@ int intel_dp_get_link_train_fallback_values(struct
intel_dp *intel_dp,
void intel_dp_start_link_train(struct intel_dp *intel_dp);
void intel_dp_stop_link_train(struct intel_dp *intel_dp);
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+ int decomp_state);
void intel_dp_encoder_reset(struct drm_encoder *encoder);
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 05f811c50d28..f3f44847c86e 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -445,6 +445,8 @@
# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
#define DP_DSC_ENABLE 0x160 /* DP 1.4 */
+#define DECOMPRESSION_ENABLE (1 << 0)
+#define DECOMPRESSION_DISABLE 0
#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
# define DP_PSR_ENABLE (1 << 0)
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/10] drm: i915: Define VDSC regs and DSC params
Defining all mmio regs from Gen9 onwards to be used
for VDSC programming.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_drv.h | 58 ++
drivers/gpu/drm/i915/i915_reg.h | 448
2 files changed, 506 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 760b97ec89ff..4073c98a267f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1169,8 +1169,66 @@ struct picture_parameters_set {
unsigned long pps_long_124_reserved;
};
+/* Secondary Data Packet Header */
+struct sdp_header {
+ /* SDP ID */
+ unsigned char sdp_id;
+ /* SDP Type */
+ unsigned char sdp_type;
+ union {
+ unsigned char sdp_byte1;
+ struct {
+ unsigned char revision_no :5;
+ unsigned char reserved1 :3;
+ };
+ };
+
+ union {
+ unsigned char sdp_byte2;
+ struct {
+ unsigned char num_of_valid_data_bytes : 5;
+ unsigned char reserved2 : 3;
+ };
+ };
+};
+
+union pps_sdp {
+ struct {
+ /* VS header data */
+ struct sdp_header secondary_data_packet_header;
+ /* PPS Payload */
+ struct picture_parameters_set pps_payload;
+ };
+};
+
+/* There are two instances of VDSC engines */
+#define DSC0 0
+#define DSC1 1
+
+/* Dislay Compression Units */
+enum dsc_types {
+ /* DSC_0 engine for eDP/MIPIDSI */
+ DSC_A = 0,
+ /* DSC_1 engine for eDP/MIPI DSI */
+ DSC_C = 1,
+ /* Applicable from Gen11.5 */
+ PIPEA_DSC_0 = 2,
+ PIPEA_DSC_1 = 3,
+ PIPEB_DSC_0 = 4,
+ PIPEB_DSC_1 = 5,
+ PIPEC_DSC_0 = 6,
+ PIPEC_DSC_1 = 7,
+ PIPED_DSC_0 = 8,
+ PIPED_DSC_1 = 9,
+ MAX_DSC_TYPES,
+ DSC_UNDEFINED = 127
+};
+
/* DSC Configuration structure */
#define NUM_BUF_RANGES 15
+/* Size in Bytes */
+#define SDP_HEADER_SIZE4
+#define PPS_PAYLOAD_SIZE 128
/* Configuration for a single Rate Control model range */
struct rc_range_parameters {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0fc24ab3a8ca..7d0574cf6e94 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9672,4 +9672,452 @@ enum skl_power_gate {
_ICL_PHY_MISC_B)
#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
+/* VDSC regs */
+
+#define DSS_CONTROL1 _MMIO(0x67400)
+#define JOINER_ENABLE (1 << 30)
+#define SPLITTER_ENABLE(1 << 31)
+
+#define DSS_CONTROL2 _MMIO(0x67404)
+#define LEFT_BRANCH_VDSC_ENABLE(1 << 31)
+#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
+
+#define PIPE_DSS_CTL1_PB _MMIO(0x78200)
+#define PIPE_DSS_CTL2_PB _MMIO(0x78204)
+#define PIPE_DSS_CTL1_PC _MMIO(0x78400)
+#define PIPE_DSS_CTL2_PC _MMIO(0x78404)
+
+#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
+#define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
+#define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
+#define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
+#define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
+#define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
+#define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
+#define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
+#define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
+#define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
+#define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
+#define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
+#define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
+#define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
+#define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
+#define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
+#define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
+
+#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
+#define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
+#define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
+#define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
+#define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
+#define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
+#define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
+#define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
+#define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
+#define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
+#def
[Intel-gfx] [PATCH 06/10] drm/i915: Populate PPS Secondary Data Pkt for Sink
Vesa Display Stream Compression defines Picture Parameter Set(PPS),
which encoders must communicate to decoders. PPS is encapsulated
in 128 bytes(PS0 through PS127). The PPS contains parameters that
the decoder needs to correctly decode pictures. Correct decoding
requires that an identical PPS be used at the encoder(@Source)
and decoder(@Sink).
The PPS is not considered to be part of any picture or slice budget
within the DSC coding algorithm. This patch populates PPS parameters
that needs to be transmitted to the Sink device.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_vdsc.c | 207 ++
1 file changed, 207 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 5eef551f0d09..536f417624cb 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -48,6 +48,9 @@ enum COLUMN_INDEX_BPC {
MAX_COLUMN_INDEX
};
+#define SWAP_TWO_BYTES(x) (unsigned short)(((x >> 8) & 0xFF) | \
+ ((x << 8) & 0xFF00))
+
#define TWOS_COMPLEMENT(x) (unsigned char)((~(x) + 1) & 0x3F)
/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
@@ -560,3 +563,207 @@ void intel_dp_compute_dsc_parameters(struct intel_dp
*intel_dp)
intel_compute_rc_parameters(intel_dp);
}
+
+void populate_pps_sdp_for_sink(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ struct picture_parameters_set *pps_params)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+ struct vdsc_config *vdsc_cfg = &(intel_dp->compr_params.dsc_cfg);
+ unsigned long rc_range_parameters[NUM_BUF_RANGES];
+ unsigned char i = 0;
+
+ /* PPS0 */
+ pps_params->major = (unsigned char)vdsc_cfg->dsc_version_major;
+ pps_params->minor = (unsigned char)vdsc_cfg->dsc_version_minor;
+
+ /* PPS1, PPS2 */
+ pps_params->picture_params_set_identifier = 0;
+
+ /* PPS3 */
+ pps_params->line_buffer_depth = (unsigned char)vdsc_cfg->line_buf_depth;
+ pps_params->bits_per_component =
+ (unsigned char)vdsc_cfg->bits_per_component;
+
+ /* PPS4,5 */
+ pps_params->block_prediction_enable =
+ (unsigned short)vdsc_cfg->block_pred_enable;
+ pps_params->convert_RGB = (unsigned short)vdsc_cfg->convert_rgb;
+ pps_params->enable422 = (unsigned short)vdsc_cfg->enable422;
+ pps_params->vbr_mode = (unsigned short)vdsc_cfg->vbr_enable;
+ pps_params->bpp_low = (unsigned short)(
+ (vdsc_cfg->bits_per_pixel >> 8) & 0x3);
+ pps_params->bpp_high = (unsigned short)(vdsc_cfg->bits_per_pixel &
+ 0xFF);
+
+ /* The PPS structure is stored as per our hardware registers which
+* are in little endian. When a value is assigned to a variable,
+* Intel systems stores data in little endian.
+* For e.g UINT16 a = 0x1234;
+* 0x34 is stored at lower address followed by 0x12.
+* Though, PPS packet to the panel must have big endian format for
+* data spanning 2 bytes. According to that logic, swap the
+* fields of the PPS packets that span more than one byte.
+*/
+
+ /* PPS6,7 */
+ pps_params->picture_height = SWAP_TWO_BYTES(vdsc_cfg->pic_height);
+
+ /* PPS8,9 */
+ pps_params->picture_width = SWAP_TWO_BYTES(vdsc_cfg->pic_width);
+
+ /* PPS10,11 */
+ pps_params->slice_height = SWAP_TWO_BYTES(vdsc_cfg->slice_height);
+
+ /* PPS12,13 */
+ pps_params->slice_width = SWAP_TWO_BYTES(vdsc_cfg->slice_width);
+
+ /* PPS14,15 */
+ pps_params->chunk_size = SWAP_TWO_BYTES(vdsc_cfg->chunk_size);
+
+ /* PPS15,16 */
+ pps_params->transmission_delay_low = (unsigned short)
+ ((vdsc_cfg->initial_xmit_delay >> 8) &
+ 0x3); //[9:8]
+ pps_params->transmission_delay_high = (unsigned short)
+ (vdsc_cfg->initial_xmit_delay & 0xFF);
+
+ /* PPS18,19 */
+ pps_params->initial_decode_delay =
+ SWAP_TWO_BYTES(vdsc_cfg->initial_dec_delay);
+
+ /* PPS20,21 */
+ pps_params->initial_scale =
+ (unsigned short)vdsc_cfg->initial_scale_value;
+
+ /* PPS22,23 */
+ pps_params->scale_increment_interval =
+ SWAP_TWO_BYTES(vdsc_cfg->scale_increment_interval);
+
+ /* PPS24,25 */
+ pps_params->scale_decrement_low = (unsigned short)(
+ (vdsc_cfg->scale_decrement_interval >> 8) & 0xF);
+ pps_params->scale_decrement_high = (unsigned short)(
+ vdsc_cfg->scale_decr
[Intel-gfx] [PATCH 02/10] drm: i915: Get DSC capability from DP sink
Get decompression capabilities from DP sink by doing
DPCD reads of different offsets as per eDP/DP specs.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dp.c | 167
1 file changed, 167 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1868f73f730c..f494a851ff89 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5883,6 +5883,149 @@ void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv,
return downclock_mode;
}
+static void intel_dp_sink_get_dsc_capability(struct intel_dp *intel_dp,
+ struct dp_sink_dsc_caps *dp_dsc_caps)
+{
+ u8 rcbuffer_blocksize;
+ u8 fec_dpcd;
+ unsigned long line_buffer_bit_depth, sink_support_max_bpp_msb;
+
+ /* VDSC is supported only for eDp v1.4 or higher, DPCD 0x00700 offset */
+ if (intel_dp->edp_dpcd[0] < 0x03)
+ return;
+
+ /* Read DPCD 0x060 to 0x06a */
+ if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT, intel_dp->dsc_dpcd,
+sizeof(intel_dp->dsc_dpcd)) < 0)
+ return;
+
+ dp_dsc_caps->is_dsc_supported = intel_dp->dsc_dpcd[0] &
+ DP_DSC_DECOMPRESSION_IS_SUPPORTED;
+
+ if (!dp_dsc_caps->is_dsc_supported)
+ return;
+
+ drm_dp_dpcd_readb(&intel_dp->aux, 0x090, &fec_dpcd);
+ intel_dp->fec_dpcd = fec_dpcd;
+
+ /* For DP DSC, FEC support is must */
+ if (!(intel_dp->fec_dpcd & 0x1))
+ return;
+
+ /* No VDSC support for less than 8 BPC */
+ if (intel_dp->dsc_dpcd[0xa] < DP_DSC_8_BPC)
+ return;
+
+ if (intel_dp->dsc_dpcd[0xa] & DP_DSC_8_BPC)
+ DRM_INFO("8 Bits per color support\n");
+ if (intel_dp->dsc_dpcd[0xa] & DP_DSC_10_BPC)
+ DRM_INFO("10 Bits per color support\n");
+ if (intel_dp->dsc_dpcd[0xa] & DP_DSC_12_BPC)
+ DRM_INFO("12 Bits per color support\n");
+
+ dp_dsc_caps->dsc_major_ver = intel_dp->dsc_dpcd[1] & DP_DSC_MAJOR_MASK;
+ dp_dsc_caps->dsc_minor_ver = (intel_dp->dsc_dpcd[1] &
+ DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT;
+
+ rcbuffer_blocksize = intel_dp->dsc_dpcd[2] & 0x3;
+
+ switch (rcbuffer_blocksize) {
+ case 0:
+ dp_dsc_caps->rcbuffer_blocksize = 1;
+ break;
+ case 1:
+ dp_dsc_caps->rcbuffer_blocksize = 4;
+ break;
+ case 2:
+ dp_dsc_caps->rcbuffer_blocksize = 16;
+ break;
+ case 3:
+ dp_dsc_caps->rcbuffer_blocksize = 64;
+ break;
+ default:
+ break;
+
+ }
+ dp_dsc_caps->rcbuffer_size_in_blocks = intel_dp->dsc_dpcd[3] + 1;
+
+ dp_dsc_caps->rcbuffer_size =
+ dp_dsc_caps->rcbuffer_size_in_blocks *
+ dp_dsc_caps->rcbuffer_blocksize * 1024 * 8;
+
+ dp_dsc_caps->slice_caps = intel_dp->dsc_dpcd[4];
+ line_buffer_bit_depth = intel_dp->dsc_dpcd[5];
+
+ if (line_buffer_bit_depth == 8)
+ dp_dsc_caps->line_buffer_bit_depth = intel_dp->dsc_dpcd[5];
+ else
+ dp_dsc_caps->line_buffer_bit_depth = intel_dp->dsc_dpcd[5] + 9;
+
+ dp_dsc_caps->is_block_pred_supported = intel_dp->dsc_dpcd[6] &
+ DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
+
+ dp_dsc_caps->sink_support_max_bpp = intel_dp->dsc_dpcd[7];
+ sink_support_max_bpp_msb = (intel_dp->dsc_dpcd[8] & 0x3) << 8;
+ dp_dsc_caps->sink_support_max_bpp |= sink_support_max_bpp_msb;
+
+ dp_dsc_caps->color_format_caps = intel_dp->dsc_dpcd[9];
+ dp_dsc_caps->color_depth_caps = intel_dp->dsc_dpcd[0xa];
+}
+
+static void intel_dp_get_compression_data(struct intel_dp *intel_dp,
+ struct dp_sink_dsc_caps dp_dsc_caps)
+{
+ if (!dp_dsc_caps.is_dsc_supported)
+ return;
+
+ intel_dp->compr_params.compression_support =
+ dp_dsc_caps.is_dsc_supported;
+ intel_dp->compr_params.dsc_cfg.dsc_version_major =
+ dp_dsc_caps.dsc_major_ver;
+ intel_dp->compr_params.dsc_cfg.dsc_version_minor =
+ dp_dsc_caps.dsc_minor_ver;
+
+ /* By default set bpc to 8 */
+ intel_dp->compr_params.dsc_cfg.bits_per_component = 8;
+
+ /* Take the max for Bits per component */
+ if (intel_dp->dsc_dpcd[0xa] & DP_DSC_8_BPC)
+ intel_dp->compr_params.dsc_cfg.bits_per_component = 8;
+ if (intel_dp->dsc_dpcd[0xa] & DP_DSC_10_BPC)
+ intel_dp->compr_params.dsc_cfg.bits_per_component = 10;
+ if (intel_dp->dsc_dpcd[0xa] & DP_DSC_12_BPC)
+ intel_dp->c
[Intel-gfx] [PATCH 00/10] Enabling VDSC in i915 driver for GLK
Display manufacturers are turning to higher-resolution displays to differentiate their products. The increased pixel counts have required increased bandwidth over the links that drive these displays. However, advances in physical layer technology have not kept up with the increases in pixel counts. These factors have created a need for compression on display links. The Video Electronics Standards Association(VESA),in liaison with the MIPI Alliance, has developed an industry standard Display Stream Compression(DSC) for interoperable, visually lossless compression over display links. These patches enable VDSC in i915 gfx driver for Gen9,Gen10 platforms and provide basic code for future platforms. Testing: Did testing on GLK RVP. By default GLK RVP has non-DSC EDP panel, there was no regression with these patches. BA Chrome Team (OTC) do not have EDP panel which supports DSC. Trying to arrrage DSC EDP panel from other teams in BA, hopeful to get it in few weeks. Dropping the patches to get the review started. Gaurav K Singh (10): drm: i915: Defining Compression Capabilities drm: i915: Get DSC capability from DP sink drm: i915: Enable/Disable DSC in DP sink drm: i915: Compute RC & DSC parameters drm: i915: Define Picture Parameter Set drm/i915: Populate PPS Secondary Data Pkt for Sink drm: i915: Define VDSC regs and DSC params drm: i915: Enable VDSC in Source drm: i915: Disable VDSC from Source drm/i915: Encoder enable/disable seq wrt DSC drivers/gpu/drm/i915/Makefile|1 + drivers/gpu/drm/i915/i915_drv.h | 589 drivers/gpu/drm/i915/i915_reg.h | 451 drivers/gpu/drm/i915/intel_ddi.c |4 + drivers/gpu/drm/i915/intel_display.c | 20 + drivers/gpu/drm/i915/intel_dp.c | 182 + drivers/gpu/drm/i915/intel_drv.h | 64 ++ drivers/gpu/drm/i915/intel_vdsc.c| 1243 ++ include/drm/drm_dp_helper.h |3 + 9 files changed, 2557 insertions(+) create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/10] drm: i915: Define Picture Parameter Set
Vesa Display Stream Compression defines Picture Parameter Set(PPS),
which encoders must communicate to decoders. PPS is encapsulated
in 128 bytes(PS0 through PS127). PPS specifies the syntax for DSC
bitstreams.Correct decoding also requires that an identical PPS be
used at the encoder and decoder. The PPS contains parameters that
the decoder needs to correctly decode pictures.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_drv.h | 389
1 file changed, 389 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4720a5ce3e69..760b97ec89ff 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -780,6 +780,395 @@ struct i915_psr {
void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *);
};
+struct picture_parameters_set {
+ union {
+ /* PPS0 */
+ unsigned char dsc_version;
+ struct {
+ /* Bit 0-3 Major version no */
+ unsigned char minor : 4;
+ /* Bit 4-7 Minor version no */
+ unsigned char major : 4;
+ };
+ };
+
+ union {
+ /* PPS 1 ,2 */
+ unsigned short picture_params_set_identifier;
+ struct {
+ /*
+* Bit 0-7 Application-specific identifier that can be
+* used to differentiate between different PPS table
+*/
+ unsigned short pps_identifier : 8;
+ /* Bit 8-15 Reserved */
+ unsigned short pps2_reserved :8;
+ };
+ };
+
+ union {
+ /* PPS 3 */
+ unsigned char bpc_and_lbd;
+ struct {
+ /*
+* Bit 0-3 [1000 = 8 bits, 1001 = 9 bits,
+* 1010 = 10 bits, 1011 = 11 bits, 1100 = 12bits}
+*/
+ unsigned char line_buffer_depth : 4;
+ /*
+* Bits 4-7 [1000 = 8 bits per component,1010 = 10 bits
+* per component,1100 = 12 bits per component]
+*/
+ unsigned char bits_per_component : 4;
+ };
+ };
+
+ union {
+ /* PPS 4,5 */
+ unsigned short general_pps_params;
+ struct {
+ /*
+* Bits 0-1 The target bits/pixel (bpp) rate that is
+* used by the encoder, in steps of 1/16 of a
+* bit per pixel
+*/
+ unsigned short bpp_low : 2;
+ /*
+* Bit 2 [0 = VBR mode is disabled,
+* 1 = VBR mode is enabled
+*/
+ unsigned short vbr_mode : 1;
+ /* Bit 3 [0 = 4:4:4 sampling, 1 = 4:2:2 sampling] */
+ unsigned short enable422 : 1;
+ /*
+* Bit 4 [ 0 = no conversion required,
+* 1 = need conversion from RGB to YCoCg-R during
+* encoding]
+*/
+ unsigned short convert_RGB : 1;
+ /*
+* Bit 5 [0 = If block prediction is not supported
+* on the receiver, 1 = If block prediction is
+* supported on the receiver]
+*/
+ unsigned short block_prediction_enable : 1;
+ /* Bit 6-7 reserved */
+ unsigned short pps4_reserved :2;
+ /*
+* Bits 8-15 The target bits/pixel (bpp) rate that is
+* used by the encoder, in steps of 1/16 of a bit per
+* pixel
+*/
+ unsigned short bpp_high : 8;
+ };
+ };
+
+ /* PPS 6,7 [2 bytes for pic height] */
+ unsigned short picture_height;
+ /* PPS 8,9 [2 bytes for pic width] */
+ unsigned short picture_width;
+ /* PPS 10,11 [2 bytes for slice height] */
+ unsigned short slice_height;
+ /* PPS 12,13 [2 bytes for slice width] */
+ unsigned short slice_width;
+
+ /* PPS 14, 15 [2 bytes for Chunk size] */
+ unsigned short chunk_size;
+
+ union {
+ /* PPS 16,17 */
+ unsigned short initial_transmission_delay;
+ struct {
+ /*
+* Bit 0-1 Application-specific identifier that can be
+* used to differentiate between differ
[Intel-gfx] [PATCH 04/10] drm: i915: Compute RC & DSC parameters
Below changes are there as part of this patch:
1. Adding Rate Control parameters for DSC
2. Compute Rate Control parameters
3. Compute DSC parameters for Picture Parameter Set
4. Adding a new .c file for VDSC operations
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_drv.h | 12 +
drivers/gpu/drm/i915/intel_dp.c | 1 +
drivers/gpu/drm/i915/intel_vdsc.c | 562 ++
4 files changed, 576 insertions(+)
create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 838f9b48246b..fee46d41100e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -114,6 +114,7 @@ i915-y += intel_audio.o \
intel_modes.o \
intel_overlay.o \
intel_psr.o \
+ intel_vdsc.o \
intel_sideband.o \
intel_sprite.o
i915-$(CONFIG_ACPI)+= intel_acpi.o intel_opregion.o
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4b1c323c0925..4720a5ce3e69 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -793,6 +793,17 @@ struct rc_range_parameters {
unsigned long range_bpg_offset;
};
+struct rc_parameters {
+ unsigned long initial_xmit_delay;
+ unsigned long first_line_bpg_Ofs;
+ unsigned long initial_offset;
+ unsigned long flatness_minQp;
+ unsigned long flatness_maxQp;
+ unsigned long rc_quant_incr_limit0;
+ unsigned long rc_quant_incr_limit1;
+ struct rc_range_parameters rc_range_params[NUM_BUF_RANGES];
+};
+
struct vdsc_config {
/* Bits / component for previous reconstructed line buffer */
unsigned long line_buf_depth;
@@ -3858,6 +3869,7 @@ extern int intel_modeset_vga_set_state(struct
drm_i915_private *dev_priv,
extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
bool enable);
+extern void intel_dp_compute_dsc_parameters(struct intel_dp *dp);
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c3b48b214e8f..93d3d6afa711 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -6092,6 +6092,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
if (INTEL_GEN(dev_priv) >= 9) {
intel_dp_sink_get_dsc_capability(intel_dp, &sink_dp_dsc_caps);
intel_dp_get_compression_data(intel_dp, sink_dp_dsc_caps);
+ intel_dp_compute_dsc_parameters(intel_dp);
}
mutex_lock(&dev->mode_config.mutex);
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
new file mode 100644
index ..5eef551f0d09
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -0,0 +1,562 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Gaurav K Singh
+ */
+
+#include
+#include
+#include "i915_drv.h"
+#include "intel_drv.h"
+
+enum ROW_INDEX_BPP {
+ ROW_INDEX_INVALID = 127,
+ ROW_INDEX_6BPP = 0,
+ ROW_INDEX_8BPP,
+ ROW_INDEX_10BPP,
+ ROW_INDEX_12BPP,
+ ROW_INDEX_15BPP,
+ MAX_ROW_INDEX
+};
+
+enum COLUMN_INDEX_BPC {
+ COLUMN_INDEX_INVALID = 127,
+ COLUMN_INDEX_8BPC = 0,
+ COLUMN_INDEX_10BPC,
+ COLUMN_INDEX_12BPC,
+ COLUMN_INDEX_14BPC,
+ COLUMN_INDEX_16BPC,
+ MAX_COLUMN_INDEX
+};
+
+#define TWOS_COMPLEMENT(x) (unsigned char)((~(x) + 1) & 0x3F)
+
+/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
+static unsigned long rc_buf_thresh[] = {
+
[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/uc: Start preparing GuC/HuC for reset (rev2)
== Series Details == Series: drm/i915/uc: Start preparing GuC/HuC for reset (rev2) URL : https://patchwork.freedesktop.org/series/38805/ State : warning == Summary == Test kms_flip: Subgroup dpms-vs-vblank-race-interruptible: fail -> PASS (shard-hsw) fdo#103060 +1 Test kms_sysfs_edid_timing: warn -> PASS (shard-apl) fdo#100047 Test kms_cursor_crc: Subgroup cursor-64x64-suspend: incomplete -> PASS (shard-hsw) fdo#103540 Test kms_vblank: Subgroup pipe-a-query-busy-hang: pass -> SKIP (shard-snb) fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 shard-apltotal:3465 pass:1821 dwarn:1 dfail:0 fail:12 skip:1631 time:12347s shard-hswtotal:3465 pass:1768 dwarn:1 dfail:0 fail:2 skip:1693 time:11830s shard-snbtotal:3465 pass:1356 dwarn:1 dfail:0 fail:3 skip:2105 time:6599s Blacklisted hosts: shard-kbltotal:3399 pass:1921 dwarn:1 dfail:0 fail:14 skip:1462 time:9184s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8142/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/8] drm/i915: Collect aux ch vfunc setup into intel_dp_aux_init()
On Thu, Feb 22, 2018 at 08:10:32PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Collect all the aux ch vfunc assignments into intel_dp_aux_init() > instead of having it spread around. > > Reviewed-by: Chris Wilson > Reviewed-by: Rodrigo Vivi > Signed-off-by: Ville Syrjälä Pushed 1-4 to dinq. Thanks for the reviews. -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/preemption: Allow preemption between submission ports
Chris Wilson writes:
> Sometimes we need to boost the priority of an in-flight request, which
> may lead to the situation where the second submission port then contains
> a higher priority context than the first and so we need to inject a
> preemption event. To do so we must always check inside
> execlists_dequeue() whether there is a priority inversion between the
> ports themselves as well as the head of the priority sorted queue, and we
> cannot just skip dequeuing if the queue is empty.
>
> Signed-off-by: Chris Wilson
> Cc: Michał Winiarski
> Cc: Michel Thierry
> Cc: Mika Kuoppala
> Cc: Tvrtko Ursulin
Reviewed-by: Mika Kuoppala
> ---
> Rebase for conflicts
> -Chris
> ---
> drivers/gpu/drm/i915/intel_engine_cs.c | 2 +
> drivers/gpu/drm/i915/intel_guc_submission.c | 17 +--
> drivers/gpu/drm/i915/intel_lrc.c| 161
>
> drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +
> 4 files changed, 107 insertions(+), 78 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> index c31544406974..ce7fcf55ba18 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -423,6 +423,7 @@ static void intel_engine_init_execlist(struct
> intel_engine_cs *engine)
> BUILD_BUG_ON_NOT_POWER_OF_2(execlists_num_ports(execlists));
> GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
>
> + execlists->queue_priority = INT_MIN;
> execlists->queue = RB_ROOT;
> execlists->first = NULL;
> }
> @@ -1903,6 +1904,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
> spin_lock_irq(&engine->timeline->lock);
> list_for_each_entry(rq, &engine->timeline->requests, link)
> print_request(m, rq, "\t\tE ");
> + drm_printf(m, "\t\tQueue priority: %d\n", execlists->queue_priority);
> for (rb = execlists->first; rb; rb = rb_next(rb)) {
> struct i915_priolist *p =
> rb_entry(rb, typeof(*p), node);
> diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
> b/drivers/gpu/drm/i915/intel_guc_submission.c
> index 649113c7a3c2..586dde579903 100644
> --- a/drivers/gpu/drm/i915/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
> @@ -75,6 +75,11 @@
> *
> */
>
> +static inline struct i915_priolist *to_priolist(struct rb_node *rb)
> +{
> + return rb_entry(rb, struct i915_priolist, node);
> +}
> +
> static inline bool is_high_priority(struct intel_guc_client *client)
> {
> return (client->priority == GUC_CLIENT_PRIORITY_KMD_HIGH ||
> @@ -682,15 +687,12 @@ static void guc_dequeue(struct intel_engine_cs *engine)
> rb = execlists->first;
> GEM_BUG_ON(rb_first(&execlists->queue) != rb);
>
> - if (!rb)
> - goto unlock;
> -
> if (port_isset(port)) {
> if (engine->i915->preempt_context) {
> struct guc_preempt_work *preempt_work =
> &engine->i915->guc.preempt_work[engine->id];
>
> - if (rb_entry(rb, struct i915_priolist, node)->priority >
> + if (execlists->queue_priority >
> max(port_request(port)->priotree.priority, 0)) {
> execlists_set_active(execlists,
>EXECLISTS_ACTIVE_PREEMPT);
> @@ -706,8 +708,8 @@ static void guc_dequeue(struct intel_engine_cs *engine)
> }
> GEM_BUG_ON(port_isset(port));
>
> - do {
> - struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
> + while (rb) {
> + struct i915_priolist *p = to_priolist(rb);
> struct i915_request *rq, *rn;
>
> list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) {
> @@ -736,8 +738,9 @@ static void guc_dequeue(struct intel_engine_cs *engine)
> INIT_LIST_HEAD(&p->requests);
> if (p->priority != I915_PRIORITY_NORMAL)
> kmem_cache_free(engine->i915->priorities, p);
> - } while (rb);
> + }
> done:
> + execlists->queue_priority = rb ? to_priolist(rb)->priority : INT_MIN;
> execlists->first = rb;
> if (submit) {
> port_assign(port, last);
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 964885b5d7cb..4bc72fbaf793 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -169,6 +169,23 @@ static void execlists_init_reg_state(u32 *reg_state,
>struct intel_engine_cs *engine,
>struct intel_ring *ring);
>
> +static inline struct i915_priolist *to_priolist(struct rb_node *rb)
> +{
> + return rb_entry(rb, struct i915_priolist, node);
> +}
> +
> +static inline int rq_prio(const struct i915_request *rq)
> +{
> + return r
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/uc: Introduce intel_uc_suspend|resume
== Series Details == Series: series starting with [1/2] drm/i915/uc: Introduce intel_uc_suspend|resume URL : https://patchwork.freedesktop.org/series/38867/ State : success == Summary == Series 38867v1 series starting with [1/2] drm/i915/uc: Introduce intel_uc_suspend|resume https://patchwork.freedesktop.org/api/1.0/series/38867/revisions/1/mbox/ Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-c: pass -> FAIL (fi-skl-6700k2) fdo#104108 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:415s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:422s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:376s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:487s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:283s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:480s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:483s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:466s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:453s fi-cfl-8700k total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:390s fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:564s fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:414s fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:291s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:506s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:386s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:406s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:452s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:448s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:488s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:449s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:488s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:586s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:429s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:498s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:519s fi-skl-6700k2total:288 pass:263 dwarn:0 dfail:0 fail:1 skip:24 time:472s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:466s fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:405s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:426s fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:520s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:389s 562dc33a969ded94e63f6fd1d76eb42d344052fb drm-tip: 2018y-02m-23d-09h-04m-20s UTC integration manifest bad5f6e76de7 HAX: Enable GuC for CI 05ec834cb9c7 drm/i915/uc: Introduce intel_uc_suspend|resume == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8143/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 7/8] drm/i915: Keep the AKSV details in intel_dp_hdcp_write_an_aksv()
On Friday 23 February 2018 07:16 PM, Ville Syrjälä wrote:
On Fri, Feb 23, 2018 at 04:40:42PM +0530, Ramalingam C wrote:
This is really making it cleaner.
Reviewed-by: Ramalingam C
On Friday 23 February 2018 02:57 AM, Ville Syrjala wrote:
From: Ville Syrjälä
Let's try to keep the details on the AKSV stuff concentrated
in one place. So move the control bit and +5 data size handling
there.
v2: Increase txbuf[] to include the payload which intel_dp_aux_xfer()
will still load into the registers even though the hardware
will ignore it
Cc: Sean Paul
Cc: Ramalingam C
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_dp.c | 42
+
1 file changed, 13 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 217cc6aee477..0d699d230b77 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1059,29 +1059,11 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp,
DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
}
-static uint32_t intel_dp_get_aux_send_ctl(struct intel_dp *intel_dp,
- bool has_aux_irq,
- int send_bytes,
- uint32_t aux_clock_divider,
- bool aksv_write)
-{
- uint32_t val = 0;
-
- if (aksv_write) {
- send_bytes += 5;
- val |= DP_AUX_CH_CTL_AUX_AKSV_SELECT;
- }
-
- return val | intel_dp->get_aux_send_ctl(intel_dp,
- has_aux_irq,
- send_bytes,
- aux_clock_divider);
-}
-
static int
intel_dp_aux_xfer(struct intel_dp *intel_dp,
const uint8_t *send, int send_bytes,
- uint8_t *recv, int recv_size, bool aksv_write)
+ uint8_t *recv, int recv_size,
+ u32 aux_send_ctl_flags)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv =
@@ -1145,11 +1127,12 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
}
while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
- u32 send_ctl = intel_dp_get_aux_send_ctl(intel_dp,
-has_aux_irq,
-send_bytes,
-aux_clock_divider,
-aksv_write);
+ u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
+ has_aux_irq,
+ send_bytes,
+ aux_clock_divider);
+
+ send_ctl |= aux_send_ctl_flags;
/* Must try at least 3 times according to DP spec */
for (try = 0; try < 5; try++) {
@@ -1287,7 +1270,7 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct
drm_dp_aux_msg *msg)
memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
- rxbuf, rxsize, false);
+ rxbuf, rxsize, 0);
if (ret > 0) {
msg->reply = rxbuf[0] >> 4;
@@ -1310,7 +1293,7 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
return -E2BIG;
ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
- rxbuf, rxsize, false);
+ rxbuf, rxsize, 0);
if (ret > 0) {
msg->reply = rxbuf[0] >> 4;
/*
@@ -5085,7 +5068,7 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port
*intel_dig_port,
u8 *an)
{
struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
- uint8_t txbuf[4], rxbuf[2], reply = 0;
+ uint8_t txbuf[4+5] = {}, rxbuf[2], reply = 0;
You might want to use the macros for size of txbuf as HEADER_SIZE +
DRM_HDCP_KSV_LEN, as it is done in the next patch.
As the original code was using a bare 5 I figured I'll keep using it here
as well to make it easier to see what's moving where.
Suggested the above, to make the 8th patch just for pulling out the aux
header population.
I am happy with the current shape too :)
--Ram
--Ram
ssize_t dpcd_ret;
int ret;
@@ -5110,7 +5093,8 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
txbuf[3] = DRM_HDCP_KSV_LEN - 1;
ret =
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/uc: Start preparing GuC/HuC for reset (rev2)
== Series Details == Series: drm/i915/uc: Start preparing GuC/HuC for reset (rev2) URL : https://patchwork.freedesktop.org/series/38805/ State : success == Summary == Series 38805v2 drm/i915/uc: Start preparing GuC/HuC for reset https://patchwork.freedesktop.org/api/1.0/series/38805/revisions/2/mbox/ fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:418s fi-bdw-gvtdvmtotal:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:425s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:375s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:487s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:285s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:481s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:483s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:469s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:457s fi-cfl-8700k total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:390s fi-cfl-s2total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:564s fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:416s fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:287s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:509s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:385s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:410s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:452s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:452s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:494s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:450s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:492s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:593s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:425s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:502s fi-skl-6700hqtotal:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:522s fi-skl-6700k2total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:481s fi-skl-6770hqtotal:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:484s fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:407s fi-skl-gvtdvmtotal:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:433s fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:533s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:393s 562dc33a969ded94e63f6fd1d76eb42d344052fb drm-tip: 2018y-02m-23d-09h-04m-20s UTC integration manifest d2c3f7fe851c drm/i915/uc: Start preparing GuC/HuC for reset == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8142/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/preemption: Allow preemption between submission ports
Quoting Mika Kuoppala (2018-02-23 14:06:06)
> Chris Wilson writes:
> > static inline bool is_high_priority(struct intel_guc_client *client)
> > {
> > return (client->priority == GUC_CLIENT_PRIORITY_KMD_HIGH ||
> > @@ -682,15 +687,12 @@ static void guc_dequeue(struct intel_engine_cs
> > *engine)
> > rb = execlists->first;
> > GEM_BUG_ON(rb_first(&execlists->queue) != rb);
> >
> > - if (!rb)
> > - goto unlock;
> > -
> > if (port_isset(port)) {
> > if (engine->i915->preempt_context) {
> > struct guc_preempt_work *preempt_work =
> > &engine->i915->guc.preempt_work[engine->id];
> >
> > - if (rb_entry(rb, struct i915_priolist,
> > node)->priority >
> > + if (execlists->queue_priority >
> > max(port_request(port)->priotree.priority, 0)) {
> > execlists_set_active(execlists,
> >
> > EXECLISTS_ACTIVE_PREEMPT);
>
> This is the priority inversion part? We preempt and clear the ports
> to rearrange if the last port has a higher priority request?
Yes, along with a strong kick from
> > @@ -1050,8 +1068,9 @@ static void execlists_schedule(struct i915_request
> > *request, int prio)
> > pt->priority = prio;
> > if (!list_empty(&pt->link)) {
> > __list_del_entry(&pt->link);
> > - insert_request(engine, pt, prio);
> > + queue_request(engine, pt, prio);
> > }
> > + submit_queue(engine, prio);
So that we re-evaluate ELSP if the active prio change.
> > @@ -264,7 +281,7 @@ lookup_priolist(struct intel_engine_cs *engine,
> > if (first)
> > execlists->first = &p->node;
> >
> > - return ptr_pack_bits(p, first, 1);
> > + return p;
>
> Hmm there is no need for decode first as we always resubmit
> the queue depending on the prio?
Right, the first bit is now checked against queue_priority instead. If
we are higher priority than the queue, we must rerun the tasklet.
Whereas before we knew we only had to do it if we inserted into the
start of the queue.
> > @@ -453,12 +467,17 @@ static void inject_preempt_context(struct
> > intel_engine_cs *engine)
> > _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
> > CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT));
> >
> > + /*
> > + * Switch to our empty preempt context so
> > + * the state of the GPU is known (idle).
> > + */
> > GEM_TRACE("%s\n", engine->name);
> > for (n = execlists_num_ports(&engine->execlists); --n; )
> > elsp_write(0, engine->execlists.elsp);
> >
> > elsp_write(ce->lrc_desc, engine->execlists.elsp);
> > execlists_clear_active(&engine->execlists, EXECLISTS_ACTIVE_HWACK);
> > + execlists_set_active(&engine->execlists, EXECLISTS_ACTIVE_PREEMPT);
>
> Surely a better place. Now looking at this would it be more prudent to
> move both the clear and set right before the last elsp write?
>
> Well I guess it really doesn't matter as we hold the timeline lock.
And we only process ELSP from a single cpu, so it's all sequential,
right.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] tests/perf_pmu: Handle CPU hotplug failures better
On 23/02/2018 11:58, Petri Latvala wrote:
On Fri, Feb 23, 2018 at 11:34:53AM +, Tvrtko Ursulin wrote:
From: Chris Wilson
CPU hotplug, especially CPU0, can be flaky on commodity hardware.
To improve test reliability and reponse times when testing larger runs we
need to handle those cases better.
Handle failures to off-line a CPU by immediately skipping the test, and
failures to on-line a CPU by immediately rebooting the machine.
This patch includes igt_sysrq_reboot implementation from Chris Wilson.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
---
lib/Makefile.sources | 2 ++
lib/igt_sysrq.c | 22 ++
lib/igt_sysrq.h | 30 ++
lib/meson.build | 2 ++
tests/perf_pmu.c | 42 ++
5 files changed, 90 insertions(+), 8 deletions(-)
create mode 100644 lib/igt_sysrq.c
create mode 100644 lib/igt_sysrq.h
diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 5b13ef8896c0..3d37ef1d1984 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -35,6 +35,8 @@ lib_source_list = \
igt_stats.h \
igt_sysfs.c \
igt_sysfs.h \
+ igt_sysrq.c \
+ igt_sysrq.h \
igt_x86.h \
igt_x86.c \
igt_vgem.c \
diff --git a/lib/igt_sysrq.c b/lib/igt_sysrq.c
new file mode 100644
index ..fe3d2e344ff1
--- /dev/null
+++ b/lib/igt_sysrq.c
@@ -0,0 +1,22 @@
+#include
+#include
+#include
+#include
+
+#include "igt_core.h"
+
+#include "igt_sysrq.h"
+
+void igt_sysrq_reboot(void)
+{
+ sync();
+
+ /* Try to be nice at first, and if that fails pull the trigger */
+ if (reboot(RB_AUTOBOOT)) {
+ int fd = open("/proc/sysrq-trigger", O_WRONLY);
+ igt_ignore_warn(write(fd, "b", 2));
+ close(fd);
+ }
+
+ abort();
+}
While the cause for taking this action might be dire, rebooting
people's machines can be kind of a dick move, even considering they're
running tests that can be fatal to the machine in other ways.
We have IGT_HANG and IGT_HANG_WITHOUT_RESET so the users can opt
in/out of some fatal behaviour already. I'm fine with auto-rebooting,
even as the default, if users can opt out of it with
IGT_NO_REBOOT_PRETTY_PLEASE or so.
I am fine with something like that. Just lets define how to call the env
variable and what the default should be?
Do we have a return code from a test which stops the test runner?
I am thinking that the best approach would be not to reboot but to halt
testing, unless this environment option is set.
But then it is up to CI people to say if they want to be setting this
option across all systems, or would actually prefer to reboot by default.
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/uc: Introduce intel_uc_suspend|resume
We want to use higher level 'uc' functions as the main entry points to
the GuC/HuC code to hide some details and keep code layered.
Signed-off-by: Michal Wajdeczko
Cc: Sagar Arun Kamble
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 6 +++---
drivers/gpu/drm/i915/i915_gem.c | 4 ++--
drivers/gpu/drm/i915/intel_guc.c | 42 +
drivers/gpu/drm/i915/intel_guc.h | 4 ++--
drivers/gpu/drm/i915/intel_uc.c | 45
drivers/gpu/drm/i915/intel_uc.h | 2 ++
6 files changed, 68 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index aaa861b..d61b51c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2575,7 +2575,7 @@ static int intel_runtime_suspend(struct device *kdev)
*/
i915_gem_runtime_suspend(dev_priv);
- intel_guc_suspend(dev_priv);
+ intel_uc_suspend(dev_priv);
intel_runtime_pm_disable_interrupts(dev_priv);
@@ -2597,7 +2597,7 @@ static int intel_runtime_suspend(struct device *kdev)
intel_runtime_pm_enable_interrupts(dev_priv);
- intel_guc_resume(dev_priv);
+ intel_uc_resume(dev_priv);
i915_gem_init_swizzling(dev_priv);
i915_gem_restore_fences(dev_priv);
@@ -2683,7 +2683,7 @@ static int intel_runtime_resume(struct device *kdev)
intel_runtime_pm_enable_interrupts(dev_priv);
- intel_guc_resume(dev_priv);
+ intel_uc_resume(dev_priv);
/*
* No point of rolling back things in case of an error, as the best
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 14c855b..ef6aff8 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4919,7 +4919,7 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
i915_gem_contexts_lost(dev_priv);
mutex_unlock(&dev->struct_mutex);
- intel_guc_suspend(dev_priv);
+ intel_uc_suspend(dev_priv);
cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
cancel_delayed_work_sync(&dev_priv->gt.retire_work);
@@ -4986,7 +4986,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
if (i915_gem_init_hw(i915))
goto err_wedged;
- intel_guc_resume(i915);
+ intel_uc_resume(i915);
/* Always reload a context for powersaving. */
if (i915_gem_switch_to_kernel_context(i915))
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 21140cc..6ca6b9a 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -403,22 +403,15 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32
rsa_offset)
/**
* intel_guc_suspend() - notify GuC entering suspend state
- * @dev_priv: i915 device private
+ * @guc: the guc
*/
-int intel_guc_suspend(struct drm_i915_private *dev_priv)
+int intel_guc_suspend(struct intel_guc *guc)
{
- struct intel_guc *guc = &dev_priv->guc;
- u32 data[3];
-
- if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
- return 0;
-
- gen9_disable_guc_interrupts(dev_priv);
-
- data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
- /* any value greater than GUC_POWER_D0 */
- data[1] = GUC_POWER_D1;
- data[2] = guc_ggtt_offset(guc->shared_data);
+ u32 data[] = {
+ INTEL_GUC_ACTION_ENTER_S_STATE,
+ GUC_POWER_D1, /* any value greater than GUC_POWER_D0 */
+ guc_ggtt_offset(guc->shared_data)
+ };
return intel_guc_send(guc, data, ARRAY_SIZE(data));
}
@@ -448,22 +441,15 @@ int intel_guc_reset_engine(struct intel_guc *guc,
/**
* intel_guc_resume() - notify GuC resuming from suspend state
- * @dev_priv: i915 device private
+ * @guc: the guc
*/
-int intel_guc_resume(struct drm_i915_private *dev_priv)
+int intel_guc_resume(struct intel_guc *guc)
{
- struct intel_guc *guc = &dev_priv->guc;
- u32 data[3];
-
- if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
- return 0;
-
- if (i915_modparams.guc_log_level)
- gen9_enable_guc_interrupts(dev_priv);
-
- data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
- data[1] = GUC_POWER_D0;
- data[2] = guc_ggtt_offset(guc->shared_data);
+ u32 data[] = {
+ INTEL_GUC_ACTION_EXIT_S_STATE,
+ GUC_POWER_D0,
+ guc_ggtt_offset(guc->shared_data)
+ };
return intel_guc_send(guc, data, ARRAY_SIZE(data));
}
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 52856a9..b9424ac 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -127,8 +127,8 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
[Intel-gfx] [PATCH 2/2] HAX: Enable GuC for CI
v2: except running with HYPERVISOR Signed-off-by: Michal Wajdeczko --- drivers/gpu/drm/i915/i915_params.h | 2 +- drivers/gpu/drm/i915/intel_uc.c| 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 430f5f9..3deae1e 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -47,7 +47,7 @@ param(int, disable_power_well, -1) \ param(int, enable_ips, 1) \ param(int, invert_brightness, 0) \ - param(int, enable_guc, 0) \ + param(int, enable_guc, -1) \ param(int, guc_log_level, 0) \ param(char *, guc_firmware_path, NULL) \ param(char *, huc_firmware_path, NULL) \ diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index a821f7a..0e72e60 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -63,6 +63,8 @@ static int __get_platform_enable_guc(struct drm_i915_private *dev_priv) enable_guc |= ENABLE_GUC_LOAD_HUC; /* Any platform specific fine-tuning can be done here */ + if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) + enable_guc = 0; return enable_guc; } -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/preemption: Allow preemption between submission ports
On Fri, Feb 23, 2018 at 09:04:08AM +, Chris Wilson wrote:
> Sometimes we need to boost the priority of an in-flight request, which
> may lead to the situation where the second submission port then contains
> a higher priority context than the first and so we need to inject a
> preemption event. To do so we must always check inside
> execlists_dequeue() whether there is a priority inversion between the
> ports themselves as well as the head of the priority sorted queue, and we
> cannot just skip dequeuing if the queue is empty.
>
> Signed-off-by: Chris Wilson
> Cc: Michał Winiarski
> Cc: Michel Thierry
> Cc: Mika Kuoppala
> Cc: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/intel_engine_cs.c | 2 +
> drivers/gpu/drm/i915/intel_guc_submission.c | 17 +--
> drivers/gpu/drm/i915/intel_lrc.c| 161
>
> drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +
> 4 files changed, 107 insertions(+), 78 deletions(-)
>
[SNIP]
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
> b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index a9b83bf7e837..c4e9022b34e3 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -257,6 +257,11 @@ struct intel_engine_execlists {
>*/
> unsigned int port_mask;
>
> + /**
> + * @queue_priority: Highest pending priority.
> + */
> + int queue_priority;
> +
Can we expand the comment a bit? Mentioning that it's referring to both requests
that are in the queue and those already sent to the HW?
Reviewed-by: Michał Winiarski
-Michał
> /**
>* @queue: queue of requests, in priority lists
>*/
> --
> 2.16.1
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/preemption: Allow preemption between submission ports
Chris Wilson writes:
> Sometimes we need to boost the priority of an in-flight request, which
> may lead to the situation where the second submission port then contains
> a higher priority context than the first and so we need to inject a
> preemption event. To do so we must always check inside
> execlists_dequeue() whether there is a priority inversion between the
> ports themselves as well as the head of the priority sorted queue, and we
> cannot just skip dequeuing if the queue is empty.
>
> Signed-off-by: Chris Wilson
> Cc: Michał Winiarski
> Cc: Michel Thierry
> Cc: Mika Kuoppala
> Cc: Tvrtko Ursulin
> ---
> Rebase for conflicts
> -Chris
> ---
> drivers/gpu/drm/i915/intel_engine_cs.c | 2 +
> drivers/gpu/drm/i915/intel_guc_submission.c | 17 +--
> drivers/gpu/drm/i915/intel_lrc.c| 161
>
> drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +
> 4 files changed, 107 insertions(+), 78 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> index c31544406974..ce7fcf55ba18 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -423,6 +423,7 @@ static void intel_engine_init_execlist(struct
> intel_engine_cs *engine)
> BUILD_BUG_ON_NOT_POWER_OF_2(execlists_num_ports(execlists));
> GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
>
> + execlists->queue_priority = INT_MIN;
> execlists->queue = RB_ROOT;
> execlists->first = NULL;
> }
> @@ -1903,6 +1904,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
> spin_lock_irq(&engine->timeline->lock);
> list_for_each_entry(rq, &engine->timeline->requests, link)
> print_request(m, rq, "\t\tE ");
> + drm_printf(m, "\t\tQueue priority: %d\n", execlists->queue_priority);
> for (rb = execlists->first; rb; rb = rb_next(rb)) {
> struct i915_priolist *p =
> rb_entry(rb, typeof(*p), node);
> diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
> b/drivers/gpu/drm/i915/intel_guc_submission.c
> index 649113c7a3c2..586dde579903 100644
> --- a/drivers/gpu/drm/i915/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
> @@ -75,6 +75,11 @@
> *
> */
>
> +static inline struct i915_priolist *to_priolist(struct rb_node *rb)
> +{
> + return rb_entry(rb, struct i915_priolist, node);
> +}
> +
> static inline bool is_high_priority(struct intel_guc_client *client)
> {
> return (client->priority == GUC_CLIENT_PRIORITY_KMD_HIGH ||
> @@ -682,15 +687,12 @@ static void guc_dequeue(struct intel_engine_cs *engine)
> rb = execlists->first;
> GEM_BUG_ON(rb_first(&execlists->queue) != rb);
>
> - if (!rb)
> - goto unlock;
> -
> if (port_isset(port)) {
> if (engine->i915->preempt_context) {
> struct guc_preempt_work *preempt_work =
> &engine->i915->guc.preempt_work[engine->id];
>
> - if (rb_entry(rb, struct i915_priolist, node)->priority >
> + if (execlists->queue_priority >
> max(port_request(port)->priotree.priority, 0)) {
> execlists_set_active(execlists,
>EXECLISTS_ACTIVE_PREEMPT);
This is the priority inversion part? We preempt and clear the ports
to rearrange if the last port has a higher priority request?
> @@ -706,8 +708,8 @@ static void guc_dequeue(struct intel_engine_cs *engine)
> }
> GEM_BUG_ON(port_isset(port));
>
> - do {
> - struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
> + while (rb) {
> + struct i915_priolist *p = to_priolist(rb);
> struct i915_request *rq, *rn;
>
> list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) {
> @@ -736,8 +738,9 @@ static void guc_dequeue(struct intel_engine_cs *engine)
> INIT_LIST_HEAD(&p->requests);
> if (p->priority != I915_PRIORITY_NORMAL)
> kmem_cache_free(engine->i915->priorities, p);
> - } while (rb);
> + }
> done:
> + execlists->queue_priority = rb ? to_priolist(rb)->priority : INT_MIN;
> execlists->first = rb;
> if (submit) {
> port_assign(port, last);
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 964885b5d7cb..4bc72fbaf793 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -169,6 +169,23 @@ static void execlists_init_reg_state(u32 *reg_state,
>struct intel_engine_cs *engine,
>struct intel_ring *ring);
>
> +static inline struct i915_priolist *to_priolist(struct rb_node *rb)
> +{
> + return rb_entry(rb, struct i915_prioli
[Intel-gfx] [PATCH v2] drm/i915/uc: Start preparing GuC/HuC for reset
Right after GPU reset there will be a small window of time during which
some of GuC/HuC fields will still show state before reset. Let's start
to fix that by sanitizing firmware status as we will use it shortly.
v2: s/reset_prepare/prepare_to_reset (Michel)
don't forget about gem_sanitize path (Daniele)
Suggested-by: Daniele Ceraolo Spurio
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Sagar Arun Kamble
Cc: Chris Wilson
Cc: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem.c| 5 -
drivers/gpu/drm/i915/intel_guc.h | 5 +
drivers/gpu/drm/i915/intel_huc.h | 5 +
drivers/gpu/drm/i915/intel_uc.c| 14 ++
drivers/gpu/drm/i915/intel_uc.h| 1 +
drivers/gpu/drm/i915/intel_uc_fw.h | 6 ++
6 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 14c855b..ae2c4ba 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2981,6 +2981,7 @@ int i915_gem_reset_prepare(struct drm_i915_private
*dev_priv)
}
i915_gem_revoke_fences(dev_priv);
+ intel_uc_prepare_to_reset(dev_priv);
return err;
}
@@ -4881,8 +4882,10 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
* it may impact the display and we are uncertain about the stability
* of the reset, so this could be applied to even earlier gen.
*/
- if (INTEL_GEN(i915) >= 5 && intel_has_gpu_reset(i915))
+ if (INTEL_GEN(i915) >= 5 && intel_has_gpu_reset(i915)) {
+ intel_uc_prepare_to_reset(i915);
WARN_ON(intel_gpu_reset(i915, ALL_ENGINES));
+ }
}
int i915_gem_suspend(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 52856a9..0f6adb1 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -132,4 +132,9 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)
struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
+static inline void intel_guc_prepare_to_reset(struct intel_guc *guc)
+{
+ intel_uc_fw_prepare_to_reset(&guc->fw);
+}
+
#endif
diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
index 40039db..96e24f9 100644
--- a/drivers/gpu/drm/i915/intel_huc.h
+++ b/drivers/gpu/drm/i915/intel_huc.h
@@ -38,4 +38,9 @@ struct intel_huc {
int intel_huc_init_hw(struct intel_huc *huc);
int intel_huc_auth(struct intel_huc *huc);
+static inline void intel_huc_prepare_to_reset(struct intel_huc *huc)
+{
+ intel_uc_fw_prepare_to_reset(&huc->fw);
+}
+
#endif
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 9f1bac6..8042d4b 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -445,3 +445,17 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
if (USES_GUC_SUBMISSION(dev_priv))
gen9_disable_guc_interrupts(dev_priv);
}
+
+void intel_uc_prepare_to_reset(struct drm_i915_private *i915)
+{
+ struct intel_huc *huc = &i915->huc;
+ struct intel_guc *guc = &i915->guc;
+
+ if (!USES_GUC(i915))
+ return;
+
+ GEM_BUG_ON(!HAS_GUC(i915));
+
+ intel_huc_prepare_to_reset(huc);
+ intel_guc_prepare_to_reset(guc);
+}
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index f2984e0..7a8ae58 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -39,6 +39,7 @@
void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
int intel_uc_init(struct drm_i915_private *dev_priv);
void intel_uc_fini(struct drm_i915_private *dev_priv);
+void intel_uc_prepare_to_reset(struct drm_i915_private *dev_priv);
static inline bool intel_uc_is_using_guc(void)
{
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h
b/drivers/gpu/drm/i915/intel_uc_fw.h
index d5fd460..f1ee653 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.h
+++ b/drivers/gpu/drm/i915/intel_uc_fw.h
@@ -115,6 +115,12 @@ static inline bool intel_uc_fw_is_selected(struct
intel_uc_fw *uc_fw)
return uc_fw->path != NULL;
}
+static inline void intel_uc_fw_prepare_to_reset(struct intel_uc_fw *uc_fw)
+{
+ if (uc_fw->load_status == INTEL_UC_FIRMWARE_SUCCESS)
+ uc_fw->load_status = INTEL_UC_FIRMWARE_PENDING;
+}
+
void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
struct intel_uc_fw *uc_fw);
int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] drm/uapi: The ctm matrix uses sign-magnitude representation
On Fri, Feb 23, 2018 at 01:52:22PM +, Brian Starkey wrote:
> Hi Ville,
>
> On Thu, Feb 22, 2018 at 11:42:29PM +0200, Ville Syrjala wrote:
> >From: Ville Syrjälä
> >
> >The documentation for the ctm matrix suggests a two's complement
> >format, but at least the i915 implementation is using sign-magnitude
> >instead. And looks like malidp is doing the same. Change the docs
> >to match the current implementation, and change the type from __s64
> >to __u64 to drive the point home.
>
> I totally agree that this is a good idea, but...
>
> >
> >Cc: dri-de...@lists.freedesktop.org
> >Cc: Mihail Atanassov
> >Cc: Liviu Dudau
> >Cc: Brian Starkey
> >Cc: Mali DP Maintainers
> >Cc: Johnson Lin
> >Cc: Uma Shankar
> >Cc: Shashank Sharma
> >Signed-off-by: Ville Syrjälä
> >---
> > include/uapi/drm/drm_mode.h | 7 +--
> > 1 file changed, 5 insertions(+), 2 deletions(-)
> >
> >diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
> >index 2c575794fb52..b5d7d9e0eff5 100644
> >--- a/include/uapi/drm/drm_mode.h
> >+++ b/include/uapi/drm/drm_mode.h
> >@@ -598,8 +598,11 @@ struct drm_mode_crtc_lut {
> > };
> >
> > struct drm_color_ctm {
> >-/* Conversion matrix in S31.32 format. */
> >-__s64 matrix[9];
> >+/*
> >+ * Conversion matrix in S31.32 sign-magnitude
> >+ * (not two's complement!) format.
> >+ */
> >+__u64 matrix[9];
>
> Isn't changing the type liable to break something for someone?
I hope not. Renaming the member would be a no no, but just changing the
type should be mostly safe I think. I suppose if someone is building
something with very strict compiler -W flags and -Werror it might cause
a build failure, so I guess one might label it as a minor api break but
not an abi break.
If people think that's a serious concern I guess we can keep the
__s64, but I'd rather not give people that much rope to hang
themselves by interpreting it as 2's complement.
--
Ville Syrjälä
Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [1/8] drm/i915: Use the correct power domain for aux ch (rev3)
On Fri, Feb 23, 2018 at 05:19:19AM -, Patchwork wrote: > == Series Details == > > Series: series starting with [1/8] drm/i915: Use the correct power domain for > aux ch (rev3) > URL : https://patchwork.freedesktop.org/series/38802/ > State : warning > > == Summary == > > Test kms_flip_tiling: > Subgroup flip-to-yf-tiled: > fail -> PASS (shard-apl) fdo#103822 > Test drv_suspend: > Subgroup forcewake: > pass -> SKIP (shard-snb) Test requirement not met in function suspend_via_rtcwake, file igt_aux.c:815: Test requirement: ret == 0 rtcwake test failed with 1 This failure could mean that something is wrong with the rtcwake tool or how your distro is set up. Subtest forcewake: SKIP (0.017s) > Test kms_flip: > Subgroup 2x-wf_vblank-ts-check: > fail -> PASS (shard-hsw) fdo#100368 +1 > Test kms_frontbuffer_tracking: > Subgroup fbc-1p-primscrn-indfb-msflip-blt: > fail -> PASS (shard-apl) fdo#103167 > > fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 > fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 > fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 > > shard-apltotal:3465 pass:1821 dwarn:1 dfail:0 fail:12 skip:1631 > time:12344s > shard-hswtotal:3465 pass:1768 dwarn:1 dfail:0 fail:2 skip:1693 > time:11672s > shard-snbtotal:3465 pass:1357 dwarn:1 dfail:0 fail:2 skip:2105 > time:6617s > Blacklisted hosts: > shard-kbltotal:3428 pass:1925 dwarn:15 dfail:1 fail:14 skip:1472 > time:9202s > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8138/shards.html -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] drm/uapi: The ctm matrix uses sign-magnitude representation
Hi Ville,
On Thu, Feb 22, 2018 at 11:42:29PM +0200, Ville Syrjala wrote:
From: Ville Syrjälä
The documentation for the ctm matrix suggests a two's complement
format, but at least the i915 implementation is using sign-magnitude
instead. And looks like malidp is doing the same. Change the docs
to match the current implementation, and change the type from __s64
to __u64 to drive the point home.
I totally agree that this is a good idea, but...
Cc: dri-de...@lists.freedesktop.org
Cc: Mihail Atanassov
Cc: Liviu Dudau
Cc: Brian Starkey
Cc: Mali DP Maintainers
Cc: Johnson Lin
Cc: Uma Shankar
Cc: Shashank Sharma
Signed-off-by: Ville Syrjälä
---
include/uapi/drm/drm_mode.h | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 2c575794fb52..b5d7d9e0eff5 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -598,8 +598,11 @@ struct drm_mode_crtc_lut {
};
struct drm_color_ctm {
- /* Conversion matrix in S31.32 format. */
- __s64 matrix[9];
+ /*
+* Conversion matrix in S31.32 sign-magnitude
+* (not two's complement!) format.
+*/
+ __u64 matrix[9];
Isn't changing the type liable to break something for someone?
Thanks,
-Brian
};
struct drm_color_lut {
--
2.16.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/4] drm/i915: Don't mangle the CTM on pre-HSW
On Fri, Feb 23, 2018 at 01:33:42PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com]
> >Sent: Friday, February 23, 2018 3:13 AM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: Lin, Johnson ; Shankar, Uma
> >; Sharma, Shashank
> >Subject: [PATCH 4/4] drm/i915: Don't mangle the CTM on pre-HSW
> >
> >From: Ville Syrjälä
> >
> >On pre-HSW we have dedicated hardware for the RGB limited range handling, and
> >so we don't want to compress with the CSC matrix.
> >
> >Toss in a FIXME about gamma LUT vs. limited range using the CSC.
> >
> >Cc: Johnson Lin
> >Cc: Uma Shankar
> >Cc: Shashank Sharma
> >Signed-off-by: Ville Syrjälä
> >---
> > drivers/gpu/drm/i915/intel_color.c | 16
> > 1 file changed, 12 insertions(+), 4 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_color.c
> >b/drivers/gpu/drm/i915/intel_color.c
> >index af1e61d3bacd..89ab0f70aa22 100644
> >--- a/drivers/gpu/drm/i915/intel_color.c
> >+++ b/drivers/gpu/drm/i915/intel_color.c
> >@@ -140,6 +140,14 @@ static void ilk_load_csc_matrix(struct drm_crtc_state
> >*crtc_state)
> > int i, pipe = intel_crtc->pipe;
> > uint16_t coeffs[9] = { 0, };
> > struct intel_crtc_state *intel_crtc_state =
> > to_intel_crtc_state(crtc_state);
> >+bool limited_color_range = false;
> >+
> >+/*
> >+ * FIXME if there's a gamma LUT after the CSC, we should
> >+ * do the range compression using the gamma LUT instead.
> >+ */
> >+if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
> >+limited_color_range = intel_crtc_state->limited_color_range;
> >
>
> Hi Ville,
> For VLV or similar platforms (having dedicated color range h/w) for
> limited_range this matrix
> would have been getting used. Though they have a dedicated h/w but I don't
> think it's getting
> programmed currently. Not sure, with removing this CSC scaling logic, it may
> break the
> limited_color scenarios on those platforms. I believe using the dedicated h/w
> or this scaled_down
> CSC should be giving similar results making the things work currently. Not
> sure if we are using
> any limited_range combinations on those platforms though :)
All pre-HSW platforms that have the pipe CSC (ILK,SNB,IVB) are using
the dedicated hardware for the limited range RGB output. We don't use
the CSC on those platforms for anything at the moment so it doesn't
actually matter what we program into it. But we want to start using
the CSC for ctm and ycbcr444 output which means we have to start
setting it up correctly.
>
> Regards,
> Uma Shankar
>
> > if (intel_crtc_state->ycbcr420) {
> > ilk_load_ycbcr_conversion_matrix(intel_crtc);
> >@@ -150,7 +158,7 @@ static void ilk_load_csc_matrix(struct drm_crtc_state
> >*crtc_state)
> > const u64 *input;
> > u64 temp[9];
> >
> >-if (intel_crtc_state->limited_color_range)
> >+if (limited_color_range)
> > input = ctm_mult_by_limited(temp, ctm->matrix);
> > else
> > input = ctm->matrix;
> >@@ -200,7 +208,7 @@ static void ilk_load_csc_matrix(struct drm_crtc_state
> >*crtc_state)
> > * into consideration.
> > */
> > for (i = 0; i < 3; i++) {
> >-if (intel_crtc_state->limited_color_range)
> >+if (limited_color_range)
> > coeffs[i * 3 + i] =
> > ILK_CSC_COEFF_LIMITED_RANGE;
> > else
> >@@ -224,7 +232,7 @@ static void ilk_load_csc_matrix(struct drm_crtc_state
> >*crtc_state)
> > if (INTEL_GEN(dev_priv) > 6) {
> > uint16_t postoff = 0;
> >
> >-if (intel_crtc_state->limited_color_range)
> >+if (limited_color_range)
> > postoff = (16 * (1 << 12) / 255) & 0x1fff;
> >
> > I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); @@ -235,7
> >+243,7 @@ static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state)
> > } else {
> > uint32_t mode = CSC_MODE_YUV_TO_RGB;
> >
> >-if (intel_crtc_state->limited_color_range)
> >+if (limited_color_range)
> > mode |= CSC_BLACK_SCREEN_OFFSET;
> >
> > I915_WRITE(PIPE_CSC_MODE(pipe), mode);
> >--
> >2.16.1
>
--
Ville Syrjälä
Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v14 1/6] drm/i915: store all subslice masks
On 22/02/18 17:53, Lionel Landwerlin wrote:
+static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
+ int slice, int subslice)
+{
+ int i, offset = sseu_eu_idx(sseu, slice, subslice);
+ u16 eu_mask = 0;
+
+ for (i = 0;
+i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
+ eu_mask = ((u16) sseu->eu_mask[offset + i]) <<
+ (i * BITS_PER_BYTE);
Found a bug here (only affecting HSW with 10EUs per half-slice).
Should be eu_mask |= ...
+ }
+
+ return eu_mask;
+}
+
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 7/8] drm/i915: Keep the AKSV details in intel_dp_hdcp_write_an_aksv()
On Fri, Feb 23, 2018 at 04:40:42PM +0530, Ramalingam C wrote:
> This is really making it cleaner.
>
> Reviewed-by: Ramalingam C
>
>
>
> On Friday 23 February 2018 02:57 AM, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Let's try to keep the details on the AKSV stuff concentrated
> > in one place. So move the control bit and +5 data size handling
> > there.
> >
> > v2: Increase txbuf[] to include the payload which intel_dp_aux_xfer()
> > will still load into the registers even though the hardware
> > will ignore it
> >
> > Cc: Sean Paul
> > Cc: Ramalingam C
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 42
> > +
> > 1 file changed, 13 insertions(+), 29 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 217cc6aee477..0d699d230b77 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1059,29 +1059,11 @@ static uint32_t skl_get_aux_send_ctl(struct
> > intel_dp *intel_dp,
> >DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
> > }
> >
> > -static uint32_t intel_dp_get_aux_send_ctl(struct intel_dp *intel_dp,
> > - bool has_aux_irq,
> > - int send_bytes,
> > - uint32_t aux_clock_divider,
> > - bool aksv_write)
> > -{
> > - uint32_t val = 0;
> > -
> > - if (aksv_write) {
> > - send_bytes += 5;
> > - val |= DP_AUX_CH_CTL_AUX_AKSV_SELECT;
> > - }
> > -
> > - return val | intel_dp->get_aux_send_ctl(intel_dp,
> > - has_aux_irq,
> > - send_bytes,
> > - aux_clock_divider);
> > -}
> > -
> > static int
> > intel_dp_aux_xfer(struct intel_dp *intel_dp,
> > const uint8_t *send, int send_bytes,
> > - uint8_t *recv, int recv_size, bool aksv_write)
> > + uint8_t *recv, int recv_size,
> > + u32 aux_send_ctl_flags)
> > {
> > struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> > struct drm_i915_private *dev_priv =
> > @@ -1145,11 +1127,12 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> > }
> >
> > while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp,
> > clock++))) {
> > - u32 send_ctl = intel_dp_get_aux_send_ctl(intel_dp,
> > -has_aux_irq,
> > -send_bytes,
> > -aux_clock_divider,
> > -aksv_write);
> > + u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
> > + has_aux_irq,
> > + send_bytes,
> > + aux_clock_divider);
> > +
> > + send_ctl |= aux_send_ctl_flags;
> >
> > /* Must try at least 3 times according to DP spec */
> > for (try = 0; try < 5; try++) {
> > @@ -1287,7 +1270,7 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct
> > drm_dp_aux_msg *msg)
> > memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
> >
> > ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
> > - rxbuf, rxsize, false);
> > + rxbuf, rxsize, 0);
> > if (ret > 0) {
> > msg->reply = rxbuf[0] >> 4;
> >
> > @@ -1310,7 +1293,7 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct
> > drm_dp_aux_msg *msg)
> > return -E2BIG;
> >
> > ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
> > - rxbuf, rxsize, false);
> > + rxbuf, rxsize, 0);
> > if (ret > 0) {
> > msg->reply = rxbuf[0] >> 4;
> > /*
> > @@ -5085,7 +5068,7 @@ int intel_dp_hdcp_write_an_aksv(struct
> > intel_digital_port *intel_dig_port,
> > u8 *an)
> > {
> > struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
> > - uint8_t txbuf[4], rxbuf[2], reply = 0;
> > + uint8_t txbuf[4+5] = {}, rxbuf[2], reply = 0;
> You might want to use the macros for size of txbuf as HEADER_SIZE +
> DRM_HDCP_KSV_LEN, as it is done in the next patch.
As the original code was using a bare 5 I figured I'll keep using it here
as well to make it easier to see what's moving where.
> --Ram
> > ssize_t dpcd_ret;
> > int ret;
> >
> > @@ -5110,7 +5093,8 @@ int intel_dp_hdcp_write_an_aksv(struct
> > intel_digital_port *intel_dig_port,
> > txbuf
Re: [Intel-gfx] [PATCH] drm/i915/preemption: Allow preemption between submission ports
Quoting Chris Wilson (2018-02-22 14:11:54)
> Sometimes we need to boost the priority of an in-flight request, which
> may lead to the situation where the second submission port then contains
> a higher priority context than the first and so we need to inject a
> preemption event. To do so we must always check inside
> execlists_dequeue() whether there is a priority inversion between the
> ports themselves as well as the head of the priority sorted queue, and we
> cannot just skip dequeuing if the queue is empty.
Michał noted this doesn't extend past 2-port submission as simply as I
thought it might. Nevertheless it does solve the problem we have today
of priority inversion within ELSP[2]. Extending the submission model as
a whole to more ports is left as an exercise to the reader. :|
-Chris
> Signed-off-by: Chris Wilson
> Cc: Michał Winiarski
> Cc: Michel Thierry
> Cc: Mika Kuoppala
> Cc: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/intel_engine_cs.c | 2 +
> drivers/gpu/drm/i915/intel_guc_submission.c | 17 +--
> drivers/gpu/drm/i915/intel_lrc.c| 161
>
> drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +
> 4 files changed, 107 insertions(+), 78 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> index c31544406974..ce7fcf55ba18 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -423,6 +423,7 @@ static void intel_engine_init_execlist(struct
> intel_engine_cs *engine)
> BUILD_BUG_ON_NOT_POWER_OF_2(execlists_num_ports(execlists));
> GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
>
> + execlists->queue_priority = INT_MIN;
> execlists->queue = RB_ROOT;
> execlists->first = NULL;
> }
> @@ -1903,6 +1904,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
> spin_lock_irq(&engine->timeline->lock);
> list_for_each_entry(rq, &engine->timeline->requests, link)
> print_request(m, rq, "E ");
> + drm_printf(m, "Queue priority: %d\n",
> execlists->queue_priority);
> for (rb = execlists->first; rb; rb = rb_next(rb)) {
> struct i915_priolist *p =
> rb_entry(rb, typeof(*p), node);
> diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
> b/drivers/gpu/drm/i915/intel_guc_submission.c
> index 649113c7a3c2..586dde579903 100644
> --- a/drivers/gpu/drm/i915/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
> @@ -75,6 +75,11 @@
> *
> */
>
> +static inline struct i915_priolist *to_priolist(struct rb_node *rb)
> +{
> + return rb_entry(rb, struct i915_priolist, node);
> +}
> +
> static inline bool is_high_priority(struct intel_guc_client *client)
> {
> return (client->priority == GUC_CLIENT_PRIORITY_KMD_HIGH ||
> @@ -682,15 +687,12 @@ static void guc_dequeue(struct intel_engine_cs *engine)
> rb = execlists->first;
> GEM_BUG_ON(rb_first(&execlists->queue) != rb);
>
> - if (!rb)
> - goto unlock;
> -
> if (port_isset(port)) {
> if (engine->i915->preempt_context) {
> struct guc_preempt_work *preempt_work =
> &engine->i915->guc.preempt_work[engine->id];
>
> - if (rb_entry(rb, struct i915_priolist,
> node)->priority >
> + if (execlists->queue_priority >
> max(port_request(port)->priotree.priority, 0)) {
> execlists_set_active(execlists,
>
> EXECLISTS_ACTIVE_PREEMPT);
> @@ -706,8 +708,8 @@ static void guc_dequeue(struct intel_engine_cs *engine)
> }
> GEM_BUG_ON(port_isset(port));
>
> - do {
> - struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
> + while (rb) {
> + struct i915_priolist *p = to_priolist(rb);
> struct i915_request *rq, *rn;
>
> list_for_each_entry_safe(rq, rn, &p->requests, priotree.link)
> {
> @@ -736,8 +738,9 @@ static void guc_dequeue(struct intel_engine_cs *engine)
> INIT_LIST_HEAD(&p->requests);
> if (p->priority != I915_PRIORITY_NORMAL)
> kmem_cache_free(engine->i915->priorities, p);
> - } while (rb);
> + }
> done:
> + execlists->queue_priority = rb ? to_priolist(rb)->priority : INT_MIN;
> execlists->first = rb;
> if (submit) {
> port_assign(port, last);
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index e781c912f197..8a98da7a5c83 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -169,6 +169,23 @@ static void execlists_init_reg_state(u32 *reg_state,
>
Re: [Intel-gfx] [PATCH 4/4] drm/i915: Don't mangle the CTM on pre-HSW
>-Original Message-
>From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, February 23, 2018 3:13 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Lin, Johnson ; Shankar, Uma
>; Sharma, Shashank
>Subject: [PATCH 4/4] drm/i915: Don't mangle the CTM on pre-HSW
>
>From: Ville Syrjälä
>
>On pre-HSW we have dedicated hardware for the RGB limited range handling, and
>so we don't want to compress with the CSC matrix.
>
>Toss in a FIXME about gamma LUT vs. limited range using the CSC.
>
>Cc: Johnson Lin
>Cc: Uma Shankar
>Cc: Shashank Sharma
>Signed-off-by: Ville Syrjälä
>---
> drivers/gpu/drm/i915/intel_color.c | 16
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_color.c
>b/drivers/gpu/drm/i915/intel_color.c
>index af1e61d3bacd..89ab0f70aa22 100644
>--- a/drivers/gpu/drm/i915/intel_color.c
>+++ b/drivers/gpu/drm/i915/intel_color.c
>@@ -140,6 +140,14 @@ static void ilk_load_csc_matrix(struct drm_crtc_state
>*crtc_state)
> int i, pipe = intel_crtc->pipe;
> uint16_t coeffs[9] = { 0, };
> struct intel_crtc_state *intel_crtc_state =
> to_intel_crtc_state(crtc_state);
>+ bool limited_color_range = false;
>+
>+ /*
>+ * FIXME if there's a gamma LUT after the CSC, we should
>+ * do the range compression using the gamma LUT instead.
>+ */
>+ if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
>+ limited_color_range = intel_crtc_state->limited_color_range;
>
Hi Ville,
For VLV or similar platforms (having dedicated color range h/w) for
limited_range this matrix
would have been getting used. Though they have a dedicated h/w but I don't
think it's getting
programmed currently. Not sure, with removing this CSC scaling logic, it may
break the
limited_color scenarios on those platforms. I believe using the dedicated h/w
or this scaled_down
CSC should be giving similar results making the things work currently. Not sure
if we are using
any limited_range combinations on those platforms though :)
Regards,
Uma Shankar
> if (intel_crtc_state->ycbcr420) {
> ilk_load_ycbcr_conversion_matrix(intel_crtc);
>@@ -150,7 +158,7 @@ static void ilk_load_csc_matrix(struct drm_crtc_state
>*crtc_state)
> const u64 *input;
> u64 temp[9];
>
>- if (intel_crtc_state->limited_color_range)
>+ if (limited_color_range)
> input = ctm_mult_by_limited(temp, ctm->matrix);
> else
> input = ctm->matrix;
>@@ -200,7 +208,7 @@ static void ilk_load_csc_matrix(struct drm_crtc_state
>*crtc_state)
>* into consideration.
>*/
> for (i = 0; i < 3; i++) {
>- if (intel_crtc_state->limited_color_range)
>+ if (limited_color_range)
> coeffs[i * 3 + i] =
> ILK_CSC_COEFF_LIMITED_RANGE;
> else
>@@ -224,7 +232,7 @@ static void ilk_load_csc_matrix(struct drm_crtc_state
>*crtc_state)
> if (INTEL_GEN(dev_priv) > 6) {
> uint16_t postoff = 0;
>
>- if (intel_crtc_state->limited_color_range)
>+ if (limited_color_range)
> postoff = (16 * (1 << 12) / 255) & 0x1fff;
>
> I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); @@ -235,7
>+243,7 @@ static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state)
> } else {
> uint32_t mode = CSC_MODE_YUV_TO_RGB;
>
>- if (intel_crtc_state->limited_color_range)
>+ if (limited_color_range)
> mode |= CSC_BLACK_SCREEN_OFFSET;
>
> I915_WRITE(PIPE_CSC_MODE(pipe), mode);
>--
>2.16.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/4] drm/i915: Rename pipe CSC to use ilk_ prefix
>-Original Message-
>From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, February 23, 2018 3:13 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Lin, Johnson ; Shankar, Uma
>; Sharma, Shashank
>Subject: [PATCH 3/4] drm/i915: Rename pipe CSC to use ilk_ prefix
>
>From: Ville Syrjälä
>
>The pipe CSC was introduced by ILK, so change everything related to use ilk_ as
>the prefix.
>
Looks ok to me.
Reviewed-by: Uma Shankar
>Cc: Johnson Lin
>Cc: Uma Shankar
>Cc: Shashank Sharma
>Signed-off-by: Ville Syrjälä
>---
> drivers/gpu/drm/i915/intel_color.c | 39 +++---
> 1 file changed, 19 insertions(+), 20 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_color.c
>b/drivers/gpu/drm/i915/intel_color.c
>index c9af260be113..af1e61d3bacd 100644
>--- a/drivers/gpu/drm/i915/intel_color.c
>+++ b/drivers/gpu/drm/i915/intel_color.c
>@@ -66,13 +66,13 @@
> * of the CTM coefficient and we write the value from bit 3. We also round the
> * value.
> */
>-#define I9XX_CSC_COEFF_FP(coeff, fbits) \
>+#define ILK_CSC_COEFF_FP(coeff, fbits)\
> (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
>
>-#define I9XX_CSC_COEFF_LIMITED_RANGE \
>- I9XX_CSC_COEFF_FP(CTM_COEFF_LIMITED_RANGE, 9)
>-#define I9XX_CSC_COEFF_1_0\
>- ((7 << 12) | I9XX_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
>+#define ILK_CSC_COEFF_LIMITED_RANGE \
>+ ILK_CSC_COEFF_FP(CTM_COEFF_LIMITED_RANGE, 9)
>+#define ILK_CSC_COEFF_1_0 \
>+ ((7 << 12) | ILK_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
>
> static bool crtc_state_is_legacy_gamma(struct drm_crtc_state *state) { @@ -
>108,7 +108,7 @@ static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
> return result;
> }
>
>-static void i9xx_load_ycbcr_conversion_matrix(struct intel_crtc *intel_crtc)
>+static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc
>+*intel_crtc)
> {
> int pipe = intel_crtc->pipe;
> struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); @@ -
>132,8 +132,7 @@ static void i9xx_load_ycbcr_conversion_matrix(struct
>intel_crtc *intel_crtc)
> I915_WRITE(PIPE_CSC_MODE(pipe), 0);
> }
>
>-/* Set up the pipe CSC unit. */
>-static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)
>+static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state)
> {
> struct drm_crtc *crtc = crtc_state->crtc;
> struct drm_i915_private *dev_priv = to_i915(crtc->dev); @@ -143,7
>+142,7 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)
> struct intel_crtc_state *intel_crtc_state =
> to_intel_crtc_state(crtc_state);
>
> if (intel_crtc_state->ycbcr420) {
>- i9xx_load_ycbcr_conversion_matrix(intel_crtc);
>+ ilk_load_ycbcr_conversion_matrix(intel_crtc);
> return;
> } else if (crtc_state->ctm) {
> struct drm_color_ctm *ctm =
>@@ -175,21 +174,21 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state
>*crtc_state)
>
> if (abs_coeff < CTM_COEFF_0_125)
> coeffs[i] |= (3 << 12) |
>- I9XX_CSC_COEFF_FP(abs_coeff, 12);
>+ ILK_CSC_COEFF_FP(abs_coeff, 12);
> else if (abs_coeff < CTM_COEFF_0_25)
> coeffs[i] |= (2 << 12) |
>- I9XX_CSC_COEFF_FP(abs_coeff, 11);
>+ ILK_CSC_COEFF_FP(abs_coeff, 11);
> else if (abs_coeff < CTM_COEFF_0_5)
> coeffs[i] |= (1 << 12) |
>- I9XX_CSC_COEFF_FP(abs_coeff, 10);
>+ ILK_CSC_COEFF_FP(abs_coeff, 10);
> else if (abs_coeff < CTM_COEFF_1_0)
>- coeffs[i] |= I9XX_CSC_COEFF_FP(abs_coeff, 9);
>+ coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
> else if (abs_coeff < CTM_COEFF_2_0)
> coeffs[i] |= (7 << 12) |
>- I9XX_CSC_COEFF_FP(abs_coeff, 8);
>+ ILK_CSC_COEFF_FP(abs_coeff, 8);
> else
> coeffs[i] |= (6 << 12) |
>- I9XX_CSC_COEFF_FP(abs_coeff, 7);
>+ ILK_CSC_COEFF_FP(abs_coeff, 7);
> }
> } else {
> /*
>@@ -203,9 +202,9 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state
>*crtc_state)
> for (i = 0; i < 3; i++) {
> if (intel_crtc_state->limited_color_range)
> coeffs[i * 3 + i] =
>- I9XX_CSC_COEFF_LIMITED_RANGE;
>+ ILK_CSC_COEFF_LIMITED_RANGE;
>
Re: [Intel-gfx] [PATCH 2/4] drm/i915: Remove the pointless 1:1 matrix copy
>-Original Message-
>From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, February 23, 2018 3:13 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Lin, Johnson ; Shankar, Uma
>; Sharma, Shashank
>Subject: [PATCH 2/4] drm/i915: Remove the pointless 1:1 matrix copy
>
>From: Ville Syrjälä
>
>If we don't have to frob with the user provided ctm matrix there's no point in
>copying it over. Just point at the user ctm directly.
>
>Also the matrix gets fully populated by ctm_mult_by_limited() so no need to
>zero
>initialize it.
>
Looks ok to me.
Reviewed-by: Uma Shankar
>Cc: Johnson Lin
>Cc: Uma Shankar
>Cc: Shashank Sharma
>Signed-off-by: Ville Syrjälä
>---
> drivers/gpu/drm/i915/intel_color.c | 17 +
> 1 file changed, 9 insertions(+), 8 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_color.c
>b/drivers/gpu/drm/i915/intel_color.c
>index a383d993b844..c9af260be113 100644
>--- a/drivers/gpu/drm/i915/intel_color.c
>+++ b/drivers/gpu/drm/i915/intel_color.c
>@@ -86,7 +86,7 @@ static bool crtc_state_is_legacy_gamma(struct
>drm_crtc_state *state)
> * When using limited range, multiply the matrix given by userspace by
> * the matrix that we would use for the limited range.
> */
>-static void ctm_mult_by_limited(u64 *result, const u64 *input)
>+static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
> {
> int i;
>
>@@ -104,6 +104,8 @@ static void ctm_mult_by_limited(u64 *result, const u64
>*input)
> result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30;
> result[i] |= user_coeff & CTM_COEFF_SIGN;
> }
>+
>+ return result;
> }
>
> static void i9xx_load_ycbcr_conversion_matrix(struct intel_crtc *intel_crtc)
> @@
>-146,14 +148,13 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state
>*crtc_state)
> } else if (crtc_state->ctm) {
> struct drm_color_ctm *ctm =
> (struct drm_color_ctm *)crtc_state->ctm->data;
>- uint64_t input[9] = { 0, };
>+ const u64 *input;
>+ u64 temp[9];
>
>- if (intel_crtc_state->limited_color_range) {
>- ctm_mult_by_limited(input, ctm->matrix);
>- } else {
>- for (i = 0; i < ARRAY_SIZE(input); i++)
>- input[i] = ctm->matrix[i];
>- }
>+ if (intel_crtc_state->limited_color_range)
>+ input = ctm_mult_by_limited(temp, ctm->matrix);
>+ else
>+ input = ctm->matrix;
>
> /*
>* Convert fixed point S31.32 input to format supported by the
>--
>2.16.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] drm/uapi: The ctm matrix uses sign-magnitude representation
>-Original Message-
>From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, February 23, 2018 3:12 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: dri-de...@lists.freedesktop.org; Mihail Atanassov
>; Liviu Dudau ; Brian
>Starkey ; Mali DP Maintainers
>; Lin, Johnson ; Shankar, Uma
>; Sharma, Shashank
>Subject: [PATCH 1/4] drm/uapi: The ctm matrix uses sign-magnitude
>representation
>
>From: Ville Syrjälä
>
>The documentation for the ctm matrix suggests a two's complement format, but
>at least the i915 implementation is using sign-magnitude instead. And looks
>like
>malidp is doing the same. Change the docs to match the current implementation,
>and change the type from __s64 to __u64 to drive the point home.
>
Looks ok to me.
Reviewed-by: Uma Shankar
>Cc: dri-de...@lists.freedesktop.org
>Cc: Mihail Atanassov
>Cc: Liviu Dudau
>Cc: Brian Starkey
>Cc: Mali DP Maintainers
>Cc: Johnson Lin
>Cc: Uma Shankar
>Cc: Shashank Sharma
>Signed-off-by: Ville Syrjälä
>---
> include/uapi/drm/drm_mode.h | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
>diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
>index 2c575794fb52..b5d7d9e0eff5 100644
>--- a/include/uapi/drm/drm_mode.h
>+++ b/include/uapi/drm/drm_mode.h
>@@ -598,8 +598,11 @@ struct drm_mode_crtc_lut { };
>
> struct drm_color_ctm {
>- /* Conversion matrix in S31.32 format. */
>- __s64 matrix[9];
>+ /*
>+ * Conversion matrix in S31.32 sign-magnitude
>+ * (not two's complement!) format.
>+ */
>+ __u64 matrix[9];
> };
>
> struct drm_color_lut {
>--
>2.16.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] tests/perf_pmu: Handle CPU hotplug failures better
On Fri, Feb 23, 2018 at 11:34:53AM +, Tvrtko Ursulin wrote:
> From: Chris Wilson
>
> CPU hotplug, especially CPU0, can be flaky on commodity hardware.
>
> To improve test reliability and reponse times when testing larger runs we
> need to handle those cases better.
>
> Handle failures to off-line a CPU by immediately skipping the test, and
> failures to on-line a CPU by immediately rebooting the machine.
>
> This patch includes igt_sysrq_reboot implementation from Chris Wilson.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Chris Wilson
> ---
> lib/Makefile.sources | 2 ++
> lib/igt_sysrq.c | 22 ++
> lib/igt_sysrq.h | 30 ++
> lib/meson.build | 2 ++
> tests/perf_pmu.c | 42 ++
> 5 files changed, 90 insertions(+), 8 deletions(-)
> create mode 100644 lib/igt_sysrq.c
> create mode 100644 lib/igt_sysrq.h
>
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> index 5b13ef8896c0..3d37ef1d1984 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -35,6 +35,8 @@ lib_source_list = \
> igt_stats.h \
> igt_sysfs.c \
> igt_sysfs.h \
> + igt_sysrq.c \
> + igt_sysrq.h \
> igt_x86.h \
> igt_x86.c \
> igt_vgem.c \
> diff --git a/lib/igt_sysrq.c b/lib/igt_sysrq.c
> new file mode 100644
> index ..fe3d2e344ff1
> --- /dev/null
> +++ b/lib/igt_sysrq.c
> @@ -0,0 +1,22 @@
> +#include
> +#include
> +#include
> +#include
> +
> +#include "igt_core.h"
> +
> +#include "igt_sysrq.h"
> +
> +void igt_sysrq_reboot(void)
> +{
> + sync();
> +
> + /* Try to be nice at first, and if that fails pull the trigger */
> + if (reboot(RB_AUTOBOOT)) {
> + int fd = open("/proc/sysrq-trigger", O_WRONLY);
> + igt_ignore_warn(write(fd, "b", 2));
> + close(fd);
> + }
> +
> + abort();
> +}
While the cause for taking this action might be dire, rebooting
people's machines can be kind of a dick move, even considering they're
running tests that can be fatal to the machine in other ways.
We have IGT_HANG and IGT_HANG_WITHOUT_RESET so the users can opt
in/out of some fatal behaviour already. I'm fine with auto-rebooting,
even as the default, if users can opt out of it with
IGT_NO_REBOOT_PRETTY_PLEASE or so.
--
Petri Latvala
> diff --git a/lib/igt_sysrq.h b/lib/igt_sysrq.h
> new file mode 100644
> index ..422473d2a480
> --- /dev/null
> +++ b/lib/igt_sysrq.h
> @@ -0,0 +1,30 @@
> +/*
> + * Copyright © 2018 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#ifndef __IGT_SYSRQ_H__
> +#define __IGT_SYSRQ_H__
> +
> +void igt_sysrq_reboot(void) __attribute__((noreturn));
> +
> +#endif /* __IGT_SYSRQ_H__ */
> diff --git a/lib/meson.build b/lib/meson.build
> index 8f14f6320ecf..63afd3ddb535 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -22,6 +22,7 @@ lib_headers = [
> 'igt_stats.h',
> 'igt_syncobj.h',
> 'igt_sysfs.h',
> + 'igt_sysrq.h',
> 'igt_x86.h',
> 'igt_vgem.h',
> 'instdone.h',
> @@ -69,6 +70,7 @@ lib_sources = [
> 'igt_stats.c',
> 'igt_syncobj.c',
> 'igt_sysfs.c',
> + 'igt_sysrq.c',
> 'igt_vgem.c',
> 'igt_x86.c',
> 'instdone.c',
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index 3bbb18d2f216..658d0976137f 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -41,6 +41,7 @@
> #include "igt_core.h"
> #include "igt_perf.h"
> #include "igt_sysfs.h"
> +#include "igt_sysrq.h"
> #include "igt_pm.h"
> #include "sw_sync.h"
>
> @@ -965,6 +966,7 @@ static void cpu_hotplug(int gem_fd)
> int link[2];
> int fd, ret;
> int cur
[Intel-gfx] [PATCH i-g-t] tests/perf_pmu: Handle CPU hotplug failures better
From: Chris Wilson
CPU hotplug, especially CPU0, can be flaky on commodity hardware.
To improve test reliability and reponse times when testing larger runs we
need to handle those cases better.
Handle failures to off-line a CPU by immediately skipping the test, and
failures to on-line a CPU by immediately rebooting the machine.
This patch includes igt_sysrq_reboot implementation from Chris Wilson.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
---
lib/Makefile.sources | 2 ++
lib/igt_sysrq.c | 22 ++
lib/igt_sysrq.h | 30 ++
lib/meson.build | 2 ++
tests/perf_pmu.c | 42 ++
5 files changed, 90 insertions(+), 8 deletions(-)
create mode 100644 lib/igt_sysrq.c
create mode 100644 lib/igt_sysrq.h
diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 5b13ef8896c0..3d37ef1d1984 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -35,6 +35,8 @@ lib_source_list = \
igt_stats.h \
igt_sysfs.c \
igt_sysfs.h \
+ igt_sysrq.c \
+ igt_sysrq.h \
igt_x86.h \
igt_x86.c \
igt_vgem.c \
diff --git a/lib/igt_sysrq.c b/lib/igt_sysrq.c
new file mode 100644
index ..fe3d2e344ff1
--- /dev/null
+++ b/lib/igt_sysrq.c
@@ -0,0 +1,22 @@
+#include
+#include
+#include
+#include
+
+#include "igt_core.h"
+
+#include "igt_sysrq.h"
+
+void igt_sysrq_reboot(void)
+{
+ sync();
+
+ /* Try to be nice at first, and if that fails pull the trigger */
+ if (reboot(RB_AUTOBOOT)) {
+ int fd = open("/proc/sysrq-trigger", O_WRONLY);
+ igt_ignore_warn(write(fd, "b", 2));
+ close(fd);
+ }
+
+ abort();
+}
diff --git a/lib/igt_sysrq.h b/lib/igt_sysrq.h
new file mode 100644
index ..422473d2a480
--- /dev/null
+++ b/lib/igt_sysrq.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __IGT_SYSRQ_H__
+#define __IGT_SYSRQ_H__
+
+void igt_sysrq_reboot(void) __attribute__((noreturn));
+
+#endif /* __IGT_SYSRQ_H__ */
diff --git a/lib/meson.build b/lib/meson.build
index 8f14f6320ecf..63afd3ddb535 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -22,6 +22,7 @@ lib_headers = [
'igt_stats.h',
'igt_syncobj.h',
'igt_sysfs.h',
+ 'igt_sysrq.h',
'igt_x86.h',
'igt_vgem.h',
'instdone.h',
@@ -69,6 +70,7 @@ lib_sources = [
'igt_stats.c',
'igt_syncobj.c',
'igt_sysfs.c',
+ 'igt_sysrq.c',
'igt_vgem.c',
'igt_x86.c',
'instdone.c',
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 3bbb18d2f216..658d0976137f 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -41,6 +41,7 @@
#include "igt_core.h"
#include "igt_perf.h"
#include "igt_sysfs.h"
+#include "igt_sysrq.h"
#include "igt_pm.h"
#include "sw_sync.h"
@@ -965,6 +966,7 @@ static void cpu_hotplug(int gem_fd)
int link[2];
int fd, ret;
int cur = 0;
+ char buf;
igt_skip_on(IS_BROXTON(intel_get_drm_devid(gem_fd)));
igt_require(cpu0_hotplug_support());
@@ -994,7 +996,7 @@ static void cpu_hotplug(int gem_fd)
for (;;) {
char name[128];
- int cpufd;
+ int cpufd, ret;
igt_assert_lt(snprintf(name, sizeof(name),
"/sys/devices/system/cpu/cpu%d/online",
@@ -1011,9 +1013,33 @@ static void cpu_hotplug(int gem_fd)
}
/* Offline followed by online a CPU. */
- igt_assert_eq(write(cpufd, "0", 2), 2);
+
+
