[Intel-gfx] [PATCH v4 1/2] drm/i915: Add modular FIA
From: Anusha Srivatsa
Some platforms may have Modular FIA. If Modular FIA is used in the SOC,
then Display Driver will access the additional instances of
FIA based on pre-assigned offset in GTTMADDR space.
Each Modular FIA instance has its own IOSF Sideband Port ID
and it houses only 2 Type-C Port. In SOC that has more than
two Type-C Ports, there are multiple instances of Modular FIA.
Gunit will need to use different destination ID when it access
different pair of Type-C Port.
The DFLEXDPSP register has Modular FIA bit starting on Tiger Lake. If
Modular FIA is used in the SOC, this register bit exists in all the
instances of Modular FIA. IOM FW is required to program only the MF bit
in first FIA instance that houses the Type-C Port 0 and Port 1, for
Display Driver to read from.
v2 (Lucas):
- Move all accesses to FIA to be contained in intel_tc.c, along with
display_fia that is now called tc_phy_fia
- Save the fia instance number on intel_digital_port, so we don't have
to query if modular FIA is used on every access
v3 (Lucas): Make function static
v4 (Lucas): Move enum phy_fia to the header and use it in
intel_digital_port (suggested by Ville)
v5 (Lucas): Add comment about the mapping between FIA and TC port
(suggested by Stuart)
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
Signed-off-by: Lucas De Marchi
Acked-by: Ville Syrjälä
Reviewed-by: Stuart Summers
---
drivers/gpu/drm/i915/display/intel_display.h | 6 +++
drivers/gpu/drm/i915/display/intel_tc.c | 47
drivers/gpu/drm/i915/i915_reg.h | 13 --
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
5 files changed, 56 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 67743eea4a50..d2c718f25478 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -260,6 +260,12 @@ enum phy {
#define phy_name(a) ((a) + 'A')
+enum phy_fia {
+ FIA1,
+ FIA2,
+ FIA3,
+};
+
#define for_each_pipe(__dev_priv, __p) \
for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index f44ee4bfe7c8..c96a81c2416c 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -22,6 +22,28 @@ static const char *tc_port_mode_name(enum tc_port_mode mode)
return names[mode];
}
+static bool has_modular_fia(struct drm_i915_private *i915)
+{
+ if (!INTEL_INFO(i915)->display.has_modular_fia)
+ return false;
+
+ return intel_uncore_read(>uncore,
+PORT_TX_DFLEXDPSP(FIA1)) & MODULAR_FIA_MASK;
+}
+
+static enum phy_fia tc_port_to_fia(struct drm_i915_private *i915,
+ enum tc_port tc_port)
+{
+ if (!has_modular_fia(i915))
+ return FIA1;
+
+ /*
+* Each Modular FIA instance houses 2 TC ports. In SOC that has more
+* than two TC ports, there are multiple instances of Modular FIA.
+*/
+ return tc_port / 2;
+}
+
u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@@ -29,7 +51,8 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port
*dig_port)
struct intel_uncore *uncore = >uncore;
u32 lane_mask;
- lane_mask = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
+ lane_mask = intel_uncore_read(uncore,
+ PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
WARN_ON(lane_mask == 0x);
@@ -78,7 +101,8 @@ void intel_tc_port_set_fia_lane_count(struct
intel_digital_port *dig_port,
WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
- val = intel_uncore_read(uncore, PORT_TX_DFLEXDPMLE1);
+ val = intel_uncore_read(uncore,
+ PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
switch (required_lanes) {
@@ -97,7 +121,8 @@ void intel_tc_port_set_fia_lane_count(struct
intel_digital_port *dig_port,
MISSING_CASE(required_lanes);
}
- intel_uncore_write(uncore, PORT_TX_DFLEXDPMLE1, val);
+ intel_uncore_write(uncore,
+ PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val);
}
static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
@@ -129,7 +154,8 @@ static u32 tc_port_live_status_mask(struct
intel_digital_port *dig_port)
u32 mask = 0;
u32 val;
- val = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
+ val = intel_uncore_read(uncore,
+ PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
if (val ==
[Intel-gfx] [PATCH v4 2/2] drm/i915/tgl: add modular FIA to device info
Tiger Lake has modular FIA bit indicating if we are using it, so add to
the device info.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e83c94cf2744..7ec8170f1794 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -790,6 +790,7 @@ static const struct intel_device_info
intel_tigerlake_12_info = {
PLATFORM(INTEL_TIGERLAKE),
.num_pipes = 4,
.require_force_probe = 1,
+ .display.has_modular_fia = 1,
.engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
};
--
2.21.0
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 0/2] Modular FIA
https://patchwork.freedesktop.org/series/63175/ Changes: - Add comment explaining mapping port <-> FIA - Add commit to apply modular FIA on TGL Anusha Srivatsa (1): drm/i915: Add modular FIA Lucas De Marchi (1): drm/i915/tgl: add modular FIA to device info drivers/gpu/drm/i915/display/intel_display.h | 6 +++ drivers/gpu/drm/i915/display/intel_tc.c | 47 drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 13 -- drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_drv.h | 1 + 6 files changed, 57 insertions(+), 12 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/4] drm/i915: Fix WaProgramMgsrForL3BankSpecificMmioReads
On 12/07/2019 00:51, Summers, Stuart wrote:
On Thu, 2019-07-11 at 16:59 +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
This is generally much more readable than the previous implementation,
thanks! Some minor comments below...
Two issues in this code:
1.
fls() usage is incorrect causing off by one in subslice mask lookup,
which in other words means subslice mask of all zeroes is always used
(subslice mask of a slice which is not present, or even out of bounds
array access), rendering the checks in wa_init_mcr either futile or
random.
2.
Condition in WARN_ON is not correct. It is doing a bitwise and
operation
between a positive (present subslices) and negative mask (disabled L3
banks).
This means that with corrected fls() usage the assert would always
incorrectly fail.
We can fix this by inverting the fuse bits in the check.
v2:
* Simplify check for logic and redability.
* Improve commentary explaining what is really happening ie. what
the
assert is really trying to check and why.
Signed-off-by: Tvrtko Ursulin
Fixes: fe864b76c2ab ("drm/i915: Implement
WaProgramMgsrForL3BankSpecificMmioReads")
Reviewed-by: Chris Wilson # v1
Cc: Michał Winiarski
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 80 ++-
--
1 file changed, 40 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 9e069286d3ce..80f1159e5cda 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -761,7 +761,27 @@ static void
wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
const struct sseu_dev_info *sseu = _INFO(i915)->sseu;
- u32 mcr_slice_subslice_mask;
+ u32 mcr_mask, mcr;
+
+ /*
+* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
+* Before any MMIO read into slice/subslice specific registers,
MCR
+* packet control register needs to be programmed to point to
any
+* enabled s/ss pair. Otherwise, incorrect values will be
returned.
+* This means each subsequent MMIO read will be forwarded to an
+* specific s/ss combination, but this is OK since these
registers
+* are consistent across s/ss in almost all cases. In the rare
+* occasions, such as INSTDONE, where this value is dependent
+* on s/ss combo, the read should be done with
read_subslice_reg.
+*/
+ mcr = intel_calculate_mcr_s_ss_select(i915);
+
+ if (INTEL_GEN(i915) >= 11)
+ mcr_mask = GEN11_MCR_SLICE_MASK |
GEN11_MCR_SUBSLICE_MASK;
+ else
+ mcr_mask = GEN8_MCR_SLICE_MASK |
GEN8_MCR_SUBSLICE_MASK;
+
+ wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
Was there a specific reason to move this up to the top? Or this is
Yes, so below can check the actually selected MCR instead of deriving it
from slice/subslice mask as stored in the driver.
purely to move this functionality all together rather than spread out
through the function? Looking at the documentation, we do want to
specifically apply WaProgramMgsrForL3BankSpecificMmioReads before any
other workarounds. So maybe just move this whole block to the bottom of
the function instead?
I think it works better if MCR selection is first. Going forward, and
for robustness, this probably needs to be improved to do both
workarounds in a single block. Along the lines of ffs(ss_ena & l3_ena).
And WARN_ON if no common bits. Oh well.. now I got no excuses not to do
it...
/*
* WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
@@ -776,49 +796,29 @@ wa_init_mcr(struct drm_i915_private *i915,
struct i915_wa_list *wal)
* something more complex that requires checking the range of
every
* MMIO read).
*/
- if (INTEL_GEN(i915) >= 10 &&
- is_power_of_2(sseu->slice_mask)) {
+ if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
/*
-* read FUSE3 for enabled L3 Bank IDs, if L3 Bank
matches
-* enabled subslice, no need to redirect MCR packet
+* GEN8_MCR_SELECTOR contains dual-purpose bits which
select
+* both to which subslice, or to which L3 bank, the
respective
+* mmio reads will go.
+* Since we have selected one enabled subslice in
+* WaProgramMgsrForCorrectSliceSpecificMmioReads, we
now
+* need to check if the L3 bank of the equal "instance"
is also
+* enabled.
+* If that is not the case we could try to find a
number which
+* works for both, or going even further, implement a
dynamic
+* scheme where we switch at before every affected mmio
s/at //?
read.
+* Fortunately neither seems to be needed at the moment
for
+* current parts and current driver
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Drop extern qualifiers from header function prototypes (rev2)
== Series Details == Series: drm/i915: Drop extern qualifiers from header function prototypes (rev2) URL : https://patchwork.freedesktop.org/series/63508/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6456_full -> Patchwork_13617_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13617_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13617_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13617_full: ### IGT changes ### Possible regressions * igt@gem_mmap_gtt@forked-big-copy-odd: - shard-kbl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6456/shard-kbl2/igt@gem_mmap_...@forked-big-copy-odd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13617/shard-kbl6/igt@gem_mmap_...@forked-big-copy-odd.html Known issues Here are the changes found in Patchwork_13617_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_tiled_swapping@non-threaded: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108686]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6456/shard-apl5/igt@gem_tiled_swapp...@non-threaded.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13617/shard-apl3/igt@gem_tiled_swapp...@non-threaded.html * igt@kms_flip@flip-vs-suspend: - shard-glk: [PASS][5] -> [INCOMPLETE][6] ([fdo#103359] / [k.org#198133]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6456/shard-glk8/igt@kms_f...@flip-vs-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13617/shard-glk2/igt@kms_f...@flip-vs-suspend.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6456/shard-apl1/igt@kms_f...@flip-vs-suspend-interruptible.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13617/shard-apl4/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_flip@modeset-vs-vblank-race: - shard-glk: [PASS][9] -> [FAIL][10] ([fdo#103060]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6456/shard-glk2/igt@kms_f...@modeset-vs-vblank-race.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13617/shard-glk2/igt@kms_f...@modeset-vs-vblank-race.html * igt@kms_flip@plain-flip-fb-recreate-interruptible: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#100368]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6456/shard-skl4/igt@kms_f...@plain-flip-fb-recreate-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13617/shard-skl2/igt@kms_f...@plain-flip-fb-recreate-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +6 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6456/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13617/shard-iclb7/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6456/shard-skl8/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13617/shard-skl5/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109642] / [fdo#111068]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6456/shard-iclb2/igt@kms_psr2...@frontbuffer.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13617/shard-iclb4/igt@kms_psr2...@frontbuffer.html * igt@kms_setmode@basic: - shard-kbl: [PASS][19] -> [FAIL][20] ([fdo#99912]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6456/shard-kbl6/igt@kms_setm...@basic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13617/shard-kbl1/igt@kms_setm...@basic.html * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend: - shard-kbl: [PASS][21] -> [INCOMPLETE][22] ([fdo#103665]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6456/shard-kbl7/igt@kms_vbl...@pipe-a-ts-continuation-dpms-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13617/shard-kbl3/igt@kms_vbl...@pipe-a-ts-continuation-dpms-suspend.html Possible fixes *
Re: [Intel-gfx] [igt-dev] [PATCH V6 i-g-t 3/6] lib: Add function to hash a framebuffer
On 07/10, Ser, Simon wrote:
> On Wed, 2019-07-10 at 15:30 +, Ser, Simon wrote:
> > Mostly LGTM, here are a few nits.
> >
> > On Wed, 2019-06-12 at 23:17 -0300, Brian Starkey wrote:
> > > To use writeback buffers as a CRC source, we need to be able to hash
> > > them. Implement a simple FVA-1a hashing routine for this purpose.
> > >
> > > Doing a bytewise hash on the framebuffer directly can be very slow if
> > > the memory is noncached. By making a copy of each line in the FB first
> > > (which can take advantage of word-access speedup), we can do the hash
> > > on a cached copy, which is much faster (10x speedup on my platform).
> > >
> > > v6: use igt_memcpy_from_wc() instead of plain memcpy, as suggested by
> > > Chris Wilson
> > >
> > > Signed-off-by: Brian Starkey
> > > [rebased and updated to the most recent API]
> > > Signed-off-by: Liviu Dudau
> > > ---
> > > lib/igt_fb.c | 66
> > > lib/igt_fb.h | 3 +++
> > > 2 files changed, 69 insertions(+)
> > >
> > > diff --git a/lib/igt_fb.c b/lib/igt_fb.c
> > > index 9d4f905e..d07dae39 100644
> > > --- a/lib/igt_fb.c
> > > +++ b/lib/igt_fb.c
> > > @@ -3256,6 +3256,72 @@ bool igt_fb_supported_format(uint32_t drm_format)
> > > return false;
> > > }
> > >
> > > +/*
> > > + * This implements the FNV-1a hashing algorithm instead of CRC, for
> > > + * simplicity
> > > + * http://www.isthe.com/chongo/tech/comp/fnv/index.html
> > > + *
> > > + * hash = offset_basis
> > > + * for each octet_of_data to be hashed
> > > + * hash = hash xor octet_of_data
> > > + * hash = hash * FNV_prime
> > > + * return hash
> > > + *
> > > + * 32 bit offset_basis = 2166136261
> > > + * 32 bit FNV_prime = 224 + 28 + 0x93 = 16777619
> > > + */
> > > +int igt_fb_get_crc(struct igt_fb *fb, igt_crc_t *crc)
> > > +{
> > > +#define FNV1a_OFFSET_BIAS 2166136261
> > > +#define FNV1a_PRIME 16777619
> >
> > I'd just use plain uint32_t variables for those, but no big deal.
> >
> > > + uint32_t hash;
> > > + void *map;
> > > + char *ptr, *line = NULL;
> > > + int x, y, cpp = igt_drm_format_to_bpp(fb->drm_format) / 8;
> > > + uint32_t stride = calc_plane_stride(fb, 0);
> >
> > We could return -EINVAL in case fb->num_planes != 1.
>
> Let's not waste cycles. With this ^ fixed, this patch is:
>
> Reviewed-by: Simon Ser
>
> Other nits are optional.
I agreed with all your suggestions, and I already applied all of them.
Should I wait for the other patches review, or should I resend the new
version?
Thanks for all the feedback
Best Regards
> > > + if (fb->is_dumb)
> > > + map = kmstest_dumb_map_buffer(fb->fd, fb->gem_handle, fb->size,
> > > + PROT_READ);
> > > + else
> > > + map = gem_mmap__gtt(fb->fd, fb->gem_handle, fb->size,
> > > + PROT_READ);
> > > + ptr = map;
> >
> > Nit: no need for this, can assign the result of mmap directly to ptr.
> >
> > > +
> > > + /*
> > > + * Framebuffers are often uncached, which can make byte-wise accesses
> > > + * very slow. We copy each line of the FB into a local buffer to speed
> > > + * up the hashing.
> > > + */
> > > + line = malloc(stride);
> > > + if (!line) {
> > > + munmap(map, fb->size);
> > > + return -ENOMEM;
> > > + }
> > > +
> > > + hash = FNV1a_OFFSET_BIAS;
> > > +
> > > + for (y = 0; y < fb->height; y++, ptr += stride) {
> > > +
> > > + igt_memcpy_from_wc(line, ptr, stride);
> >
> > Nit: no need to copy the whole stride actually, we can just copy
> > fb->width * cpp since we're only going to read that.
> >
> > > +
> > > + for (x = 0; x < fb->width * cpp; x++) {
> > > + hash ^= line[x];
> > > + hash *= FNV1a_PRIME;
> > > + }
> > > + }
> > > +
> > > + crc->n_words = 1;
> > > + crc->crc[0] = hash;
> > > +
> > > + free(line);
> > > + munmap(map, fb->size);
> > > +
> > > + return 0;
> > > +#undef FNV1a_OFFSET_BIAS
> > > +#undef FNV1a_PRIME
> > > +}
> > > +
> > > /**
> > > * igt_format_is_yuv:
> > > * @drm_format: drm fourcc
> > > diff --git a/lib/igt_fb.h b/lib/igt_fb.h
> > > index adefebe1..a2741c05 100644
> > > --- a/lib/igt_fb.h
> > > +++ b/lib/igt_fb.h
> > > @@ -37,6 +37,7 @@
> > > #include
> > >
> > > #include "igt_color_encoding.h"
> > > +#include "igt_debugfs.h"
> > >
> > > /*
> > > * Internal format to denote a buffer compatible with pixman's
> > > @@ -194,5 +195,7 @@ int igt_format_plane_bpp(uint32_t drm_format, int
> > > plane);
> > > void igt_format_array_fill(uint32_t **formats_array, unsigned int *count,
> > > bool allow_yuv);
> > >
> > > +int igt_fb_get_crc(struct igt_fb *fb, igt_crc_t *crc);
> > > +
> > > #endif /* __IGT_FB_H__ */
> > >
> > > ___
> > > igt-dev mailing list
> > > igt-...@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/igt-dev
> >
Re: [Intel-gfx] [igt-dev] [PATCH V6 i-g-t 2/6] kms_writeback: Add initial writeback tests
On 07/10, Ser, Simon wrote:
> Hi,
>
> Thanks for the patch! Here are a few comments.
>
> For bonus points, it would be nice to add igt_describe descriptions of
> each sub-test.
Hi Simon,
First of all, thanks for your feedback; I already applied most of your
suggestions. I just have some inline comments/questions.
> On Wed, 2019-06-12 at 23:16 -0300, Brian Starkey wrote:
> > Add tests for the WRITEBACK_PIXEL_FORMATS, WRITEBACK_OUT_FENCE_PTR and
> > WRITEBACK_FB_ID properties on writeback connectors, ensuring their
> > behaviour is correct.
> >
> > Signed-off-by: Brian Starkey
> > [rebased and updated do_writeback_test() function to address feedback]
> > Signed-off-by: Liviu Dudau
> > ---
> > tests/Makefile.sources | 1 +
> > tests/kms_writeback.c | 314 +
> > tests/meson.build | 1 +
> > 3 files changed, 316 insertions(+)
> > create mode 100644 tests/kms_writeback.c
> >
> > diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> > index 027ed82f..03cc8efa 100644
> > --- a/tests/Makefile.sources
> > +++ b/tests/Makefile.sources
> > @@ -77,6 +77,7 @@ TESTS_progs = \
> > kms_universal_plane \
> > kms_vblank \
> > kms_vrr \
> > + kms_writeback \
> > meta_test \
> > perf \
> > perf_pmu \
> > diff --git a/tests/kms_writeback.c b/tests/kms_writeback.c
> > new file mode 100644
> > index ..66ef48a6
> > --- /dev/null
> > +++ b/tests/kms_writeback.c
> > @@ -0,0 +1,314 @@
> > +/*
> > + * (C) COPYRIGHT 2017 ARM Limited. All rights reserved.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the
> > "Software"),
> > + * to deal in the Software without restriction, including without
> > limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including the
> > next
> > + * paragraph) shall be included in all copies or substantial portions of
> > the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
> > OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> > DEALINGS
> > + * IN THE SOFTWARE.
> > + *
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +#include "igt.h"
> > +#include "igt_core.h"
> > +#include "igt_fb.h"
> > +
> > +static drmModePropertyBlobRes *get_writeback_formats_blob(igt_output_t
> > *output)
> > +{
> > + drmModePropertyBlobRes *blob = NULL;
> > + uint64_t blob_id;
> > + int ret;
> > +
> > + ret = kmstest_get_property(output->display->drm_fd,
> > + output->config.connector->connector_id,
> > + DRM_MODE_OBJECT_CONNECTOR,
> > +
> > igt_connector_prop_names[IGT_CONNECTOR_WRITEBACK_PIXEL_FORMATS],
> > + NULL, _id, NULL);
> > + if (ret)
> > + blob = drmModeGetPropertyBlob(output->display->drm_fd, blob_id);
> > +
> > + igt_assert(blob);
> > +
> > + return blob;
> > +}
> > +
> > +static bool check_writeback_config(igt_display_t *display, igt_output_t
> > *output)
> > +{
> > + igt_fb_t input_fb, output_fb;
> > + igt_plane_t *plane;
> > + uint32_t writeback_format = DRM_FORMAT_XRGB;
> > + uint64_t tiling = igt_fb_mod_to_tiling(0);
> > + int width, height, ret;
> > + drmModeModeInfo override_mode = {
> > + .clock = 25175,
> > + .hdisplay = 640,
> > + .hsync_start = 656,
> > + .hsync_end = 752,
> > + .htotal = 800,
> > + .hskew = 0,
> > + .vdisplay = 480,
> > + .vsync_start = 490,
> > + .vsync_end = 492,
> > + .vtotal = 525,
> > + .vscan = 0,
> > + .vrefresh = 60,
> > + .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
> > + .name = {"640x480-60"},
> > + };
> > + igt_output_override_mode(output, _mode);
> > +
> > + width = override_mode.hdisplay;
> > + height = override_mode.vdisplay;
> > +
> > + ret = igt_create_fb(display->drm_fd, width, height,
> > DRM_FORMAT_XRGB, tiling, _fb);
> > + igt_assert(ret >= 0);
> > +
> > + ret = igt_create_fb(display->drm_fd, width, height, writeback_format,
> > tiling, _fb);
> > + igt_assert(ret >= 0);
> > +
> > + plane = igt_output_get_plane_type(output,
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v5,1/2] drm/i915: Add support for retrying hotplug
== Series Details ==
Series: series starting with [v5,1/2] drm/i915: Add support for retrying hotplug
URL : https://patchwork.freedesktop.org/series/63597/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6467 -> Patchwork_13632
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13632/
Known issues
Here are the changes found in Patchwork_13632 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6467/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13632/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
* igt@gem_mmap_gtt@basic-small-bo:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6467/fi-icl-u3/igt@gem_mmap_...@basic-small-bo.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13632/fi-icl-u3/igt@gem_mmap_...@basic-small-bo.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-dsi: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713] /
[fdo#108569])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6467/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13632/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][7] -> [FAIL][8] ([fdo#109485])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6467/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13632/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_busy@busy-all:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6467/fi-icl-u3/igt@gem_b...@busy-all.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13632/fi-icl-u3/igt@gem_b...@busy-all.html
* igt@i915_module_load@reload:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#106107]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6467/fi-icl-u3/igt@i915_module_l...@reload.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13632/fi-icl-u3/igt@i915_module_l...@reload.html
* igt@kms_chamelium@hdmi-hpd-fast:
- {fi-icl-u4}:[FAIL][13] ([fdo#111045]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6467/fi-icl-u4/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13632/fi-icl-u4/igt@kms_chamel...@hdmi-hpd-fast.html
- fi-kbl-7567u: [FAIL][15] ([fdo#109485]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6467/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13632/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
Participating hosts (53 -> 47)
--
Missing(6): fi-kbl-soraka fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6467 -> Patchwork_13632
CI_DRM_6467: 883fcf47ede1d5c42702b0ec198262a2f110abae @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5094: d7f140b5b02d054183a74842b4579cf7f5533927 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13632: cba558669f18790165711495afa780914588b6f9 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cba558669f18 drm/i915: Enable hotplug retry
fe1e11c1cdd6 drm/i915: Add support for retrying hotplug
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13632/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 1/2] drm/i915: Add support for retrying hotplug
On Thu, 2019-07-11 at 13:55 -0700, Shane McKee wrote:
> On Thu, Jul 11, 2019 at 11:05:15PM +0300, Ville Syrjälä wrote:
> > On Wed, Jul 10, 2019 at 03:14:59PM -0700, José Roberto de Souza
> > wrote:
> > > From: Imre Deak
> > >
> > > There is some scenarios that we are aware that sink probe can
> > > fail,
> > > so lets add the infrastructure to let hotplug() hook to request
> > > another probe after some time.
> > >
> > > v2: Handle shared HPD pins (Imre)
> > > v3: Rebased
> > > v4: Renamed INTEL_HOTPLUG_NOCHANGE to INTEL_HOTPLUG_UNCHANGED to
> > > keep
> > > it consistent(Rodrigo)
> > >
> > > Cc: Ville Syrjälä
> Tested-by: Shane McKee
I missed this =/
I will add it while merging, thanks for testing.
> > > Reviewed-by: Rodrigo Vivi
> > > Signed-off-by: José Roberto de Souza
> > > Signed-off-by: Jani Nikula
> > > Signed-off-by: Imre Deak
> > > ---
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++--
> > > drivers/gpu/drm/i915/display/intel_dp.c | 12 ++--
> > > drivers/gpu/drm/i915/display/intel_hotplug.c | 59
> > > +++-
> > > drivers/gpu/drm/i915/display/intel_hotplug.h | 5 +-
> > > drivers/gpu/drm/i915/display/intel_sdvo.c| 8 ++-
> > > drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> > > drivers/gpu/drm/i915/i915_drv.h | 3 +-
> > > drivers/gpu/drm/i915/intel_drv.h | 11 +++-
> > > 8 files changed, 80 insertions(+), 32 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index ad638e7f27bb..734c004800f8 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -4047,14 +4047,16 @@ static int intel_hdmi_reset_link(struct
> > > intel_encoder *encoder,
> > > return modeset_pipe(>base, ctx);
> > > }
> > >
> > > -static bool intel_ddi_hotplug(struct intel_encoder *encoder,
> > > - struct intel_connector *connector)
> > > +static enum intel_hotplug_state
> > > +intel_ddi_hotplug(struct intel_encoder *encoder,
> > > + struct intel_connector *connector,
> > > + bool irq_received)
> > > {
> > > struct drm_modeset_acquire_ctx ctx;
> > > - bool changed;
> > > + enum intel_hotplug_state state;
> > > int ret;
> > >
> > > - changed = intel_encoder_hotplug(encoder, connector);
> > > + state = intel_encoder_hotplug(encoder, connector,
> > > irq_received);
> > >
> > > drm_modeset_acquire_init(, 0);
> > >
> > > @@ -4076,7 +4078,7 @@ static bool intel_ddi_hotplug(struct
> > > intel_encoder *encoder,
> > > drm_modeset_acquire_fini();
> > > WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
> > >
> > > - return changed;
> > > + return state;
> > > }
> > >
> > > static struct intel_connector *
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 0bdb7ecc5a81..4423abbc7907 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -4853,14 +4853,16 @@ int intel_dp_retrain_link(struct
> > > intel_encoder *encoder,
> > > * retrain the link to get a picture. That's in case no
> > > * userspace component reacted to intermittent HPD dip.
> > > */
> > > -static bool intel_dp_hotplug(struct intel_encoder *encoder,
> > > - struct intel_connector *connector)
> > > +static enum intel_hotplug_state
> > > +intel_dp_hotplug(struct intel_encoder *encoder,
> > > + struct intel_connector *connector,
> > > + bool irq_received)
> > > {
> > > struct drm_modeset_acquire_ctx ctx;
> > > - bool changed;
> > > + enum intel_hotplug_state state;
> > > int ret;
> > >
> > > - changed = intel_encoder_hotplug(encoder, connector);
> > > + state = intel_encoder_hotplug(encoder, connector,
> > > irq_received);
> > >
> > > drm_modeset_acquire_init(, 0);
> > >
> > > @@ -4879,7 +4881,7 @@ static bool intel_dp_hotplug(struct
> > > intel_encoder *encoder,
> > > drm_modeset_acquire_fini();
> > > WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
> > >
> > > - return changed;
> > > + return state;
> > > }
> > >
> > > static void intel_dp_check_service_irq(struct intel_dp
> > > *intel_dp)
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > index ea3de4acc850..2ca92780c659 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > @@ -112,6 +112,7 @@ enum hpd_pin intel_hpd_pin_default(struct
> > > drm_i915_private *dev_priv,
> > >
> > > #define HPD_STORM_DETECT_PERIOD 1000
> > > #define HPD_STORM_REENABLE_DELAY (2 * 60 * 1000)
> > > +#define HPD_RETRY_DELAY 1000
> > >
> > > /**
> > > * intel_hpd_irq_storm_detect - gather stats and detect HPD IRQ
> > > storm on a pin
> > > @@ -266,8 +267,10 @@
Re: [Intel-gfx] [PATCH v4 1/2] drm/i915: Add support for retrying hotplug
On Thu, 2019-07-11 at 23:05 +0300, Ville Syrjälä wrote:
> On Wed, Jul 10, 2019 at 03:14:59PM -0700, José Roberto de Souza
> wrote:
> > From: Imre Deak
> >
> > There is some scenarios that we are aware that sink probe can fail,
> > so lets add the infrastructure to let hotplug() hook to request
> > another probe after some time.
> >
> > v2: Handle shared HPD pins (Imre)
> > v3: Rebased
> > v4: Renamed INTEL_HOTPLUG_NOCHANGE to INTEL_HOTPLUG_UNCHANGED to
> > keep
> > it consistent(Rodrigo)
> >
> > Cc: Ville Syrjälä
> > Reviewed-by: Rodrigo Vivi
> > Signed-off-by: José Roberto de Souza
> > Signed-off-by: Jani Nikula
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++--
> > drivers/gpu/drm/i915/display/intel_dp.c | 12 ++--
> > drivers/gpu/drm/i915/display/intel_hotplug.c | 59 +++-
> >
> > drivers/gpu/drm/i915/display/intel_hotplug.h | 5 +-
> > drivers/gpu/drm/i915/display/intel_sdvo.c| 8 ++-
> > drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> > drivers/gpu/drm/i915/i915_drv.h | 3 +-
> > drivers/gpu/drm/i915/intel_drv.h | 11 +++-
> > 8 files changed, 80 insertions(+), 32 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index ad638e7f27bb..734c004800f8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4047,14 +4047,16 @@ static int intel_hdmi_reset_link(struct
> > intel_encoder *encoder,
> > return modeset_pipe(>base, ctx);
> > }
> >
> > -static bool intel_ddi_hotplug(struct intel_encoder *encoder,
> > - struct intel_connector *connector)
> > +static enum intel_hotplug_state
> > +intel_ddi_hotplug(struct intel_encoder *encoder,
> > + struct intel_connector *connector,
> > + bool irq_received)
> > {
> > struct drm_modeset_acquire_ctx ctx;
> > - bool changed;
> > + enum intel_hotplug_state state;
> > int ret;
> >
> > - changed = intel_encoder_hotplug(encoder, connector);
> > + state = intel_encoder_hotplug(encoder, connector,
> > irq_received);
> >
> > drm_modeset_acquire_init(, 0);
> >
> > @@ -4076,7 +4078,7 @@ static bool intel_ddi_hotplug(struct
> > intel_encoder *encoder,
> > drm_modeset_acquire_fini();
> > WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
> >
> > - return changed;
> > + return state;
> > }
> >
> > static struct intel_connector *
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 0bdb7ecc5a81..4423abbc7907 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -4853,14 +4853,16 @@ int intel_dp_retrain_link(struct
> > intel_encoder *encoder,
> > * retrain the link to get a picture. That's in case no
> > * userspace component reacted to intermittent HPD dip.
> > */
> > -static bool intel_dp_hotplug(struct intel_encoder *encoder,
> > -struct intel_connector *connector)
> > +static enum intel_hotplug_state
> > +intel_dp_hotplug(struct intel_encoder *encoder,
> > +struct intel_connector *connector,
> > +bool irq_received)
> > {
> > struct drm_modeset_acquire_ctx ctx;
> > - bool changed;
> > + enum intel_hotplug_state state;
> > int ret;
> >
> > - changed = intel_encoder_hotplug(encoder, connector);
> > + state = intel_encoder_hotplug(encoder, connector,
> > irq_received);
> >
> > drm_modeset_acquire_init(, 0);
> >
> > @@ -4879,7 +4881,7 @@ static bool intel_dp_hotplug(struct
> > intel_encoder *encoder,
> > drm_modeset_acquire_fini();
> > WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
> >
> > - return changed;
> > + return state;
> > }
> >
> > static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
> > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
> > b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > index ea3de4acc850..2ca92780c659 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > @@ -112,6 +112,7 @@ enum hpd_pin intel_hpd_pin_default(struct
> > drm_i915_private *dev_priv,
> >
> > #define HPD_STORM_DETECT_PERIOD1000
> > #define HPD_STORM_REENABLE_DELAY (2 * 60 * 1000)
> > +#define HPD_RETRY_DELAY1000
> >
> > /**
> > * intel_hpd_irq_storm_detect - gather stats and detect HPD IRQ
> > storm on a pin
> > @@ -266,8 +267,10 @@ static void
> > intel_hpd_irq_storm_reenable_work(struct work_struct *work)
> > intel_runtime_pm_put(_priv->runtime_pm, wakeref);
> > }
> >
> > -bool intel_encoder_hotplug(struct intel_encoder *encoder,
> > - struct intel_connector *connector)
> > +enum intel_hotplug_state
> > +intel_encoder_hotplug(struct intel_encoder
[Intel-gfx] [PATCH v5 2/2] drm/i915: Enable hotplug retry
Right now we are aware of two cases that needs another hotplug retry:
- Unpowered type-c dongles
- HDMI slow unplug
Both have a complete explanation in the code to schedule another run
of the hotplug handler.
It could have more checks to just trigger the retry in those two
specific cases but why would sink signal a long pulse if there is
no change? Also the drawback of running the hotplug handler again
is really low and that could fix another cases that we are not
aware.
Also retrying for old DP ports(non-DDI) to make it consistent and not
cause CI failures if those systems are connected to chamelium boards
that will be used to simulate the issues reported in here.
v2: Also retrying for old DP ports(non-DDI)(Imre)
v4: Renamed INTEL_HOTPLUG_NOCHANGE to INTEL_HOTPLUG_UNCHANGED to keep
it consistent(Rodrigo)
Tested-by: Timo Aaltonen
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Jani Nikula
Reviewed-by: Imre Deak
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi.c | 21 +
drivers/gpu/drm/i915/display/intel_dp.c | 7 ++
drivers/gpu/drm/i915/display/intel_hdmi.c | 28 ++-
3 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index c89d0c7543dc..18bc0f2690c9 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4075,6 +4075,7 @@ intel_ddi_hotplug(struct intel_encoder *encoder,
struct intel_connector *connector,
bool irq_received)
{
+ struct intel_digital_port *dig_port = enc_to_dig_port(>base);
struct drm_modeset_acquire_ctx ctx;
enum intel_hotplug_state state;
int ret;
@@ -4101,6 +4102,26 @@ intel_ddi_hotplug(struct intel_encoder *encoder,
drm_modeset_acquire_fini();
WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
+ /*
+* Unpowered type-c dongles can take some time to boot and be
+* responsible, so here giving some time to those dongles to power up
+* and then retrying the probe.
+*
+* On many platforms the HDMI live state signal is known to be
+* unreliable, so we can't use it to detect if a sink is connected or
+* not. Instead we detect if it's connected based on whether we can
+* read the EDID or not. That in turn has a problem during disconnect,
+* since the HPD interrupt may be raised before the DDC lines get
+* disconnected (due to how the required length of DDC vs. HPD
+* connector pins are specified) and so we'll still be able to get a
+* valid EDID. To solve this schedule another detection cycle if this
+* time around we didn't detect any change in the sink's connection
+* status.
+*/
+ if (state == INTEL_HOTPLUG_UNCHANGED && irq_received &&
+ !dig_port->dp.is_mst)
+ state = INTEL_HOTPLUG_RETRY;
+
return state;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index a870ecab78a7..b2ac19b74e85 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4884,6 +4884,13 @@ intel_dp_hotplug(struct intel_encoder *encoder,
drm_modeset_acquire_fini();
WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
+ /*
+* Keeping it consistent with intel_ddi_hotplug() and
+* intel_hdmi_hotplug().
+*/
+ if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
+ state = INTEL_HOTPLUG_RETRY;
+
return state;
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 77af0dfd93ce..a8a3b73d697c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3125,6 +3125,32 @@ void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port,
DRM_DEBUG_KMS("CEC notifier get failed\n");
}
+static enum intel_hotplug_state
+intel_hdmi_hotplug(struct intel_encoder *encoder,
+ struct intel_connector *connector, bool irq_received)
+{
+ enum intel_hotplug_state state;
+
+ state = intel_encoder_hotplug(encoder, connector, irq_received);
+
+ /*
+* On many platforms the HDMI live state signal is known to be
+* unreliable, so we can't use it to detect if a sink is connected or
+* not. Instead we detect if it's connected based on whether we can
+* read the EDID or not. That in turn has a problem during disconnect,
+* since the HPD interrupt may be raised before the DDC lines get
+* disconnected (due to how the required length of DDC vs. HPD
+* connector pins are specified) and so we'll still be able to get a
+* valid EDID. To solve this schedule another detection cycle if this
[Intel-gfx] [PATCH v5 1/2] drm/i915: Add support for retrying hotplug
From: Imre Deak
There is some scenarios that we are aware that sink probe can fail,
so lets add the infrastructure to let hotplug() hook to request
another probe after some time.
v2: Handle shared HPD pins (Imre)
v3: Rebased
v4: Renamed INTEL_HOTPLUG_NOCHANGE to INTEL_HOTPLUG_UNCHANGED to keep
it consistent(Rodrigo)
v5: Making the working queue used explicit through all the callers to
hotplug_work (Ville)
Tested-by: Timo Aaltonen
Cc: Ville Syrjälä
Reviewed-by: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
Signed-off-by: Jani Nikula
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++--
drivers/gpu/drm/i915/display/intel_dp.c | 12 ++--
drivers/gpu/drm/i915/display/intel_hotplug.c | 59 +++-
drivers/gpu/drm/i915/display/intel_hotplug.h | 5 +-
drivers/gpu/drm/i915/display/intel_sdvo.c| 8 ++-
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 3 +-
drivers/gpu/drm/i915/intel_drv.h | 11 +++-
8 files changed, 80 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 8445244aa593..c89d0c7543dc 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4070,14 +4070,16 @@ static int intel_hdmi_reset_link(struct intel_encoder
*encoder,
return modeset_pipe(>base, ctx);
}
-static bool intel_ddi_hotplug(struct intel_encoder *encoder,
- struct intel_connector *connector)
+static enum intel_hotplug_state
+intel_ddi_hotplug(struct intel_encoder *encoder,
+ struct intel_connector *connector,
+ bool irq_received)
{
struct drm_modeset_acquire_ctx ctx;
- bool changed;
+ enum intel_hotplug_state state;
int ret;
- changed = intel_encoder_hotplug(encoder, connector);
+ state = intel_encoder_hotplug(encoder, connector, irq_received);
drm_modeset_acquire_init(, 0);
@@ -4099,7 +4101,7 @@ static bool intel_ddi_hotplug(struct intel_encoder
*encoder,
drm_modeset_acquire_fini();
WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
- return changed;
+ return state;
}
static struct intel_connector *
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 24592d985bcb..a870ecab78a7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4856,14 +4856,16 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
* retrain the link to get a picture. That's in case no
* userspace component reacted to intermittent HPD dip.
*/
-static bool intel_dp_hotplug(struct intel_encoder *encoder,
-struct intel_connector *connector)
+static enum intel_hotplug_state
+intel_dp_hotplug(struct intel_encoder *encoder,
+struct intel_connector *connector,
+bool irq_received)
{
struct drm_modeset_acquire_ctx ctx;
- bool changed;
+ enum intel_hotplug_state state;
int ret;
- changed = intel_encoder_hotplug(encoder, connector);
+ state = intel_encoder_hotplug(encoder, connector, irq_received);
drm_modeset_acquire_init(, 0);
@@ -4882,7 +4884,7 @@ static bool intel_dp_hotplug(struct intel_encoder
*encoder,
drm_modeset_acquire_fini();
WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
- return changed;
+ return state;
}
static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
b/drivers/gpu/drm/i915/display/intel_hotplug.c
index ea3de4acc850..342587d91d57 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -112,6 +112,7 @@ enum hpd_pin intel_hpd_pin_default(struct drm_i915_private
*dev_priv,
#define HPD_STORM_DETECT_PERIOD1000
#define HPD_STORM_REENABLE_DELAY (2 * 60 * 1000)
+#define HPD_RETRY_DELAY1000
/**
* intel_hpd_irq_storm_detect - gather stats and detect HPD IRQ storm on a pin
@@ -266,8 +267,10 @@ static void intel_hpd_irq_storm_reenable_work(struct
work_struct *work)
intel_runtime_pm_put(_priv->runtime_pm, wakeref);
}
-bool intel_encoder_hotplug(struct intel_encoder *encoder,
- struct intel_connector *connector)
+enum intel_hotplug_state
+intel_encoder_hotplug(struct intel_encoder *encoder,
+ struct intel_connector *connector,
+ bool irq_received)
{
struct drm_device *dev = connector->base.dev;
enum drm_connector_status old_status;
@@ -279,7 +282,7 @@ bool intel_encoder_hotplug(struct intel_encoder *encoder,
drm_helper_probe_detect(>base, NULL, false);
if (old_status ==
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,01/21] drm/i915: Add 4th pipe and transcoder
== Series Details == Series: series starting with [CI,01/21] drm/i915: Add 4th pipe and transcoder URL : https://patchwork.freedesktop.org/series/63528/ State : success == Summary == CI Bug Log - changes from CI_DRM_6453_full -> Patchwork_13616_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13616_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110854]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb4/igt@gem_exec_balan...@smoke.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13616/shard-iclb3/igt@gem_exec_balan...@smoke.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-apl5/igt@gem_workarou...@suspend-resume-context.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13616/shard-apl8/igt@gem_workarou...@suspend-resume-context.html * igt@i915_pm_rpm@system-suspend: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#104108] / [fdo#107807]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl4/igt@i915_pm_...@system-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13616/shard-skl4/igt@i915_pm_...@system-suspend.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][7] -> [FAIL][8] ([fdo#105767]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-hsw7/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13616/shard-hsw8/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#105363]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl7/igt@kms_f...@flip-vs-expired-vblank.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13616/shard-skl5/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-hsw: [PASS][11] -> [INCOMPLETE][12] ([fdo#103540]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-hsw5/igt@kms_f...@flip-vs-suspend-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13616/shard-hsw5/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_flip@plain-flip-fb-recreate-interruptible: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#100368]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl9/igt@kms_f...@plain-flip-fb-recreate-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13616/shard-skl3/igt@kms_f...@plain-flip-fb-recreate-interruptible.html * igt@kms_flip_tiling@flip-changes-tiling-yf: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108228] / [fdo#108303]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl10/igt@kms_flip_til...@flip-changes-tiling-yf.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13616/shard-skl6/igt@kms_flip_til...@flip-changes-tiling-yf.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13616/shard-iclb7/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [fdo#110403]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl8/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13616/shard-skl9/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103166]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb6/igt@kms_plane_low...@pipe-a-tiling-y.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13616/shard-iclb8/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_psr@psr2_sprite_render: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb2/igt@kms_psr@psr2_sprite_render.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13616/shard-iclb7/igt@kms_psr@psr2_sprite_render.html * igt@kms_setmode@basic: -
Re: [Intel-gfx] [PATCH v3 1/1] drm/i915: Add modular FIA
On Thu, 2019-07-11 at 16:49 -0700, Lucas De Marchi wrote:
> On Thu, Jul 11, 2019 at 04:15:42PM -0700, Summers, Stuart wrote:
> > On Thu, 2019-07-11 at 13:58 -0700, Lucas De Marchi wrote:
> > > From: Anusha Srivatsa
> > >
> > > Some platforms may have Modular FIA. If Modular FIA is used in
> > > the
> > > SOC,
> > > then Display Driver will access the additional instances of
> > > FIA based on pre-assigned offset in GTTMADDR space.
> > >
> > > Each Modular FIA instance has its own IOSF Sideband Port ID
> > > and it houses only 2 Type-C Port. In SOC that has more than
> > > two Type-C Ports, there are multiple instances of Modular FIA.
> > > Gunit will need to use different destination ID when it access
> > > different pair of Type-C Port.
> > >
> > > The DFLEXDPSP register has Modular FIA bit starting on Tiger
> > > Lake. If
> > > Modular FIA is used in the SOC, this register bit exists in all
> > > the
> > > instances of Modular FIA. IOM FW is required to program only the
> > > MF
> > > bit
> > > in first FIA instance that houses the Type-C Port 0 and Port 1,
> > > for
> > > Display Driver to read from.
> > >
> > > v2 (Lucas):
> > > - Move all accesses to FIA to be contained in intel_tc.c, along
> > > with
> > > display_fia that is now called tc_phy_fia
> > > - Save the fia instance number on intel_digital_port, so we
> > > don't
> > > have
> > > to query if modular FIA is used on every access
> > > v3 (Lucas): Make function static
> > > v4 (Lucas): Move enum phy_fia to the header and use it in
> > >intel_digital_port (suggested by Ville)
> > >
> > > Cc: Jani Nikula
> > > Signed-off-by: Anusha Srivatsa
> > > Signed-off-by: Lucas De Marchi
> > > Acked-by: Ville Syrjälä
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.h | 6 +++
> > > drivers/gpu/drm/i915/display/intel_tc.c | 43
> > >
> > >
> > > drivers/gpu/drm/i915/i915_reg.h | 13 --
> > > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > > drivers/gpu/drm/i915/intel_drv.h | 1 +
> > > 5 files changed, 52 insertions(+), 12 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> > > b/drivers/gpu/drm/i915/display/intel_display.h
> > > index 8a4a57ef82a2..8b048976f7b4 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > > @@ -243,6 +243,12 @@ enum phy {
> > >
> > > #define phy_name(a) ((a) + 'A')
> > >
> > > +enum phy_fia {
> > > + FIA1,
> > > + FIA2,
> > > + FIA3,
> > > +};
> > > +
> > > #define for_each_pipe(__dev_priv, __p) \
> > > for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes;
> > > (__p)++)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> > > b/drivers/gpu/drm/i915/display/intel_tc.c
> > > index f44ee4bfe7c8..9400da4f7916 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_tc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> > > @@ -22,6 +22,24 @@ static const char *tc_port_mode_name(enum
> > > tc_port_mode mode)
> > > return names[mode];
> > > }
> > >
> > > +static bool has_modular_fia(struct drm_i915_private *i915)
> > > +{
> > > + if (!INTEL_INFO(i915)->display.has_modular_fia)
> > > + return false;
> > > +
> > > + return intel_uncore_read(>uncore,
> > > + PORT_TX_DFLEXDPSP(FIA1)) &
> > > MODULAR_FIA_MASK;
> > > +}
> > > +
> > > +static enum phy_fia tc_port_to_fia(struct drm_i915_private
> > > *i915,
> > > +enum tc_port tc_port)
> > > +{
> > > + if (!has_modular_fia(i915))
> > > + return FIA1;
> > > +
> > > + return tc_port / 2;
> >
> > I realize this is described in the commit message, but would be
> > nice to
> > have a brief comment describing why we need this conversion.
> >
> > > +}
> > > +
> > > u32 intel_tc_port_get_lane_mask(struct intel_digital_port
> > > *dig_port)
> > > {
> > > struct drm_i915_private *i915 = to_i915(dig_port-
> > > > base.base.dev);
> > >
> > > @@ -29,7 +47,8 @@ u32 intel_tc_port_get_lane_mask(struct
> > > intel_digital_port *dig_port)
> > > struct intel_uncore *uncore = >uncore;
> > > u32 lane_mask;
> > >
> > > - lane_mask = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
> > > + lane_mask = intel_uncore_read(uncore,
> > > + PORT_TX_DFLEXDPSP(dig_port-
> > > > tc_phy_fia));
> > >
> > > WARN_ON(lane_mask == 0x);
> > >
> > > @@ -78,7 +97,8 @@ void intel_tc_port_set_fia_lane_count(struct
> > > intel_digital_port *dig_port,
> > >
> > > WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
> > >
> > > - val = intel_uncore_read(uncore, PORT_TX_DFLEXDPMLE1);
> > > + val = intel_uncore_read(uncore,
> > > + PORT_TX_DFLEXDPMLE1(dig_port-
> > > > tc_phy_fia));
> > >
> > > val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
> > >
> > > switch (required_lanes) {
> > > @@ -97,7 +117,8 @@ void
Re: [Intel-gfx] [PATCH v2 2/4] drm/i915: Fix WaProgramMgsrForL3BankSpecificMmioReads
On Thu, 2019-07-11 at 16:59 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
This is generally much more readable than the previous implementation,
thanks! Some minor comments below...
>
> Two issues in this code:
>
> 1.
> fls() usage is incorrect causing off by one in subslice mask lookup,
> which in other words means subslice mask of all zeroes is always used
> (subslice mask of a slice which is not present, or even out of bounds
> array access), rendering the checks in wa_init_mcr either futile or
> random.
>
> 2.
> Condition in WARN_ON is not correct. It is doing a bitwise and
> operation
> between a positive (present subslices) and negative mask (disabled L3
> banks).
>
> This means that with corrected fls() usage the assert would always
> incorrectly fail.
>
> We can fix this by inverting the fuse bits in the check.
>
> v2:
> * Simplify check for logic and redability.
> * Improve commentary explaining what is really happening ie. what
> the
>assert is really trying to check and why.
>
> Signed-off-by: Tvrtko Ursulin
> Fixes: fe864b76c2ab ("drm/i915: Implement
> WaProgramMgsrForL3BankSpecificMmioReads")
> Reviewed-by: Chris Wilson # v1
> Cc: Michał Winiarski
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 80 ++-
> --
> 1 file changed, 40 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 9e069286d3ce..80f1159e5cda 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -761,7 +761,27 @@ static void
> wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> {
> const struct sseu_dev_info *sseu = _INFO(i915)->sseu;
> - u32 mcr_slice_subslice_mask;
> + u32 mcr_mask, mcr;
> +
> + /*
> + * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
> + * Before any MMIO read into slice/subslice specific registers,
> MCR
> + * packet control register needs to be programmed to point to
> any
> + * enabled s/ss pair. Otherwise, incorrect values will be
> returned.
> + * This means each subsequent MMIO read will be forwarded to an
> + * specific s/ss combination, but this is OK since these
> registers
> + * are consistent across s/ss in almost all cases. In the rare
> + * occasions, such as INSTDONE, where this value is dependent
> + * on s/ss combo, the read should be done with
> read_subslice_reg.
> + */
> + mcr = intel_calculate_mcr_s_ss_select(i915);
> +
> + if (INTEL_GEN(i915) >= 11)
> + mcr_mask = GEN11_MCR_SLICE_MASK |
> GEN11_MCR_SUBSLICE_MASK;
> + else
> + mcr_mask = GEN8_MCR_SLICE_MASK |
> GEN8_MCR_SUBSLICE_MASK;
> +
> + wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
Was there a specific reason to move this up to the top? Or this is
purely to move this functionality all together rather than spread out
through the function? Looking at the documentation, we do want to
specifically apply WaProgramMgsrForL3BankSpecificMmioReads before any
other workarounds. So maybe just move this whole block to the bottom of
the function instead?
>
> /*
>* WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
> @@ -776,49 +796,29 @@ wa_init_mcr(struct drm_i915_private *i915,
> struct i915_wa_list *wal)
>* something more complex that requires checking the range of
> every
>* MMIO read).
>*/
> - if (INTEL_GEN(i915) >= 10 &&
> - is_power_of_2(sseu->slice_mask)) {
> + if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
> /*
> - * read FUSE3 for enabled L3 Bank IDs, if L3 Bank
> matches
> - * enabled subslice, no need to redirect MCR packet
> + * GEN8_MCR_SELECTOR contains dual-purpose bits which
> select
> + * both to which subslice, or to which L3 bank, the
> respective
> + * mmio reads will go.
> + * Since we have selected one enabled subslice in
> + * WaProgramMgsrForCorrectSliceSpecificMmioReads, we
> now
> + * need to check if the L3 bank of the equal "instance"
> is also
> + * enabled.
> + * If that is not the case we could try to find a
> number which
> + * works for both, or going even further, implement a
> dynamic
> + * scheme where we switch at before every affected mmio
s/at //?
> read.
> + * Fortunately neither seems to be needed at the moment
> for
> + * current parts and current driver behaviour.
>*/
> - u32 slice = fls(sseu->slice_mask);
> - u32 fuse3 =
> - intel_uncore_read(>uncore,
> GEN10_MIRROR_FUSE3);
> - u8 ss_mask = sseu->subslice_mask[slice];
> -
> - u8 enabled_mask = (ss_mask | ss_mask >>
> -
Re: [Intel-gfx] [PATCH v3 1/1] drm/i915: Add modular FIA
On Thu, Jul 11, 2019 at 04:15:42PM -0700, Summers, Stuart wrote:
On Thu, 2019-07-11 at 13:58 -0700, Lucas De Marchi wrote:
From: Anusha Srivatsa
Some platforms may have Modular FIA. If Modular FIA is used in the
SOC,
then Display Driver will access the additional instances of
FIA based on pre-assigned offset in GTTMADDR space.
Each Modular FIA instance has its own IOSF Sideband Port ID
and it houses only 2 Type-C Port. In SOC that has more than
two Type-C Ports, there are multiple instances of Modular FIA.
Gunit will need to use different destination ID when it access
different pair of Type-C Port.
The DFLEXDPSP register has Modular FIA bit starting on Tiger
Lake. If
Modular FIA is used in the SOC, this register bit exists in all the
instances of Modular FIA. IOM FW is required to program only the MF
bit
in first FIA instance that houses the Type-C Port 0 and Port 1, for
Display Driver to read from.
v2 (Lucas):
- Move all accesses to FIA to be contained in intel_tc.c, along
with
display_fia that is now called tc_phy_fia
- Save the fia instance number on intel_digital_port, so we don't
have
to query if modular FIA is used on every access
v3 (Lucas): Make function static
v4 (Lucas): Move enum phy_fia to the header and use it in
intel_digital_port (suggested by Ville)
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
Signed-off-by: Lucas De Marchi
Acked-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.h | 6 +++
drivers/gpu/drm/i915/display/intel_tc.c | 43
drivers/gpu/drm/i915/i915_reg.h | 13 --
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
5 files changed, 52 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 8a4a57ef82a2..8b048976f7b4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -243,6 +243,12 @@ enum phy {
#define phy_name(a) ((a) + 'A')
+enum phy_fia {
+ FIA1,
+ FIA2,
+ FIA3,
+};
+
#define for_each_pipe(__dev_priv, __p) \
for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes;
(__p)++)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index f44ee4bfe7c8..9400da4f7916 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -22,6 +22,24 @@ static const char *tc_port_mode_name(enum
tc_port_mode mode)
return names[mode];
}
+static bool has_modular_fia(struct drm_i915_private *i915)
+{
+ if (!INTEL_INFO(i915)->display.has_modular_fia)
+ return false;
+
+ return intel_uncore_read(>uncore,
+PORT_TX_DFLEXDPSP(FIA1)) &
MODULAR_FIA_MASK;
+}
+
+static enum phy_fia tc_port_to_fia(struct drm_i915_private *i915,
+ enum tc_port tc_port)
+{
+ if (!has_modular_fia(i915))
+ return FIA1;
+
+ return tc_port / 2;
I realize this is described in the commit message, but would be nice to
have a brief comment describing why we need this conversion.
+}
+
u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port-
>base.base.dev);
@@ -29,7 +47,8 @@ u32 intel_tc_port_get_lane_mask(struct
intel_digital_port *dig_port)
struct intel_uncore *uncore = >uncore;
u32 lane_mask;
- lane_mask = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
+ lane_mask = intel_uncore_read(uncore,
+ PORT_TX_DFLEXDPSP(dig_port-
>tc_phy_fia));
WARN_ON(lane_mask == 0x);
@@ -78,7 +97,8 @@ void intel_tc_port_set_fia_lane_count(struct
intel_digital_port *dig_port,
WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
- val = intel_uncore_read(uncore, PORT_TX_DFLEXDPMLE1);
+ val = intel_uncore_read(uncore,
+ PORT_TX_DFLEXDPMLE1(dig_port-
>tc_phy_fia));
val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
switch (required_lanes) {
@@ -97,7 +117,8 @@ void intel_tc_port_set_fia_lane_count(struct
intel_digital_port *dig_port,
MISSING_CASE(required_lanes);
}
- intel_uncore_write(uncore, PORT_TX_DFLEXDPMLE1, val);
+ intel_uncore_write(uncore,
+ PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia),
val);
}
static void tc_port_fixup_legacy_flag(struct intel_digital_port
*dig_port,
@@ -129,7 +150,8 @@ static u32 tc_port_live_status_mask(struct
intel_digital_port *dig_port)
u32 mask = 0;
u32 val;
- val = intel_uncore_rea
d(uncore, PORT_TX_DFLEXDPSP);
+ val = intel_uncore_read(uncore,
+ PORT_TX_DFLEXDPSP(dig_port-
>tc_phy_fia));
if (val == 0x) {
DRM_DEBUG_KMS("Port
Re: [Intel-gfx] screen freeze with 5.2-rc6 Dell XPS-13 skylake i915
On Thu, 2019-07-11 at 23:28 +, Souza, Jose wrote: > On Fri, 2019-07-12 at 01:03 +0200, Paul Bolle wrote: > > James Bottomley schreef op do 11-07-2019 om 15:38 [-0700]: > > > On Thu, 2019-07-11 at 22:26 +, Souza, Jose wrote: > > > > It eventually comes back from screen freeze? Like moving the > > > > mouse or typing brings it back? > > > > > > No, it seems to be frozen for all time (at least until I got > > > bored waiting, which was probably 20 minutes). Even if I reboot > > > the machine, the current screen state stays until the system > > > powers off. > > > > As I mentioned earlier, a suspend/resume cycle unfreezes the > > screen. > > > > And I seem to remember that, if the gnome screen-locking eventually > > kicks in, unlocking the screen still works, as the screen then > > isn't frozen anymore. > > > > Thanks, > > Thanks for all the information Paul. > > Could test with the patch attached? Applied and running with it now. > If the issue happens again could send the output of: > > /sys/kernel/debug/dri/0/eDP-1/i915_psr_sink_status > /sys/kernel/debug/dri/0/i915_edp_psr_status > > Thanks so much for all the help Sure, James ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 1/1] drm/i915: Add modular FIA
On Thu, 2019-07-11 at 13:58 -0700, Lucas De Marchi wrote:
> From: Anusha Srivatsa
>
> Some platforms may have Modular FIA. If Modular FIA is used in the
> SOC,
> then Display Driver will access the additional instances of
> FIA based on pre-assigned offset in GTTMADDR space.
>
> Each Modular FIA instance has its own IOSF Sideband Port ID
> and it houses only 2 Type-C Port. In SOC that has more than
> two Type-C Ports, there are multiple instances of Modular FIA.
> Gunit will need to use different destination ID when it access
> different pair of Type-C Port.
>
> The DFLEXDPSP register has Modular FIA bit starting on Tiger
> Lake. If
> Modular FIA is used in the SOC, this register bit exists in all the
> instances of Modular FIA. IOM FW is required to program only the MF
> bit
> in first FIA instance that houses the Type-C Port 0 and Port 1, for
> Display Driver to read from.
>
> v2 (Lucas):
> - Move all accesses to FIA to be contained in intel_tc.c, along
> with
> display_fia that is now called tc_phy_fia
> - Save the fia instance number on intel_digital_port, so we don't
> have
> to query if modular FIA is used on every access
> v3 (Lucas): Make function static
> v4 (Lucas): Move enum phy_fia to the header and use it in
>intel_digital_port (suggested by Ville)
>
> Cc: Jani Nikula
> Signed-off-by: Anusha Srivatsa
> Signed-off-by: Lucas De Marchi
> Acked-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_display.h | 6 +++
> drivers/gpu/drm/i915/display/intel_tc.c | 43
>
> drivers/gpu/drm/i915/i915_reg.h | 13 --
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 5 files changed, 52 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 8a4a57ef82a2..8b048976f7b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -243,6 +243,12 @@ enum phy {
>
> #define phy_name(a) ((a) + 'A')
>
> +enum phy_fia {
> + FIA1,
> + FIA2,
> + FIA3,
> +};
> +
> #define for_each_pipe(__dev_priv, __p) \
> for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes;
> (__p)++)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> b/drivers/gpu/drm/i915/display/intel_tc.c
> index f44ee4bfe7c8..9400da4f7916 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -22,6 +22,24 @@ static const char *tc_port_mode_name(enum
> tc_port_mode mode)
> return names[mode];
> }
>
> +static bool has_modular_fia(struct drm_i915_private *i915)
> +{
> + if (!INTEL_INFO(i915)->display.has_modular_fia)
> + return false;
> +
> + return intel_uncore_read(>uncore,
> + PORT_TX_DFLEXDPSP(FIA1)) &
> MODULAR_FIA_MASK;
> +}
> +
> +static enum phy_fia tc_port_to_fia(struct drm_i915_private *i915,
> +enum tc_port tc_port)
> +{
> + if (!has_modular_fia(i915))
> + return FIA1;
> +
> + return tc_port / 2;
I realize this is described in the commit message, but would be nice to
have a brief comment describing why we need this conversion.
> +}
> +
> u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
> {
> struct drm_i915_private *i915 = to_i915(dig_port-
> >base.base.dev);
> @@ -29,7 +47,8 @@ u32 intel_tc_port_get_lane_mask(struct
> intel_digital_port *dig_port)
> struct intel_uncore *uncore = >uncore;
> u32 lane_mask;
>
> - lane_mask = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
> + lane_mask = intel_uncore_read(uncore,
> + PORT_TX_DFLEXDPSP(dig_port-
> >tc_phy_fia));
>
> WARN_ON(lane_mask == 0x);
>
> @@ -78,7 +97,8 @@ void intel_tc_port_set_fia_lane_count(struct
> intel_digital_port *dig_port,
>
> WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
>
> - val = intel_uncore_read(uncore, PORT_TX_DFLEXDPMLE1);
> + val = intel_uncore_read(uncore,
> + PORT_TX_DFLEXDPMLE1(dig_port-
> >tc_phy_fia));
> val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
>
> switch (required_lanes) {
> @@ -97,7 +117,8 @@ void intel_tc_port_set_fia_lane_count(struct
> intel_digital_port *dig_port,
> MISSING_CASE(required_lanes);
> }
>
> - intel_uncore_write(uncore, PORT_TX_DFLEXDPMLE1, val);
> + intel_uncore_write(uncore,
> +PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia),
> val);
> }
>
> static void tc_port_fixup_legacy_flag(struct intel_digital_port
> *dig_port,
> @@ -129,7 +150,8 @@ static u32 tc_port_live_status_mask(struct
> intel_digital_port *dig_port)
> u32 mask = 0;
> u32 val;
>
> - val = intel_uncore_rea
> d(uncore, PORT_TX_DFLEXDPSP);
> + val =
Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/display/icl: Bump up the vdisplay to reflect higher transcoder vertical limits
On Thu, Jul 11, 2019 at 01:38:41PM +0300, Ville Syrjälä wrote:
> On Wed, Jul 10, 2019 at 02:39:50PM -0700, Manasi Navare wrote:
> > On ICL+, the vertical limits for the transcoders are increased to 8192 so
> > bump up
> > limits in intel_mode_valid()
> >
> > v3:
> > * Supported starting ICL (Ville)
> > * Use the higher limits from TRANS_VTOTAL register (Ville)
> > v2:
> > * Checkpatch warning (Manasi)
> >
> > Cc: Maarten Lankhorst
> > Cc: Ville Syrjälä
> > Signed-off-by: Manasi Navare
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 9 +++--
> > 1 file changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index f07081815b80..9883f607bb88 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev,
> >DRM_MODE_FLAG_CLKDIV2))
> > return MODE_BAD;
> >
> > - if (INTEL_GEN(dev_priv) >= 9 ||
> > - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> > + if (INTEL_GEN(dev_priv) >= 11) {
> > + hdisplay_max = 8192;
> > + vdisplay_max = 8192;
>
> The horiz limits should be 16k.
So the TRANS_HTOTAL has had 14 bits so allowed 16K even for Gen9+, should
this be changed for all?
Manasi
>
> > + htotal_max = 8192;
> > + vtotal_max = 8192;
> > + } else if (INTEL_GEN(dev_priv) >= 9 ||
> > + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> > hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
> > vdisplay_max = 4096;
> > htotal_max = 8192;
> > --
> > 2.19.1
>
> --
> Ville Syrjälä
> Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gtt: Use shallow dma pages for scratch
== Series Details == Series: drm/i915/gtt: Use shallow dma pages for scratch URL : https://patchwork.freedesktop.org/series/63595/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6466 -> Patchwork_13631 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13631 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13631, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13631/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13631: ### IGT changes ### Possible regressions * igt@i915_selftest@live_contexts: - fi-glk-dsi: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6466/fi-glk-dsi/igt@i915_selftest@live_contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13631/fi-glk-dsi/igt@i915_selftest@live_contexts.html - fi-bxt-j4205: [PASS][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6466/fi-bxt-j4205/igt@i915_selftest@live_contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13631/fi-bxt-j4205/igt@i915_selftest@live_contexts.html - fi-cml-u: [PASS][5] -> [DMESG-FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6466/fi-cml-u/igt@i915_selftest@live_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13631/fi-cml-u/igt@i915_selftest@live_contexts.html - fi-icl-u3: [PASS][7] -> [DMESG-FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6466/fi-icl-u3/igt@i915_selftest@live_contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13631/fi-icl-u3/igt@i915_selftest@live_contexts.html - fi-icl-u2: [PASS][9] -> [DMESG-FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6466/fi-icl-u2/igt@i915_selftest@live_contexts.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13631/fi-icl-u2/igt@i915_selftest@live_contexts.html - fi-bdw-5557u: [PASS][11] -> [DMESG-FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6466/fi-bdw-5557u/igt@i915_selftest@live_contexts.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13631/fi-bdw-5557u/igt@i915_selftest@live_contexts.html - fi-bdw-gvtdvm: [PASS][13] -> [DMESG-FAIL][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6466/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13631/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html - fi-kbl-guc: [PASS][15] -> [DMESG-FAIL][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6466/fi-kbl-guc/igt@i915_selftest@live_contexts.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13631/fi-kbl-guc/igt@i915_selftest@live_contexts.html - fi-kbl-r: [PASS][17] -> [DMESG-FAIL][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6466/fi-kbl-r/igt@i915_selftest@live_contexts.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13631/fi-kbl-r/igt@i915_selftest@live_contexts.html - fi-skl-6260u: [PASS][19] -> [DMESG-FAIL][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6466/fi-skl-6260u/igt@i915_selftest@live_contexts.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13631/fi-skl-6260u/igt@i915_selftest@live_contexts.html - fi-bsw-kefka: [PASS][21] -> [DMESG-FAIL][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6466/fi-bsw-kefka/igt@i915_selftest@live_contexts.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13631/fi-bsw-kefka/igt@i915_selftest@live_contexts.html - fi-kbl-8809g: [PASS][23] -> [DMESG-FAIL][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6466/fi-kbl-8809g/igt@i915_selftest@live_contexts.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13631/fi-kbl-8809g/igt@i915_selftest@live_contexts.html - fi-skl-gvtdvm: [PASS][25] -> [DMESG-FAIL][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6466/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13631/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html - fi-skl-6770hq: [PASS][27] -> [DMESG-FAIL][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6466/fi-skl-6770hq/igt@i915_selftest@live_contexts.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13631/fi-skl-6770hq/igt@i915_selftest@live_contexts.html - fi-cfl-guc: [PASS][29] -> [DMESG-FAIL][30] [29]:
Re: [Intel-gfx] screen freeze with 5.2-rc6 Dell XPS-13 skylake i915
James Bottomley schreef op do 11-07-2019 om 15:38 [-0700]: > On Thu, 2019-07-11 at 22:26 +, Souza, Jose wrote: > > It eventually comes back from screen freeze? Like moving the mouse or > > typing brings it back? > > No, it seems to be frozen for all time (at least until I got bored > waiting, which was probably 20 minutes). Even if I reboot the machine, > the current screen state stays until the system powers off. As I mentioned earlier, a suspend/resume cycle unfreezes the screen. And I seem to remember that, if the gnome screen-locking eventually kicks in, unlocking the screen still works, as the screen then isn't frozen anymore. Thanks, Paul Bolle ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gtt: Use shallow dma pages for scratch
== Series Details == Series: drm/i915/gtt: Use shallow dma pages for scratch URL : https://patchwork.freedesktop.org/series/63595/ State : warning == Summary == $ dim checkpatch origin/drm-tip f0b680cba1f4 drm/i915/gtt: Use shallow dma pages for scratch -:540: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'px' - possible side-effects? #540: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:262: +#define px_base(px) \ + __px_choose_expr(px, struct i915_page_dma *, __x, \ + __px_choose_expr(px, struct i915_page_table *, &__x->base, \ + __px_choose_expr(px, struct i915_page_directory *, &__x->base, \ + (void)0))) total: 0 errors, 0 warnings, 1 checks, 501 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Initial support for Tiger Lake (rev8)
== Series Details ==
Series: Initial support for Tiger Lake (rev8)
URL : https://patchwork.freedesktop.org/series/62726/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6466 -> Patchwork_13630
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13630/
Known issues
Here are the changes found in Patchwork_13630 that come from known issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@read_all_entries:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6466/fi-icl-u3/igt@debugfs_test@read_all_entries.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13630/fi-icl-u3/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6466/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13630/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#109485])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6466/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13630/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][7] -> [DMESG-WARN][8] ([fdo#102614])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6466/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13630/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_exec_reloc@basic-softpin:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +1
similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6466/fi-icl-u3/igt@gem_exec_re...@basic-softpin.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13630/fi-icl-u3/igt@gem_exec_re...@basic-softpin.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [FAIL][11] ([fdo#103167]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6466/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13630/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046
Participating hosts (50 -> 47)
--
Additional (3): fi-bsw-n3050 fi-apl-guc fi-pnv-d510
Missing(6): fi-kbl-soraka fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6466 -> Patchwork_13630
CI_DRM_6466: 26e891479328bfe381b635d9278f5f23143792d8 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5094: d7f140b5b02d054183a74842b4579cf7f5533927 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13630: a995fa3f5008138eab0b1d5b0f75565b8685f5ea @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a995fa3f5008 drm/i915/tgl: Update DPLL clock reference register
5f78ee1146f5 drm/i915/tgl: Add DPLL registers
74c7d63fdab7 drm/i915/tgl: Add vbt value mapping for DDC Bus pin
bf6f326339b3 drm/i915/tgl: port to ddc pin mapping
3f94caf873a3 drm/i915/tgl: Add gmbus gpio pin to port mapping
23a6017a675e drm/i915/gen12: MBUS B credit change
2cc14230d65d drm/i915/tgl: apply Display WA #1178 to fix type C dongles
12b705f92223 drm/i915/tgl: init ddi port A-C for Tiger Lake
1b6b9adeb31d drm/i915/tgl: Add additional PHYs for Tiger Lake
22cf397c2e61 drm/i915/tgl: Add additional ports for Tiger Lake
d8b25c49dada drm/i915/tgl: Add pll manager
c13c89a986b0 drm/i915/tgl: Add new pll ids
d6b06463f2d2 drm/i915/tgl: Add power well to support 4th pipe
5b6e27cc5532 drm/i915/tgl: Add power well support
9c274b6a4602 drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on transcoder A
cdb44f60e265 drm/i915/tgl: Check if pipe D is fused
f62cc20361e8 drm/i915/tgl: Add TGL PCI IDs
5ad7f4c463f0 drm/i915/tgl: Add TGL PCH detection in virtualized environment
17ed1276c7b9 drm/i915/tgl: Introduce Tiger Lake PCH
95c7ae28d487 drm/i915/tgl: add
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v4,1/2] drm/i915: Add support for retrying hotplug
== Series Details == Series: series starting with [v4,1/2] drm/i915: Add support for retrying hotplug URL : https://patchwork.freedesktop.org/series/63523/ State : success == Summary == CI Bug Log - changes from CI_DRM_6453_full -> Patchwork_13613_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13613_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110854]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb4/igt@gem_exec_balan...@smoke.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13613/shard-iclb8/igt@gem_exec_balan...@smoke.html * igt@gem_tiled_swapping@non-threaded: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108686]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-apl6/igt@gem_tiled_swapp...@non-threaded.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13613/shard-apl7/igt@gem_tiled_swapp...@non-threaded.html * igt@kms_color@pipe-c-ctm-green-to-red: - shard-skl: [PASS][5] -> [FAIL][6] ([fdo#107201]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl2/igt@kms_co...@pipe-c-ctm-green-to-red.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13613/shard-skl8/igt@kms_co...@pipe-c-ctm-green-to-red.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +5 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-apl6/igt@kms_cursor_...@pipe-c-cursor-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13613/shard-apl7/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([fdo#104108]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl3/igt@kms_fbcon_...@psr-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13613/shard-skl8/igt@kms_fbcon_...@psr-suspend.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([fdo#109507]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl5/igt@kms_f...@flip-vs-suspend-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13613/shard-skl10/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_flip_tiling@flip-changes-tiling-yf: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108228] / [fdo#108303]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl10/igt@kms_flip_til...@flip-changes-tiling-yf.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13613/shard-skl4/igt@kms_flip_til...@flip-changes-tiling-yf.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +5 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb3/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13613/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13613/shard-skl8/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [fdo#110403]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl8/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13613/shard-skl3/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103166]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb6/igt@kms_plane_low...@pipe-a-tiling-x.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13613/shard-iclb5/igt@kms_plane_low...@pipe-a-tiling-x.html * igt@kms_psr@psr2_sprite_render: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb2/igt@kms_psr@psr2_sprite_render.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13613/shard-iclb7/igt@kms_psr@psr2_sprite_render.html * igt@kms_setmode@basic: - shard-apl: [PASS][25] -> [FAIL][26]
Re: [Intel-gfx] screen freeze with 5.2-rc6 Dell XPS-13 skylake i915
On Thu, 2019-07-11 at 22:26 +, Souza, Jose wrote: > On Thu, 2019-07-11 at 14:57 -0700, James Bottomley wrote: > > On Thu, 2019-07-11 at 13:28 -0700, James Bottomley wrote: > > > I've also updated to the released 5.2 kernel and am running with > > > the > > > debug parameters you requested ... but so far no reproduction. > > > > OK, it's happened. I've attached the dmesg (it's 4MB > > uncompressed). > > Is there any other output you'd like from the machine? I've got an > > ssh session into it so I can try anything. > > Thanks, could you also share the output of this after the screen > freeze? > > /sys/kernel/debug/dri/0/i915_edp_psr_status > /sys/kernel/debug/dri/0/i915_display_info > /sys/kernel/debug/dri/0/i915_dmc_info > /sys/kernel/debug/pmc_core/package_cstate_show jarvis:~ # for f in `cat ~/tmp.txt`; do echo $f; cat $f; done /sys/kernel/debug/dri/0/i915_edp_psr_status Sink support: yes [0x01] PSR mode: PSR1 enabled Source PSR ctl: disabled [0x01f00726] Source PSR status: IDLE [0x04010216] Busy frontbuffer bits: 0x0001 /sys/kernel/debug/dri/0/i915_display_info CRTC info - CRTC 47: pipe: A, active=yes, (size=3200x1800), dither=no, bpp=24 fb: 118, pos: 0x0, size: 3200x1800 encoder 84: type: DDI A, connectors: connector 85: type: eDP-1, status: connected, mode: "": 0 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa cursor visible? yes, position (-3, 261), size 256x256, addr 0x0174 num_scalers=2, scaler_users=0 scaler_id=-1, scalers[0]: use=no, mode=0, scalers[1]: use=no, mode=0 --Plane id 30: type=PRI, crtc_pos= 0x 0, crtc_size=3200x1800, src_pos=0.x0., src_size=3200.x1800., format=XR24 little-endian (0x34325258), rotation=0 (0x0001) --Plane id 37: type=OVL, crtc_pos= 0x 0, crtc_size= 0x 0, src_pos=0.x0., src_size=0.x0., format=N/A, rotation=0 (0x0001) --Plane id 44: type=CUR, crtc_pos= -3x 261, crtc_size= 256x 256, src_pos=0.x0., src_size=256.x256., format=AR24 little-endian (0x34325241), rotation=0 (0x0001) underrun reporting: cpu=yes pch=yes CRTC 65: pipe: B, active=yes, (size=1600x1200), dither=no, bpp=24 fb: 118, pos: 0x0, size: 3200x1800 encoder 90: type: DDI B, connectors: connector 91: type: DP-1, status: connected, mode: "": 0 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x0 0x5 cursor visible? yes, position (-3, 261), size 256x256, addr 0x017c num_scalers=2, scaler_users=0 scaler_id=-1, scalers[0]: use=no, mode=0, scalers[1]: use=no, mode=0 --Plane id 48: type=PRI, crtc_pos= 0x 0, crtc_size=1600x1200, src_pos=0.x0., src_size=1600.x1200., format=XR24 little-endian (0x34325258), rotation=0 (0x0001) --Plane id 55: type=OVL, crtc_pos= 0x 0, crtc_size= 0x 0, src_pos=0.x0., src_size=0.x0., format=N/A, rotation=0 (0x0001) --Plane id 62: type=CUR, crtc_pos= -3x 261, crtc_size= 256x 256, src_pos=0.x0., src_size=256.x256., format=AR24 little-endian (0x34325241), rotation=0 (0x0001) underrun reporting: cpu=yes pch=yes CRTC 83: pipe: C, active=no, (size=0x0), dither=no, bpp=0 underrun reporting: cpu=yes pch=yes Connector info -- connector 85: type eDP-1, status: connected physical dimensions: 290x170mm subpixel order: Unknown CEA rev: 0 DPCD rev: 12 audio support: no fixed mode: "3200x1800": 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa DP branch device present: no modes: "3200x1800": 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa "3200x1800": 48 298600 3200 3248 3280 3360 1800 1803 1808 1852 0x40 0xa connector 91: type DP-1, status: connected physical dimensions: 430x320mm subpixel order: Unknown CEA rev: 0 DPCD rev: 12 audio support: no DP branch device present: yes Type: VGA ID: HW: 0.0 SW: 1.0 modes: "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x48 0x5 "1400x1050": 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6 "1400x1050": 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6 "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 "1280x960": 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 "1024x768": 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev8)
== Series Details == Series: Initial support for Tiger Lake (rev8) URL : https://patchwork.freedesktop.org/series/62726/ State : warning == Summary == $ dim checkpatch origin/drm-tip d6bd962a2eb2 drm/i915: Add 4th pipe and transcoder 95c7ae28d487 drm/i915/tgl: add initial Tiger Lake definitions 17ed1276c7b9 drm/i915/tgl: Introduce Tiger Lake PCH 5ad7f4c463f0 drm/i915/tgl: Add TGL PCH detection in virtualized environment f62cc20361e8 drm/i915/tgl: Add TGL PCI IDs -:34: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #34: FILE: include/drm/i915_pciids.h:587: +#define INTEL_TGL_12_IDS(info) \ + INTEL_VGA_DEVICE(0x9A49, info), \ + INTEL_VGA_DEVICE(0x9A40, info), \ + INTEL_VGA_DEVICE(0x9A59, info), \ + INTEL_VGA_DEVICE(0x9A60, info), \ + INTEL_VGA_DEVICE(0x9A68, info), \ + INTEL_VGA_DEVICE(0x9A70, info), \ + INTEL_VGA_DEVICE(0x9A78, info) -:34: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #34: FILE: include/drm/i915_pciids.h:587: +#define INTEL_TGL_12_IDS(info) \ + INTEL_VGA_DEVICE(0x9A49, info), \ + INTEL_VGA_DEVICE(0x9A40, info), \ + INTEL_VGA_DEVICE(0x9A59, info), \ + INTEL_VGA_DEVICE(0x9A60, info), \ + INTEL_VGA_DEVICE(0x9A68, info), \ + INTEL_VGA_DEVICE(0x9A70, info), \ + INTEL_VGA_DEVICE(0x9A78, info) total: 1 errors, 0 warnings, 1 checks, 21 lines checked cdb44f60e265 drm/i915/tgl: Check if pipe D is fused 9c274b6a4602 drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on transcoder A 5b6e27cc5532 drm/i915/tgl: Add power well support d6b06463f2d2 drm/i915/tgl: Add power well to support 4th pipe c13c89a986b0 drm/i915/tgl: Add new pll ids d8b25c49dada drm/i915/tgl: Add pll manager 22cf397c2e61 drm/i915/tgl: Add additional ports for Tiger Lake 1b6b9adeb31d drm/i915/tgl: Add additional PHYs for Tiger Lake 12b705f92223 drm/i915/tgl: init ddi port A-C for Tiger Lake 2cc14230d65d drm/i915/tgl: apply Display WA #1178 to fix type C dongles 23a6017a675e drm/i915/gen12: MBUS B credit change 3f94caf873a3 drm/i915/tgl: Add gmbus gpio pin to port mapping bf6f326339b3 drm/i915/tgl: port to ddc pin mapping 74c7d63fdab7 drm/i915/tgl: Add vbt value mapping for DDC Bus pin 5f78ee1146f5 drm/i915/tgl: Add DPLL registers a995fa3f5008 drm/i915/tgl: Update DPLL clock reference register ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] screen freeze with 5.2-rc6 Dell XPS-13 skylake i915
On Thu, 2019-07-11 at 14:57 -0700, James Bottomley wrote: > On Thu, 2019-07-11 at 13:28 -0700, James Bottomley wrote: > > I've also updated to the released 5.2 kernel and am running with > > the > > debug parameters you requested ... but so far no reproduction. > > OK, it's happened. I've attached the dmesg (it's 4MB uncompressed). > Is there any other output you'd like from the machine? I've got an > ssh > session into it so I can try anything. Thanks, could you also share the output of this after the screen freeze? /sys/kernel/debug/dri/0/i915_edp_psr_status /sys/kernel/debug/dri/0/i915_display_info /sys/kernel/debug/dri/0/i915_dmc_info /sys/kernel/debug/pmc_core/package_cstate_show It eventually comes back from screen freeze? Like moving the mouse or typing brings it back? > > James
[Intel-gfx] [CI] drm/i915/gtt: Use shallow dma pages for scratch
We only use the dma pages for scratch, and so do not need to allocate
the extra storage for the shadow page directory.
v2: Refrain from reintroducing I915_PDES
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 196
drivers/gpu/drm/i915/i915_gem_gtt.h | 23 +++-
2 files changed, 100 insertions(+), 119 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 236c964dd761..1a94bbddc467 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -594,26 +594,17 @@ static void cleanup_page_dma(struct i915_address_space
*vm,
#define kmap_atomic_px(px) kmap_atomic(px_base(px)->page)
-#define fill_px(vm, px, v) fill_page_dma((vm), px_base(px), (v))
-#define fill32_px(vm, px, v) fill_page_dma_32((vm), px_base(px), (v))
-
-static void fill_page_dma(struct i915_address_space *vm,
- struct i915_page_dma *p,
- const u64 val)
+static void
+fill_page_dma(const struct i915_page_dma *p, const u64 val, unsigned int count)
{
- u64 * const vaddr = kmap_atomic(p->page);
-
- memset64(vaddr, val, PAGE_SIZE / sizeof(val));
-
- kunmap_atomic(vaddr);
+ kunmap_atomic(memset64(kmap_atomic(p->page), val, count));
}
-static void fill_page_dma_32(struct i915_address_space *vm,
-struct i915_page_dma *p,
-const u32 v)
-{
- fill_page_dma(vm, p, (u64)v << 32 | v);
-}
+#define fill_px(px, v) fill_page_dma(px_base(px), (v), PAGE_SIZE / sizeof(u64))
+#define fill32_px(px, v) do { \
+ u64 v__ = lower_32_bits(v); \
+ fill_px((px), v__ << 32 | v__); \
+} while (0)
static int
setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
@@ -687,6 +678,21 @@ static void cleanup_scratch_page(struct i915_address_space
*vm)
__free_pages(p->page, order);
}
+static void free_scratch(struct i915_address_space *vm)
+{
+ if (!vm->scratch_page.daddr) /* set to 0 on clones */
+ return;
+
+ if (vm->scratch_pdp.daddr)
+ cleanup_page_dma(vm, >scratch_pdp);
+ if (vm->scratch_pd.daddr)
+ cleanup_page_dma(vm, >scratch_pd);
+ if (vm->scratch_pt.daddr)
+ cleanup_page_dma(vm, >scratch_pt);
+
+ cleanup_scratch_page(vm);
+}
+
static struct i915_page_table *alloc_pt(struct i915_address_space *vm)
{
struct i915_page_table *pt;
@@ -711,18 +717,6 @@ static void free_pt(struct i915_address_space *vm, struct
i915_page_table *pt)
kfree(pt);
}
-static void gen8_initialize_pt(struct i915_address_space *vm,
- struct i915_page_table *pt)
-{
- fill_px(vm, pt, vm->scratch_pte);
-}
-
-static void gen6_initialize_pt(struct i915_address_space *vm,
- struct i915_page_table *pt)
-{
- fill32_px(vm, pt, vm->scratch_pte);
-}
-
static struct i915_page_directory *__alloc_pd(void)
{
struct i915_page_directory *pd;
@@ -765,9 +759,11 @@ static void free_pd(struct i915_address_space *vm,
kfree(pd);
}
-#define init_pd(vm, pd, to) { \
- fill_px((vm), (pd), gen8_pde_encode(px_dma(to), I915_CACHE_LLC)); \
- memset_p((pd)->entry, (to), 512); \
+static void init_pd(struct i915_page_directory *pd,
+ struct i915_page_dma *scratch)
+{
+ fill_px(pd, gen8_pde_encode(scratch->daddr, I915_CACHE_LLC));
+ memset_p(pd->entry, scratch, 512);
}
static inline void
@@ -869,12 +865,11 @@ static void gen8_ppgtt_clear_pd(struct i915_address_space
*vm,
u32 pde;
gen8_for_each_pde(pt, pd, start, length, pde) {
- GEM_BUG_ON(pt == vm->scratch_pt);
+ GEM_BUG_ON(px_base(pt) == >scratch_pt);
atomic_inc(>used);
gen8_ppgtt_clear_pt(vm, pt, start, length);
- if (release_pd_entry(pd, pde, >used,
-px_base(vm->scratch_pt)))
+ if (release_pd_entry(pd, pde, >used, >scratch_pt))
free_pt(vm, pt);
}
}
@@ -890,12 +885,11 @@ static void gen8_ppgtt_clear_pdp(struct
i915_address_space *vm,
unsigned int pdpe;
gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
- GEM_BUG_ON(pd == vm->scratch_pd);
+ GEM_BUG_ON(px_base(pd) == >scratch_pd);
atomic_inc(>used);
gen8_ppgtt_clear_pd(vm, pd, start, length);
- if (release_pd_entry(pdp, pdpe, >used,
-px_base(vm->scratch_pd)))
+ if (release_pd_entry(pdp, pdpe, >used, >scratch_pd))
free_pd(vm, pd);
[Intel-gfx] ✓ Fi.CI.BAT: success for Modular FIA (rev4)
== Series Details ==
Series: Modular FIA (rev4)
URL : https://patchwork.freedesktop.org/series/63175/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6465 -> Patchwork_13629
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13629/
Known issues
Here are the changes found in Patchwork_13629 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6465/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13629/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#109485])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6465/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13629/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@prime_busy@basic-wait-after-default:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6465/fi-icl-u3/igt@prime_b...@basic-wait-after-default.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13629/fi-icl-u3/igt@prime_b...@basic-wait-after-default.html
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: [PASS][7] -> [DMESG-WARN][8] ([fdo#106387]) +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6465/fi-ilk-650/igt@prime_v...@basic-fence-flip.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13629/fi-ilk-650/igt@prime_v...@basic-fence-flip.html
Possible fixes
* {igt@gem_ctx_switch@legacy-render}:
- fi-icl-guc: [INCOMPLETE][9] ([fdo#107713]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6465/fi-icl-guc/igt@gem_ctx_swi...@legacy-render.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13629/fi-icl-guc/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_exec_create@basic:
- fi-cml-u: [INCOMPLETE][11] ([fdo#110566]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6465/fi-cml-u/igt@gem_exec_cre...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13629/fi-cml-u/igt@gem_exec_cre...@basic.html
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [INCOMPLETE][13] ([fdo#111050]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6465/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13629/fi-skl-iommu/igt@i915_selftest@live_contexts.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-dsi: [INCOMPLETE][15] ([fdo#107713] / [fdo#108569]) ->
[PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6465/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13629/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
Participating hosts (53 -> 46)
--
Missing(7): fi-kbl-soraka fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-bdw-samus fi-byt-clapper fi-skl-6600u
Build changes
-
* Linux: CI_DRM_6465 -> Patchwork_13629
CI_DRM_6465: 91f0552e964f1126335af43fd4fb6716bbddc7ec @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5094: d7f140b5b02d054183a74842b4579cf7f5533927 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13629: 9570f60f2f05a77fd998f5771961f58db99fc180 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9570f60f2f05 drm/i915: Add modular FIA
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13629/
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Re: [Intel-gfx] [PATCH] drm/i915/tgl: apply Display WA #1178 to fix type C dongles
On Thu, Jul 11, 2019 at 02:35:17PM -0700, Lucas De Marchi wrote:
> Add port C to workaround to cover Tiger Lake.
>
> Cc: Rodrigo Vivi
> Signed-off-by: Lucas De Marchi
> Reviewed-by: Rodrigo Vivi
> Link:
> https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-22-lucas.demar...@intel.com
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 12 +---
> drivers/gpu/drm/i915/i915_reg.h| 4 +++-
> 2 files changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 12aa9ce08d95..d25fd5a25199 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -453,6 +453,7 @@ icl_combo_phy_aux_power_well_enable(struct
> drm_i915_private *dev_priv,
> int pw_idx = power_well->desc->hsw.idx;
> enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
> u32 val;
> + int wa_idx_max;
>
> val = I915_READ(regs->driver);
> I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
> @@ -462,9 +463,14 @@ icl_combo_phy_aux_power_well_enable(struct
> drm_i915_private *dev_priv,
>
> hsw_wait_for_power_well_enable(dev_priv, power_well);
>
> - /* Display WA #1178: icl */
> - if (IS_ICELAKE(dev_priv) &&
> - pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
> + /* Display WA #1178: icl, tgl */
> + if (IS_TIGERLAKE(dev_priv))
> + wa_idx_max = ICL_PW_CTL_IDX_AUX_C;
> + else
> + wa_idx_max = ICL_PW_CTL_IDX_AUX_B;
> +
> + if (!IS_ELKHARTLAKE(dev_priv) &&
> + pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= wa_idx_max &&
> !intel_bios_is_port_edp(dev_priv, (enum port)phy)) {
> val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));
> val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b1a6628199e4..a8e2e05e7d7e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9274,9 +9274,11 @@ enum skl_power_gate {
> #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
> #define _ICL_AUX_ANAOVRD1_A 0x162398
> #define _ICL_AUX_ANAOVRD1_B 0x6C398
> +#define _TGL_AUX_ANAOVRD1_C 0x160398
> #define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
> _ICL_AUX_ANAOVRD1_A, \
> - _ICL_AUX_ANAOVRD1_B))
> + _ICL_AUX_ANAOVRD1_B, \
> + _TGL_AUX_ANAOVRD1_C))
> #define ICL_AUX_ANAOVRD1_LDO_BYPASS(1 << 7)
> #define ICL_AUX_ANAOVRD1_ENABLE(1 << 0)
>
> --
> 2.21.0
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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[Intel-gfx] [PATCH] drm/i915/tgl: apply Display WA #1178 to fix type C dongles
Add port C to workaround to cover Tiger Lake.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-22-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_display_power.c | 12 +---
drivers/gpu/drm/i915/i915_reg.h| 4 +++-
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 12aa9ce08d95..d25fd5a25199 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -453,6 +453,7 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private
*dev_priv,
int pw_idx = power_well->desc->hsw.idx;
enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
u32 val;
+ int wa_idx_max;
val = I915_READ(regs->driver);
I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
@@ -462,9 +463,14 @@ icl_combo_phy_aux_power_well_enable(struct
drm_i915_private *dev_priv,
hsw_wait_for_power_well_enable(dev_priv, power_well);
- /* Display WA #1178: icl */
- if (IS_ICELAKE(dev_priv) &&
- pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
+ /* Display WA #1178: icl, tgl */
+ if (IS_TIGERLAKE(dev_priv))
+ wa_idx_max = ICL_PW_CTL_IDX_AUX_C;
+ else
+ wa_idx_max = ICL_PW_CTL_IDX_AUX_B;
+
+ if (!IS_ELKHARTLAKE(dev_priv) &&
+ pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= wa_idx_max &&
!intel_bios_is_port_edp(dev_priv, (enum port)phy)) {
val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));
val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b1a6628199e4..a8e2e05e7d7e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9274,9 +9274,11 @@ enum skl_power_gate {
#define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
#define _ICL_AUX_ANAOVRD1_A0x162398
#define _ICL_AUX_ANAOVRD1_B0x6C398
+#define _TGL_AUX_ANAOVRD1_C0x160398
#define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
_ICL_AUX_ANAOVRD1_A, \
- _ICL_AUX_ANAOVRD1_B))
+ _ICL_AUX_ANAOVRD1_B, \
+ _TGL_AUX_ANAOVRD1_C))
#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
--
2.21.0
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Re: [Intel-gfx] [PATCH v3 15/21] drm/i915/tgl: apply Display WA #1178 to fix type C dongles
On Thu, Jul 11, 2019 at 01:52:13PM -0700, Matt Roper wrote:
On Thu, Jul 11, 2019 at 10:31:09AM -0700, Lucas De Marchi wrote:
Add port C to workaround to cover Tiger Lake.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/display/intel_display_power.c | 7 +++
drivers/gpu/drm/i915/i915_reg.h| 4 +++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 12aa9ce08d95..061432862c7d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -453,6 +453,7 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private
*dev_priv,
int pw_idx = power_well->desc->hsw.idx;
enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
u32 val;
+ int wa_idx_max;
val = I915_READ(regs->driver);
I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
@@ -462,6 +463,12 @@ icl_combo_phy_aux_power_well_enable(struct
drm_i915_private *dev_priv,
hsw_wait_for_power_well_enable(dev_priv, power_well);
+ /* Display WA #1178: icl, tgl */
+ if (IS_TIGERLAKE(dev_priv))
+ wa_idx_max = ICL_PW_CTL_IDX_AUX_C;
+ else
+ wa_idx_max = ICL_PW_CTL_IDX_AUX_B;
+
/* Display WA #1178: icl */
if (IS_ICELAKE(dev_priv) &&
I think this needs to change to !ehl now.
pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
And this should use your new wa_idx_max variable
thanks for catching this, wrong rebase on my side.
Lucas De Marchi
Matt
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ca70be40a467..ad96c5b4975c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9244,9 +9244,11 @@ enum skl_power_gate {
#define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
#define _ICL_AUX_ANAOVRD1_A0x162398
#define _ICL_AUX_ANAOVRD1_B0x6C398
+#define _TGL_AUX_ANAOVRD1_C0x160398
#define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
_ICL_AUX_ANAOVRD1_A, \
- _ICL_AUX_ANAOVRD1_B))
+ _ICL_AUX_ANAOVRD1_B, \
+ _TGL_AUX_ANAOVRD1_C))
#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
--
2.21.0
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v3,1/2] drm/i915/display/icl: Bump up the vdisplay to reflect higher transcoder vertical limits
== Series Details == Series: series starting with [v3,1/2] drm/i915/display/icl: Bump up the vdisplay to reflect higher transcoder vertical limits URL : https://patchwork.freedesktop.org/series/63522/ State : success == Summary == CI Bug Log - changes from CI_DRM_6453_full -> Patchwork_13612_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13612_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110854]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb4/igt@gem_exec_balan...@smoke.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-iclb7/igt@gem_exec_balan...@smoke.html * igt@gem_exec_nop@basic-series: - shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] / [fdo#109100]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb7/igt@gem_exec_...@basic-series.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-iclb7/igt@gem_exec_...@basic-series.html * igt@gem_exec_suspend@basic-s3: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#104108]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl4/igt@gem_exec_susp...@basic-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-skl2/igt@gem_exec_susp...@basic-s3.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +5 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-apl2/igt@i915_susp...@fence-restore-tiled2untiled.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-apl7/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_flip@flip-vs-suspend: - shard-kbl: [PASS][9] -> [INCOMPLETE][10] ([fdo#103665]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-kbl7/igt@kms_f...@flip-vs-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-kbl7/igt@kms_f...@flip-vs-suspend.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-render.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-render.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145] / [fdo#110403]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl8/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-skl3/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_sprite_render: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb2/igt@kms_psr@psr2_sprite_render.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-iclb6/igt@kms_psr@psr2_sprite_render.html Possible fixes * igt@gem_softpin@noreloc-s3: - shard-skl: [INCOMPLETE][19] ([fdo#104108] / [fdo#107773]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl9/igt@gem_soft...@noreloc-s3.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-skl6/igt@gem_soft...@noreloc-s3.html * igt@kms_color@pipe-b-ctm-red-to-blue: - shard-skl: [FAIL][21] ([fdo#107201]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl3/igt@kms_co...@pipe-b-ctm-red-to-blue.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-skl2/igt@kms_co...@pipe-b-ctm-red-to-blue.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [DMESG-WARN][23] ([fdo#108566]) -> [PASS][24] +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-kbl3/igt@kms_cursor_...@pipe-c-cursor-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-kbl6/igt@kms_cursor_...@pipe-c-cursor-suspend.html *
Re: [Intel-gfx] [PATCH v3 07/21] drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on transcoder A
On Thu, Jul 11, 2019 at 10:31:01AM -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza
>
> On TGL the special EDP transcoder is gone and it should be handled by
> transcoder A.
>
> v2 (Lucas):
> - Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggested by Ville)
> - Use crtc->dev since new_crtc_state->state may be NULL on atomic
> commit (suggested by Maarten)
> v3 (Lucas):
> - Rename power domain so it's clear it can also be used for transcoder
> A in TGL (requested by José and Manasi)
>
> Cc: Imre Deak
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Lucas De Marchi
> Acked-by: José Roberto de Souza
With the name change it looks good to me
Reviewed-by: Manasi Navare
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++---
> drivers/gpu/drm/i915/display/intel_display_power.h | 3 ++-
> drivers/gpu/drm/i915/display/intel_vdsc.c | 14 ++
> 3 files changed, 15 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 7e22a2704843..6a5e0d0724cb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -48,8 +48,8 @@ intel_display_power_domain_str(enum
> intel_display_power_domain domain)
> return "TRANSCODER_C";
> case POWER_DOMAIN_TRANSCODER_EDP:
> return "TRANSCODER_EDP";
> - case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
> - return "TRANSCODER_EDP_VDSC";
> + case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
> + return "TRANSCODER_VDSC_PW2";
> case POWER_DOMAIN_TRANSCODER_DSI_A:
> return "TRANSCODER_DSI_A";
> case POWER_DOMAIN_TRANSCODER_DSI_C:
> @@ -2450,7 +2450,7 @@ void intel_display_power_put(struct drm_i915_private
> *dev_priv,
>*/
> #define ICL_PW_2_POWER_DOMAINS ( \
> ICL_PW_3_POWER_DOMAINS |\
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> /*
>* - KVMR (HW control)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 8f43f7051a16..cc6956132ebc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -25,7 +25,8 @@ enum intel_display_power_domain {
> POWER_DOMAIN_TRANSCODER_B,
> POWER_DOMAIN_TRANSCODER_C,
> POWER_DOMAIN_TRANSCODER_EDP,
> - POWER_DOMAIN_TRANSCODER_EDP_VDSC,
> + /* VDSC/joining for TRANSCODER_EDP (ICL) or TRANSCODER_A (TGL) */
> + POWER_DOMAIN_TRANSCODER_VDSC_PW2,
> POWER_DOMAIN_TRANSCODER_DSI_A,
> POWER_DOMAIN_TRANSCODER_DSI_C,
> POWER_DOMAIN_PORT_DDI_A_LANES,
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index ffec807b8960..4ab19c432ef5 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -459,17 +459,23 @@ int intel_dp_compute_dsc_params(struct intel_dp
> *intel_dp,
> enum intel_display_power_domain
> intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> {
> + struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc->dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> /*
> - * On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
> - * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
> + * On ICL VDSC/joining for eDP transcoder uses a separate power well,
> + * PW2. This requires POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain.
>* For any other transcoder, VDSC/joining uses the power well associated
>* with the pipe/transcoder in use. Hence another reference on the
>* transcoder power domain will suffice.
> + *
> + * On TGL we have the same mapping, but for transcoder A (the special
> + * TRANSCODER_EDP is gone).
>*/
> - if (cpu_transcoder == TRANSCODER_EDP)
> - return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
> + if (INTEL_GEN(i915) >= 12 && cpu_transcoder == TRANSCODER_A)
> + return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
> + else if (cpu_transcoder == TRANSCODER_EDP)
> + return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
> else
> return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
> }
> --
> 2.21.0
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH v3 18/21] drm/i915/tgl: port to ddc pin mapping
On Thu, Jul 11, 2019 at 10:31:12AM -0700, Lucas De Marchi wrote:
> Make the icl function generic so it is based on phy type and can be
> applied to tgl as well.
>
> I checked if this could not apply to EHL as well, but unfortunately
> there the HPD and DDC/GMBUS pins for DDI C are mapped to TypeC Port 1
> even though it doesn't have TC phy.
>
> v2: don't add a separate function for TGL, but rather reuse the ICL one
> (suggested by Rodrigo)
> v3: rebase after the introduction of enum phy and use it for the
> conversions
>
> Cc: Anusha Srivatsa
> Cc: Rodrigo Vivi
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 36 ++-
> 1 file changed, 9 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 0ebec69bbbfc..77af0dfd93ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2930,33 +2930,15 @@ static u8 cnp_port_to_ddc_pin(struct drm_i915_private
> *dev_priv,
>
> static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port
> port)
> {
> - u8 ddc_pin;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
>
> - switch (port) {
> - case PORT_A:
> - ddc_pin = GMBUS_PIN_1_BXT;
> - break;
> - case PORT_B:
> - ddc_pin = GMBUS_PIN_2_BXT;
> - break;
> - case PORT_C:
> - ddc_pin = GMBUS_PIN_9_TC1_ICP;
> - break;
> - case PORT_D:
> - ddc_pin = GMBUS_PIN_10_TC2_ICP;
> - break;
> - case PORT_E:
> - ddc_pin = GMBUS_PIN_11_TC3_ICP;
> - break;
> - case PORT_F:
> - ddc_pin = GMBUS_PIN_12_TC4_ICP;
> - break;
> - default:
> - MISSING_CASE(port);
> - ddc_pin = GMBUS_PIN_2_BXT;
> - break;
> - }
> - return ddc_pin;
> + if (intel_phy_is_combo(dev_priv, phy))
> + return GMBUS_PIN_1_BXT + port;
> + else if (intel_phy_is_tc(dev_priv, phy))
> + return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
> +
> + WARN(1, "Unknown port:%c\n", port_name(port));
> + return GMBUS_PIN_2_BXT;
> }
>
> static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port
> port)
> @@ -3019,7 +3001,7 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private
> *dev_priv,
>
> if (HAS_PCH_MCC(dev_priv))
> ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
> - else if (HAS_PCH_ICP(dev_priv))
> + else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_ICP(dev_priv))
> ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
> else if (HAS_PCH_CNP(dev_priv))
> ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
> --
> 2.21.0
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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[Intel-gfx] [PATCH v3 1/1] drm/i915: Add modular FIA
From: Anusha Srivatsa
Some platforms may have Modular FIA. If Modular FIA is used in the SOC,
then Display Driver will access the additional instances of
FIA based on pre-assigned offset in GTTMADDR space.
Each Modular FIA instance has its own IOSF Sideband Port ID
and it houses only 2 Type-C Port. In SOC that has more than
two Type-C Ports, there are multiple instances of Modular FIA.
Gunit will need to use different destination ID when it access
different pair of Type-C Port.
The DFLEXDPSP register has Modular FIA bit starting on Tiger Lake. If
Modular FIA is used in the SOC, this register bit exists in all the
instances of Modular FIA. IOM FW is required to program only the MF bit
in first FIA instance that houses the Type-C Port 0 and Port 1, for
Display Driver to read from.
v2 (Lucas):
- Move all accesses to FIA to be contained in intel_tc.c, along with
display_fia that is now called tc_phy_fia
- Save the fia instance number on intel_digital_port, so we don't have
to query if modular FIA is used on every access
v3 (Lucas): Make function static
v4 (Lucas): Move enum phy_fia to the header and use it in
intel_digital_port (suggested by Ville)
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
Signed-off-by: Lucas De Marchi
Acked-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.h | 6 +++
drivers/gpu/drm/i915/display/intel_tc.c | 43
drivers/gpu/drm/i915/i915_reg.h | 13 --
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
5 files changed, 52 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 8a4a57ef82a2..8b048976f7b4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -243,6 +243,12 @@ enum phy {
#define phy_name(a) ((a) + 'A')
+enum phy_fia {
+ FIA1,
+ FIA2,
+ FIA3,
+};
+
#define for_each_pipe(__dev_priv, __p) \
for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index f44ee4bfe7c8..9400da4f7916 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -22,6 +22,24 @@ static const char *tc_port_mode_name(enum tc_port_mode mode)
return names[mode];
}
+static bool has_modular_fia(struct drm_i915_private *i915)
+{
+ if (!INTEL_INFO(i915)->display.has_modular_fia)
+ return false;
+
+ return intel_uncore_read(>uncore,
+PORT_TX_DFLEXDPSP(FIA1)) & MODULAR_FIA_MASK;
+}
+
+static enum phy_fia tc_port_to_fia(struct drm_i915_private *i915,
+ enum tc_port tc_port)
+{
+ if (!has_modular_fia(i915))
+ return FIA1;
+
+ return tc_port / 2;
+}
+
u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@@ -29,7 +47,8 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port
*dig_port)
struct intel_uncore *uncore = >uncore;
u32 lane_mask;
- lane_mask = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
+ lane_mask = intel_uncore_read(uncore,
+ PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
WARN_ON(lane_mask == 0x);
@@ -78,7 +97,8 @@ void intel_tc_port_set_fia_lane_count(struct
intel_digital_port *dig_port,
WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
- val = intel_uncore_read(uncore, PORT_TX_DFLEXDPMLE1);
+ val = intel_uncore_read(uncore,
+ PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
switch (required_lanes) {
@@ -97,7 +117,8 @@ void intel_tc_port_set_fia_lane_count(struct
intel_digital_port *dig_port,
MISSING_CASE(required_lanes);
}
- intel_uncore_write(uncore, PORT_TX_DFLEXDPMLE1, val);
+ intel_uncore_write(uncore,
+ PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val);
}
static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
@@ -129,7 +150,8 @@ static u32 tc_port_live_status_mask(struct
intel_digital_port *dig_port)
u32 mask = 0;
u32 val;
- val = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
+ val = intel_uncore_read(uncore,
+ PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
if (val == 0x) {
DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, nothing connected\n",
@@ -159,7 +181,8 @@ static bool icl_tc_phy_status_complete(struct
intel_digital_port *dig_port)
struct intel_uncore *uncore = >uncore;
u32 val;
- val = intel_uncore_read(uncore,
[Intel-gfx] [PATCH v3 0/1] Modular FIA
https://patchwork.freedesktop.org/series/63175/ Changes: - Remove already merged patches - Move enum phy_fia to the header and use it Anusha Srivatsa (1): drm/i915: Add modular FIA drivers/gpu/drm/i915/display/intel_display.h | 6 +++ drivers/gpu/drm/i915/display/intel_tc.c | 43 drivers/gpu/drm/i915/i915_reg.h | 13 -- drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_drv.h | 1 + 5 files changed, 52 insertions(+), 12 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 1/2] drm/i915: Add support for retrying hotplug
On Thu, Jul 11, 2019 at 11:05:15PM +0300, Ville Syrjälä wrote:
> On Wed, Jul 10, 2019 at 03:14:59PM -0700, José Roberto de Souza wrote:
> > From: Imre Deak
> >
> > There is some scenarios that we are aware that sink probe can fail,
> > so lets add the infrastructure to let hotplug() hook to request
> > another probe after some time.
> >
> > v2: Handle shared HPD pins (Imre)
> > v3: Rebased
> > v4: Renamed INTEL_HOTPLUG_NOCHANGE to INTEL_HOTPLUG_UNCHANGED to keep
> > it consistent(Rodrigo)
> >
> > Cc: Ville Syrjälä
Tested-by: Shane McKee
> > Reviewed-by: Rodrigo Vivi
> > Signed-off-by: José Roberto de Souza
> > Signed-off-by: Jani Nikula
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++--
> > drivers/gpu/drm/i915/display/intel_dp.c | 12 ++--
> > drivers/gpu/drm/i915/display/intel_hotplug.c | 59 +++-
> > drivers/gpu/drm/i915/display/intel_hotplug.h | 5 +-
> > drivers/gpu/drm/i915/display/intel_sdvo.c| 8 ++-
> > drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> > drivers/gpu/drm/i915/i915_drv.h | 3 +-
> > drivers/gpu/drm/i915/intel_drv.h | 11 +++-
> > 8 files changed, 80 insertions(+), 32 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index ad638e7f27bb..734c004800f8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4047,14 +4047,16 @@ static int intel_hdmi_reset_link(struct
> > intel_encoder *encoder,
> > return modeset_pipe(>base, ctx);
> > }
> >
> > -static bool intel_ddi_hotplug(struct intel_encoder *encoder,
> > - struct intel_connector *connector)
> > +static enum intel_hotplug_state
> > +intel_ddi_hotplug(struct intel_encoder *encoder,
> > + struct intel_connector *connector,
> > + bool irq_received)
> > {
> > struct drm_modeset_acquire_ctx ctx;
> > - bool changed;
> > + enum intel_hotplug_state state;
> > int ret;
> >
> > - changed = intel_encoder_hotplug(encoder, connector);
> > + state = intel_encoder_hotplug(encoder, connector, irq_received);
> >
> > drm_modeset_acquire_init(, 0);
> >
> > @@ -4076,7 +4078,7 @@ static bool intel_ddi_hotplug(struct intel_encoder
> > *encoder,
> > drm_modeset_acquire_fini();
> > WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
> >
> > - return changed;
> > + return state;
> > }
> >
> > static struct intel_connector *
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 0bdb7ecc5a81..4423abbc7907 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -4853,14 +4853,16 @@ int intel_dp_retrain_link(struct intel_encoder
> > *encoder,
> > * retrain the link to get a picture. That's in case no
> > * userspace component reacted to intermittent HPD dip.
> > */
> > -static bool intel_dp_hotplug(struct intel_encoder *encoder,
> > -struct intel_connector *connector)
> > +static enum intel_hotplug_state
> > +intel_dp_hotplug(struct intel_encoder *encoder,
> > +struct intel_connector *connector,
> > +bool irq_received)
> > {
> > struct drm_modeset_acquire_ctx ctx;
> > - bool changed;
> > + enum intel_hotplug_state state;
> > int ret;
> >
> > - changed = intel_encoder_hotplug(encoder, connector);
> > + state = intel_encoder_hotplug(encoder, connector, irq_received);
> >
> > drm_modeset_acquire_init(, 0);
> >
> > @@ -4879,7 +4881,7 @@ static bool intel_dp_hotplug(struct intel_encoder
> > *encoder,
> > drm_modeset_acquire_fini();
> > WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
> >
> > - return changed;
> > + return state;
> > }
> >
> > static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
> > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
> > b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > index ea3de4acc850..2ca92780c659 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > @@ -112,6 +112,7 @@ enum hpd_pin intel_hpd_pin_default(struct
> > drm_i915_private *dev_priv,
> >
> > #define HPD_STORM_DETECT_PERIOD1000
> > #define HPD_STORM_REENABLE_DELAY (2 * 60 * 1000)
> > +#define HPD_RETRY_DELAY1000
> >
> > /**
> > * intel_hpd_irq_storm_detect - gather stats and detect HPD IRQ storm on a
> > pin
> > @@ -266,8 +267,10 @@ static void intel_hpd_irq_storm_reenable_work(struct
> > work_struct *work)
> > intel_runtime_pm_put(_priv->runtime_pm, wakeref);
> > }
> >
> > -bool intel_encoder_hotplug(struct intel_encoder *encoder,
> > - struct intel_connector *connector)
> > +enum intel_hotplug_state
> >
Re: [Intel-gfx] [PATCH v4 2/2] drm/i915: Enable hotplug retry
On Thu, Jul 11, 2019 at 12:49:35PM -0700, Nathan Ciobanu wrote:
> On Wed, Jul 10, 2019 at 03:15:00PM -0700, José Roberto de Souza wrote:
> > Right now we are aware of two cases that needs another hotplug retry:
> > - Unpowered type-c dongles
> > - HDMI slow unplug
> >
> > Both have a complete explanation in the code to schedule another run
> > of the hotplug handler.
> >
> > It could have more checks to just trigger the retry in those two
> > specific cases but why would sink signal a long pulse if there is
> > no change? Also the drawback of running the hotplug handler again
> > is really low and that could fix another cases that we are not
> > aware.
> >
> > Also retrying for old DP ports(non-DDI) to make it consistent and not
> > cause CI failures if those systems are connected to chamelium boards
> > that will be used to simulate the issues reported in here.
> >
> > v2: Also retrying for old DP ports(non-DDI)(Imre)
> >
> > v4: Renamed INTEL_HOTPLUG_NOCHANGE to INTEL_HOTPLUG_UNCHANGED to keep
> > it consistent(Rodrigo)
> >
> > Cc: Ville Syrjälä
> > Cc: Imre Deak
> > Cc: Jani Nikula
Tested-by: Shane McKee
> > Reviewed-by: Imre Deak
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 21 +
> > drivers/gpu/drm/i915/display/intel_dp.c | 7 ++
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 28 ++-
> > 3 files changed, 55 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 734c004800f8..ea6d1873f6cb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4052,6 +4052,7 @@ intel_ddi_hotplug(struct intel_encoder *encoder,
> > struct intel_connector *connector,
> > bool irq_received)
> > {
> > + struct intel_digital_port *dig_port = enc_to_dig_port(>base);
> > struct drm_modeset_acquire_ctx ctx;
> > enum intel_hotplug_state state;
> > int ret;
> > @@ -4078,6 +4079,26 @@ intel_ddi_hotplug(struct intel_encoder *encoder,
> > drm_modeset_acquire_fini();
> > WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
> >
> > + /*
> > +* Unpowered type-c dongles can take some time to boot and be
> > +* responsible, so here giving some time to those dongles to power up
> > +* and then retrying the probe.
> > +*
> > +* On many platforms the HDMI live state signal is known to be
> > +* unreliable, so we can't use it to detect if a sink is connected or
> > +* not. Instead we detect if it's connected based on whether we can
> > +* read the EDID or not. That in turn has a problem during disconnect,
> > +* since the HPD interrupt may be raised before the DDC lines get
> > +* disconnected (due to how the required length of DDC vs. HPD
> > +* connector pins are specified) and so we'll still be able to get a
> > +* valid EDID. To solve this schedule another detection cycle if this
> > +* time around we didn't detect any change in the sink's connection
> > +* status.
> > +*/
> > + if (state == INTEL_HOTPLUG_UNCHANGED && irq_received &&
> > + !dig_port->dp.is_mst)
> > + state = INTEL_HOTPLUG_RETRY;
> > +
> > return state;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 4423abbc7907..7106a2d80f79 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -4881,6 +4881,13 @@ intel_dp_hotplug(struct intel_encoder *encoder,
> > drm_modeset_acquire_fini();
> > WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
> >
> > + /*
> > +* Keeping it consistent with intel_ddi_hotplug() and
> > +* intel_hdmi_hotplug().
> > +*/
> > + if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
> > + state = INTEL_HOTPLUG_RETRY;
> > +
> > return state;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > index 0ebec69bbbfc..26c8556f6980 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > @@ -3143,6 +3143,32 @@ void intel_hdmi_init_connector(struct
> > intel_digital_port *intel_dig_port,
> > DRM_DEBUG_KMS("CEC notifier get failed\n");
> > }
> >
> > +static enum intel_hotplug_state
> > +intel_hdmi_hotplug(struct intel_encoder *encoder,
> > + struct intel_connector *connector, bool irq_received)
> > +{
> > + enum intel_hotplug_state state;
> > +
> > + state = intel_encoder_hotplug(encoder, connector, irq_received);
> > +
> > + /*
> > +* On many platforms the HDMI live state signal is known to be
> > +* unreliable, so we can't use it to detect if a sink is connected or
> > +* not. Instead we detect if it's
Re: [Intel-gfx] [PATCH v3 15/21] drm/i915/tgl: apply Display WA #1178 to fix type C dongles
On Thu, Jul 11, 2019 at 10:31:09AM -0700, Lucas De Marchi wrote:
> Add port C to workaround to cover Tiger Lake.
>
> Cc: Rodrigo Vivi
> Signed-off-by: Lucas De Marchi
> Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 7 +++
> drivers/gpu/drm/i915/i915_reg.h| 4 +++-
> 2 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 12aa9ce08d95..061432862c7d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -453,6 +453,7 @@ icl_combo_phy_aux_power_well_enable(struct
> drm_i915_private *dev_priv,
> int pw_idx = power_well->desc->hsw.idx;
> enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
> u32 val;
> + int wa_idx_max;
>
> val = I915_READ(regs->driver);
> I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
> @@ -462,6 +463,12 @@ icl_combo_phy_aux_power_well_enable(struct
> drm_i915_private *dev_priv,
>
> hsw_wait_for_power_well_enable(dev_priv, power_well);
>
> + /* Display WA #1178: icl, tgl */
> + if (IS_TIGERLAKE(dev_priv))
> + wa_idx_max = ICL_PW_CTL_IDX_AUX_C;
> + else
> + wa_idx_max = ICL_PW_CTL_IDX_AUX_B;
> +
> /* Display WA #1178: icl */
> if (IS_ICELAKE(dev_priv) &&
I think this needs to change to !ehl now.
> pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
And this should use your new wa_idx_max variable
Matt
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ca70be40a467..ad96c5b4975c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9244,9 +9244,11 @@ enum skl_power_gate {
> #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
> #define _ICL_AUX_ANAOVRD1_A 0x162398
> #define _ICL_AUX_ANAOVRD1_B 0x6C398
> +#define _TGL_AUX_ANAOVRD1_C 0x160398
> #define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
> _ICL_AUX_ANAOVRD1_A, \
> - _ICL_AUX_ANAOVRD1_B))
> + _ICL_AUX_ANAOVRD1_B, \
> + _TGL_AUX_ANAOVRD1_C))
> #define ICL_AUX_ANAOVRD1_LDO_BYPASS(1 << 7)
> #define ICL_AUX_ANAOVRD1_ENABLE(1 << 0)
>
> --
> 2.21.0
>
--
Matt Roper
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IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Drop the duplicate workaround
== Series Details == Series: drm/i915/gt: Drop the duplicate workaround URL : https://patchwork.freedesktop.org/series/63520/ State : success == Summary == CI Bug Log - changes from CI_DRM_6453_full -> Patchwork_13611_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13611_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@unwedge-stress: - shard-snb: [PASS][1] -> [FAIL][2] ([fdo#109661]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-snb2/igt@gem_...@unwedge-stress.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13611/shard-snb4/igt@gem_...@unwedge-stress.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb4/igt@gem_exec_balan...@smoke.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13611/shard-iclb6/igt@gem_exec_balan...@smoke.html * igt@i915_pm_rpm@legacy-planes: - shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713] / [fdo#108840] / [fdo#109960]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb1/igt@i915_pm_...@legacy-planes.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13611/shard-iclb4/igt@i915_pm_...@legacy-planes.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-apl2/igt@i915_susp...@sysfs-reader.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13611/shard-apl7/igt@i915_susp...@sysfs-reader.html * igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-c: - shard-iclb: [PASS][9] -> [INCOMPLETE][10] ([fdo#107713]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb3/igt@kms_b...@extended-modeset-hang-oldfb-with-reset-render-c.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13611/shard-iclb7/igt@kms_b...@extended-modeset-hang-oldfb-with-reset-render-c.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#105363]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl4/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13611/shard-skl3/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13611/shard-iclb7/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([fdo#104108]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl8/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13611/shard-skl6/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [fdo#110403]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl9/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13611/shard-skl7/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103166]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb6/igt@kms_plane_low...@pipe-a-tiling-x.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13611/shard-iclb1/igt@kms_plane_low...@pipe-a-tiling-x.html * igt@kms_psr@psr2_sprite_render: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb2/igt@kms_psr@psr2_sprite_render.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13611/shard-iclb6/igt@kms_psr@psr2_sprite_render.html * igt@kms_setmode@basic: - shard-apl: [PASS][23] -> [FAIL][24] ([fdo#99912]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-apl5/igt@kms_setm...@basic.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13611/shard-apl3/igt@kms_setm...@basic.html * igt@kms_vblank@pipe-a-wait-forked-hang: - shard-apl: [PASS][25] -> [INCOMPLETE][26]
Re: [Intel-gfx] [PATCH 14/14] drm/i915/gt: Use intel_gt as the primary object for handling resets
On 7/11/19 1:45 PM, Daniele Ceraolo Spurio wrote:
--- a/drivers/gpu/drm/i915/selftests/i915_selftest.c
+++ b/drivers/gpu/drm/i915/selftests/i915_selftest.c
@@ -256,7 +256,7 @@ int __i915_live_setup(void *data)
{
struct drm_i915_private *i915 = data;
- return i915_terminally_wedged(i915);
+ return intel_gt_terminally_wedged(>gt);
}
int __i915_live_teardown(int err, void *data)
@@ -273,6 +273,27 @@ int __i915_live_teardown(int err, void *data)
return err;
}
+int __intel_gt_live_setup(void *data)
+{
+ struct intel_gt *gt = data;
+
+ return intel_gt_terminally_wedged(gt);
+}
+
+int __intel_gt_live_teardown(int err, void *data)
+{
+ struct intel_gt *gt = data;
+
+ mutex_lock(>i915->drm.struct_mutex);
+ if (igt_flush_test(gt->i915, I915_WAIT_LOCKED))
+ err = -EIO;
+ mutex_unlock(>i915->drm.struct_mutex);
+
+ i915_gem_drain_freed_objects(gt->i915);
+
+ return err;
+}
this is basically a copy of __i915_live_teardown, it might be worth
having one of the 2 functions call into the other if you're not planning
to have them diverge in the short term.
s/intel_gpu_reset/intel_gt_reset/ also didn't materialize but I'm happy
for that to come later.
Reviewed-by: Daniele Ceraolo Spurio
I've replied to the wrong version of this patch, the one I've actually
reviewed is the one in the 18 patches series. They look pretty much the
same anyway, but I'm clarifying anyway in case there is a difference I
missed.
Daniele
P.S.: if you have to respin for other reasons, it'd be nice if you could
use a local i915 variable where there are a lot of s/i915/gt->i915/ to
keep the diff smaller :P
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Re: [Intel-gfx] [PATCH v3 13/21] drm/i915/tgl: Add additional PHYs for Tiger Lake
On Thu, Jul 11, 2019 at 10:31:07AM -0700, Lucas De Marchi wrote:
> Tiger Lake has up to 3 combo phys and 6 TC phys. Extend the helper
> conversion functions from port to phy.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5 -
> drivers/gpu/drm/i915/display/intel_display.h | 3 +++
> 2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 1d6dc73dfc81..ba48fedd685b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6676,7 +6676,7 @@ bool intel_phy_is_combo(struct drm_i915_private
> *dev_priv, enum phy phy)
> if (phy == PHY_NONE)
> return false;
>
> - if (IS_ELKHARTLAKE(dev_priv))
> + if (IS_ELKHARTLAKE(dev_priv) || INTEL_GEN(dev_priv) >= 12)
> return phy <= PHY_C;
>
> if (INTEL_GEN(dev_priv) >= 11)
> @@ -6687,6 +6687,9 @@ bool intel_phy_is_combo(struct drm_i915_private
> *dev_priv, enum phy phy)
>
> bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
> {
> + if (INTEL_GEN(dev_priv) >= 12)
> + return phy >= PHY_D && phy <= PHY_I;
> +
> if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> return phy >= PHY_C && phy <= PHY_F;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 72ce27079a56..92931dc26470 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -249,6 +249,9 @@ enum phy {
> PHY_D,
> PHY_E,
> PHY_F,
> + PHY_G,
> + PHY_H,
> + PHY_I,
>
> I915_MAX_PHYS
> };
> --
> 2.21.0
>
--
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Re: [Intel-gfx] [PATCH v3 12/21] drm/i915/tgl: Add additional ports for Tiger Lake
On Thu, Jul 11, 2019 at 10:31:06AM -0700, Lucas De Marchi wrote:
> From: Vandita Kulkarni
>
> There are 2 new additional typeC ports in Tiger Lake and PORT-C is now a
> combophy port. This results in 6 typeC ports and 3 combophy ports.
> These 6 TC ports can be DP alternate mode, DP over thunderbolt, native
> DP on legacy DP connector or native HDMI on legacy connector.
>
> v2: Rebase on new modular FIA code (Lucas)
> v3: Also add new port in port_identifier(), even though it can't
> possibly be used there (requested by José)
> v4: Add conversion port->tc_port in helper function after introction of
> phy namespace (Lucas)
>
> Cc: Anusha Srivatsa
> Signed-off-by: Vandita Kulkarni
> Signed-off-by: Lucas De Marchi
Looks correct to me.
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 12
> drivers/gpu/drm/i915/display/intel_display.c | 3 +++
> drivers/gpu/drm/i915/display/intel_display.h | 8
> include/drm/i915_component.h | 2 +-
> include/drm/i915_drm.h | 3 +++
> 5 files changed, 27 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 1662e5c2be1c..8445244aa593 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4286,6 +4286,18 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
> intel_dig_port->ddi_io_power_domain =
> POWER_DOMAIN_PORT_DDI_F_IO;
> break;
> + case PORT_G:
> + intel_dig_port->ddi_io_power_domain =
> + POWER_DOMAIN_PORT_DDI_G_IO;
> + break;
> + case PORT_H:
> + intel_dig_port->ddi_io_power_domain =
> + POWER_DOMAIN_PORT_DDI_H_IO;
> + break;
> + case PORT_I:
> + intel_dig_port->ddi_io_power_domain =
> + POWER_DOMAIN_PORT_DDI_I_IO;
> + break;
> default:
> MISSING_CASE(port);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index d6ba15c59746..1d6dc73dfc81 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6706,6 +6706,9 @@ enum tc_port intel_port_to_tc(struct drm_i915_private
> *dev_priv, enum port port)
> if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
> return PORT_TC_NONE;
>
> + if (INTEL_GEN(dev_priv) >= 12)
> + return port - PORT_D;
> +
> return port - PORT_C;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 1f75b0a627fd..72ce27079a56 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -177,6 +177,12 @@ static inline const char *port_identifier(enum port port)
> return "Port E";
> case PORT_F:
> return "Port F";
> + case PORT_G:
> + return "Port G";
> + case PORT_H:
> + return "Port H";
> + case PORT_I:
> + return "Port I";
> default:
> return "";
> }
> @@ -189,6 +195,8 @@ enum tc_port {
> PORT_TC2,
> PORT_TC3,
> PORT_TC4,
> + PORT_TC5,
> + PORT_TC6,
>
> I915_MAX_TC_PORTS
> };
> diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
> index dcb95bd9dee6..55c3b123581b 100644
> --- a/include/drm/i915_component.h
> +++ b/include/drm/i915_component.h
> @@ -34,7 +34,7 @@ enum i915_component_type {
> /* MAX_PORT is the number of port
> * It must be sync with I915_MAX_PORTS defined i915_drv.h
> */
> -#define MAX_PORTS 6
> +#define MAX_PORTS 9
>
> /**
> * struct i915_audio_component - Used for direct communication between i915
> and hda drivers
> diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
> index 7523e9a7b6e2..eb30062359d1 100644
> --- a/include/drm/i915_drm.h
> +++ b/include/drm/i915_drm.h
> @@ -109,6 +109,9 @@ enum port {
> PORT_D,
> PORT_E,
> PORT_F,
> + PORT_G,
> + PORT_H,
> + PORT_I,
>
> I915_MAX_PORTS
> };
> --
> 2.21.0
>
--
Matt Roper
Graphics Software Engineer
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Intel Corporation
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Re: [Intel-gfx] [PATCH 14/14] drm/i915/gt: Use intel_gt as the primary object for handling resets
--- a/drivers/gpu/drm/i915/selftests/i915_selftest.c
+++ b/drivers/gpu/drm/i915/selftests/i915_selftest.c
@@ -256,7 +256,7 @@ int __i915_live_setup(void *data)
{
struct drm_i915_private *i915 = data;
- return i915_terminally_wedged(i915);
+ return intel_gt_terminally_wedged(>gt);
}
int __i915_live_teardown(int err, void *data)
@@ -273,6 +273,27 @@ int __i915_live_teardown(int err, void *data)
return err;
}
+int __intel_gt_live_setup(void *data)
+{
+ struct intel_gt *gt = data;
+
+ return intel_gt_terminally_wedged(gt);
+}
+
+int __intel_gt_live_teardown(int err, void *data)
+{
+ struct intel_gt *gt = data;
+
+ mutex_lock(>i915->drm.struct_mutex);
+ if (igt_flush_test(gt->i915, I915_WAIT_LOCKED))
+ err = -EIO;
+ mutex_unlock(>i915->drm.struct_mutex);
+
+ i915_gem_drain_freed_objects(gt->i915);
+
+ return err;
+}
this is basically a copy of __i915_live_teardown, it might be worth
having one of the 2 functions call into the other if you're not planning
to have them diverge in the short term.
s/intel_gpu_reset/intel_gt_reset/ also didn't materialize but I'm happy
for that to come later.
Reviewed-by: Daniele Ceraolo Spurio
P.S.: if you have to respin for other reasons, it'd be nice if you could
use a local i915 variable where there are a lot of s/i915/gt->i915/ to
keep the diff smaller :P
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[Intel-gfx] ✓ Fi.CI.IGT: success for Initial support for Tiger Lake (rev6)
== Series Details == Series: Initial support for Tiger Lake (rev6) URL : https://patchwork.freedesktop.org/series/62726/ State : success == Summary == CI Bug Log - changes from CI_DRM_6453_full -> Patchwork_13610_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13610_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_softpin@noreloc-s3: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([fdo#103313]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-kbl4/igt@gem_soft...@noreloc-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-kbl1/igt@gem_soft...@noreloc-s3.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-skl: [PASS][3] -> [FAIL][4] ([fdo#102670]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl10/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-skl7/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][5] -> [FAIL][6] ([fdo#105363]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-glk1/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-glk1/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][7] -> [FAIL][8] ([fdo#105363]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl4/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-skl8/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-kbl2/igt@kms_f...@flip-vs-suspend-interruptible.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-kbl3/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb5/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-iclb7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [fdo#110403]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl8/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-skl5/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103166]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb6/igt@kms_plane_low...@pipe-a-tiling-y.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-iclb7/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_psr@psr2_sprite_render: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb2/igt@kms_psr@psr2_sprite_render.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-iclb8/igt@kms_psr@psr2_sprite_render.html * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend: - shard-skl: [PASS][19] -> [INCOMPLETE][20] ([fdo#104108]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl2/igt@kms_vbl...@pipe-a-ts-continuation-dpms-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-skl2/igt@kms_vbl...@pipe-a-ts-continuation-dpms-suspend.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([fdo#108566]) +6 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-apl7/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-apl2/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html Possible fixes * igt@gem_softpin@noreloc-s3: - shard-skl: [INCOMPLETE][23] ([fdo#104108] / [fdo#107773]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl9/igt@gem_soft...@noreloc-s3.html [24]:
Re: [Intel-gfx] screen freeze with 5.2-rc6 Dell XPS-13 skylake i915
On Thu, 2019-07-11 at 20:25 +, Souza, Jose wrote: > On Thu, 2019-07-11 at 13:11 -0700, James Bottomley wrote: > > On Thu, 2019-07-11 at 10:29 +0100, Chris Wilson wrote: > > > Quoting James Bottomley (2019-06-29 19:56:52) > > > > The symptoms are really weird: the screen image is locked in > > > > place. The machine is still functional and if I log in over > > > > the network can do anything I like, including killing the X > > > > server and the display will never alter. It also seems that > > > > the system is accepting keyboard input because when it freezes > > > > I can cat information to a file (if the mouse was over an > > > > xterm) and verify over the network the file contents. Nothing > > > > unusual appears in dmesg when the lockup happens. > > > > > > > > The last kernel I booted successfully on the system was 5.0, so > > > > I'll try compiling 5.1 to narrow down the changes. > > > > > > It's likely this is panel self-refresh going haywire. > > > > > > commit 8f6e87d6d561f10cfa48a687345512419839b6d8 > > > Author: José Roberto de Souza > > > Date: Thu Mar 7 16:00:50 2019 -0800 > > > > > > drm/i915: Enable PSR2 by default > > > > > > The support for PSR2 was polished, IGT tests for PSR2 was > > > added and > > > it was tested performing regular user workloads like > > > browsing, > > > editing documents and compiling Linux, so it is time to > > > enable it by > > > default and enjoy even more power-savings. > > > > > > Temporary workaround would be to set i915.enable_psr=0 > > > > It looks plausible. I have to say I was just about to mark a > > bisect containing this as good, but that probably reflects my > > difficulty > > reproducing the issue. > > Take at look of what PSR version is supported by your panel, it > likely that a notebook shipped with Skylake will have panel that > supports only PSR1 so that patch has no effect on your machine. > > sudo more /sys/kernel/debug/dri/0/i915_edp_psr_status > Sink support: yes [0x01] It says Sink support: yes [0x01] PSR mode: PSR1 enabled Source PSR ctl: enabled [0x81f00726] Source PSR status: IDLE [0x04010212] Busy frontbuffer bits: 0x I've also updated to the released 5.2 kernel and am running with the debug parameters you requested ... but so far no reproduction. James
Re: [Intel-gfx] screen freeze with 5.2-rc6 Dell XPS-13 skylake i915
On Thu, 2019-07-11 at 13:11 -0700, James Bottomley wrote: > On Thu, 2019-07-11 at 10:29 +0100, Chris Wilson wrote: > > Quoting James Bottomley (2019-06-29 19:56:52) > > > The symptoms are really weird: the screen image is locked in > > > place. The machine is still functional and if I log in over the > > > network can do anything I like, including killing the X server > > > and > > > the display will never alter. It also seems that the system is > > > accepting keyboard input because when it freezes I can cat > > > information to a file (if the mouse was over an xterm) and verify > > > over the network the file contents. Nothing unusual appears in > > > dmesg when the lockup happens. > > > > > > The last kernel I booted successfully on the system was 5.0, so > > > I'll try compiling 5.1 to narrow down the changes. > > > > It's likely this is panel self-refresh going haywire. > > > > commit 8f6e87d6d561f10cfa48a687345512419839b6d8 > > Author: José Roberto de Souza > > Date: Thu Mar 7 16:00:50 2019 -0800 > > > > drm/i915: Enable PSR2 by default > > > > The support for PSR2 was polished, IGT tests for PSR2 was added > > and > > it was tested performing regular user workloads like browsing, > > editing documents and compiling Linux, so it is time to enable > > it > > by > > default and enjoy even more power-savings. > > > > Temporary workaround would be to set i915.enable_psr=0 > > It looks plausible. I have to say I was just about to mark a bisect > containing this as good, but that probably reflects my difficulty > reproducing the issue. Take at look of what PSR version is supported by your panel, it likely that a notebook shipped with Skylake will have panel that supports only PSR1 so that patch has no effect on your machine. sudo more /sys/kernel/debug/dri/0/i915_edp_psr_status Sink support: yes [0x01] Only if you have 0x03 your panel have support for PSR2. Or check your dmesg: [drm:intel_psr_init_dpcd [i915]] eDP panel supports PSR version 1 > > James > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Initial support for Tiger Lake (rev7)
== Series Details ==
Series: Initial support for Tiger Lake (rev7)
URL : https://patchwork.freedesktop.org/series/62726/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6462 -> Patchwork_13628
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13628/
Known issues
Here are the changes found in Patchwork_13628 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_reloc@basic-write-read-noreloc:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6462/fi-icl-u3/igt@gem_exec_re...@basic-write-read-noreloc.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13628/fi-icl-u3/igt@gem_exec_re...@basic-write-read-noreloc.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6462/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13628/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [PASS][5] -> [INCOMPLETE][6] ([fdo#111050])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6462/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13628/fi-skl-iommu/igt@i915_selftest@live_contexts.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: [PASS][7] -> [FAIL][8] ([fdo#103167])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6462/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13628/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
- fi-hsw-peppy: [PASS][9] -> [DMESG-WARN][10] ([fdo#102614])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6462/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13628/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@i915_hangman@error-state-basic:
- fi-icl-dsi: [INCOMPLETE][11] ([fdo#107713]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6462/fi-icl-dsi/igt@i915_hang...@error-state-basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13628/fi-icl-dsi/igt@i915_hang...@error-state-basic.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [FAIL][13] ([fdo#103167]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6462/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13628/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
Participating hosts (53 -> 46)
--
Missing(7): fi-kbl-soraka fi-byt-squawks fi-bsw-cyan fi-snb-2520m
fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6462 -> Patchwork_13628
CI_DRM_6462: 26ad28da569f17b9bfbda04a15f09791c8b36dda @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5094: d7f140b5b02d054183a74842b4579cf7f5533927 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13628: 542373bf46c5513d60060ecb7f9eb99d93e14c42 @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13628/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
542373bf46c5 drm/i915/tgl: Update DPLL clock reference register
3f6b9b8e3306
Re: [Intel-gfx] screen freeze with 5.2-rc6 Dell XPS-13 skylake i915
On Thu, 2019-07-11 at 10:29 +0100, Chris Wilson wrote: > Quoting James Bottomley (2019-06-29 19:56:52) > > The symptoms are really weird: the screen image is locked in > > place. The machine is still functional and if I log in over the > > network can do anything I like, including killing the X server and > > the display will never alter. It also seems that the system is > > accepting keyboard input because when it freezes I can cat > > information to a file (if the mouse was over an xterm) and verify > > over the network the file contents. Nothing unusual appears in > > dmesg when the lockup happens. > > > > The last kernel I booted successfully on the system was 5.0, so > > I'll try compiling 5.1 to narrow down the changes. > > It's likely this is panel self-refresh going haywire. > > commit 8f6e87d6d561f10cfa48a687345512419839b6d8 > Author: José Roberto de Souza > Date: Thu Mar 7 16:00:50 2019 -0800 > > drm/i915: Enable PSR2 by default > > The support for PSR2 was polished, IGT tests for PSR2 was added > and > it was tested performing regular user workloads like browsing, > editing documents and compiling Linux, so it is time to enable it > by > default and enjoy even more power-savings. > > Temporary workaround would be to set i915.enable_psr=0 It looks plausible. I have to say I was just about to mark a bisect containing this as good, but that probably reflects my difficulty reproducing the issue. James ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 1/2] drm/i915: Add support for retrying hotplug
On Wed, Jul 10, 2019 at 03:14:59PM -0700, José Roberto de Souza wrote:
> From: Imre Deak
>
> There is some scenarios that we are aware that sink probe can fail,
> so lets add the infrastructure to let hotplug() hook to request
> another probe after some time.
>
> v2: Handle shared HPD pins (Imre)
> v3: Rebased
> v4: Renamed INTEL_HOTPLUG_NOCHANGE to INTEL_HOTPLUG_UNCHANGED to keep
> it consistent(Rodrigo)
>
> Cc: Ville Syrjälä
> Reviewed-by: Rodrigo Vivi
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Jani Nikula
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++--
> drivers/gpu/drm/i915/display/intel_dp.c | 12 ++--
> drivers/gpu/drm/i915/display/intel_hotplug.c | 59 +++-
> drivers/gpu/drm/i915/display/intel_hotplug.h | 5 +-
> drivers/gpu/drm/i915/display/intel_sdvo.c| 8 ++-
> drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 3 +-
> drivers/gpu/drm/i915/intel_drv.h | 11 +++-
> 8 files changed, 80 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index ad638e7f27bb..734c004800f8 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4047,14 +4047,16 @@ static int intel_hdmi_reset_link(struct intel_encoder
> *encoder,
> return modeset_pipe(>base, ctx);
> }
>
> -static bool intel_ddi_hotplug(struct intel_encoder *encoder,
> - struct intel_connector *connector)
> +static enum intel_hotplug_state
> +intel_ddi_hotplug(struct intel_encoder *encoder,
> + struct intel_connector *connector,
> + bool irq_received)
> {
> struct drm_modeset_acquire_ctx ctx;
> - bool changed;
> + enum intel_hotplug_state state;
> int ret;
>
> - changed = intel_encoder_hotplug(encoder, connector);
> + state = intel_encoder_hotplug(encoder, connector, irq_received);
>
> drm_modeset_acquire_init(, 0);
>
> @@ -4076,7 +4078,7 @@ static bool intel_ddi_hotplug(struct intel_encoder
> *encoder,
> drm_modeset_acquire_fini();
> WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
>
> - return changed;
> + return state;
> }
>
> static struct intel_connector *
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0bdb7ecc5a81..4423abbc7907 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4853,14 +4853,16 @@ int intel_dp_retrain_link(struct intel_encoder
> *encoder,
> * retrain the link to get a picture. That's in case no
> * userspace component reacted to intermittent HPD dip.
> */
> -static bool intel_dp_hotplug(struct intel_encoder *encoder,
> - struct intel_connector *connector)
> +static enum intel_hotplug_state
> +intel_dp_hotplug(struct intel_encoder *encoder,
> + struct intel_connector *connector,
> + bool irq_received)
> {
> struct drm_modeset_acquire_ctx ctx;
> - bool changed;
> + enum intel_hotplug_state state;
> int ret;
>
> - changed = intel_encoder_hotplug(encoder, connector);
> + state = intel_encoder_hotplug(encoder, connector, irq_received);
>
> drm_modeset_acquire_init(, 0);
>
> @@ -4879,7 +4881,7 @@ static bool intel_dp_hotplug(struct intel_encoder
> *encoder,
> drm_modeset_acquire_fini();
> WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
>
> - return changed;
> + return state;
> }
>
> static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
> b/drivers/gpu/drm/i915/display/intel_hotplug.c
> index ea3de4acc850..2ca92780c659 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> @@ -112,6 +112,7 @@ enum hpd_pin intel_hpd_pin_default(struct
> drm_i915_private *dev_priv,
>
> #define HPD_STORM_DETECT_PERIOD 1000
> #define HPD_STORM_REENABLE_DELAY (2 * 60 * 1000)
> +#define HPD_RETRY_DELAY 1000
>
> /**
> * intel_hpd_irq_storm_detect - gather stats and detect HPD IRQ storm on a
> pin
> @@ -266,8 +267,10 @@ static void intel_hpd_irq_storm_reenable_work(struct
> work_struct *work)
> intel_runtime_pm_put(_priv->runtime_pm, wakeref);
> }
>
> -bool intel_encoder_hotplug(struct intel_encoder *encoder,
> -struct intel_connector *connector)
> +enum intel_hotplug_state
> +intel_encoder_hotplug(struct intel_encoder *encoder,
> + struct intel_connector *connector,
> + bool irq_received)
> {
> struct drm_device *dev = connector->base.dev;
> enum drm_connector_status old_status;
> @@ -279,7 +282,7 @@ bool
Re: [Intel-gfx] [PATCH] drm/i915: Don't overestimate 4:2:0 link symbol clock
On Thu, Jul 11, 2019 at 04:49:06PM +, Mun, Gwan-gyeong wrote:
> On Wed, 2019-07-10 at 15:58 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > With 4:2:0 output the LS clock can be half of what it is with 4:4:4.
> > Make that happen.
> >
> > Cc: Gwan-gyeong Mun
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 0bdb7ecc5a81..1dfacf090fb8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1853,8 +1853,10 @@ intel_dp_compute_link_config_wide(struct
> > intel_dp *intel_dp,
> > int mode_rate, link_clock, link_avail;
> >
> > for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 *
> > 3) {
> > + int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
> > +
> > mode_rate = intel_dp_link_required(adjusted_mode-
> > >crtc_clock,
> > - bpp);
> > + output_bpp);
> >
> > for (clock = limits->min_clock; clock <= limits-
> > >max_clock; clock++) {
> > for (lane_count = limits->min_lane_count;
> According to DP 1.4 spec section 1.7.1 [Makeup of the Main-Link],
> previous implementation worked by below explaination.
> After the stream data is packed and mapped to the Main-Link, the packed
> stream data rate shall be less than or equal to the Main-Link’s link
> symbol rate. When the packed stream data rate is less than the Main-
> Link’s link symbol rate, stuffing symbols are inserted.
>
> Reviewed-by: Gwan-gyeong Mun
> Tested-by: Gwan-gyeong Mun
Nice. Thanks for double checking. Pushed to dinq.
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v2] drm/i915: Copy name string into ring buffer for intel_update/disable_plane tracepoints
On Wed, Jul 10, 2019 at 08:12:30PM +0300, Ville Syrjala wrote:
> From: "Steven Rostedt (VMware)"
>
> Currently the intel_update_plane and intel_disable_plane tracepoints record
> the address of plane->name in the ring buffer, and then when reading the
> ring buffer uses %s to get the name. The issue with this, is that those two
> events can be minutes, hours or even days apart. It is very dangerous to
> dereference a string pointer without knowing if it still exists or not.
>
> The proper way to handle this is to use the __string() macro in the
> tracepoint which will save the string into the ring buffer at the time of
> recording. Then there's no worries if the original string still exists in
> memory when the ring buffer is read.
>
> Signed-off-by: Steven Rostedt (VMware)
> [vsyrjala: Rebase on top of drm-tip]
> Signed-off-by: Ville Syrjälä
CI is happy (not that we test this stuff) and I'm happy (the tracepoints
still work) -> pushed to drm-intel-next-queued. Thanks for the patch.
> ---
> drivers/gpu/drm/i915/i915_trace.h | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_trace.h
> b/drivers/gpu/drm/i915/i915_trace.h
> index cce426b23a24..da18b8d6b80c 100644
> --- a/drivers/gpu/drm/i915/i915_trace.h
> +++ b/drivers/gpu/drm/i915/i915_trace.h
> @@ -293,16 +293,16 @@ TRACE_EVENT(intel_update_plane,
>
> TP_STRUCT__entry(
>__field(enum pipe, pipe)
> - __field(const char *, name)
>__field(u32, frame)
>__field(u32, scanline)
>__array(int, src, 4)
>__array(int, dst, 4)
> + __string(name, plane->name)
>),
>
> TP_fast_assign(
> +__assign_str(name, plane->name);
> __entry->pipe = crtc->pipe;
> -__entry->name = plane->name;
> __entry->frame = intel_crtc_get_vblank_counter(crtc);
> __entry->scanline = intel_get_crtc_scanline(crtc);
> memcpy(__entry->src, >state->src,
> sizeof(__entry->src));
> @@ -310,7 +310,7 @@ TRACE_EVENT(intel_update_plane,
> ),
>
> TP_printk("pipe %c, plane %s, frame=%u, scanline=%u, "
> DRM_RECT_FP_FMT " -> " DRM_RECT_FMT,
> - pipe_name(__entry->pipe), __entry->name,
> + pipe_name(__entry->pipe), __get_str(name),
> __entry->frame, __entry->scanline,
> DRM_RECT_FP_ARG((const struct drm_rect *)__entry->src),
> DRM_RECT_ARG((const struct drm_rect *)__entry->dst))
> @@ -322,20 +322,20 @@ TRACE_EVENT(intel_disable_plane,
>
> TP_STRUCT__entry(
>__field(enum pipe, pipe)
> - __field(const char *, name)
>__field(u32, frame)
>__field(u32, scanline)
> + __string(name, plane->name)
>),
>
> TP_fast_assign(
> +__assign_str(name, plane->name);
> __entry->pipe = crtc->pipe;
> -__entry->name = plane->name;
> __entry->frame = intel_crtc_get_vblank_counter(crtc);
> __entry->scanline = intel_get_crtc_scanline(crtc);
> ),
>
> TP_printk("pipe %c, plane %s, frame=%u, scanline=%u",
> - pipe_name(__entry->pipe), __entry->name,
> + pipe_name(__entry->pipe), __get_str(name),
> __entry->frame, __entry->scanline)
> );
>
> --
> 2.21.0
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v4 2/2] drm/i915: Enable hotplug retry
On Wed, Jul 10, 2019 at 03:15:00PM -0700, José Roberto de Souza wrote:
> Right now we are aware of two cases that needs another hotplug retry:
> - Unpowered type-c dongles
> - HDMI slow unplug
>
> Both have a complete explanation in the code to schedule another run
> of the hotplug handler.
>
> It could have more checks to just trigger the retry in those two
> specific cases but why would sink signal a long pulse if there is
> no change? Also the drawback of running the hotplug handler again
> is really low and that could fix another cases that we are not
> aware.
>
> Also retrying for old DP ports(non-DDI) to make it consistent and not
> cause CI failures if those systems are connected to chamelium boards
> that will be used to simulate the issues reported in here.
>
> v2: Also retrying for old DP ports(non-DDI)(Imre)
>
> v4: Renamed INTEL_HOTPLUG_NOCHANGE to INTEL_HOTPLUG_UNCHANGED to keep
> it consistent(Rodrigo)
>
> Cc: Ville Syrjälä
> Cc: Imre Deak
> Cc: Jani Nikula
> Reviewed-by: Imre Deak
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 21 +
> drivers/gpu/drm/i915/display/intel_dp.c | 7 ++
> drivers/gpu/drm/i915/display/intel_hdmi.c | 28 ++-
> 3 files changed, 55 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 734c004800f8..ea6d1873f6cb 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4052,6 +4052,7 @@ intel_ddi_hotplug(struct intel_encoder *encoder,
> struct intel_connector *connector,
> bool irq_received)
> {
> + struct intel_digital_port *dig_port = enc_to_dig_port(>base);
> struct drm_modeset_acquire_ctx ctx;
> enum intel_hotplug_state state;
> int ret;
> @@ -4078,6 +4079,26 @@ intel_ddi_hotplug(struct intel_encoder *encoder,
> drm_modeset_acquire_fini();
> WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
>
> + /*
> + * Unpowered type-c dongles can take some time to boot and be
> + * responsible, so here giving some time to those dongles to power up
> + * and then retrying the probe.
> + *
> + * On many platforms the HDMI live state signal is known to be
> + * unreliable, so we can't use it to detect if a sink is connected or
> + * not. Instead we detect if it's connected based on whether we can
> + * read the EDID or not. That in turn has a problem during disconnect,
> + * since the HPD interrupt may be raised before the DDC lines get
> + * disconnected (due to how the required length of DDC vs. HPD
> + * connector pins are specified) and so we'll still be able to get a
> + * valid EDID. To solve this schedule another detection cycle if this
> + * time around we didn't detect any change in the sink's connection
> + * status.
> + */
> + if (state == INTEL_HOTPLUG_UNCHANGED && irq_received &&
> + !dig_port->dp.is_mst)
> + state = INTEL_HOTPLUG_RETRY;
> +
> return state;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4423abbc7907..7106a2d80f79 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4881,6 +4881,13 @@ intel_dp_hotplug(struct intel_encoder *encoder,
> drm_modeset_acquire_fini();
> WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
>
> + /*
> + * Keeping it consistent with intel_ddi_hotplug() and
> + * intel_hdmi_hotplug().
> + */
> + if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
> + state = INTEL_HOTPLUG_RETRY;
> +
> return state;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 0ebec69bbbfc..26c8556f6980 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -3143,6 +3143,32 @@ void intel_hdmi_init_connector(struct
> intel_digital_port *intel_dig_port,
> DRM_DEBUG_KMS("CEC notifier get failed\n");
> }
>
> +static enum intel_hotplug_state
> +intel_hdmi_hotplug(struct intel_encoder *encoder,
> +struct intel_connector *connector, bool irq_received)
> +{
> + enum intel_hotplug_state state;
> +
> + state = intel_encoder_hotplug(encoder, connector, irq_received);
> +
> + /*
> + * On many platforms the HDMI live state signal is known to be
> + * unreliable, so we can't use it to detect if a sink is connected or
> + * not. Instead we detect if it's connected based on whether we can
> + * read the EDID or not. That in turn has a problem during disconnect,
> + * since the HPD interrupt may be raised before the DDC lines get
> + * disconnected (due to how the
Re: [Intel-gfx] [PATCH v4 1/2] drm/i915: Add support for retrying hotplug
On Wed, Jul 10, 2019 at 03:14:59PM -0700, José Roberto de Souza wrote:
> From: Imre Deak
>
> There is some scenarios that we are aware that sink probe can fail,
> so lets add the infrastructure to let hotplug() hook to request
> another probe after some time.
>
> v2: Handle shared HPD pins (Imre)
> v3: Rebased
> v4: Renamed INTEL_HOTPLUG_NOCHANGE to INTEL_HOTPLUG_UNCHANGED to keep
> it consistent(Rodrigo)
>
> Cc: Ville Syrjälä
> Reviewed-by: Rodrigo Vivi
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Jani Nikula
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++--
> drivers/gpu/drm/i915/display/intel_dp.c | 12 ++--
> drivers/gpu/drm/i915/display/intel_hotplug.c | 59 +++-
> drivers/gpu/drm/i915/display/intel_hotplug.h | 5 +-
> drivers/gpu/drm/i915/display/intel_sdvo.c| 8 ++-
> drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 3 +-
> drivers/gpu/drm/i915/intel_drv.h | 11 +++-
> 8 files changed, 80 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index ad638e7f27bb..734c004800f8 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4047,14 +4047,16 @@ static int intel_hdmi_reset_link(struct intel_encoder
> *encoder,
> return modeset_pipe(>base, ctx);
> }
>
> -static bool intel_ddi_hotplug(struct intel_encoder *encoder,
> - struct intel_connector *connector)
> +static enum intel_hotplug_state
> +intel_ddi_hotplug(struct intel_encoder *encoder,
> + struct intel_connector *connector,
> + bool irq_received)
> {
> struct drm_modeset_acquire_ctx ctx;
> - bool changed;
> + enum intel_hotplug_state state;
> int ret;
>
> - changed = intel_encoder_hotplug(encoder, connector);
> + state = intel_encoder_hotplug(encoder, connector, irq_received);
>
> drm_modeset_acquire_init(, 0);
>
> @@ -4076,7 +4078,7 @@ static bool intel_ddi_hotplug(struct intel_encoder
> *encoder,
> drm_modeset_acquire_fini();
> WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
>
> - return changed;
> + return state;
> }
>
> static struct intel_connector *
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0bdb7ecc5a81..4423abbc7907 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4853,14 +4853,16 @@ int intel_dp_retrain_link(struct intel_encoder
> *encoder,
> * retrain the link to get a picture. That's in case no
> * userspace component reacted to intermittent HPD dip.
> */
> -static bool intel_dp_hotplug(struct intel_encoder *encoder,
> - struct intel_connector *connector)
> +static enum intel_hotplug_state
> +intel_dp_hotplug(struct intel_encoder *encoder,
> + struct intel_connector *connector,
> + bool irq_received)
> {
> struct drm_modeset_acquire_ctx ctx;
> - bool changed;
> + enum intel_hotplug_state state;
> int ret;
>
> - changed = intel_encoder_hotplug(encoder, connector);
> + state = intel_encoder_hotplug(encoder, connector, irq_received);
>
> drm_modeset_acquire_init(, 0);
>
> @@ -4879,7 +4881,7 @@ static bool intel_dp_hotplug(struct intel_encoder
> *encoder,
> drm_modeset_acquire_fini();
> WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
>
> - return changed;
> + return state;
> }
>
> static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
> b/drivers/gpu/drm/i915/display/intel_hotplug.c
> index ea3de4acc850..2ca92780c659 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> @@ -112,6 +112,7 @@ enum hpd_pin intel_hpd_pin_default(struct
> drm_i915_private *dev_priv,
>
> #define HPD_STORM_DETECT_PERIOD 1000
> #define HPD_STORM_REENABLE_DELAY (2 * 60 * 1000)
> +#define HPD_RETRY_DELAY 1000
>
> /**
> * intel_hpd_irq_storm_detect - gather stats and detect HPD IRQ storm on a
> pin
> @@ -266,8 +267,10 @@ static void intel_hpd_irq_storm_reenable_work(struct
> work_struct *work)
> intel_runtime_pm_put(_priv->runtime_pm, wakeref);
> }
>
> -bool intel_encoder_hotplug(struct intel_encoder *encoder,
> -struct intel_connector *connector)
> +enum intel_hotplug_state
> +intel_encoder_hotplug(struct intel_encoder *encoder,
> + struct intel_connector *connector,
> + bool irq_received)
> {
> struct drm_device *dev = connector->base.dev;
> enum drm_connector_status old_status;
> @@ -279,7 +282,7 @@ bool
Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Revert "drm/i915: Enable PSR2 by default"
On Thu, 2019-07-11 at 16:21 +0100, Chris Wilson wrote: > Quoting Patchwork (2019-07-11 16:16:45) > > Possible fixes > > > > * igt@kms_psr@cursor_plane_move: > > - fi-whl-u: [FAIL][7] ([fdo#107383]) -> [PASS][8] +3 > > similar issues > >[7]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6458/fi-whl-u/igt@kms_psr@cursor_plane_move.html > >[8]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13620/fi-whl-u/igt@kms_psr@cursor_plane_move.html > > To no great surprise as this regressed from the same patch to enable > psr2 by default. This is a flipping result as cursor_plane_move will always test PSR1, we have the same test for PSR2: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6452/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html > -Chris > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] screen freeze with 5.2-rc6 Dell XPS-13 skylake i915
Hi James and Paul Could you share a dmesg output of your system after the bug occur with this kernel parameters "drm.debug=0x1e log_buf_len=4M"? Also the output of /sys/kernel/debug/dri/0/i915_edp_psr_status Thanks On Wed, 2019-07-10 at 15:18 -0700, James Bottomley wrote: > On Wed, 2019-07-10 at 23:59 +0200, Paul Bolle wrote: > > James Bottomley schreef op wo 10-07-2019 om 10:35 [-0700]: > > > I can get back to it this afternoon, when I'm done with the > > > meeting > > > requirements and doing other dev stuff. > > > > I've started bisecting using your suggestion of that drm merge: > > $ git bisect log > > git bisect start > > # good: [89c3b37af87ec183b666d83428cb28cc421671a6] Merge > > git://git.kernel.org/pub/scm/linux/kernel/git/davem/ide > > git bisect good 89c3b37af87ec183b666d83428cb28cc421671a6 > > # bad: [a2d635decbfa9c1e4ae15cb05b68b2559f7f827c] Merge tag > > 'drm- > > next-2019-05-09' of git://anongit.freedesktop.org/drm/drm > > git bisect bad a2d635decbfa9c1e4ae15cb05b68b2559f7f827c > > # bad: [ad2c467aa92e283e9e8009bb9eb29a5c6a2d1217] drm/i915: > > Update DRIVER_DATE to 20190417 > > git bisect bad ad2c467aa92e283e9e8009bb9eb29a5c6a2d1217 > > > > Git told me I have nine steps after this. So at two hours per step > > I > > might > > pinpoint the offending commit by Friday the 12th. If I'm lucky. > > (There are > > other things to do than bisecting this issue.) > > > > If you find that commit before I do, I'll be all ears. > > Sure ... I'm doing the holistic thing and looking at the tree in that > branch. It seems to consist of 7 i915 updates > > c09d39166d8a3f3788680b32dbb0a40a70de32e2 DRIVER_DATE to 20190207 > 47ed55a9bb9e284d46d6f2489e32a53b59152809 DRIVER_DATE to 20190220 > f4ecb8ae70de86710e85138ce49af5c689951953 DRIVER_DATE to 20190311 > 1284ec985572232ace4817476baeb2d82b60be7a DRIVER_DATE to 20190320 > a01b2c6f47d86c7d1a9fa822b3b91ec233b61784 DRIVER_DATE to 20190328 > 28d618e9ab86f26a31af0b235ced55beb3e343c8 DRIVER_DATE to 20190404 > ad2c467aa92e283e9e8009bb9eb29a5c6a2d1217 DRIVER_DATE to 20190417 > > So I figured I'd see if I can locate the problem by bisection of > those > plus inspection. > > James > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Drop redundant ctx param from kerenldoc
== Series Details ==
Series: drm/i915/guc: Drop redundant ctx param from kerenldoc
URL : https://patchwork.freedesktop.org/series/63578/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6461 -> Patchwork_13627
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13627/
Known issues
Here are the changes found in Patchwork_13627 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13627/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
* igt@gem_tiled_fence_blits@basic:
- fi-icl-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/fi-icl-dsi/igt@gem_tiled_fence_bl...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13627/fi-icl-dsi/igt@gem_tiled_fence_bl...@basic.html
* igt@i915_pm_rpm@basic-rte:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/fi-icl-u3/igt@i915_pm_...@basic-rte.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13627/fi-icl-u3/igt@i915_pm_...@basic-rte.html
Possible fixes
* igt@i915_selftest@live_execlists:
- fi-bwr-2160:[DMESG-WARN][7] -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/fi-bwr-2160/igt@i915_selftest@live_execlists.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13627/fi-bwr-2160/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- fi-bwr-2160:[DMESG-FAIL][9] -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13627/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#109485]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13627/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
Participating hosts (52 -> 45)
--
Missing(7): fi-skl-guc fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6461 -> Patchwork_13627
CI_DRM_6461: c16e87caedb5fa63f7731443573348fe1e222c50 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5094: d7f140b5b02d054183a74842b4579cf7f5533927 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13627: 145f7b1bbe8ecd62c9aaad70d720d6a58be62cd9 @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13627/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
145f7b1bbe8e drm/i915/guc: Drop redundant ctx param from kerenldoc
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13627/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for MCR fixes (rev2)
== Series Details ==
Series: MCR fixes (rev2)
URL : https://patchwork.freedesktop.org/series/63457/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6461 -> Patchwork_13626
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/
Known issues
Here are the changes found in Patchwork_13626 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_close_race@basic-threads:
- fi-icl-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/fi-icl-u2/igt@gem_close_r...@basic-threads.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/fi-icl-u2/igt@gem_close_r...@basic-threads.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
Possible fixes
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [INCOMPLETE][5] ([fdo#111050]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/fi-skl-iommu/igt@i915_selftest@live_contexts.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][7] ([fdo#08]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
- fi-bwr-2160:[DMESG-WARN][9] -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/fi-bwr-2160/igt@i915_selftest@live_execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/fi-bwr-2160/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- fi-bwr-2160:[DMESG-FAIL][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#109485]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-dsi: [FAIL][15] ([fdo#103167]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/fi-icl-dsi/igt@kms_frontbuffer_track...@basic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/fi-icl-dsi/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
Participating hosts (52 -> 45)
--
Missing(7): fi-skl-guc fi-byt-squawks fi-bsw-cyan fi-icl-u3 fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6461 -> Patchwork_13626
CI_DRM_6461: c16e87caedb5fa63f7731443573348fe1e222c50 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5094: d7f140b5b02d054183a74842b4579cf7f5533927 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13626: 524a74bd73ba307f2a952efaaa0b44698b80b883 @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev7)
== Series Details == Series: Initial support for Tiger Lake (rev7) URL : https://patchwork.freedesktop.org/series/62726/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3b308280d186 drm/i915: Add 4th pipe and transcoder 22ff20d71578 drm/i915/tgl: add initial Tiger Lake definitions 2983d1e70483 drm/i915/tgl: Introduce Tiger Lake PCH 7149b1effb99 drm/i915/tgl: Add TGL PCH detection in virtualized environment 0df93c01c401 drm/i915/tgl: Add TGL PCI IDs -:34: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #34: FILE: include/drm/i915_pciids.h:587: +#define INTEL_TGL_12_IDS(info) \ + INTEL_VGA_DEVICE(0x9A49, info), \ + INTEL_VGA_DEVICE(0x9A40, info), \ + INTEL_VGA_DEVICE(0x9A59, info), \ + INTEL_VGA_DEVICE(0x9A60, info), \ + INTEL_VGA_DEVICE(0x9A68, info), \ + INTEL_VGA_DEVICE(0x9A70, info), \ + INTEL_VGA_DEVICE(0x9A78, info) -:34: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #34: FILE: include/drm/i915_pciids.h:587: +#define INTEL_TGL_12_IDS(info) \ + INTEL_VGA_DEVICE(0x9A49, info), \ + INTEL_VGA_DEVICE(0x9A40, info), \ + INTEL_VGA_DEVICE(0x9A59, info), \ + INTEL_VGA_DEVICE(0x9A60, info), \ + INTEL_VGA_DEVICE(0x9A68, info), \ + INTEL_VGA_DEVICE(0x9A70, info), \ + INTEL_VGA_DEVICE(0x9A78, info) total: 1 errors, 0 warnings, 1 checks, 21 lines checked 2f8ef50027bf drm/i915/tgl: Check if pipe D is fused 94eba30b3e6c drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on transcoder A bf8ff2c09217 drm/i915/tgl: Add power well support 2989b1102dc2 drm/i915/tgl: Add power well to support 4th pipe d7400914c2ff drm/i915/tgl: Add new pll ids 22c6e15f27f6 drm/i915/tgl: Add pll manager debae094a188 drm/i915/tgl: Add additional ports for Tiger Lake 0778c4f497cd drm/i915/tgl: Add additional PHYs for Tiger Lake 2eb2a6413434 drm/i915/tgl: init ddi port A-C for Tiger Lake 65cdba68fd27 drm/i915/tgl: apply Display WA #1178 to fix type C dongles 22c07d339ead drm/i915/gen12: MBUS B credit change be190cc98460 drm/i915/tgl: Add gmbus gpio pin to port mapping 3e56d7286d31 drm/i915/tgl: port to ddc pin mapping e0bdb26890c9 drm/i915/tgl: Add vbt value mapping for DDC Bus pin 3f6b9b8e3306 drm/i915/tgl: Add DPLL registers 542373bf46c5 drm/i915/tgl: Update DPLL clock reference register ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/display/icl: Bump up the vdisplay to reflect higher transcoder vertical limits
On Thu, Jul 11, 2019 at 01:38:41PM +0300, Ville Syrjälä wrote:
> On Wed, Jul 10, 2019 at 02:39:50PM -0700, Manasi Navare wrote:
> > On ICL+, the vertical limits for the transcoders are increased to 8192 so
> > bump up
> > limits in intel_mode_valid()
> >
> > v3:
> > * Supported starting ICL (Ville)
> > * Use the higher limits from TRANS_VTOTAL register (Ville)
> > v2:
> > * Checkpatch warning (Manasi)
> >
> > Cc: Maarten Lankhorst
> > Cc: Ville Syrjälä
> > Signed-off-by: Manasi Navare
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 9 +++--
> > 1 file changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index f07081815b80..9883f607bb88 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev,
> >DRM_MODE_FLAG_CLKDIV2))
> > return MODE_BAD;
> >
> > - if (INTEL_GEN(dev_priv) >= 9 ||
> > - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> > + if (INTEL_GEN(dev_priv) >= 11) {
> > + hdisplay_max = 8192;
> > + vdisplay_max = 8192;
>
> The horiz limits should be 16k.
Oh yes didnt look at the TRANS_HTOTAL so yes thats 14 bits so 16384, will make
that change
Manasi
>
> > + htotal_max = 8192;
> > + vtotal_max = 8192;
> > + } else if (INTEL_GEN(dev_priv) >= 9 ||
> > + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> > hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
> > vdisplay_max = 4096;
> > htotal_max = 8192;
> > --
> > 2.19.1
>
> --
> Ville Syrjälä
> Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Copy name string into ring buffer for intel_update/disable_plane tracepoints (rev2)
== Series Details == Series: drm/i915: Copy name string into ring buffer for intel_update/disable_plane tracepoints (rev2) URL : https://patchwork.freedesktop.org/series/63516/ State : success == Summary == CI Bug Log - changes from CI_DRM_6451_full -> Patchwork_13609_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13609_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-iclb3/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13609/shard-iclb1/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +5 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-apl3/igt@gem_workarou...@suspend-resume-context.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13609/shard-apl5/igt@gem_workarou...@suspend-resume-context.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-kbl6/igt@kms_cursor_...@pipe-a-cursor-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13609/shard-kbl3/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: [PASS][7] -> [FAIL][8] ([fdo#105767]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-hsw7/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13609/shard-hsw6/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html * igt@kms_cursor_legacy@all-pipes-torture-bo: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([fdo#107122]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-kbl7/igt@kms_cursor_leg...@all-pipes-torture-bo.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13609/shard-kbl2/igt@kms_cursor_leg...@all-pipes-torture-bo.html * igt@kms_flip@plain-flip-fb-recreate-interruptible: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#100368]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-skl6/igt@kms_f...@plain-flip-fb-recreate-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13609/shard-skl4/igt@kms_f...@plain-flip-fb-recreate-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +5 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-msflip-blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13609/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-msflip-blt.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103166]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-iclb3/igt@kms_plane_low...@pipe-a-tiling-x.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13609/shard-iclb4/igt@kms_plane_low...@pipe-a-tiling-x.html * igt@kms_psr2_su@page_flip: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109642] / [fdo#111068]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-iclb2/igt@kms_psr2_su@page_flip.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13609/shard-iclb4/igt@kms_psr2_su@page_flip.html * igt@kms_vblank@pipe-b-query-forked-busy-hang: - shard-hsw: [PASS][19] -> [INCOMPLETE][20] ([fdo#103540]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-hsw1/igt@kms_vbl...@pipe-b-query-forked-busy-hang.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13609/shard-hsw8/igt@kms_vbl...@pipe-b-query-forked-busy-hang.html Possible fixes * igt@gem_eio@reset-stress: - shard-snb: [FAIL][21] ([fdo#109661]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-snb1/igt@gem_...@reset-stress.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13609/shard-snb6/igt@gem_...@reset-stress.html * igt@i915_suspend@sysfs-reader: - shard-apl: [DMESG-WARN][23] ([fdo#108566]) -> [PASS][24] +5 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-apl7/igt@i915_susp...@sysfs-reader.html [24]:
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3] drm/i915/oa: Reconfigure contexts on the fly (rev4)
== Series Details ==
Series: series starting with [v3] drm/i915/oa: Reconfigure contexts on the fly
(rev4)
URL : https://patchwork.freedesktop.org/series/63362/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6460 -> Patchwork_13625
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13625/
Known issues
Here are the changes found in Patchwork_13625 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [PASS][1] -> [DMESG-FAIL][2] ([fdo#08])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6460/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13625/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] /
[fdo#108569])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6460/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13625/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
Possible fixes
* igt@gem_close_race@basic-threads:
- {fi-icl-u4}:[INCOMPLETE][5] ([fdo#107713]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6460/fi-icl-u4/igt@gem_close_r...@basic-threads.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13625/fi-icl-u4/igt@gem_close_r...@basic-threads.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
Participating hosts (50 -> 46)
--
Additional (2): fi-icl-u3 fi-apl-guc
Missing(6): fi-byt-squawks fi-bsw-cyan fi-skl-6260u fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6460 -> Patchwork_13625
CI_DRM_6460: 32d52650873db547f6702f12ebdbae3e8e052dad @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5094: d7f140b5b02d054183a74842b4579cf7f5533927 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13625: 09112e115f02cc9dab9ec22c932915912c83c3cb @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13625/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
09112e115f02 drm/i915: Add to timeline requires the timeline mutex
9495a1c4b913 drm/i915/oa: Reconfigure contexts on the fly
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13625/
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[Intel-gfx] [PATCH v3 16/21] drm/i915/gen12: MBUS B credit change
From: Rodrigo Vivi
Previously, the recommended B credit for all platforms was 24 / number
of pipes, which would give 6 for newer platforms with 4 pipes. However 6
is not enough and we need 12 on these cases.
We also need a different BW credit for these platforms.
Cc: Arthur J Runyan
Signed-off-by: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index c9b18aab437d..8389cf517ee6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6423,8 +6423,14 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
u32 val;
val = MBUS_DBOX_A_CREDIT(2);
- val |= MBUS_DBOX_BW_CREDIT(1);
- val |= MBUS_DBOX_B_CREDIT(8);
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ val |= MBUS_DBOX_BW_CREDIT(2);
+ val |= MBUS_DBOX_B_CREDIT(12);
+ } else {
+ val |= MBUS_DBOX_BW_CREDIT(1);
+ val |= MBUS_DBOX_B_CREDIT(8);
+ }
I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
}
--
2.21.0
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[Intel-gfx] [PATCH v3 04/21] drm/i915/tgl: Add TGL PCH detection in virtualized environment
From: Mahesh Kumar Assume PCH_TGP when platform is TGL. Cc: Rodrigo Vivi Signed-off-by: Mahesh Kumar Signed-off-by: Lucas De Marchi Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_drv.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index bcedd2d8e267..926bbf2d169b 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -255,7 +255,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv) * make an educated guess as to which PCH is really there. */ - if (IS_ELKHARTLAKE(dev_priv)) + if (IS_TIGERLAKE(dev_priv)) + id = INTEL_PCH_TGP_DEVICE_ID_TYPE; + else if (IS_ELKHARTLAKE(dev_priv)) id = INTEL_PCH_MCC_DEVICE_ID_TYPE; else if (IS_ICELAKE(dev_priv)) id = INTEL_PCH_ICP_DEVICE_ID_TYPE; -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 01/21] drm/i915: Add 4th pipe and transcoder
Add pipe D and transcoder D to prepare for platforms having them.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
drivers/gpu/drm/i915/display/intel_display.h | 4
drivers/gpu/drm/i915/i915_reg.h | 3 +++
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 0286b97caa22..d6ba15c59746 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17189,7 +17189,7 @@ struct intel_display_error_state {
u32 vtotal;
u32 vblank;
u32 vsync;
- } transcoder[4];
+ } transcoder[5];
};
struct intel_display_error_state *
@@ -17200,6 +17200,7 @@ intel_display_capture_error_state(struct
drm_i915_private *dev_priv)
TRANSCODER_A,
TRANSCODER_B,
TRANSCODER_C,
+ TRANSCODER_D,
TRANSCODER_EDP,
};
int i;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 8a4a57ef82a2..1f75b0a627fd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -58,6 +58,7 @@ enum pipe {
PIPE_A = 0,
PIPE_B,
PIPE_C,
+ PIPE_D,
_PIPE_EDP,
I915_MAX_PIPES = _PIPE_EDP
@@ -75,6 +76,7 @@ enum transcoder {
TRANSCODER_A = PIPE_A,
TRANSCODER_B = PIPE_B,
TRANSCODER_C = PIPE_C,
+ TRANSCODER_D = PIPE_D,
/*
* The following transcoders can map to any pipe, their enum value
@@ -98,6 +100,8 @@ static inline const char *transcoder_name(enum transcoder
transcoder)
return "B";
case TRANSCODER_C:
return "C";
+ case TRANSCODER_D:
+ return "D";
case TRANSCODER_EDP:
return "EDP";
case TRANSCODER_DSI_A:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 95b9ca1fda2e..6fe3d74f99ff 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4217,6 +4217,7 @@ enum {
#define TRANSCODER_B_OFFSET 0x61000
#define TRANSCODER_C_OFFSET 0x62000
#define CHV_TRANSCODER_C_OFFSET 0x63000
+#define TRANSCODER_D_OFFSET 0x63000
#define TRANSCODER_EDP_OFFSET 0x6f000
#define TRANSCODER_DSI0_OFFSET 0x6b000
#define TRANSCODER_DSI1_OFFSET 0x6b800
@@ -5763,6 +5764,7 @@ enum {
#define PIPE_A_OFFSET 0x7
#define PIPE_B_OFFSET 0x71000
#define PIPE_C_OFFSET 0x72000
+#define PIPE_D_OFFSET 0x73000
#define CHV_PIPE_C_OFFSET 0x74000
/*
* There's actually no pipe EDP. Some pipe registers have
@@ -9346,6 +9348,7 @@ enum skl_power_gate {
#define _TRANS_DDI_FUNC_CTL_A 0x60400
#define _TRANS_DDI_FUNC_CTL_B 0x61400
#define _TRANS_DDI_FUNC_CTL_C 0x62400
+#define _TRANS_DDI_FUNC_CTL_D 0x63400
#define _TRANS_DDI_FUNC_CTL_EDP0x6F400
#define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
#define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
--
2.21.0
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[Intel-gfx] [PATCH v3 10/21] drm/i915/tgl: Add new pll ids
From: Vandita Kulkarni
Add 2 new PLLs for additional TC ports. The names for the PLLs on TGL
changed, but most registers remained the same, like MGPLL5_ENABLE,
MGPLL6_ENABLE. So continue to use the name from ICL.
Cc: Madhav Chauhan
Cc: Rodrigo Vivi
Signed-off-by: Vandita Kulkarni
Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 23 +++
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 4c2c5e93aff3..d0e14ed6e5f8 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -112,11 +112,11 @@ enum intel_dpll_id {
/**
-* @DPLL_ID_ICL_DPLL0: ICL combo PHY DPLL0
+* @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
*/
DPLL_ID_ICL_DPLL0 = 0,
/**
-* @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1
+* @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
*/
DPLL_ID_ICL_DPLL1 = 1,
/**
@@ -124,27 +124,40 @@ enum intel_dpll_id {
*/
DPLL_ID_EHL_DPLL4 = 2,
/**
-* @DPLL_ID_ICL_TBTPLL: ICL TBT PLL
+* @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
*/
DPLL_ID_ICL_TBTPLL = 2,
/**
-* @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C)
+* @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
+* TGL TC PLL 1 port 1 (TC1)
*/
DPLL_ID_ICL_MGPLL1 = 3,
/**
* @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
+* TGL TC PLL 1 port 2 (TC2)
*/
DPLL_ID_ICL_MGPLL2 = 4,
/**
* @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
+* TGL TC PLL 1 port 3 (TC3)
*/
DPLL_ID_ICL_MGPLL3 = 5,
/**
* @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
+* TGL TC PLL 1 port 4 (TC4)
*/
DPLL_ID_ICL_MGPLL4 = 6,
+ /**
+* @DPLL_ID_TGL_TCPLL5: TGL TC PLL port 5 (TC5)
+*/
+ DPLL_ID_TGL_MGPLL5 = 7,
+ /**
+* @DPLL_ID_TGL_TCPLL6: TGL TC PLL port 6 (TC6)
+*/
+ DPLL_ID_TGL_MGPLL6 = 8,
};
-#define I915_NUM_PLLS 7
+
+#define I915_NUM_PLLS 9
enum icl_port_dpll_id {
ICL_PORT_DPLL_DEFAULT,
--
2.21.0
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[Intel-gfx] [PATCH v3 11/21] drm/i915/tgl: Add pll manager
From: Vandita Kulkarni
Add a new pll array for Tiger Lake. The TC pll functions for type C will
be covered in later patches after its phy is implemented.
Cc: Madhav Chauhan
Cc: Rodrigo Vivi
Signed-off-by: Vandita Kulkarni
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index fc6f3c52629a..8d6ac0b1c4d4 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3466,6 +3466,21 @@ static const struct intel_dpll_mgr ehl_pll_mgr = {
.dump_hw_state = icl_dump_hw_state,
};
+static const struct dpll_info tgl_plls[] = {
+ { "DPLL 0", _pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
+ { "DPLL 1", _pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+ { "TBT PLL", _pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
+ /* TODO: Add typeC plls */
+ { },
+};
+
+static const struct intel_dpll_mgr tgl_pll_mgr = {
+ .dpll_info = tgl_plls,
+ .get_dplls = icl_get_dplls,
+ .put_dplls = icl_put_dplls,
+ .dump_hw_state = icl_dump_hw_state,
+};
+
/**
* intel_shared_dpll_init - Initialize shared DPLLs
* @dev: drm device
@@ -3479,7 +3494,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
const struct dpll_info *dpll_info;
int i;
- if (IS_ELKHARTLAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 12)
+ dpll_mgr = _pll_mgr;
+ else if (IS_ELKHARTLAKE(dev_priv))
dpll_mgr = _pll_mgr;
else if (INTEL_GEN(dev_priv) >= 11)
dpll_mgr = _pll_mgr;
--
2.21.0
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[Intel-gfx] [PATCH v3 03/21] drm/i915/tgl: Introduce Tiger Lake PCH
From: Radhakrishna Sripada
Add the enum additions to TGP.
Cc: Rodrigo Vivi
Cc: Joonas Lahtinen
Cc: David Weinehall
Cc: James Ausmus
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.c | 4
drivers/gpu/drm/i915/i915_drv.h | 3 +++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 794c6814a6d0..bcedd2d8e267 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -224,6 +224,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv,
unsigned short id)
DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n");
WARN_ON(!IS_ELKHARTLAKE(dev_priv));
return PCH_MCC;
+ case INTEL_PCH_TGP_DEVICE_ID_TYPE:
+ DRM_DEBUG_KMS("Found Tiger Lake LP PCH\n");
+ WARN_ON(!IS_TIGERLAKE(dev_priv));
+ return PCH_TGP;
default:
return PCH_NONE;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d6cbae6ae33c..75f7751dd0ee 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -536,6 +536,7 @@ enum intel_pch {
PCH_CNP,/* Cannon/Comet Lake PCH */
PCH_ICP,/* Ice Lake PCH */
PCH_MCC,/* Mule Creek Canyon PCH */
+ PCH_TGP,/* Tiger Lake PCH */
};
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
@@ -2320,6 +2321,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
#define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00
#define INTEL_PCH_MCC2_DEVICE_ID_TYPE 0x3880
+#define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA080
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
@@ -2327,6 +2329,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
#define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
+#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
#define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
--
2.21.0
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[Intel-gfx] ✓ Fi.CI.BAT: success for Associate ddc adapters with connectors
== Series Details ==
Series: Associate ddc adapters with connectors
URL : https://patchwork.freedesktop.org/series/63558/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6460 -> Patchwork_13624
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13624/
Known issues
Here are the changes found in Patchwork_13624 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6460/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13624/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] /
[fdo#108569])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6460/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13624/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
* igt@i915_selftest@live_mman:
- fi-glk-dsi: [PASS][5] -> [INCOMPLETE][6] ([fdo#103359] /
[k.org#198133])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6460/fi-glk-dsi/igt@i915_selftest@live_mman.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13624/fi-glk-dsi/igt@i915_selftest@live_mman.html
Possible fixes
* igt@gem_close_race@basic-threads:
- {fi-icl-u4}:[INCOMPLETE][7] ([fdo#107713]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6460/fi-icl-u4/igt@gem_close_r...@basic-threads.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13624/fi-icl-u4/igt@gem_close_r...@basic-threads.html
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [INCOMPLETE][9] ([fdo#111050]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6460/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13624/fi-skl-iommu/igt@i915_selftest@live_contexts.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (50 -> 47)
--
Additional (2): fi-icl-u3 fi-apl-guc
Missing(5): fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6460 -> Patchwork_13624
CI_DRM_6460: 32d52650873db547f6702f12ebdbae3e8e052dad @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5094: d7f140b5b02d054183a74842b4579cf7f5533927 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13624: 60e82dafe00cea91a273ea2e55475beaccd52954 @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13624/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
60e82dafe00c drm/i915: Provide ddc symlink in hdmi connector sysfs directory
2bdcc775cc25 drm/radeon: Provide ddc symlink in connector sysfs directory
61b383c5fb93 drm/amdgpu: Provide ddc symlink in connector sysfs directory
b3958f606ccc drm/bridge: ti-tfp410: Provide ddc symlink in connector sysfs
directory
d726b6da43f7 drm/bridge: dw-hdmi: Provide ddc symlink in connector sysfs
directory
136be3295b29 drm/bridge: dumb-vga-dac: Provide ddc symlink in connector sysfs
directory
752f9e9d23e4 drm/ast: Provide ddc symlink in connector sysfs directory
475547eaa2a8 drm/mgag200: Provide ddc symlink in connector sysfs directory
4e708680d16d drm: sti: Provide ddc symlink in hdmi connector sysfs directory
09e81b72cb45 drm/tilcdc: Provide ddc symlink in connector sysfs directory
e5a5a4ec10e8 drm: zte: Provide ddc symlink in vga connector sysfs directory
0abf56fc70c9 drm: zte: Provide ddc
[Intel-gfx] [PATCH v3 08/21] drm/i915/tgl: Add power well support
From: Imre Deak
The patch adds the new power wells introduced by TGL (GEN 12) and
maps these to existing/new power domains. The changes for GEN 12 wrt
to GEN 11 are the following:
- Transcoder#EDP removed from power well#1 (Transcoder#A used in
low-power mode instead)
- Transcoder#A is now backed by power well#1 instead of power well#3
- The DDI#B/C combo PHY ports are now backed by power well#1 instead of
power well#3
- New power well#5 added for pipe#D functionality (TODO)
- 2 additional TC ports (TC#5-6) backed by power well#3, 2 port
specific IO power wells (only for the non-TBT modes) and 4 port
specific AUX power wells (2-2 for TBT vs. non-TBT modes)
- Power well#2 backs now VDSC/joining for pipe#A instead of VDSC for
eDP and MIPI DSI (TODO)
On TGL Port DDI#C changed to be a combo PHY (native DP/HDMI) and
BSpec has renamed ports DDI#D-F to TC#4-6 respectively. Thus on ICL we
have the following naming for ports:
- Combo PHYs (native DP/HDMI):
DDI#A-B
- TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
DDI#C-F
Starting from GEN 12 we have the following naming for ports:
- Combo PHYs (native DP/HDMI):
DDI#A-C
- TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
DDI TC#1-6
To save some space in the power domain enum the power domain naming in
the driver reflects the above change, that is power domains TC#1-3 are
added as aliases for DDI#D-F and new power domains are reserved for
TC#4-6.
v2 (Lucas):
- Separate out the bits and definitions for TGL from the ICL ones.
Fix use of TRANSCODER_EDP_VDSC, that is now the correct define since
we don't define TRANSCODER_A_VDSC power domain to spare a one bit in
the bitmask (suggested by Ville)
v3 (Lucas):
- Fix missing squashes on v2
- Rebase on renamed TRANSCODER_EDP_VDSC
Cc: Ville Syrjälä
Cc: Anusha Srivatsa
Cc: Rodrigo Vivi
Cc: José Roberto de Souza
Signed-off-by: Imre Deak
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_power.c| 474 +-
.../drm/i915/display/intel_display_power.h| 26 +-
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 20 +-
4 files changed, 506 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 6a5e0d0724cb..2d91cd70b05b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -23,8 +23,11 @@ bool intel_display_power_well_is_enabled(struct
drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id);
const char *
-intel_display_power_domain_str(enum intel_display_power_domain domain)
+intel_display_power_domain_str(struct drm_i915_private *i915,
+ enum intel_display_power_domain domain)
{
+ bool ddi_tc_ports = IS_GEN(i915, 12);
+
switch (domain) {
case POWER_DOMAIN_DISPLAY_CORE:
return "DISPLAY_CORE";
@@ -61,11 +64,23 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
case POWER_DOMAIN_PORT_DDI_C_LANES:
return "PORT_DDI_C_LANES";
case POWER_DOMAIN_PORT_DDI_D_LANES:
- return "PORT_DDI_D_LANES";
+ BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_LANES !=
+POWER_DOMAIN_PORT_DDI_TC1_LANES);
+ return ddi_tc_ports ? "PORT_DDI_TC1_LANES" : "PORT_DDI_D_LANES";
case POWER_DOMAIN_PORT_DDI_E_LANES:
- return "PORT_DDI_E_LANES";
+ BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_LANES !=
+POWER_DOMAIN_PORT_DDI_TC2_LANES);
+ return ddi_tc_ports ? "PORT_DDI_TC2_LANES" : "PORT_DDI_E_LANES";
case POWER_DOMAIN_PORT_DDI_F_LANES:
- return "PORT_DDI_F_LANES";
+ BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_LANES !=
+POWER_DOMAIN_PORT_DDI_TC3_LANES);
+ return ddi_tc_ports ? "PORT_DDI_TC3_LANES" : "PORT_DDI_F_LANES";
+ case POWER_DOMAIN_PORT_DDI_TC4_LANES:
+ return "PORT_DDI_TC4_LANES";
+ case POWER_DOMAIN_PORT_DDI_TC5_LANES:
+ return "PORT_DDI_TC5_LANES";
+ case POWER_DOMAIN_PORT_DDI_TC6_LANES:
+ return "PORT_DDI_TC6_LANES";
case POWER_DOMAIN_PORT_DDI_A_IO:
return "PORT_DDI_A_IO";
case POWER_DOMAIN_PORT_DDI_B_IO:
@@ -73,11 +88,23 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
case POWER_DOMAIN_PORT_DDI_C_IO:
return "PORT_DDI_C_IO";
case POWER_DOMAIN_PORT_DDI_D_IO:
- return "PORT_DDI_D_IO";
+ BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_IO !=
+POWER_DOMAIN_PORT_DDI_TC1_IO);
+ return ddi_tc_ports ? "PORT_DDI_TC1_IO" : "PORT_DDI_D_IO";
case
[Intel-gfx] [PATCH v3 17/21] drm/i915/tgl: Add gmbus gpio pin to port mapping
From: Mahesh Kumar
Add default GPIO pin mapping for all ports. Tiger Lake has 3 combophy
ports and 6 TC ports, gpio pin1-3 are mapped to combophy & pin9-14 are
mapped to TC ports.
Cc: Anusha Srivatsa
Cc: Rodrigo Vivi
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display.h | 2 ++
drivers/gpu/drm/i915/display/intel_gmbus.c | 20 ++--
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
3 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 92931dc26470..67743eea4a50 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -45,6 +45,8 @@ enum i915_gpio {
GPIOK,
GPIOL,
GPIOM,
+ GPION,
+ GPIOO,
};
/*
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 4f6a9bd5af47..b42c79aea61a 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -94,11 +94,25 @@ static const struct gmbus_pin gmbus_pins_mcc[] = {
[GMBUS_PIN_9_TC1_ICP] = { "dpc", GPIOJ },
};
+static const struct gmbus_pin gmbus_pins_tgp[] = {
+ [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+ [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+ [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+ [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
+ [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
+ [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
+ [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
+ [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
+ [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
+};
+
/* pin is expected to be valid */
static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
unsigned int pin)
{
- if (HAS_PCH_MCC(dev_priv))
+ if (HAS_PCH_TGP(dev_priv))
+ return _pins_tgp[pin];
+ else if (HAS_PCH_MCC(dev_priv))
return _pins_mcc[pin];
else if (HAS_PCH_ICP(dev_priv))
return _pins_icp[pin];
@@ -119,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv,
{
unsigned int size;
- if (HAS_PCH_MCC(dev_priv))
+ if (HAS_PCH_TGP(dev_priv))
+ size = ARRAY_SIZE(gmbus_pins_tgp);
+ else if (HAS_PCH_MCC(dev_priv))
size = ARRAY_SIZE(gmbus_pins_mcc);
else if (HAS_PCH_ICP(dev_priv))
size = ARRAY_SIZE(gmbus_pins_icp);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ad96c5b4975c..62ac8a119602 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3254,8 +3254,10 @@ enum i915_power_well_id {
#define GMBUS_PIN_10_TC2_ICP 10
#define GMBUS_PIN_11_TC3_ICP 11
#define GMBUS_PIN_12_TC4_ICP 12
+#define GMBUS_PIN_13_TC5_TGP 13
+#define GMBUS_PIN_14_TC6_TGP 14
-#define GMBUS_NUM_PINS 13 /* including 0 */
+#define GMBUS_NUM_PINS 15 /* including 0 */
#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /*
command/status */
#define GMBUS_SW_CLR_INT (1 << 31)
#define GMBUS_SW_RDY (1 << 30)
--
2.21.0
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[Intel-gfx] [PATCH v3 14/21] drm/i915/tgl: init ddi port A-C for Tiger Lake
From: Mahesh Kumar
This patch initializes DDI PORT A, B & C for Tiger lake. Other
TC ports need to be initialized later once corresponding code is there.
Cc: Madhav Chauhan
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index ba48fedd685b..c9b18aab437d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15310,13 +15310,18 @@ static void intel_setup_outputs(struct
drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (IS_ELKHARTLAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 12) {
+ /* TODO: initialize TC ports as well */
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ intel_ddi_init(dev_priv, PORT_C);
+ } else if (IS_ELKHARTLAKE(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
intel_ddi_init(dev_priv, PORT_D);
icl_dsi_init(dev_priv);
- } else if (INTEL_GEN(dev_priv) >= 11) {
+ } else if (IS_GEN(dev_priv, 11)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
--
2.21.0
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[Intel-gfx] [PATCH v3 15/21] drm/i915/tgl: apply Display WA #1178 to fix type C dongles
Add port C to workaround to cover Tiger Lake.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/display/intel_display_power.c | 7 +++
drivers/gpu/drm/i915/i915_reg.h| 4 +++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 12aa9ce08d95..061432862c7d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -453,6 +453,7 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private
*dev_priv,
int pw_idx = power_well->desc->hsw.idx;
enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
u32 val;
+ int wa_idx_max;
val = I915_READ(regs->driver);
I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
@@ -462,6 +463,12 @@ icl_combo_phy_aux_power_well_enable(struct
drm_i915_private *dev_priv,
hsw_wait_for_power_well_enable(dev_priv, power_well);
+ /* Display WA #1178: icl, tgl */
+ if (IS_TIGERLAKE(dev_priv))
+ wa_idx_max = ICL_PW_CTL_IDX_AUX_C;
+ else
+ wa_idx_max = ICL_PW_CTL_IDX_AUX_B;
+
/* Display WA #1178: icl */
if (IS_ICELAKE(dev_priv) &&
pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ca70be40a467..ad96c5b4975c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9244,9 +9244,11 @@ enum skl_power_gate {
#define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
#define _ICL_AUX_ANAOVRD1_A0x162398
#define _ICL_AUX_ANAOVRD1_B0x6C398
+#define _TGL_AUX_ANAOVRD1_C0x160398
#define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
_ICL_AUX_ANAOVRD1_A, \
- _ICL_AUX_ANAOVRD1_B))
+ _ICL_AUX_ANAOVRD1_B, \
+ _TGL_AUX_ANAOVRD1_C))
#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
--
2.21.0
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[Intel-gfx] [PATCH v3 06/21] drm/i915/tgl: Check if pipe D is fused
From: José Roberto de Souza
On Tiger Lake there is one more pipe - check if it's fused.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
Reviewed-by: Mika Kahola
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6fe3d74f99ff..94e76fa9d114 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7633,6 +7633,7 @@ enum {
#define SKL_DFSM_PIPE_A_DISABLE(1 << 30)
#define SKL_DFSM_PIPE_B_DISABLE(1 << 21)
#define SKL_DFSM_PIPE_C_DISABLE(1 << 28)
+#define TGL_DFSM_PIPE_D_DISABLE(1 << 22)
#define SKL_DSSM _MMIO(0x51004)
#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz(1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index e0d9a7a37994..f99c9fd497b2 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -938,6 +938,9 @@ void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv)
enabled_mask &= ~BIT(PIPE_B);
if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
enabled_mask &= ~BIT(PIPE_C);
+ if (INTEL_GEN(dev_priv) >= 12 &&
+ (dfsm & TGL_DFSM_PIPE_D_DISABLE))
+ enabled_mask &= ~BIT(PIPE_D);
/*
* At least one pipe should be enabled and if there are
--
2.21.0
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[Intel-gfx] [PATCH v3 09/21] drm/i915/tgl: Add power well to support 4th pipe
From: Mika Kahola
Add power well 5 to support 4th pipe and transcoder on TGL.
Cc: James Ausmus
Cc: Imre Deak
Signed-off-by: Mika Kahola
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
---
.../drm/i915/display/intel_display_power.c| 28 +--
.../drm/i915/display/intel_display_power.h| 3 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
3 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 2d91cd70b05b..12aa9ce08d95 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -37,18 +37,24 @@ intel_display_power_domain_str(struct drm_i915_private
*i915,
return "PIPE_B";
case POWER_DOMAIN_PIPE_C:
return "PIPE_C";
+ case POWER_DOMAIN_PIPE_D:
+ return "PIPE_D";
case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
return "PIPE_A_PANEL_FITTER";
case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
return "PIPE_B_PANEL_FITTER";
case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
return "PIPE_C_PANEL_FITTER";
+ case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
+ return "PIPE_D_PANEL_FITTER";
case POWER_DOMAIN_TRANSCODER_A:
return "TRANSCODER_A";
case POWER_DOMAIN_TRANSCODER_B:
return "TRANSCODER_B";
case POWER_DOMAIN_TRANSCODER_C:
return "TRANSCODER_C";
+ case POWER_DOMAIN_TRANSCODER_D:
+ return "TRANSCODER_D";
case POWER_DOMAIN_TRANSCODER_EDP:
return "TRANSCODER_EDP";
case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
@@ -2540,8 +2546,13 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
#define ICL_AUX_TBT4_IO_POWER_DOMAINS (\
BIT_ULL(POWER_DOMAIN_AUX_TBT4))
-/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
+#define TGL_PW_5_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_D) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
#define TGL_PW_4_POWER_DOMAINS ( \
+ TGL_PW_5_POWER_DOMAINS |\
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -2551,7 +2562,7 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |\
- /* TODO: TRANSCODER_D */\
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |\
BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) | \
@@ -3894,7 +3905,18 @@ static const struct i915_power_well_desc
tgl_power_wells[] = {
.hsw.irq_pipe_mask = BIT(PIPE_C),
}
},
- /* TODO: power well 5 for pipe D */
+ {
+ .name = "power well 5",
+ .domains = TGL_PW_5_POWER_DOMAINS,
+ .ops = _power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = _power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_PW_5,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_D),
+ },
+ },
};
static int
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index 54ad4f0b0886..a264f18c95f1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -18,12 +18,15 @@ enum intel_display_power_domain {
POWER_DOMAIN_PIPE_A,
POWER_DOMAIN_PIPE_B,
POWER_DOMAIN_PIPE_C,
+ POWER_DOMAIN_PIPE_D,
POWER_DOMAIN_PIPE_A_PANEL_FITTER,
POWER_DOMAIN_PIPE_B_PANEL_FITTER,
POWER_DOMAIN_PIPE_C_PANEL_FITTER,
+ POWER_DOMAIN_PIPE_D_PANEL_FITTER,
POWER_DOMAIN_TRANSCODER_A,
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_TRANSCODER_C,
+ POWER_DOMAIN_TRANSCODER_D,
POWER_DOMAIN_TRANSCODER_EDP,
/* VDSC/joining for TRANSCODER_EDP (ICL) or TRANSCODER_A (TGL) */
POWER_DOMAIN_TRANSCODER_VDSC_PW2,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7df1584e7ff1..ca70be40a467 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9148,6 +9148,7 @@ enum {
#define SKL_PW_CTL_IDX_MISC_IO 0
/* ICL/TGL - power wells */
+#define TGL_PW_CTL_IDX_PW_5 4
#define
[Intel-gfx] [PATCH v3 19/21] drm/i915/tgl: Add vbt value mapping for DDC Bus pin
From: Mahesh Kumar
Add VBT-value to DDC bus pin mapping for the same.
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 17 -
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 3 +++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 4fdbb5c35d87..2fe68f72b88f 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1355,12 +1355,27 @@ static const u8 mcc_ddc_pin_map[] = {
[MCC_DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP,
};
+static const u8 tgp_ddc_pin_map[] = {
+ [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
+ [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
+ [TGL_DDC_BUS_DDI_C] = GMBUS_PIN_3_BXT,
+ [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP,
+ [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP,
+ [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP,
+ [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP,
+ [TGL_DDC_BUS_PORT_5] = GMBUS_PIN_13_TC5_TGP,
+ [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
+};
+
static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
{
const u8 *ddc_pin_map;
int n_entries;
- if (HAS_PCH_MCC(dev_priv)) {
+ if (HAS_PCH_TGP(dev_priv)) {
+ ddc_pin_map = tgp_ddc_pin_map;
+ n_entries = ARRAY_SIZE(tgp_ddc_pin_map);
+ } else if (HAS_PCH_MCC(dev_priv)) {
ddc_pin_map = mcc_ddc_pin_map;
n_entries = ARRAY_SIZE(mcc_ddc_pin_map);
} else if (HAS_PCH_ICP(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 2f4894e9a03d..93f5c9d204d6 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -310,10 +310,13 @@ enum vbt_gmbus_ddi {
DDC_BUS_DDI_F,
ICL_DDC_BUS_DDI_A = 0x1,
ICL_DDC_BUS_DDI_B,
+ TGL_DDC_BUS_DDI_C,
ICL_DDC_BUS_PORT_1 = 0x4,
ICL_DDC_BUS_PORT_2,
ICL_DDC_BUS_PORT_3,
ICL_DDC_BUS_PORT_4,
+ TGL_DDC_BUS_PORT_5,
+ TGL_DDC_BUS_PORT_6,
MCC_DDC_BUS_DDI_A = 0x1,
MCC_DDC_BUS_DDI_B,
MCC_DDC_BUS_DDI_C = 0x4,
--
2.21.0
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[Intel-gfx] [PATCH v3 21/21] drm/i915/tgl: Update DPLL clock reference register
From: José Roberto de Souza
This register definition changed from ICL and has now another meaning.
Use the right bits on TGL.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 9baa6adc63db..aafe25e6319a 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2602,8 +2602,12 @@ static bool icl_calc_dpll_state(struct intel_crtc_state
*crtc_state,
cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
DPLL_CFGCR1_KDIV(pll_params.kdiv) |
-DPLL_CFGCR1_PDIV(pll_params.pdiv) |
-DPLL_CFGCR1_CENTRAL_FREQ_8400;
+DPLL_CFGCR1_PDIV(pll_params.pdiv);
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
+ else
+ cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
memset(pll_state, 0, sizeof(*pll_state));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c8277862bbbe..3ff659a180e6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9944,6 +9944,7 @@ enum skl_power_gate {
#define DPLL_CFGCR1_PDIV_7(8 << 2)
#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
+#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
#define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1,
_CNL_DPLL1_CFGCR1)
#define _ICL_DPLL0_CFGCR0 0x164000
--
2.21.0
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[Intel-gfx] [PATCH v3 20/21] drm/i915/tgl: Add DPLL registers
On TGL the port programming for combophy is very similar to ICL, so
adapt the callers to possibly use the different register values.
v2 (Lucas): Add TODO with about DPLL4 (requested by Ville)
Cc: Vandita Kulkarni
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++
drivers/gpu/drm/i915/i915_reg.h | 17 +
2 files changed, 36 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 8d6ac0b1c4d4..9baa6adc63db 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3124,8 +3124,13 @@ static bool icl_pll_get_hw_state(struct drm_i915_private
*dev_priv,
if (!(val & PLL_ENABLE))
goto out;
- hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
- hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
+ if (INTEL_GEN(dev_priv) >= 12) {
+ hw_state->cfgcr0 = I915_READ(TGL_DPLL_CFGCR0(id));
+ hw_state->cfgcr1 = I915_READ(TGL_DPLL_CFGCR1(id));
+ } else {
+ hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
+ hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
+ }
ret = true;
out:
@@ -3159,10 +3164,19 @@ static void icl_dpll_write(struct drm_i915_private
*dev_priv,
{
struct intel_dpll_hw_state *hw_state = >state.hw_state;
const enum intel_dpll_id id = pll->info->id;
+ i915_reg_t cfgcr0_reg, cfgcr1_reg;
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ cfgcr0_reg = TGL_DPLL_CFGCR0(id);
+ cfgcr1_reg = TGL_DPLL_CFGCR1(id);
+ } else {
+ cfgcr0_reg = ICL_DPLL_CFGCR0(id);
+ cfgcr1_reg = ICL_DPLL_CFGCR1(id);
+ }
- I915_WRITE(ICL_DPLL_CFGCR0(id), hw_state->cfgcr0);
- I915_WRITE(ICL_DPLL_CFGCR1(id), hw_state->cfgcr1);
- POSTING_READ(ICL_DPLL_CFGCR1(id));
+ I915_WRITE(cfgcr0_reg, hw_state->cfgcr0);
+ I915_WRITE(cfgcr1_reg, hw_state->cfgcr1);
+ POSTING_READ(cfgcr1_reg);
}
static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 62ac8a119602..c8277862bbbe 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -242,6 +242,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
+#define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c))
/*
* Device info offset array based helpers for groups of registers with unevenly
@@ -9955,6 +9956,22 @@ enum skl_power_gate {
#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
_ICL_DPLL1_CFGCR1)
+#define _TGL_DPLL0_CFGCR0 0x164284
+#define _TGL_DPLL1_CFGCR0 0x16428C
+/* TODO: add DPLL4 */
+#define _TGL_TBTPLL_CFGCR0 0x16429C
+#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
+ _TGL_DPLL1_CFGCR0, \
+ _TGL_TBTPLL_CFGCR0)
+
+#define _TGL_DPLL0_CFGCR1 0x164288
+#define _TGL_DPLL1_CFGCR1 0x164290
+/* TODO: add DPLL4 */
+#define _TGL_TBTPLL_CFGCR1 0x1642A0
+#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
+ _TGL_DPLL1_CFGCR1, \
+ _TGL_TBTPLL_CFGCR1)
+
/* BXT display engine PLL */
#define BXT_DE_PLL_CTL _MMIO(0x6d000)
#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
--
2.21.0
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[Intel-gfx] [PATCH v3 18/21] drm/i915/tgl: port to ddc pin mapping
Make the icl function generic so it is based on phy type and can be
applied to tgl as well.
I checked if this could not apply to EHL as well, but unfortunately
there the HPD and DDC/GMBUS pins for DDI C are mapped to TypeC Port 1
even though it doesn't have TC phy.
v2: don't add a separate function for TGL, but rather reuse the ICL one
(suggested by Rodrigo)
v3: rebase after the introduction of enum phy and use it for the
conversions
Cc: Anusha Srivatsa
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 36 ++-
1 file changed, 9 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0ebec69bbbfc..77af0dfd93ce 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2930,33 +2930,15 @@ static u8 cnp_port_to_ddc_pin(struct drm_i915_private
*dev_priv,
static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port
port)
{
- u8 ddc_pin;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
- switch (port) {
- case PORT_A:
- ddc_pin = GMBUS_PIN_1_BXT;
- break;
- case PORT_B:
- ddc_pin = GMBUS_PIN_2_BXT;
- break;
- case PORT_C:
- ddc_pin = GMBUS_PIN_9_TC1_ICP;
- break;
- case PORT_D:
- ddc_pin = GMBUS_PIN_10_TC2_ICP;
- break;
- case PORT_E:
- ddc_pin = GMBUS_PIN_11_TC3_ICP;
- break;
- case PORT_F:
- ddc_pin = GMBUS_PIN_12_TC4_ICP;
- break;
- default:
- MISSING_CASE(port);
- ddc_pin = GMBUS_PIN_2_BXT;
- break;
- }
- return ddc_pin;
+ if (intel_phy_is_combo(dev_priv, phy))
+ return GMBUS_PIN_1_BXT + port;
+ else if (intel_phy_is_tc(dev_priv, phy))
+ return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
+
+ WARN(1, "Unknown port:%c\n", port_name(port));
+ return GMBUS_PIN_2_BXT;
}
static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port
port)
@@ -3019,7 +3001,7 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private
*dev_priv,
if (HAS_PCH_MCC(dev_priv))
ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
- else if (HAS_PCH_ICP(dev_priv))
+ else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_ICP(dev_priv))
ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
else if (HAS_PCH_CNP(dev_priv))
ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
--
2.21.0
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[Intel-gfx] [PATCH v3 13/21] drm/i915/tgl: Add additional PHYs for Tiger Lake
Tiger Lake has up to 3 combo phys and 6 TC phys. Extend the helper
conversion functions from port to phy.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 5 -
drivers/gpu/drm/i915/display/intel_display.h | 3 +++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 1d6dc73dfc81..ba48fedd685b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6676,7 +6676,7 @@ bool intel_phy_is_combo(struct drm_i915_private
*dev_priv, enum phy phy)
if (phy == PHY_NONE)
return false;
- if (IS_ELKHARTLAKE(dev_priv))
+ if (IS_ELKHARTLAKE(dev_priv) || INTEL_GEN(dev_priv) >= 12)
return phy <= PHY_C;
if (INTEL_GEN(dev_priv) >= 11)
@@ -6687,6 +6687,9 @@ bool intel_phy_is_combo(struct drm_i915_private
*dev_priv, enum phy phy)
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
+ if (INTEL_GEN(dev_priv) >= 12)
+ return phy >= PHY_D && phy <= PHY_I;
+
if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
return phy >= PHY_C && phy <= PHY_F;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 72ce27079a56..92931dc26470 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -249,6 +249,9 @@ enum phy {
PHY_D,
PHY_E,
PHY_F,
+ PHY_G,
+ PHY_H,
+ PHY_I,
I915_MAX_PHYS
};
--
2.21.0
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[Intel-gfx] [PATCH v3 12/21] drm/i915/tgl: Add additional ports for Tiger Lake
From: Vandita Kulkarni
There are 2 new additional typeC ports in Tiger Lake and PORT-C is now a
combophy port. This results in 6 typeC ports and 3 combophy ports.
These 6 TC ports can be DP alternate mode, DP over thunderbolt, native
DP on legacy DP connector or native HDMI on legacy connector.
v2: Rebase on new modular FIA code (Lucas)
v3: Also add new port in port_identifier(), even though it can't
possibly be used there (requested by José)
v4: Add conversion port->tc_port in helper function after introction of
phy namespace (Lucas)
Cc: Anusha Srivatsa
Signed-off-by: Vandita Kulkarni
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 12
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
drivers/gpu/drm/i915/display/intel_display.h | 8
include/drm/i915_component.h | 2 +-
include/drm/i915_drm.h | 3 +++
5 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1662e5c2be1c..8445244aa593 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4286,6 +4286,18 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
intel_dig_port->ddi_io_power_domain =
POWER_DOMAIN_PORT_DDI_F_IO;
break;
+ case PORT_G:
+ intel_dig_port->ddi_io_power_domain =
+ POWER_DOMAIN_PORT_DDI_G_IO;
+ break;
+ case PORT_H:
+ intel_dig_port->ddi_io_power_domain =
+ POWER_DOMAIN_PORT_DDI_H_IO;
+ break;
+ case PORT_I:
+ intel_dig_port->ddi_io_power_domain =
+ POWER_DOMAIN_PORT_DDI_I_IO;
+ break;
default:
MISSING_CASE(port);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d6ba15c59746..1d6dc73dfc81 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6706,6 +6706,9 @@ enum tc_port intel_port_to_tc(struct drm_i915_private
*dev_priv, enum port port)
if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
return PORT_TC_NONE;
+ if (INTEL_GEN(dev_priv) >= 12)
+ return port - PORT_D;
+
return port - PORT_C;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 1f75b0a627fd..72ce27079a56 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -177,6 +177,12 @@ static inline const char *port_identifier(enum port port)
return "Port E";
case PORT_F:
return "Port F";
+ case PORT_G:
+ return "Port G";
+ case PORT_H:
+ return "Port H";
+ case PORT_I:
+ return "Port I";
default:
return "";
}
@@ -189,6 +195,8 @@ enum tc_port {
PORT_TC2,
PORT_TC3,
PORT_TC4,
+ PORT_TC5,
+ PORT_TC6,
I915_MAX_TC_PORTS
};
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index dcb95bd9dee6..55c3b123581b 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -34,7 +34,7 @@ enum i915_component_type {
/* MAX_PORT is the number of port
* It must be sync with I915_MAX_PORTS defined i915_drv.h
*/
-#define MAX_PORTS 6
+#define MAX_PORTS 9
/**
* struct i915_audio_component - Used for direct communication between i915
and hda drivers
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 7523e9a7b6e2..eb30062359d1 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -109,6 +109,9 @@ enum port {
PORT_D,
PORT_E,
PORT_F,
+ PORT_G,
+ PORT_H,
+ PORT_I,
I915_MAX_PORTS
};
--
2.21.0
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[Intel-gfx] [PATCH v3 02/21] drm/i915/tgl: add initial Tiger Lake definitions
From: Daniele Ceraolo Spurio
Tiger Lake is a Intel® Processor containing Intel® HD Graphics.
This is just an initial Tiger Lake definition. PCI IDs, generic support
and new features coming in following patches.
v2 (Lucas):
- Remove modular FIA - feature will be re-introduced in future
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 29
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
4 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 76116e44b7e1..d6cbae6ae33c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2086,6 +2086,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_CANNONLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
#define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
+#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 94b588e0a1dd..da926485845d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -765,6 +765,35 @@ static const struct intel_device_info
intel_elkhartlake_info = {
.ppgtt_size = 36,
};
+#define GEN12_FEATURES \
+ GEN11_FEATURES, \
+ GEN(12), \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ [TRANSCODER_C] = PIPE_C_OFFSET, \
+ [TRANSCODER_D] = PIPE_D_OFFSET, \
+ [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
+ [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
+ [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
+ [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
+ [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
+ }
+
+static const struct intel_device_info intel_tigerlake_12_info = {
+ GEN12_FEATURES,
+ PLATFORM(INTEL_TIGERLAKE),
+ .num_pipes = 4,
+ .require_force_probe = 1,
+ .engine_mask =
+ BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+};
+
#undef GEN
#undef PLATFORM
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index e64536e1fd1b..e0d9a7a37994 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -58,6 +58,7 @@ static const char * const platform_names[] = {
PLATFORM_NAME(CANNONLAKE),
PLATFORM_NAME(ICELAKE),
PLATFORM_NAME(ELKHARTLAKE),
+ PLATFORM_NAME(TIGERLAKE),
};
#undef PLATFORM_NAME
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index ddafc819bf30..468582484758 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -78,6 +78,8 @@ enum intel_platform {
/* gen11 */
INTEL_ICELAKE,
INTEL_ELKHARTLAKE,
+ /* gen12 */
+ INTEL_TIGERLAKE,
INTEL_MAX_PLATFORMS
};
--
2.21.0
___
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[Intel-gfx] [PATCH v3 05/21] drm/i915/tgl: Add TGL PCI IDs
Current list of PCI IDs for Tiger Lake.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Reviewed-by: Mika Kahola
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h | 10 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index da926485845d..e83c94cf2744 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -865,6 +865,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_CNL_IDS(_cannonlake_info),
INTEL_ICL_11_IDS(_icelake_11_info),
INTEL_EHL_IDS(_elkhartlake_info),
+ INTEL_TGL_12_IDS(_tigerlake_12_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 6c342ac470c8..a70c982ddff9 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -583,4 +583,14 @@
INTEL_VGA_DEVICE(0x4551, info), \
INTEL_VGA_DEVICE(0x4541, info)
+/* TGL */
+#define INTEL_TGL_12_IDS(info) \
+ INTEL_VGA_DEVICE(0x9A49, info), \
+ INTEL_VGA_DEVICE(0x9A40, info), \
+ INTEL_VGA_DEVICE(0x9A59, info), \
+ INTEL_VGA_DEVICE(0x9A60, info), \
+ INTEL_VGA_DEVICE(0x9A68, info), \
+ INTEL_VGA_DEVICE(0x9A70, info), \
+ INTEL_VGA_DEVICE(0x9A78, info)
+
#endif /* _I915_PCIIDS_H */
--
2.21.0
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[Intel-gfx] [PATCH v3 07/21] drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on transcoder A
From: José Roberto de Souza
On TGL the special EDP transcoder is gone and it should be handled by
transcoder A.
v2 (Lucas):
- Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggested by Ville)
- Use crtc->dev since new_crtc_state->state may be NULL on atomic
commit (suggested by Maarten)
v3 (Lucas):
- Rename power domain so it's clear it can also be used for transcoder
A in TGL (requested by José and Manasi)
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
Acked-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++---
drivers/gpu/drm/i915/display/intel_display_power.h | 3 ++-
drivers/gpu/drm/i915/display/intel_vdsc.c | 14 ++
3 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 7e22a2704843..6a5e0d0724cb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -48,8 +48,8 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
return "TRANSCODER_C";
case POWER_DOMAIN_TRANSCODER_EDP:
return "TRANSCODER_EDP";
- case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
- return "TRANSCODER_EDP_VDSC";
+ case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
+ return "TRANSCODER_VDSC_PW2";
case POWER_DOMAIN_TRANSCODER_DSI_A:
return "TRANSCODER_DSI_A";
case POWER_DOMAIN_TRANSCODER_DSI_C:
@@ -2450,7 +2450,7 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
*/
#define ICL_PW_2_POWER_DOMAINS ( \
ICL_PW_3_POWER_DOMAINS |\
- BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
BIT_ULL(POWER_DOMAIN_INIT))
/*
* - KVMR (HW control)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index 8f43f7051a16..cc6956132ebc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -25,7 +25,8 @@ enum intel_display_power_domain {
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_TRANSCODER_C,
POWER_DOMAIN_TRANSCODER_EDP,
- POWER_DOMAIN_TRANSCODER_EDP_VDSC,
+ /* VDSC/joining for TRANSCODER_EDP (ICL) or TRANSCODER_A (TGL) */
+ POWER_DOMAIN_TRANSCODER_VDSC_PW2,
POWER_DOMAIN_TRANSCODER_DSI_A,
POWER_DOMAIN_TRANSCODER_DSI_C,
POWER_DOMAIN_PORT_DDI_A_LANES,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index ffec807b8960..4ab19c432ef5 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -459,17 +459,23 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
enum intel_display_power_domain
intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
{
+ struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
/*
-* On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
-* This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
+* On ICL VDSC/joining for eDP transcoder uses a separate power well,
+* PW2. This requires POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain.
* For any other transcoder, VDSC/joining uses the power well associated
* with the pipe/transcoder in use. Hence another reference on the
* transcoder power domain will suffice.
+*
+* On TGL we have the same mapping, but for transcoder A (the special
+* TRANSCODER_EDP is gone).
*/
- if (cpu_transcoder == TRANSCODER_EDP)
- return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
+ if (INTEL_GEN(i915) >= 12 && cpu_transcoder == TRANSCODER_A)
+ return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
+ else if (cpu_transcoder == TRANSCODER_EDP)
+ return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
else
return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
}
--
2.21.0
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[Intel-gfx] [PATCH v3 00/21] Initial support for Tiger Lake
v3 of https://patchwork.freedesktop.org/series/62726/ (with the individual patch updates in v2). This removes the patches that can't be applied right away because of lack of reviews and rebase the series on the just introduced enum phy. Patches that changed too much or are new got their R-b tags removed. Please re-review. Daniele Ceraolo Spurio (1): drm/i915/tgl: add initial Tiger Lake definitions Imre Deak (1): drm/i915/tgl: Add power well support José Roberto de Souza (3): drm/i915/tgl: Check if pipe D is fused drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on transcoder A drm/i915/tgl: Update DPLL clock reference register Lucas De Marchi (6): drm/i915: Add 4th pipe and transcoder drm/i915/tgl: Add TGL PCI IDs drm/i915/tgl: Add additional PHYs for Tiger Lake drm/i915/tgl: apply Display WA #1178 to fix type C dongles drm/i915/tgl: port to ddc pin mapping drm/i915/tgl: Add DPLL registers Mahesh Kumar (4): drm/i915/tgl: Add TGL PCH detection in virtualized environment drm/i915/tgl: init ddi port A-C for Tiger Lake drm/i915/tgl: Add gmbus gpio pin to port mapping drm/i915/tgl: Add vbt value mapping for DDC Bus pin Mika Kahola (1): drm/i915/tgl: Add power well to support 4th pipe Radhakrishna Sripada (1): drm/i915/tgl: Introduce Tiger Lake PCH Rodrigo Vivi (1): drm/i915/gen12: MBUS B credit change Vandita Kulkarni (3): drm/i915/tgl: Add new pll ids drm/i915/tgl: Add pll manager drm/i915/tgl: Add additional ports for Tiger Lake drivers/gpu/drm/i915/display/intel_bios.c | 17 +- drivers/gpu/drm/i915/display/intel_ddi.c | 12 + drivers/gpu/drm/i915/display/intel_display.c | 30 +- drivers/gpu/drm/i915/display/intel_display.h | 17 + .../drm/i915/display/intel_display_power.c| 509 +- .../drm/i915/display/intel_display_power.h| 32 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 51 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 23 +- drivers/gpu/drm/i915/display/intel_gmbus.c| 20 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 36 +- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 3 + drivers/gpu/drm/i915/display/intel_vdsc.c | 14 +- drivers/gpu/drm/i915/i915_debugfs.c | 3 +- drivers/gpu/drm/i915/i915_drv.c | 8 +- drivers/gpu/drm/i915/i915_drv.h | 4 + drivers/gpu/drm/i915/i915_pci.c | 30 ++ drivers/gpu/drm/i915/i915_reg.h | 51 +- drivers/gpu/drm/i915/intel_device_info.c | 4 + drivers/gpu/drm/i915/intel_device_info.h | 2 + include/drm/i915_component.h | 2 +- include/drm/i915_drm.h| 3 + include/drm/i915_pciids.h | 10 + 22 files changed, 803 insertions(+), 78 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Ensure we don't clamp a random offset to 32b (rev2)
== Series Details == Series: drm/i915/selftests: Ensure we don't clamp a random offset to 32b (rev2) URL : https://patchwork.freedesktop.org/series/63506/ State : success == Summary == CI Bug Log - changes from CI_DRM_6451_full -> Patchwork_13608_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13608_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +5 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-apl3/igt@gem_workarou...@suspend-resume-context.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13608/shard-apl5/igt@gem_workarou...@suspend-resume-context.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-kbl6/igt@kms_cursor_...@pipe-a-cursor-suspend.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13608/shard-kbl3/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][5] -> [FAIL][6] ([fdo#105363]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-skl10/igt@kms_f...@flip-vs-expired-vblank.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13608/shard-skl6/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-suspend: - shard-hsw: [PASS][7] -> [INCOMPLETE][8] ([fdo#103540]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-hsw5/igt@kms_f...@flip-vs-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13608/shard-hsw2/igt@kms_f...@flip-vs-suspend.html * igt@kms_flip_tiling@flip-y-tiled: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#108303]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-iclb2/igt@kms_flip_til...@flip-y-tiled.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13608/shard-iclb7/igt@kms_flip_til...@flip-y-tiled.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13608/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [fdo#110403]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-skl6/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13608/shard-skl2/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_psr2_su@page_flip: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109642] / [fdo#111068]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-iclb2/igt@kms_psr2_su@page_flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13608/shard-iclb7/igt@kms_psr2_su@page_flip.html * igt@kms_vblank@pipe-a-wait-busy-hang: - shard-iclb: [PASS][17] -> [INCOMPLETE][18] ([fdo#107713]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-iclb5/igt@kms_vbl...@pipe-a-wait-busy-hang.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13608/shard-iclb7/igt@kms_vbl...@pipe-a-wait-busy-hang.html * igt@perf@polling: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#110728]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-skl9/igt@p...@polling.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13608/shard-skl7/igt@p...@polling.html Possible fixes * igt@gem_eio@reset-stress: - shard-snb: [FAIL][21] ([fdo#109661]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-snb1/igt@gem_...@reset-stress.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13608/shard-snb6/igt@gem_...@reset-stress.html * igt@gem_exec_flush@basic-wb-ro-default: - shard-apl: [INCOMPLETE][23] ([fdo#103927]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-apl3/igt@gem_exec_fl...@basic-wb-ro-default.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13608/shard-apl4/igt@gem_exec_fl...@basic-wb-ro-default.html * igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled: - shard-skl: [FAIL][25] ([fdo#103184] / [fdo#103232]) -> [PASS][26] [25]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix wrong escape clock divisor init for GLK (rev2)
== Series Details ==
Series: drm/i915: Fix wrong escape clock divisor init for GLK (rev2)
URL : https://patchwork.freedesktop.org/series/63505/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6460 -> Patchwork_13623
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13623/
Known issues
Here are the changes found in Patchwork_13623 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6460/fi-blb-e6850/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13623/fi-blb-e6850/igt@i915_module_l...@reload.html
Possible fixes
* igt@gem_close_race@basic-threads:
- {fi-icl-u4}:[INCOMPLETE][3] ([fdo#107713]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6460/fi-icl-u4/igt@gem_close_r...@basic-threads.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13623/fi-icl-u4/igt@gem_close_r...@basic-threads.html
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [INCOMPLETE][5] ([fdo#111050]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6460/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13623/fi-skl-iommu/igt@i915_selftest@live_contexts.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
Participating hosts (50 -> 47)
--
Additional (2): fi-icl-u3 fi-apl-guc
Missing(5): fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6460 -> Patchwork_13623
CI_DRM_6460: 32d52650873db547f6702f12ebdbae3e8e052dad @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5094: d7f140b5b02d054183a74842b4579cf7f5533927 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13623: a0b1ea18d27c9e818358a60789c8c472c0e3a0ff @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13623/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
a0b1ea18d27c drm/i915: Fix wrong escape clock divisor init for GLK
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13623/
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Join quoted strings and align them with open parenthesis
== Series Details == Series: drm/i915: Join quoted strings and align them with open parenthesis URL : https://patchwork.freedesktop.org/series/63510/ State : success == Summary == CI Bug Log - changes from CI_DRM_6451_full -> Patchwork_13605_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13605_full that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@mock_fence: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-iclb5/igt@i915_selftest@mock_fence.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13605/shard-iclb7/igt@i915_selftest@mock_fence.html * igt@i915_suspend@debugfs-reader: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-apl1/igt@i915_susp...@debugfs-reader.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13605/shard-apl6/igt@i915_susp...@debugfs-reader.html * igt@kms_atomic_transition@1x-modeset-transitions: - shard-hsw: [PASS][5] -> [INCOMPLETE][6] ([fdo#103540]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-hsw5/igt@kms_atomic_transit...@1x-modeset-transitions.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13605/shard-hsw2/igt@kms_atomic_transit...@1x-modeset-transitions.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-kbl4/igt@kms_f...@flip-vs-suspend-interruptible.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13605/shard-kbl3/igt@kms_f...@flip-vs-suspend-interruptible.html - shard-snb: [PASS][9] -> [DMESG-WARN][10] ([fdo#102365]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-snb5/igt@kms_f...@flip-vs-suspend-interruptible.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13605/shard-snb2/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +6 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-iclb5/igt@kms_frontbuffer_track...@fbc-rgb565-draw-pwrite.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13605/shard-iclb7/igt@kms_frontbuffer_track...@fbc-rgb565-draw-pwrite.html * igt@kms_psr2_su@page_flip: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109642] / [fdo#111068]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-iclb2/igt@kms_psr2_su@page_flip.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13605/shard-iclb4/igt@kms_psr2_su@page_flip.html Possible fixes * igt@gem_eio@reset-stress: - shard-snb: [FAIL][15] ([fdo#109661]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-snb1/igt@gem_...@reset-stress.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13605/shard-snb7/igt@gem_...@reset-stress.html * igt@gem_exec_flush@basic-wb-ro-default: - shard-apl: [INCOMPLETE][17] ([fdo#103927]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-apl3/igt@gem_exec_fl...@basic-wb-ro-default.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13605/shard-apl1/igt@gem_exec_fl...@basic-wb-ro-default.html * igt@i915_suspend@sysfs-reader: - shard-apl: [DMESG-WARN][19] ([fdo#108566]) -> [PASS][20] +5 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-apl7/igt@i915_susp...@sysfs-reader.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13605/shard-apl7/igt@i915_susp...@sysfs-reader.html * igt@kms_color@pipe-c-ctm-green-to-red: - shard-skl: [FAIL][21] ([fdo#107201]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-skl8/igt@kms_co...@pipe-c-ctm-green-to-red.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13605/shard-skl10/igt@kms_co...@pipe-c-ctm-green-to-red.html * igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled: - shard-skl: [FAIL][23] ([fdo#103184] / [fdo#103232]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6451/shard-skl5/igt@kms_draw_...@draw-method-rgb565-mmap-wc-ytiled.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13605/shard-skl9/igt@kms_draw_...@draw-method-rgb565-mmap-wc-ytiled.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-glk: [FAIL][25] ([fdo#105363]) -> [PASS][26] +2 similar issues [25]:
Re: [Intel-gfx] [PATCH] drm/i915/guc: Drop redundant ctx param from kerenldoc
On 7/11/19 9:24 AM, Chris Wilson wrote: drivers/gpu/drm/i915/intel_guc_submission.c:799: warning: Excess function parameter 'ctx' description in 'guc_client_alloc' Signed-off-by: Chris Wilson Cc: Daniele Ceraolo Spurio Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/intel_guc_submission.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c index 30692f8289bd..b663b5fe51a8 100644 --- a/drivers/gpu/drm/i915/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/intel_guc_submission.c @@ -789,8 +789,6 @@ static bool guc_verify_doorbells(struct intel_guc *guc) *The kernel client to replace ExecList submission is created with *NORMAL priority. Priority of a client for scheduler can be HIGH, *while a preemption context can use CRITICAL. - * @ctx: the context that owns the client (we use the default render - * context) * * Return:An intel_guc_client object if success, else NULL. */ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 17/23] drm/ast: Provide ddc symlink in connector sysfs directory
Acked-by: Thomas Zimmermann
Am 11.07.19 um 13:26 schrieb Andrzej Pietrasiewicz:
> Use the ddc pointer provided by the generic connector.
>
> Signed-off-by: Andrzej Pietrasiewicz
> ---
> drivers/gpu/drm/ast/ast_mode.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c
> index ffccbef962a4..1ca9bc4aa3bb 100644
> --- a/drivers/gpu/drm/ast/ast_mode.c
> +++ b/drivers/gpu/drm/ast/ast_mode.c
> @@ -890,6 +890,11 @@ static int ast_connector_init(struct drm_device *dev)
> return -ENOMEM;
>
> connector = _connector->base;
> + ast_connector->i2c = ast_i2c_create(dev);
> + if (!ast_connector->i2c)
> + DRM_ERROR("failed to add ddc bus for connector\n");
> +
> + connector->ddc = _connector->i2c->adapter;
> drm_connector_init(dev, connector, _connector_funcs,
> DRM_MODE_CONNECTOR_VGA);
>
> drm_connector_helper_add(connector, _connector_helper_funcs);
> @@ -904,10 +909,6 @@ static int ast_connector_init(struct drm_device *dev)
> encoder = list_first_entry(>mode_config.encoder_list, struct
> drm_encoder, head);
> drm_connector_attach_encoder(connector, encoder);
>
> - ast_connector->i2c = ast_i2c_create(dev);
> - if (!ast_connector->i2c)
> - DRM_ERROR("failed to add ddc bus for connector\n");
> -
> return 0;
> }
>
>
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Linux GmbH, Maxfeldstrasse 5, 90409 Nuernberg, Germany
GF: Felix Imendörffer, Mary Higgins, Sri Rasiah
HRB 21284 (AG Nürnberg)
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Re: [Intel-gfx] [PATCH v4 16/23] drm/mgag200: Provide ddc symlink in connector sysfs directory
Acked-by: Thomas Zimmermann
Am 11.07.19 um 13:26 schrieb Andrzej Pietrasiewicz:
> Use the ddc pointer provided by the generic connector.
>
> Signed-off-by: Andrzej Pietrasiewicz
> ---
> drivers/gpu/drm/mgag200/mgag200_mode.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c
> b/drivers/gpu/drm/mgag200/mgag200_mode.c
> index a25054015e8c..8fb9444b2142 100644
> --- a/drivers/gpu/drm/mgag200/mgag200_mode.c
> +++ b/drivers/gpu/drm/mgag200/mgag200_mode.c
> @@ -1703,6 +1703,11 @@ static struct drm_connector *mga_vga_init(struct
> drm_device *dev)
> return NULL;
>
> connector = _connector->base;
> + mga_connector->i2c = mgag200_i2c_create(dev);
> + if (!mga_connector->i2c)
> + DRM_ERROR("failed to add ddc bus\n");
> +
> + connector->ddc = _connector->i2c->adapter;
>
> drm_connector_init(dev, connector,
> _vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
> @@ -1711,10 +1716,6 @@ static struct drm_connector *mga_vga_init(struct
> drm_device *dev)
>
> drm_connector_register(connector);
>
> - mga_connector->i2c = mgag200_i2c_create(dev);
> - if (!mga_connector->i2c)
> - DRM_ERROR("failed to add ddc bus\n");
> -
> return connector;
> }
>
>
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Linux GmbH, Maxfeldstrasse 5, 90409 Nuernberg, Germany
GF: Felix Imendörffer, Mary Higgins, Sri Rasiah
HRB 21284 (AG Nürnberg)
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Re: [Intel-gfx] [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL
On Thu, Jul 11, 2019 at 04:47:17PM +0300, Ville Syrjälä wrote:
> On Wed, Jul 10, 2019 at 04:09:21PM -0700, Anusha Srivatsa wrote:
> > DSC engine on ICL supports only 8 and 10 BPC as the input
> > BPC. But DSC engine in TGL supports 8, 10 and 12 BPC.
> > Add 12 BPC support for DSC while calculating compression
> > configuration.
> >
> > Cc: Manasi Navare
> > Signed-off-by: Anusha Srivatsa
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 9 +++--
> > 1 file changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 0bdb7ecc5a81..cd089643c80d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -71,6 +71,7 @@
> > #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
> > #define DP_DSC_MIN_SUPPORTED_BPC 8
> > #define DP_DSC_MAX_SUPPORTED_BPC 10
> > +#define TGL_DP_DSC_MAX_SUPPORTED_BPC 12
>
> These defines aren't doing any good IMO. I'd just nuke them.
So just remove all the #defines and use the values directly?
>
> >
> > /* DP DSC throughput values used for slice count calculations KPixels/s */
> > #define DP_DSC_PEAK_PIXEL_RATE 272
> > @@ -1911,8 +1912,12 @@ static int intel_dp_dsc_compute_config(struct
> > intel_dp *intel_dp,
> > if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> > return -EINVAL;
> >
> > - dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> > - conn_state->max_requested_bpc);
> > + if (INTEL_GEN(dev_priv) > 11)
>
> More customarily >= 12
I agree
Manasi
>
> > + dsc_max_bpc = min_t(u8, TGL_DP_DSC_MAX_SUPPORTED_BPC,
> > + conn_state->max_requested_bpc);
> > + else
> > + dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> > + conn_state->max_requested_bpc);
> >
> > pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
> > if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
> > --
> > 2.21.0
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH] drm/i915: Don't overestimate 4:2:0 link symbol clock
On Wed, 2019-07-10 at 15:58 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> With 4:2:0 output the LS clock can be half of what it is with 4:4:4.
> Make that happen.
>
> Cc: Gwan-gyeong Mun
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0bdb7ecc5a81..1dfacf090fb8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1853,8 +1853,10 @@ intel_dp_compute_link_config_wide(struct
> intel_dp *intel_dp,
> int mode_rate, link_clock, link_avail;
>
> for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 *
> 3) {
> + int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
> +
> mode_rate = intel_dp_link_required(adjusted_mode-
> >crtc_clock,
> -bpp);
> +output_bpp);
>
> for (clock = limits->min_clock; clock <= limits-
> >max_clock; clock++) {
> for (lane_count = limits->min_lane_count;
According to DP 1.4 spec section 1.7.1 [Makeup of the Main-Link],
previous implementation worked by below explaination.
After the stream data is packed and mapped to the Main-Link, the packed
stream data rate shall be less than or equal to the Main-Link’s link
symbol rate. When the packed stream data rate is less than the Main-
Link’s link symbol rate, stuffing symbols are inserted.
Reviewed-by: Gwan-gyeong Mun
Tested-by: Gwan-gyeong Mun
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Re: [Intel-gfx] [PATCH v2] drm/i915: Fix wrong escape clock divisor init for GLK
On Thu, Jul 11, 2019 at 01:44:01PM +0300, Stanislav Lisovskiy wrote:
> According to Bspec clock divisor registers in GeminiLake
> should be initialized by shifting 1(<<) to amount of correspondent
> divisor. While i915 was writing all this time that value as is.
>
> Surprisingly that it by accident worked, until we met some issues
> with Microtech Etab.
>
> v2: Added Fixes tag and cc
>
> Signed-off-by: stanislav.lisovs...@intel.com
Your git is a bit misconfigured
-:46: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal
patch author 'Stanislav Lisovskiy '
And I think we want cc:stable on this as well.
> Reviewed-by: Vandita Kulkarni
> Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=108826
> Fixes: bcc657004841 ("drm/i915/glk: Program txesc clock divider for GLK")
> Cc: Deepak M
> Cc: Madhav Chauhan
> Cc: Jani Nikula
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Cc: intel-gfx@lists.freedesktop.org
> ---
> drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> index 99cc3e2e9c2c..f016a776a39e 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> @@ -396,8 +396,8 @@ static void glk_dsi_program_esc_clock(struct drm_device
> *dev,
> else
> txesc2_div = 10;
>
> - I915_WRITE(MIPIO_TXESC_CLK_DIV1, txesc1_div & GLK_TX_ESC_CLK_DIV1_MASK);
> - I915_WRITE(MIPIO_TXESC_CLK_DIV2, txesc2_div & GLK_TX_ESC_CLK_DIV2_MASK);
> + I915_WRITE(MIPIO_TXESC_CLK_DIV1, (1 << (txesc1_div - 1)) &
> GLK_TX_ESC_CLK_DIV1_MASK);
> + I915_WRITE(MIPIO_TXESC_CLK_DIV2, (1 << (txesc2_div - 1)) &
> GLK_TX_ESC_CLK_DIV2_MASK);
> }
>
> /* Program BXT Mipi clocks and dividers */
> --
> 2.17.1
--
Ville Syrjälä
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/edid: Add new modes from CTA-861-G
== Series Details ==
Series: drm/edid: Add new modes from CTA-861-G
URL : https://patchwork.freedesktop.org/series/63554/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6458 -> Patchwork_13622
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13622/
Known issues
Here are the changes found in Patchwork_13622 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6458/fi-blb-e6850/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13622/fi-blb-e6850/igt@i915_module_l...@reload.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [PASS][3] -> [DMESG-FAIL][4] ([fdo#08])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6458/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13622/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_sanitycheck:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6458/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13622/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html
Possible fixes
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [FAIL][7] ([fdo#108511]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6458/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13622/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
Participating hosts (53 -> 46)
--
Missing(7): fi-kbl-soraka fi-byt-j1900 fi-byt-squawks fi-bsw-cyan
fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6458 -> Patchwork_13622
CI_DRM_6458: fe4d1459b31768c40f907bb859f25197e1af2d07 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5093: 86dc48ede7c33bf69e15f84179d2f9e5b84c179b @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13622: edc08ee6d32bca5ba5976780de3119ff94822617 @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13622/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
edc08ee6d32b drm/edid: Make sure the CEA mode arrays have the correct amount of
modes
252fbde36820 drm/edid: Throw away the dummy VIC 0 cea mode
72a1da8ed5f6 drm/edid: Add CTA-861-G modes with VIC >= 193
1616f2361bc5 drm/edid: Abstract away cea_edid_modes[]
04c1e8935b2a drm/edid: Add CTA-861-G modes with VIC < 128
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13622/
___
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[Intel-gfx] [PATCH] drm/i915/guc: Drop redundant ctx param from kerenldoc
drivers/gpu/drm/i915/intel_guc_submission.c:799: warning: Excess function parameter 'ctx' description in 'guc_client_alloc' Signed-off-by: Chris Wilson Cc: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/intel_guc_submission.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c index 30692f8289bd..b663b5fe51a8 100644 --- a/drivers/gpu/drm/i915/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/intel_guc_submission.c @@ -789,8 +789,6 @@ static bool guc_verify_doorbells(struct intel_guc *guc) * The kernel client to replace ExecList submission is created with * NORMAL priority. Priority of a client for scheduler can be HIGH, * while a preemption context can use CRITICAL. - * @ctx: the context that owns the client (we use the default render - * context) * * Return: An intel_guc_client object if success, else NULL. */ -- 2.22.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Vulkan performance query support (rev9)
== Series Details ==
Series: drm/i915: Vulkan performance query support (rev9)
URL : https://patchwork.freedesktop.org/series/60916/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6458 -> Patchwork_13621
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13621/
Known issues
Here are the changes found in Patchwork_13621 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [PASS][1] -> [DMESG-FAIL][2] ([fdo#08])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6458/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13621/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
Possible fixes
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [FAIL][3] ([fdo#108511]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6458/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13621/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [INCOMPLETE][5] ([fdo#111050]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6458/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13621/fi-skl-iommu/igt@i915_selftest@live_contexts.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [FAIL][7] ([fdo#103167]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6458/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13621/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
Participating hosts (53 -> 47)
--
Missing(6): fi-kbl-soraka fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6458 -> Patchwork_13621
CI_DRM_6458: fe4d1459b31768c40f907bb859f25197e1af2d07 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5093: 86dc48ede7c33bf69e15f84179d2f9e5b84c179b @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13621: 1e247fc1940038de320c65afa25b6fdba48ad9e1 @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13621/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
AR drivers/gpu/drm/i915/built-in.a
CC [M] drivers/gpu/drm/i915/header_test_i915_active_types.o
CC [M] drivers/gpu/drm/i915/header_test_i915_debugfs.o
CC [M] drivers/gpu/drm/i915/header_test_i915_drv.o
CC [M] drivers/gpu/drm/i915/header_test_i915_fixed.o
CC [M] drivers/gpu/drm/i915/header_test_i915_gem_gtt.o
CC [M] drivers/gpu/drm/i915/header_test_i915_globals.o
CC [M] drivers/gpu/drm/i915/header_test_i915_irq.o
CC [M] drivers/gpu/drm/i915/header_test_i915_params.o
CC [M] drivers/gpu/drm/i915/header_test_i915_priolist_types.o
CC [M] drivers/gpu/drm/i915/header_test_i915_pvinfo.o
CC [M] drivers/gpu/drm/i915/header_test_i915_reg.o
CC [M] drivers/gpu/drm/i915/header_test_i915_scheduler_types.o
CC [M] drivers/gpu/drm/i915/header_test_i915_utils.o
CC [M] drivers/gpu/drm/i915/header_test_i915_vgpu.o
CC [M] drivers/gpu/drm/i915/header_test_intel_csr.o
CC [M] drivers/gpu/drm/i915/header_test_intel_drv.o
CC [M] drivers/gpu/drm/i915/header_test_intel_guc_ct.o
CC [M] drivers/gpu/drm/i915/header_test_intel_guc_fwif.o
CC [M] drivers/gpu/drm/i915/header_test_intel_guc_reg.o
CC [M] drivers/gpu/drm/i915/header_test_intel_gvt.o
CC [M] drivers/gpu/drm/i915/header_test_intel_pm.o
CC [M] drivers/gpu/drm/i915/header_test_intel_runtime_pm.o
CC [M] drivers/gpu/drm/i915/header_test_intel_sideband.o
CC [M] drivers/gpu/drm/i915/header_test_intel_uc_fw.o
CC [M] drivers/gpu/drm/i915/header_test_intel_uncore.o
CC [M] drivers/gpu/drm/i915/header_test_intel_wakeref.o
CC [M] drivers/gpu/drm/i915/i915_debugfs.o
drivers/gpu/drm/i915/i915_debugfs.c: In function ‘i915_perf_noa_delay_set’:
drivers/gpu/drm/i915/i915_debugfs.c:3659:18: error: left shift count >= width
of type [-Werror=shift-count-overflow]
if (val > ((1ul << 32) - 1) *
Re: [Intel-gfx] [PATCH] drm/i915: Use the "display core" power domain in vlv/chv set_cdclk()
On Mon, Jul 01, 2019 at 07:15:34PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > The PFI credit programming performed during cdclk change on vlv/chv > requires access to a register in the disp2d power well. So far > we've abused pipe-A power domain for this, but now we have the > more appropriate "display core" domain so let's make use of it. > > Signed-off-by: Ville Syrjälä Reviewed-by: Imre Deak > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 12 ++-- > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c > b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 0b8b8ae3b7fc..d0581a1ac243 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -545,10 +545,10 @@ static void vlv_set_cdclk(struct drm_i915_private > *dev_priv, > /* There are cases where we can end up here with power domains >* off and a CDCLK frequency other than the minimum, like when >* issuing a modeset without actually changing any display after > - * a system suspend. So grab the PIPE-A domain, which covers > + * a system suspend. So grab the display core domain, which covers >* the HW blocks needed for the following programming. >*/ > - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); > + wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); > > vlv_iosf_sb_get(dev_priv, > BIT(VLV_IOSF_SB_CCK) | > @@ -606,7 +606,7 @@ static void vlv_set_cdclk(struct drm_i915_private > *dev_priv, > > vlv_program_pfi_credits(dev_priv); > > - intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A, wakeref); > + intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); > } > > static void chv_set_cdclk(struct drm_i915_private *dev_priv, > @@ -631,10 +631,10 @@ static void chv_set_cdclk(struct drm_i915_private > *dev_priv, > /* There are cases where we can end up here with power domains >* off and a CDCLK frequency other than the minimum, like when >* issuing a modeset without actually changing any display after > - * a system suspend. So grab the PIPE-A domain, which covers > + * a system suspend. So grab the display core domain, which covers >* the HW blocks needed for the following programming. >*/ > - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); > + wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); > > vlv_punit_get(dev_priv); > val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); > @@ -653,7 +653,7 @@ static void chv_set_cdclk(struct drm_i915_private > *dev_priv, > > vlv_program_pfi_credits(dev_priv); > > - intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A, wakeref); > + intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); > } > > static int bdw_calc_cdclk(int min_cdclk) > -- > 2.21.0 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/6] drm/i915: Check crtc_state->wm.need_postvbl_update before grabbing wm.mutex
On Mon, Jul 01, 2019 at 07:05:45PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> wm.mutex does not protect the crtc state so no point in grabbing it
> to check crtc_state->wm.need_postvbl_update.
>
> Also do a bit of s/intel_crtc/crtc/ while at it.
>
> Signed-off-by: Ville Syrjälä
Looks ok, on patches 1-6:
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/intel_pm.c | 23 ---
> 1 file changed, 12 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d10c62d3f10c..807a078690d5 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1566,13 +1566,13 @@ static void g4x_optimize_watermarks(struct
> intel_atomic_state *state,
> struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>
> if (!crtc_state->wm.need_postvbl_update)
> return;
>
> mutex_lock(_priv->wm.wm_mutex);
> - intel_crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
> + crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
> g4x_program_watermarks(dev_priv);
> mutex_unlock(_priv->wm.wm_mutex);
> }
> @@ -2185,13 +2185,13 @@ static void vlv_optimize_watermarks(struct
> intel_atomic_state *state,
> struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>
> if (!crtc_state->wm.need_postvbl_update)
> return;
>
> mutex_lock(_priv->wm.wm_mutex);
> - intel_crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
> + crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
> vlv_program_watermarks(dev_priv);
> mutex_unlock(_priv->wm.wm_mutex);
> }
> @@ -5723,10 +5723,10 @@ static void ilk_initial_watermarks(struct
> intel_atomic_state *state,
> struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>
> mutex_lock(_priv->wm.wm_mutex);
> - intel_crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
> + crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
> ilk_program_watermarks(dev_priv);
> mutex_unlock(_priv->wm.wm_mutex);
> }
> @@ -5735,13 +5735,14 @@ static void ilk_optimize_watermarks(struct
> intel_atomic_state *state,
> struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +
> + if (!crtc_state->wm.need_postvbl_update)
> + return;
>
> mutex_lock(_priv->wm.wm_mutex);
> - if (crtc_state->wm.need_postvbl_update) {
> - intel_crtc->wm.active.ilk = crtc_state->wm.ilk.optimal;
> - ilk_program_watermarks(dev_priv);
> - }
> + crtc->wm.active.ilk = crtc_state->wm.ilk.optimal;
> + ilk_program_watermarks(dev_priv);
> mutex_unlock(_priv->wm.wm_mutex);
> }
>
> --
> 2.21.0
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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