Re: [Intel-gfx] [PATCH 3/4] dma-fence: Refactor signaling for manual invocation
Am 12.08.19 um 16:53 schrieb Chris Wilson: > Quoting Koenig, Christian (2019-08-12 15:50:59) >> Am 12.08.19 um 16:43 schrieb Chris Wilson: >>> Quoting Koenig, Christian (2019-08-12 15:34:32) Am 10.08.19 um 17:34 schrieb Chris Wilson: > Move the duplicated code within dma-fence.c into the header for wider > reuse. In the process apply a small micro-optimisation to only prune the > fence->cb_list once rather than use list_del on every entry. > > Signed-off-by: Chris Wilson > Cc: Tvrtko Ursulin > --- > drivers/dma-buf/Makefile| 10 +- > drivers/dma-buf/dma-fence-trace.c | 28 +++ > drivers/dma-buf/dma-fence.c | 33 +-- > drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 32 +-- > include/linux/dma-fence-impl.h | 83 +++ > include/linux/dma-fence-types.h | 258 > include/linux/dma-fence.h | 228 + Mhm, I don't really see the value in creating more header files. Especially I'm pretty sure that the types should stay in dma-fence.h >>> iirc, when I included the trace.h from dma-fence.h or dma-fence-impl.h >>> without separating the types, amdgpu failed to compile (which is more >>> than likely to be simply due to be first drm in the list to compile). >> Ah, but why do you want to include trace.h in a header in the first place? >> >> That's usually not something I would recommend either. > The problem is that we do emit a tracepoint as part of the sequence I > want to put into the reusable chunk of code. Ok, we are going in circles here. Why do you want to reuse the code then? Christian. > -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: drop engine_pin/unpin_breadcrumbs_irq
Quoting Daniele Ceraolo Spurio (2019-08-13 00:31:51) > The last user has been removed, so drop the functions. > > Signed-off-by: Daniele Ceraolo Spurio > Cc: Chris Wilson If this sticks, we can remove the b->irq_enabled counter (iirc). For the moment, keep it simple in case we need to revive it for gvt/pv. Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 3/9] i915/gem_mmap_gtt: Test mmap_offset lifetime
Closing the object on another file should not affect the local
mmap_offset.
Signed-off-by: Chris Wilson
Cc: Abdiel Janulgue
---
tests/i915/gem_mmap_gtt.c | 40 +++
1 file changed, 40 insertions(+)
diff --git a/tests/i915/gem_mmap_gtt.c b/tests/i915/gem_mmap_gtt.c
index 6f3a9c36e..8eff91850 100644
--- a/tests/i915/gem_mmap_gtt.c
+++ b/tests/i915/gem_mmap_gtt.c
@@ -322,6 +322,44 @@ test_pf_nonblock(int i915)
igt_spin_free(i915, spin);
}
+static void
+test_isolation(int i915)
+{
+ struct drm_i915_gem_mmap_gtt mmap_arg;
+ int A = gem_reopen_driver(i915);
+ int B = gem_reopen_driver(i915);
+ uint64_t offset_a, offset_b;
+ uint32_t a, b;
+ void *ptr;
+
+ a = gem_create(A, 4096);
+ b = gem_open(B, gem_flink(A, a));
+
+ mmap_arg.handle = a;
+ do_ioctl(A, DRM_IOCTL_I915_GEM_MMAP_GTT, &mmap_arg);
+ offset_a = mmap_arg.offset;
+
+ mmap_arg.handle = b;
+ do_ioctl(B, DRM_IOCTL_I915_GEM_MMAP_GTT, &mmap_arg);
+ offset_b = mmap_arg.offset;
+
+ igt_info("A: {fd:%d, handle:%d, offset:%"PRIx64"}\n",
+A, a, offset_a);
+ igt_info("B: {fd:%d, handle:%d, offset:%"PRIx64"}\n",
+B, b, offset_b);
+
+ close(B);
+
+ ptr = mmap64(0, 4096, PROT_READ, MAP_SHARED, A, offset_a);
+ igt_assert(ptr != MAP_FAILED);
+ munmap(ptr, 4096);
+
+ close(A);
+
+ ptr = mmap64(0, 4096, PROT_READ, MAP_SHARED, A, offset_a);
+ igt_assert(ptr == MAP_FAILED);
+}
+
static void
test_write_gtt(int fd)
{
@@ -945,6 +983,8 @@ igt_main
test_write_cpu_read_gtt(fd);
igt_subtest("basic-wc")
test_wc(fd);
+ igt_subtest("isolation")
+ test_isolation(fd);
igt_subtest("pf-nonblock")
test_pf_nonblock(fd);
--
2.23.0.rc1
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[Intel-gfx] [PATCH i-g-t 6/9] i915/gem_exec_schedule: Check timeslice
Check that we can run a second request even if an equal priority spinner
is hogging the engine.
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Cc: Tvrtko Ursulin
---
tests/i915/gem_exec_schedule.c | 36 ++
1 file changed, 36 insertions(+)
diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index 058102103..04cede9c9 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -1033,6 +1033,39 @@ static void preempt_queue(int fd, unsigned ring,
unsigned int flags)
}
}
+static void preempt_timeslice(int fd, unsigned ring)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ struct drm_i915_gem_exec_object2 obj = {
+ .handle = gem_create(fd, 4096)
+ };
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(&obj),
+ .buffer_count = 1,
+ .flags = ring,
+ .rsvd1 = gem_context_create(fd),
+ };
+ igt_spin_t *spin;
+
+ /*
+* Launch a spinner to occupy the target engine, and then
+* check we execute a ping underneath it from a second context.
+*/
+ spin = igt_spin_new(fd, .engine = ring, .flags = IGT_SPIN_POLL_RUN);
+ igt_spin_busywait_until_started(spin);
+
+ /* Both the active spinner and this are at the same priority */
+ gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
+ gem_execbuf(fd, &execbuf);
+ gem_sync(fd, obj.handle);
+
+ igt_assert(gem_bo_busy(fd, spin->handle));
+ igt_spin_free(fd, spin);
+
+ gem_context_destroy(fd, execbuf.rsvd1);
+ gem_close(fd, obj.handle);
+}
+
static void preempt_self(int fd, unsigned ring)
{
uint32_t result = gem_create(fd, 4096);
@@ -1740,6 +1773,9 @@ igt_main
igt_subtest_f("preempt-queue-contexts-chain-%s", e->name)
preempt_queue(fd, e->exec_id |
e->flags, CONTEXTS | CHAIN);
+ igt_subtest_f("preempt-timeslice-%s",
e->name)
+ preempt_timeslice(fd,
e->exec_id | e->flags);
+
igt_subtest_group {
igt_hang_t hang;
--
2.23.0.rc1
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[Intel-gfx] [PATCH i-g-t 7/9] i915/perf_pmu: Flush idle work before waiting for suspend
Runtime suspend kicks in quicker if we flush any idle work that may been accrued. Signed-off-by: Chris Wilson --- tests/perf_pmu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c index d392a67d4..351090710 100644 --- a/tests/perf_pmu.c +++ b/tests/perf_pmu.c @@ -1417,6 +1417,7 @@ test_rc6(int gem_fd, unsigned int flags) drmModeFreeResources(res); igt_require(igt_setup_runtime_pm()); + igt_drop_caches_set(gem_fd, DROP_IDLE); igt_require(igt_wait_for_pm_status(IGT_RUNTIME_PM_STATUS_SUSPENDED)); /* -- 2.23.0.rc1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 2/9] i915/gem_eio: Restrict number of batches of submitted
Make sure we don't block while setting up the stress case before the reset by only submitting less batches than would fill the ring. References: https://bugs.freedesktop.org/show_bug.cgi?id=111379 Signed-off-by: Chris Wilson --- tests/i915/gem_eio.c | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/tests/i915/gem_eio.c b/tests/i915/gem_eio.c index dcbcefa97..9b086a039 100644 --- a/tests/i915/gem_eio.c +++ b/tests/i915/gem_eio.c @@ -734,6 +734,11 @@ static void reset_stress(int fd, uint32_t ctx0, .flags = engine, }; igt_stats_t stats; + int max; + + max = gem_measure_ring_inflight(fd, engine, 0); + max = max / 2 - 1; /* assume !execlists and a shared ring */ + igt_require(max > 0); gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe)); @@ -755,11 +760,11 @@ static void reset_stress(int fd, uint32_t ctx0, hang = spin_sync(fd, ctx0, engine); execbuf.rsvd1 = ctx; - for (i = 0; i < 10; i++) + for (i = 0; i < max; i++) gem_execbuf(fd, &execbuf); execbuf.rsvd1 = ctx0; - for (i = 0; i < 10; i++) + for (i = 0; i < max; i++) gem_execbuf(fd, &execbuf); /* Wedge after a small delay. */ @@ -777,11 +782,11 @@ static void reset_stress(int fd, uint32_t ctx0, * both contexts. */ execbuf.rsvd1 = ctx; - for (i = 0; i < 5; i++) + for (i = 0; i < max; i++) gem_execbuf(fd, &execbuf); execbuf.rsvd1 = ctx0; - for (i = 0; i < 5; i++) + for (i = 0; i < max; i++) gem_execbuf(fd, &execbuf); gem_sync(fd, obj.handle); -- 2.23.0.rc1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 9/9] i915/gem_ctx_engine: Drip feed requests into 'independent'
The intent of the test is to exercise that each channel in the engine[]
is an independent context/ring/timeline. It setups 64 channels pointing
to rcs0 and then submits one request to each in turn waiting on a
timeline that will force them to run out of submission order. They can
only run in fence order and not submission order if the timelines of
each channel are truly independent.
However, we released the fences en masse, and once the requests are
ready they are independent any may be executed in any order by the HW,
especially true with timeslicing that may reorder the requests on a
whim. So instead of releasing all requests at once, increment the
timeline step by step and check we get our results advancing. If the
requests can not be run in fence order and fall back to submission
order, we will time out waiting for our incremental results and trigger
a few GPU hangs.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110987
Signed-off-by: Chris Wilson
---
tests/i915/gem_ctx_engines.c | 39 +++-
1 file changed, 29 insertions(+), 10 deletions(-)
diff --git a/tests/i915/gem_ctx_engines.c b/tests/i915/gem_ctx_engines.c
index 8c66fb261..2e80d0f3e 100644
--- a/tests/i915/gem_ctx_engines.c
+++ b/tests/i915/gem_ctx_engines.c
@@ -405,6 +405,14 @@ static void execute_allforone(int i915)
gem_context_destroy(i915, param.ctx_id);
}
+static uint32_t read_result(int timeline, uint32_t *map, int idx)
+{
+ sw_sync_timeline_inc(timeline, 1);
+ while (!READ_ONCE(map[idx]))
+ ;
+ return map[idx];
+}
+
static void independent(int i915)
{
#define RCS_TIMESTAMP (0x2000 + 0x358)
@@ -438,6 +446,12 @@ static void independent(int i915)
memset(&engines, 0, sizeof(engines)); /* All rcs0 */
gem_context_set_param(i915, ¶m);
+ gem_set_caching(i915, results.handle, I915_CACHING_CACHED);
+ map = gem_mmap__cpu(i915, results.handle, 0, 4096, PROT_READ);
+ gem_set_domain(i915, results.handle,
+ I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
+ memset(map, 0, 4096);
+
for (int i = 0; i < I915_EXEC_RING_MASK + 1; i++) {
struct drm_i915_gem_exec_object2 obj[2] = {
results, /* write hazard lies! */
@@ -472,21 +486,21 @@ static void independent(int i915)
gem_close(i915, obj[1].handle);
close(execbuf.rsvd2);
}
- close(timeline);
- gem_sync(i915, results.handle);
-
- map = gem_mmap__cpu(i915, results.handle, 0, 4096, PROT_READ);
- gem_set_domain(i915, results.handle, I915_GEM_DOMAIN_CPU, 0);
- gem_close(i915, results.handle);
- last = map[0];
+ last = read_result(timeline, map, 0);
for (int i = 1; i < I915_EXEC_RING_MASK + 1; i++) {
- igt_assert_f((map[i] - last) > 0,
-"Engine instance [%d] executed too late\n", i);
- last = map[i];
+ uint32_t t = read_result(timeline, map, i);
+ igt_assert_f(t - last > 0,
+"Engine instance [%d] executed too late, previous
timestamp %08x, now %08x\n",
+i, last, t);
+ last = t;
}
munmap(map, 4096);
+ close(timeline);
+ gem_sync(i915, results.handle);
+ gem_close(i915, results.handle);
+
gem_context_destroy(i915, param.ctx_id);
}
@@ -500,6 +514,8 @@ igt_main
gem_require_contexts(i915);
igt_require(has_context_engines(i915));
+
+ igt_fork_hang_detector(i915);
}
igt_subtest("invalid-engines")
@@ -519,4 +535,7 @@ igt_main
igt_subtest("independent")
independent(i915);
+
+ igt_fixture
+ igt_stop_hang_detector();
}
--
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[Intel-gfx] [PATCH i-g-t 1/9] i915/gem_exec_schedule: Limit the plug to fit small rings
If we are not running with a scheduler, we are using a global ringbuffer
which may not accommodate 16 extra batches. Fortunately, we only need
one such batch to block the submission queue as without a scheduler, it
is in order submission (and so the batch is after the main setup
anyway!).
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_schedule.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index 6e8466299..058102103 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -164,8 +164,13 @@ static uint32_t create_highest_priority(int fd)
static void unplug_show_queue(int fd, struct igt_cork *c, unsigned int engine)
{
igt_spin_t *spin[MAX_ELSP_QLEN];
+ int max = MAX_ELSP_QLEN;
- for (int n = 0; n < ARRAY_SIZE(spin); n++) {
+ /* If no scheduler, all batches are emitted in submission order */
+ if (!gem_scheduler_enabled(fd))
+ max = 1;
+
+ for (int n = 0; n < max; n++) {
const struct igt_spin_factory opts = {
.ctx = create_highest_priority(fd),
.engine = engine,
@@ -177,7 +182,7 @@ static void unplug_show_queue(int fd, struct igt_cork *c,
unsigned int engine)
igt_cork_unplug(c); /* batches will now be queued on the engine */
igt_debugfs_dump(fd, "i915_engine_info");
- for (int n = 0; n < ARRAY_SIZE(spin); n++)
+ for (int n = 0; n < max; n++)
igt_spin_free(fd, spin[n]);
}
--
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[Intel-gfx] [PATCH i-g-t 8/9] Force spin-batch to cause a hang as required
When using a spinner to trigger a hang, make it unpreemptable so that it
appears like a true hang.
References: https://bugs.freedesktop.org/show_bug.cgi?id=109661
Signed-off-by: Chris Wilson
---
tests/i915/gem_eio.c| 4 +++-
tests/i915/gem_exec_fence.c | 3 ++-
tests/kms_busy.c| 3 ++-
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/tests/i915/gem_eio.c b/tests/i915/gem_eio.c
index 9b086a039..a783b7bff 100644
--- a/tests/i915/gem_eio.c
+++ b/tests/i915/gem_eio.c
@@ -176,7 +176,9 @@ static igt_spin_t * __spin_poll(int fd, uint32_t ctx,
unsigned long flags)
struct igt_spin_factory opts = {
.ctx = ctx,
.engine = flags,
- .flags = IGT_SPIN_FAST | IGT_SPIN_FENCE_OUT,
+ .flags = (IGT_SPIN_FAST |
+ IGT_SPIN_NO_PREEMPTION |
+ IGT_SPIN_FENCE_OUT),
};
if (gem_can_store_dword(fd, opts.engine))
diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
index 207182922..2f04d7af4 100644
--- a/tests/i915/gem_exec_fence.c
+++ b/tests/i915/gem_exec_fence.c
@@ -331,7 +331,8 @@ static void test_fence_await(int fd, unsigned ring,
unsigned flags)
spin = igt_spin_new(fd,
.engine = ring,
- .flags = IGT_SPIN_FENCE_OUT);
+ .flags = (IGT_SPIN_FENCE_OUT |
+ IGT_SPIN_NO_PREEMPTION));
igt_assert(spin->out_fence != -1);
i = 0;
diff --git a/tests/kms_busy.c b/tests/kms_busy.c
index 66f26cd08..7e5ab3d19 100644
--- a/tests/kms_busy.c
+++ b/tests/kms_busy.c
@@ -271,7 +271,8 @@ static void test_pageflip_modeset_hang(igt_display_t *dpy,
t = igt_spin_new(dpy->drm_fd,
.engine = ring,
-.dependency = fb.gem_handle);
+.dependency = fb.gem_handle,
+.flags = IGT_SPIN_NO_PREEMPTION);
do_or_die(drmModePageFlip(dpy->drm_fd, dpy->pipes[pipe].crtc_id,
fb.fb_id, DRM_MODE_PAGE_FLIP_EVENT, &fb));
--
2.23.0.rc1
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[Intel-gfx] [PATCH i-g-t 4/9] i915/gem_shrink: Make some pages dirty
Trying to hit a deadlock for invalidating dirty userptr pages (via
kcompactd).
Signed-off-by: Chris Wilson
---
tests/i915/gem_shrink.c | 36
1 file changed, 32 insertions(+), 4 deletions(-)
diff --git a/tests/i915/gem_shrink.c b/tests/i915/gem_shrink.c
index 037ff005b..3db754f55 100644
--- a/tests/i915/gem_shrink.c
+++ b/tests/i915/gem_shrink.c
@@ -45,6 +45,13 @@ static void get_pages(int fd, uint64_t alloc)
gem_madvise(fd, handle, I915_MADV_DONTNEED);
}
+static void get_pages_dirty(int fd, uint64_t alloc)
+{
+ uint32_t handle = gem_create(fd, alloc);
+ gem_set_domain(fd, handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+ gem_madvise(fd, handle, I915_MADV_DONTNEED);
+}
+
static void pwrite_(int fd, uint64_t alloc)
{
uint32_t tmp;
@@ -214,7 +221,8 @@ static void hang(int fd, uint64_t alloc)
munmap(obj, obj_size);
}
-static void userptr(int fd, uint64_t alloc)
+static void userptr(int fd, uint64_t alloc, unsigned int flags)
+#define UDIRTY (1 << 0)
{
struct local_i915_gem_userptr userptr;
void *ptr;
@@ -231,7 +239,11 @@ static void userptr(int fd, uint64_t alloc)
userptr.user_ptr = to_user_pointer(ptr);
do_ioctl(fd, LOCAL_IOCTL_I915_GEM_USERPTR, &userptr);
- gem_set_domain(fd, userptr.handle, I915_GEM_DOMAIN_GTT, 0);
+ if (flags & UDIRTY)
+ gem_set_domain(fd, userptr.handle,
+ I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+ else
+ gem_set_domain(fd, userptr.handle, I915_GEM_DOMAIN_GTT, 0);
madvise(ptr, alloc, MADV_FREE);
}
@@ -273,7 +285,8 @@ static void leak(int fd, uint64_t alloc)
#define SOLO 1
#define USERPTR 2
-#define OOM 4
+#define USERPTR_DIRTY 4
+#define OOM 8
static void run_test(int nchildren, uint64_t alloc,
void (*func)(int, uint64_t), unsigned flags)
@@ -309,7 +322,20 @@ static void run_test(int nchildren, uint64_t alloc,
igt_until_timeout(timeout) {
int fd = drm_open_driver(DRIVER_INTEL);
for (int pass = 0; pass < nchildren; pass++)
- userptr(fd, alloc);
+ userptr(fd, alloc, 0);
+ close(fd);
+ }
+ }
+ nchildren = (nchildren + 1)/2;
+ }
+
+ if (flags & USERPTR_DIRTY) {
+ igt_require(has_userptr());
+ igt_fork(child, (nchildren + 1)/2) {
+ igt_until_timeout(timeout) {
+ int fd = drm_open_driver(DRIVER_INTEL);
+ for (int pass = 0; pass < nchildren; pass++)
+ userptr(fd, alloc, UDIRTY);
close(fd);
}
}
@@ -373,6 +399,7 @@ igt_main
void (*func)(int, uint64_t);
} tests[] = {
{ "get-pages", get_pages },
+ { "get-pages-dirty", get_pages_dirty },
{ "pwrite", pwrite_ },
{ "pread", pread_ },
{ "mmap-gtt", mmap_gtt },
@@ -390,6 +417,7 @@ igt_main
{ "-sanitycheck", SOLO },
{ "", 0 },
{ "-userptr", USERPTR },
+ { "-userptr-dirty", USERPTR | USERPTR_DIRTY },
{ "-oom", USERPTR | OOM },
{ NULL },
};
--
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[Intel-gfx] [PATCH i-g-t 5/9] i915/gem_userptr_blits: Apply some THP pressure
Still trying to hit a deadlock with userptr from kcompatcd.
Signed-off-by: Chris Wilson
---
tests/i915/gem_userptr_blits.c | 49 +-
1 file changed, 42 insertions(+), 7 deletions(-)
diff --git a/tests/i915/gem_userptr_blits.c b/tests/i915/gem_userptr_blits.c
index 1373f160b..5f7770c93 100644
--- a/tests/i915/gem_userptr_blits.c
+++ b/tests/i915/gem_userptr_blits.c
@@ -1662,20 +1662,24 @@ struct stress_thread_data {
static void *mm_stress_thread(void *data)
{
struct stress_thread_data *stdata = (struct stress_thread_data *)data;
+ const size_t sz = 2 << 20;
void *ptr;
- int ret;
while (!stdata->stop) {
- ptr = mmap(NULL, PAGE_SIZE, PROT_READ | PROT_WRITE,
- MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
+ ptr = mmap(NULL, sz, PROT_READ | PROT_WRITE,
+ MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
if (ptr == MAP_FAILED) {
stdata->exit_code = -EFAULT;
break;
}
- ret = munmap(ptr, PAGE_SIZE);
- if (ret) {
- stdata->exit_code = errno;
- break;
+
+ madvise(ptr, sz, MADV_HUGEPAGE);
+ for (size_t page = 0; page < sz; page += PAGE_SIZE)
+ *(volatile uint32_t *)((unsigned char *)ptr + page) = 0;
+
+ if (munmap(ptr, sz)) {
+ stdata->exit_code = errno;
+ break;
}
}
@@ -1713,6 +1717,35 @@ static void test_stress_mm(int fd)
igt_assert_eq(stdata.exit_code, 0);
}
+static void test_stress_purge(int fd)
+{
+ struct stress_thread_data stdata;
+ uint32_t handle;
+ pthread_t t;
+ void *ptr;
+
+ memset(&stdata, 0, sizeof(stdata));
+
+ igt_assert(posix_memalign(&ptr, PAGE_SIZE, PAGE_SIZE) == 0);
+ igt_assert(!pthread_create(&t, NULL, mm_stress_thread, &stdata));
+
+ igt_until_timeout(150) {
+ gem_userptr(fd, ptr, PAGE_SIZE, 0, userptr_flags, &handle);
+
+ gem_set_domain(fd, handle,
+ I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+ intel_purge_vm_caches(fd);
+
+ gem_close(fd, handle);
+ }
+
+ free(ptr);
+
+ stdata.stop = 1;
+ igt_assert(!pthread_join(t, NULL));
+ igt_assert_eq(stdata.exit_code, 0);
+}
+
struct userptr_close_thread_data {
int fd;
void *ptr;
@@ -1975,6 +2008,8 @@ igt_main_args("c:", NULL, help_str, opt_handler, NULL)
igt_subtest("stress-mm")
test_stress_mm(fd);
+ igt_subtest("stress-purge")
+ test_stress_purge(fd);
igt_subtest("stress-mm-invalidate-close")
test_invalidate_close_race(fd, false);
--
2.23.0.rc1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Limit the plug to fit small rings
If we are not running with a scheduler, we are using a global ringbuffer
which may not accommodate 16 extra batches. Fortunately, we only need
one such batch to block the submission queue as without a scheduler, it
is in order submission (and so the batch is after the main setup
anyway!).
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_schedule.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index 6e8466299..058102103 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -164,8 +164,13 @@ static uint32_t create_highest_priority(int fd)
static void unplug_show_queue(int fd, struct igt_cork *c, unsigned int engine)
{
igt_spin_t *spin[MAX_ELSP_QLEN];
+ int max = MAX_ELSP_QLEN;
- for (int n = 0; n < ARRAY_SIZE(spin); n++) {
+ /* If no scheduler, all batches are emitted in submission order */
+ if (!gem_scheduler_enabled(fd))
+ max = 1;
+
+ for (int n = 0; n < max; n++) {
const struct igt_spin_factory opts = {
.ctx = create_highest_priority(fd),
.engine = engine,
@@ -177,7 +182,7 @@ static void unplug_show_queue(int fd, struct igt_cork *c,
unsigned int engine)
igt_cork_unplug(c); /* batches will now be queued on the engine */
igt_debugfs_dump(fd, "i915_engine_info");
- for (int n = 0; n < ARRAY_SIZE(spin); n++)
+ for (int n = 0; n < max; n++)
igt_spin_free(fd, spin[n]);
}
--
2.23.0.rc1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix missing parentheses on TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT
== Series Details == Series: drm/i915/tgl: Fix missing parentheses on TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT URL : https://patchwork.freedesktop.org/series/65097/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6687_full -> Patchwork_13990_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13990_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13990_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13990_full: ### IGT changes ### Possible regressions * igt@kms_plane@plane-position-hole-dpms-pipe-b-planes: - shard-kbl: NOTRUN -> [DMESG-WARN][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13990/shard-kbl3/igt@kms_pl...@plane-position-hole-dpms-pipe-b-planes.html Known issues Here are the changes found in Patchwork_13990_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vecs0-s3: - shard-skl: [PASS][2] -> [INCOMPLETE][3] ([fdo#104108]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-skl4/igt@gem_ctx_isolat...@vecs0-s3.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13990/shard-skl10/igt@gem_ctx_isolat...@vecs0-s3.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#111325]) +4 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-iclb6/igt@gem_exec_sched...@preempt-other-chain-bsd.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13990/shard-iclb1/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen: - shard-skl: [PASS][6] -> [FAIL][7] ([fdo#103232]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-skl8/igt@kms_cursor_...@pipe-a-cursor-64x21-offscreen.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13990/shard-skl9/igt@kms_cursor_...@pipe-a-cursor-64x21-offscreen.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][8] -> [FAIL][9] ([fdo#105363]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-glk3/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13990/shard-glk6/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-apl: [PASS][10] -> [DMESG-WARN][11] ([fdo#108566]) +3 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-apl3/igt@kms_f...@flip-vs-suspend-interruptible.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13990/shard-apl4/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][12] -> [FAIL][13] ([fdo#103167]) +2 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-iclb4/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13990/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render: - shard-iclb: [PASS][14] -> [INCOMPLETE][15] ([fdo#106978] / [fdo#107713]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-iclb2/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-draw-render.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13990/shard-iclb7/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-draw-render.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][16] -> [FAIL][17] ([fdo#108145]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-skl8/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13990/shard-skl9/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_psr@psr2_primary_blt: - shard-iclb: [PASS][18] -> [SKIP][19] ([fdo#109441]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-iclb2/igt@kms_psr@psr2_primary_blt.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13990/shard-iclb5/igt@kms_psr@psr2_primary_blt.html * igt@perf@polling: - shard-skl: [PASS][20] -> [FAIL][21] ([fdo#110728]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-skl2/igt@p...@polling.h
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/2] drm/i915: Forgo last_fence active request tracking
== Series Details == Series: series starting with [CI,1/2] drm/i915: Forgo last_fence active request tracking URL : https://patchwork.freedesktop.org/series/65096/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6687_full -> Patchwork_13989_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13989_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13989_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13989_full: ### IGT changes ### Possible regressions * igt@kms_plane@plane-position-hole-dpms-pipe-b-planes: - shard-kbl: NOTRUN -> [DMESG-WARN][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/shard-kbl7/igt@kms_pl...@plane-position-hole-dpms-pipe-b-planes.html Known issues Here are the changes found in Patchwork_13989_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@preempt-hang-vebox: - shard-apl: [PASS][2] -> [INCOMPLETE][3] ([fdo#103927]) +2 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-apl1/igt@gem_exec_sched...@preempt-hang-vebox.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/shard-apl8/igt@gem_exec_sched...@preempt-hang-vebox.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#111325]) +7 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-iclb6/igt@gem_exec_sched...@preempt-other-chain-bsd.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/shard-iclb2/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][6] -> [DMESG-WARN][7] ([fdo#108566]) +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-apl6/igt@gem_workarou...@suspend-resume-context.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/shard-apl1/igt@gem_workarou...@suspend-resume-context.html * igt@i915_selftest@live_hangcheck: - shard-iclb: [PASS][8] -> [INCOMPLETE][9] ([fdo#107713] / [fdo#108569]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-iclb5/igt@i915_selftest@live_hangcheck.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/shard-iclb7/igt@i915_selftest@live_hangcheck.html * igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen: - shard-skl: [PASS][10] -> [FAIL][11] ([fdo#103232]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-skl8/igt@kms_cursor_...@pipe-a-cursor-64x21-offscreen.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/shard-skl10/igt@kms_cursor_...@pipe-a-cursor-64x21-offscreen.html * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-iclb: [PASS][12] -> [FAIL][13] ([fdo#103167]) +4 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][14] -> [FAIL][15] ([fdo#108145]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-skl8/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/shard-skl10/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: [PASS][16] -> [FAIL][17] ([fdo#103166]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-iclb7/igt@kms_plane_low...@pipe-a-tiling-x.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/shard-iclb4/igt@kms_plane_low...@pipe-a-tiling-x.html * igt@kms_psr@psr2_primary_blt: - shard-iclb: [PASS][18] -> [SKIP][19] ([fdo#109441]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-iclb2/igt@kms_psr@psr2_primary_blt.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/shard-iclb5/igt@kms_psr@psr2_primary_blt.html * igt@kms_setmode@basic: - shard-apl: [PASS][20] -> [FAIL][21] ([fdo#99912]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-apl6/igt@kms_setm...@basic.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/shard-apl4/igt@kms_setm...@basic.html * igt@prime_busy@hang-bsd2:
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/icl: Implement gen11 flush including tile cache
== Series Details == Series: series starting with [1/2] drm/i915/icl: Implement gen11 flush including tile cache URL : https://patchwork.freedesktop.org/series/65094/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6687_full -> Patchwork_13988_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13988_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13988_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13988_full: ### IGT changes ### Possible regressions * igt@kms_plane@plane-position-hole-dpms-pipe-b-planes: - shard-kbl: NOTRUN -> [DMESG-WARN][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13988/shard-kbl4/igt@kms_pl...@plane-position-hole-dpms-pipe-b-planes.html Known issues Here are the changes found in Patchwork_13988_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@preempt-hang-vebox: - shard-apl: [PASS][2] -> [INCOMPLETE][3] ([fdo#103927]) +4 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-apl1/igt@gem_exec_sched...@preempt-hang-vebox.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13988/shard-apl2/igt@gem_exec_sched...@preempt-hang-vebox.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#111325]) +6 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-iclb6/igt@gem_exec_sched...@preempt-other-chain-bsd.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13988/shard-iclb4/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_tiled_swapping@non-threaded: - shard-glk: [PASS][6] -> [DMESG-WARN][7] ([fdo#108686]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-glk9/igt@gem_tiled_swapp...@non-threaded.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13988/shard-glk2/igt@gem_tiled_swapp...@non-threaded.html * igt@i915_pm_rc6_residency@rc6-accuracy: - shard-kbl: [PASS][8] -> [SKIP][9] ([fdo#109271]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-kbl6/igt@i915_pm_rc6_reside...@rc6-accuracy.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13988/shard-kbl7/igt@i915_pm_rc6_reside...@rc6-accuracy.html * igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen: - shard-skl: [PASS][10] -> [FAIL][11] ([fdo#103232]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-skl8/igt@kms_cursor_...@pipe-a-cursor-64x21-offscreen.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13988/shard-skl9/igt@kms_cursor_...@pipe-a-cursor-64x21-offscreen.html * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-skl: [PASS][12] -> [FAIL][13] ([fdo#103184] / [fdo#103232]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-skl6/igt@kms_draw_...@draw-method-rgb565-mmap-gtt-xtiled.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13988/shard-skl1/igt@kms_draw_...@draw-method-rgb565-mmap-gtt-xtiled.html * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-iclb: [PASS][14] -> [FAIL][15] ([fdo#103167]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13988/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][16] -> [FAIL][17] ([fdo#108145]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-skl8/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13988/shard-skl9/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: [PASS][18] -> [FAIL][19] ([fdo#103166]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-iclb7/igt@kms_plane_low...@pipe-a-tiling-x.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13988/shard-iclb4/igt@kms_plane_low...@pipe-a-tiling-x.html * igt@kms_setmode@basic: - shard-apl: [PASS][20] -> [FAIL][21] ([fdo#99912]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-apl6/igt@kms_setm...@basic.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13988/shard-apl6/igt@kms_setm...@basic.htm
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/guc: keep breadcrumb irq always enabled
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/guc: keep breadcrumb irq always
enabled
URL : https://patchwork.freedesktop.org/series/65105/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6690 -> Patchwork_13995
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13995/
Known issues
Here are the changes found in Patchwork_13995 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6690/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13995/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#109485])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6690/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13995/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
Participating hosts (54 -> 46)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6690 -> Patchwork_13995
CI-20190529: 20190529
CI_DRM_6690: cf72e4ec99679a4a65fbb94341e3b6033a76483b @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5129: 06d5765ab2daba9f8826a36ce99eb95b58d4ccf4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13995: df14552c0c50a14cc1b6ed8f53ff7376b50532bb @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
df14552c0c50 drm/i915: drop engine_pin/unpin_breadcrumbs_irq
29af7f2e7ad9 drm/i915/guc: keep breadcrumb irq always enabled
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13995/
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for dma-buf/sw_sync: Synchronize signal vs syncpt free
== Series Details == Series: dma-buf/sw_sync: Synchronize signal vs syncpt free URL : https://patchwork.freedesktop.org/series/65092/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6687_full -> Patchwork_13987_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13987_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13987_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13987_full: ### IGT changes ### Possible regressions * igt@kms_plane@plane-position-hole-dpms-pipe-b-planes: - shard-kbl: NOTRUN -> [DMESG-WARN][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13987/shard-kbl4/igt@kms_pl...@plane-position-hole-dpms-pipe-b-planes.html * igt@sw_sync@sync_multi_producer_single_consumer: - shard-skl: [PASS][2] -> [INCOMPLETE][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-skl1/igt@sw_sync@sync_multi_producer_single_consumer.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13987/shard-skl2/igt@sw_sync@sync_multi_producer_single_consumer.html Known issues Here are the changes found in Patchwork_13987_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@pi-ringfull-bsd: - shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#111325]) +4 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-iclb7/igt@gem_exec_sched...@pi-ringfull-bsd.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13987/shard-iclb2/igt@gem_exec_sched...@pi-ringfull-bsd.html * igt@gem_userptr_blits@sync-unmap-cycles: - shard-apl: [PASS][6] -> [INCOMPLETE][7] ([fdo#103927]) +4 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-apl6/igt@gem_userptr_bl...@sync-unmap-cycles.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13987/shard-apl7/igt@gem_userptr_bl...@sync-unmap-cycles.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][8] -> [DMESG-WARN][9] ([fdo#108566]) +5 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-apl2/igt@i915_susp...@sysfs-reader.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13987/shard-apl4/igt@i915_susp...@sysfs-reader.html * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-skl: [PASS][10] -> [FAIL][11] ([fdo#103184] / [fdo#103232]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-skl6/igt@kms_draw_...@draw-method-rgb565-mmap-gtt-xtiled.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13987/shard-skl3/igt@kms_draw_...@draw-method-rgb565-mmap-gtt-xtiled.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][12] -> [FAIL][13] ([fdo#102887]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-glk3/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13987/shard-glk5/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-badstride: - shard-iclb: [PASS][14] -> [FAIL][15] ([fdo#103167]) +6 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-iclb6/igt@kms_frontbuffer_track...@fbc-badstride.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13987/shard-iclb1/igt@kms_frontbuffer_track...@fbc-badstride.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][16] -> [FAIL][17] ([fdo#108145]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-skl6/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13987/shard-skl3/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html * igt@kms_psr@psr2_primary_blt: - shard-iclb: [PASS][18] -> [SKIP][19] ([fdo#109441]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-iclb2/igt@kms_psr@psr2_primary_blt.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13987/shard-iclb1/igt@kms_psr@psr2_primary_blt.html * igt@kms_setmode@basic: - shard-apl: [PASS][20] -> [FAIL][21] ([fdo#99912]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/shard-apl6/igt@kms_setm...@basic.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13987/shard-apl4/igt@kms_setm...@basic.html * igt@prime_busy@hang-bsd2: - shard-iclb: [PASS][22] -> [SKIP][23] ([fdo#109276]) +16 similar issues [22]
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/i915/guc: keep breadcrumb irq always enabled
== Series Details == Series: series starting with [v2,1/2] drm/i915/guc: keep breadcrumb irq always enabled URL : https://patchwork.freedesktop.org/series/65105/ State : warning == Summary == $ dim checkpatch origin/drm-tip 29af7f2e7ad9 drm/i915/guc: keep breadcrumb irq always enabled -:54: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #54: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1080: + engine->park = engine->unpark = NULL; total: 0 errors, 0 warnings, 1 checks, 43 lines checked df14552c0c50 drm/i915: drop engine_pin/unpin_breadcrumbs_irq ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/2] drm/i915: drop engine_pin/unpin_breadcrumbs_irq
The last user has been removed, so drop the functions.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 22 -
drivers/gpu/drm/i915/gt/intel_engine.h | 3 ---
2 files changed, 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
index ceba1da61967..15bbdd8c7552 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
@@ -212,28 +212,6 @@ static void signal_irq_work(struct irq_work *work)
intel_engine_breadcrumbs_irq(engine);
}
-void intel_engine_pin_breadcrumbs_irq(struct intel_engine_cs *engine)
-{
- struct intel_breadcrumbs *b = &engine->breadcrumbs;
-
- spin_lock_irq(&b->irq_lock);
- if (!b->irq_enabled++)
- irq_enable(engine);
- GEM_BUG_ON(!b->irq_enabled); /* no overflow! */
- spin_unlock_irq(&b->irq_lock);
-}
-
-void intel_engine_unpin_breadcrumbs_irq(struct intel_engine_cs *engine)
-{
- struct intel_breadcrumbs *b = &engine->breadcrumbs;
-
- spin_lock_irq(&b->irq_lock);
- GEM_BUG_ON(!b->irq_enabled); /* no underflow! */
- if (!--b->irq_enabled)
- irq_disable(engine);
- spin_unlock_irq(&b->irq_lock);
-}
-
static void __intel_breadcrumbs_arm_irq(struct intel_breadcrumbs *b)
{
struct intel_engine_cs *engine =
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index e1228b0e577f..bc694adcd9ea 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -338,9 +338,6 @@ void intel_engine_init_execlists(struct intel_engine_cs
*engine);
void intel_engine_init_breadcrumbs(struct intel_engine_cs *engine);
void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
-void intel_engine_pin_breadcrumbs_irq(struct intel_engine_cs *engine);
-void intel_engine_unpin_breadcrumbs_irq(struct intel_engine_cs *engine);
-
void intel_engine_signal_breadcrumbs(struct intel_engine_cs *engine);
void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine);
--
2.22.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/2] drm/i915/guc: keep breadcrumb irq always enabled
We rely on the tasklet to update the GT PM refcount, so we can't disable
it even if we've processed all the requests for the engine because we
might have detected the request completion before the interrupt arrived.
Since on all platforms on which we plan to support guc submission we
don't allow disabling the breadcrumb interrupts, we can further siplify
the park/unpark flow by removing the interrupt pin/unpin. A BUG_ON has
been added to catch changes to this flow that would require us to
restore some kind of pinning.
v2: split removal of engine_pin/unpin_breadcrumbs_irq to its own
patch (chris)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Michal Wajdeczko
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 25 ---
1 file changed, 11 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 449ca6357018..deb054eeb37c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1059,18 +1059,6 @@ static void guc_interrupts_release(struct intel_gt *gt)
rps->pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK;
}
-static void guc_submission_park(struct intel_engine_cs *engine)
-{
- intel_engine_unpin_breadcrumbs_irq(engine);
- engine->flags &= ~I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
-}
-
-static void guc_submission_unpark(struct intel_engine_cs *engine)
-{
- engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
- intel_engine_pin_breadcrumbs_irq(engine);
-}
-
static void guc_set_default_submission(struct intel_engine_cs *engine)
{
/*
@@ -1088,8 +1076,8 @@ static void guc_set_default_submission(struct
intel_engine_cs *engine)
engine->execlists.tasklet.func = guc_submission_tasklet;
- engine->park = guc_submission_park;
- engine->unpark = guc_submission_unpark;
+ /* do not use execlists park/unpark */
+ engine->park = engine->unpark = NULL;
engine->reset.prepare = guc_reset_prepare;
engine->reset.reset = guc_reset;
@@ -1098,6 +1086,15 @@ static void guc_set_default_submission(struct
intel_engine_cs *engine)
engine->cancel_requests = guc_cancel_requests;
engine->flags &= ~I915_ENGINE_SUPPORTS_STATS;
+ engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
+
+ /*
+* For the breadcrumb irq to work we need the interrupts to stay
+* enabled. However, on all platforms on which we'll have support for
+* GuC submission we don't allow disabling the interrupts at runtime, so
+* we're always safe with the current flow.
+*/
+ GEM_BUG_ON(engine->irq_enable || engine->irq_disable);
}
int intel_guc_submission_enable(struct intel_guc *guc)
--
2.22.0
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cml: Add Missing PCI IDs
== Series Details ==
Series: drm/i915/cml: Add Missing PCI IDs
URL : https://patchwork.freedesktop.org/series/65104/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6690 -> Patchwork_13994
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13994/
Known issues
Here are the changes found in Patchwork_13994 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_basic@basic-all:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6690/fi-icl-u3/igt@gem_exec_ba...@basic-all.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13994/fi-icl-u3/igt@gem_exec_ba...@basic-all.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6690/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13994/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@i915_module_load@reload-no-display:
- fi-kbl-8809g: [PASS][5] -> [INCOMPLETE][6] ([fdo#103665])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6690/fi-kbl-8809g/igt@i915_module_l...@reload-no-display.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13994/fi-kbl-8809g/igt@i915_module_l...@reload-no-display.html
* igt@i915_selftest@live_requests:
- fi-byt-j1900: [PASS][7] -> [INCOMPLETE][8] ([fdo#102657])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6690/fi-byt-j1900/igt@i915_selftest@live_requests.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13994/fi-byt-j1900/igt@i915_selftest@live_requests.html
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: [PASS][9] -> [SKIP][10] ([fdo#109271] / [fdo#109278])
+2 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6690/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13994/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
* igt@kms_busy@basic-flip-c:
- fi-kbl-7500u: [PASS][11] -> [SKIP][12] ([fdo#109271] /
[fdo#109278]) +2 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6690/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13994/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102657]: https://bugs.freedesktop.org/show_bug.cgi?id=102657
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
Participating hosts (54 -> 46)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6690 -> Patchwork_13994
CI-20190529: 20190529
CI_DRM_6690: cf72e4ec99679a4a65fbb94341e3b6033a76483b @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5129: 06d5765ab2daba9f8826a36ce99eb95b58d4ccf4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13994: 78de0f6f216c3dfd67632b575898a7db75c3a50e @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
78de0f6f216c drm/i915/cml: Add Missing PCI IDs
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13994/
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: keep breadcrumb irq always enabled
== Series Details ==
Series: drm/i915/guc: keep breadcrumb irq always enabled
URL : https://patchwork.freedesktop.org/series/65103/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6690 -> Patchwork_13993
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13993/
Known issues
Here are the changes found in Patchwork_13993 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [PASS][1] -> [FAIL][2] ([fdo#108511])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6690/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13993/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live_gtt:
- fi-glk-dsi: [PASS][3] -> [DMESG-WARN][4] ([fdo#111377])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6690/fi-glk-dsi/igt@i915_selftest@live_gtt.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13993/fi-glk-dsi/igt@i915_selftest@live_gtt.html
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: [PASS][5] -> [SKIP][6] ([fdo#109271] / [fdo#109278])
+2 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6690/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13993/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
* igt@kms_busy@basic-flip-c:
- fi-kbl-7500u: [PASS][7] -> [SKIP][8] ([fdo#109271] / [fdo#109278])
+2 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6690/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13993/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][9] -> [FAIL][10] ([fdo#103167])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6690/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13993/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-fence-wait-default:
- fi-icl-u3: [PASS][11] -> [DMESG-WARN][12] ([fdo#107724])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6690/fi-icl-u3/igt@prime_v...@basic-fence-wait-default.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13993/fi-icl-u3/igt@prime_v...@basic-fence-wait-default.html
Possible fixes
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: [INCOMPLETE][13] ([fdo#107718]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6690/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13993/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111377]: https://bugs.freedesktop.org/show_bug.cgi?id=111377
Participating hosts (54 -> 46)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6690 -> Patchwork_13993
CI-20190529: 20190529
CI_DRM_6690: cf72e4ec99679a4a65fbb94341e3b6033a76483b @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5129: 06d5765ab2daba9f8826a36ce99eb95b58d4ccf4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13993: 836e502a988731c4870e39e308e44805191e28bf @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
836e502a9887 drm/i915/guc: keep breadcrumb irq always enabled
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13993/
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[Intel-gfx] [PATCH] drm/i915/cml: Add Missing PCI IDs
The BSpec has added three new IDS for CML. Update the IDs in accordance to the Spec. Cc: Lucas De Marchi Cc: José Roberto de Souza Signed-off-by: Anusha Srivatsa --- include/drm/i915_pciids.h | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index a70c982ddff9..b1f66b117c74 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -466,7 +466,10 @@ INTEL_VGA_DEVICE(0x9BC5, info), \ INTEL_VGA_DEVICE(0x9BC8, info), \ INTEL_VGA_DEVICE(0x9BC4, info), \ - INTEL_VGA_DEVICE(0x9BC2, info) + INTEL_VGA_DEVICE(0x9BC2, info), \ + INTEL_VGA_DEVICE(0x9BC6, info), \ + INTEL_VGA_DEVICE(0x9BE6, info), \ + INTEL_VGA_DEVICE(0x9BF6, info) #define INTEL_KBL_IDS(info) \ INTEL_KBL_GT1_IDS(info), \ -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/guc: keep breadcrumb irq always enabled
== Series Details == Series: drm/i915/guc: keep breadcrumb irq always enabled URL : https://patchwork.freedesktop.org/series/65103/ State : warning == Summary == $ dim checkpatch origin/drm-tip 836e502a9887 drm/i915/guc: keep breadcrumb irq always enabled -:98: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #98: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1080: + engine->park = engine->unpark = NULL; total: 0 errors, 0 warnings, 1 checks, 80 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915/tgl: Introduce initial Tigerlake Workarounds
On Thu, Jul 25, 2019 at 05:02:24PM -0700, Lucas De Marchi wrote:
> From: Michel Thierry
>
> Inherit workarounds from previous platforms that are still valid for
> Tigerlake.
>
> WaPipelineFlushCoherentLines:tgl (changed register but has same name)
> WaSendPushConstantsFromMMIO:tgl
> WaAllowUMDToModifySamplerMode:tgl
> WaRsForcewakeAddDelayForAck:tgl
>
> Cc: Daniele Ceraolo Spurio
Reviewed-by: Radhakrishna Sripada
> Signed-off-by: Michel Thierry
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 40 +++--
> drivers/gpu/drm/i915/i915_reg.h | 3 ++
> drivers/gpu/drm/i915/intel_pm.c | 4 ++-
> drivers/gpu/drm/i915/intel_uncore.c | 2 +-
> 5 files changed, 46 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 884dfc1cb033..893c58df8be0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -2069,6 +2069,8 @@ static int intel_init_workaround_bb(struct
> intel_engine_cs *engine)
> return 0;
>
> switch (INTEL_GEN(engine->i915)) {
> + case 12:
> + return 0;
> case 11:
> return 0;
> case 10:
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 704ace01e7f5..a6eb9c6e87ec 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -569,6 +569,11 @@ static void icl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
> }
>
> +static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> + struct i915_wa_list *wal)
> +{
> +}
> +
> static void
> __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
> struct i915_wa_list *wal,
> @@ -581,7 +586,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>
> wa_init_start(wal, name, engine->name);
>
> - if (IS_GEN(i915, 11))
> + if (IS_GEN(i915, 12))
> + tgl_ctx_workarounds_init(engine, wal);
> + else if (IS_GEN(i915, 11))
> icl_ctx_workarounds_init(engine, wal);
> else if (IS_CANNONLAKE(i915))
> cnl_ctx_workarounds_init(engine, wal);
> @@ -890,10 +897,17 @@ icl_gt_workarounds_init(struct drm_i915_private *i915,
> struct i915_wa_list *wal)
> GAMT_CHKN_DISABLE_L3_COH_PIPE);
> }
>
> +static void
> +tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
> *wal)
> +{
> +}
> +
> static void
> gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
> {
> - if (IS_GEN(i915, 11))
> + if (IS_GEN(i915, 12))
> + tgl_gt_workarounds_init(i915, wal);
> + else if (IS_GEN(i915, 11))
> icl_gt_workarounds_init(i915, wal);
> else if (IS_CANNONLAKE(i915))
> cnl_gt_workarounds_init(i915, wal);
> @@ -1183,6 +1197,17 @@ static void icl_whitelist_build(struct intel_engine_cs
> *engine)
> }
> }
>
> +static void tgl_whitelist_build(struct intel_engine_cs *engine)
> +{
> + struct i915_wa_list *w = &engine->whitelist;
> +
> + /* WaSendPushConstantsFromMMIO:tgl */
> + whitelist_reg(w, COMMON_SLICE_CHICKEN2);
> +
> + /* WaAllowUMDToModifySamplerMode:tgl */
> + whitelist_reg(w, GEN10_SAMPLER_MODE);
> +}
> +
> void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> {
> struct drm_i915_private *i915 = engine->i915;
> @@ -1190,7 +1215,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs
> *engine)
>
> wa_init_start(w, "whitelist", engine->name);
>
> - if (IS_GEN(i915, 11))
> + if (IS_GEN(i915, 12))
> + tgl_whitelist_build(engine);
> + else if (IS_GEN(i915, 11))
> icl_whitelist_build(engine);
> else if (IS_CANNONLAKE(i915))
> cnl_whitelist_build(engine);
> @@ -1240,6 +1267,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> {
> struct drm_i915_private *i915 = engine->i915;
>
> + if (IS_GEN(i915, 12)) {
> + /* WaPipelineFlushCoherentLines:tgl */
> + wa_write_or(wal,
> + GEN12_L3SQCREG2,
> + GEN12_LQSC_FLUSH_COHERENT_LINES);
> + }
> +
> if (IS_GEN(i915, 11)) {
> /* This is not an Wa. Enable for better image quality */
> wa_masked_en(wal,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 24f2a52a2b42..54ea25be 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7729,6 +7729,9 @@ enum {
> #define GEN8_LQSC_RO_PERF_DIS (1 << 27)
> #d
Re: [Intel-gfx] [PATCH] drm/i915/guc: keep breadcrumb irq always enabled
Quoting Daniele Ceraolo Spurio (2019-08-12 23:10:16)
> We rely on the tasklet to update the GT PM refcount, so we can't disable
> it even if we've processed all the requests for the engine because we
> might have detected the request completion before the interrupt arrived.
>
> Since on all platforms on which we plan to support guc submission we
> don't allow disabling the breadcrumb interrupts, we can further siplify
> the park/unpark flow by removing the interrupt pin/unpin. A BUG_ON has
> been added to catch changes to this flow that would require us to
> restore some kind of pinning.
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Chris Wilson
> Cc: Michal Wajdeczko
> ---
> drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 22
> drivers/gpu/drm/i915/gt/intel_engine.h| 3 ---
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 25 ---
> 3 files changed, 11 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
> b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
> index ceba1da61967..15bbdd8c7552 100644
> --- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
> @@ -212,28 +212,6 @@ static void signal_irq_work(struct irq_work *work)
> intel_engine_breadcrumbs_irq(engine);
> }
>
> -void intel_engine_pin_breadcrumbs_irq(struct intel_engine_cs *engine)
> -{
> - struct intel_breadcrumbs *b = &engine->breadcrumbs;
> -
> - spin_lock_irq(&b->irq_lock);
> - if (!b->irq_enabled++)
> - irq_enable(engine);
> - GEM_BUG_ON(!b->irq_enabled); /* no overflow! */
> - spin_unlock_irq(&b->irq_lock);
> -}
> -
> -void intel_engine_unpin_breadcrumbs_irq(struct intel_engine_cs *engine)
> -{
> - struct intel_breadcrumbs *b = &engine->breadcrumbs;
> -
> - spin_lock_irq(&b->irq_lock);
> - GEM_BUG_ON(!b->irq_enabled); /* no underflow! */
> - if (!--b->irq_enabled)
> - irq_disable(engine);
> - spin_unlock_irq(&b->irq_lock);
> -}
Could you split this to a second patch? The last draft of the pv-engine
was still using this pin_irq.
> -
> static void __intel_breadcrumbs_arm_irq(struct intel_breadcrumbs *b)
> {
> struct intel_engine_cs *engine =
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
> b/drivers/gpu/drm/i915/gt/intel_engine.h
> index e1228b0e577f..bc694adcd9ea 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -338,9 +338,6 @@ void intel_engine_init_execlists(struct intel_engine_cs
> *engine);
> void intel_engine_init_breadcrumbs(struct intel_engine_cs *engine);
> void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
>
> -void intel_engine_pin_breadcrumbs_irq(struct intel_engine_cs *engine);
> -void intel_engine_unpin_breadcrumbs_irq(struct intel_engine_cs *engine);
> -
> void intel_engine_signal_breadcrumbs(struct intel_engine_cs *engine);
> void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine);
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 449ca6357018..deb054eeb37c 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1059,18 +1059,6 @@ static void guc_interrupts_release(struct intel_gt *gt)
> rps->pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK;
> }
>
> -static void guc_submission_park(struct intel_engine_cs *engine)
> -{
> - intel_engine_unpin_breadcrumbs_irq(engine);
> - engine->flags &= ~I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
> -}
> -
> -static void guc_submission_unpark(struct intel_engine_cs *engine)
> -{
> - engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
> - intel_engine_pin_breadcrumbs_irq(engine);
> -}
> -
> static void guc_set_default_submission(struct intel_engine_cs *engine)
> {
> /*
> @@ -1088,8 +1076,8 @@ static void guc_set_default_submission(struct
> intel_engine_cs *engine)
>
> engine->execlists.tasklet.func = guc_submission_tasklet;
>
> - engine->park = guc_submission_park;
> - engine->unpark = guc_submission_unpark;
> + /* do not use execlists park/unpark */
> + engine->park = engine->unpark = NULL;
>
> engine->reset.prepare = guc_reset_prepare;
> engine->reset.reset = guc_reset;
> @@ -1098,6 +1086,15 @@ static void guc_set_default_submission(struct
> intel_engine_cs *engine)
> engine->cancel_requests = guc_cancel_requests;
>
> engine->flags &= ~I915_ENGINE_SUPPORTS_STATS;
> + engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
> +
> + /*
> +* For the breadcrumb irq to work we need the interrupts to stay
> +* enabled. However, on all platforms on which we'll have support for
> +* GuC submission we don't allow disabling the interrupts at runtime,
> so
> +* we
[Intel-gfx] [PATCH] drm/i915/guc: keep breadcrumb irq always enabled
We rely on the tasklet to update the GT PM refcount, so we can't disable
it even if we've processed all the requests for the engine because we
might have detected the request completion before the interrupt arrived.
Since on all platforms on which we plan to support guc submission we
don't allow disabling the breadcrumb interrupts, we can further siplify
the park/unpark flow by removing the interrupt pin/unpin. A BUG_ON has
been added to catch changes to this flow that would require us to
restore some kind of pinning.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 22
drivers/gpu/drm/i915/gt/intel_engine.h| 3 ---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 25 ---
3 files changed, 11 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
index ceba1da61967..15bbdd8c7552 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
@@ -212,28 +212,6 @@ static void signal_irq_work(struct irq_work *work)
intel_engine_breadcrumbs_irq(engine);
}
-void intel_engine_pin_breadcrumbs_irq(struct intel_engine_cs *engine)
-{
- struct intel_breadcrumbs *b = &engine->breadcrumbs;
-
- spin_lock_irq(&b->irq_lock);
- if (!b->irq_enabled++)
- irq_enable(engine);
- GEM_BUG_ON(!b->irq_enabled); /* no overflow! */
- spin_unlock_irq(&b->irq_lock);
-}
-
-void intel_engine_unpin_breadcrumbs_irq(struct intel_engine_cs *engine)
-{
- struct intel_breadcrumbs *b = &engine->breadcrumbs;
-
- spin_lock_irq(&b->irq_lock);
- GEM_BUG_ON(!b->irq_enabled); /* no underflow! */
- if (!--b->irq_enabled)
- irq_disable(engine);
- spin_unlock_irq(&b->irq_lock);
-}
-
static void __intel_breadcrumbs_arm_irq(struct intel_breadcrumbs *b)
{
struct intel_engine_cs *engine =
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index e1228b0e577f..bc694adcd9ea 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -338,9 +338,6 @@ void intel_engine_init_execlists(struct intel_engine_cs
*engine);
void intel_engine_init_breadcrumbs(struct intel_engine_cs *engine);
void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
-void intel_engine_pin_breadcrumbs_irq(struct intel_engine_cs *engine);
-void intel_engine_unpin_breadcrumbs_irq(struct intel_engine_cs *engine);
-
void intel_engine_signal_breadcrumbs(struct intel_engine_cs *engine);
void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 449ca6357018..deb054eeb37c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1059,18 +1059,6 @@ static void guc_interrupts_release(struct intel_gt *gt)
rps->pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK;
}
-static void guc_submission_park(struct intel_engine_cs *engine)
-{
- intel_engine_unpin_breadcrumbs_irq(engine);
- engine->flags &= ~I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
-}
-
-static void guc_submission_unpark(struct intel_engine_cs *engine)
-{
- engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
- intel_engine_pin_breadcrumbs_irq(engine);
-}
-
static void guc_set_default_submission(struct intel_engine_cs *engine)
{
/*
@@ -1088,8 +1076,8 @@ static void guc_set_default_submission(struct
intel_engine_cs *engine)
engine->execlists.tasklet.func = guc_submission_tasklet;
- engine->park = guc_submission_park;
- engine->unpark = guc_submission_unpark;
+ /* do not use execlists park/unpark */
+ engine->park = engine->unpark = NULL;
engine->reset.prepare = guc_reset_prepare;
engine->reset.reset = guc_reset;
@@ -1098,6 +1086,15 @@ static void guc_set_default_submission(struct
intel_engine_cs *engine)
engine->cancel_requests = guc_cancel_requests;
engine->flags &= ~I915_ENGINE_SUPPORTS_STATS;
+ engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
+
+ /*
+* For the breadcrumb irq to work we need the interrupts to stay
+* enabled. However, on all platforms on which we'll have support for
+* GuC submission we don't allow disabling the interrupts at runtime, so
+* we're always safe with the current flow.
+*/
+ GEM_BUG_ON(engine->irq_enable || engine->irq_disable);
}
int intel_guc_submission_enable(struct intel_guc *guc)
--
2.22.0
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Re: [Intel-gfx] [PATCH 3/3] drm/i915/tgl: Implement Wa_1406941453
On Thu, Jul 25, 2019 at 05:02:26PM -0700, Lucas De Marchi wrote:
> From: Michel Thierry
>
> Enable Small PL for power benefit.
>
> Signed-off-by: Michel Thierry
> Signed-off-by: Lucas De Marchi
> Reviewed-by: Stuart Summers
Reviewed-by: Radhakrishna Sripada
> Link:
> https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-18-lucas.demar...@intel.com
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 3235ef355dfd..830ccd416a29 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1279,6 +1279,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> wa_write_or(wal,
> GEN12_L3SQCREG2,
> GEN12_LQSC_FLUSH_COHERENT_LINES);
> +
> + /* Wa_1406941453:tgl */
> + wa_masked_en(wal,
> + SAMPLER_MODE,
> + SAMPLER_ENABLE_SMALL_PL);
> }
>
> if (IS_GEN(i915, 11)) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fbbb89f6ca2f..71efb37f54a3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8965,6 +8965,9 @@ enum {
> #define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5)
> #define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
>
> +#define SAMPLER_MODE _MMIO(0xe18c)
> +#define SAMPLER_ENABLE_SMALL_PL(1 << 15)
> +
> #define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
> #define FLOW_CONTROL_ENABLE(1 << 15)
> #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1 << 8)
> --
> 2.21.0
>
> ___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with drm/i915/guc: Use a local cancel_port_requests (rev2)
== Series Details == Series: series starting with drm/i915/guc: Use a local cancel_port_requests (rev2) URL : https://patchwork.freedesktop.org/series/65089/ State : failure == Summary == Applying: drm/i915/guc: Use a local cancel_port_requests Applying: drm/i915: Push the wakeref->count deferral to the backend Applying: drm/i915/gt: Save/restore interrupts around breadcrumb disable Applying: drm/i915/execlists: Lift process_csb() out of the irq-off spinlock Applying: drm/i915/gt: Track timeline activeness in enter/exit Applying: drm/i915/gt: Convert timeline tracking to spinlock Applying: drm/i915/gt: Guard timeline pinning with its own mutex Applying: drm/i915: Protect request retirement with timeline->mutex Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gt/intel_gt.c M drivers/gpu/drm/i915/gt/intel_gt_types.h M drivers/gpu/drm/i915/gt/intel_ringbuffer.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/gt/intel_ringbuffer.c Auto-merging drivers/gpu/drm/i915/gt/intel_gt_types.h Auto-merging drivers/gpu/drm/i915/gt/intel_gt.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_gt.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0008 drm/i915: Protect request retirement with timeline->mutex When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/uc: Log fw status changes only under debug config
== Series Details ==
Series: drm/i915/uc: Log fw status changes only under debug config
URL : https://patchwork.freedesktop.org/series/65101/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6689 -> Patchwork_13991
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13991/
Known issues
Here are the changes found in Patchwork_13991 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6689/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13991/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
* igt@gem_mmap_gtt@basic-read-write-distinct:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6689/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13991/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
* igt@i915_selftest@live_reset:
- fi-bsw-n3050: [PASS][5] -> [DMESG-WARN][6] ([fdo#107709])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6689/fi-bsw-n3050/igt@i915_selftest@live_reset.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13991/fi-bsw-n3050/igt@i915_selftest@live_reset.html
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-7500u: [PASS][7] -> [SKIP][8] ([fdo#109271]) +23 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6689/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13991/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html
Possible fixes
* igt@gem_mmap_gtt@basic:
- fi-glk-dsi: [INCOMPLETE][9] ([fdo#103359] / [k.org#198133]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6689/fi-glk-dsi/igt@gem_mmap_...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13991/fi-glk-dsi/igt@gem_mmap_...@basic.html
* igt@i915_selftest@live_gtt:
- fi-bxt-dsi: [INCOMPLETE][11] ([fdo#103927]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6689/fi-bxt-dsi/igt@i915_selftest@live_gtt.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13991/fi-bxt-dsi/igt@i915_selftest@live_gtt.html
* igt@kms_busy@basic-flip-c:
- {fi-icl-u4}:[DMESG-WARN][13] ([fdo#105602]) -> [PASS][14] +5
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6689/fi-icl-u4/igt@kms_b...@basic-flip-c.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13991/fi-icl-u4/igt@kms_b...@basic-flip-c.html
- fi-kbl-7500u: [SKIP][15] ([fdo#109271] / [fdo#109278]) ->
[PASS][16] +2 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6689/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13991/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][17] ([fdo#109485]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6689/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13991/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#110503]: https://bugs.freedesktop.org/show_bug.cgi?id=110503
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (53 -> 46)
--
Additional (1): fi-pnv-d510
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-201905
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/18] drm/i915/guc: Use a local cancel_port_requests
== Series Details == Series: series starting with [01/18] drm/i915/guc: Use a local cancel_port_requests URL : https://patchwork.freedesktop.org/series/65089/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6686_full -> Patchwork_13986_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13986_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13986_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13986_full: ### IGT changes ### Possible regressions * igt@gem_ctx_shared@q-out-order-bsd1: - shard-skl: [PASS][1] -> [INCOMPLETE][2] +29 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6686/shard-skl5/igt@gem_ctx_sha...@q-out-order-bsd1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/shard-skl10/igt@gem_ctx_sha...@q-out-order-bsd1.html * igt@gem_ctx_shared@q-smoketest-blt: - shard-skl: [PASS][3] -> [DMESG-FAIL][4] +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6686/shard-skl6/igt@gem_ctx_sha...@q-smoketest-blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/shard-skl5/igt@gem_ctx_sha...@q-smoketest-blt.html - shard-iclb: NOTRUN -> [DMESG-FAIL][5] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/shard-iclb5/igt@gem_ctx_sha...@q-smoketest-blt.html * igt@gem_ctx_shared@q-smoketest-bsd1: - shard-apl: [PASS][6] -> [DMESG-FAIL][7] +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6686/shard-apl1/igt@gem_ctx_sha...@q-smoketest-bsd1.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/shard-apl8/igt@gem_ctx_sha...@q-smoketest-bsd1.html - shard-glk: [PASS][8] -> [DMESG-FAIL][9] +2 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6686/shard-glk8/igt@gem_ctx_sha...@q-smoketest-bsd1.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/shard-glk7/igt@gem_ctx_sha...@q-smoketest-bsd1.html - shard-iclb: [PASS][10] -> [DMESG-FAIL][11] +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6686/shard-iclb4/igt@gem_ctx_sha...@q-smoketest-bsd1.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/shard-iclb6/igt@gem_ctx_sha...@q-smoketest-bsd1.html * igt@gem_exec_schedule@preempt-contexts-vebox: - shard-skl: NOTRUN -> [INCOMPLETE][12] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/shard-skl6/igt@gem_exec_sched...@preempt-contexts-vebox.html * igt@gem_exec_schedule@smoketest-vebox: - shard-kbl: [PASS][13] -> [DMESG-FAIL][14] +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6686/shard-kbl1/igt@gem_exec_sched...@smoketest-vebox.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/shard-kbl7/igt@gem_exec_sched...@smoketest-vebox.html * igt@runner@aborted: - shard-kbl: NOTRUN -> ([FAIL][15], [FAIL][16], [FAIL][17], [FAIL][18], [FAIL][19], [FAIL][20], [FAIL][21], [FAIL][22], [FAIL][23], [FAIL][24], [FAIL][25], [FAIL][26], [FAIL][27], [FAIL][28], [FAIL][29], [FAIL][30], [FAIL][31], [FAIL][32], [FAIL][33], [FAIL][34], [FAIL][35], [FAIL][36], [FAIL][37], [FAIL][38], [FAIL][39], [FAIL][40], [FAIL][41], [FAIL][42], [FAIL][43], [FAIL][44], [FAIL][45], [FAIL][46], [FAIL][47], [FAIL][48]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/shard-kbl7/igt@run...@aborted.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/shard-kbl7/igt@run...@aborted.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/shard-kbl7/igt@run...@aborted.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/shard-kbl2/igt@run...@aborted.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/shard-kbl6/igt@run...@aborted.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/shard-kbl2/igt@run...@aborted.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/shard-kbl3/igt@run...@aborted.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/shard-kbl6/igt@run...@aborted.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/shard-kbl1/igt@run...@aborted.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/shard-kbl3/igt@run...@aborted.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/shard-kbl7/igt@run...@aborted.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/shard-kbl7/igt@run...@aborted.html [27]: https:/
Re: [Intel-gfx] [PATCH 6/8] drm/i915/guc: Keep the engine awake until the tasklet is idle
Quoting Daniele Ceraolo Spurio (2019-08-12 21:38:39) > > > On 8/12/19 3:44 AM, Chris Wilson wrote: > > Quoting Chris Wilson (2019-08-12 10:10:43) > >> For the guc, we need to keep the engine awake (and not parked) and not > >> just the gt. If we let the engine park, we disable the irq and stop > >> processing the tasklet, leaving state outstanding inside the tasklet. > >> > >> The downside is, of course, we now have to wait until the tasklet is run > >> before we consider the engine idle. > > > > Fwiw, because of this I think it may be preferable to keep to using GT > > pm for the tasklet; and apply Daniele's patch to keep > > NEEDS_BREADCRUMB_TASKLET set (which is the right thing to do anyway now > > that we stop switching between submission modes). > > -Chris > > > > Given that the GuC submission code is about to undergo a rework I > believe it'd be better to keep the fix contained to the GuC side of > things for now and avoid impacting the more general request paths (i.e. > patch 4 in this series, unless you still want that for other reasons). > I'll clean up and send the other patch. Oh, we need that anyway :) https://bugs.freedesktop.org/show_bug.cgi?id=111378 And it actually clarified some of the heartbeat code, so it's an eventual win. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 6/8] drm/i915/guc: Keep the engine awake until the tasklet is idle
On 8/12/19 3:44 AM, Chris Wilson wrote: Quoting Chris Wilson (2019-08-12 10:10:43) For the guc, we need to keep the engine awake (and not parked) and not just the gt. If we let the engine park, we disable the irq and stop processing the tasklet, leaving state outstanding inside the tasklet. The downside is, of course, we now have to wait until the tasklet is run before we consider the engine idle. Fwiw, because of this I think it may be preferable to keep to using GT pm for the tasklet; and apply Daniele's patch to keep NEEDS_BREADCRUMB_TASKLET set (which is the right thing to do anyway now that we stop switching between submission modes). -Chris Given that the GuC submission code is about to undergo a rework I believe it'd be better to keep the fix contained to the GuC side of things for now and avoid impacting the more general request paths (i.e. patch 4 in this series, unless you still want that for other reasons). I'll clean up and send the other patch. Daniele ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/guc: Use a local cancel_port_requests
Since execlists and the guc have diverged in their port tracking, we
cannot simply reuse the execlists cancellation code as it leads to
unbalanced reference counting. Use a local, simpler routine for the guc.
Signed-off-by: Chris Wilson
Cc: Daniele Ceraolo Spurio
Reviewed-by: Daniele Ceraolo Spurio
---
Add reminders that we only use the execlists->inflight queue currently.
---
drivers/gpu/drm/i915/gt/intel_engine.h| 3 --
drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +--
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 ++-
3 files changed, 30 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index e1228b0e577f..4b6a1cf80706 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -136,9 +136,6 @@ execlists_active(const struct intel_engine_execlists
*execlists)
return READ_ONCE(*execlists->active);
}
-void
-execlists_cancel_port_requests(struct intel_engine_execlists * const
execlists);
-
struct i915_request *
execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b97047d58d3d..5c26c4ae139b 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1297,8 +1297,8 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
}
}
-void
-execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)
+static void
+cancel_port_requests(struct intel_engine_execlists * const execlists)
{
struct i915_request * const *port, *rq;
@@ -2355,7 +2355,7 @@ static void __execlists_reset(struct intel_engine_cs
*engine, bool stalled)
unwind:
/* Push back any incomplete requests for replay after the reset. */
- execlists_cancel_port_requests(execlists);
+ cancel_port_requests(execlists);
__unwind_incomplete_requests(engine);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 449ca6357018..26918261d60d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -517,11 +517,14 @@ static struct i915_request *schedule_in(struct
i915_request *rq, int idx)
{
trace_i915_request_in(rq, idx);
- if (!rq->hw_context->inflight)
- rq->hw_context->inflight = rq->engine;
- intel_context_inflight_inc(rq->hw_context);
- intel_gt_pm_get(rq->engine->gt);
+ /*
+* Currently we are not tracking the rq->context being inflight
+* (ce->inflight = rq->engine). It is only used by the execlists
+* backend at the moment, a similar counting strategy would be
+* required if we generalise the inflight tracking.
+*/
+ intel_gt_pm_get(rq->engine->gt);
return i915_request_get(rq);
}
@@ -529,10 +532,6 @@ static void schedule_out(struct i915_request *rq)
{
trace_i915_request_out(rq);
- intel_context_inflight_dec(rq->hw_context);
- if (!intel_context_inflight_count(rq->hw_context))
- rq->hw_context->inflight = NULL;
-
intel_gt_pm_put(rq->engine->gt);
i915_request_put(rq);
}
@@ -556,6 +555,11 @@ static void __guc_dequeue(struct intel_engine_cs *engine)
last = NULL;
}
+ /*
+* We write directly into the execlists->inflight queue and don't use
+* the execlists->pending queue, as we don't have a distinct switch
+* event.
+*/
port = first;
while ((rb = rb_first_cached(&execlists->queue))) {
struct i915_priolist *p = to_priolist(rb);
@@ -636,6 +640,19 @@ static void guc_reset_prepare(struct intel_engine_cs
*engine)
__tasklet_disable_sync_once(&execlists->tasklet);
}
+static void
+cancel_port_requests(struct intel_engine_execlists * const execlists)
+{
+ struct i915_request * const *port, *rq;
+
+ /* Note we are only using the inflight and not the pending queue */
+
+ for (port = execlists->active; (rq = *port); port++)
+ schedule_out(rq);
+ execlists->active =
+ memset(execlists->inflight, 0, sizeof(execlists->inflight));
+}
+
static void guc_reset(struct intel_engine_cs *engine, bool stalled)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
@@ -644,7 +661,7 @@ static void guc_reset(struct intel_engine_cs *engine, bool
stalled)
spin_lock_irqsave(&engine->active.lock, flags);
- execlists_cancel_port_requests(execlists);
+ cancel_port_requests(execlists);
/* Push back any incomplete requests for replay after the reset. */
rq = execlists_unwind_incomplete_requests(execlists);
@@ -687,7 +704,7 @@ static void guc_cancel_requests(struct intel_engine_c
Re: [Intel-gfx] [PATCH 01/18] drm/i915/guc: Use a local cancel_port_requests
On 8/12/19 6:38 AM, Chris Wilson wrote:
Since execlista and the guc have diverged in their port tracking, we
cannot simply reuse the execlists cancellation code as it leads to
unbalanced reference counting. Use a local simpler routine for the guc.
LGTM, just wondering if we should put a comment somewhere to note that
ce->inflight and execlists->pending are currently unused in the GuC
path, so we don't incorrectly assume they're always set at certain
stages of the submission. But anyway:
Reviewed-by: Daniele Ceraolo Spurio
Janusz, does this work for you?
Thanks,
Daniele
Signed-off-by: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_engine.h| 3 ---
drivers/gpu/drm/i915/gt/intel_lrc.c | 6 ++---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 23 +++
3 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index e1228b0e577f..4b6a1cf80706 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -136,9 +136,6 @@ execlists_active(const struct intel_engine_execlists
*execlists)
return READ_ONCE(*execlists->active);
}
-void
-execlists_cancel_port_requests(struct intel_engine_execlists * const
execlists);
-
struct i915_request *
execlists_unwind_incomplete_requests(struct intel_engine_execlists
*execlists);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b97047d58d3d..5c26c4ae139b 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1297,8 +1297,8 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
}
}
-void
-execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)
+static void
+cancel_port_requests(struct intel_engine_execlists * const execlists)
{
struct i915_request * const *port, *rq;
@@ -2355,7 +2355,7 @@ static void __execlists_reset(struct intel_engine_cs *engine, bool stalled)
unwind:
/* Push back any incomplete requests for replay after the reset. */
- execlists_cancel_port_requests(execlists);
+ cancel_port_requests(execlists);
__unwind_incomplete_requests(engine);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 449ca6357018..a37afc6266ec 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -517,11 +517,7 @@ static struct i915_request *schedule_in(struct
i915_request *rq, int idx)
{
trace_i915_request_in(rq, idx);
- if (!rq->hw_context->inflight)
- rq->hw_context->inflight = rq->engine;
- intel_context_inflight_inc(rq->hw_context);
intel_gt_pm_get(rq->engine->gt);
-
return i915_request_get(rq);
}
@@ -529,10 +525,6 @@ static void schedule_out(struct i915_request *rq)
{
trace_i915_request_out(rq);
- intel_context_inflight_dec(rq->hw_context);
- if (!intel_context_inflight_count(rq->hw_context))
- rq->hw_context->inflight = NULL;
-
intel_gt_pm_put(rq->engine->gt);
i915_request_put(rq);
}
@@ -636,6 +628,17 @@ static void guc_reset_prepare(struct intel_engine_cs
*engine)
__tasklet_disable_sync_once(&execlists->tasklet);
}
+static void
+cancel_port_requests(struct intel_engine_execlists * const execlists)
+{
+ struct i915_request * const *port, *rq;
+
+ for (port = execlists->active; (rq = *port); port++)
+ schedule_out(rq);
+ execlists->active =
+ memset(execlists->inflight, 0, sizeof(execlists->inflight));
+}
+
static void guc_reset(struct intel_engine_cs *engine, bool stalled)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
@@ -644,7 +647,7 @@ static void guc_reset(struct intel_engine_cs *engine, bool
stalled)
spin_lock_irqsave(&engine->active.lock, flags);
- execlists_cancel_port_requests(execlists);
+ cancel_port_requests(execlists);
/* Push back any incomplete requests for replay after the reset. */
rq = execlists_unwind_incomplete_requests(execlists);
@@ -687,7 +690,7 @@ static void guc_cancel_requests(struct intel_engine_cs
*engine)
spin_lock_irqsave(&engine->active.lock, flags);
/* Cancel the requests on the HW and clear the ELSP tracker. */
- execlists_cancel_port_requests(execlists);
+ cancel_port_requests(execlists);
/* Mark all executing requests as skipped. */
list_for_each_entry(rq, &engine->active.requests, sched.link) {
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC] drm/i915/uc: Log fw status changes only under debug config
Quoting Michal Wajdeczko (2019-08-12 20:51:25)
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
> b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
> index 20a5ddb753c3..885a4d7e4d37 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
> @@ -42,7 +42,7 @@ enum intel_uc_fw_type {
> */
> struct intel_uc_fw {
> enum intel_uc_fw_type type;
> - enum intel_uc_fw_status status;
> + enum intel_uc_fw_status _status;
What you can do to prevent accidentally writing into the variable, while
keeping fw->status for convenience, is
- enum intel_uc_fw_status _status;
+ union {
+ const enum intel_uc_fw_status status;
+ enum intel_uc_fw_status __status; /* no accidental overwrites */
+ };
The only catch is that is disallows struct assignment (but memcpy is
still fine).
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC] drm/i915/uc: Log fw status changes only under debug config
We don't care about internal firmware status changes unless
we are doing some real debugging. Note that our CI is not
using DRM_I915_DEBUG_GUC config by default so use it.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 4 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 56 ++-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 19 ++--
5 files changed, 55 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 445dcea51e51..5528224448f6 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -157,10 +157,10 @@ int intel_guc_fw_upload(struct intel_guc *guc)
if (ret)
goto out;
- guc->fw.status = INTEL_UC_FIRMWARE_RUNNING;
+ intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_RUNNING);
return 0;
out:
- guc->fw.status = INTEL_UC_FIRMWARE_FAIL;
+ intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_FAIL);
return ret;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 75dade1cfbca..1edda1657411 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -147,12 +147,12 @@ int intel_huc_auth(struct intel_huc *huc)
goto fail;
}
- huc->fw.status = INTEL_UC_FIRMWARE_RUNNING;
+ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING);
return 0;
fail:
i915_probe_error(gt->i915, "HuC: Authentication failed %d\n", ret);
- huc->fw.status = INTEL_UC_FIRMWARE_FAIL;
+ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_FAIL);
return ret;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 0dc2b0cf4604..73bf673e153b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -418,7 +418,7 @@ int intel_uc_init_hw(struct intel_uc *uc)
return 0;
if (!intel_uc_fw_is_available(&guc->fw)) {
- ret = intel_uc_fw_status_to_error(guc->fw.status);
+ ret = intel_uc_fw_status_to_error(guc->fw._status);
goto err_out;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 302eb1b909dc..b71197f3da8a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -11,6 +11,29 @@
#include "intel_uc_fw_abi.h"
#include "i915_drv.h"
+#ifdef CONFIG_DRM_I915_DEBUG_GUC
+static inline struct intel_gt *__uc_fw_to_gt(struct intel_uc_fw *uc_fw)
+{
+ GEM_BUG_ON(uc_fw->_status == INTEL_UC_FIRMWARE_UNINITIALIZED);
+ if (uc_fw->type == INTEL_UC_FW_TYPE_GUC)
+ return container_of(uc_fw, struct intel_gt, uc.guc.fw);
+
+ GEM_BUG_ON(uc_fw->type != INTEL_UC_FW_TYPE_HUC);
+ return container_of(uc_fw, struct intel_gt, uc.huc.fw);
+}
+
+void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
+ enum intel_uc_fw_status status)
+{
+ uc_fw->_status = status;
+ DRM_DEV_DEBUG_DRIVER(__uc_fw_to_gt(uc_fw)->i915->drm.dev,
+"%s firmware -> %s\n",
+intel_uc_fw_type_repr(uc_fw->type),
+status == INTEL_UC_FIRMWARE_SELECTED ?
+uc_fw->path : intel_uc_fw_status_repr(status));
+}
+#endif
+
/*
* List of required GuC and HuC binaries per-platform.
* Must be ordered based on platform + revid, from newer to older.
@@ -173,7 +196,7 @@ void intel_uc_fw_init_early(struct intel_uc_fw *uc_fw,
* before we're looked at the HW caps to see if we have uc support
*/
BUILD_BUG_ON(INTEL_UC_FIRMWARE_UNINITIALIZED);
- GEM_BUG_ON(uc_fw->status);
+ GEM_BUG_ON(uc_fw->_status);
GEM_BUG_ON(uc_fw->path);
uc_fw->type = type;
@@ -183,10 +206,9 @@ void intel_uc_fw_init_early(struct intel_uc_fw *uc_fw,
__uc_fw_user_override(uc_fw);
}
- if (uc_fw->path && *uc_fw->path)
- uc_fw->status = INTEL_UC_FIRMWARE_SELECTED;
- else
- uc_fw->status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
+ intel_uc_fw_change_status(uc_fw, uc_fw->path && *uc_fw->path ?
+ INTEL_UC_FIRMWARE_SELECTED :
+ INTEL_UC_FIRMWARE_NOT_SUPPORTED);
}
static void __force_fw_fetch_failures(struct intel_uc_fw *uc_fw,
@@ -343,20 +365,15 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw, struct
drm_i915_private *i915)
uc_fw->obj = obj;
uc_fw->size = fw->size;
- uc_fw->status = INTEL_UC_FIRMWARE_AVAILABLE;
-
- DRM_D
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/8] drm/i915/execlists: Avoid sync calls during park (rev2)
== Series Details == Series: series starting with [1/8] drm/i915/execlists: Avoid sync calls during park (rev2) URL : https://patchwork.freedesktop.org/series/65080/ State : success == Summary == CI Bug Log - changes from CI_DRM_6685_full -> Patchwork_13984_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13984_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vecs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/shard-apl4/igt@gem_ctx_isolat...@vecs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13984/shard-apl8/igt@gem_ctx_isolat...@vecs0-s3.html * igt@gem_exec_schedule@wide-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/shard-iclb6/igt@gem_exec_sched...@wide-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13984/shard-iclb2/igt@gem_exec_sched...@wide-bsd.html * igt@i915_pm_rpm@system-suspend: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#104108] / [fdo#107807]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/shard-skl8/igt@i915_pm_...@system-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13984/shard-skl7/igt@i915_pm_...@system-suspend.html * igt@kms_cursor_crc@pipe-c-cursor-128x128-sliding: - shard-apl: [PASS][7] -> [INCOMPLETE][8] ([fdo#103927]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/shard-apl3/igt@kms_cursor_...@pipe-c-cursor-128x128-sliding.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13984/shard-apl6/igt@kms_cursor_...@pipe-c-cursor-128x128-sliding.html * igt@kms_flip@dpms-vs-vblank-race-interruptible: - shard-glk: [PASS][9] -> [FAIL][10] ([fdo#103060]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/shard-glk8/igt@kms_f...@dpms-vs-vblank-race-interruptible.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13984/shard-glk3/igt@kms_f...@dpms-vs-vblank-race-interruptible.html * igt@kms_flip@flip-vs-panning-vs-hang: - shard-hsw: [PASS][11] -> [INCOMPLETE][12] ([fdo#103540]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/shard-hsw5/igt@kms_f...@flip-vs-panning-vs-hang.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13984/shard-hsw2/igt@kms_f...@flip-vs-panning-vs-hang.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +5 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-render.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13984/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-render.html * igt@kms_frontbuffer_tracking@fbc-1p-rte: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167] / [fdo#110378]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-rte.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13984/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-rte.html * igt@kms_frontbuffer_tracking@psr-suspend: - shard-skl: [PASS][17] -> [INCOMPLETE][18] ([fdo#104108] / [fdo#106978]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/shard-skl8/igt@kms_frontbuffer_track...@psr-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13984/shard-skl10/igt@kms_frontbuffer_track...@psr-suspend.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: [PASS][19] -> [INCOMPLETE][20] ([fdo#104108]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/shard-skl6/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13984/shard-skl1/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [fdo#110403]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/shard-skl7/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13984/shard-skl5/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_vblank@pipe-b-ts-continuation-suspend: - shard-kbl: [PASS][23] -> [INCOMPLETE][24] ([fdo#103665]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/shard-kbl7/igt@kms_vbl...@pipe-b-ts-continuation-suspend.html [24]: https://intel-
Re: [Intel-gfx] [PATCH] dma-buf/sw_sync: Synchronize signal vs syncpt free
Hi, [This is an automated email] This commit has been processed because it contains a "Fixes:" tag, fixing commit: d3862e44daa7 dma-buf/sw-sync: Fix locking around sync_timeline lists. The bot has tested the following trees: v5.2.8, v4.19.66, v4.14.138, v4.9.189. v5.2.8: Build OK! v4.19.66: Build OK! v4.14.138: Build OK! v4.9.189: Failed to apply! Possible dependencies: Unable to calculate NOTE: The patch will not be queued to stable trees until it is upstream. How should we proceed with this patch? -- Thanks, Sasha ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Fix missing parentheses on TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT
== Series Details ==
Series: drm/i915/tgl: Fix missing parentheses on
TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT
URL : https://patchwork.freedesktop.org/series/65097/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6687 -> Patchwork_13990
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13990/
Known issues
Here are the changes found in Patchwork_13990 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_busy@basic-flip-c:
- fi-kbl-7500u: [PASS][1] -> [SKIP][2] ([fdo#109271] / [fdo#109278])
+2 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13990/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-icl-dsi}: [INCOMPLETE][3] ([fdo#107713] / [fdo#109100]) ->
[PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13990/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@i915_module_load@reload-no-display:
- fi-skl-6260u: [INCOMPLETE][5] -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-skl-6260u/igt@i915_module_l...@reload-no-display.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13990/fi-skl-6260u/igt@i915_module_l...@reload-no-display.html
* igt@i915_selftest@live_requests:
- {fi-icl-guc}: [DMESG-FAIL][7] ([fdo#109644] / [fdo#110464]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-icl-guc/igt@i915_selftest@live_requests.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13990/fi-icl-guc/igt@i915_selftest@live_requests.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [FAIL][9] ([fdo#110627]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13990/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#109485]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13990/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_prop_blob@basic:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-icl-u3/igt@kms_prop_b...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13990/fi-icl-u3/igt@kms_prop_b...@basic.html
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-7500u: [SKIP][15] ([fdo#109271]) -> [PASS][16] +23 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13990/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#109644]: https://bugs.freedesktop.org/show_bug.cgi?id=109644
[fdo#110464]: https://bugs.freedesktop.org/show_bug.cgi?id=110464
[fdo#110627]: https://bugs.freedesktop.org/show_bug.cgi?id=110627
Participating hosts (54 -> 45)
--
Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-apl-guc fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6687 -> Patchwork_13990
CI-20190529: 20190529
CI_DRM_6687: 36e9b72a9b9150ffca7e5613c0e421570b8e92ce @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5128: a49a3a6cdbc4949c0ae8df5f3d8c3e476aefdea1 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13990: efdcc43de9ae39ac50928e204b845d1bff1e5194 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
efdcc43de9ae drm/i915/tgl: Fix missing parentheses on
TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13990/
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Re: [Intel-gfx] [PATCH] drm/i915/tgl: Fix missing parentheses on TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT
On Mon, Aug 12, 2019 at 10:54:05AM -0700, Jose Souza wrote:
In this case we want to apply the mask and then shift so the
parentheses is needed.
SPANK! SPANK! SPANK! Naughty programmer!
Fixes: 9749a5b6c09f ("drm/i915/tgl: Fix the read of the DDI that transcoder is
attached to")
Cc: Lucas De Marchi
Cc: Chris Wilson
Signed-off-by: José Roberto de Souza
Reviewed-by: Lucas De Marchi
Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4a947bd0a294..def6dbdc7e2e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9433,7 +9433,7 @@ enum skl_power_gate {
#define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
#define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
#define TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) (((val) & TRANS_DDI_PORT_MASK)
>> TRANS_DDI_PORT_SHIFT)
-#define TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) (((val) & TGL_TRANS_DDI_PORT_MASK
>> TGL_TRANS_DDI_PORT_SHIFT) - 1)
+#define TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) val) & TGL_TRANS_DDI_PORT_MASK)
>> TGL_TRANS_DDI_PORT_SHIFT) - 1)
#define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
#define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
#define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
--
2.22.0
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Fix missing parentheses on TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT
== Series Details == Series: drm/i915/tgl: Fix missing parentheses on TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT URL : https://patchwork.freedesktop.org/series/65097/ State : warning == Summary == $ dim checkpatch origin/drm-tip efdcc43de9ae drm/i915/tgl: Fix missing parentheses on TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT -:30: WARNING:LONG_LINE: line over 100 characters #30: FILE: drivers/gpu/drm/i915/i915_reg.h:9436: +#define TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) val) & TGL_TRANS_DDI_PORT_MASK) >> TGL_TRANS_DDI_PORT_SHIFT) - 1) total: 0 errors, 1 warnings, 0 checks, 8 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915: Forgo last_fence active request tracking
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Forgo last_fence active request
tracking
URL : https://patchwork.freedesktop.org/series/65096/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6687 -> Patchwork_13989
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_13989:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_execlists:
- {fi-icl-dsi}: NOTRUN -> [DMESG-FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/fi-icl-dsi/igt@i915_selftest@live_execlists.html
Known issues
Here are the changes found in Patchwork_13989 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [PASS][2] -> [DMESG-WARN][3] ([fdo#107724])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
* igt@gem_mmap_gtt@basic-read:
- fi-glk-dsi: [PASS][4] -> [INCOMPLETE][5] ([fdo#103359] /
[k.org#198133])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-glk-dsi/igt@gem_mmap_...@basic-read.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/fi-glk-dsi/igt@gem_mmap_...@basic-read.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [PASS][6] -> [INCOMPLETE][7] ([fdo#107713] /
[fdo#108569])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
* igt@i915_selftest@live_requests:
- fi-byt-j1900: [PASS][8] -> [INCOMPLETE][9] ([fdo#102657])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-byt-j1900/igt@i915_selftest@live_requests.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/fi-byt-j1900/igt@i915_selftest@live_requests.html
* igt@kms_busy@basic-flip-c:
- fi-kbl-7500u: [PASS][10] -> [SKIP][11] ([fdo#109271] /
[fdo#109278]) +2 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-icl-dsi}: [INCOMPLETE][12] ([fdo#107713] / [fdo#109100]) ->
[PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@i915_module_load@reload:
- {fi-icl-u4}:[DMESG-WARN][14] ([fdo#105602]) -> [PASS][15] +1
similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-icl-u4/igt@i915_module_l...@reload.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/fi-icl-u4/igt@i915_module_l...@reload.html
* igt@i915_module_load@reload-no-display:
- fi-skl-6260u: [INCOMPLETE][16] -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-skl-6260u/igt@i915_module_l...@reload-no-display.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/fi-skl-6260u/igt@i915_module_l...@reload-no-display.html
* igt@i915_selftest@live_requests:
- {fi-icl-guc}: [DMESG-FAIL][18] ([fdo#109644] / [fdo#110464]) ->
[PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-icl-guc/igt@i915_selftest@live_requests.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/fi-icl-guc/igt@i915_selftest@live_requests.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [FAIL][20] ([fdo#110627]) -> [PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_prop_blob@basic:
- fi-icl-u3: [DMESG-WARN][22] ([fdo#107724]) -> [PASS][23]
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-icl-u3/igt@kms_prop_b...@basic.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13989/fi-icl-u3/igt@kms_prop_b...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILUR
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/uc: Update copyright and license
== Series Details == Series: drm/i915/uc: Update copyright and license URL : https://patchwork.freedesktop.org/series/65083/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6685_full -> Patchwork_13983_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13983_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13983_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13983_full: ### IGT changes ### Possible regressions * igt@perf_pmu@busy-idle-no-semaphores-rcs0: - shard-skl: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/shard-skl9/igt@perf_...@busy-idle-no-semaphores-rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13983/shard-skl6/igt@perf_...@busy-idle-no-semaphores-rcs0.html * igt@runner@aborted: - shard-apl: NOTRUN -> [FAIL][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13983/shard-apl1/igt@run...@aborted.html Known issues Here are the changes found in Patchwork_13983_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vecs0-s3: - shard-skl: [PASS][4] -> [INCOMPLETE][5] ([fdo#104108]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/shard-skl1/igt@gem_ctx_isolat...@vecs0-s3.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13983/shard-skl2/igt@gem_ctx_isolat...@vecs0-s3.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#111325]) +6 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/shard-iclb8/igt@gem_exec_sched...@preemptive-hang-bsd.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13983/shard-iclb2/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@kms_busy@extended-modeset-hang-newfb-render-c: - shard-apl: [PASS][8] -> [INCOMPLETE][9] ([fdo#103927]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/shard-apl8/igt@kms_b...@extended-modeset-hang-newfb-render-c.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13983/shard-apl3/igt@kms_b...@extended-modeset-hang-newfb-render-c.html * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-untiled: - shard-skl: [PASS][10] -> [FAIL][11] ([fdo#103184] / [fdo#103232] / [fdo#108472]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/shard-skl4/igt@kms_draw_...@draw-method-xrgb2101010-mmap-gtt-untiled.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13983/shard-skl8/igt@kms_draw_...@draw-method-xrgb2101010-mmap-gtt-untiled.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-apl: [PASS][12] -> [DMESG-WARN][13] ([fdo#108566]) +3 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/shard-apl6/igt@kms_f...@flip-vs-suspend-interruptible.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13983/shard-apl2/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-iclb: [PASS][14] -> [FAIL][15] ([fdo#103167]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/shard-iclb7/igt@kms_frontbuffer_track...@fbc-stridechange.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13983/shard-iclb6/igt@kms_frontbuffer_track...@fbc-stridechange.html * igt@kms_frontbuffer_tracking@fbcpsr-suspend: - shard-skl: [PASS][16] -> [INCOMPLETE][17] ([fdo#104108] / [fdo#106978]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/shard-skl7/igt@kms_frontbuffer_track...@fbcpsr-suspend.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13983/shard-skl8/igt@kms_frontbuffer_track...@fbcpsr-suspend.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: [PASS][18] -> [INCOMPLETE][19] ([fdo#103665]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/shard-kbl3/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13983/shard-kbl4/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][20] -> [FAIL][21] ([fdo#108145]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/shard-skl4/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13983/shard-skl8/i
Re: [Intel-gfx] [PATCH] drm/i915/tgl: Fix missing parentheses on TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT
Quoting José Roberto de Souza (2019-08-12 18:54:05)
> In this case we want to apply the mask and then shift so the
> parentheses is needed.
>
> SPANK! SPANK! SPANK! Naughty programmer!
>
> Fixes: 9749a5b6c09f ("drm/i915/tgl: Fix the read of the DDI that transcoder
> is attached to")
> Cc: Lucas De Marchi
> Cc: Chris Wilson
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4a947bd0a294..def6dbdc7e2e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9433,7 +9433,7 @@ enum skl_power_gate {
> #define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
> #define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) <<
> TGL_TRANS_DDI_PORT_SHIFT)
> #define TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val)(((val) &
> TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT)
> -#define TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) (((val) &
> TGL_TRANS_DDI_PORT_MASK >> TGL_TRANS_DDI_PORT_SHIFT) - 1)
> +#define TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) val) &
> TGL_TRANS_DDI_PORT_MASK) >> TGL_TRANS_DDI_PORT_SHIFT) - 1)
That makes the most sense in the possible variations of (:)
Reviewed-by: Chris Wilson
-Chris
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[Intel-gfx] [PATCH] drm/i915/tgl: Fix missing parentheses on TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT
In this case we want to apply the mask and then shift so the
parentheses is needed.
SPANK! SPANK! SPANK! Naughty programmer!
Fixes: 9749a5b6c09f ("drm/i915/tgl: Fix the read of the DDI that transcoder is
attached to")
Cc: Lucas De Marchi
Cc: Chris Wilson
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4a947bd0a294..def6dbdc7e2e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9433,7 +9433,7 @@ enum skl_power_gate {
#define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
#define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
#define TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val)(((val) & TRANS_DDI_PORT_MASK)
>> TRANS_DDI_PORT_SHIFT)
-#define TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) (((val) &
TGL_TRANS_DDI_PORT_MASK >> TGL_TRANS_DDI_PORT_SHIFT) - 1)
+#define TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) val) &
TGL_TRANS_DDI_PORT_MASK) >> TGL_TRANS_DDI_PORT_SHIFT) - 1)
#define TRANS_DDI_MODE_SELECT_MASK(7 << 24)
#define TRANS_DDI_MODE_SELECT_HDMI(0 << 24)
#define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
--
2.22.0
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Re: [Intel-gfx] [PATCH v7 4/4] drm/i915: Add transcoder restriction to PSR2
On Mon, 2019-08-12 at 19:20 +0530, Gupta, Anshuman wrote:
>
> On 7/31/2019 4:17 AM, José Roberto de Souza wrote:
> > According to PSR2_CTL definition on BSpec there is only one
> > instance
> > of PSR2_CTL also ICL display overview state that PSR2 is only
> > supported in EDP transcoder, so now that is possible to have PSR in
> > any transcoder lets add this hardware restriction.
> >
> > BSpec: 7713
> > BSpec: 20584
> > Cc: Dhinakaran Pandiyan
> > Cc: Rodrigo Vivi
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/display/intel_psr.c | 5 +
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index f06b4a0b9e26..526990767c52 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -545,6 +545,11 @@ static bool intel_psr2_config_valid(struct
> > intel_dp *intel_dp,
> > if (!dev_priv->psr.sink_psr2_support)
> > return false;
> >
> > + if (crtc_state->cpu_transcoder != TRANSCODER_EDP) {
> > + DRM_DEBUG_KMS("PSR2 is only supported in EDP
> > transcoder\n");
> > + return false;
> > + }
> > +
> TGL supports PSR2 on TRANSCODER_A, am i missing anything here?
That is right TGL support PSR2 on TRANSCODER_A, this series was being
sent before TGL was made public that is why this why only edp in here,
I will fix that in the next version but anyways there a few more PSR
patches to enable PSR on TGL.
> > /*
> > * DSC and PSR2 cannot be enabled simultaneously. If a
> > requested
> > * resolution requires DSC to be enabled, priority is given to
> > DSC
> >
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[Intel-gfx] [CI 2/2] drm/i915/overlay: Switch to using i915_active tracking
Remove the raw i915_active_request tracking in favour of the higher
level i915_active tracking for the sole purpose of making the lockless
transition easier in later patches.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/display/intel_overlay.c | 129 +--
drivers/gpu/drm/i915/i915_active.h | 19 ---
2 files changed, 64 insertions(+), 84 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c
b/drivers/gpu/drm/i915/display/intel_overlay.c
index 4d3b2086570e..4f78586ee05e 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -191,7 +191,8 @@ struct intel_overlay {
struct overlay_registers __iomem *regs;
u32 flip_addr;
/* flip handling */
- struct i915_active_request last_flip;
+ struct i915_active last_flip;
+ void (*flip_complete)(struct intel_overlay *ovl);
};
static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv,
@@ -217,30 +218,25 @@ static void i830_overlay_clock_gating(struct
drm_i915_private *dev_priv,
PCI_DEVFN(0, 0), I830_CLOCK_GATE, val);
}
-static void intel_overlay_submit_request(struct intel_overlay *overlay,
-struct i915_request *rq,
-i915_active_retire_fn retire)
+static struct i915_request *
+alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay
*))
{
- GEM_BUG_ON(i915_active_request_peek(&overlay->last_flip,
- &overlay->i915->drm.struct_mutex));
- i915_active_request_set_retire_fn(&overlay->last_flip, retire,
- &overlay->i915->drm.struct_mutex);
- __i915_active_request_set(&overlay->last_flip, rq);
- i915_request_add(rq);
-}
+ struct i915_request *rq;
+ int err;
-static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
-struct i915_request *rq,
-i915_active_retire_fn retire)
-{
- intel_overlay_submit_request(overlay, rq, retire);
- return i915_active_request_retire(&overlay->last_flip,
- &overlay->i915->drm.struct_mutex);
-}
+ overlay->flip_complete = fn;
-static struct i915_request *alloc_request(struct intel_overlay *overlay)
-{
- return i915_request_create(overlay->context);
+ rq = i915_request_create(overlay->context);
+ if (IS_ERR(rq))
+ return rq;
+
+ err = i915_active_ref(&overlay->last_flip, rq->fence.context, rq);
+ if (err) {
+ i915_request_add(rq);
+ return ERR_PTR(err);
+ }
+
+ return rq;
}
/* overlay needs to be disable in OCMD reg */
@@ -252,7 +248,7 @@ static int intel_overlay_on(struct intel_overlay *overlay)
WARN_ON(overlay->active);
- rq = alloc_request(overlay);
+ rq = alloc_request(overlay, NULL);
if (IS_ERR(rq))
return PTR_ERR(rq);
@@ -273,7 +269,9 @@ static int intel_overlay_on(struct intel_overlay *overlay)
*cs++ = MI_NOOP;
intel_ring_advance(rq, cs);
- return intel_overlay_do_wait_request(overlay, rq, NULL);
+ i915_request_add(rq);
+
+ return i915_active_wait(&overlay->last_flip);
}
static void intel_overlay_flip_prepare(struct intel_overlay *overlay,
@@ -317,7 +315,7 @@ static int intel_overlay_continue(struct intel_overlay
*overlay,
if (tmp & (1 << 17))
DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
- rq = alloc_request(overlay);
+ rq = alloc_request(overlay, NULL);
if (IS_ERR(rq))
return PTR_ERR(rq);
@@ -332,8 +330,7 @@ static int intel_overlay_continue(struct intel_overlay
*overlay,
intel_ring_advance(rq, cs);
intel_overlay_flip_prepare(overlay, vma);
-
- intel_overlay_submit_request(overlay, rq, NULL);
+ i915_request_add(rq);
return 0;
}
@@ -354,20 +351,13 @@ static void intel_overlay_release_old_vma(struct
intel_overlay *overlay)
}
static void
-intel_overlay_release_old_vid_tail(struct i915_active_request *active,
- struct i915_request *rq)
+intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
{
- struct intel_overlay *overlay =
- container_of(active, typeof(*overlay), last_flip);
-
intel_overlay_release_old_vma(overlay);
}
-static void intel_overlay_off_tail(struct i915_active_request *active,
- struct i915_request *rq)
+static void intel_overlay_off_tail(struct intel_overlay *overlay)
{
- struct intel_overlay *overlay =
- container_of(active, typeof(*overlay), last_flip);
struct drm_i915_private *dev_priv = overlay->i915;
[Intel-gfx] [CI 1/2] drm/i915: Forgo last_fence active request tracking
We were using the last_fence to track the last request that used this
vma that might be interpreted by a fence register and forced ourselves
to wait for this request before modifying any fence register that
overlapped our vma. Due to requirement that we need to track any XY_BLT
command, linear or tiled, this in effect meant that we have to track the
vma for its active lifespan anyway, so we can forgo the explicit
last_fence tracking and just use the whole vma->active.
Another solution would be to pipeline the register updates, and would
help resolve some long running stalls for gen3 (but only gen 2 and 3!)
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +---
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 ++
drivers/gpu/drm/i915/i915_gem_gtt.c | 1 -
drivers/gpu/drm/i915/i915_vma.c | 13 -
drivers/gpu/drm/i915/i915_vma.h | 1 -
5 files changed, 3 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index b616ba0e0da0..2c640987c24d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -212,9 +212,7 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object
*obj)
}
}
if (vma->fence)
- seq_printf(m, " , fence: %d%s",
- vma->fence->id,
- i915_active_request_isset(&vma->last_fence)
? "*" : "");
+ seq_printf(m, " , fence: %d", vma->fence->id);
seq_puts(m, ")");
spin_lock(&obj->vma.lock);
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index bcac359ec661..c9654f1a468f 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -230,16 +230,14 @@ static int fence_update(struct i915_fence_reg *fence,
i915_gem_object_get_tiling(vma->obj)))
return -EINVAL;
- ret = i915_active_request_retire(&vma->last_fence,
-&vma->obj->base.dev->struct_mutex);
+ ret = i915_active_wait(&vma->active);
if (ret)
return ret;
}
old = xchg(&fence->vma, NULL);
if (old) {
- ret = i915_active_request_retire(&old->last_fence,
-&old->obj->base.dev->struct_mutex);
+ ret = i915_active_wait(&old->active);
if (ret) {
fence->vma = old;
return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 72a227c43e35..e07c1ae971d7 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1867,7 +1867,6 @@ static struct i915_vma *pd_vma_create(struct gen6_ppgtt
*ppgtt, int size)
return ERR_PTR(-ENOMEM);
i915_active_init(i915, &vma->active, NULL, NULL);
- INIT_ACTIVE_REQUEST(&vma->last_fence);
vma->vm = &ggtt->vm;
vma->ops = &pd_vma_ops;
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 4183b0e10324..8be1bbef40e5 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -120,7 +120,6 @@ vma_create(struct drm_i915_gem_object *obj,
i915_active_init(vm->i915, &vma->active,
__i915_vma_active, __i915_vma_retire);
- INIT_ACTIVE_REQUEST(&vma->last_fence);
/* Declare ourselves safe for use inside shrinkers */
if (IS_ENABLED(CONFIG_LOCKDEP)) {
@@ -802,8 +801,6 @@ static void __i915_vma_destroy(struct i915_vma *vma)
GEM_BUG_ON(vma->node.allocated);
GEM_BUG_ON(vma->fence);
- GEM_BUG_ON(i915_active_request_isset(&vma->last_fence));
-
mutex_lock(&vma->vm->mutex);
list_del(&vma->vm_link);
mutex_unlock(&vma->vm->mutex);
@@ -928,9 +925,6 @@ int i915_vma_move_to_active(struct i915_vma *vma,
obj->read_domains |= I915_GEM_GPU_DOMAINS;
obj->mm.dirty = true;
- if (flags & EXEC_OBJECT_NEEDS_FENCE)
- __i915_active_request_set(&vma->last_fence, rq);
-
GEM_BUG_ON(!i915_vma_is_active(vma));
return 0;
}
@@ -961,14 +955,7 @@ int i915_vma_unbind(struct i915_vma *vma)
* before we are finished).
*/
__i915_vma_pin(vma);
-
ret = i915_active_wait(&vma->active);
- if (ret)
- goto unpin;
-
- ret = i915_active_request_retire(&vma->last_fence,
- &vma->vm->i915->drm.struct_mutex);
-unpin:
__i915_vma_unpin(vma);
if (ret)
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/icl: Implement gen11 flush including tile cache
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Implement gen11 flush
including tile cache
URL : https://patchwork.freedesktop.org/series/65094/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6687 -> Patchwork_13988
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13988/
Known issues
Here are the changes found in Patchwork_13988 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_active:
- fi-bsw-n3050: [PASS][1] -> [DMESG-WARN][2] ([fdo#111373])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-bsw-n3050/igt@i915_selftest@live_active.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13988/fi-bsw-n3050/igt@i915_selftest@live_active.html
* igt@i915_selftest@live_gtt:
- fi-glk-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#103359] /
[k.org#198133])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-glk-dsi/igt@i915_selftest@live_gtt.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13988/fi-glk-dsi/igt@i915_selftest@live_gtt.html
* igt@kms_busy@basic-flip-c:
- fi-kbl-7500u: [PASS][5] -> [SKIP][6] ([fdo#109271] / [fdo#109278])
+2 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13988/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
* igt@vgem_basic@second-client:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724]) +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-icl-u3/igt@vgem_ba...@second-client.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13988/fi-icl-u3/igt@vgem_ba...@second-client.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-icl-dsi}: [INCOMPLETE][9] ([fdo#107713] / [fdo#109100]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13988/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@i915_module_load@reload-no-display:
- fi-skl-6260u: [INCOMPLETE][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-skl-6260u/igt@i915_module_l...@reload-no-display.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13988/fi-skl-6260u/igt@i915_module_l...@reload-no-display.html
* igt@i915_selftest@live_requests:
- {fi-icl-guc}: [DMESG-FAIL][13] ([fdo#109644] / [fdo#110464]) ->
[PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-icl-guc/igt@i915_selftest@live_requests.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13988/fi-icl-guc/igt@i915_selftest@live_requests.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [FAIL][15] ([fdo#110627]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13988/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_prop_blob@basic:
- {fi-icl-u4}:[DMESG-WARN][17] ([fdo#105602]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-icl-u4/igt@kms_prop_b...@basic.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13988/fi-icl-u4/igt@kms_prop_b...@basic.html
- fi-icl-u3: [DMESG-WARN][19] ([fdo#107724]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-icl-u3/igt@kms_prop_b...@basic.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13988/fi-icl-u3/igt@kms_prop_b...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109644]: https://bugs.freedesktop.org/show_bug.cgi?id=109644
[fdo#110464]: https://bugs.freedesktop.org/show_bug.cgi?id=110464
[fdo#110627]: https://bugs.freedesktop.org/show_bug.cgi?id=110627
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046
[fdo#111373]: https://bugs.freedesktop.org/show_bug.cgi?id=111373
[k.org#198133]: https://bugz
Re: [Intel-gfx] [PATCH] dma-buf/sw_sync: Synchronize signal vs syncpt free
Am 12.08.19 um 17:42 schrieb Chris Wilson:
> During release of the syncpt, we remove it from the list of syncpt and
> the tree, but only if it is not already been removed. However, during
> signaling, we first remove the syncpt from the list. So, if we
> concurrently free and signal the syncpt, the free may decide that it is
> not part of the tree and immediately free itself -- meanwhile the
> signaler goes onto to use the now freed datastructure.
>
> In particular, we get struct by commit 0e2f733addbf ("dma-buf: make
> dma_fence structure a bit smaller v2") as the cb_list is immediately
> clobbered by the kfree_rcu.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111381
> Fixes: d3862e44daa7 ("dma-buf/sw-sync: Fix locking around sync_timeline
> lists")
> References: 0e2f733addbf ("dma-buf: make dma_fence structure a bit smaller
> v2")
> Signed-off-by: Chris Wilson
> Cc: Sumit Semwal
> Cc: Sean Paul
> Cc: Gustavo Padovan
> Cc: Christian König
> Cc: # v4.14+
Acked-by: Christian König
> ---
> drivers/dma-buf/sw_sync.c | 13 +
> 1 file changed, 5 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/dma-buf/sw_sync.c b/drivers/dma-buf/sw_sync.c
> index 051f6c2873c7..27b1d549ed38 100644
> --- a/drivers/dma-buf/sw_sync.c
> +++ b/drivers/dma-buf/sw_sync.c
> @@ -132,17 +132,14 @@ static void timeline_fence_release(struct dma_fence
> *fence)
> {
> struct sync_pt *pt = dma_fence_to_sync_pt(fence);
> struct sync_timeline *parent = dma_fence_parent(fence);
> + unsigned long flags;
>
> + spin_lock_irqsave(fence->lock, flags);
> if (!list_empty(&pt->link)) {
> - unsigned long flags;
> -
> - spin_lock_irqsave(fence->lock, flags);
> - if (!list_empty(&pt->link)) {
> - list_del(&pt->link);
> - rb_erase(&pt->node, &parent->pt_tree);
> - }
> - spin_unlock_irqrestore(fence->lock, flags);
> + list_del(&pt->link);
> + rb_erase(&pt->node, &parent->pt_tree);
> }
> + spin_unlock_irqrestore(fence->lock, flags);
>
> sync_timeline_put(parent);
> dma_fence_free(fence);
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for dma-buf/sw_sync: Synchronize signal vs syncpt free
== Series Details ==
Series: dma-buf/sw_sync: Synchronize signal vs syncpt free
URL : https://patchwork.freedesktop.org/series/65092/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6687 -> Patchwork_13987
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13987/
Known issues
Here are the changes found in Patchwork_13987 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_sync@basic-many-each:
- fi-snb-2600:[PASS][1] -> [INCOMPLETE][2] ([fdo#105411])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-snb-2600/igt@gem_s...@basic-many-each.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13987/fi-snb-2600/igt@gem_s...@basic-many-each.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [PASS][3] -> [DMESG-FAIL][4] ([fdo#08])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13987/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-7500u: [PASS][5] -> [WARN][6] ([fdo#109483])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13987/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
Possible fixes
* igt@i915_module_load@reload-no-display:
- fi-skl-6260u: [INCOMPLETE][7] -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-skl-6260u/igt@i915_module_l...@reload-no-display.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13987/fi-skl-6260u/igt@i915_module_l...@reload-no-display.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [FAIL][9] ([fdo#110627]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13987/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#109485]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13987/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_prop_blob@basic:
- {fi-icl-u4}:[DMESG-WARN][13] ([fdo#105602]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-icl-u4/igt@kms_prop_b...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13987/fi-icl-u4/igt@kms_prop_b...@basic.html
- fi-icl-u3: [DMESG-WARN][15] ([fdo#107724]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-icl-u3/igt@kms_prop_b...@basic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13987/fi-icl-u3/igt@kms_prop_b...@basic.html
Warnings
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-kbl-guc: [SKIP][17] ([fdo#109271]) -> [FAIL][18] ([fdo#107707])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6687/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13987/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107707]: https://bugs.freedesktop.org/show_bug.cgi?id=107707
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#110627]: https://bugs.freedesktop.org/show_bug.cgi?id=110627
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
Participating hosts (54 -> 46)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6687 -> Patchwork_13987
CI-20190529: 20190529
CI_DRM_6687: 36e9b72a9b9150ffca7e5613c0e421570b8e92ce @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5128: a49a3a6cdbc4949c0ae8df5f3d8c3e476aefdea1 @
git://anong
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/icl: Implement gen11 flush including tile cache
== Series Details == Series: series starting with [1/2] drm/i915/icl: Implement gen11 flush including tile cache URL : https://patchwork.freedesktop.org/series/65094/ State : warning == Summary == $ dim checkpatch origin/drm-tip 34ef48906b2c drm/i915/icl: Implement gen11 flush including tile cache -:27: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #27: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:211: +#define PIPE_CONTROL_TILE_CACHE_FLUSH(1<<28) /* gen11+ */ ^ total: 0 errors, 0 warnings, 1 checks, 82 lines checked a3c8d341c403 drm/i915/icl: Add command cache invalidate -:20: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #20: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:211: +#define PIPE_CONTROL_COMMAND_CACHE_INVALIDATE(1<<29) /* gen11+ */ ^ total: 0 errors, 0 warnings, 1 checks, 14 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 29/37] drm/i915: Introduce DRM_I915_GEM_MMAP_OFFSET
On Tue, Jul 30, 2019 at 6:22 PM Daniel Vetter wrote: > On Tue, Jul 30, 2019 at 03:28:11PM +0100, Matthew Auld wrote: > > On 30/07/2019 10:49, Daniel Vetter wrote: > > > On Thu, Jun 27, 2019 at 09:56:25PM +0100, Matthew Auld wrote: > > > > From: Abdiel Janulgue > > > > > > > > Add a new CPU mmap implementation that allows multiple fault handlers > > > > that depends on the object's backing pages. > > > > > > > > Note that we multiplex mmap_gtt and mmap_offset through the same ioctl, > > > > and use the zero extending behaviour of drm to differentiate between > > > > them, when we inspect the flags. > > > > > > > > Signed-off-by: Abdiel Janulgue > > > > Signed-off-by: Matthew Auld > > > > Cc: Joonas Lahtinen > > > > > > So I thought that the plan is to reject invalid mmaps, i.e. mmap modes > > > which are not compatibale with all placement options. Given that, why do > > > we need this? > > > > We are meant to reject anything !wc for LMEM. There were some patches for > > that but I guess got lost under the radar... > > > > > > > > - cpu mmap with all the flags still keep working, as long as the only > > >placement you select is smem. > > > > > > - for lmem/stolen the only option we have is a wc mapping, either through > > >the pci bar or through the gtt. So for objects only sitting in there > > >also no problem, we can just keep using the current gtt mmap stuff (but > > >redirect it internally). > > > > > > - that leaves us with objects which can move around. Only option allows is > > >WC, and the gtt mmap ioctl does that already. When the object is in > > > smem > > >we'll need to redirect it to a cpu wc mmap, but I think we need to do > > >that anyway. > > > > So for legacy, gtt_mmap will still go through the aperture, otherwise if > > LMEM is supported then there is no aperture, so we just wc mmap via cpu or > > LMEMBAR depending on the final object placement. And cpu_mmap still works if > > we don't care about LMEM. Hmm, so do we even need most of the previous patch > > then? ALso does that mean we also have to track the placement of an object > > in igt? > > > > gem_mmap__wc: > > > > if (supports_lmem(dev)) > > gtt_mmap(); > > else > > gem_mmap(wc); > > > > gem_mmap__wc: > > > > if (placement_contains(obj, LMEM)) > > gtt_mmap(); > > else > > gem_mmap(wc); > > > > ? > > Well if you want cpu wc mmaps, then just allocate it as smem ... we might > need a new gem_mmap__lmem I guess to exercise all the possible ways to get > at stuff in lmem (including when it migrates around underneath us while we > access it through the mmap). I wouldn't try too hard to smash all these > use/testcases into one. Chatted a lot with Joonas today, and realized I missread outright what this does. Looking at the end result I think it's all nicely aligned with other (discrete/ttm) drivers, so all good from that point of view. Still not sure whether it's really a good idea to do this fairly minor uapi cleanup tied in with lmem. But I guess we committed to that now, so welp ... -Daniel > > > So not really seeing what the uapi problem is you're trying to solve here? > > > > > > Can you pls explain why we need this? > > > > The naming of gtt_mmap seemed confusing, since there is no aperture, and > > having one mmap ioctl to cover both smem and lmem seemed like a nice > > idea...also I think umd's stopped using gtt_mmap(or were told to?) but maybe > > those aren't good enough reasons. > > We stopped using gtt mmap because for many cases cpu WC mmap is faster. > > Wrt having a clean slate: Not sure why this would benefit us, we just > diverge a bit more from how this works on !lmem, so a bit more complexity > (not much) everywhere for not much gain. > > I'm also not sure whether there will be a whole lot of uses of such a > magic LMEMBAR wc mapping. It's probably slow for the exact same reasons > gtt mmap is slow. > -Daniel > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/icl: Implement gen11 flush including tile cache
Quoting Mika Kuoppala (2019-08-12 17:01:07)
> Add tile cache flushing for gen11. To relive us from the
> burden of previous obsolete workarounds, make a dedicated
> flush/invalidate callback for gen11.
>
> To fortify an independent single flush, do post
> sync op as there are indications that without it
> we don't flush everything. This should also make this
> callback more readily usable in tgl (see l3 fabric flush).
>
> Cc: Chris Wilson
> Cc: Daniele Ceraolo Spurio
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
> drivers/gpu/drm/i915/gt/intel_lrc.c | 63 +++-
> 2 files changed, 63 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index 6a0879c27d14..929a17e54f2c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -208,6 +208,7 @@
> #define DISPLAY_PLANE_A (0<<20)
> #define DISPLAY_PLANE_B (1<<20)
> #define GFX_OP_PIPE_CONTROL(len)
> ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
> +#define PIPE_CONTROL_TILE_CACHE_FLUSH(1<<28) /*
> gen11+ */
Ack.
> #define PIPE_CONTROL_FLUSH_L3(1<<27)
> #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
> #define PIPE_CONTROL_MMIO_WRITE (1<<23)
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index b97047d58d3d..891db3c933c9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -2655,6 +2655,64 @@ static int gen8_emit_flush_render(struct i915_request
> *request,
> return 0;
> }
>
> +static int gen11_emit_flush_render(struct i915_request *request,
> + u32 mode)
> +{
> + struct intel_engine_cs *engine = request->engine;
> + const u32 scratch_addr =
> + intel_gt_scratch_offset(engine->gt,
> + INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
> +
> + if (mode & EMIT_FLUSH) {
> + u32 *cs;
> + u32 flags = 0;
> +
> + flags |= PIPE_CONTROL_CS_STALL;
> +
> + flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> + flags |= PIPE_CONTROL_FLUSH_ENABLE;
> + flags |= PIPE_CONTROL_QW_WRITE;
> + flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
Ok.
> +
> + cs = intel_ring_begin(request, 6);
> + if (IS_ERR(cs))
> + return PTR_ERR(cs);
> +
> + cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
> +
Personally, I wouldn't leave a newline here.
> + intel_ring_advance(request, cs);
> + }
> +
> + if (mode & EMIT_INVALIDATE) {
> + u32 *cs;
> + u32 flags = 0;
> +
> + flags |= PIPE_CONTROL_CS_STALL;
> +
> + flags |= PIPE_CONTROL_TLB_INVALIDATE;
> + flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
> + flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
> + flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
> + flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
> + flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
> + flags |= PIPE_CONTROL_QW_WRITE;
> + flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
Ok.
> +
> + cs = intel_ring_begin(request, 6);
> + if (IS_ERR(cs))
> + return PTR_ERR(cs);
> +
> + cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
> +
> + intel_ring_advance(request, cs);
> + }
> +
> + return 0;
> +}
> +
> /*
> * Reserve space for 2 NOOPs at the end of each request to be
> * used as a workaround for not being allowed to do lite
> @@ -2829,7 +2887,10 @@ int intel_execlists_submission_setup(struct
> intel_engine_cs *engine)
> logical_ring_default_irqs(engine);
>
> if (engine->class == RENDER_CLASS) {
> - engine->emit_flush = gen8_emit_flush_render;
> + if (INTEL_GEN(engine->i915) >= 11)
> + engine->emit_flush = gen11_emit_flush_render;
> + else
> + engine->emit_flush = gen8_emit_flush_render;
> engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
No fini breadcrumb flush?
-Chris
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Re: [Intel-gfx] [PATCH 0/5] Tiger Lake: DKL phy PLLs
+Vandita On Thu, Jul 25, 2019 at 4:57 PM Lucas De Marchi wrote: > > Mostly the same patches as https://patchwork.freedesktop.org/series/63670/. > Rebased. > > Lucas De Marchi (2): > drm/i915/tgl: re-indent code to prepare for DKL changes > drm/i915/tgl: start adding the DKL PLLs to use on TC ports Vandita, can you review these 2 patches since they are related to yours? Thanks Lucas De Marchi > > Vandita Kulkarni (3): > drm/i915/tgl: Add DKL phy pll registers > drm/i915/tgl: Add DKL phy pll state calculations > drm/i915/tgl: Add support for dkl pll write > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 335 ++ > drivers/gpu/drm/i915/i915_reg.h | 94 + > 2 files changed, 368 insertions(+), 61 deletions(-) > > -- > 2.21.0 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Lucas De Marchi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for dma-buf/sw_sync: Synchronize signal vs syncpt free
== Series Details ==
Series: dma-buf/sw_sync: Synchronize signal vs syncpt free
URL : https://patchwork.freedesktop.org/series/65092/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
857ced2942e5 dma-buf/sw_sync: Synchronize signal vs syncpt free
-:22: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#22:
References: 0e2f733addbf ("dma-buf: make dma_fence structure a bit smaller v2")
-:22: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 0e2f733addbf ("dma-buf: make
dma_fence structure a bit smaller v2")'
#22:
References: 0e2f733addbf ("dma-buf: make dma_fence structure a bit smaller v2")
total: 1 errors, 1 warnings, 0 checks, 22 lines checked
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/icl: Add command cache invalidate
Quoting Mika Kuoppala (2019-08-12 17:01:08) > On the set of invalidations, we need to add command > cache invalidate as a new domain. Found the bit, left none the wiser, but just based on the invalidate keyword it fits our mo. > Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/icl: Implement gen11 flush including tile cache
Add tile cache flushing for gen11. To relive us from the
burden of previous obsolete workarounds, make a dedicated
flush/invalidate callback for gen11.
To fortify an independent single flush, do post
sync op as there are indications that without it
we don't flush everything. This should also make this
callback more readily usable in tgl (see l3 fabric flush).
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 63 +++-
2 files changed, 63 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 6a0879c27d14..929a17e54f2c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -208,6 +208,7 @@
#define DISPLAY_PLANE_A (0<<20)
#define DISPLAY_PLANE_B (1<<20)
#define GFX_OP_PIPE_CONTROL(len)
((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
+#define PIPE_CONTROL_TILE_CACHE_FLUSH(1<<28) /*
gen11+ */
#define PIPE_CONTROL_FLUSH_L3(1<<27)
#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
#define PIPE_CONTROL_MMIO_WRITE (1<<23)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b97047d58d3d..891db3c933c9 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2655,6 +2655,64 @@ static int gen8_emit_flush_render(struct i915_request
*request,
return 0;
}
+static int gen11_emit_flush_render(struct i915_request *request,
+ u32 mode)
+{
+ struct intel_engine_cs *engine = request->engine;
+ const u32 scratch_addr =
+ intel_gt_scratch_offset(engine->gt,
+ INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
+
+ if (mode & EMIT_FLUSH) {
+ u32 *cs;
+ u32 flags = 0;
+
+ flags |= PIPE_CONTROL_CS_STALL;
+
+ flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
+ flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
+ flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+ flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
+ flags |= PIPE_CONTROL_FLUSH_ENABLE;
+ flags |= PIPE_CONTROL_QW_WRITE;
+ flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
+
+ cs = intel_ring_begin(request, 6);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
+
+ intel_ring_advance(request, cs);
+ }
+
+ if (mode & EMIT_INVALIDATE) {
+ u32 *cs;
+ u32 flags = 0;
+
+ flags |= PIPE_CONTROL_CS_STALL;
+
+ flags |= PIPE_CONTROL_TLB_INVALIDATE;
+ flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
+ flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
+ flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
+ flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
+ flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
+ flags |= PIPE_CONTROL_QW_WRITE;
+ flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
+
+ cs = intel_ring_begin(request, 6);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
+
+ intel_ring_advance(request, cs);
+ }
+
+ return 0;
+}
+
/*
* Reserve space for 2 NOOPs at the end of each request to be
* used as a workaround for not being allowed to do lite
@@ -2829,7 +2887,10 @@ int intel_execlists_submission_setup(struct
intel_engine_cs *engine)
logical_ring_default_irqs(engine);
if (engine->class == RENDER_CLASS) {
- engine->emit_flush = gen8_emit_flush_render;
+ if (INTEL_GEN(engine->i915) >= 11)
+ engine->emit_flush = gen11_emit_flush_render;
+ else
+ engine->emit_flush = gen8_emit_flush_render;
engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
}
--
2.17.1
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[Intel-gfx] [PATCH 2/2] drm/i915/icl: Add command cache invalidate
On the set of invalidations, we need to add command cache invalidate as a new domain. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 + drivers/gpu/drm/i915/gt/intel_lrc.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h index 929a17e54f2c..86e00a2db8a4 100644 --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h @@ -208,6 +208,7 @@ #define DISPLAY_PLANE_A (0<<20) #define DISPLAY_PLANE_B (1<<20) #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2)) +#define PIPE_CONTROL_COMMAND_CACHE_INVALIDATE(1<<29) /* gen11+ */ #define PIPE_CONTROL_TILE_CACHE_FLUSH(1<<28) /* gen11+ */ #define PIPE_CONTROL_FLUSH_L3(1<<27) #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 891db3c933c9..27f1445fed40 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2692,6 +2692,7 @@ static int gen11_emit_flush_render(struct i915_request *request, flags |= PIPE_CONTROL_CS_STALL; + flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE; flags |= PIPE_CONTROL_TLB_INVALIDATE; flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] dma-buf/sw_sync: Synchronize signal vs syncpt free
During release of the syncpt, we remove it from the list of syncpt and
the tree, but only if it is not already been removed. However, during
signaling, we first remove the syncpt from the list. So, if we
concurrently free and signal the syncpt, the free may decide that it is
not part of the tree and immediately free itself -- meanwhile the
signaler goes onto to use the now freed datastructure.
In particular, we get struct by commit 0e2f733addbf ("dma-buf: make
dma_fence structure a bit smaller v2") as the cb_list is immediately
clobbered by the kfree_rcu.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111381
Fixes: d3862e44daa7 ("dma-buf/sw-sync: Fix locking around sync_timeline lists")
References: 0e2f733addbf ("dma-buf: make dma_fence structure a bit smaller v2")
Signed-off-by: Chris Wilson
Cc: Sumit Semwal
Cc: Sean Paul
Cc: Gustavo Padovan
Cc: Christian König
Cc: # v4.14+
---
drivers/dma-buf/sw_sync.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/dma-buf/sw_sync.c b/drivers/dma-buf/sw_sync.c
index 051f6c2873c7..27b1d549ed38 100644
--- a/drivers/dma-buf/sw_sync.c
+++ b/drivers/dma-buf/sw_sync.c
@@ -132,17 +132,14 @@ static void timeline_fence_release(struct dma_fence
*fence)
{
struct sync_pt *pt = dma_fence_to_sync_pt(fence);
struct sync_timeline *parent = dma_fence_parent(fence);
+ unsigned long flags;
+ spin_lock_irqsave(fence->lock, flags);
if (!list_empty(&pt->link)) {
- unsigned long flags;
-
- spin_lock_irqsave(fence->lock, flags);
- if (!list_empty(&pt->link)) {
- list_del(&pt->link);
- rb_erase(&pt->node, &parent->pt_tree);
- }
- spin_unlock_irqrestore(fence->lock, flags);
+ list_del(&pt->link);
+ rb_erase(&pt->node, &parent->pt_tree);
}
+ spin_unlock_irqrestore(fence->lock, flags);
sync_timeline_put(parent);
dma_fence_free(fence);
--
2.23.0.rc1
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Re: [Intel-gfx] [PATCH 11/18] drm/i915/overlay: Switch to using i915_active tracking
On Mon, 12 Aug 2019 at 14:41, Chris Wilson wrote: > > Remove the raw i915_active_request tracking in favour of the higher > level i915_active tracking for the sole purpose of making the lockless > transition easier in later patches. > > Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/execlists: Lift process_csb() out of the irq-off spinlock
Hi Chris,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.3-rc4]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-execlists-Lift-process_csb-out-of-the-irq-off-spinlock/20190812-211057
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-10) 7.4.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c: In function 'schedule_in':
>> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:541:2: error: implicit
>> declaration of function 'intel_context_inflight_inc'; did you mean
>> 'intel_context_inflight_count'? [-Werror=implicit-function-declaration]
intel_context_inflight_inc(rq->hw_context);
^~
intel_context_inflight_count
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c: In function
'schedule_out':
>> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:551:2: error: implicit
>> declaration of function 'intel_context_inflight_dec'; did you mean
>> 'intel_context_inflight'? [-Werror=implicit-function-declaration]
intel_context_inflight_dec(rq->hw_context);
^~
intel_context_inflight
cc1: some warnings being treated as errors
vim +541 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
77f0d0e925e8a0 drivers/gpu/drm/i915/i915_guc_submission.cChris Wilson
2017-05-17 534
22b7a426bbe1eb drivers/gpu/drm/i915/intel_guc_submission.c Chris Wilson
2019-06-20 535 static struct i915_request *schedule_in(struct i915_request
*rq, int idx)
2a694feb93556e drivers/gpu/drm/i915/intel_guc_submission.c Chris Wilson
2018-04-03 536 {
22b7a426bbe1eb drivers/gpu/drm/i915/intel_guc_submission.c Chris Wilson
2019-06-20 537 trace_i915_request_in(rq, idx);
22b7a426bbe1eb drivers/gpu/drm/i915/intel_guc_submission.c Chris Wilson
2019-06-20 538
22b7a426bbe1eb drivers/gpu/drm/i915/intel_guc_submission.c Chris Wilson
2019-06-20 539 if (!rq->hw_context->inflight)
22b7a426bbe1eb drivers/gpu/drm/i915/intel_guc_submission.c Chris Wilson
2019-06-20 540 rq->hw_context->inflight = rq->engine;
22b7a426bbe1eb drivers/gpu/drm/i915/intel_guc_submission.c Chris Wilson
2019-06-20 @541 intel_context_inflight_inc(rq->hw_context);
c7302f204490f3 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c Chris Wilson
2019-08-08 542 intel_gt_pm_get(rq->engine->gt);
22b7a426bbe1eb drivers/gpu/drm/i915/intel_guc_submission.c Chris Wilson
2019-06-20 543
22b7a426bbe1eb drivers/gpu/drm/i915/intel_guc_submission.c Chris Wilson
2019-06-20 544 return i915_request_get(rq);
2a694feb93556e drivers/gpu/drm/i915/intel_guc_submission.c Chris Wilson
2018-04-03 545 }
2a694feb93556e drivers/gpu/drm/i915/intel_guc_submission.c Chris Wilson
2018-04-03 546
22b7a426bbe1eb drivers/gpu/drm/i915/intel_guc_submission.c Chris Wilson
2019-06-20 547 static void schedule_out(struct i915_request *rq)
2a694feb93556e drivers/gpu/drm/i915/intel_guc_submission.c Chris Wilson
2018-04-03 548 {
22b7a426bbe1eb drivers/gpu/drm/i915/intel_guc_submission.c Chris Wilson
2019-06-20 549 trace_i915_request_out(rq);
22b7a426bbe1eb drivers/gpu/drm/i915/intel_guc_submission.c Chris Wilson
2019-06-20 550
22b7a426bbe1eb drivers/gpu/drm/i915/intel_guc_submission.c Chris Wilson
2019-06-20 @551 intel_context_inflight_dec(rq->hw_context);
22b7a426bbe1eb drivers/gpu/drm/i915/intel_guc_submission.c Chris Wilson
2019-06-20 552 if (!intel_context_inflight_count(rq->hw_context))
22b7a426bbe1eb drivers/gpu/drm/i915/intel_guc_submission.c Chris Wilson
2019-06-20 553 rq->hw_context->inflight = NULL;
22b7a426bbe1eb drivers/gpu/drm/i915/intel_guc_submission.c Chris Wilson
2019-06-20 554
c7302f204490f3 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c Chris Wilson
2019-08-08 555 intel_gt_pm_put(rq->engine->gt);
22b7a426bbe1eb drivers/gpu/drm/i915/intel_guc_submission.c Chris Wilson
2019-06-20 556 i915_request_put(rq);
2a694feb93556e drivers/gpu/drm/i915/intel_guc_submission.c Chris Wilson
2018-04-03 557 }
2a694feb93556e drivers/gpu/drm/i915/intel_guc_submission.c Chris Wilson
2018-04-03 558
:: The code at line 541 was first introduced by commit
:: 22b7a426bbe1ebe1520f92da4cd1617d1e1b5fc4 drm/i915/execlists:
Preempt-to-busy
:: TO: Chris Wilson
[Intel-gfx] [PATCH i-g-t] i915/gem_eio: Restrict number of batches of submitted
Make sure we don't block while setting up the stress case before the reset by only submitting less batches than would fill the ring. References: https://bugs.freedesktop.org/show_bug.cgi?id=111379 Signed-off-by: Chris Wilson --- tests/i915/gem_eio.c | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/tests/i915/gem_eio.c b/tests/i915/gem_eio.c index dcbcefa97..9b086a039 100644 --- a/tests/i915/gem_eio.c +++ b/tests/i915/gem_eio.c @@ -734,6 +734,11 @@ static void reset_stress(int fd, uint32_t ctx0, .flags = engine, }; igt_stats_t stats; + int max; + + max = gem_measure_ring_inflight(fd, engine, 0); + max = max / 2 - 1; /* assume !execlists and a shared ring */ + igt_require(max > 0); gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe)); @@ -755,11 +760,11 @@ static void reset_stress(int fd, uint32_t ctx0, hang = spin_sync(fd, ctx0, engine); execbuf.rsvd1 = ctx; - for (i = 0; i < 10; i++) + for (i = 0; i < max; i++) gem_execbuf(fd, &execbuf); execbuf.rsvd1 = ctx0; - for (i = 0; i < 10; i++) + for (i = 0; i < max; i++) gem_execbuf(fd, &execbuf); /* Wedge after a small delay. */ @@ -777,11 +782,11 @@ static void reset_stress(int fd, uint32_t ctx0, * both contexts. */ execbuf.rsvd1 = ctx; - for (i = 0; i < 5; i++) + for (i = 0; i < max; i++) gem_execbuf(fd, &execbuf); execbuf.rsvd1 = ctx0; - for (i = 0; i < 5; i++) + for (i = 0; i < max; i++) gem_execbuf(fd, &execbuf); gem_sync(fd, obj.handle); -- 2.23.0.rc1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/4] dma-fence: Refactor signaling for manual invocation
Quoting Koenig, Christian (2019-08-12 15:50:59) > Am 12.08.19 um 16:43 schrieb Chris Wilson: > > Quoting Koenig, Christian (2019-08-12 15:34:32) > >> Am 10.08.19 um 17:34 schrieb Chris Wilson: > >>> Move the duplicated code within dma-fence.c into the header for wider > >>> reuse. In the process apply a small micro-optimisation to only prune the > >>> fence->cb_list once rather than use list_del on every entry. > >>> > >>> Signed-off-by: Chris Wilson > >>> Cc: Tvrtko Ursulin > >>> --- > >>>drivers/dma-buf/Makefile| 10 +- > >>>drivers/dma-buf/dma-fence-trace.c | 28 +++ > >>>drivers/dma-buf/dma-fence.c | 33 +-- > >>>drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 32 +-- > >>>include/linux/dma-fence-impl.h | 83 +++ > >>>include/linux/dma-fence-types.h | 258 > >>>include/linux/dma-fence.h | 228 + > >> Mhm, I don't really see the value in creating more header files. > >> > >> Especially I'm pretty sure that the types should stay in dma-fence.h > > iirc, when I included the trace.h from dma-fence.h or dma-fence-impl.h > > without separating the types, amdgpu failed to compile (which is more > > than likely to be simply due to be first drm in the list to compile). > > Ah, but why do you want to include trace.h in a header in the first place? > > That's usually not something I would recommend either. The problem is that we do emit a tracepoint as part of the sequence I want to put into the reusable chunk of code. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 5/5] drm/i915: Cancel non-persistent contexts on close
Quoting Bloomfield, Jon (2019-08-12 15:39:33) > > -Original Message- > > From: Chris Wilson > > Sent: Friday, August 9, 2019 4:35 PM > > To: intel-gfx@lists.freedesktop.org > > Cc: Joonas Lahtinen ; Winiarski, Michal > > ; Bloomfield, Jon > > Subject: Re: [PATCH 5/5] drm/i915: Cancel non-persistent contexts on close > > > > Quoting Chris Wilson (2019-08-06 14:47:25) > > > Normally, we rely on our hangcheck to prevent persistent batches from > > > hogging the GPU. However, if the user disables hangcheck, this mechanism > > > breaks down. Despite our insistence that this is unsafe, the users are > > > equally insistent that they want to use endless batches and will disable > > > the hangcheck mechanism. We are looking are perhaps replacing hangcheck > > > with a softer mechanism, that sends a pulse down the engine to check if > > > it is well. We can use the same preemptive pulse to flush an active > > > persistent context off the GPU upon context close, preventing resources > > > being lost and unkillable requests remaining on the GPU, after process > > > termination. To avoid changing the ABI and accidentally breaking > > > existing userspace, we make the persistence of a context explicit and > > > enable it by default. Userspace can opt out of persistent mode (forcing > > > requests to be cancelled when the context is closed by process > > > termination or explicitly) by a context parameter, or to facilitate > > > existing use-cases by disabling hangcheck (i915.enable_hangcheck=0). > > > (Note, one of the outcomes for supporting endless mode will be the > > > removal of hangchecking, at which point opting into persistent mode will > > > be mandatory, or maybe the default.) > > > > For the record, I've finally run into examples of desktop clients > > exiting before their rendering is shown. No longer hypothetical. > > -Chris > > Can you share any details - Might be useful for testing. In cinnamon, the atl-tab switcher seems to be one. Another one seems to be around firefox, but I haven't established the trigger. I should actually log who owned the context! -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/4] dma-fence: Refactor signaling for manual invocation
Am 12.08.19 um 16:43 schrieb Chris Wilson: > Quoting Koenig, Christian (2019-08-12 15:34:32) >> Am 10.08.19 um 17:34 schrieb Chris Wilson: >>> Move the duplicated code within dma-fence.c into the header for wider >>> reuse. In the process apply a small micro-optimisation to only prune the >>> fence->cb_list once rather than use list_del on every entry. >>> >>> Signed-off-by: Chris Wilson >>> Cc: Tvrtko Ursulin >>> --- >>>drivers/dma-buf/Makefile| 10 +- >>>drivers/dma-buf/dma-fence-trace.c | 28 +++ >>>drivers/dma-buf/dma-fence.c | 33 +-- >>>drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 32 +-- >>>include/linux/dma-fence-impl.h | 83 +++ >>>include/linux/dma-fence-types.h | 258 >>>include/linux/dma-fence.h | 228 + >> Mhm, I don't really see the value in creating more header files. >> >> Especially I'm pretty sure that the types should stay in dma-fence.h > iirc, when I included the trace.h from dma-fence.h or dma-fence-impl.h > without separating the types, amdgpu failed to compile (which is more > than likely to be simply due to be first drm in the list to compile). Ah, but why do you want to include trace.h in a header in the first place? That's usually not something I would recommend either. Christian. > > Doing more work wasn't through choice. > -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/4] dma-fence: Refactor signaling for manual invocation
Quoting Koenig, Christian (2019-08-12 15:34:32) > Am 10.08.19 um 17:34 schrieb Chris Wilson: > > Move the duplicated code within dma-fence.c into the header for wider > > reuse. In the process apply a small micro-optimisation to only prune the > > fence->cb_list once rather than use list_del on every entry. > > > > Signed-off-by: Chris Wilson > > Cc: Tvrtko Ursulin > > --- > > drivers/dma-buf/Makefile| 10 +- > > drivers/dma-buf/dma-fence-trace.c | 28 +++ > > drivers/dma-buf/dma-fence.c | 33 +-- > > drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 32 +-- > > include/linux/dma-fence-impl.h | 83 +++ > > include/linux/dma-fence-types.h | 258 > > include/linux/dma-fence.h | 228 + > > Mhm, I don't really see the value in creating more header files. > > Especially I'm pretty sure that the types should stay in dma-fence.h iirc, when I included the trace.h from dma-fence.h or dma-fence-impl.h without separating the types, amdgpu failed to compile (which is more than likely to be simply due to be first drm in the list to compile). Doing more work wasn't through choice. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 5/5] drm/i915: Cancel non-persistent contexts on close
> -Original Message- > From: Chris Wilson > Sent: Friday, August 9, 2019 4:35 PM > To: intel-gfx@lists.freedesktop.org > Cc: Joonas Lahtinen ; Winiarski, Michal > ; Bloomfield, Jon > Subject: Re: [PATCH 5/5] drm/i915: Cancel non-persistent contexts on close > > Quoting Chris Wilson (2019-08-06 14:47:25) > > Normally, we rely on our hangcheck to prevent persistent batches from > > hogging the GPU. However, if the user disables hangcheck, this mechanism > > breaks down. Despite our insistence that this is unsafe, the users are > > equally insistent that they want to use endless batches and will disable > > the hangcheck mechanism. We are looking are perhaps replacing hangcheck > > with a softer mechanism, that sends a pulse down the engine to check if > > it is well. We can use the same preemptive pulse to flush an active > > persistent context off the GPU upon context close, preventing resources > > being lost and unkillable requests remaining on the GPU, after process > > termination. To avoid changing the ABI and accidentally breaking > > existing userspace, we make the persistence of a context explicit and > > enable it by default. Userspace can opt out of persistent mode (forcing > > requests to be cancelled when the context is closed by process > > termination or explicitly) by a context parameter, or to facilitate > > existing use-cases by disabling hangcheck (i915.enable_hangcheck=0). > > (Note, one of the outcomes for supporting endless mode will be the > > removal of hangchecking, at which point opting into persistent mode will > > be mandatory, or maybe the default.) > > For the record, I've finally run into examples of desktop clients > exiting before their rendering is shown. No longer hypothetical. > -Chris Can you share any details - Might be useful for testing. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/4] dma-fence: Refactor signaling for manual invocation
Am 10.08.19 um 17:34 schrieb Chris Wilson:
> Move the duplicated code within dma-fence.c into the header for wider
> reuse. In the process apply a small micro-optimisation to only prune the
> fence->cb_list once rather than use list_del on every entry.
>
> Signed-off-by: Chris Wilson
> Cc: Tvrtko Ursulin
> ---
> drivers/dma-buf/Makefile| 10 +-
> drivers/dma-buf/dma-fence-trace.c | 28 +++
> drivers/dma-buf/dma-fence.c | 33 +--
> drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 32 +--
> include/linux/dma-fence-impl.h | 83 +++
> include/linux/dma-fence-types.h | 258
> include/linux/dma-fence.h | 228 +
Mhm, I don't really see the value in creating more header files.
Especially I'm pretty sure that the types should stay in dma-fence.h
Christian.
> 7 files changed, 386 insertions(+), 286 deletions(-)
> create mode 100644 drivers/dma-buf/dma-fence-trace.c
> create mode 100644 include/linux/dma-fence-impl.h
> create mode 100644 include/linux/dma-fence-types.h
>
> diff --git a/drivers/dma-buf/Makefile b/drivers/dma-buf/Makefile
> index e8c7310cb800..65c43778e571 100644
> --- a/drivers/dma-buf/Makefile
> +++ b/drivers/dma-buf/Makefile
> @@ -1,6 +1,12 @@
> # SPDX-License-Identifier: GPL-2.0-only
> -obj-y := dma-buf.o dma-fence.o dma-fence-array.o dma-fence-chain.o \
> - reservation.o seqno-fence.o
> +obj-y := \
> + dma-buf.o \
> + dma-fence.o \
> + dma-fence-array.o \
> + dma-fence-chain.o \
> + dma-fence-trace.o \
> + reservation.o \
> + seqno-fence.o
> obj-$(CONFIG_SYNC_FILE) += sync_file.o
> obj-$(CONFIG_SW_SYNC) += sw_sync.o sync_debug.o
> obj-$(CONFIG_UDMABUF) += udmabuf.o
> diff --git a/drivers/dma-buf/dma-fence-trace.c
> b/drivers/dma-buf/dma-fence-trace.c
> new file mode 100644
> index ..eb6f282be4c0
> --- /dev/null
> +++ b/drivers/dma-buf/dma-fence-trace.c
> @@ -0,0 +1,28 @@
> +/*
> + * Fence mechanism for dma-buf and to allow for asynchronous dma access
> + *
> + * Copyright (C) 2012 Canonical Ltd
> + * Copyright (C) 2012 Texas Instruments
> + *
> + * Authors:
> + * Rob Clark
> + * Maarten Lankhorst
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published
> by
> + * the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but
> WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + */
> +
> +#include
> +
> +#define CREATE_TRACE_POINTS
> +#include
> +
> +EXPORT_TRACEPOINT_SYMBOL(dma_fence_emit);
> +EXPORT_TRACEPOINT_SYMBOL(dma_fence_enable_signal);
> +EXPORT_TRACEPOINT_SYMBOL(dma_fence_signaled);
> diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c
> index 59ac96ec7ba8..027a6a894abd 100644
> --- a/drivers/dma-buf/dma-fence.c
> +++ b/drivers/dma-buf/dma-fence.c
> @@ -14,15 +14,9 @@
> #include
> #include
> #include
> +#include
> #include
>
> -#define CREATE_TRACE_POINTS
> -#include
> -
> -EXPORT_TRACEPOINT_SYMBOL(dma_fence_emit);
> -EXPORT_TRACEPOINT_SYMBOL(dma_fence_enable_signal);
> -EXPORT_TRACEPOINT_SYMBOL(dma_fence_signaled);
> -
> static DEFINE_SPINLOCK(dma_fence_stub_lock);
> static struct dma_fence dma_fence_stub;
>
> @@ -128,7 +122,6 @@ EXPORT_SYMBOL(dma_fence_context_alloc);
>*/
> int dma_fence_signal_locked(struct dma_fence *fence)
> {
> - struct dma_fence_cb *cur, *tmp;
> int ret = 0;
>
> lockdep_assert_held(fence->lock);
> @@ -136,7 +129,7 @@ int dma_fence_signal_locked(struct dma_fence *fence)
> if (WARN_ON(!fence))
> return -EINVAL;
>
> - if (test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
> + if (!__dma_fence_signal(fence)) {
> ret = -EINVAL;
>
> /*
> @@ -144,15 +137,10 @@ int dma_fence_signal_locked(struct dma_fence *fence)
>* still run through all callbacks
>*/
> } else {
> - fence->timestamp = ktime_get();
> - set_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &fence->flags);
> - trace_dma_fence_signaled(fence);
> + __dma_fence_signal__timestamp(fence, ktime_get());
> }
>
> - list_for_each_entry_safe(cur, tmp, &fence->cb_list, node) {
> - list_del_init(&cur->node);
> - cur->func(fence, cur);
> - }
> + __dma_fence_signal__notify(fence);
> return ret;
> }
> EXPORT_SYMBOL(dma_fence_signal_locked);
> @@ -177,21 +165,14 @@ int dma_fence_signal(struct dma_fence *fence)
> if (!fence)
> return -EINVAL;
>
> - if (test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence
Re: [Intel-gfx] [PATCH] drm/i915: Extract general GT interrupt handlers
Quoting Chris Wilson (2019-08-11 22:06:33) > From: Andi Shyti > > i915_irq.c is large. It serves as the central dispatch and handler for > all of our device interrupts. Lets break it up by pulling out the GT > interrupt handlers. > > Based on a patch by Chris Wilson. > > Signed-off-by: Andi Shyti Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Extract GT powermanagement interrupt handling
Quoting Chris Wilson (2019-08-11 15:28:00) > From: Andi Shyti > > i915_irq.c is large. It serves as the central dispatch and handler for > all of our device interrupts. Pull out the GT pm interrupt handling > (leaving the central dispatch) so that we can encapsulate the logic a > little better. > > Based on a patch by Chris Wilson. > > Signed-off-by: Andi Shyti Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/18] drm/i915/guc: Use a local cancel_port_requests
== Series Details ==
Series: series starting with [01/18] drm/i915/guc: Use a local
cancel_port_requests
URL : https://patchwork.freedesktop.org/series/65089/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6686 -> Patchwork_13986
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/
Known issues
Here are the changes found in Patchwork_13986 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_reloc@basic-write-read:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6686/fi-icl-u3/igt@gem_exec_re...@basic-write-read.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/fi-icl-u3/igt@gem_exec_re...@basic-write-read.html
* igt@i915_module_load@reload:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6686/fi-blb-e6850/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/fi-blb-e6850/igt@i915_module_l...@reload.html
* igt@i915_selftest@live_gtt:
- fi-glk-dsi: [PASS][5] -> [DMESG-WARN][6] ([fdo#111377])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6686/fi-glk-dsi/igt@i915_selftest@live_gtt.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/fi-glk-dsi/igt@i915_selftest@live_gtt.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [PASS][7] -> [FAIL][8] ([fdo#110627])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6686/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-7500u: [PASS][9] -> [SKIP][10] ([fdo#109271]) +23 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6686/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html
Possible fixes
* igt@gem_exec_reloc@basic-gtt-read:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6686/fi-icl-u3/igt@gem_exec_re...@basic-gtt-read.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/fi-icl-u3/igt@gem_exec_re...@basic-gtt-read.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][13] ([fdo#08]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6686/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@kms_busy@basic-flip-c:
- fi-kbl-7500u: [SKIP][15] ([fdo#109271] / [fdo#109278]) ->
[PASS][16] +2 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6686/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13986/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#110627]: https://bugs.freedesktop.org/show_bug.cgi?id=110627
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
[fdo#111377]: https://bugs.freedesktop.org/show_bug.cgi?id=111377
Participating hosts (55 -> 46)
--
Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-j1900
fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6686 -> Patchwork_13986
CI-20190529: 20190529
CI_DRM_6686: 3f5325e706a026d1e35e82642a6b93d374235b1b @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5127: f43f5fa12ac1b93febfe3eeb9e9985f5f3e2eff0 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13986: cf70cd608fef60d64d5a0499174e813f2695e88d @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cf70cd608fef drm/i915: Push the use-semaphore marker onto the intel_context
755f401dfa30 drm/i915: Drop GEM context as a direct link from i915_request
06be1ed317e9 drm/i915/pmu: Use GT parked for estimating RC6 while asleep
c30b4b8baf8c drm/i915: Move context management under GEM
65858a67e53d drm/i915: Remove l
Re: [Intel-gfx] [PATCH i-g-t] lib/i915: Trim ring measurement by one
Chris Wilson writes: > Quoting Mika Kuoppala (2019-08-12 12:52:56) >> Chris Wilson writes: >> >> > Be a little more conservative in our ring measurement and exclude one >> > batch to leave room in case our user needs to wrap (where a request will >> > be expanded to cover the unused space at the end of the ring). >> > >> >> did read the wrapping part and that seems to be the case that >> we enlarge the wrapping request. >> >> However do we lose some coverage on the actual wrap tests? > > The tests where we call measure_ring_size, are those that we do not want > to block due to running out of space (and wrapping) :) Ok. The bugs on the wrap itself should bubble to surface indirectly. Agreed that estimating the inflight wrong is bad. Reviewed-by: Mika Kuoppala ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Extract GT powermanagement interrupt handling (rev3)
== Series Details == Series: series starting with [1/2] drm/i915: Extract GT powermanagement interrupt handling (rev3) URL : https://patchwork.freedesktop.org/series/65049/ State : success == Summary == CI Bug Log - changes from CI_DRM_6683_full -> Patchwork_13981_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13981_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_switch@legacy-vebox-queue: - shard-apl: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6683/shard-apl4/igt@gem_ctx_swi...@legacy-vebox-queue.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13981/shard-apl1/igt@gem_ctx_swi...@legacy-vebox-queue.html - shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6683/shard-iclb7/igt@gem_ctx_swi...@legacy-vebox-queue.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13981/shard-iclb7/igt@gem_ctx_swi...@legacy-vebox-queue.html * igt@gem_exec_schedule@fifo-bsd1: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +14 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6683/shard-iclb4/igt@gem_exec_sched...@fifo-bsd1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13981/shard-iclb3/igt@gem_exec_sched...@fifo-bsd1.html * igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6683/shard-iclb3/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13981/shard-iclb4/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +5 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6683/shard-apl2/igt@i915_susp...@sysfs-reader.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13981/shard-apl8/igt@i915_susp...@sysfs-reader.html * igt@kms_color@pipe-a-degamma: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#104782] / [fdo#108145]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6683/shard-skl5/igt@kms_co...@pipe-a-degamma.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13981/shard-skl3/igt@kms_co...@pipe-a-degamma.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic: - shard-glk: [PASS][13] -> [FAIL][14] ([fdo#104873]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6683/shard-glk4/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13981/shard-glk7/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-atomic.html * igt@kms_flip@2x-modeset-vs-vblank-race-interruptible: - shard-glk: [PASS][15] -> [FAIL][16] ([fdo#103060]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6683/shard-glk1/igt@kms_f...@2x-modeset-vs-vblank-race-interruptible.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13981/shard-glk6/igt@kms_f...@2x-modeset-vs-vblank-race-interruptible.html * igt@kms_flip@absolute-wf_vblank: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([fdo#103558] / [fdo#105602]) +26 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6683/shard-kbl1/igt@kms_flip@absolute-wf_vblank.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13981/shard-kbl6/igt@kms_flip@absolute-wf_vblank.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +5 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6683/shard-iclb5/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13981/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-blt.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: [PASS][21] -> [INCOMPLETE][22] ([fdo#103665]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6683/shard-kbl2/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13981/shard-kbl4/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6683/shard-skl2/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13981/
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/18] drm/i915/guc: Use a local cancel_port_requests
== Series Details == Series: series starting with [01/18] drm/i915/guc: Use a local cancel_port_requests URL : https://patchwork.freedesktop.org/series/65089/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/guc: Use a local cancel_port_requests Okay! Commit: drm/i915: Push the wakeref->count deferral to the backend Okay! Commit: drm/i915/gt: Save/restore interrupts around breadcrumb disable Okay! Commit: drm/i915/execlists: Lift process_csb() out of the irq-off spinlock +drivers/gpu/drm/i915/gt/intel_lrc.c:983:24: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gt/intel_lrc.c:983:24: warning: expression using sizeof(void) -./drivers/gpu/drm/i915/i915_utils.h:262:16: warning: expression using sizeof(void) -./drivers/gpu/drm/i915/i915_utils.h:262:16: warning: expression using sizeof(void) -./drivers/gpu/drm/i915/i915_utils.h:262:16: warning: expression using sizeof(void) -./drivers/gpu/drm/i915/i915_utils.h:262:16: warning: expression using sizeof(void) -./drivers/gpu/drm/i915/i915_utils.h:262:16: warning: expression using sizeof(void) -./drivers/gpu/drm/i915/i915_utils.h:262:16: warning: expression using sizeof(void) -./drivers/gpu/drm/i915/i915_utils.h:262:16: warning: expression using sizeof(void) -./drivers/gpu/drm/i915/i915_utils.h:262:16: warning: expression using sizeof(void) +./drivers/gpu/drm/i915/i915_utils.h:260:16: warning: expression using sizeof(void) +./drivers/gpu/drm/i915/i915_utils.h:260:16: warning: expression using sizeof(void) +./drivers/gpu/drm/i915/i915_utils.h:260:16: warning: expression using sizeof(void) +./drivers/gpu/drm/i915/i915_utils.h:260:16: warning: expression using sizeof(void) +./drivers/gpu/drm/i915/i915_utils.h:260:16: warning: expression using sizeof(void) +./drivers/gpu/drm/i915/i915_utils.h:260:16: warning: expression using sizeof(void) +./drivers/gpu/drm/i915/i915_utils.h:260:16: warning: expression using sizeof(void) +./drivers/gpu/drm/i915/i915_utils.h:260:16: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/../i915_utils.h:262:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_utils.h:260:16: warning: expression using sizeof(void) Commit: drm/i915/gt: Track timeline activeness in enter/exit Okay! Commit: drm/i915/gt: Convert timeline tracking to spinlock Okay! Commit: drm/i915/gt: Guard timeline pinning with its own mutex Okay! Commit: drm/i915: Protect request retirement with timeline->mutex Okay! Commit: drm/i915/gt: Mark context->active_count as protected by timeline->mutex Okay! Commit: drm/i915: Forgo last_fence active request tracking Okay! Commit: drm/i915/overlay: Switch to using i915_active tracking Okay! Commit: drm/i915: Extract intel_frontbuffer active tracking Okay! Commit: drm/i915: Markup expected timeline locks for i915_active Okay! Commit: drm/i915: Remove logical HW ID Okay! Commit: drm/i915: Move context management under GEM +drivers/gpu/drm/i915/i915_sysfs.c:175:17: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_sysfs.c:175:17: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_sysfs.c:176:17: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_sysfs.c:176:17: warning: expression using sizeof(void) Commit: drm/i915/pmu: Use GT parked for estimating RC6 while asleep Okay! Commit: drm/i915: Drop GEM context as a direct link from i915_request Okay! Commit: drm/i915: Push the use-semaphore marker onto the intel_context Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/18] drm/i915/guc: Use a local cancel_port_requests
== Series Details == Series: series starting with [01/18] drm/i915/guc: Use a local cancel_port_requests URL : https://patchwork.freedesktop.org/series/65089/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3d6da5baf737 drm/i915/guc: Use a local cancel_port_requests 1f0621c12a25 drm/i915: Push the wakeref->count deferral to the backend 51e08f66cc0f drm/i915/gt: Save/restore interrupts around breadcrumb disable 88b0e6e02044 drm/i915/execlists: Lift process_csb() out of the irq-off spinlock c21f3d612d80 drm/i915/gt: Track timeline activeness in enter/exit 05aa0e74a899 drm/i915/gt: Convert timeline tracking to spinlock 93e83bb04cbe drm/i915/gt: Guard timeline pinning with its own mutex 0fa69645057d drm/i915: Protect request retirement with timeline->mutex 6c8d9b314a1a drm/i915/gt: Mark context->active_count as protected by timeline->mutex a55ae8c560fb drm/i915: Forgo last_fence active request tracking 11cdeb0ac83c drm/i915/overlay: Switch to using i915_active tracking 5efada370bbb drm/i915: Extract intel_frontbuffer active tracking 01e460adcc41 drm/i915: Markup expected timeline locks for i915_active -:290: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment #290: FILE: drivers/gpu/drm/i915/i915_active_types.h:28: + struct mutex *lock; total: 0 errors, 0 warnings, 1 checks, 242 lines checked 65858a67e53d drm/i915: Remove logical HW ID c30b4b8baf8c drm/i915: Move context management under GEM -:411: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment #411: FILE: drivers/gpu/drm/i915/i915_drv.h:1768: + struct mutex mutex; total: 0 errors, 0 warnings, 1 checks, 547 lines checked 06be1ed317e9 drm/i915/pmu: Use GT parked for estimating RC6 while asleep 755f401dfa30 drm/i915: Drop GEM context as a direct link from i915_request cf70cd608fef drm/i915: Push the use-semaphore marker onto the intel_context ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for Support mipi dsi video mode on TGL (rev3)
== Series Details == Series: Support mipi dsi video mode on TGL (rev3) URL : https://patchwork.freedesktop.org/series/63058/ State : failure == Summary == Applying: drm/i915/tgl/dsi: Program TRANS_VBLANK register Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/icl_dsi.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/display/icl_dsi.c No changes -- Patch already applied. Applying: drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/icl_dsi.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/display/icl_dsi.c No changes -- Patch already applied. Applying: drm/i915/tgl/dsi: Do not override TA_SURE Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/icl_dsi.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/display/icl_dsi.c No changes -- Patch already applied. Applying: drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/icl_dsi.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/display/icl_dsi.c No changes -- Patch already applied. Applying: drm/i915/tgl: Add mipi dsi support for TGL Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_display.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/display/intel_display.c No changes -- Patch already applied. Applying: drm/i915/tgl/dsi: Enable blanking packets during BLLP for video mode Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/icl_dsi.c M drivers/gpu/drm/i915/i915_reg.h Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_reg.h No changes -- Patch already applied. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/18] drm/i915/gt: Save/restore interrupts around breadcrumb disable
Stop assuming we only get called with irqs-on for disarming the
breadcrumbs, and do a full save/restore spin_lock_irq.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
index e1bbc9b428cd..90db41d173df 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
@@ -67,14 +67,15 @@ static void __intel_breadcrumbs_disarm_irq(struct
intel_breadcrumbs *b)
void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine)
{
struct intel_breadcrumbs *b = &engine->breadcrumbs;
+ unsigned long flags;
if (!b->irq_armed)
return;
- spin_lock_irq(&b->irq_lock);
+ spin_lock_irqsave(&b->irq_lock, flags);
if (b->irq_armed)
__intel_breadcrumbs_disarm_irq(b);
- spin_unlock_irq(&b->irq_lock);
+ spin_unlock_irqrestore(&b->irq_lock, flags);
}
static inline bool __request_completed(const struct i915_request *rq)
--
2.23.0.rc1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 18/18] drm/i915: Push the use-semaphore marker onto the intel_context
Instead of rummaging through the intel_context to peek at the GEM
context in the middle of request submission to decide whether to use
semaphores, store that information on the intel_context itself.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 52 +--
drivers/gpu/drm/i915/gt/intel_context.c | 3 ++
drivers/gpu/drm/i915/gt/intel_context.h | 15 ++
drivers/gpu/drm/i915/gt/intel_context_types.h | 5 +-
drivers/gpu/drm/i915/i915_request.c | 8 ++-
5 files changed, 59 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 1d7e9c32c2bb..188935b8063f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1603,6 +1603,40 @@ get_engines(struct i915_gem_context *ctx,
return err;
}
+static void __apply_priority(struct intel_context *ce, void *arg)
+{
+ struct i915_gem_context *ctx = arg;
+
+ if (intel_context_use_semaphores(ce) &&
+ ctx->sched.priority < I915_PRIORITY_NORMAL)
+ intel_context_clear_use_semaphores(ce);
+}
+
+static int set_priority(struct i915_gem_context *ctx,
+ const struct drm_i915_gem_context_param *args)
+{
+ s64 priority = args->value;
+
+ if (args->size)
+ return -EINVAL;
+
+ if (!(ctx->i915->caps.scheduler & I915_SCHEDULER_CAP_PRIORITY))
+ return -ENODEV;
+
+ if (priority > I915_CONTEXT_MAX_USER_PRIORITY ||
+ priority < I915_CONTEXT_MIN_USER_PRIORITY)
+ return -EINVAL;
+
+ if (priority > I915_CONTEXT_DEFAULT_PRIORITY &&
+ !capable(CAP_SYS_NICE))
+ return -EPERM;
+
+ ctx->sched.priority = I915_USER_PRIORITY(priority);
+ context_apply_all(ctx, __apply_priority, NULL);
+
+ return 0;
+}
+
static int ctx_setparam(struct drm_i915_file_private *fpriv,
struct i915_gem_context *ctx,
struct drm_i915_gem_context_param *args)
@@ -1649,23 +1683,7 @@ static int ctx_setparam(struct drm_i915_file_private
*fpriv,
break;
case I915_CONTEXT_PARAM_PRIORITY:
- {
- s64 priority = args->value;
-
- if (args->size)
- ret = -EINVAL;
- else if (!(ctx->i915->caps.scheduler &
I915_SCHEDULER_CAP_PRIORITY))
- ret = -ENODEV;
- else if (priority > I915_CONTEXT_MAX_USER_PRIORITY ||
-priority < I915_CONTEXT_MIN_USER_PRIORITY)
- ret = -EINVAL;
- else if (priority > I915_CONTEXT_DEFAULT_PRIORITY &&
-!capable(CAP_SYS_NICE))
- ret = -EPERM;
- else
- ctx->sched.priority =
- I915_USER_PRIORITY(priority);
- }
+ ret = set_priority(ctx, args);
break;
case I915_CONTEXT_PARAM_SSEU:
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 40e61184f24f..bde5d0917903 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -227,6 +227,9 @@ intel_context_init(struct intel_context *ce,
ce->vm = i915_vm_get(ctx->vm ?: &engine->gt->ggtt->vm);
if (ctx->timeline)
ce->timeline = intel_timeline_get(ctx->timeline);
+ if (ctx->sched.priority >= I915_PRIORITY_NORMAL &&
+ intel_engine_has_semaphores(engine))
+ __set_bit(CONTEXT_USE_SEMAPHORES, &ce->flags);
ce->engine = engine;
ce->ops = engine->cops;
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
b/drivers/gpu/drm/i915/gt/intel_context.h
index fe03b1eeab63..7fdca6fe7a70 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -154,6 +154,21 @@ static inline struct intel_ring
*__intel_context_ring_size(u64 sz)
return u64_to_ptr(struct intel_ring, sz);
}
+static inline bool intel_context_use_semaphores(const struct intel_context *ce)
+{
+ return test_bit(CONTEXT_USE_SEMAPHORES, &ce->flags);
+}
+
+static inline void intel_context_set_use_semaphores(struct intel_context *ce)
+{
+ set_bit(CONTEXT_USE_SEMAPHORES, &ce->flags);
+}
+
+static inline void intel_context_clear_use_semaphores(struct intel_context *ce)
+{
+ clear_bit(CONTEXT_USE_SEMAPHORES, &ce->flags);
+}
+
static inline bool intel_context_is_banned(const struct intel_context *ce)
{
return test_bit(CONTEXT_BANNED, &ce->flags);
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 9c8c6dcd0f07..278680833146
[Intel-gfx] [PATCH 13/18] drm/i915: Markup expected timeline locks for i915_active
As every i915_active_request should be serialised by a dedicated lock,
i915_active consists of a tree of locks; one for each node. Markup up
the i915_active_request with what lock is supposed to be guarding it so
that we can verify that the serialised updated are indeed serialised.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
.../gpu/drm/i915/gem/i915_gem_client_blt.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/gt/intel_context.c | 11 +++
drivers/gpu/drm/i915/gt/intel_engine_pool.h | 2 +-
drivers/gpu/drm/i915/gt/intel_timeline.c | 7 +++
drivers/gpu/drm/i915/gt/selftest_timeline.c | 4
.../gpu/drm/i915/gt/selftests/mock_timeline.c | 2 +-
drivers/gpu/drm/i915/i915_active.c| 19 +++
drivers/gpu/drm/i915/i915_active.h| 12 ++--
drivers/gpu/drm/i915/i915_active_types.h | 3 +++
drivers/gpu/drm/i915/i915_vma.c | 4 ++--
drivers/gpu/drm/i915/selftests/i915_active.c | 3 +--
13 files changed, 46 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c
b/drivers/gpu/drm/i915/display/intel_overlay.c
index e1248eace0e1..eca41c4a5aa6 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -230,7 +230,7 @@ alloc_request(struct intel_overlay *overlay, void
(*fn)(struct intel_overlay *))
if (IS_ERR(rq))
return rq;
- err = i915_active_ref(&overlay->last_flip, rq->fence.context, rq);
+ err = i915_active_ref(&overlay->last_flip, rq->timeline, rq);
if (err) {
i915_request_add(rq);
return ERR_PTR(err);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
index ac14677dd537..2536d1f54629 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
@@ -211,7 +211,7 @@ static void clear_pages_worker(struct work_struct *work)
* keep track of the GPU activity within this vma/request, and
* propagate the signal from the request to w->dma.
*/
- err = i915_active_ref(&vma->active, rq->fence.context, rq);
+ err = i915_active_ref(&vma->active, rq->timeline, rq);
if (err)
goto out_request;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index a6b0cb714292..cd1fd2e5423a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -908,7 +908,7 @@ static int context_barrier_task(struct i915_gem_context
*ctx,
if (emit)
err = emit(rq, data);
if (err == 0)
- err = i915_active_ref(&cb->base, rq->fence.context, rq);
+ err = i915_active_ref(&cb->base, rq->timeline, rq);
i915_request_add(rq);
if (err)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 9114953bf920..f55691d151ae 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -306,10 +306,10 @@ int intel_context_prepare_remote_request(struct
intel_context *ce,
/* Queue this switch after current activity by this context. */
err = i915_active_request_set(&tl->last_request, rq);
+ mutex_unlock(&tl->mutex);
if (err)
- goto unlock;
+ return err;
}
- lockdep_assert_held(&tl->mutex);
/*
* Guarantee context image and the timeline remains pinned until the
@@ -319,12 +319,7 @@ int intel_context_prepare_remote_request(struct
intel_context *ce,
* words transfer the pinned ce object to tracked active request.
*/
GEM_BUG_ON(i915_active_is_idle(&ce->active));
- err = i915_active_ref(&ce->active, rq->fence.context, rq);
-
-unlock:
- if (rq->timeline != tl)
- mutex_unlock(&tl->mutex);
- return err;
+ return i915_active_ref(&ce->active, rq->timeline, rq);
}
struct i915_request *intel_context_create_request(struct intel_context *ce)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pool.h
b/drivers/gpu/drm/i915/gt/intel_engine_pool.h
index f7a0a660c1c9..8d069efd9457 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pool.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pool.h
@@ -18,7 +18,7 @@ static inline int
intel_engine_pool_mark_active(struct intel_engine_pool_node *node,
struct i915_request *rq)
{
- return i915_active_ref(&node->active, rq->fence.context, rq);
+ return i915_active_ref(&node->active, rq->timeline, rq);
}
static inline void
diff --git a/drivers/gpu/drm/i915/gt/intel_timelin
[Intel-gfx] [PATCH 12/18] drm/i915: Extract intel_frontbuffer active tracking
Move the active tracking for the frontbuffer operations out of the
i915_gem_object and into its own first class (refcounted) object. In the
process of detangling, we switch from low level request tracking to the
easier i915_active -- with the plan that this avoids any potential
atomic callbacks as the frontbuffer tracking wishes to sleep as it
flushes.
Signed-off-by: Chris Wilson
---
Documentation/gpu/i915.rst| 3 -
drivers/gpu/drm/i915/display/intel_display.c | 70 +++--
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_fbdev.c| 40 ++-
.../gpu/drm/i915/display/intel_frontbuffer.c | 255 +-
.../gpu/drm/i915/display/intel_frontbuffer.h | 70 +++--
drivers/gpu/drm/i915/display/intel_overlay.c | 8 +-
drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_domain.c| 14 +-
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 4 -
drivers/gpu/drm/i915/gem/i915_gem_object.c| 27 +-
drivers/gpu/drm/i915/gem/i915_gem_object.h| 2 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 8 +-
drivers/gpu/drm/i915/i915_debugfs.c | 5 -
drivers/gpu/drm/i915/i915_drv.h | 4 -
drivers/gpu/drm/i915/i915_gem.c | 47 +---
drivers/gpu/drm/i915/i915_vma.c | 6 +-
17 files changed, 306 insertions(+), 260 deletions(-)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 0e322688be5c..3415255ad3dc 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -91,9 +91,6 @@ Frontbuffer Tracking
.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c
:internal:
-.. kernel-doc:: drivers/gpu/drm/i915/i915_gem.c
- :functions: i915_gem_track_fb
-
Display FIFO Underrun Reporting
---
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 647f49ca86ff..84e8827c9107 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3049,12 +3049,13 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_i915_gem_object *obj = NULL;
struct drm_mode_fb_cmd2 mode_cmd = { 0 };
struct drm_framebuffer *fb = &plane_config->fb->base;
u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
u32 size_aligned = round_up(plane_config->base + plane_config->size,
PAGE_SIZE);
+ struct drm_i915_gem_object *obj;
+ bool ret = false;
size_aligned -= base_aligned;
@@ -3096,7 +3097,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
break;
default:
MISSING_CASE(plane_config->tiling);
- return false;
+ goto out;
}
mode_cmd.pixel_format = fb->format->format;
@@ -3108,16 +3109,15 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
DRM_DEBUG_KMS("intel fb init failed\n");
- goto out_unref_obj;
+ goto out;
}
DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
- return true;
-
-out_unref_obj:
+ ret = true;
+out:
i915_gem_object_put(obj);
- return false;
+ return ret;
}
static void
@@ -3174,6 +3174,12 @@ static void intel_plane_disable_noatomic(struct
intel_crtc *crtc,
intel_disable_plane(plane, crtc_state);
}
+static struct intel_frontbuffer *
+to_intel_frontbuffer(struct drm_framebuffer *fb)
+{
+ return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
+}
+
static void
intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
struct intel_initial_plane_config *plane_config)
@@ -3181,7 +3187,6 @@ intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc,
struct drm_device *dev = intel_crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_crtc *c;
- struct drm_i915_gem_object *obj;
struct drm_plane *primary = intel_crtc->base.primary;
struct drm_plane_state *plane_state = primary->state;
struct intel_plane *intel_plane = to_intel_plane(primary);
@@ -3257,8 +3262,7 @@ intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc,
return;
}
- obj = intel_fb_obj(fb);
- intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
+ intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
plane_state->src_x = 0;
plane_state->src_y = 0;
@@ -3273,14 +3277,14 @@ intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc,
intel_state->base.src = drm_plane_state_src(plane_state);
intel_state->base.dst
Re: [Intel-gfx] [PATCH v7 4/4] drm/i915: Add transcoder restriction to PSR2
On 7/31/2019 4:17 AM, José Roberto de Souza wrote:
According to PSR2_CTL definition on BSpec there is only one instance
of PSR2_CTL also ICL display overview state that PSR2 is only
supported in EDP transcoder, so now that is possible to have PSR in
any transcoder lets add this hardware restriction.
BSpec: 7713
BSpec: 20584
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_psr.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index f06b4a0b9e26..526990767c52 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -545,6 +545,11 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
if (!dev_priv->psr.sink_psr2_support)
return false;
+ if (crtc_state->cpu_transcoder != TRANSCODER_EDP) {
+ DRM_DEBUG_KMS("PSR2 is only supported in EDP transcoder\n");
+ return false;
+ }
+
TGL supports PSR2 on TRANSCODER_A, am i missing anything here?
/*
* DSC and PSR2 cannot be enabled simultaneously. If a requested
* resolution requires DSC to be enabled, priority is given to DSC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/18] drm/i915/overlay: Switch to using i915_active tracking
Remove the raw i915_active_request tracking in favour of the higher
level i915_active tracking for the sole purpose of making the lockless
transition easier in later patches.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_overlay.c | 129 +--
drivers/gpu/drm/i915/i915_active.h | 19 ---
2 files changed, 64 insertions(+), 84 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c
b/drivers/gpu/drm/i915/display/intel_overlay.c
index 4d3b2086570e..4f78586ee05e 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -191,7 +191,8 @@ struct intel_overlay {
struct overlay_registers __iomem *regs;
u32 flip_addr;
/* flip handling */
- struct i915_active_request last_flip;
+ struct i915_active last_flip;
+ void (*flip_complete)(struct intel_overlay *ovl);
};
static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv,
@@ -217,30 +218,25 @@ static void i830_overlay_clock_gating(struct
drm_i915_private *dev_priv,
PCI_DEVFN(0, 0), I830_CLOCK_GATE, val);
}
-static void intel_overlay_submit_request(struct intel_overlay *overlay,
-struct i915_request *rq,
-i915_active_retire_fn retire)
+static struct i915_request *
+alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay
*))
{
- GEM_BUG_ON(i915_active_request_peek(&overlay->last_flip,
- &overlay->i915->drm.struct_mutex));
- i915_active_request_set_retire_fn(&overlay->last_flip, retire,
- &overlay->i915->drm.struct_mutex);
- __i915_active_request_set(&overlay->last_flip, rq);
- i915_request_add(rq);
-}
+ struct i915_request *rq;
+ int err;
-static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
-struct i915_request *rq,
-i915_active_retire_fn retire)
-{
- intel_overlay_submit_request(overlay, rq, retire);
- return i915_active_request_retire(&overlay->last_flip,
- &overlay->i915->drm.struct_mutex);
-}
+ overlay->flip_complete = fn;
-static struct i915_request *alloc_request(struct intel_overlay *overlay)
-{
- return i915_request_create(overlay->context);
+ rq = i915_request_create(overlay->context);
+ if (IS_ERR(rq))
+ return rq;
+
+ err = i915_active_ref(&overlay->last_flip, rq->fence.context, rq);
+ if (err) {
+ i915_request_add(rq);
+ return ERR_PTR(err);
+ }
+
+ return rq;
}
/* overlay needs to be disable in OCMD reg */
@@ -252,7 +248,7 @@ static int intel_overlay_on(struct intel_overlay *overlay)
WARN_ON(overlay->active);
- rq = alloc_request(overlay);
+ rq = alloc_request(overlay, NULL);
if (IS_ERR(rq))
return PTR_ERR(rq);
@@ -273,7 +269,9 @@ static int intel_overlay_on(struct intel_overlay *overlay)
*cs++ = MI_NOOP;
intel_ring_advance(rq, cs);
- return intel_overlay_do_wait_request(overlay, rq, NULL);
+ i915_request_add(rq);
+
+ return i915_active_wait(&overlay->last_flip);
}
static void intel_overlay_flip_prepare(struct intel_overlay *overlay,
@@ -317,7 +315,7 @@ static int intel_overlay_continue(struct intel_overlay
*overlay,
if (tmp & (1 << 17))
DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
- rq = alloc_request(overlay);
+ rq = alloc_request(overlay, NULL);
if (IS_ERR(rq))
return PTR_ERR(rq);
@@ -332,8 +330,7 @@ static int intel_overlay_continue(struct intel_overlay
*overlay,
intel_ring_advance(rq, cs);
intel_overlay_flip_prepare(overlay, vma);
-
- intel_overlay_submit_request(overlay, rq, NULL);
+ i915_request_add(rq);
return 0;
}
@@ -354,20 +351,13 @@ static void intel_overlay_release_old_vma(struct
intel_overlay *overlay)
}
static void
-intel_overlay_release_old_vid_tail(struct i915_active_request *active,
- struct i915_request *rq)
+intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
{
- struct intel_overlay *overlay =
- container_of(active, typeof(*overlay), last_flip);
-
intel_overlay_release_old_vma(overlay);
}
-static void intel_overlay_off_tail(struct i915_active_request *active,
- struct i915_request *rq)
+static void intel_overlay_off_tail(struct intel_overlay *overlay)
{
- struct intel_overlay *overlay =
- container_of(active, typeof(*overlay), last_flip);
struct drm_i915_private *dev_priv = overlay->i915;
intel_overlay_release
[Intel-gfx] [PATCH 17/18] drm/i915: Drop GEM context as a direct link from i915_request
Keep the intel_context as being the primary state for i915_request, with
the GEM context a backpointer from the low level state for the rarer
cases we need client information. Our goal is to remove such references
to clients from the backend, and leave the HW submission agnostic to
client interfaces and self-contained.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 ++-
drivers/gpu/drm/i915/gem/i915_gem_context.h | 20 -
.../gpu/drm/i915/gem/i915_gem_context_types.h | 6 +--
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 6 +--
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 4 +-
drivers/gpu/drm/i915/gt/intel_context.c | 2 +-
drivers/gpu/drm/i915/gt/intel_context.h | 24 +++
drivers/gpu/drm/i915/gt/intel_context_types.h | 4 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 42 +--
drivers/gpu/drm/i915/gt/intel_reset.c | 38 +
drivers/gpu/drm/i915/gt/intel_ringbuffer.c| 12 +++---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 +--
drivers/gpu/drm/i915/gvt/scheduler.c | 18
drivers/gpu/drm/i915/i915_gem.c | 6 +--
drivers/gpu/drm/i915/i915_gpu_error.c | 11 +++--
drivers/gpu/drm/i915/i915_request.c | 15 ---
drivers/gpu/drm/i915/i915_request.h | 3 +-
18 files changed, 117 insertions(+), 107 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 51b8101e9836..1d7e9c32c2bb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -69,8 +69,9 @@
#include
-#include "gt/intel_lrc_reg.h"
+#include "gt/intel_context.h"
#include "gt/intel_engine_user.h"
+#include "gt/intel_lrc_reg.h"
#include "i915_gem_context.h"
#include "i915_globals.h"
@@ -842,7 +843,7 @@ static void set_ppgtt_barrier(void *data)
static int emit_ppgtt_update(struct i915_request *rq, void *data)
{
- struct i915_address_space *vm = rq->hw_context->vm;
+ struct i915_address_space *vm = rq->context->vm;
struct intel_engine_cs *engine = rq->engine;
u32 base = engine->mmio_base;
u32 *cs;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index 441715f9ee3a..bfc0826591c5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -74,26 +74,6 @@ static inline void i915_gem_context_clear_recoverable(struct
i915_gem_context *c
clear_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags);
}
-static inline bool i915_gem_context_is_banned(const struct i915_gem_context
*ctx)
-{
- return test_bit(CONTEXT_BANNED, &ctx->flags);
-}
-
-static inline void i915_gem_context_set_banned(struct i915_gem_context *ctx)
-{
- set_bit(CONTEXT_BANNED, &ctx->flags);
-}
-
-static inline bool i915_gem_context_force_single_submission(const struct
i915_gem_context *ctx)
-{
- return test_bit(CONTEXT_FORCE_SINGLE_SUBMISSION, &ctx->flags);
-}
-
-static inline void i915_gem_context_set_force_single_submission(struct
i915_gem_context *ctx)
-{
- __set_bit(CONTEXT_FORCE_SINGLE_SUBMISSION, &ctx->flags);
-}
-
static inline bool
i915_gem_context_user_engines(const struct i915_gem_context *ctx)
{
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index 87be27877e22..53e1f17ed3fe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -142,10 +142,8 @@ struct i915_gem_context {
* @flags: small set of booleans
*/
unsigned long flags;
-#define CONTEXT_BANNED 0
-#define CONTEXT_CLOSED 1
-#define CONTEXT_FORCE_SINGLE_SUBMISSION2
-#define CONTEXT_USER_ENGINES 3
+#define CONTEXT_CLOSED 0
+#define CONTEXT_USER_ENGINES 1
struct mutex mutex;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index b8432c3437e9..60bda03c53f5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -742,9 +742,6 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
unsigned int i, batch;
int err;
- if (unlikely(i915_gem_context_is_banned(eb->gem_context)))
- return -EIO;
-
INIT_LIST_HEAD(&eb->relocs);
INIT_LIST_HEAD(&eb->unbound);
@@ -2152,6 +2149,9 @@ static int __eb_pin_engine(struct i915_execbuffer *eb,
struct intel_context *ce)
if (err)
return err;
+ if (unlikely(intel_context_is_banned(ce)))
+ return -EIO;
+
/*
* Pinning the contexts may generate requests in order to acquire
* GGTT sp
[Intel-gfx] [PATCH 14/18] drm/i915: Remove logical HW ID
With the introduction of ctx->engines[] we allow multiple logical
contexts to be used on the same engine (e.g. with virtual engines). Each
logical context requires a unique tag in order for context-switching to
occur correctly between them.
We only need to keep a unique tag for the active lifetime of the
context, and for as long as we need to identify that context. The HW
uses the tag to determine if it should use a lite-restore (why not the
LRCA?) and passes the tag back for various status identifies. The only
status we need to track is for OA, so when using perf, we assign the
specific context a unique tag.
Note that although we it call it the HW ID, the hardware calls it the SW
ID! That's all it is a cookie we give to the HW that it passes back on
event notifications so we can identify the source context.
Fixes: 976b55f0e1db ("drm/i915: Allow a context to define its set of engines")
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 144 --
drivers/gpu/drm/i915/gem/i915_gem_context.h | 15 --
.../gpu/drm/i915/gem/i915_gem_context_types.h | 18 ---
.../drm/i915/gem/selftests/i915_gem_context.c | 13 +-
.../gpu/drm/i915/gem/selftests/mock_context.c | 8 -
drivers/gpu/drm/i915/gt/intel_context_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 4 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 29 ++--
drivers/gpu/drm/i915/gvt/kvmgt.c | 17 ---
drivers/gpu/drm/i915/i915_debugfs.c | 3 -
drivers/gpu/drm/i915/i915_gpu_error.c | 7 +-
drivers/gpu/drm/i915/i915_gpu_error.h | 1 -
drivers/gpu/drm/i915/i915_perf.c | 30 ++--
drivers/gpu/drm/i915/i915_trace.h | 38 ++---
.../gpu/drm/i915/selftests/i915_gem_evict.c | 4 +-
drivers/gpu/drm/i915/selftests/i915_vma.c | 2 +-
16 files changed, 50 insertions(+), 284 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index cd1fd2e5423a..774a3ac853a8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -167,95 +167,6 @@ lookup_user_engine(struct i915_gem_context *ctx,
return i915_gem_context_get_engine(ctx, idx);
}
-static inline int new_hw_id(struct drm_i915_private *i915, gfp_t gfp)
-{
- unsigned int max;
-
- lockdep_assert_held(&i915->contexts.mutex);
-
- if (INTEL_GEN(i915) >= 11)
- max = GEN11_MAX_CONTEXT_HW_ID;
- else if (USES_GUC_SUBMISSION(i915))
- /*
-* When using GuC in proxy submission, GuC consumes the
-* highest bit in the context id to indicate proxy submission.
-*/
- max = MAX_GUC_CONTEXT_HW_ID;
- else
- max = MAX_CONTEXT_HW_ID;
-
- return ida_simple_get(&i915->contexts.hw_ida, 0, max, gfp);
-}
-
-static int steal_hw_id(struct drm_i915_private *i915)
-{
- struct i915_gem_context *ctx, *cn;
- LIST_HEAD(pinned);
- int id = -ENOSPC;
-
- lockdep_assert_held(&i915->contexts.mutex);
-
- list_for_each_entry_safe(ctx, cn,
-&i915->contexts.hw_id_list, hw_id_link) {
- if (atomic_read(&ctx->hw_id_pin_count)) {
- list_move_tail(&ctx->hw_id_link, &pinned);
- continue;
- }
-
- GEM_BUG_ON(!ctx->hw_id); /* perma-pinned kernel context */
- list_del_init(&ctx->hw_id_link);
- id = ctx->hw_id;
- break;
- }
-
- /*
-* Remember how far we got up on the last repossesion scan, so the
-* list is kept in a "least recently scanned" order.
-*/
- list_splice_tail(&pinned, &i915->contexts.hw_id_list);
- return id;
-}
-
-static int assign_hw_id(struct drm_i915_private *i915, unsigned int *out)
-{
- int ret;
-
- lockdep_assert_held(&i915->contexts.mutex);
-
- /*
-* We prefer to steal/stall ourselves and our users over that of the
-* entire system. That may be a little unfair to our users, and
-* even hurt high priority clients. The choice is whether to oomkill
-* something else, or steal a context id.
-*/
- ret = new_hw_id(i915, GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
- if (unlikely(ret < 0)) {
- ret = steal_hw_id(i915);
- if (ret < 0) /* once again for the correct errno code */
- ret = new_hw_id(i915, GFP_KERNEL);
- if (ret < 0)
- return ret;
- }
-
- *out = ret;
- return 0;
-}
-
-static void release_hw_id(struct i915_gem_context *ctx)
-{
- struct drm_i915_private *i915 = ctx->i915;
-
- if (list_empty(&ctx->hw_id_link))
- return;
-
- mutex_lock(&i915->contexts.mutex);
- if (!list_empty(&ctx->hw_id_link)) {
-
[Intel-gfx] [PATCH 15/18] drm/i915: Move context management under GEM
Keep track of the GEM contexts underneath i915->gem.contexts and assign
them their own lock for the purposes of list management.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 108 +++---
drivers/gpu/drm/i915/gem/i915_gem_context.h | 4 +-
.../gpu/drm/i915/gem/selftests/mock_context.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 16 +--
drivers/gpu/drm/i915/i915_drv.c | 2 -
drivers/gpu/drm/i915/i915_drv.h | 24 ++--
drivers/gpu/drm/i915/i915_gem.c | 8 +-
drivers/gpu/drm/i915/i915_perf.c | 13 ++-
drivers/gpu/drm/i915/i915_sysfs.c | 38 +++---
.../gpu/drm/i915/selftests/mock_gem_device.c | 4 +-
10 files changed, 93 insertions(+), 126 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 774a3ac853a8..51b8101e9836 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -218,9 +218,12 @@ static struct i915_gem_engines *default_engines(struct
i915_gem_context *ctx)
static void i915_gem_context_free(struct i915_gem_context *ctx)
{
- lockdep_assert_held(&ctx->i915->drm.struct_mutex);
GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
+ mutex_lock(&ctx->i915->gem.contexts.mutex);
+ list_del(&ctx->link);
+ mutex_unlock(&ctx->i915->gem.contexts.mutex);
+
if (ctx->vm)
i915_vm_put(ctx->vm);
@@ -233,56 +236,40 @@ static void i915_gem_context_free(struct i915_gem_context
*ctx)
kfree(ctx->name);
put_pid(ctx->pid);
- list_del(&ctx->link);
mutex_destroy(&ctx->mutex);
kfree_rcu(ctx, rcu);
}
-static void contexts_free(struct drm_i915_private *i915)
+static void contexts_free_all(struct llist_node *list)
{
- struct llist_node *freed = llist_del_all(&i915->contexts.free_list);
struct i915_gem_context *ctx, *cn;
- lockdep_assert_held(&i915->drm.struct_mutex);
-
- llist_for_each_entry_safe(ctx, cn, freed, free_link)
+ llist_for_each_entry_safe(ctx, cn, list, free_link)
i915_gem_context_free(ctx);
}
-static void contexts_free_first(struct drm_i915_private *i915)
+static void contexts_flush_free(struct i915_gem_contexts *gc)
{
- struct i915_gem_context *ctx;
- struct llist_node *freed;
-
- lockdep_assert_held(&i915->drm.struct_mutex);
-
- freed = llist_del_first(&i915->contexts.free_list);
- if (!freed)
- return;
-
- ctx = container_of(freed, typeof(*ctx), free_link);
- i915_gem_context_free(ctx);
+ contexts_free_all(llist_del_all(&gc->free_list));
}
static void contexts_free_worker(struct work_struct *work)
{
- struct drm_i915_private *i915 =
- container_of(work, typeof(*i915), contexts.free_work);
+ struct i915_gem_contexts *gc =
+ container_of(work, typeof(*gc), free_work);
- mutex_lock(&i915->drm.struct_mutex);
- contexts_free(i915);
- mutex_unlock(&i915->drm.struct_mutex);
+ contexts_flush_free(gc);
}
void i915_gem_context_release(struct kref *ref)
{
struct i915_gem_context *ctx = container_of(ref, typeof(*ctx), ref);
- struct drm_i915_private *i915 = ctx->i915;
+ struct i915_gem_contexts *gc = &ctx->i915->gem.contexts;
trace_i915_context_free(ctx);
- if (llist_add(&ctx->free_link, &i915->contexts.free_list))
- queue_work(i915->wq, &i915->contexts.free_work);
+ if (llist_add(&ctx->free_link, &gc->free_list))
+ queue_work(ctx->i915->wq, &gc->free_work);
}
static void context_close(struct i915_gem_context *ctx)
@@ -316,7 +303,6 @@ __create_context(struct drm_i915_private *i915)
return ERR_PTR(-ENOMEM);
kref_init(&ctx->ref);
- list_add_tail(&ctx->link, &i915->contexts.list);
ctx->i915 = i915;
ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_NORMAL);
mutex_init(&ctx->mutex);
@@ -342,6 +328,10 @@ __create_context(struct drm_i915_private *i915)
for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp); i++)
ctx->hang_timestamp[i] = jiffies - CONTEXT_FAST_HANG_JIFFIES;
+ mutex_lock(&i915->gem.contexts.mutex);
+ list_add_tail(&ctx->link, &i915->gem.contexts.list);
+ mutex_unlock(&i915->gem.contexts.mutex);
+
return ctx;
err_free:
@@ -416,27 +406,25 @@ static void __assign_timeline(struct i915_gem_context
*ctx,
}
static struct i915_gem_context *
-i915_gem_create_context(struct drm_i915_private *dev_priv, unsigned int flags)
+i915_gem_create_context(struct drm_i915_private *i915, unsigned int flags)
{
struct i915_gem_context *ctx;
- lockdep_assert_held(&dev_priv->drm.struct_mutex);
-
if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE &&
-
[Intel-gfx] [PATCH 02/18] drm/i915: Push the wakeref->count deferral to the backend
If the backend wishes to defer the wakeref parking, make it responsible
for unlocking the wakeref (i.e. bumping the counter). This allows it to
time the unlock much more carefully in case it happens to needs the
wakeref to be active during its deferral.
For instance, during engine parking we may choose to emit an idle
barrier (a request). To do so, we borrow the engine->kernel_context
timeline and to ensure exclusive access we keep the
engine->wakeref.count as 0. However, to submit that request to HW may
require a intel_engine_pm_get() (e.g. to keep the submission tasklet
alive) and before we allow that we have to rewake our wakeref to avoid a
recursive deadlock.
Signed-off-by: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 8 ++-
drivers/gpu/drm/i915/i915_request.c | 66 ---
drivers/gpu/drm/i915/i915_request.h | 2 +
drivers/gpu/drm/i915/i915_scheduler.c | 3 +-
drivers/gpu/drm/i915/intel_wakeref.c | 4 +-
drivers/gpu/drm/i915/intel_wakeref.h | 11
6 files changed, 56 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 6b15e3335dd6..ad37c9808c1f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -68,9 +68,13 @@ static bool switch_to_kernel_context(struct intel_engine_cs
*engine)
/* Check again on the next retirement. */
engine->wakeref_serial = engine->serial + 1;
-
i915_request_add_active_barriers(rq);
+
+ rq->sched.attr.priority = INT_MAX; /* Preemption barrier */
+
__i915_request_commit(rq);
+ __intel_wakeref_defer_park(&engine->wakeref);
+ __i915_request_queue(rq, NULL);
return false;
}
@@ -98,7 +102,7 @@ static int __engine_park(struct intel_wakeref *wf)
intel_engine_pool_park(&engine->pool);
/* Must be reset upon idling, or we may miss the busy wakeup. */
- GEM_BUG_ON(engine->execlists.queue_priority_hint != INT_MIN);
+ engine->execlists.queue_priority_hint = INT_MIN;
if (engine->park)
engine->park(engine);
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 43175bada09e..4703aab3ae21 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1186,6 +1186,12 @@ struct i915_request *__i915_request_commit(struct
i915_request *rq)
list_add(&ring->active_link, &rq->i915->gt.active_rings);
rq->emitted_jiffies = jiffies;
+ return prev;
+}
+
+void __i915_request_queue(struct i915_request *rq,
+ const struct i915_sched_attr *attr)
+{
/*
* Let the backend know a new request has arrived that may need
* to adjust the existing execution schedule due to a high priority
@@ -1199,43 +1205,15 @@ struct i915_request *__i915_request_commit(struct
i915_request *rq)
*/
local_bh_disable();
i915_sw_fence_commit(&rq->semaphore);
- if (engine->schedule) {
- struct i915_sched_attr attr = rq->gem_context->sched;
-
- /*
-* Boost actual workloads past semaphores!
-*
-* With semaphores we spin on one engine waiting for another,
-* simply to reduce the latency of starting our work when
-* the signaler completes. However, if there is any other
-* work that we could be doing on this engine instead, that
-* is better utilisation and will reduce the overall duration
-* of the current work. To avoid PI boosting a semaphore
-* far in the distance past over useful work, we keep a history
-* of any semaphore use along our dependency chain.
-*/
- if (!(rq->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN))
- attr.priority |= I915_PRIORITY_NOSEMAPHORE;
-
- /*
-* Boost priorities to new clients (new request flows).
-*
-* Allow interactive/synchronous clients to jump ahead of
-* the bulk clients. (FQ_CODEL)
-*/
- if (list_empty(&rq->sched.signalers_list))
- attr.priority |= I915_PRIORITY_WAIT;
-
- engine->schedule(rq, &attr);
- }
+ if (attr && rq->engine->schedule)
+ rq->engine->schedule(rq, attr);
i915_sw_fence_commit(&rq->submit);
local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
-
- return prev;
}
void i915_request_add(struct i915_request *rq)
{
+ struct i915_sched_attr attr = rq->gem_context->sched;
struct i915_request *prev;
lockdep_assert_held(&rq->timeline->mutex);
@@ -1245,6 +1223,32 @@ void i915_request_add(struct i915_
[Intel-gfx] [PATCH 04/18] drm/i915/execlists: Lift process_csb() out of the irq-off spinlock
If we only call process_csb() from the tasklet, though we lose the
ability to bypass ksoftirqd interrupt processing on direct submission
paths, we can push it out of the irq-off spinlock.
The penalty is that we then allow schedule_out to be called concurrently
with schedule_in requiring us to handle the usage count (baked into the
pointer itself) atomically.
As we do kick the tasklets (via local_bh_enable()) after our submission,
there is a possibility there to see if we can pull the local softirq
processing back from the ksoftirqd.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 4 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 130 +++---
drivers/gpu/drm/i915/i915_utils.h | 20 ++-
4 files changed, 94 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index a632b20ec4d8..d8ce266c049f 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -41,9 +41,7 @@ struct intel_context {
struct intel_engine_cs *engine;
struct intel_engine_cs *inflight;
#define intel_context_inflight(ce) ptr_mask_bits((ce)->inflight, 2)
-#define intel_context_inflight_count(ce) ptr_unmask_bits((ce)->inflight, 2)
-#define intel_context_inflight_inc(ce) ptr_count_inc(&(ce)->inflight)
-#define intel_context_inflight_dec(ce) ptr_count_dec(&(ce)->inflight)
+#define intel_context_inflight_count(ce) ptr_unmask_bits((ce)->inflight, 2)
struct i915_address_space *vm;
struct i915_gem_context *gem_context;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index c7b241417ee1..13a569907c3d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1459,7 +1459,7 @@ int intel_enable_engine_stats(struct intel_engine_cs
*engine)
for (port = execlists->pending; (rq = *port); port++) {
/* Exclude any contexts already counted in active */
- if (intel_context_inflight_count(rq->hw_context) == 1)
+ if (!intel_context_inflight_count(rq->hw_context))
engine->stats.active++;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 5c26c4ae139b..945f3acc2e75 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -547,27 +547,39 @@ execlists_context_status_change(struct i915_request *rq,
unsigned long status)
status, rq);
}
+static inline struct intel_engine_cs *
+__execlists_schedule_in(struct i915_request *rq)
+{
+ struct intel_engine_cs * const engine = rq->engine;
+ struct intel_context * const ce = rq->hw_context;
+
+ intel_context_get(ce);
+
+ intel_gt_pm_get(engine->gt);
+ execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
+ intel_engine_context_in(engine);
+
+ return engine;
+}
+
static inline struct i915_request *
execlists_schedule_in(struct i915_request *rq, int idx)
{
- struct intel_context *ce = rq->hw_context;
- int count;
+ struct intel_context * const ce = rq->hw_context;
+ struct intel_engine_cs *old;
+ GEM_BUG_ON(!intel_engine_pm_is_awake(rq->engine));
trace_i915_request_in(rq, idx);
- count = intel_context_inflight_count(ce);
- if (!count) {
- intel_context_get(ce);
- ce->inflight = rq->engine;
-
- intel_gt_pm_get(ce->inflight->gt);
- execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
- intel_engine_context_in(ce->inflight);
- }
+ old = READ_ONCE(ce->inflight);
+ do {
+ if (!old) {
+ WRITE_ONCE(ce->inflight, __execlists_schedule_in(rq));
+ break;
+ }
+ } while (!try_cmpxchg(&ce->inflight, &old, ptr_inc(old)));
- intel_context_inflight_inc(ce);
GEM_BUG_ON(intel_context_inflight(ce) != rq->engine);
-
return i915_request_get(rq);
}
@@ -581,35 +593,45 @@ static void kick_siblings(struct i915_request *rq, struct
intel_context *ce)
}
static inline void
-execlists_schedule_out(struct i915_request *rq)
+__execlists_schedule_out(struct i915_request *rq)
{
- struct intel_context *ce = rq->hw_context;
+ struct intel_engine_cs * const engine = rq->engine;
+ struct intel_context * const ce = rq->hw_context;
- GEM_BUG_ON(!intel_context_inflight_count(ce));
+ intel_engine_context_out(engine);
+ execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
+ intel_gt_pm_put(engine->gt);
- trace_i915_request_out(rq);
+ /*
+* I
[Intel-gfx] [PATCH 10/18] drm/i915: Forgo last_fence active request tracking
We were using the last_fence to track the last request that used this
vma that might be interpreted by a fence register and forced ourselves
to wait for this request before modifying any fence register that
overlapped our vma. Due to requirement that we need to track any XY_BLT
command, linear or tiled, this in effect meant that we have to track the
vma for its active lifespan anyway, so we can forgo the explicit
last_fence tracking and just use the whole vma->active.
Another solution would be to pipeline the register updates, and would
help resolve some long running stalls for gen3 (but only gen 2 and 3!)
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +---
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 ++
drivers/gpu/drm/i915/i915_gem_gtt.c | 1 -
drivers/gpu/drm/i915/i915_vma.c | 13 -
drivers/gpu/drm/i915/i915_vma.h | 1 -
5 files changed, 3 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index b616ba0e0da0..2c640987c24d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -212,9 +212,7 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object
*obj)
}
}
if (vma->fence)
- seq_printf(m, " , fence: %d%s",
- vma->fence->id,
- i915_active_request_isset(&vma->last_fence)
? "*" : "");
+ seq_printf(m, " , fence: %d", vma->fence->id);
seq_puts(m, ")");
spin_lock(&obj->vma.lock);
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index bcac359ec661..c9654f1a468f 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -230,16 +230,14 @@ static int fence_update(struct i915_fence_reg *fence,
i915_gem_object_get_tiling(vma->obj)))
return -EINVAL;
- ret = i915_active_request_retire(&vma->last_fence,
-&vma->obj->base.dev->struct_mutex);
+ ret = i915_active_wait(&vma->active);
if (ret)
return ret;
}
old = xchg(&fence->vma, NULL);
if (old) {
- ret = i915_active_request_retire(&old->last_fence,
-&old->obj->base.dev->struct_mutex);
+ ret = i915_active_wait(&old->active);
if (ret) {
fence->vma = old;
return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 72a227c43e35..e07c1ae971d7 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1867,7 +1867,6 @@ static struct i915_vma *pd_vma_create(struct gen6_ppgtt
*ppgtt, int size)
return ERR_PTR(-ENOMEM);
i915_active_init(i915, &vma->active, NULL, NULL);
- INIT_ACTIVE_REQUEST(&vma->last_fence);
vma->vm = &ggtt->vm;
vma->ops = &pd_vma_ops;
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 4183b0e10324..8be1bbef40e5 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -120,7 +120,6 @@ vma_create(struct drm_i915_gem_object *obj,
i915_active_init(vm->i915, &vma->active,
__i915_vma_active, __i915_vma_retire);
- INIT_ACTIVE_REQUEST(&vma->last_fence);
/* Declare ourselves safe for use inside shrinkers */
if (IS_ENABLED(CONFIG_LOCKDEP)) {
@@ -802,8 +801,6 @@ static void __i915_vma_destroy(struct i915_vma *vma)
GEM_BUG_ON(vma->node.allocated);
GEM_BUG_ON(vma->fence);
- GEM_BUG_ON(i915_active_request_isset(&vma->last_fence));
-
mutex_lock(&vma->vm->mutex);
list_del(&vma->vm_link);
mutex_unlock(&vma->vm->mutex);
@@ -928,9 +925,6 @@ int i915_vma_move_to_active(struct i915_vma *vma,
obj->read_domains |= I915_GEM_GPU_DOMAINS;
obj->mm.dirty = true;
- if (flags & EXEC_OBJECT_NEEDS_FENCE)
- __i915_active_request_set(&vma->last_fence, rq);
-
GEM_BUG_ON(!i915_vma_is_active(vma));
return 0;
}
@@ -961,14 +955,7 @@ int i915_vma_unbind(struct i915_vma *vma)
* before we are finished).
*/
__i915_vma_pin(vma);
-
ret = i915_active_wait(&vma->active);
- if (ret)
- goto unpin;
-
- ret = i915_active_request_retire(&vma->last_fence,
- &vma->vm->i915->drm.struct_mutex);
-unpin:
__i915_vma_unpin(vma);
if (ret)
[Intel-gfx] [PATCH 05/18] drm/i915/gt: Track timeline activeness in enter/exit
Lift moving the timeline to/from the active_list on enter/exit in order
to shorten the active tracking span in comparison to the existing
pin/unpin.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 1 -
drivers/gpu/drm/i915/gt/intel_context.c | 2 +
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +
drivers/gpu/drm/i915/gt/intel_timeline.c | 98 +++
drivers/gpu/drm/i915/gt/intel_timeline.h | 3 +-
.../gpu/drm/i915/gt/intel_timeline_types.h| 18
drivers/gpu/drm/i915/gt/selftest_timeline.c | 2 -
8 files changed, 64 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 17e3618241c5..92e53c25424c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -37,7 +37,6 @@ static void i915_gem_park(struct drm_i915_private *i915)
for_each_engine(engine, i915, id)
call_idle_barriers(engine); /* cleanup after wedging */
- intel_timelines_park(i915);
i915_vma_parked(i915);
i915_globals_park();
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 77833f1558a9..9114953bf920 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -280,10 +280,12 @@ int __init i915_global_context_init(void)
void intel_context_enter_engine(struct intel_context *ce)
{
intel_engine_pm_get(ce->engine);
+ intel_timeline_enter(ce->timeline);
}
void intel_context_exit_engine(struct intel_context *ce)
{
+ intel_timeline_exit(ce->timeline);
intel_engine_pm_put(ce->engine);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index ad37c9808c1f..d6a00a04ed6d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -66,6 +66,8 @@ static bool switch_to_kernel_context(struct intel_engine_cs
*engine)
/* Context switch failed, hope for the best! Maybe reset? */
return true;
+ intel_timeline_enter(rq->timeline);
+
/* Check again on the next retirement. */
engine->wakeref_serial = engine->serial + 1;
i915_request_add_active_barriers(rq);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 945f3acc2e75..b5618e6c1361 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3255,6 +3255,8 @@ static void virtual_context_enter(struct intel_context
*ce)
for (n = 0; n < ve->num_siblings; n++)
intel_engine_pm_get(ve->siblings[n]);
+
+ intel_timeline_enter(ce->timeline);
}
static void virtual_context_exit(struct intel_context *ce)
@@ -3262,6 +3264,8 @@ static void virtual_context_exit(struct intel_context *ce)
struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
unsigned int n;
+ intel_timeline_exit(ce->timeline);
+
for (n = 0; n < ve->num_siblings; n++)
intel_engine_pm_put(ve->siblings[n]);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c
b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 6daa9eb59e19..4af0b9801d91 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -278,64 +278,11 @@ void intel_timelines_init(struct drm_i915_private *i915)
timelines_init(&i915->gt);
}
-static void timeline_add_to_active(struct intel_timeline *tl)
-{
- struct intel_gt_timelines *gt = &tl->gt->timelines;
-
- mutex_lock(>->mutex);
- list_add(&tl->link, >->active_list);
- mutex_unlock(>->mutex);
-}
-
-static void timeline_remove_from_active(struct intel_timeline *tl)
-{
- struct intel_gt_timelines *gt = &tl->gt->timelines;
-
- mutex_lock(>->mutex);
- list_del(&tl->link);
- mutex_unlock(>->mutex);
-}
-
-static void timelines_park(struct intel_gt *gt)
-{
- struct intel_gt_timelines *timelines = >->timelines;
- struct intel_timeline *timeline;
-
- mutex_lock(&timelines->mutex);
- list_for_each_entry(timeline, &timelines->active_list, link) {
- /*
-* All known fences are completed so we can scrap
-* the current sync point tracking and start afresh,
-* any attempt to wait upon a previous sync point
-* will be skipped as the fence was signaled.
-*/
- i915_syncmap_free(&timeline->sync);
- }
- mutex_unlock(&timelines->mutex);
-}
-
-/**
- * intel_timelines_park - called when the driver idles
- * @i915: the drm_i915_private device
- *
- * When the driver is completely idle, we know that all of our sync points
- * have been signaled and our tracking is then entirely r
[Intel-gfx] [PATCH 07/18] drm/i915/gt: Guard timeline pinning with its own mutex
In preparation for removing struct_mutex from around context retirement,
we need to make timeline pinning safe. Since multiple engines/contexts
can share a single timeline, it needs to be protected by a mutex.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_timeline.c | 27 +--
.../gpu/drm/i915/gt/intel_timeline_types.h| 2 +-
drivers/gpu/drm/i915/gt/mock_engine.c | 6 ++---
3 files changed, 16 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c
b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 355dfc52c804..7b476cd55dac 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -211,9 +211,9 @@ int intel_timeline_init(struct intel_timeline *timeline,
void *vaddr;
kref_init(&timeline->kref);
+ atomic_set(&timeline->pin_count, 0);
timeline->gt = gt;
- timeline->pin_count = 0;
timeline->has_initial_breadcrumb = !hwsp;
timeline->hwsp_cacheline = NULL;
@@ -280,7 +280,7 @@ void intel_timelines_init(struct drm_i915_private *i915)
void intel_timeline_fini(struct intel_timeline *timeline)
{
- GEM_BUG_ON(timeline->pin_count);
+ GEM_BUG_ON(atomic_read(&timeline->pin_count));
GEM_BUG_ON(!list_empty(&timeline->requests));
if (timeline->hwsp_cacheline)
@@ -314,33 +314,31 @@ int intel_timeline_pin(struct intel_timeline *tl)
{
int err;
- if (tl->pin_count++)
+ if (atomic_add_unless(&tl->pin_count, 1, 0))
return 0;
- GEM_BUG_ON(!tl->pin_count);
- GEM_BUG_ON(tl->active_count);
err = i915_vma_pin(tl->hwsp_ggtt, 0, 0, PIN_GLOBAL | PIN_HIGH);
if (err)
- goto unpin;
+ return err;
tl->hwsp_offset =
i915_ggtt_offset(tl->hwsp_ggtt) +
offset_in_page(tl->hwsp_offset);
cacheline_acquire(tl->hwsp_cacheline);
+ if (atomic_fetch_inc(&tl->pin_count)) {
+ cacheline_release(tl->hwsp_cacheline);
+ __i915_vma_unpin(tl->hwsp_ggtt);
+ }
return 0;
-
-unpin:
- tl->pin_count = 0;
- return err;
}
void intel_timeline_enter(struct intel_timeline *tl)
{
struct intel_gt_timelines *timelines = &tl->gt->timelines;
- GEM_BUG_ON(!tl->pin_count);
+ GEM_BUG_ON(!atomic_read(&tl->pin_count));
if (tl->active_count++)
return;
GEM_BUG_ON(!tl->active_count); /* overflow? */
@@ -372,7 +370,7 @@ void intel_timeline_exit(struct intel_timeline *tl)
static u32 timeline_advance(struct intel_timeline *tl)
{
- GEM_BUG_ON(!tl->pin_count);
+ GEM_BUG_ON(!atomic_read(&tl->pin_count));
GEM_BUG_ON(tl->seqno & tl->has_initial_breadcrumb);
return tl->seqno += 1 + tl->has_initial_breadcrumb;
@@ -523,11 +521,10 @@ int intel_timeline_read_hwsp(struct i915_request *from,
void intel_timeline_unpin(struct intel_timeline *tl)
{
- GEM_BUG_ON(!tl->pin_count);
- if (--tl->pin_count)
+ GEM_BUG_ON(!atomic_read(&tl->pin_count));
+ if (!atomic_dec_and_test(&tl->pin_count))
return;
- GEM_BUG_ON(tl->active_count);
cacheline_release(tl->hwsp_cacheline);
__i915_vma_unpin(tl->hwsp_ggtt);
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
index b1a9f0c54bf0..2b1baf2fcc8e 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
@@ -41,7 +41,7 @@ struct intel_timeline {
* but the pin_count is protected by a combination of serialisation
* from the intel_context caller plus internal atomicity.
*/
- unsigned int pin_count;
+ atomic_t pin_count;
unsigned int active_count;
const u32 *hwsp_seqno;
diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c
b/drivers/gpu/drm/i915/gt/mock_engine.c
index a63dd8a42cd4..54a11dde3076 100644
--- a/drivers/gpu/drm/i915/gt/mock_engine.c
+++ b/drivers/gpu/drm/i915/gt/mock_engine.c
@@ -34,13 +34,13 @@
static void mock_timeline_pin(struct intel_timeline *tl)
{
- tl->pin_count++;
+ atomic_inc(&tl->pin_count);
}
static void mock_timeline_unpin(struct intel_timeline *tl)
{
- GEM_BUG_ON(!tl->pin_count);
- tl->pin_count--;
+ GEM_BUG_ON(!atomic_read(&tl->pin_count));
+ atomic_dec(&tl->pin_count);
}
static struct intel_ring *mock_ring(struct intel_engine_cs *engine)
--
2.23.0.rc1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/18] drm/i915/gt: Convert timeline tracking to spinlock
Convert the list manipulation of active to use spinlocks so that we can
perform the updates from underneath a quick interrupt callback.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c| 10 --
drivers/gpu/drm/i915/gt/intel_timeline.c | 12 +---
drivers/gpu/drm/i915/i915_gem.c | 14 +++---
4 files changed, 21 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 789102f4f46b..3b34b658de3f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -40,7 +40,7 @@ struct intel_gt {
struct intel_uc uc;
struct intel_gt_timelines {
- struct mutex mutex; /* protects list */
+ spinlock_t lock; /* protects active_list */
struct list_head active_list;
/* Pack multiple timelines' seqnos into the same page */
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index ec85740de942..077716442c90 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -811,7 +811,7 @@ static bool __intel_gt_unset_wedged(struct intel_gt *gt)
*
* No more can be submitted until we reset the wedged bit.
*/
- mutex_lock(&timelines->mutex);
+ spin_lock(&timelines->lock);
list_for_each_entry(tl, &timelines->active_list, link) {
struct i915_request *rq;
@@ -819,6 +819,8 @@ static bool __intel_gt_unset_wedged(struct intel_gt *gt)
if (!rq)
continue;
+ spin_unlock(&timelines->lock);
+
/*
* All internal dependencies (i915_requests) will have
* been flushed by the set-wedge, but we may be stuck waiting
@@ -828,8 +830,12 @@ static bool __intel_gt_unset_wedged(struct intel_gt *gt)
*/
dma_fence_default_wait(&rq->fence, false, MAX_SCHEDULE_TIMEOUT);
i915_request_put(rq);
+
+ /* Restart iteration after droping lock */
+ spin_lock(&timelines->lock);
+ tl = list_entry(&timelines->active_list, typeof(*tl), link);
}
- mutex_unlock(&timelines->mutex);
+ spin_unlock(&timelines->lock);
intel_gt_sanitize(gt, false);
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c
b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 4af0b9801d91..355dfc52c804 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -266,7 +266,7 @@ static void timelines_init(struct intel_gt *gt)
{
struct intel_gt_timelines *timelines = >->timelines;
- mutex_init(&timelines->mutex);
+ spin_lock_init(&timelines->lock);
INIT_LIST_HEAD(&timelines->active_list);
spin_lock_init(&timelines->hwsp_lock);
@@ -345,9 +345,9 @@ void intel_timeline_enter(struct intel_timeline *tl)
return;
GEM_BUG_ON(!tl->active_count); /* overflow? */
- mutex_lock(&timelines->mutex);
+ spin_lock(&timelines->lock);
list_add(&tl->link, &timelines->active_list);
- mutex_unlock(&timelines->mutex);
+ spin_unlock(&timelines->lock);
}
void intel_timeline_exit(struct intel_timeline *tl)
@@ -358,9 +358,9 @@ void intel_timeline_exit(struct intel_timeline *tl)
if (--tl->active_count)
return;
- mutex_lock(&timelines->mutex);
+ spin_lock(&timelines->lock);
list_del(&tl->link);
- mutex_unlock(&timelines->mutex);
+ spin_unlock(&timelines->lock);
/*
* Since this timeline is idle, all bariers upon which we were waiting
@@ -548,8 +548,6 @@ static void timelines_fini(struct intel_gt *gt)
GEM_BUG_ON(!list_empty(&timelines->active_list));
GEM_BUG_ON(!list_empty(&timelines->hwsp_free_list));
-
- mutex_destroy(&timelines->mutex);
}
void intel_timelines_fini(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4752a3bf9636..29be25a7aade 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -897,18 +897,18 @@ static long
wait_for_timelines(struct drm_i915_private *i915,
unsigned int flags, long timeout)
{
- struct intel_gt_timelines *gt = &i915->gt.timelines;
+ struct intel_gt_timelines *timelines = &i915->gt.timelines;
struct intel_timeline *tl;
- mutex_lock(>->mutex);
- list_for_each_entry(tl, >->active_list, link) {
+ spin_lock(&timelines->lock);
+ list_for_each_entry(tl, &timelines->active_list, link) {
struct i915_request *rq;
rq = i915_active_request_get_unlocked(&tl->last_request);
if (!rq)
[Intel-gfx] [PATCH 01/18] drm/i915/guc: Use a local cancel_port_requests
Since execlista and the guc have diverged in their port tracking, we
cannot simply reuse the execlists cancellation code as it leads to
unbalanced reference counting. Use a local simpler routine for the guc.
Signed-off-by: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_engine.h| 3 ---
drivers/gpu/drm/i915/gt/intel_lrc.c | 6 ++---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 23 +++
3 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index e1228b0e577f..4b6a1cf80706 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -136,9 +136,6 @@ execlists_active(const struct intel_engine_execlists
*execlists)
return READ_ONCE(*execlists->active);
}
-void
-execlists_cancel_port_requests(struct intel_engine_execlists * const
execlists);
-
struct i915_request *
execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b97047d58d3d..5c26c4ae139b 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1297,8 +1297,8 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
}
}
-void
-execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)
+static void
+cancel_port_requests(struct intel_engine_execlists * const execlists)
{
struct i915_request * const *port, *rq;
@@ -2355,7 +2355,7 @@ static void __execlists_reset(struct intel_engine_cs
*engine, bool stalled)
unwind:
/* Push back any incomplete requests for replay after the reset. */
- execlists_cancel_port_requests(execlists);
+ cancel_port_requests(execlists);
__unwind_incomplete_requests(engine);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 449ca6357018..a37afc6266ec 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -517,11 +517,7 @@ static struct i915_request *schedule_in(struct
i915_request *rq, int idx)
{
trace_i915_request_in(rq, idx);
- if (!rq->hw_context->inflight)
- rq->hw_context->inflight = rq->engine;
- intel_context_inflight_inc(rq->hw_context);
intel_gt_pm_get(rq->engine->gt);
-
return i915_request_get(rq);
}
@@ -529,10 +525,6 @@ static void schedule_out(struct i915_request *rq)
{
trace_i915_request_out(rq);
- intel_context_inflight_dec(rq->hw_context);
- if (!intel_context_inflight_count(rq->hw_context))
- rq->hw_context->inflight = NULL;
-
intel_gt_pm_put(rq->engine->gt);
i915_request_put(rq);
}
@@ -636,6 +628,17 @@ static void guc_reset_prepare(struct intel_engine_cs
*engine)
__tasklet_disable_sync_once(&execlists->tasklet);
}
+static void
+cancel_port_requests(struct intel_engine_execlists * const execlists)
+{
+ struct i915_request * const *port, *rq;
+
+ for (port = execlists->active; (rq = *port); port++)
+ schedule_out(rq);
+ execlists->active =
+ memset(execlists->inflight, 0, sizeof(execlists->inflight));
+}
+
static void guc_reset(struct intel_engine_cs *engine, bool stalled)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
@@ -644,7 +647,7 @@ static void guc_reset(struct intel_engine_cs *engine, bool
stalled)
spin_lock_irqsave(&engine->active.lock, flags);
- execlists_cancel_port_requests(execlists);
+ cancel_port_requests(execlists);
/* Push back any incomplete requests for replay after the reset. */
rq = execlists_unwind_incomplete_requests(execlists);
@@ -687,7 +690,7 @@ static void guc_cancel_requests(struct intel_engine_cs
*engine)
spin_lock_irqsave(&engine->active.lock, flags);
/* Cancel the requests on the HW and clear the ELSP tracker. */
- execlists_cancel_port_requests(execlists);
+ cancel_port_requests(execlists);
/* Mark all executing requests as skipped. */
list_for_each_entry(rq, &engine->active.requests, sched.link) {
--
2.23.0.rc1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/18] drm/i915: Protect request retirement with timeline->mutex
Forgo the struct_mutex requirement for request retirement as we have
been transitioning over to only using the timeline->mutex for
controlling the lifetime of a request on that timeline.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 183 ++
drivers/gpu/drm/i915/gt/intel_context.h | 18 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 -
drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 -
drivers/gpu/drm/i915/gt/intel_gt.c| 2 -
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 -
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
drivers/gpu/drm/i915/gt/intel_ringbuffer.c| 19 +-
drivers/gpu/drm/i915/gt/mock_engine.c | 1 -
drivers/gpu/drm/i915/gt/selftest_context.c| 9 +-
drivers/gpu/drm/i915/i915_request.c | 156 +++
drivers/gpu/drm/i915/i915_request.h | 3 -
12 files changed, 209 insertions(+), 189 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 533db2b1fae9..b8432c3437e9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -735,63 +735,6 @@ static int eb_select_context(struct i915_execbuffer *eb)
return 0;
}
-static struct i915_request *__eb_wait_for_ring(struct intel_ring *ring)
-{
- struct i915_request *rq;
-
- /*
-* Completely unscientific finger-in-the-air estimates for suitable
-* maximum user request size (to avoid blocking) and then backoff.
-*/
- if (intel_ring_update_space(ring) >= PAGE_SIZE)
- return NULL;
-
- /*
-* Find a request that after waiting upon, there will be at least half
-* the ring available. The hysteresis allows us to compete for the
-* shared ring and should mean that we sleep less often prior to
-* claiming our resources, but not so long that the ring completely
-* drains before we can submit our next request.
-*/
- list_for_each_entry(rq, &ring->request_list, ring_link) {
- if (__intel_ring_space(rq->postfix,
- ring->emit, ring->size) > ring->size / 2)
- break;
- }
- if (&rq->ring_link == &ring->request_list)
- return NULL; /* weird, we will check again later for real */
-
- return i915_request_get(rq);
-}
-
-static int eb_wait_for_ring(const struct i915_execbuffer *eb)
-{
- struct i915_request *rq;
- int ret = 0;
-
- /*
-* Apply a light amount of backpressure to prevent excessive hogs
-* from blocking waiting for space whilst holding struct_mutex and
-* keeping all of their resources pinned.
-*/
-
- rq = __eb_wait_for_ring(eb->context->ring);
- if (rq) {
- mutex_unlock(&eb->i915->drm.struct_mutex);
-
- if (i915_request_wait(rq,
- I915_WAIT_INTERRUPTIBLE,
- MAX_SCHEDULE_TIMEOUT) < 0)
- ret = -EINTR;
-
- i915_request_put(rq);
-
- mutex_lock(&eb->i915->drm.struct_mutex);
- }
-
- return ret;
-}
-
static int eb_lookup_vmas(struct i915_execbuffer *eb)
{
struct radix_tree_root *handles_vma = &eb->gem_context->handles_vma;
@@ -2132,10 +2075,75 @@ static const enum intel_engine_id user_ring_map[] = {
[I915_EXEC_VEBOX] = VECS0
};
-static int eb_pin_context(struct i915_execbuffer *eb, struct intel_context *ce)
+static struct i915_request *eb_throttle(struct intel_context *ce)
+{
+ struct intel_ring *ring = ce->ring;
+ struct intel_timeline *tl = ce->timeline;
+ struct i915_request *rq;
+
+ /*
+* Completely unscientific finger-in-the-air estimates for suitable
+* maximum user request size (to avoid blocking) and then backoff.
+*/
+ if (intel_ring_update_space(ring) >= PAGE_SIZE)
+ return NULL;
+
+ /*
+* Find a request that after waiting upon, there will be at least half
+* the ring available. The hysteresis allows us to compete for the
+* shared ring and should mean that we sleep less often prior to
+* claiming our resources, but not so long that the ring completely
+* drains before we can submit our next request.
+*/
+ list_for_each_entry(rq, &tl->requests, link) {
+ if (rq->ring != ring)
+ continue;
+
+ if (__intel_ring_space(rq->postfix,
+ ring->emit, ring->size) > ring->size / 2)
+ break;
+ }
+ if (&rq->link == &tl->requests)
+ return NULL; /* weird, we will check again later for real */
+
+ return i915_request_get(rq);
+}
+
+static int
+__eb_pin_context(struct
[Intel-gfx] [PATCH 16/18] drm/i915/pmu: Use GT parked for estimating RC6 while asleep
As we track when we put the GT device to sleep upon idling, we can use
that callback to sample the current rc6 counters and record the
timestamp for estimating samples after that point while asleep.
v2: Stick to using ktime_t
v3: Track user_wakerefs that interfere with the new
intel_gt_pm_wait_for_idle
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105010
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 19
drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 +
drivers/gpu/drm/i915/i915_debugfs.c | 30 +++---
drivers/gpu/drm/i915/i915_pmu.c | 120 +++
drivers/gpu/drm/i915/i915_pmu.h | 4 +-
5 files changed, 96 insertions(+), 78 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 92e53c25424c..e62cf413a832 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -140,6 +140,21 @@ bool i915_gem_load_power_context(struct drm_i915_private
*i915)
return switch_to_kernel_context_sync(&i915->gt);
}
+static void user_forcewake(struct intel_gt *gt, bool suspend)
+{
+ int count = atomic_read(>->user_wakeref);
+
+ if (likely(!count))
+ return;
+
+ intel_gt_pm_get(gt);
+ if (suspend)
+ atomic_sub(count, >->wakeref.count);
+ else
+ atomic_add(count, >->wakeref.count);
+ intel_gt_pm_put(gt);
+}
+
void i915_gem_suspend(struct drm_i915_private *i915)
{
GEM_TRACE("\n");
@@ -147,6 +162,8 @@ void i915_gem_suspend(struct drm_i915_private *i915)
intel_wakeref_auto(&i915->ggtt.userfault_wakeref, 0);
flush_workqueue(i915->wq);
+ user_forcewake(&i915->gt, true);
+
mutex_lock(&i915->drm.struct_mutex);
/*
@@ -261,6 +278,8 @@ void i915_gem_resume(struct drm_i915_private *i915)
if (!i915_gem_load_power_context(i915))
goto err_wedged;
+ user_forcewake(&i915->gt, false);
+
out_unlock:
intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
mutex_unlock(&i915->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 8da7b9f1f46e..7db661bf75fa 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -49,6 +49,7 @@ struct intel_gt {
} timelines;
struct intel_wakeref wakeref;
+ atomic_t user_wakeref;
struct list_head closed_vma;
spinlock_t closed_lock; /* guards the list of closed_vma */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index aed549906410..a89937150f47 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3655,8 +3655,12 @@ i915_drop_caches_set(void *data, u64 val)
mutex_unlock(&i915->drm.struct_mutex);
- if (ret == 0 && val & DROP_IDLE)
- ret = intel_gt_pm_wait_for_idle(&i915->gt);
+ if (ret == 0 && val & DROP_IDLE) {
+ if (atomic_read(&i915->gt.user_wakeref))
+ ret = -EBUSY;
+ else
+ ret = intel_gt_pm_wait_for_idle(&i915->gt);
+ }
}
if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(&i915->gt))
@@ -3984,13 +3988,12 @@ static int i915_sseu_status(struct seq_file *m, void
*unused)
static int i915_forcewake_open(struct inode *inode, struct file *file)
{
struct drm_i915_private *i915 = inode->i_private;
+ struct intel_gt *gt = &i915->gt;
- if (INTEL_GEN(i915) < 6)
- return 0;
-
- file->private_data =
- (void *)(uintptr_t)intel_runtime_pm_get(&i915->runtime_pm);
- intel_uncore_forcewake_user_get(&i915->uncore);
+ atomic_inc(>->user_wakeref);
+ intel_gt_pm_get(gt);
+ if (INTEL_GEN(i915) >= 6)
+ intel_uncore_forcewake_user_get(gt->uncore);
return 0;
}
@@ -3998,13 +4001,12 @@ static int i915_forcewake_open(struct inode *inode,
struct file *file)
static int i915_forcewake_release(struct inode *inode, struct file *file)
{
struct drm_i915_private *i915 = inode->i_private;
+ struct intel_gt *gt = &i915->gt;
- if (INTEL_GEN(i915) < 6)
- return 0;
-
- intel_uncore_forcewake_user_put(&i915->uncore);
- intel_runtime_pm_put(&i915->runtime_pm,
-(intel_wakeref_t)(uintptr_t)file->private_data);
+ if (INTEL_GEN(i915) >= 6)
+ intel_uncore_forcewake_user_put(&i915->uncore);
+ intel_gt_pm_put(gt);
+ atomic_dec(>->user_wakeref);
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index c7ee0ab180e8..2faefe9e630e 100644
--- a/drivers/gpu/drm/i915/i9
[Intel-gfx] [PATCH 09/18] drm/i915/gt: Mark context->active_count as protected by timeline->mutex
We use timeline->mutex to protect modifications to
context->active_count, and the associated enable/disable callbacks.
Due to complications with engine-pm barrier there is a path where we used
a "superlock" to provide serialised protect and so could not
unconditionally assert with lockdep that it was always held. However,
we can mark the mutex as taken (noting that we may be nested underneath
ourselves) which means we can be reassured the right timeline->mutex is
always treated as held and let lockdep roam free.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_context.h | 3 +++
drivers/gpu/drm/i915/gt/intel_context_types.h | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 14 ++
drivers/gpu/drm/i915/gt/intel_timeline.c | 4
drivers/gpu/drm/i915/i915_request.c | 3 ++-
5 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
b/drivers/gpu/drm/i915/gt/intel_context.h
index 053a1307ecb4..dd742ac2fbdb 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -89,17 +89,20 @@ void intel_context_exit_engine(struct intel_context *ce);
static inline void intel_context_enter(struct intel_context *ce)
{
+ lockdep_assert_held(&ce->timeline->mutex);
if (!ce->active_count++)
ce->ops->enter(ce);
}
static inline void intel_context_mark_active(struct intel_context *ce)
{
+ lockdep_assert_held(&ce->timeline->mutex);
++ce->active_count;
}
static inline void intel_context_exit(struct intel_context *ce)
{
+ lockdep_assert_held(&ce->timeline->mutex);
GEM_BUG_ON(!ce->active_count);
if (!--ce->active_count)
ce->ops->exit(ce);
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index d8ce266c049f..bf9cedfccbf0 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -59,7 +59,7 @@ struct intel_context {
u32 *lrc_reg_state;
u64 lrc_desc;
- unsigned int active_count; /* notionally protected by timeline->mutex */
+ unsigned int active_count; /* protected by timeline->mutex */
atomic_t pin_count;
struct mutex pin_mutex; /* guards pinning and associated on-gpuing */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index d6a00a04ed6d..f4358f75193e 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -37,6 +37,16 @@ static int __engine_unpark(struct intel_wakeref *wf)
return 0;
}
+static inline void __timeline_mark_lock(struct intel_context *ce)
+{
+ mutex_acquire(&ce->timeline->mutex.dep_map, 2, 0, _THIS_IP_);
+}
+
+static inline void __timeline_mark_unlock(struct intel_context *ce)
+{
+ mutex_release(&ce->timeline->mutex.dep_map, 0, _THIS_IP_);
+}
+
static bool switch_to_kernel_context(struct intel_engine_cs *engine)
{
struct i915_request *rq;
@@ -61,6 +71,8 @@ static bool switch_to_kernel_context(struct intel_engine_cs
*engine)
* retiring the last request, thus all rings should be empty and
* all timelines idle.
*/
+ __timeline_mark_lock(engine->kernel_context);
+
rq = __i915_request_create(engine->kernel_context, GFP_NOWAIT);
if (IS_ERR(rq))
/* Context switch failed, hope for the best! Maybe reset? */
@@ -78,6 +90,8 @@ static bool switch_to_kernel_context(struct intel_engine_cs
*engine)
__intel_wakeref_defer_park(&engine->wakeref);
__i915_request_queue(rq, NULL);
+ __timeline_mark_unlock(engine->kernel_context);
+
return false;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c
b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 7b476cd55dac..eafd94d5e211 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -338,6 +338,8 @@ void intel_timeline_enter(struct intel_timeline *tl)
{
struct intel_gt_timelines *timelines = &tl->gt->timelines;
+ lockdep_assert_held(&tl->mutex);
+
GEM_BUG_ON(!atomic_read(&tl->pin_count));
if (tl->active_count++)
return;
@@ -352,6 +354,8 @@ void intel_timeline_exit(struct intel_timeline *tl)
{
struct intel_gt_timelines *timelines = &tl->gt->timelines;
+ lockdep_assert_held(&tl->mutex);
+
GEM_BUG_ON(!tl->active_count);
if (--tl->active_count)
return;
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 74b611ab60a2..7170ccb3c677 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1087,7 +1087,8 @@ __i915_request_add_to_timeline(struct i915_request *rq)
* precludes optimising to use semaphores serialisation of
Re: [Intel-gfx] [PATCH i-g-t] lib/i915: Trim ring measurement by one
Quoting Mika Kuoppala (2019-08-12 12:52:56) > Chris Wilson writes: > > > Be a little more conservative in our ring measurement and exclude one > > batch to leave room in case our user needs to wrap (where a request will > > be expanded to cover the unused space at the end of the ring). > > > > did read the wrapping part and that seems to be the case that > we enlarge the wrapping request. > > However do we lose some coverage on the actual wrap tests? The tests where we call measure_ring_size, are those that we do not want to block due to running out of space (and wrapping) :) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/8] drm/i915/execlists: Avoid sync calls during park (rev2)
== Series Details == Series: series starting with [1/8] drm/i915/execlists: Avoid sync calls during park (rev2) URL : https://patchwork.freedesktop.org/series/65080/ State : success == Summary == CI Bug Log - changes from CI_DRM_6685 -> Patchwork_13984 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13984/ Known issues Here are the changes found in Patchwork_13984 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_fence@basic-wait-default: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/fi-icl-u3/igt@gem_exec_fe...@basic-wait-default.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13984/fi-icl-u3/igt@gem_exec_fe...@basic-wait-default.html * igt@gem_exec_suspend@basic-s4-devices: - fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13984/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_selftest@live_execlists: - fi-skl-gvtdvm: [PASS][5] -> [DMESG-FAIL][6] ([fdo#08]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13984/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7567u: [PASS][7] -> [FAIL][8] ([fdo#109485]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13984/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: [PASS][9] -> [FAIL][10] ([fdo#103167]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13984/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html * igt@prime_vgem@basic-fence-flip: - fi-kbl-7500u: [PASS][11] -> [SKIP][12] ([fdo#109271]) +23 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13984/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html Possible fixes * igt@gem_mmap_gtt@basic-read-write: - fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13984/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html * igt@i915_selftest@live_active: - fi-bsw-n3050: [DMESG-WARN][15] ([fdo#111373]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/fi-bsw-n3050/igt@i915_selftest@live_active.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13984/fi-bsw-n3050/igt@i915_selftest@live_active.html * igt@kms_chamelium@dp-crc-fast: - fi-cml-u2: [FAIL][17] ([fdo#109483]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13984/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 [fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08 [fdo#111373]: https://bugs.freedesktop.org/show_bug.cgi?id=111373 Participating hosts (55 -> 47) -- Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6685 -> Patchwork_13984 CI-20190529: 20190529 CI_DRM_6685: acabc817e999dd7a158654fb207f7e61d68295f9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5127: f43f5fa12ac1b93febfe3eeb9e9985f5f3e2eff0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13984: 78d72ec3911b38f273d4d782fa15bf43f2ad72af @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 78d72ec3911b drm/i915/execlists: Lift process_csb() out of the irq-off spinlock 01856543d38e drm/i915/gt: Use the lo
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/uc: Update copyright and license
== Series Details ==
Series: drm/i915/uc: Update copyright and license
URL : https://patchwork.freedesktop.org/series/65083/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6685 -> Patchwork_13983
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13983/
Known issues
Here are the changes found in Patchwork_13983 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/fi-blb-e6850/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13983/fi-blb-e6850/igt@i915_module_l...@reload.html
* igt@i915_selftest@live_workarounds:
- fi-bsw-n3050: [PASS][3] -> [DMESG-WARN][4] ([fdo#111373])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/fi-bsw-n3050/igt@i915_selftest@live_workarounds.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13983/fi-bsw-n3050/igt@i915_selftest@live_workarounds.html
* igt@kms_addfb_basic@bad-pitch-999:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/fi-icl-u3/igt@kms_addfb_ba...@bad-pitch-999.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13983/fi-icl-u3/igt@kms_addfb_ba...@bad-pitch-999.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][7] -> [FAIL][8] ([fdo#103167])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13983/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-7500u: [PASS][9] -> [SKIP][10] ([fdo#109271]) +23 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13983/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html
Possible fixes
* igt@gem_mmap_gtt@basic-read-write:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13983/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html
* igt@kms_busy@basic-flip-c:
- fi-kbl-7500u: [SKIP][13] ([fdo#109271] / [fdo#109278]) ->
[PASS][14] +2 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13983/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [FAIL][15] ([fdo#109483]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13983/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][17] ([fdo#109485]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6685/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13983/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106350]: https://bugs.freedesktop.org/show_bug.cgi?id=106350
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046
[fdo#111373]: https://bugs.freedesktop.org/show_bug.cgi?id=111373
Participating hosts (55 -> 46)
--
Missing(9): fi-kbl-soraka fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u
fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6685 -> Patchwork_13983
CI-20190529: 20190529
CI_DRM_6685: acab
