Re: [Intel-gfx] [PATCH v7 1/8] overflow: Move and add few utility macros into overflow
On 8/23/22 5:12 AM, Kees Cook wrote:
On Tue, Aug 23, 2022 at 04:32:10AM +0900, Gwan-gyeong Mun wrote:
On 8/22/22 11:05 PM, Andrzej Hajda wrote:
On 18.08.2022 02:12, Kees Cook wrote:
On Thu, Aug 18, 2022 at 01:07:29AM +0200, Andi Shyti wrote:
[...]
+#define safe_conversion(ptr, value) ({ \
+ typeof(value) __v = (value); \
+ typeof(ptr) __ptr = (ptr); \
+ overflows_type(__v, *__ptr) ? 0 : ((*__ptr =
(typeof(*__ptr))__v), 1); \
+})
I try to avoid "safe" as an adjective for interface names, since it
doesn't really answer "safe from what?" This looks more like "assign, but
zero when out of bounds". And it can be built from existing macros here:
if (check_add_overflow(0, value, ptr))
*ptr = 0;
I actually want to push back on this a bit, because there can still be
logic bugs built around this kind of primitive. Shouldn't out-of-bounds
assignments be seen as a direct failure? I would think this would be
sufficient:
#define check_assign(value, ptr) check_add_overflow(0, value, ptr)
And callers would do:
if (check_assign(value, &var))
return -EINVAL;
Yes, I also like check_assign() you suggested more than safe_conversion.
As shown below, it would be more readable to return true when assign
succeeds and false when it fails. What do you think?
No, this inverts the style of all the other check_*() functions, so it
should remain "non-zero is failure".
Hi Kees,
Yes, I will not invert this part as you commented.
/**
* check_assign - perform a type conversion (cast) of an source value into
* a new variable, checking that the destination is large enough to hold the
* source value.
*
* @value: Source value
* @ptr: Destination pointer address, If the pointer type is not used, a
warning message is output during build.
*
* Returns:
* If the value would overflow the destination, it returns false. If not
return true.
*/
#define check_assign(value, ptr) __must_check_overflow(({ \
typecheck_pointer(ptr); \
!__builtin_add_overflow(0, value, ptr); \
}))
Please don't use the __builtin*s, instead stick to the check_* family,
as they correctly wrap the builtins and perform type checking, etc. As
mentioned, check_assign() should just be:
#define check_assign(value, ptr) check_add_overflow(0, value, ptr)
I don't think any of the other code is needed? What's the use-case for
the other stuff? i.e. Why does anything need overflows_type()?
And, the reason for using the __builtin_add_overflow() built-in function
directly instead of using the check_add_overflow() function is ,
#define check_add_overflow(a, b, d) __must_check_overflow(({\
typeof(a) __a = (a);\
typeof(b) __b = (b);\
typeof(d) __d = (d);\
(void) (&__a == &__b); \
(void) (&__a == __d); \
__builtin_add_overflow(__a, __b, __d); \
}))
In this part of the implementation of check_add_overflow()
(void) (&__a == &__b);
(void) (&__a == __d);
When comparing the pointer types of a, b, and d, if the pointer types of
source and ptr in check_assign() are different, a warning may occur when
building, I used the __builtin_add_overflow() built-in function directly.
Br,
G.G.
-Kees
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/combo_phy: Set DCC_MODE to one time update mode
== Series Details == Series: drm/i915/combo_phy: Set DCC_MODE to one time update mode URL : https://patchwork.freedesktop.org/series/107551/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12009_full -> Patchwork_107551v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_107551v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_107551v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (13 -> 12) -- Missing(1): shard-dg1 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_107551v1_full: ### IGT changes ### Possible regressions * igt@gem_exec_fair@basic-none-rrul: - shard-kbl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107551v1/shard-kbl7/igt@gem_exec_f...@basic-none-rrul.html Known issues Here are the changes found in Patchwork_107551v1_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-snb: ([PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26]) -> ([PASS][27], [PASS][28], [PASS][29], [FAIL][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51]) ([i915#4338]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb6/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb6/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb6/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb6/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb6/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb6/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb4/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb4/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb4/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb4/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb4/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb4/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb2/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb2/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb2/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb2/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb2/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107551v1/shard-snb2/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107551v1/shard-snb2/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107551v1/shard-snb5/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107551v1/shard-snb5/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107551v1/shard-snb5/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107551v1/shard-snb5/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107551v1/shard-snb6/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107551v1/shard-snb6/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107551v1/shard-snb6/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107551v1/shard-snb
[Intel-gfx] ✓ Fi.CI.IGT: success for Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes
== Series Details == Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes URL : https://patchwork.freedesktop.org/series/107550/ State : success == Summary == CI Bug Log - changes from CI_DRM_12009_full -> Patchwork_107550v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (13 -> 13) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_107550v1_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-snb: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [FAIL][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) ([i915#4338]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb6/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb6/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb6/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb6/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb6/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb6/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb4/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb4/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb4/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb4/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb4/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb4/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb2/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb2/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb2/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb2/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb2/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb6/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb6/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb6/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb6/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb6/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb5/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb5/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb5/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb5/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb5/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb5/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb5/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb4/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb4/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb4/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb4/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb4/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchw
[Intel-gfx] [PATCH 16/19] drm/i915/perf: Apply Wa_18013179988
OA reports in the OA buffer contain an OA timestamp field that helps
user calculate delta between 2 OA reports. The calculation relies on the
CS timestamp frequency to convert the timestamp value to nanoseconds.
The CS timestamp frequency is a function of the CTC_SHIFT value in
RPM_CONFIG0.
In DG2, OA unit assumes that the CTC_SHIFT is 3, instead of using the
actual value from RPM_CONFIG0. At the user level, this results in an
error in calculating delta between 2 OA reports since the OA timestamp
is not shifted in the same manner as CS timestamp.
To resolve this, return actual OA timestamp frequency to the user in
i915_getparam_ioctl.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_getparam.c | 3 +++
drivers/gpu/drm/i915/i915_perf.c | 30 ++--
drivers/gpu/drm/i915/i915_perf.h | 2 ++
include/uapi/drm/i915_drm.h | 6 ++
4 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_getparam.c
b/drivers/gpu/drm/i915/i915_getparam.c
index 6fd15b39570c..cdb2208ecabd 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -175,6 +175,9 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
case I915_PARAM_PERF_REVISION:
value = i915_perf_ioctl_version();
break;
+ case I915_PARAM_OA_TIMESTAMP_FREQUENCY:
+ value = i915_perf_oa_timestamp_frequency(i915);
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index ce379ac88a60..00371b4146d7 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3189,6 +3189,30 @@ get_sseu_config(struct intel_sseu *out_sseu,
return i915_gem_user_to_context_sseu(engine->gt, drm_sseu, out_sseu);
}
+/*
+ * OA timestamp frequency = CS timestamp frequency in most platforms. On some
+ * platforms OA unit ignores the CTC_SHIFT and the 2 timestamps differ. In such
+ * cases, return the adjusted CS timestamp frequency to the user.
+ */
+u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)
+{
+ /* Wa_18013179988:dg2 */
+ if (IS_DG2(i915)) {
+ intel_wakeref_t wakeref;
+ u32 reg, shift;
+
+ with_intel_runtime_pm(to_gt(i915)->uncore->rpm, wakeref)
+ reg = intel_uncore_read(to_gt(i915)->uncore,
RPM_CONFIG0);
+
+ shift = (reg & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
+GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT;
+
+ return to_gt(i915)->clock_frequency << (3 - shift);
+ }
+
+ return to_gt(i915)->clock_frequency;
+}
+
/**
* i915_oa_stream_init - validate combined props for OA stream and init
* @stream: An i915 perf stream
@@ -3913,8 +3937,10 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
{
- return intel_gt_clock_interval_to_ns(to_gt(perf->i915),
-2ULL << exponent);
+ u64 nom = (2ULL << exponent) * NSEC_PER_SEC;
+ u32 den = i915_perf_oa_timestamp_frequency(perf->i915);
+
+ return div_u64(nom + den - 1, den);
}
static __always_inline bool
diff --git a/drivers/gpu/drm/i915/i915_perf.h b/drivers/gpu/drm/i915/i915_perf.h
index 1d1329e5af3a..f96e09a4af04 100644
--- a/drivers/gpu/drm/i915/i915_perf.h
+++ b/drivers/gpu/drm/i915/i915_perf.h
@@ -57,4 +57,6 @@ static inline void i915_oa_config_put(struct i915_oa_config
*oa_config)
kref_put(&oa_config->ref, i915_oa_config_release);
}
+u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915);
+
#endif /* __I915_PERF_H__ */
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 9168412e0da8..18ada8ce1a58 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -749,6 +749,12 @@ typedef struct drm_i915_irq_wait {
/* Query if the kernel supports the I915_USERPTR_PROBE flag. */
#define I915_PARAM_HAS_USERPTR_PROBE 56
+/*
+ * Frequency of the timestamps in OA reports. This used to be the same as the
CS
+ * timestamp frequency, but differs on some platforms.
+ */
+#define I915_PARAM_OA_TIMESTAMP_FREQUENCY 57
+
/* Must be kept compact -- no holes and well documented */
/**
--
2.25.1
[Intel-gfx] [PATCH 18/19] drm/i915/guc: Support OA when Wa_16011777198 is enabled
From: Vinay Belgaumkar
There is a w/a to reset RCS/CCS before it goes into RC6. This breaks
OA. Fix it by disabling RC6.
Signed-off-by: Vinay Belgaumkar
---
.../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h | 9
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 45 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 2 +
drivers/gpu/drm/i915/i915_perf.c | 29
4 files changed, 85 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
index 4c840a2639dc..811add10c30d 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
@@ -128,6 +128,15 @@ enum slpc_media_ratio_mode {
SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO = 2,
};
+enum slpc_gucrc_mode {
+ SLPC_GUCRC_MODE_HW = 0,
+ SLPC_GUCRC_MODE_GUCRC_NO_RC6 = 1,
+ SLPC_GUCRC_MODE_GUCRC_STATIC_TIMEOUT = 2,
+ SLPC_GUCRC_MODE_GUCRC_DYNAMIC_HYSTERESIS = 3,
+
+ SLPC_GUCRC_MODE_MAX,
+};
+
enum slpc_event_id {
SLPC_EVENT_RESET = 0,
SLPC_EVENT_SHUTDOWN = 1,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index e1fa1f32f29e..23989f5452a7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -642,6 +642,51 @@ static void slpc_get_rp_values(struct intel_guc_slpc *slpc)
slpc->boost_freq = slpc->rp0_freq;
}
+/**
+ * intel_guc_slpc_override_gucrc_mode() - override GUCRC mode
+ * @slpc: pointer to intel_guc_slpc.
+ * @mode: new value of the mode.
+ *
+ * This function will override the GUCRC mode.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_override_gucrc_mode(struct intel_guc_slpc *slpc, u32 mode)
+{
+ int ret;
+ struct drm_i915_private *i915 = slpc_to_i915(slpc);
+ intel_wakeref_t wakeref;
+
+ if (mode >= SLPC_GUCRC_MODE_MAX)
+ return -EINVAL;
+
+ wakeref = intel_runtime_pm_get(&i915->runtime_pm);
+
+ ret = slpc_set_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE, mode);
+ if (ret)
+ drm_err(&i915->drm,
+ "Override gucrc mode %d failed %d\n",
+ mode, ret);
+
+ intel_runtime_pm_put(&i915->runtime_pm, wakeref);
+
+ return ret;
+}
+
+int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc)
+{
+ struct drm_i915_private *i915 = slpc_to_i915(slpc);
+ int ret = 0;
+
+ ret = slpc_unset_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE);
+ if (ret)
+ drm_err(&i915->drm,
+ "Unsetting gucrc mode failed %d\n",
+ ret);
+
+ return ret;
+}
+
/*
* intel_guc_slpc_enable() - Start SLPC
* @slpc: pointer to intel_guc_slpc.
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
index 82a98f78f96c..ccf483730d9d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
@@ -42,5 +42,7 @@ int intel_guc_slpc_set_media_ratio_mode(struct intel_guc_slpc
*slpc, u32 val);
void intel_guc_pm_intrmsk_enable(struct intel_gt *gt);
void intel_guc_slpc_boost(struct intel_guc_slpc *slpc);
void intel_guc_slpc_dec_waiters(struct intel_guc_slpc *slpc);
+int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc);
+int intel_guc_slpc_override_gucrc_mode(struct intel_guc_slpc *slpc, u32 mode);
#endif
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 00371b4146d7..ad69c9674e80 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -208,6 +208,7 @@
#include "gt/intel_lrc.h"
#include "gt/intel_lrc_reg.h"
#include "gt/intel_ring.h"
+#include "gt/uc/intel_guc_slpc.h"
#include "i915_drv.h"
#include "i915_file_private.h"
@@ -1660,6 +1661,16 @@ static void i915_oa_stream_destroy(struct
i915_perf_stream *stream)
free_oa_buffer(stream);
+ /*
+* Wa_16011777198:dg2: Unset the override of GUCRC mode to enable rc6.
+*/
+ if (intel_guc_slpc_is_used(>->uc.guc) &&
+ intel_uc_uses_guc_rc(>->uc) &&
+ (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
+IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)))
+ drm_WARN_ON(>->i915->drm,
+ intel_guc_slpc_unset_gucrc_mode(>->uc.guc.slpc));
+
intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);
intel_engine_pm_put(stream->engine);
@@ -3348,6 +3359,24 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
intel_engine_pm_get(stream->engine);
intel_uncore_forcewake_get(stream->uncore, FORCEWAKE_ALL);
+ /*
+* Wa_16011777198:dg2: GuC resets render as part of the Wa. This causes
+* OA to lose the c
[Intel-gfx] [PATCH 15/19] drm/i915/perf: Add Wa_1508761755:dg2
Disable Clock gating in EU when gathering the events so that EU events
are not lost.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/i915_perf.c| 23 +++
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index b3b49f6d6d1c..b90b88accc34 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1121,6 +1121,7 @@
#define GEN12_DISABLE_EARLY_READ REG_BIT(14)
#define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12)
#define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
+#define GEN12_DISABLE_DOP_GATING REG_BIT(0)
#define RT_CTRL_MMIO(0xe530)
#define DIS_NULL_QUERY REG_BIT(10)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 494c67e29d6c..ce379ac88a60 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2856,6 +2856,18 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
u32 sqcnt1;
int ret;
+ /*
+* Wa_1508761755:xehpsdv, dg2
+* EU NOA signals behave incorrectly if EU clock gating is enabled.
+* Disable thread stall DOP gating and EU DOP gating.
+*/
+ if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
+ intel_uncore_write(uncore, GEN8_ROW_CHICKEN,
+ _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
+ intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
+ _MASKED_BIT_ENABLE(GEN12_DISABLE_DOP_GATING));
+ }
+
intel_uncore_write(uncore, GEN12_OAG_OA_DEBUG,
/* Disable clk ratio reports, like previous Gens. */
_MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
@@ -2934,6 +2946,17 @@ static void gen12_disable_metric_set(struct
i915_perf_stream *stream)
struct drm_i915_private *i915 = stream->perf->i915;
u32 sqcnt1;
+ /*
+* Wa_1508761755:xehpsdv, dg2
+* Enable thread stall DOP gating and EU DOP gating.
+*/
+ if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
+ intel_uncore_write(uncore, GEN8_ROW_CHICKEN,
+ _MASKED_BIT_DISABLE(STALL_DOP_GATING_DISABLE));
+ intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
+ _MASKED_BIT_DISABLE(GEN12_DISABLE_DOP_GATING));
+ }
+
/* Reset all contexts' slices/subslices configurations. */
gen12_configure_all_contexts(stream, NULL, NULL);
--
2.25.1
[Intel-gfx] [PATCH 12/19] drm/i915/perf: Parse 64bit report header formats correctly
Now that OA formats come in flavor of 64 bit reports, the report header
has 64 bit report-id, timestamp, context-id and gpu-ticks fields. When
filtering these reports, use the right width for these fields.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 109 -
drivers/gpu/drm/i915/i915_perf_types.h | 6 ++
2 files changed, 94 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 41634d614ba5..c3183aedc712 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -324,8 +324,8 @@ static const struct i915_oa_format
oa_formats[I915_OA_FORMAT_MAX] = {
[I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
[I915_OAR_FORMAT_A32u40_A4u32_B8_C8]= { 5, 256 },
[I915_OA_FORMAT_A24u40_A14u32_B8_C8]= { 5, 256 },
- [I915_OAR_FORMAT_A36u64_B8_C8] = { 1, 384 },
- [I915_OA_FORMAT_A38u64_R2u64_B8_C8] = { 1, 448 },
+ [I915_OAR_FORMAT_A36u64_B8_C8] = { 1, 384, HDR_64_BIT },
+ [I915_OA_FORMAT_A38u64_R2u64_B8_C8] = { 1, 448, HDR_64_BIT },
};
#define SAMPLE_OA_REPORT (1<<0)
@@ -457,6 +457,75 @@ static u32 gen7_oa_hw_tail_read(struct i915_perf_stream
*stream)
return oastatus1 & GEN7_OASTATUS1_TAIL_MASK;
}
+#define oa_report_header_64bit(__s) \
+ ((__s)->oa_buffer.format->header == HDR_64_BIT)
+
+static inline u64
+oa_report_id(struct i915_perf_stream *stream, void *report)
+{
+ return oa_report_header_64bit(stream) ? *(u64 *)report : *(u32 *)report;
+}
+
+static inline u64
+oa_report_reason(struct i915_perf_stream *stream, void *report)
+{
+ return (oa_report_id(stream, report) >> OAREPORT_REASON_SHIFT) &
+ (GRAPHICS_VER(stream->perf->i915) == 12 ?
+ OAREPORT_REASON_MASK_EXTENDED :
+ OAREPORT_REASON_MASK);
+}
+
+static inline void
+oa_report_id_clear(struct i915_perf_stream *stream, u32 *report)
+{
+ if (oa_report_header_64bit(stream))
+ *(u64 *)report = 0;
+ else
+ *report = 0;
+}
+
+static inline bool
+oa_report_ctx_invalid(struct i915_perf_stream *stream, void *report)
+{
+ return !(oa_report_id(stream, report) &
+ stream->perf->gen8_valid_ctx_bit) &&
+ GRAPHICS_VER(stream->perf->i915) <= 11;
+}
+
+static inline u64
+oa_timestamp(struct i915_perf_stream *stream, void *report)
+{
+ return oa_report_header_64bit(stream) ?
+ *((u64 *)report + 1) :
+ *((u32 *)report + 1);
+}
+
+static inline void
+oa_timestamp_clear(struct i915_perf_stream *stream, u32 *report)
+{
+ if (oa_report_header_64bit(stream))
+ *(u64 *)&report[2] = 0;
+ else
+ report[1] = 0;
+}
+
+static inline u32
+oa_context_id(struct i915_perf_stream *stream, u32 *report)
+{
+ u32 ctx_id = oa_report_header_64bit(stream) ? report[4] : report[2];
+
+ return ctx_id & stream->specific_ctx_id_mask;
+}
+
+static inline void
+oa_context_id_squash(struct i915_perf_stream *stream, u32 *report)
+{
+ if (oa_report_header_64bit(stream))
+ report[4] = INVALID_CTX_ID;
+ else
+ report[2] = INVALID_CTX_ID;
+}
+
/**
* oa_buffer_check_unlocked - check for data and update tail ptr state
* @stream: i915 stream instance
@@ -546,9 +615,10 @@ static bool oa_buffer_check_unlocked(struct
i915_perf_stream *stream)
* If not : (╯°□°）╯︵ ┻━┻
*/
while (_oa_taken(stream, tail, aged_tail) >= report_size) {
- u32 *report32 = (void *)(stream->oa_buffer.vaddr +
tail);
+ void *report = stream->oa_buffer.vaddr + tail;
- if (report32[0] != 0 || report32[1] != 0)
+ if (oa_report_id(stream, report) ||
+ oa_timestamp(stream, report))
break;
tail = _rewind_tail(stream, tail, report_size);
@@ -741,23 +811,19 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
u8 *report = oa_buf_base + head;
u32 *report32 = (void *)report;
u32 ctx_id;
- u32 reason;
+ u64 reason;
/*
* The reason field includes flags identifying what
* triggered this specific report (mostly timer
* triggered or e.g. due to a context switch).
*
-* This field is never expected to be zero so we can
-* check that the report isn't invalid before copying
-* it to userspace...
+* In MMIO triggered reports, some platforms do not set the
+* reason bit in this field and it is valid to have a reason
+* field of zero.
*/
- rea
[Intel-gfx] [PATCH 10/19] drm/i915/perf: Use gt-specific ggtt for OA and noa-wait buffers
User passes uabi engine class and instance to the perf OA interface. Use
gt corresponding to the engine to pin the buffers to the right ggtt.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index b79321559684..e1e0d4369ea6 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1766,6 +1766,7 @@ static void gen12_init_oa_buffer(struct i915_perf_stream
*stream)
static int alloc_oa_buffer(struct i915_perf_stream *stream)
{
struct drm_i915_private *i915 = stream->perf->i915;
+ struct intel_gt *gt = stream->engine->gt;
struct drm_i915_gem_object *bo;
struct i915_vma *vma;
int ret;
@@ -1785,11 +1786,22 @@ static int alloc_oa_buffer(struct i915_perf_stream
*stream)
i915_gem_object_set_cache_coherency(bo, I915_CACHE_LLC);
/* PreHSW required 512K alignment, HSW requires 16M */
- vma = i915_gem_object_ggtt_pin(bo, NULL, 0, SZ_16M, 0);
+ vma = i915_vma_instance(bo, >->ggtt->vm, NULL);
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);
goto err_unref;
}
+
+ /*
+* PreHSW required 512K alignment.
+* HSW and onwards, align to requested size of OA buffer.
+*/
+ ret = i915_vma_pin(vma, 0, SZ_16M, PIN_GLOBAL | PIN_HIGH);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to pin OA buffer %d\n", ret);
+ goto err_unref;
+ }
+
stream->oa_buffer.vma = vma;
stream->oa_buffer.vaddr =
@@ -1839,6 +1851,7 @@ static u32 *save_restore_register(struct i915_perf_stream
*stream, u32 *cs,
static int alloc_noa_wait(struct i915_perf_stream *stream)
{
struct drm_i915_private *i915 = stream->perf->i915;
+ struct intel_gt *gt = stream->engine->gt;
struct drm_i915_gem_object *bo;
struct i915_vma *vma;
const u64 delay_ticks = 0x -
@@ -1879,12 +1892,16 @@ static int alloc_noa_wait(struct i915_perf_stream
*stream)
* multiple OA config BOs will have a jump to this address and it
* needs to be fixed during the lifetime of the i915/perf stream.
*/
- vma = i915_gem_object_ggtt_pin_ww(bo, &ww, NULL, 0, 0, PIN_HIGH);
+ vma = i915_vma_instance(bo, >->ggtt->vm, NULL);
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);
goto out_ww;
}
+ ret = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_GLOBAL | PIN_HIGH);
+ if (ret)
+ goto out_ww;
+
batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
if (IS_ERR(batch)) {
ret = PTR_ERR(batch);
--
2.25.1
[Intel-gfx] [PATCH 14/19] drm/i915/perf: Add Wa_1608133521:dg2
DG2 introduces 64 bit counters and OA reports that have 64 bit values
for fields in the report header - report_id, timestamp, context_id and
gpu ticks. i915 uses report_id, timestamp and context_id to check for
valid reports.
In some DG2 variants, only the lower dwords for timestamp, report_id and
context_id are accessible. Add workaround for such reports.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 3a1e0c5271e2..494c67e29d6c 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -310,7 +310,7 @@ static u32 i915_oa_max_sample_rate = 10;
* be used as a mask to align the OA tail pointer. In some of the
* formats, R is used to denote reserved field.
*/
-static const struct i915_oa_format oa_formats[I915_OA_FORMAT_MAX] = {
+static struct i915_oa_format oa_formats[I915_OA_FORMAT_MAX] = {
[I915_OA_FORMAT_A13]= { 0, 64 },
[I915_OA_FORMAT_A29]= { 1, 128 },
[I915_OA_FORMAT_A13_B8_C8] = { 2, 128 },
@@ -4755,6 +4755,13 @@ static void oa_init_supported_formats(struct i915_perf
*perf)
/* Wa_16010703925:dg2 */
clear_bit(I915_OAR_FORMAT_A36u64_B8_C8, perf->format_mask);
}
+
+ if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) ||
+ IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_FOREVER)) {
+ /* Wa_1608133521:dg2 */
+ oa_formats[I915_OAR_FORMAT_A36u64_B8_C8].header = HDR_32_BIT;
+ oa_formats[I915_OA_FORMAT_A38u64_R2u64_B8_C8].header =
HDR_32_BIT;
+ }
}
static void i915_perf_init_info(struct drm_i915_private *i915)
--
2.25.1
[Intel-gfx] [PATCH 11/19] drm/i915/perf: Store a pointer to oa_format in oa_buffer
DG2 introduces OA reports with 64 bit report header fields. Perf OA
would need more information about the OA format in order to process such
reports. Store all OA format info in oa_buffer instead of just the size
and format-id.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 23 ++-
drivers/gpu/drm/i915/i915_perf_types.h | 3 +--
2 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index e1e0d4369ea6..41634d614ba5 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -484,7 +484,7 @@ static u32 gen7_oa_hw_tail_read(struct i915_perf_stream
*stream)
static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream)
{
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
- int report_size = stream->oa_buffer.format_size;
+ int report_size = stream->oa_buffer.format->size;
unsigned long flags;
bool pollin;
u32 hw_tail;
@@ -631,7 +631,7 @@ static int append_oa_sample(struct i915_perf_stream *stream,
size_t *offset,
const u8 *report)
{
- int report_size = stream->oa_buffer.format_size;
+ int report_size = stream->oa_buffer.format->size;
struct drm_i915_perf_record_header header;
int report_size_partial;
u8 *oa_buf_end;
@@ -695,7 +695,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
size_t *offset)
{
struct intel_uncore *uncore = stream->uncore;
- int report_size = stream->oa_buffer.format_size;
+ int report_size = stream->oa_buffer.format->size;
u8 *oa_buf_base = stream->oa_buffer.vaddr;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
size_t start_offset = *offset;
@@ -971,7 +971,7 @@ static int gen7_append_oa_reports(struct i915_perf_stream
*stream,
size_t *offset)
{
struct intel_uncore *uncore = stream->uncore;
- int report_size = stream->oa_buffer.format_size;
+ int report_size = stream->oa_buffer.format->size;
u8 *oa_buf_base = stream->oa_buffer.vaddr;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
u32 mask = (OA_BUFFER_SIZE - 1);
@@ -2518,7 +2518,7 @@ static int gen12_configure_oar_context(struct
i915_perf_stream *stream,
{
int err;
struct intel_context *ce = stream->pinned_ctx;
- u32 format = stream->oa_buffer.format;
+ u32 format = stream->oa_buffer.format->format;
u32 offset = stream->perf->ctx_oactxctrl_offset;
struct flex regs_context[] = {
{
@@ -2891,7 +2891,7 @@ static void gen7_oa_enable(struct i915_perf_stream
*stream)
u32 ctx_id = stream->specific_ctx_id;
bool periodic = stream->periodic;
u32 period_exponent = stream->period_exponent;
- u32 report_format = stream->oa_buffer.format;
+ u32 report_format = stream->oa_buffer.format->format;
/*
* Reset buf pointers so we don't forward reports from before now.
@@ -2917,7 +2917,7 @@ static void gen7_oa_enable(struct i915_perf_stream
*stream)
static void gen8_oa_enable(struct i915_perf_stream *stream)
{
struct intel_uncore *uncore = stream->uncore;
- u32 report_format = stream->oa_buffer.format;
+ u32 report_format = stream->oa_buffer.format->format;
/*
* Reset buf pointers so we don't forward reports from before now.
@@ -2943,7 +2943,7 @@ static void gen8_oa_enable(struct i915_perf_stream
*stream)
static void gen12_oa_enable(struct i915_perf_stream *stream)
{
struct intel_uncore *uncore = stream->uncore;
- u32 report_format = stream->oa_buffer.format;
+ u32 report_format = stream->oa_buffer.format->format;
/*
* If we don't want OA reports from the OA buffer, then we don't even
@@ -3185,15 +3185,12 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
stream->sample_flags = props->sample_flags;
stream->sample_size += format_size;
- stream->oa_buffer.format_size = format_size;
- if (drm_WARN_ON(&i915->drm, stream->oa_buffer.format_size == 0))
+ stream->oa_buffer.format = &perf->oa_formats[props->oa_format];
+ if (drm_WARN_ON(&i915->drm, stream->oa_buffer.format->size == 0))
return -EINVAL;
stream->hold_preemption = props->hold_preemption;
- stream->oa_buffer.format =
- perf->oa_formats[props->oa_format].format;
-
stream->periodic = props->oa_periodic;
if (stream->periodic)
stream->period_exponent = props->oa_period_exponent;
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h
b/drivers/gpu/drm/i915/i915_perf_types.h
index dc9bfd8086cf..e0c96b44eda8 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drive
[Intel-gfx] [PATCH 17/19] drm/i915/perf: Save/restore EU flex counters across reset
If a drm client is killed, then hw contexts used by the client are reset immediately. This reset clears the EU flex counter configuration. If an OA use case is running in parallel, it would start seeing zeroed eu counter values following the reset even if the drm client is restarted. Save/restore the EU flex counter config so that the EU counters can be monitored continuously across resets. Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index 74cbe8eaf531..3e152219fcb2 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -375,6 +375,14 @@ static int guc_mmio_regset_init(struct temp_regset *regset, for (i = 0; i < GEN9_LNCFCMOCS_REG_COUNT; i++) ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false); + ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL0, false); + ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL1, false); + ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL2, false); + ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL3, false); + ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL4, false); + ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL5, false); + ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL6, false); + return ret ? -1 : 0; } -- 2.25.1
[Intel-gfx] [PATCH 08/19] drm/i915/perf: Move gt-specific data from i915->perf to gt->perf
Make perf part of gt as the OAG buffer is specific to a gt. The refactor
eventually simplifies programming the right OA buffer and the right HW
registers when supporting multiple gts.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
drivers/gpu/drm/i915/gt/intel_sseu.c | 4 +-
drivers/gpu/drm/i915/i915_perf.c | 75 +-
drivers/gpu/drm/i915/i915_perf_types.h | 39 +--
drivers/gpu/drm/i915/selftests/i915_perf.c | 16 +++--
5 files changed, 80 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 4d56f7d5a3be..3d079d206cec 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -20,6 +20,7 @@
#include "intel_gsc.h"
#include "i915_vma.h"
+#include "i915_perf_types.h"
#include "intel_engine_types.h"
#include "intel_gt_buffer_pool_types.h"
#include "intel_hwconfig.h"
@@ -260,6 +261,8 @@ struct intel_gt {
/* sysfs defaults per gt */
struct gt_defaults defaults;
struct kobject *sysfs_defaults;
+
+ struct i915_perf_gt perf;
};
enum intel_gt_scratch_field {
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index c6d3050604c8..fcaf3c58b554 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -678,8 +678,8 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
* If i915/perf is active, we want a stable powergating configuration
* on the system. Use the configuration pinned by i915/perf.
*/
- if (i915->perf.exclusive_stream)
- req_sseu = &i915->perf.sseu;
+ if (gt->perf.exclusive_stream)
+ req_sseu = >->perf.sseu;
slices = hweight8(req_sseu->slice_mask);
subslices = hweight8(req_sseu->subslice_mask);
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 7920b91e1c6b..a96085058942 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1578,8 +1578,9 @@ free_noa_wait(struct i915_perf_stream *stream)
static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
{
struct i915_perf *perf = stream->perf;
+ struct intel_gt *gt = stream->engine->gt;
- BUG_ON(stream != perf->exclusive_stream);
+ BUG_ON(stream != gt->perf.exclusive_stream);
/*
* Unset exclusive_stream first, it will be checked while disabling
@@ -1587,7 +1588,7 @@ static void i915_oa_stream_destroy(struct
i915_perf_stream *stream)
*
* See i915_oa_init_reg_state() and lrc_configure_all_contexts()
*/
- WRITE_ONCE(perf->exclusive_stream, NULL);
+ WRITE_ONCE(gt->perf.exclusive_stream, NULL);
perf->ops.disable_metric_set(stream);
free_oa_buffer(stream);
@@ -2580,10 +2581,11 @@ oa_configure_all_contexts(struct i915_perf_stream
*stream,
{
struct drm_i915_private *i915 = stream->perf->i915;
struct intel_engine_cs *engine;
+ struct intel_gt *gt = stream->engine->gt;
struct i915_gem_context *ctx, *cn;
int err;
- lockdep_assert_held(&stream->perf->lock);
+ lockdep_assert_held(>->perf.lock);
/*
* The OA register config is setup through the context image. This image
@@ -3104,6 +3106,7 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
{
struct drm_i915_private *i915 = stream->perf->i915;
struct i915_perf *perf = stream->perf;
+ struct intel_gt *gt;
int format_size;
int ret;
@@ -3112,6 +3115,7 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
"OA engine not specified\n");
return -EINVAL;
}
+ gt = props->engine->gt;
/*
* If the sysfs metrics/ directory wasn't registered for some
@@ -3142,7 +3146,7 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
* counter reports and marshal to the appropriate client
* we currently only allow exclusive access
*/
- if (perf->exclusive_stream) {
+ if (gt->perf.exclusive_stream) {
drm_dbg(&stream->perf->i915->drm,
"OA unit already in use\n");
return -EBUSY;
@@ -3222,8 +3226,8 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
stream->ops = &i915_oa_stream_ops;
- perf->sseu = props->sseu;
- WRITE_ONCE(perf->exclusive_stream, stream);
+ stream->engine->gt->perf.sseu = props->sseu;
+ WRITE_ONCE(gt->perf.exclusive_stream, stream);
ret = i915_perf_stream_enable_sync(stream);
if (ret) {
@@ -3245,7 +3249,7 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
return 0;
err_enable:
- WRITE_ONCE(perf->exclusive_stream, NULL);
+
[Intel-gfx] [PATCH 05/19] drm/i915/perf: Enable commands per clock reporting in OA
XEHPSDV and DG2 provide a way to configure bytes per clock vs commands
per clock reporting. Enable command per clock setting on enabling OA.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_perf.c | 20
drivers/gpu/drm/i915/i915_perf_oa_regs.h | 4
drivers/gpu/drm/i915/intel_device_info.h | 1 +
5 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 086bbe8945d6..b1a13cfd8c09 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1287,6 +1287,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
+#define HAS_OA_BPC_REPORTING(dev_priv) \
+ (INTEL_INFO(dev_priv)->has_oa_bpc_reporting)
+
/*
* Set this flag, when platform requires 64K GTT page sizes or larger for
* device local memory access.
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 9fd788e147a3..3427042beab3 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1019,6 +1019,7 @@ static const struct intel_device_info adl_p_info = {
.has_logical_ring_contexts = 1, \
.has_logical_ring_elsq = 1, \
.has_mslice_steering = 1, \
+ .has_oa_bpc_reporting = 1, \
.has_rc6 = 1, \
.has_reset_engine = 1, \
.has_rps = 1, \
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index efa7eda83edd..6fc4f0d8fc5a 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2745,10 +2745,12 @@ static int
gen12_enable_metric_set(struct i915_perf_stream *stream,
struct i915_active *active)
{
+ struct drm_i915_private *i915 = stream->perf->i915;
struct intel_uncore *uncore = stream->uncore;
struct i915_oa_config *oa_config = stream->oa_config;
bool periodic = stream->periodic;
u32 period_exponent = stream->period_exponent;
+ u32 sqcnt1;
int ret;
intel_uncore_write(uncore, GEN12_OAG_OA_DEBUG,
@@ -2767,6 +2769,16 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
(period_exponent <<
GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT))
: 0);
+ /*
+* Initialize Super Queue Internal Cnt Register
+* Set PMON Enable in order to collect valid metrics.
+* Enable commands per clock reporting in OA for XEHPSDV onward.
+*/
+ sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
+(HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
+
+ intel_uncore_rmw(uncore, GEN12_SQCNT1, 0, sqcnt1);
+
/*
* Update all contexts prior writing the mux configurations as we need
* to make sure all slices/subslices are ON before writing to NOA
@@ -2816,6 +2828,8 @@ static void gen11_disable_metric_set(struct
i915_perf_stream *stream)
static void gen12_disable_metric_set(struct i915_perf_stream *stream)
{
struct intel_uncore *uncore = stream->uncore;
+ struct drm_i915_private *i915 = stream->perf->i915;
+ u32 sqcnt1;
/* Reset all contexts' slices/subslices configurations. */
gen12_configure_all_contexts(stream, NULL, NULL);
@@ -2826,6 +2840,12 @@ static void gen12_disable_metric_set(struct
i915_perf_stream *stream)
/* Make sure we disable noa to save power. */
intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
+
+ sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
+(HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
+
+ /* Reset PMON Enable to save power. */
+ intel_uncore_rmw(uncore, GEN12_SQCNT1, sqcnt1, 0);
}
static void gen7_oa_enable(struct i915_perf_stream *stream)
diff --git a/drivers/gpu/drm/i915/i915_perf_oa_regs.h
b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
index 0ef3562ff4aa..381d94101610 100644
--- a/drivers/gpu/drm/i915/i915_perf_oa_regs.h
+++ b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
@@ -134,4 +134,8 @@
#define GDT_CHICKEN_BITS_MMIO(0x9840)
#define GT_NOA_ENABLE0x0080
+#define GEN12_SQCNT1 _MMIO(0x8718)
+#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
+#define GEN12_SQCNT1_OABPC REG_BIT(29)
+
#endif /* __INTEL_PERF_OA_REGS__ */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 23bf230aa104..fc2a0660426e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -163,6 +163,7 @@ enum intel_ppgtt_type {
func(has_logical_ring_elsq); \
func(has_media_ratio_mode); \
func(has_mslice_steering); \
+
[Intel-gfx] [PATCH 09/19] drm/i915/perf: Replace gt->perf.lock with stream->lock for file ops
With multi-gt, user can access multiple OA buffers concurrently. Use
stream->lock instead of gt->perf.lock to serialize file operations.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 31 --
drivers/gpu/drm/i915/i915_perf_types.h | 5 +
2 files changed, 19 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index a96085058942..b79321559684 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3245,6 +3245,7 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
stream->poll_check_timer.function = oa_poll_check_timer_cb;
init_waitqueue_head(&stream->poll_wq);
spin_lock_init(&stream->oa_buffer.ptr_lock);
+ mutex_init(&stream->lock);
return 0;
@@ -3308,7 +3309,6 @@ static ssize_t i915_perf_read(struct file *file,
loff_t *ppos)
{
struct i915_perf_stream *stream = file->private_data;
- struct intel_gt *gt = stream->engine->gt;
size_t offset = 0;
int ret;
@@ -3332,14 +3332,14 @@ static ssize_t i915_perf_read(struct file *file,
if (ret)
return ret;
- mutex_lock(>->perf.lock);
+ mutex_lock(&stream->lock);
ret = stream->ops->read(stream, buf, count, &offset);
- mutex_unlock(>->perf.lock);
+ mutex_unlock(&stream->lock);
} while (!offset && !ret);
} else {
- mutex_lock(>->perf.lock);
+ mutex_lock(&stream->lock);
ret = stream->ops->read(stream, buf, count, &offset);
- mutex_unlock(>->perf.lock);
+ mutex_unlock(&stream->lock);
}
/* We allow the poll checking to sometimes report false positive EPOLLIN
@@ -3386,9 +3386,6 @@ static enum hrtimer_restart oa_poll_check_timer_cb(struct
hrtimer *hrtimer)
* &i915_perf_stream_ops->poll_wait to call poll_wait() with a wait queue that
* will be woken for new stream data.
*
- * Note: The >->perf.lock mutex has been taken to serialize
- * with any non-file-operation driver hooks.
- *
* Returns: any poll events that are ready without sleeping
*/
static __poll_t i915_perf_poll_locked(struct i915_perf_stream *stream,
@@ -3427,12 +3424,11 @@ static __poll_t i915_perf_poll_locked(struct
i915_perf_stream *stream,
static __poll_t i915_perf_poll(struct file *file, poll_table *wait)
{
struct i915_perf_stream *stream = file->private_data;
- struct intel_gt *gt = stream->engine->gt;
__poll_t ret;
- mutex_lock(>->perf.lock);
+ mutex_lock(&stream->lock);
ret = i915_perf_poll_locked(stream, file, wait);
- mutex_unlock(>->perf.lock);
+ mutex_unlock(&stream->lock);
return ret;
}
@@ -3531,9 +3527,6 @@ static long i915_perf_config_locked(struct
i915_perf_stream *stream,
* @cmd: the ioctl request
* @arg: the ioctl data
*
- * Note: The >->perf.lock mutex has been taken to serialize
- * with any non-file-operation driver hooks.
- *
* Returns: zero on success or a negative error code. Returns -EINVAL for
* an unknown ioctl request.
*/
@@ -3571,12 +3564,11 @@ static long i915_perf_ioctl(struct file *file,
unsigned long arg)
{
struct i915_perf_stream *stream = file->private_data;
- struct intel_gt *gt = stream->engine->gt;
long ret;
- mutex_lock(>->perf.lock);
+ mutex_lock(&stream->lock);
ret = i915_perf_ioctl_locked(stream, cmd, arg);
- mutex_unlock(>->perf.lock);
+ mutex_unlock(&stream->lock);
return ret;
}
@@ -3622,6 +3614,11 @@ static int i915_perf_release(struct inode *inode, struct
file *file)
struct i915_perf *perf = stream->perf;
struct intel_gt *gt = stream->engine->gt;
+ /*
+* Within this call, we know that the fd is being closed and we have no
+* other user of stream->lock. Use the perf lock to destroy the stream
+* here.
+*/
mutex_lock(>->perf.lock);
i915_perf_destroy_locked(stream);
mutex_unlock(>->perf.lock);
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h
b/drivers/gpu/drm/i915/i915_perf_types.h
index e888bfab478f..dc9bfd8086cf 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -146,6 +146,11 @@ struct i915_perf_stream {
*/
struct intel_engine_cs *engine;
+ /*
+* Lock associated with operations on stream
+*/
+ struct mutex lock;
+
/**
* @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
* properties given when opening a stream, representing the contents
--
2.25.1
[Intel-gfx] [PATCH 06/19] drm/i915/perf: Use helpers to process reports w.r.t. OA buffer size
DG2 has a new feature to supports OA buffer sizes up to 128Mb by
toggling a bit in OA_DEBUG. This would eventually be a user configurable
parameter. Use OA buffer vma size in all calculations with some helpers.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 47 ++--
1 file changed, 32 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 6fc4f0d8fc5a..18cc9a311b7e 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -385,6 +385,22 @@ static struct ctl_table_header *sysctl_header;
static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
+static inline u32 _oa_taken(struct i915_perf_stream * stream,
+ u32 tail, u32 head)
+{
+ u32 size = stream->oa_buffer.vma->size;
+
+ return tail >= head ? tail - head : size - (head - tail);
+}
+
+static inline u32 _rewind_tail(struct i915_perf_stream * stream,
+ u32 relative_hw_tail, u32 rewind_delta)
+{
+ return rewind_delta > relative_hw_tail ?
+ stream->oa_buffer.vma->size - (rewind_delta - relative_hw_tail) :
+ relative_hw_tail - rewind_delta;
+}
+
void i915_oa_config_release(struct kref *ref)
{
struct i915_oa_config *oa_config =
@@ -487,12 +503,14 @@ static bool oa_buffer_check_unlocked(struct
i915_perf_stream *stream)
* sizes need not be integral multiples or 64 or powers of 2.
* Compute potentially partially landed report in the OA buffer
*/
- partial_report_size = OA_TAKEN(hw_tail, stream->oa_buffer.tail);
+ partial_report_size =
+ _oa_taken(stream, hw_tail, stream->oa_buffer.tail);
partial_report_size %= report_size;
/* Subtract partial amount off the tail */
- hw_tail = gtt_offset + ((hw_tail - partial_report_size) &
- (stream->oa_buffer.vma->size - 1));
+ hw_tail = gtt_offset + _rewind_tail(stream,
+ hw_tail - gtt_offset,
+ partial_report_size);
now = ktime_get_mono_fast_ns();
@@ -527,16 +545,16 @@ static bool oa_buffer_check_unlocked(struct
i915_perf_stream *stream)
* memory in the order they were written to.
* If not : (╯°□°）╯︵ ┻━┻
*/
- while (OA_TAKEN(tail, aged_tail) >= report_size) {
+ while (_oa_taken(stream, tail, aged_tail) >= report_size) {
u32 *report32 = (void *)(stream->oa_buffer.vaddr +
tail);
if (report32[0] != 0 || report32[1] != 0)
break;
- tail = (tail - report_size) & (OA_BUFFER_SIZE - 1);
+ tail = _rewind_tail(stream, tail, report_size);
}
- if (OA_TAKEN(hw_tail, tail) > report_size &&
+ if (_oa_taken(stream, hw_tail, tail) > report_size &&
__ratelimit(&stream->perf->tail_pointer_race))
DRM_NOTE("unlanded report(s) head=0x%x "
"tail=0x%x hw_tail=0x%x\n",
@@ -547,8 +565,9 @@ static bool oa_buffer_check_unlocked(struct
i915_perf_stream *stream)
stream->oa_buffer.aging_timestamp = now;
}
- pollin = OA_TAKEN(stream->oa_buffer.tail - gtt_offset,
- stream->oa_buffer.head - gtt_offset) >= report_size;
+ pollin = _oa_taken(stream,
+ stream->oa_buffer.tail,
+ stream->oa_buffer.head) >= report_size;
spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
@@ -679,11 +698,9 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
int report_size = stream->oa_buffer.format_size;
u8 *oa_buf_base = stream->oa_buffer.vaddr;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
- u32 mask = (OA_BUFFER_SIZE - 1);
size_t start_offset = *offset;
unsigned long flags;
- u32 head, tail;
- u32 taken;
+ u32 head, tail, size;
int ret = 0;
if (drm_WARN_ON(&uncore->i915->drm, !stream->enabled))
@@ -693,6 +710,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
head = stream->oa_buffer.head;
tail = stream->oa_buffer.tail;
+ size = stream->oa_buffer.vma->size;
spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
@@ -711,16 +729,15 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
* all a power of two).
*/
if (drm_WARN_ONCE(&uncore->i915->drm,
- head > stream->oa_buffer.vma->size ||
- tail > stream->oa_buffer.vma->size,
+ head > size || tail > siz
[Intel-gfx] [PATCH 13/19] drm/i915/perf: Add Wa_16010703925:dg2
On DG2 A0, the OAR report format is buggy. Workaround is to not use it
for A0. For A0, remove the OAR format from the bitmask of supported
formats.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index c3183aedc712..3a1e0c5271e2 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4750,6 +4750,11 @@ static void oa_init_supported_formats(struct i915_perf
*perf)
default:
MISSING_CASE(platform);
}
+
+ if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
+ /* Wa_16010703925:dg2 */
+ clear_bit(I915_OAR_FORMAT_A36u64_B8_C8, perf->format_mask);
+ }
}
static void i915_perf_init_info(struct drm_i915_private *i915)
--
2.25.1
[Intel-gfx] [PATCH 03/19] drm/i915/perf: Fix noa wait predication for DG2
Predication for batch buffer commands changed in XEHPSDV.
MI_BATCH_BUFFER_START predicates based on MI_SET_PREDICATE_RESULT
register. The MI_SET_PREDICATE_RESULT register can only be modified
with MI_SET_PREDICATE command. When configured, the MI_SET_PREDICATE
command sets MI_SET_PREDICATE_RESULT based on bit 0 of
MI_PREDICATE_RESULT_2. Use this to configure predication in noa_wait.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 1 +
drivers/gpu/drm/i915/i915_perf.c| 24 +
2 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
index 889f0df3940b..25d23f3a4769 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -200,6 +200,7 @@
#define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+
*/
#define RING_PREDICATE_RESULT(base)_MMIO((base) + 0x3b8)
+#define MI_PREDICATE_RESULT_2_ENGINE(base) _MMIO((base) + 0x3bc)
#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) *
4)
#define RING_FORCE_TO_NONPRIV_DENY REG_BIT(30)
#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index c8331b549d31..3526693d64fa 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -286,6 +286,7 @@ static u32 i915_perf_stream_paranoid = true;
#define OAREPORT_REASON_CTX_SWITCH (1<<3)
#define OAREPORT_REASON_CLK_RATIO (1<<5)
+#define HAS_MI_SET_PREDICATE(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
/* For sysctl proc_dointvec_minmax of i915_oa_max_sample_rate
*
@@ -1766,6 +1767,9 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
DELTA_TARGET,
N_CS_GPR
};
+ i915_reg_t mi_predicate_result = HAS_MI_SET_PREDICATE(i915) ?
+ MI_PREDICATE_RESULT_2_ENGINE(base) :
+
MI_PREDICATE_RESULT_1(RENDER_RING_BASE);
bo = i915_gem_object_create_internal(i915, 4096);
if (IS_ERR(bo)) {
@@ -1803,7 +1807,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
stream, cs, true /* save */, CS_GPR(i),
INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
cs = save_restore_register(
- stream, cs, true /* save */,
MI_PREDICATE_RESULT_1(RENDER_RING_BASE),
+ stream, cs, true /* save */, mi_predicate_result,
INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
/* First timestamp snapshot location. */
@@ -1857,7 +1861,10 @@ static int alloc_noa_wait(struct i915_perf_stream
*stream)
*/
*cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
*cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
- *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1(RENDER_RING_BASE));
+ *cs++ = i915_mmio_reg_offset(mi_predicate_result);
+
+ if (HAS_MI_SET_PREDICATE(i915))
+ *cs++ = MI_SET_PREDICATE | 1;
/* Restart from the beginning if we had timestamps roll over. */
*cs++ = (GRAPHICS_VER(i915) < 8 ?
@@ -1867,6 +1874,9 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
*cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4;
*cs++ = 0;
+ if (HAS_MI_SET_PREDICATE(i915))
+ *cs++ = MI_SET_PREDICATE;
+
/*
* Now add the diff between to previous timestamps and add it to :
* (((1 * << 64) - 1) - delay_ns)
@@ -1894,7 +1904,10 @@ static int alloc_noa_wait(struct i915_perf_stream
*stream)
*/
*cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
*cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
- *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1(RENDER_RING_BASE));
+ *cs++ = i915_mmio_reg_offset(mi_predicate_result);
+
+ if (HAS_MI_SET_PREDICATE(i915))
+ *cs++ = MI_SET_PREDICATE | 1;
/* Predicate the jump. */
*cs++ = (GRAPHICS_VER(i915) < 8 ?
@@ -1904,13 +1917,16 @@ static int alloc_noa_wait(struct i915_perf_stream
*stream)
*cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4;
*cs++ = 0;
+ if (HAS_MI_SET_PREDICATE(i915))
+ *cs++ = MI_SET_PREDICATE;
+
/* Restore registers. */
for (i = 0; i < N_CS_GPR; i++)
cs = save_restore_register(
stream, cs, false /* restore */, CS_GPR(i),
INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
cs = save_restore_register(
- stream, cs, false /* restore */,
MI_PREDICATE_RESULT_1(RENDER_RING_BASE),
+ stream, cs, false /* restore */, mi_predica
[Intel-gfx] [PATCH 04/19] drm/i915/perf: Determine gen12 oa ctx offset at runtime
Some SKUs of same gen12 platform may have different oactxctrl
offsets. For gen12, determine oactxctrl offsets at runtime.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 149 ++-
drivers/gpu/drm/i915/i915_perf_oa_regs.h | 2 +-
2 files changed, 120 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 3526693d64fa..efa7eda83edd 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1363,6 +1363,67 @@ static int gen12_get_render_context_id(struct
i915_perf_stream *stream)
return 0;
}
+#define MI_OPCODE(x) (((x) >> 23) & 0x3f)
+#define IS_MI_LRI_CMD(x) (MI_OPCODE(x) == MI_OPCODE(MI_INSTR(0x22, 0)))
+#define MI_LRI_LEN(x) (((x) & 0xff) + 1)
+#define __valid_oactxctrl_offset(x) ((x) && (x) != U32_MAX)
+static bool __find_reg_in_lri(u32 *state, u32 reg, u32 *offset)
+{
+ u32 idx = *offset;
+ u32 len = MI_LRI_LEN(state[idx]) + idx;
+
+ idx++;
+ for (; idx < len; idx += 2)
+ if (state[idx] == reg)
+ break;
+
+ *offset = idx;
+ return state[idx] == reg;
+}
+
+static u32 __context_image_offset(struct intel_context *ce, u32 reg)
+{
+ u32 offset, len = (ce->engine->context_size - PAGE_SIZE) / 4;
+ u32 *state = ce->lrc_reg_state;
+
+ for (offset = 0; offset < len; ) {
+ if (IS_MI_LRI_CMD(state[offset])) {
+ if (__find_reg_in_lri(state, reg, &offset))
+ break;
+ } else {
+ offset++;
+ }
+ }
+
+ return offset < len ? offset : U32_MAX;
+}
+
+static int __set_oa_ctx_ctrl_offset(struct intel_context *ce)
+{
+ i915_reg_t reg = GEN12_OACTXCONTROL(ce->engine->mmio_base);
+ struct i915_perf *perf = &ce->engine->i915->perf;
+ u32 saved_offset = perf->ctx_oactxctrl_offset;
+ u32 offset;
+
+ /* Do this only once. Failure is stored as offset of U32_MAX */
+ if (saved_offset)
+ return 0;
+
+ offset = __context_image_offset(ce, i915_mmio_reg_offset(reg));
+ perf->ctx_oactxctrl_offset = offset;
+
+ drm_dbg(&ce->engine->i915->drm,
+ "%s oa ctx control at 0x%08x dword offset\n",
+ ce->engine->name, offset);
+
+ return __valid_oactxctrl_offset(offset) ? 0 : -ENODEV;
+}
+
+static bool engine_supports_mi_query(struct intel_engine_cs *engine)
+{
+ return engine->class == RENDER_CLASS;
+}
+
/**
* oa_get_render_ctx_id - determine and hold ctx hw id
* @stream: An i915-perf stream opened for OA metrics
@@ -1382,6 +1443,17 @@ static int oa_get_render_ctx_id(struct i915_perf_stream
*stream)
if (IS_ERR(ce))
return PTR_ERR(ce);
+ if (engine_supports_mi_query(stream->engine)) {
+ ret = __set_oa_ctx_ctrl_offset(ce);
+ if (ret && !(stream->sample_flags & SAMPLE_OA_REPORT)) {
+ intel_context_unpin(ce);
+ drm_err(&stream->perf->i915->drm,
+ "Enabling perf query failed for %s\n",
+ stream->engine->name);
+ return ret;
+ }
+ }
+
switch (GRAPHICS_VER(ce->engine->i915)) {
case 7: {
/*
@@ -2412,10 +2484,11 @@ static int gen12_configure_oar_context(struct
i915_perf_stream *stream,
int err;
struct intel_context *ce = stream->pinned_ctx;
u32 format = stream->oa_buffer.format;
+ u32 offset = stream->perf->ctx_oactxctrl_offset;
struct flex regs_context[] = {
{
GEN8_OACTXCONTROL,
- stream->perf->ctx_oactxctrl_offset + 1,
+ offset + 1,
active ? GEN8_OA_COUNTER_RESUME : 0,
},
};
@@ -2440,15 +2513,18 @@ static int gen12_configure_oar_context(struct
i915_perf_stream *stream,
},
};
- /* Modify the context image of pinned context with regs_context*/
- err = intel_context_lock_pinned(ce);
- if (err)
- return err;
+ /* Modify the context image of pinned context with regs_context */
+ if (__valid_oactxctrl_offset(offset)) {
+ err = intel_context_lock_pinned(ce);
+ if (err)
+ return err;
- err = gen8_modify_context(ce, regs_context, ARRAY_SIZE(regs_context));
- intel_context_unlock_pinned(ce);
- if (err)
- return err;
+ err = gen8_modify_context(ce, regs_context,
+ ARRAY_SIZE(regs_context));
+ intel_context_unlock_pinned(ce);
+ if (err)
+ return err;
+ }
/* Apply regs_lri using LRI with pinned context */
[Intel-gfx] [PATCH 00/19] Add DG2 OA support
Add OA format support for DG2 and various fixes for DG2. The below 2 patches have uapi changes: drm/i915/perf: Add OA formats for DG2 drm/i915/perf: Apply Wa_18013179988 Test-with: 20220822235657.280702-1-umesh.nerlige.rama...@intel.com Signed-off-by: Umesh Nerlige Ramappa Umesh Nerlige Ramappa (18): drm/i915/perf: Fix OA filtering logic for GuC mode drm/i915/perf: Add OA formats for DG2 drm/i915/perf: Fix noa wait predication for DG2 drm/i915/perf: Determine gen12 oa ctx offset at runtime drm/i915/perf: Enable commands per clock reporting in OA drm/i915/perf: Use helpers to process reports w.r.t. OA buffer size drm/i915/perf: Simply use stream->ctx drm/i915/perf: Move gt-specific data from i915->perf to gt->perf drm/i915/perf: Replace gt->perf.lock with stream->lock for file ops drm/i915/perf: Use gt-specific ggtt for OA and noa-wait buffers drm/i915/perf: Store a pointer to oa_format in oa_buffer drm/i915/perf: Parse 64bit report header formats correctly drm/i915/perf: Add Wa_16010703925:dg2 drm/i915/perf: Add Wa_1608133521:dg2 drm/i915/perf: Add Wa_1508761755:dg2 drm/i915/perf: Apply Wa_18013179988 drm/i915/perf: Save/restore EU flex counters across reset drm/i915/perf: Enable OA for DG2 Vinay Belgaumkar (1): drm/i915/guc: Support OA when Wa_16011777198 is enabled drivers/gpu/drm/i915/gt/intel_engine_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 + drivers/gpu/drm/i915/gt/intel_lrc.h | 2 + drivers/gpu/drm/i915/gt/intel_sseu.c | 4 +- .../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h | 9 + drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 8 + drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 45 + drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 2 + drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/i915_getparam.c | 3 + drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_perf.c | 769 ++ drivers/gpu/drm/i915/i915_perf.h | 2 + drivers/gpu/drm/i915/i915_perf_oa_regs.h | 6 +- drivers/gpu/drm/i915/i915_perf_types.h| 53 +- drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/selftests/i915_perf.c| 16 +- include/uapi/drm/i915_drm.h | 12 + 19 files changed, 746 insertions(+), 195 deletions(-) -- 2.25.1
[Intel-gfx] [PATCH 01/19] drm/i915/perf: Fix OA filtering logic for GuC mode
With GuC mode of submission, GuC is in control of defining the context id field
that is part of the OA reports. To filter reports, UMD and KMD must know what sw
context id was chosen by GuC. There is not interface between KMD and GuC to
determine this, so read the upper-dword of EXECLIST_STATUS to filter/squash OA
reports for the specific context.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_lrc.h | 2 +
drivers/gpu/drm/i915/i915_perf.c| 141
2 files changed, 124 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h
b/drivers/gpu/drm/i915/gt/intel_lrc.h
index a390f0813c8b..7111bae759f3 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -110,6 +110,8 @@ enum {
#define XEHP_SW_CTX_ID_WIDTH 16
#define XEHP_SW_COUNTER_SHIFT 58
#define XEHP_SW_COUNTER_WIDTH 6
+#define GEN12_GUC_SW_CTX_ID_SHIFT 39
+#define GEN12_GUC_SW_CTX_ID_WIDTH 16
static inline void lrc_runtime_start(struct intel_context *ce)
{
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index f3c23fe9ad9c..735244a3aedd 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1233,6 +1233,125 @@ static struct intel_context *oa_pin_context(struct
i915_perf_stream *stream)
return stream->pinned_ctx;
}
+static int
+__store_reg_to_mem(struct i915_request *rq, i915_reg_t reg, u32 ggtt_offset)
+{
+ u32 *cs, cmd;
+
+ cmd = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
+ if (GRAPHICS_VER(rq->engine->i915) >= 8)
+ cmd++;
+
+ cs = intel_ring_begin(rq, 4);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ *cs++ = cmd;
+ *cs++ = i915_mmio_reg_offset(reg);
+ *cs++ = ggtt_offset;
+ *cs++ = 0;
+
+ intel_ring_advance(rq, cs);
+
+ return 0;
+}
+
+static int
+__read_reg(struct intel_context *ce, i915_reg_t reg, u32 ggtt_offset)
+{
+ struct i915_request *rq;
+ int err;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ i915_request_get(rq);
+
+ err = __store_reg_to_mem(rq, reg, ggtt_offset);
+
+ i915_request_add(rq);
+ if (!err && i915_request_wait(rq, 0, HZ / 2) < 0)
+ err = -ETIME;
+
+ i915_request_put(rq);
+
+ return err;
+}
+
+static int
+gen12_guc_sw_ctx_id(struct intel_context *ce, u32 *ctx_id)
+{
+ struct i915_vma *scratch;
+ u32 *val;
+ int err;
+
+ scratch =
__vm_create_scratch_for_read_pinned(&ce->engine->gt->ggtt->vm, 4);
+ if (IS_ERR(scratch))
+ return PTR_ERR(scratch);
+
+ err = i915_vma_sync(scratch);
+ if (err)
+ goto err_scratch;
+
+ err = __read_reg(ce, RING_EXECLIST_STATUS_HI(ce->engine->mmio_base),
+i915_ggtt_offset(scratch));
+ if (err)
+ goto err_scratch;
+
+ val = i915_gem_object_pin_map_unlocked(scratch->obj, I915_MAP_WB);
+ if (IS_ERR(val)) {
+ err = PTR_ERR(val);
+ goto err_scratch;
+ }
+
+ *ctx_id = *val;
+ i915_gem_object_unpin_map(scratch->obj);
+
+err_scratch:
+ i915_vma_unpin_and_release(&scratch, 0);
+ return err;
+}
+
+/*
+ * For execlist mode of submission, pick an unused context id
+ * 0 - (NUM_CONTEXT_TAG -1) are used by other contexts
+ * XXX_MAX_CONTEXT_HW_ID is used by idle context
+ *
+ * For GuC mode of submission read context id from the upper dword of the
+ * EXECLIST_STATUS register.
+ */
+static int gen12_get_render_context_id(struct i915_perf_stream *stream)
+{
+ u32 ctx_id, mask;
+ int ret;
+
+ if (intel_engine_uses_guc(stream->engine)) {
+ ret = gen12_guc_sw_ctx_id(stream->pinned_ctx, &ctx_id);
+ if (ret)
+ return ret;
+
+ mask = ((1U << GEN12_GUC_SW_CTX_ID_WIDTH) - 1) <<
+ (GEN12_GUC_SW_CTX_ID_SHIFT - 32);
+ } else if (GRAPHICS_VER_FULL(stream->engine->i915) >= IP_VER(12, 50)) {
+ ctx_id = (XEHP_MAX_CONTEXT_HW_ID - 1) <<
+ (XEHP_SW_CTX_ID_SHIFT - 32);
+
+ mask = ((1U << XEHP_SW_CTX_ID_WIDTH) - 1) <<
+ (XEHP_SW_CTX_ID_SHIFT - 32);
+ } else {
+ ctx_id = (GEN12_MAX_CONTEXT_HW_ID - 1) <<
+(GEN11_SW_CTX_ID_SHIFT - 32);
+
+ mask = ((1U << GEN11_SW_CTX_ID_WIDTH) - 1) <<
+ (GEN11_SW_CTX_ID_SHIFT - 32);
+ }
+ stream->specific_ctx_id = ctx_id & mask;
+ stream->specific_ctx_id_mask = mask;
+
+ return 0;
+}
+
/**
* oa_get_render_ctx_id - determine and hold ctx hw id
* @stream: An i915-perf stream opened for OA metrics
@@ -1246,6 +1365,7 @@ static struct intel_context *oa_pi
[Intel-gfx] [PATCH 02/19] drm/i915/perf: Add OA formats for DG2
Add new OA formats for DG2. Some of the newer OA formats are not
multples of 64 bytes and are not powers of 2. For those formats, adjust
hw_tail accordingly when checking for new reports.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 63
include/uapi/drm/i915_drm.h | 6 +++
2 files changed, 46 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 735244a3aedd..c8331b549d31 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -306,7 +306,8 @@ static u32 i915_oa_max_sample_rate = 10;
/* XXX: beware if future OA HW adds new report formats that the current
* code assumes all reports have a power-of-two size and ~(size - 1) can
- * be used as a mask to align the OA tail pointer.
+ * be used as a mask to align the OA tail pointer. In some of the
+ * formats, R is used to denote reserved field.
*/
static const struct i915_oa_format oa_formats[I915_OA_FORMAT_MAX] = {
[I915_OA_FORMAT_A13]= { 0, 64 },
@@ -320,6 +321,10 @@ static const struct i915_oa_format
oa_formats[I915_OA_FORMAT_MAX] = {
[I915_OA_FORMAT_A12]= { 0, 64 },
[I915_OA_FORMAT_A12_B8_C8] = { 2, 128 },
[I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
+ [I915_OAR_FORMAT_A32u40_A4u32_B8_C8]= { 5, 256 },
+ [I915_OA_FORMAT_A24u40_A14u32_B8_C8]= { 5, 256 },
+ [I915_OAR_FORMAT_A36u64_B8_C8] = { 1, 384 },
+ [I915_OA_FORMAT_A38u64_R2u64_B8_C8] = { 1, 448 },
};
#define SAMPLE_OA_REPORT (1<<0)
@@ -467,6 +472,7 @@ static bool oa_buffer_check_unlocked(struct
i915_perf_stream *stream)
bool pollin;
u32 hw_tail;
u64 now;
+ u32 partial_report_size;
/* We have to consider the (unlikely) possibility that read() errors
* could result in an OA buffer reset which might reset the head and
@@ -476,10 +482,16 @@ static bool oa_buffer_check_unlocked(struct
i915_perf_stream *stream)
hw_tail = stream->perf->ops.oa_hw_tail_read(stream);
- /* The tail pointer increases in 64 byte increments,
-* not in report_size steps...
+ /* The tail pointer increases in 64 byte increments, whereas report
+* sizes need not be integral multiples or 64 or powers of 2.
+* Compute potentially partially landed report in the OA buffer
*/
- hw_tail &= ~(report_size - 1);
+ partial_report_size = OA_TAKEN(hw_tail, stream->oa_buffer.tail);
+ partial_report_size %= report_size;
+
+ /* Subtract partial amount off the tail */
+ hw_tail = gtt_offset + ((hw_tail - partial_report_size) &
+ (stream->oa_buffer.vma->size - 1));
now = ktime_get_mono_fast_ns();
@@ -601,6 +613,8 @@ static int append_oa_sample(struct i915_perf_stream *stream,
{
int report_size = stream->oa_buffer.format_size;
struct drm_i915_perf_record_header header;
+ int report_size_partial;
+ u8 *oa_buf_end;
header.type = DRM_I915_PERF_RECORD_SAMPLE;
header.pad = 0;
@@ -614,7 +628,19 @@ static int append_oa_sample(struct i915_perf_stream
*stream,
return -EFAULT;
buf += sizeof(header);
- if (copy_to_user(buf, report, report_size))
+ oa_buf_end = stream->oa_buffer.vaddr +
+stream->oa_buffer.vma->size;
+ report_size_partial = oa_buf_end - report;
+
+ if (report_size_partial < report_size) {
+ if(copy_to_user(buf, report, report_size_partial))
+ return -EFAULT;
+ buf += report_size_partial;
+
+ if(copy_to_user(buf, stream->oa_buffer.vaddr,
+ report_size - report_size_partial))
+ return -EFAULT;
+ } else if (copy_to_user(buf, report, report_size))
return -EFAULT;
(*offset) += header.size;
@@ -684,8 +710,8 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
* all a power of two).
*/
if (drm_WARN_ONCE(&uncore->i915->drm,
- head > OA_BUFFER_SIZE || head % report_size ||
- tail > OA_BUFFER_SIZE || tail % report_size,
+ head > stream->oa_buffer.vma->size ||
+ tail > stream->oa_buffer.vma->size,
"Inconsistent OA buffer pointers: head = %u, tail =
%u\n",
head, tail))
return -EIO;
@@ -699,22 +725,6 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
u32 ctx_id;
u32 reason;
- /*
-* All the report sizes factor neatly into the buffer
-* size so we never expect to see a report split
-* between the beginning and
Re: [Intel-gfx] [Bug 216388] New: On Host, kernel errors in KVM, on guests, it shows CPU stalls
On 2022.08.22 17:50:33 +, Sean Christopherson wrote: > +GVT folks > > On Sun, Aug 21, 2022, bugzilla-dae...@kernel.org wrote: > > https://bugzilla.kernel.org/show_bug.cgi?id=216388 > > > > Bug ID: 216388 > >Summary: On Host, kernel errors in KVM, on guests, it shows CPU > > stalls > >Product: Virtualization > >Version: unspecified > > Kernel Version: 5.19.0 / 5.19.1 / 5.19.2 > > Hardware: All > > OS: Linux > > Tree: Mainline > > Status: NEW > > Severity: high > > Priority: P1 > > Component: kvm > > Assignee: virtualization_...@kernel-bugs.osdl.org > > Reporter: nan...@eskimo.com > > Regression: No > > > > Created attachment 301614 > > --> https://bugzilla.kernel.org/attachment.cgi?id=301614&action=edit > > The configuration file used to Comile this kernel. > > > > This behavior has persisted across 5.19.0, 5.19.1, and 5.19.2. While the > > kernel I am taking this example from is tainted (owing to using Intel > > development drivers for GPU virtualization), it is also occurring on > > non-tainted kernels on servers with no development or third party modules > > installed. > > > > INFO: task CPU 2/KVM:2343 blocked for more than 1228 seconds. > > [207177.050049] Tainted: G UI 5.19.2 #1 > > [207177.050050] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables > > this message. > > [207177.050051] task:CPU 2/KVM state:D stack:0 pid: 2343 ppid: > > 1 > > flags:0x0002 > > [207177.050054] Call Trace: > > [207177.050055] > > [207177.050056] __schedule+0x359/0x1400 > > [207177.050060] ? kvm_mmu_page_fault+0x1ee/0x980 > > [207177.050062] ? kvm_set_msr_common+0x31f/0x1060 > > [207177.050065] schedule+0x5f/0x100 > > [207177.050066] schedule_preempt_disabled+0x15/0x30 > > [207177.050068] __mutex_lock.constprop.0+0x4e2/0x750 > > [207177.050070] ? aa_file_perm+0x124/0x4f0 > > [207177.050071] __mutex_lock_slowpath+0x13/0x20 > > [207177.050072] mutex_lock+0x25/0x30 > > [207177.050075] intel_vgpu_emulate_mmio_read+0x5d/0x3b0 [kvmgt] > > This isn't a KVM problem, it's a KVMGT problem (despite the name, KVMGT is > very > much not KVM). > > > [207177.050084] intel_vgpu_rw+0xb8/0x1c0 [kvmgt] > > [207177.050091] intel_vgpu_read+0x20d/0x250 [kvmgt] > > [207177.050097] vfio_device_fops_read+0x1f/0x40 > > [207177.050100] vfs_read+0x9b/0x160 > > [207177.050102] __x64_sys_pread64+0x93/0xd0 > > [207177.050104] do_syscall_64+0x58/0x80 > > [207177.050106] ? kvm_on_user_return+0x84/0xe0 > > [207177.050107] ? fire_user_return_notifiers+0x37/0x70 > > [207177.050109] ? exit_to_user_mode_prepare+0x41/0x200 > > [207177.050111] ? syscall_exit_to_user_mode+0x1b/0x40 > > [207177.050112] ? do_syscall_64+0x67/0x80 > > [207177.050114] ? irqentry_exit+0x54/0x70 > > [207177.050115] ? sysvec_call_function_single+0x4b/0xa0 > > [207177.050116] entry_SYSCALL_64_after_hwframe+0x63/0xcd > > [207177.050118] RIP: 0033:0x7ff51131293f > > [207177.050119] RSP: 002b:7ff4ddffa260 EFLAGS: 0293 ORIG_RAX: > > 0011 > > [207177.050121] RAX: ffda RBX: 5599a6835420 RCX: > > 7ff51131293f > > [207177.050122] RDX: 0004 RSI: 7ff4ddffa2a8 RDI: > > 0027 > > [207177.050123] RBP: 0004 R08: R09: > > > > [207177.050124] R10: 00065f10 R11: 0293 R12: > > 00065f10 > > [207177.050124] R13: 5599a6835330 R14: 0004 R15: > > 00065f10 > > [207177.050126] > > > > I am seeing this on Intel i7-6700k, i7-6850k, and i7-9700k platforms. One recent regression fix on Comet Lake is https://patchwork.freedesktop.org/patch/496987/, it's on the way to 6.0-rc and would be pushed to 5.19 stable as well. But looks this report impacts on more platforms? We'll double check. Thanks > > > > This did not happen on 5.17 kernels, and 5.18 kernels never ran stable > > enough on my platforms to actually run them for more than a few minutes. > > > > Likewise 6.0-rc1 has not been stable enough to run in production. > > After > > less than three hours running on my workstation it locked hard with even the > > magic sys-request key being unresponsive and only power cycling the machine > > got > > it back. > > > > The operating system in use for the host on all machines is Ubuntu > > 22.04. > > > > Guests vary with Ubuntu 22.04 being the most common but also Mint, > > Debian, > > Manjaro, Centos, Fedora, ScientificLinux, Zorin, and Windows being in use. > > > > I see the same issue manifest on platforms running only Ubuntu guests > > as > > with guests of varying operating systems. > > > > The configuration file I used to compile this kernel is attached. I > > compiled it with gcc 12.1.0. > > > > This behavior does not manifest its
[Intel-gfx] ✗ Fi.CI.IGT: failure for Add DP MST DSC support to i915 (rev7)
== Series Details == Series: Add DP MST DSC support to i915 (rev7) URL : https://patchwork.freedesktop.org/series/101492/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12009_full -> Patchwork_101492v7_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_101492v7_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_101492v7_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (13 -> 13) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_101492v7_full: ### IGT changes ### Possible regressions * igt@i915_module_load@reload-with-fault-injection: - shard-snb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb4/igt@i915_module_l...@reload-with-fault-injection.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v7/shard-snb4/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_suspend@basic-s3-without-i915: - shard-iclb: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-iclb5/igt@i915_susp...@basic-s3-without-i915.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v7/shard-iclb2/igt@i915_susp...@basic-s3-without-i915.html Known issues Here are the changes found in Patchwork_101492v7_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@parallel-contexts: - shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-iclb4/igt@gem_exec_balan...@parallel-contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v7/shard-iclb5/igt@gem_exec_balan...@parallel-contexts.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-glk5/igt@gem_exec_fair@basic-none-r...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v7/shard-glk8/igt@gem_exec_fair@basic-none-r...@rcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-apl: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-apl6/igt@gem_exec_fair@basic-none-s...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v7/shard-apl4/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_lmem_swapping@random-engines: - shard-kbl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v7/shard-kbl7/igt@gem_lmem_swapp...@random-engines.html * igt@i915_suspend@debugfs-reader: - shard-kbl: [PASS][12] -> [DMESG-WARN][13] ([i915#180]) +4 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-kbl4/igt@i915_susp...@debugfs-reader.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v7/shard-kbl4/igt@i915_susp...@debugfs-reader.html * igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc: - shard-kbl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#3886]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v7/shard-kbl7/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html * igt@kms_chamelium@hdmi-crc-single: - shard-kbl: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v7/shard-kbl7/igt@kms_chamel...@hdmi-crc-single.html * igt@kms_flip@plain-flip-ts-check@c-hdmi-a1: - shard-glk: [PASS][16] -> [FAIL][17] ([i915#2122]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-glk7/igt@kms_flip@plain-flip-ts-ch...@c-hdmi-a1.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v7/shard-glk9/igt@kms_flip@plain-flip-ts-ch...@c-hdmi-a1.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-default-mode: - shard-iclb: NOTRUN -> [SKIP][18] ([i915#2672] / [i915#3555]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v7/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscal...@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode: - shard-iclb: NOTRUN -> [SKIP][19] ([i915#2672]) [19]: h
Re: [Intel-gfx] [PATCH v1] drm/i915: fix null pointer dereference
On Tue, Feb 01, 2022 at 04:33:54PM +0100, Lukasz Bartosik wrote:
> From: Łukasz Bartosik
>
> Asus chromebook CX550 crashes during boot on v5.17-rc1 kernel.
> The root cause is null pointer defeference of bi_next
> in tgl_get_bw_info() in drivers/gpu/drm/i915/display/intel_bw.c.
>
> BUG: kernel NULL pointer dereference, address: 002e
> PGD 0 P4D 0
> Oops: 0002 [#1] PREEMPT SMP NOPTI
> CPU: 0 PID: 1 Comm: swapper/0 Tainted: G U5.17.0-rc1
> Hardware name: Google Delbin/Delbin, BIOS Google_Delbin.13672.156.3 05/14/2021
> RIP: 0010:tgl_get_bw_info+0x2de/0x510
> ...
> [2.554467] Call Trace:
> [2.554467]
> [2.554467] intel_bw_init_hw+0x14a/0x434
> [2.554467] ? _printk+0x59/0x73
> [2.554467] ? _dev_err+0x77/0x91
> [2.554467] i915_driver_hw_probe+0x329/0x33e
> [2.554467] i915_driver_probe+0x4c8/0x638
> [2.554467] i915_pci_probe+0xf8/0x14e
> [2.554467] ? _raw_spin_unlock_irqrestore+0x12/0x2c
> [2.554467] pci_device_probe+0xaa/0x142
> [2.554467] really_probe+0x13f/0x2f4
> [2.554467] __driver_probe_device+0x9e/0xd3
> [2.554467] driver_probe_device+0x24/0x7c
> [2.554467] __driver_attach+0xba/0xcf
> [2.554467] ? driver_attach+0x1f/0x1f
> [2.554467] bus_for_each_dev+0x8c/0xc0
> [2.554467] bus_add_driver+0x11b/0x1f7
> [2.554467] driver_register+0x60/0xea
> [2.554467] ? mipi_dsi_bus_init+0x16/0x16
> [2.554467] i915_init+0x2c/0xb9
> [2.554467] ? mipi_dsi_bus_init+0x16/0x16
> [2.554467] do_one_initcall+0x12e/0x2b3
> [2.554467] do_initcall_level+0xd6/0xf3
> [2.554467] do_initcalls+0x4e/0x79
> [2.554467] kernel_init_freeable+0xed/0x14d
> [2.554467] ? rest_init+0xc1/0xc1
> [2.554467] kernel_init+0x1a/0x120
> [2.554467] ret_from_fork+0x1f/0x30
> [2.554467]
> ...
> Kernel panic - not syncing: Fatal exception
>
> Fixes: c64a9a7c05be ("drm/i915: Update memory bandwidth formulae")
> Signed-off-by: Łukasz Bartosik
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 16 +---
> 1 file changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 2da4aacc956b..bd0ed68b7faa 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -404,15 +404,17 @@ static int tgl_get_bw_info(struct drm_i915_private
> *dev_priv, const struct intel
> int clpchgroup;
> int j;
>
> - if (i < num_groups - 1)
> - bi_next = &dev_priv->max_bw[i + 1];
> -
> clpchgroup = (sa->deburst * qi.deinterleave / num_channels) <<
> i;
>
> - if (i < num_groups - 1 && clpchgroup < clperchgroup)
> - bi_next->num_planes = (ipqdepth - clpchgroup) /
> clpchgroup + 1;
> - else
> - bi_next->num_planes = 0;
> + if (i < num_groups - 1) {
> + bi_next = &dev_priv->max_bw[i + 1];
> +
> + if (clpchgroup < clperchgroup)
> + bi_next->num_planes = (ipqdepth - clpchgroup) /
> +clpchgroup + 1;
> + else
> + bi_next->num_planes = 0;
> + }
>
> bi->num_qgv_points = qi.num_points;
> bi->num_psf_gv_points = qi.num_psf_points;
(Some email path may be clogged; Nathan Chancellor has also sent email,
but I wanted to comment too.)
This patch solves https://github.com/ClangBuiltLinux/linux/issues/1626
And it's actually fixing a wild write as well: for folks where
"i < num_groups - 1" is false and they don't get "lucky" with a NULL
deref, this is writing to some address left over on the stack. :|
-Kees
--
Kees Cook
Re: [Intel-gfx] [PATCH v7 1/8] overflow: Move and add few utility macros into overflow
On Tue, Aug 23, 2022 at 04:32:10AM +0900, Gwan-gyeong Mun wrote:
> On 8/22/22 11:05 PM, Andrzej Hajda wrote:
> > On 18.08.2022 02:12, Kees Cook wrote:
> > > On Thu, Aug 18, 2022 at 01:07:29AM +0200, Andi Shyti wrote:
> > > > [...]
> > > > > +#define safe_conversion(ptr, value) ({ \
> > > > > + typeof(value) __v = (value); \
> > > > > + typeof(ptr) __ptr = (ptr); \
> > > > > + overflows_type(__v, *__ptr) ? 0 : ((*__ptr =
> > > > > (typeof(*__ptr))__v), 1); \
> > > > > +})
> > >
> > > I try to avoid "safe" as an adjective for interface names, since it
> > > doesn't really answer "safe from what?" This looks more like "assign, but
> > > zero when out of bounds". And it can be built from existing macros here:
> > >
> > > if (check_add_overflow(0, value, ptr))
> > > *ptr = 0;
> > >
> > > I actually want to push back on this a bit, because there can still be
> > > logic bugs built around this kind of primitive. Shouldn't out-of-bounds
> > > assignments be seen as a direct failure? I would think this would be
> > > sufficient:
> > >
> > > #define check_assign(value, ptr) check_add_overflow(0, value, ptr)
> > >
> > > And callers would do:
> > >
> > > if (check_assign(value, &var))
> > > return -EINVAL;
> > >
> Yes, I also like check_assign() you suggested more than safe_conversion.
> As shown below, it would be more readable to return true when assign
> succeeds and false when it fails. What do you think?
No, this inverts the style of all the other check_*() functions, so it
should remain "non-zero is failure".
> /**
> * check_assign - perform a type conversion (cast) of an source value into
> * a new variable, checking that the destination is large enough to hold the
> * source value.
> *
> * @value: Source value
> * @ptr: Destination pointer address, If the pointer type is not used, a
> warning message is output during build.
> *
> * Returns:
> * If the value would overflow the destination, it returns false. If not
> return true.
> */
> #define check_assign(value, ptr) __must_check_overflow(({ \
> typecheck_pointer(ptr); \
> !__builtin_add_overflow(0, value, ptr); \
> }))
Please don't use the __builtin*s, instead stick to the check_* family,
as they correctly wrap the builtins and perform type checking, etc. As
mentioned, check_assign() should just be:
#define check_assign(value, ptr) check_add_overflow(0, value, ptr)
I don't think any of the other code is needed? What's the use-case for
the other stuff? i.e. Why does anything need overflows_type()?
-Kees
--
Kees Cook
[Intel-gfx] ✓ Fi.CI.BAT: success for Enable Pipewriteback Framework
== Series Details ==
Series: Enable Pipewriteback Framework
URL : https://patchwork.freedesktop.org/series/107573/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12012 -> Patchwork_107573v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107573v1/index.html
Participating hosts (36 -> 37)
--
Additional (2): bat-dg2-10 fi-tgl-dsi
Missing(1): fi-cfl-8700k
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_107573v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@core_hotunplug@unbind-rebind:
- {bat-dg2-10}: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107573v1/bat-dg2-10/igt@core_hotunp...@unbind-rebind.html
Known issues
Here are the changes found in Patchwork_107573v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258: [PASS][2] -> [INCOMPLETE][3] ([i915#3303] /
[i915#4785])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12012/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107573v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][4] -> [DMESG-FAIL][5] ([i915#4528])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12012/fi-pnv-d510/igt@i915_selftest@l...@requests.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107573v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html
*
igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka: [PASS][6] -> [FAIL][7] ([i915#6298])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12012/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107573v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
* igt@runner@aborted:
- fi-hsw-g3258: NOTRUN -> [FAIL][8] ([fdo#109271] / [i915#4312] /
[i915#6246])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107573v1/fi-hsw-g3258/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gt_lrc:
- {bat-dg2-8}:[INCOMPLETE][9] ([i915#6580]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12012/bat-dg2-8/igt@i915_selftest@live@gt_lrc.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107573v1/bat-dg2-8/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][11] ([i915#4494] / [i915#4957]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12012/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107573v1/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- {bat-rpls-1}: [INCOMPLETE][13] ([i915#6380]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12012/bat-rpls-1/igt@i915_selftest@l...@requests.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107573v1/bat-rpls-1/igt@i915_selftest@l...@requests.html
Warnings
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [DMESG-FAIL][15] ([i915#4957]) -> [DMESG-FAIL][16]
([i915#4494] / [i915#4957])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12012/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107573v1/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-glk-j4005: [INCOMPLETE][17] -> [INCOMPLETE][18] ([i915#6598])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12012/fi-glk-j4005/igt@i915_susp...@basic-s3-without-i915.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107573v1/fi-glk-j4005/igt@i915_susp...@basic-s3-without-i915.html
- fi-elk-e7500: [INCOMPLETE][19] ([i915#6598] / [i915#6601] /
[i915#6648]) -> [INCOMPLETE][20] ([i915#6648])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12012/fi-elk-e7500/igt@i915_susp...@basic-s3-without-i915.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107573v1/fi-elk-e7500/igt@i915_susp...@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cg
Re: [Intel-gfx] [PATCH v7 1/8] overflow: Move and add few utility macros into overflow
On 8/22/22 11:05 PM, Andrzej Hajda wrote:
On 18.08.2022 02:12, Kees Cook wrote:
On Thu, Aug 18, 2022 at 01:07:29AM +0200, Andi Shyti wrote:
Hi Kees,
would you mind taking a look at this patch?
Hi! Thanks for the heads-up!
Thanks,
Andi
On Tue, Aug 16, 2022 at 06:35:18PM +0900, Gwan-gyeong Mun wrote:
It moves overflows_type utility macro into overflow header from
i915_utils
header. The overflows_type can be used to catch the truncation
between data
types. And it adds safe_conversion() macro which performs a type
conversion
(cast) of an source value into a new variable, checking that the
destination is large enough to hold the source value. And the
functionality
of overflows_type has been improved to handle the signbit.
The is_unsigned_type macro has been added to check the sign bit of the
built-in type.
v3: Add is_type_unsigned() macro (Mauro)
Modify overflows_type() macro to consider signed data types
(Mauro)
Fix the problem that safe_conversion() macro always returns true
v4: Fix kernel-doc markups
v6: Move macro addition location so that it can be used by other
than drm
subsystem (Jani, Mauro, Andi)
Change is_type_unsigned to is_unsigned_type to have the same
name form
as is_signed_type macro
Signed-off-by: Gwan-gyeong Mun
Cc: Thomas Hellström
Cc: Matthew Auld
Cc: Nirmoy Das
Cc: Jani Nikula
Cc: Andi Shyti
Reviewed-by: Mauro Carvalho Chehab (v5)
---
drivers/gpu/drm/i915/i915_utils.h | 5 +--
include/linux/overflow.h | 54
+++
2 files changed, 55 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_utils.h
b/drivers/gpu/drm/i915/i915_utils.h
index c10d68cdc3ca..eb0ded23fa9c 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -32,6 +32,7 @@
#include
#include
#include
+#include
#ifdef CONFIG_X86
#include
@@ -111,10 +112,6 @@ bool i915_error_injected(void);
#define range_overflows_end_t(type, start, size, max) \
range_overflows_end((type)(start), (type)(size), (type)(max))
-/* Note we don't consider signbits :| */
-#define overflows_type(x, T) \
- (sizeof(x) > sizeof(T) && (x) >> BITS_PER_TYPE(T))
-
#define ptr_mask_bits(ptr, n) ({ \
unsigned long __v = (unsigned long)(ptr); \
(typeof(ptr))(__v & -BIT(n)); \
diff --git a/include/linux/overflow.h b/include/linux/overflow.h
index f1221d11f8e5..462a03454377 100644
--- a/include/linux/overflow.h
+++ b/include/linux/overflow.h
@@ -35,6 +35,60 @@
#define type_max(T) ((T)((__type_half_max(T) - 1) +
__type_half_max(T)))
#define type_min(T) ((T)((T)-type_max(T)-(T)1))
+/**
+ * is_unsigned_type - helper for checking data type which is an
unsigned data
+ * type or not
+ * @x: The data type to check
+ *
+ * Returns:
+ * True if the data type is an unsigned data type, false otherwise.
+ */
+#define is_unsigned_type(x) ((typeof(x))-1 >= (typeof(x))0)
I'd rather not have separate logic for this. Instead, I'd like it to be:
#define is_unsigned_type(x) (!is_signed_type(x))
+
+/**
+ * overflows_type - helper for checking the truncation between data
types
+ * @x: Source for overflow type comparison
+ * @T: Destination for overflow type comparison
+ *
+ * It compares the values and size of each data type between the
first and
+ * second argument to check whether truncation can occur when
assigning the
+ * first argument to the variable of the second argument.
+ * Source and Destination can be used with or without sign bit.
+ * Composite data structures such as union and structure are not
considered.
+ * Enum data types are not considered.
+ * Floating point data types are not considered.
+ *
+ * Returns:
+ * True if truncation can occur, false otherwise.
+ */
+#define overflows_type(x, T) \
+ (is_unsigned_type(x) ? \
+ is_unsigned_type(T) ? \
+ (sizeof(x) > sizeof(T) && (x) >> BITS_PER_TYPE(T)) ? 1
: 0 \
+ : (sizeof(x) >= sizeof(T) && (x) >> (BITS_PER_TYPE(T) -
1)) ? 1 : 0 \
+ : is_unsigned_type(T) ? \
+ ((x) < 0) ? 1 : (sizeof(x) > sizeof(T) && (x) >>
BITS_PER_TYPE(T)) ? 1 : 0 \
+ : (sizeof(x) > sizeof(T)) ? \
+ ((x) < 0) ? (((x) * -1) >> BITS_PER_TYPE(T)) ? 1 : 0 \
+ : ((x) >> BITS_PER_TYPE(T)) ? 1 : 0 \
+ : 0)
Like the other, I'd much rather this was rephrased in terms of the
existing macros (e.g. type_min()/type_max().)
Thanks for all of your comments.
The version that implements overflows_type() using type_min() and
type_max() includes modifications to the following macros.
In implementations of is_signed_type(), __type_half_max(), type_max(),
type_min(), where types are used as variables, the addition of typeof()
is necessary.
And the operation was confirmed through previously shared test cases.
https://patchwork.freedesktop.org/patch/492374/?series=104704&rev=3
#define is_signed_type(x) (((typeof(x))(
[Intel-gfx] [PATCH 1/3] drm/i915: Define WD trancoder for i915
From: Suraj Kandpal
Adding WD Types, WD transcoder to enum list and WD Transcoder offsets.
Adding i915 register definitions related to WD transcoder
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_display.h | 6 +
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/i915_reg.h | 139 ++
3 files changed, 146 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index fa5371036239..4e9f22954a41 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -120,6 +120,8 @@ enum transcoder {
TRANSCODER_DSI_1,
TRANSCODER_DSI_A = TRANSCODER_DSI_0,/* legacy DSI */
TRANSCODER_DSI_C = TRANSCODER_DSI_1,/* legacy DSI */
+ TRANSCODER_WD_0,
+ TRANSCODER_WD_1,
I915_MAX_TRANSCODERS
};
@@ -141,6 +143,10 @@ static inline const char *transcoder_name(enum transcoder
transcoder)
return "DSI A";
case TRANSCODER_DSI_C:
return "DSI C";
+ case TRANSCODER_WD_0:
+ return "WD 0";
+ case TRANSCODER_WD_1:
+ return "WD 1";
default:
return "";
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0da9b208d56e..0e94bd430bcb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -79,6 +79,7 @@ enum intel_output_type {
INTEL_OUTPUT_DSI = 9,
INTEL_OUTPUT_DDI = 10,
INTEL_OUTPUT_DP_MST = 11,
+ INTEL_OUTPUT_WD = 12,
};
enum hdmi_force_audio {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf5c39d9f953..e3fced4b9980 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2059,6 +2059,8 @@
#define TRANSCODER_EDP_OFFSET 0x6f000
#define TRANSCODER_DSI0_OFFSET 0x6b000
#define TRANSCODER_DSI1_OFFSET 0x6b800
+#define TRANSCODER_WD0_OFFSET 0x6e000
+#define TRANSCODER_WD1_OFFSET 0x6e800
#define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
#define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
@@ -3831,6 +3833,11 @@
#define PIPE_DSI0_OFFSET 0x7b000
#define PIPE_DSI1_OFFSET 0x7b800
+/* WD 0 and 1 */
+#define PIPE_WD0_OFFSET0x7e000
+#define PIPE_WD1_OFFSET0x7d000
+
+
#define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
#define PIPEFRAME(pipe)_MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
@@ -4495,6 +4502,10 @@
#define _PIPEDSI0CONF 0x7b008
#define _PIPEDSI1CONF 0x7b808
+/* WD 0 and 1 */
+#define _PIPEWD0CONF 0x7e008
+#define _PIPEWD1CONF 0x7d008
+
/* Sprite A control */
#define _DVSACNTR 0x72180
#define DVS_ENABLE REG_BIT(31)
@@ -5720,6 +5731,7 @@
#define GEN8_DE_MISC_IER _MMIO(0x4446c)
#define GEN8_DE_MISC_GSE (1 << 27)
#define GEN8_DE_EDP_PSR (1 << 19)
+#define GEN8_DE_MISC_WD0 (1 << 23)
#define GEN8_PCU_ISR _MMIO(0x444e0)
#define GEN8_PCU_IMR _MMIO(0x444e4)
@@ -8714,6 +8726,133 @@ enum skl_power_gate {
#define DSB_ENABLE (1 << 31)
#define DSB_STATUS (1 << 0)
+#define TGL_ROOT_DEVICE_ID 0x9A00
+#define TGL_ROOT_DEVICE_MASK 0xFF00
+#define TGL_ROOT_DEVICE_SKU_MASK 0xF
+#define TGL_ROOT_DEVICE_SKU_ULX0x2
+#define TGL_ROOT_DEVICE_SKU_ULT0x4
+
+/* Gen12 WD */
+#define _MMIO_WD(tc, wd0, wd1) _MMIO_TRANS((tc) - TRANSCODER_WD_0, \
+ wd0, wd1)
+
+#define WD_TRANS_ENABLE(1 << 31)
+#define WD_TRANS_DISABLE 0
+#define WD_TRANS_ACTIVE(1 << 30)
+
+/* WD transcoder control */
+#define _WD_TRANS_FUNC_CTL_0 0x6e400
+#define _WD_TRANS_FUNC_CTL_1 0x6ec00
+#define WD_TRANS_FUNC_CTL(tc) _MMIO_WD(tc,\
+ _WD_TRANS_FUNC_CTL_0,\
+ _WD_TRANS_FUNC_CTL_1)
+
+#define TRANS_WD_FUNC_ENABLE (1 << 31)
+#define WD_TRIGGERED_CAP_MODE_ENABLE (1 << 30)
+#define START_TRIGGER_FRAME(1 << 29)
+#define STOP_TRIGGER_FRAME (1 << 28)
+#define WD_CTL_POINTER_ETEH(0 << 18)
+#define WD_CTL_POINTER_ETDH(1 << 18)
+#define WD_CTL_POINTER_DTDH(2 << 18)
+#define WD_INPUT_SELECT_MASK (7 << 12)
+#define WD_INPUT_PIPE_A(0 << 12)
+#define WD_INPUT_PIPE_B(5 << 12)
+#define WD_INPUT_PIPE_C(6 << 12)
+#define WD_INPUT_PIPE_D(7 << 12)
+
+#def
[Intel-gfx] [PATCH 3/3] drm/i915: Enabling WD Transcoder
From: Suraj Kandpal
Adding support for writeback transcoder to start capturing frames using
interrupt mechanism
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_acpi.c | 1 +
drivers/gpu/drm/i915/display/intel_crtc.c | 6 +
.../drm/i915/display/intel_crtc_state_dump.c | 1 +
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +
drivers/gpu/drm/i915/display/intel_display.c | 65 +-
drivers/gpu/drm/i915/display/intel_display.h | 5 +
.../drm/i915/display/intel_display_debugfs.c | 13 +-
.../drm/i915/display/intel_display_types.h| 6 +
drivers/gpu/drm/i915/display/intel_dpll.c | 6 +
.../drm/i915/display/intel_modeset_setup.c| 103 ++-
.../drm/i915/display/intel_modeset_verify.c | 17 +-
drivers/gpu/drm/i915/display/intel_opregion.c | 3 +
.../gpu/drm/i915/display/intel_wb_connector.h | 20 +
drivers/gpu/drm/i915/display/intel_wd.c | 699 ++
drivers/gpu/drm/i915/display/intel_wd.h | 48 ++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 8 +-
drivers/gpu/drm/i915/i915_pci.c | 7 +-
19 files changed, 970 insertions(+), 46 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_wb_connector.h
create mode 100644 drivers/gpu/drm/i915/display/intel_wd.c
create mode 100644 drivers/gpu/drm/i915/display/intel_wd.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 522ef9b4aff3..ec63ed16c250 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -302,6 +302,7 @@ i915-y += \
display/intel_tv.o \
display/intel_vdsc.o \
display/intel_vrr.o \
+ display/intel_wd.o \
display/vlv_dsi.o \
display/vlv_dsi_pll.o
diff --git a/drivers/gpu/drm/i915/display/intel_acpi.c
b/drivers/gpu/drm/i915/display/intel_acpi.c
index e78430001f07..ae08db164f73 100644
--- a/drivers/gpu/drm/i915/display/intel_acpi.c
+++ b/drivers/gpu/drm/i915/display/intel_acpi.c
@@ -247,6 +247,7 @@ static u32 acpi_display_type(struct intel_connector
*connector)
case DRM_MODE_CONNECTOR_LVDS:
case DRM_MODE_CONNECTOR_eDP:
case DRM_MODE_CONNECTOR_DSI:
+ case DRM_MODE_CONNECTOR_WRITEBACK:
display_type = ACPI_DISPLAY_TYPE_INTERNAL_DIGITAL;
break;
case DRM_MODE_CONNECTOR_Unknown:
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
b/drivers/gpu/drm/i915/display/intel_crtc.c
index 6792a9056f46..66d552758720 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -491,6 +491,9 @@ void intel_pipe_update_start(struct intel_crtc_state
*new_crtc_state)
if (new_crtc_state->do_async_flip)
return;
+ if (new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD))
+ return;
+
if (intel_crtc_needs_vblank_work(new_crtc_state))
intel_crtc_vblank_work_init(new_crtc_state);
@@ -638,6 +641,9 @@ void intel_pipe_update_end(struct intel_crtc_state
*new_crtc_state)
if (new_crtc_state->do_async_flip)
return;
+ if (new_crtc_state->output_types & BIT(INTEL_OUTPUT_WD))
+ return;
+
trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
/*
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index e9212f69c360..8435065f3b7d 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -71,6 +71,7 @@ static const char * const output_type_str[] = {
OUTPUT_TYPE(DSI),
OUTPUT_TYPE(DDI),
OUTPUT_TYPE(DP_MST),
+ OUTPUT_TYPE(WD),
};
#undef OUTPUT_TYPE
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index a4c8493f3ce7..1360406ca531 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1974,6 +1974,12 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct
intel_encoder *encoder)
*/
if (encoder->type == INTEL_OUTPUT_DP_MST)
return;
+ /*
+* WD transcoder is a virtual encoder hence sanization
+* is not required for it
+*/
+ if (encoder->type == INTEL_OUTPUT_WD)
+ return;
if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
u8 pipe_mask;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f143adefdf38..52fb23846856 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -115,6 +115,7 @@
#include "intel_sprite.h"
#include "intel_tc.h"
#include "intel_vga.h"
+#include "intel_wd.h"
#include "i9xx_plane.h"
#include "skl
[Intel-gfx] [PATCH 2/3] drm/i915 : Changing intel_connector iterators
From: Suraj Kandpal
Changing intel_connector iterators as with writeback introduction
not all drm_connector will be embedded within intel_connector.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_display.h | 7 ++---
.../drm/i915/display/intel_display_types.h| 26 ++-
.../drm/i915/display/intel_modeset_setup.c| 16 +---
3 files changed, 40 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 4e9f22954a41..3b9987b5f304 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -52,6 +52,7 @@ struct intel_crtc_state;
struct intel_digital_port;
struct intel_dp;
struct intel_encoder;
+struct intel_connector;
struct intel_initial_plane_config;
struct intel_load_detect_pipe;
struct intel_plane;
@@ -469,16 +470,12 @@ enum hpd_pin {
for_each_if(intel_encoder_can_psr(intel_encoder))
#define for_each_intel_connector_iter(intel_connector, iter) \
- while ((intel_connector =
to_intel_connector(drm_connector_list_iter_next(iter
+ while ((intel_connector = intel_connector_list_iter_next(iter)))
#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list,
base.head) \
for_each_if((intel_encoder)->base.crtc == (__crtc))
-#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
- list_for_each_entry((intel_connector),
&(dev)->mode_config.connector_list, base.head) \
- for_each_if((intel_connector)->base.encoder == (__encoder))
-
#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state,
__i) \
for ((__i) = 0; \
(__i) < (__state)->base.dev->mode_config.num_total_plane && \
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0e94bd430bcb..7a82b7acbaf2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1497,12 +1497,14 @@ struct cxsr_latency {
#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state,
base)
#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
-#define to_intel_connector(x) container_of(x, struct intel_connector, base)
+#define to_intel_wb_connector(x) container_of(x, struct intel_wb_connector,
base)
#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
#define to_intel_plane(x) container_of(x, struct intel_plane, base)
#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
#define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
+#define to_intel_connector(x) (((x->connector_type ==
DRM_MODE_CONNECTOR_WRITEBACK)) ? \
+ NULL : container_of(x, struct intel_connector,
base))
struct intel_hdmi {
i915_reg_t hdmi_reg;
@@ -2068,4 +2070,26 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
}
+static inline struct intel_connector *
+intel_connector_list_iter_next(struct drm_connector_list_iter *iter)
+{
+ struct drm_connector *connector;
+ bool flag = true;
+ /*
+* Skipping connector that are Writeback connector as they will
+* not be embedded in intel connector
+*/
+ while (flag) {
+ connector = drm_connector_list_iter_next(iter);
+ if (connector && !to_intel_connector(connector))
+ continue;
+
+ flag = false;
+
+ if (connector)
+ return to_intel_connector(connector);
+
+ }
+ return NULL;
+}
#endif /* __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index f0e04d3904c6..985dfa5f7aa1 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -204,12 +204,22 @@ static bool intel_crtc_has_encoders(struct intel_crtc
*crtc)
static struct intel_connector *intel_encoder_find_connector(struct
intel_encoder *encoder)
{
- struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_connector *connector;
+ struct drm_connector_list_iter conn_iter;
+ bool found_connector = false;
- for_each_connector_on_encoder(dev, &encoder->base, connector)
- return connector;
+ drm_connector_list_iter_begin(&i915->drm, &conn_iter);
+ for_each_intel_connector_iter(connector, &conn_iter
[Intel-gfx] [PATCH 0/3] Enable Pipewriteback Framework
A patch series was floated in the drm mailing list which aimed to change the drm_connector and drm_encoder fields to pointer in the drm_connector_writeback structure, this received a huge pushback from the community but since i915 expects each connector present in the drm_device list to be a intel_connector but drm_writeback framework makes us have a connector which cannot be embedded in an intel_connector structure. [1] https://patchwork.kernel.org/project/dri-devel/patch/20220202081702.22119-1-suraj.kand...@intel.com/ [2] https://patchwork.kernel.org/project/dri-devel/patch/20220202085429.22261-6-suraj.kand...@intel.com/ Since no one had an issue with encoder field being changed into a pointer it was decided to break the connector and encoder pointer changes into two different series.The encoder field changes is currently being worked upon by Abhinav Kumar and the changes have been merged. [3]https://patchwork.kernel.org/project/dri-devel/list/?series=633565 Going forward we use a drm_connector which is not embedded in intel_connector. We also create a intel_encoder to avoid changes to many iterators but no intel_connector. We also changed all iterators that go through connectors and add a check to only cast connectors which are not writeback connectors. I had also floated a previous series to Enable writeback but floating a new one as i created an extra patch in this series as suggested by Jani, Nikula for intel_connector iterator changes. Please go check the below link if interested. [4]https://patchwork.freedesktop.org/series/106902/ Suraj Kandpal (3): drm/i915: Define WD trancoder for i915 drm/i915 : Changing intel_connector iterators drm/i915: Enabling WD Transcoder drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_acpi.c | 1 + drivers/gpu/drm/i915/display/intel_crtc.c | 6 + .../drm/i915/display/intel_crtc_state_dump.c | 1 + drivers/gpu/drm/i915/display/intel_ddi.c | 6 + drivers/gpu/drm/i915/display/intel_display.c | 65 +- drivers/gpu/drm/i915/display/intel_display.h | 18 +- .../drm/i915/display/intel_display_debugfs.c | 13 +- .../drm/i915/display/intel_display_types.h| 33 +- drivers/gpu/drm/i915/display/intel_dpll.c | 6 + .../drm/i915/display/intel_modeset_setup.c| 119 ++- .../drm/i915/display/intel_modeset_verify.c | 17 +- drivers/gpu/drm/i915/display/intel_opregion.c | 3 + .../gpu/drm/i915/display/intel_wb_connector.h | 20 + drivers/gpu/drm/i915/display/intel_wd.c | 699 ++ drivers/gpu/drm/i915/display/intel_wd.h | 48 ++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_irq.c | 8 +- drivers/gpu/drm/i915/i915_pci.c | 7 +- drivers/gpu/drm/i915/i915_reg.h | 139 20 files changed, 1156 insertions(+), 55 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_wb_connector.h create mode 100644 drivers/gpu/drm/i915/display/intel_wd.c create mode 100644 drivers/gpu/drm/i915/display/intel_wd.h -- 2.25.1
Re: [Intel-gfx] [PULL] gvt-fixes (resend)
On Mon, Aug 22, 2022 at 11:12:15AM +0800, Zhenyu Wang wrote: > > (resend after fixing sign-off after rebase) > > Hi, > > Here's one gvt-fixes pull for 6.0-rc. Major one is Cometlake > regression fix for mmio table rework, and others are left kernel doc > fixes not pushed yet. Pulled, thanks! > > Thanks! > -- > The following changes since commit a7a47a5dfa9a9692a41764ee9ab4054f12924a42: > > drm/i915/reset: Add additional steps for Wa_22011802037 for execlist > backend (2022-07-25 15:57:54 +0100) > > are available in the Git repository at: > > https://github.com/intel/gvt-linux tags/gvt-fixes-2022-08-22 > > for you to fetch changes up to b75ef35bb57791a5d675699ed4a40c870d1da12f: > > drm/i915/gvt: Fix Comet Lake (2022-08-22 11:33:12 +0800) > > > gvt-fixes-2022-08-22 > > - CometLake regression fix in mmio table rework (Alex) > - misc kernel doc and typo fixes > > > Alex Williamson (1): > drm/i915/gvt: Fix Comet Lake > > Colin Ian King (1): > drm/i915/reg: Fix spelling mistake "Unsupport" -> "Unsupported" > > Jiapeng Chong (3): > drm/i915/gvt: Fix kernel-doc > drm/i915/gvt: Fix kernel-doc > drm/i915/gvt: Fix kernel-doc > > Julia Lawall (1): > drm/i915/gvt: fix typo in comment > > drivers/gpu/drm/i915/gvt/aperture_gm.c | 4 ++-- > drivers/gpu/drm/i915/gvt/gtt.c | 2 +- > drivers/gpu/drm/i915/gvt/handlers.c | 4 ++-- > drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +- > drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 3 ++- > 5 files changed, 8 insertions(+), 7 deletions(-) >
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc/slpc: Allow SLPC to use efficient frequency (rev5)
== Series Details ==
Series: drm/i915/guc/slpc: Allow SLPC to use efficient frequency (rev5)
URL : https://patchwork.freedesktop.org/series/107101/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12011 -> Patchwork_107101v5
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_107101v5 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_107101v5, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107101v5/index.html
Participating hosts (37 -> 37)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_107101v5:
### IGT changes ###
Warnings
* igt@i915_suspend@basic-s3-without-i915:
- fi-kbl-7567u: [INCOMPLETE][1] ([i915#6598]) -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12011/fi-kbl-7567u/igt@i915_susp...@basic-s3-without-i915.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107101v5/fi-kbl-7567u/igt@i915_susp...@basic-s3-without-i915.html
Known issues
Here are the changes found in Patchwork_107101v5 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258: [PASS][3] -> [INCOMPLETE][4] ([i915#3303] /
[i915#4785])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12011/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107101v5/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@late_gt_pm:
- fi-bsw-nick:[PASS][5] -> [DMESG-FAIL][6] ([i915#3428] /
[i915#6217])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12011/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107101v5/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
*
igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka: [PASS][7] -> [FAIL][8] ([i915#6298])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12011/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107101v5/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
* igt@runner@aborted:
- fi-bsw-nick:NOTRUN -> [FAIL][9] ([fdo#109271] / [i915#4312])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107101v5/fi-bsw-nick/igt@run...@aborted.html
- fi-hsw-g3258: NOTRUN -> [FAIL][10] ([fdo#109271] / [i915#4312] /
[i915#6246])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107101v5/fi-hsw-g3258/igt@run...@aborted.html
Warnings
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [DMESG-FAIL][11] ([i915#4494] / [i915#4957]) ->
[DMESG-FAIL][12] ([i915#4957])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12011/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107101v5/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-elk-e7500: [INCOMPLETE][13] ([i915#6648]) -> [INCOMPLETE][14]
([i915#6598] / [i915#6601] / [i915#6648])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12011/fi-elk-e7500/igt@i915_susp...@basic-s3-without-i915.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107101v5/fi-elk-e7500/igt@i915_susp...@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#6217]: https://gitlab.freedesktop.org/drm/intel/issues/6217
[i915#6246]: https://gitlab.freedesktop.org/drm/intel/issues/6246
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6530]: https://gitlab.freedesktop.org/drm/intel/issues/6530
[i915#6598]: https://gitlab.freedesktop.org/drm/intel/issues/6598
[i915#6601]: https://gitlab.freedesktop.org/drm/intel/issues/6601
[i915#6637]: ht
Re: [Intel-gfx] [PATCH v6 3/4] drm/i915/display: add hotplug.suspended flag
On Fri, Jul 22, 2022 at 02:51:42PM +0200, Andrzej Hajda wrote:
> HPD events during driver removal can be generated by hardware and
> software frameworks - drm_dp_mst, the former we can avoid by disabling
> interrupts, the latter can be triggered by any drm_dp_mst transaction,
> and this is too late. Introducing suspended flag allows to solve this
> chicken-egg problem.
intel_hpd_cancel_work() is always called after suspending MST and
disabling IRQs (with the order I suggested in patch 1). If both of these
have disabled the corresponding functionality (MST, IRQs) properly with
all their MST/IRQ scheduled works guaranteed to not get rescheduled,
then it's not clear how could either intel_hpd_trigger_irq() or an IRQ
work run. So the problematic sequence would need a better explanation.
There's also already
dev_priv->runtime_pm.irqs_enabled
showing if hotplug interrupts are disabled (along with all other IRQs).
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5950
> Signed-off-by: Andrzej Hajda
> Reviewed-by: Arun R Murthy
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hotplug.c | 11 ++-
> drivers/gpu/drm/i915/display/intel_hotplug.h | 2 +-
> drivers/gpu/drm/i915/i915_driver.c | 4 ++--
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> 5 files changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f1c765ac7ab8aa..cd6139bb36151b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -9022,7 +9022,7 @@ void intel_modeset_driver_remove_noirq(struct
> drm_i915_private *i915)
> intel_dp_mst_suspend(i915);
>
> /* MST is the last user of HPD work */
> - intel_hpd_cancel_work(i915);
> + intel_hpd_suspend(i915);
>
> /* poll work can call into fbdev, hence clean that up afterwards */
> intel_fbdev_fini(i915);
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
> b/drivers/gpu/drm/i915/display/intel_hotplug.c
> index 5f8b4f481cff9a..e1d384cb99df6b 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> @@ -303,6 +303,8 @@ static void i915_digport_work_func(struct work_struct
> *work)
> u32 old_bits = 0;
>
> spin_lock_irq(&dev_priv->irq_lock);
> + if (dev_priv->hotplug.suspended)
> + return spin_unlock_irq(&dev_priv->irq_lock);
> long_port_mask = dev_priv->hotplug.long_port_mask;
> dev_priv->hotplug.long_port_mask = 0;
> short_port_mask = dev_priv->hotplug.short_port_mask;
> @@ -353,6 +355,8 @@ void intel_hpd_trigger_irq(struct intel_digital_port
> *dig_port)
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>
> spin_lock_irq(&i915->irq_lock);
> + if (i915->hotplug.suspended)
> + return spin_unlock_irq(&i915->irq_lock);
> i915->hotplug.short_port_mask |= BIT(dig_port->base.port);
> spin_unlock_irq(&i915->irq_lock);
>
> @@ -475,6 +479,9 @@ void intel_hpd_irq_handler(struct drm_i915_private
> *dev_priv,
>
> spin_lock(&dev_priv->irq_lock);
>
> + if (dev_priv->hotplug.suspended)
> + return spin_unlock(&dev_priv->irq_lock);
> +
> /*
>* Determine whether ->hpd_pulse() exists for each pin, and
>* whether we have a short or a long pulse. This is needed
> @@ -603,6 +610,7 @@ void intel_hpd_init(struct drm_i915_private *dev_priv)
>* just to make the assert_spin_locked checks happy.
>*/
> spin_lock_irq(&dev_priv->irq_lock);
> + dev_priv->hotplug.suspended = false;
> intel_hpd_irq_setup(dev_priv);
> spin_unlock_irq(&dev_priv->irq_lock);
> }
> @@ -721,13 +729,14 @@ void intel_hpd_init_work(struct drm_i915_private
> *dev_priv)
> intel_hpd_irq_storm_reenable_work);
> }
>
> -void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
> +void intel_hpd_suspend(struct drm_i915_private *dev_priv)
> {
> if (!HAS_DISPLAY(dev_priv))
> return;
>
> spin_lock_irq(&dev_priv->irq_lock);
>
> + dev_priv->hotplug.suspended = true;
> dev_priv->hotplug.long_port_mask = 0;
> dev_priv->hotplug.short_port_mask = 0;
> dev_priv->hotplug.event_bits = 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.h
> b/drivers/gpu/drm/i915/display/intel_hotplug.h
> index b87e95d606e668..54bddc4dd63421 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug.h
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.h
> @@ -23,7 +23,7 @@ void intel_hpd_irq_handler(struct drm_i915_private
> *dev_priv,
> void intel_hpd_trigger_irq(struct intel_digital_port *dig_port);
> void intel_hpd_init(struct drm_i915_private *dev_priv);
> void intel_hpd_init_work(struct drm_i915_private *dev_priv);
> -void intel_hpd_cancel_work(str
Re: [Intel-gfx] [PATCH v6 2/4] drm/i915/fbdev: suspend HPD before fbdev unregistration
On Fri, Jul 22, 2022 at 02:51:41PM +0200, Andrzej Hajda wrote: > HPD event after fbdev unregistration can cause registration of deferred > fbdev which will not be unregistered later, causing use-after-free. > To avoid it HPD handling should be suspended before fbdev unregistration. > > It should fix following GPF: > [272.634530] general protection fault, probably for non-canonical address > 0x6b6b6b6b6b6b6b6b: [#1] PREEMPT SMP NOPTI > [272.634536] CPU: 0 PID: 6030 Comm: i915_selftest Tainted: G U > 5.18.0-rc5-CI_DRM_11603-g12dccf4f5eef+ #1 > [272.634541] Hardware name: Intel Corporation Raptor Lake Client > Platform/RPL-S ADP-S DDR5 UDIMM CRB, BIOS RPLSFWI1.R00.2397.A01.2109300731 > 09/30/2021 > [272.634545] RIP: 0010:fb_do_apertures_overlap.part.14+0x26/0x60 > ... > [272.634582] Call Trace: > [272.634583] > [272.634585] do_remove_conflicting_framebuffers+0x59/0xa0 > [272.634589] remove_conflicting_framebuffers+0x2d/0xc0 > [272.634592] remove_conflicting_pci_framebuffers+0xc8/0x110 > [272.634595] drm_aperture_remove_conflicting_pci_framebuffers+0x52/0x70 > [272.634604] i915_driver_probe+0x63a/0xdd0 [i915] > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5329 > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5510 > Signed-off-by: Andrzej Hajda > Reviewed-by: Arun R Murthy > --- > drivers/gpu/drm/i915/display/intel_fbdev.c | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c > b/drivers/gpu/drm/i915/display/intel_fbdev.c > index 221336178991f0..94ddc0f34fde64 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbdev.c > +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c > @@ -573,7 +573,8 @@ void intel_fbdev_unregister(struct drm_i915_private > *dev_priv) > if (!ifbdev) > return; > > - cancel_work_sync(&dev_priv->fbdev_suspend_work); > + intel_fbdev_set_suspend(&dev_priv->drm, FBINFO_STATE_SUSPENDED, true); > + > if (!current_is_async()) > intel_fbdev_sync(ifbdev); > > @@ -618,7 +619,7 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int > state, bool synchronous > struct fb_info *info; > > if (!ifbdev || !ifbdev->vma) > - return; > + goto unlock; goto set_suspend; Reviewed-by: Imre Deak > > info = ifbdev->helper.fbdev; > > @@ -661,6 +662,7 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int > state, bool synchronous > drm_fb_helper_set_suspend(&ifbdev->helper, state); > console_unlock(); > > +unlock: > intel_fbdev_hpd_set_suspend(dev_priv, state); > } > > -- > 2.25.1 >
Re: [Intel-gfx] [PATCH v6 1/4] drm/i915/hpd: postpone HPD cancel work after last user suspension
On Fri, Jul 22, 2022 at 02:51:40PM +0200, Andrzej Hajda wrote: > i915->hotplug.dig_port_work can be queued from intel_hpd_irq_handler > called by IRQ handler or by intel_hpd_trigger_irq called from dp_mst. > Since dp_mst is suspended after irq handler uninstall, a cleaner approach > is to cancel hpd work after intel_dp_mst_suspend, otherwise we risk > use-after-free. > > It should fix following WARNINGS: > [283.405824] cpu_latency_qos_update_request called for unknown object > [283.405866] WARNING: CPU: 2 PID: 240 at kernel/power/qos.c:296 > cpu_latency_qos_update_request+0x2d/0x100 > [283.405912] CPU: 2 PID: 240 Comm: kworker/u64:9 Not tainted > 5.18.0-rc6-Patchwork_103738v3-g1672d1c43e43+ #1 > [283.405915] Hardware name: Intel Corporation Raptor Lake Client > Platform/RPL-S ADP-S DDR5 UDIMM CRB, BIOS RPLSFWI1.R00.2397.A01.2109300731 > 09/30/2021 > [283.405916] Workqueue: i915-dp i915_digport_work_func [i915] > [283.406020] RIP: 0010:cpu_latency_qos_update_request+0x2d/0x100 > ... > [283.406040] Call Trace: > [283.406041] > [283.406044] intel_dp_aux_xfer+0x60e/0x8e0 [i915] > [283.406131] ? finish_swait+0x80/0x80 > [283.406139] intel_dp_aux_transfer+0xc5/0x2b0 [i915] > [283.406218] drm_dp_dpcd_access+0x79/0x130 [drm_display_helper] > [283.406227] drm_dp_dpcd_read+0xe2/0xf0 [drm_display_helper] > [283.406233] intel_dp_hpd_pulse+0x134/0x570 [i915] > [283.406308] ? __down_killable+0x70/0x140 > [283.406313] i915_digport_work_func+0xba/0x150 [i915] > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4586 > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5558 > Signed-off-by: Andrzej Hajda > Reviewed-by: Arun R Murthy > --- > drivers/gpu/drm/i915/display/intel_display.c | 3 +++ > drivers/gpu/drm/i915/i915_irq.c | 1 - > 2 files changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index a0f84cbe974fc3..f1c765ac7ab8aa 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -9021,6 +9021,9 @@ void intel_modeset_driver_remove_noirq(struct > drm_i915_private *i915) >*/ > intel_dp_mst_suspend(i915); > > + /* MST is the last user of HPD work */ > + intel_hpd_cancel_work(i915); > + MST still requires AUX and short HPD interrupts and during shutdown and suspend the order is suspend-MST -> disable-IRQs. So I think it makes more sense to move intel_dp_mst_suspend() to i915_driver_remove() before intel_irq_uninstall(). > /* poll work can call into fbdev, hence clean that up afterwards */ > intel_fbdev_fini(i915); > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 73cebc6aa65072..db14787aef95dd 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -4597,7 +4597,6 @@ void intel_irq_uninstall(struct drm_i915_private > *dev_priv) > > free_irq(irq, dev_priv); > > - intel_hpd_cancel_work(dev_priv); > dev_priv->runtime_pm.irqs_enabled = false; > } > > -- > 2.25.1 >
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/backlight: Disable pps power hook for aux based backlight
== Series Details ==
Series: drm/i915/backlight: Disable pps power hook for aux based backlight
URL : https://patchwork.freedesktop.org/series/107555/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12011 -> Patchwork_107555v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107555v1/index.html
Participating hosts (37 -> 36)
--
Missing(1): fi-hsw-4770
Known issues
Here are the changes found in Patchwork_107555v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_suspend@basic-s3-without-i915:
- fi-pnv-d510:NOTRUN -> [INCOMPLETE][1] ([i915#6598] / [i915#6601])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107555v1/fi-pnv-d510/igt@i915_susp...@basic-s3-without-i915.html
*
igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka: [PASS][2] -> [FAIL][3] ([i915#6298])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12011/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107555v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
Possible fixes
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rplp-1}: [DMESG-WARN][4] ([i915#2867]) -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12011/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107555v1/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510:[DMESG-FAIL][6] ([i915#4528]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12011/fi-pnv-d510/igt@i915_selftest@l...@requests.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107555v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html
Warnings
* igt@i915_suspend@basic-s3-without-i915:
- fi-elk-e7500: [INCOMPLETE][8] ([i915#6648]) -> [INCOMPLETE][9]
([i915#6598] / [i915#6601] / [i915#6648])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12011/fi-elk-e7500/igt@i915_susp...@basic-s3-without-i915.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107555v1/fi-elk-e7500/igt@i915_susp...@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6503]: https://gitlab.freedesktop.org/drm/intel/issues/6503
[i915#6579]: https://gitlab.freedesktop.org/drm/intel/issues/6579
[i915#6598]: https://gitlab.freedesktop.org/drm/intel/issues/6598
[i915#6601]: https://gitlab.freedesktop.org/drm/intel/issues/6601
[i915#6648]: https://gitlab.freedesktop.org/drm/intel/issues/6648
Build changes
-
* Linux: CI_DRM_12011 -> Patchwork_107555v1
CI-20190529: 20190529
CI_DRM_12011: 9292bbfc4e5bcf539ccdd248881d149d4066eafc @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6634: e01fe99f00692864b709253638c809231d1fb333 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_107555v1: 9292bbfc4e5bcf539ccdd248881d149d4066eafc @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
4be9592c0848 drm/i915/backlight: Disable pps power hook for aux based backlight
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107555v1/index.html
Re: [Intel-gfx] [PATCH v7 1/8] overflow: Move and add few utility macros into overflow
On 22.08.2022 16:05, Andrzej Hajda wrote:
On 18.08.2022 02:12, Kees Cook wrote:
On Thu, Aug 18, 2022 at 01:07:29AM +0200, Andi Shyti wrote:
Hi Kees,
would you mind taking a look at this patch?
Hi! Thanks for the heads-up!
Thanks,
Andi
On Tue, Aug 16, 2022 at 06:35:18PM +0900, Gwan-gyeong Mun wrote:
It moves overflows_type utility macro into overflow header from
i915_utils
header. The overflows_type can be used to catch the truncation
between data
types. And it adds safe_conversion() macro which performs a type
conversion
(cast) of an source value into a new variable, checking that the
destination is large enough to hold the source value. And the
functionality
of overflows_type has been improved to handle the signbit.
The is_unsigned_type macro has been added to check the sign bit of the
built-in type.
v3: Add is_type_unsigned() macro (Mauro)
Modify overflows_type() macro to consider signed data types
(Mauro)
Fix the problem that safe_conversion() macro always returns true
v4: Fix kernel-doc markups
v6: Move macro addition location so that it can be used by other
than drm
subsystem (Jani, Mauro, Andi)
Change is_type_unsigned to is_unsigned_type to have the same
name form
as is_signed_type macro
Signed-off-by: Gwan-gyeong Mun
Cc: Thomas Hellström
Cc: Matthew Auld
Cc: Nirmoy Das
Cc: Jani Nikula
Cc: Andi Shyti
Reviewed-by: Mauro Carvalho Chehab (v5)
---
(...)
+
+/**
+ * overflows_type - helper for checking the truncation between data
types
+ * @x: Source for overflow type comparison
+ * @T: Destination for overflow type comparison
+ *
+ * It compares the values and size of each data type between the
first and
+ * second argument to check whether truncation can occur when
assigning the
+ * first argument to the variable of the second argument.
+ * Source and Destination can be used with or without sign bit.
+ * Composite data structures such as union and structure are not
considered.
+ * Enum data types are not considered.
+ * Floating point data types are not considered.
+ *
+ * Returns:
+ * True if truncation can occur, false otherwise.
+ */
+#define overflows_type(x, T) \
+ (is_unsigned_type(x) ? \
+ is_unsigned_type(T) ? \
+ (sizeof(x) > sizeof(T) && (x) >> BITS_PER_TYPE(T)) ? 1
: 0 \
+ : (sizeof(x) >= sizeof(T) && (x) >> (BITS_PER_TYPE(T) -
1)) ? 1 : 0 \
+ : is_unsigned_type(T) ? \
+ ((x) < 0) ? 1 : (sizeof(x) > sizeof(T) && (x) >>
BITS_PER_TYPE(T)) ? 1 : 0 \
+ : (sizeof(x) > sizeof(T)) ? \
+ ((x) < 0) ? (((x) * -1) >> BITS_PER_TYPE(T)) ? 1 : 0 \
+ : ((x) >> BITS_PER_TYPE(T)) ? 1 : 0 \
+ : 0)
Like the other, I'd much rather this was rephrased in terms of the
existing macros (e.g. type_min()/type_max().)
I am not sure how it could be rephrased with type_(min|max), but I guess
the shortest could be sth like:
#define overflows_type(x, T) __builtin_add_overflow_p(x, (typeof(T))0,
(typeof(T))0)
Except this macro is available since gcc 7, but apparently
__builtin_add_overflow is supported since gcc 5, which should be OK:
#define overflows_type(x, T) ({ typeof(T) r = 0;
__builtin_add_overflow_p((x), r, r); })
Regards
Andrzej
Regards
Andrzej
+
+/**
+ * safe_conversion - perform a type conversion (cast) of an source
value into
+ * a new variable, checking that the destination is large enough to
hold the
+ * source value.
+ * @ptr: Destination pointer address
+ * @value: Source value
+ *
+ * Returns:
+ * If the value would overflow the destination, it returns false.
+ */
+#define safe_conversion(ptr, value) ({ \
+ typeof(value) __v = (value); \
+ typeof(ptr) __ptr = (ptr); \
+ overflows_type(__v, *__ptr) ? 0 : ((*__ptr =
(typeof(*__ptr))__v), 1); \
+})
I try to avoid "safe" as an adjective for interface names, since it
doesn't really answer "safe from what?" This looks more like "assign, but
zero when out of bounds". And it can be built from existing macros here:
if (check_add_overflow(0, value, ptr))
*ptr = 0;
I actually want to push back on this a bit, because there can still be
logic bugs built around this kind of primitive. Shouldn't out-of-bounds
assignments be seen as a direct failure? I would think this would be
sufficient:
#define check_assign(value, ptr) check_add_overflow(0, value, ptr)
And callers would do:
if (check_assign(value, &var))
return -EINVAL;
etc.
[Intel-gfx] [PATCH] drm/i915/backlight: Disable pps power hook for aux based backlight
Pps power hook seems to be problematic for backlight controlled via
aux channel. Disable it for such cases.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3657
Signed-off-by: Jouni Högander
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_backlight.c | 11 ---
drivers/gpu/drm/i915/display/intel_dp.c| 2 --
2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c
b/drivers/gpu/drm/i915/display/intel_backlight.c
index af28b143d27a..5d317a20dd0f 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -17,6 +17,7 @@
#include "intel_dsi_dcs_backlight.h"
#include "intel_panel.h"
#include "intel_pci_config.h"
+#include "intel_pps.h"
/**
* scale - scale values from one range to another
@@ -1778,9 +1779,13 @@ void intel_backlight_init_funcs(struct intel_panel
*panel)
panel->backlight.pwm_funcs = &i9xx_pwm_funcs;
}
- if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&
- intel_dp_aux_init_backlight_funcs(connector) == 0)
- return;
+ if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
+ if (intel_dp_aux_init_backlight_funcs(connector) == 0)
+ return;
+
+ if (!(dev_priv->quirks & QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK))
+ connector->panel.backlight.power =
intel_pps_backlight_power;
+ }
/* We're using a standard PWM backlight interface */
panel->backlight.funcs = &pwm_bl_funcs;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 32292c0be2bd..ac90d455a7c7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5293,8 +5293,6 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
intel_panel_init(intel_connector);
- if (!(dev_priv->quirks & QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK))
- intel_connector->panel.backlight.power =
intel_pps_backlight_power;
intel_backlight_setup(intel_connector, pipe);
intel_edp_add_properties(intel_dp);
--
2.34.1
Re: [Intel-gfx] [PATCH v7 1/8] overflow: Move and add few utility macros into overflow
On 18.08.2022 02:12, Kees Cook wrote:
On Thu, Aug 18, 2022 at 01:07:29AM +0200, Andi Shyti wrote:
Hi Kees,
would you mind taking a look at this patch?
Hi! Thanks for the heads-up!
Thanks,
Andi
On Tue, Aug 16, 2022 at 06:35:18PM +0900, Gwan-gyeong Mun wrote:
It moves overflows_type utility macro into overflow header from i915_utils
header. The overflows_type can be used to catch the truncation between data
types. And it adds safe_conversion() macro which performs a type conversion
(cast) of an source value into a new variable, checking that the
destination is large enough to hold the source value. And the functionality
of overflows_type has been improved to handle the signbit.
The is_unsigned_type macro has been added to check the sign bit of the
built-in type.
v3: Add is_type_unsigned() macro (Mauro)
Modify overflows_type() macro to consider signed data types (Mauro)
Fix the problem that safe_conversion() macro always returns true
v4: Fix kernel-doc markups
v6: Move macro addition location so that it can be used by other than drm
subsystem (Jani, Mauro, Andi)
Change is_type_unsigned to is_unsigned_type to have the same name form
as is_signed_type macro
Signed-off-by: Gwan-gyeong Mun
Cc: Thomas Hellström
Cc: Matthew Auld
Cc: Nirmoy Das
Cc: Jani Nikula
Cc: Andi Shyti
Reviewed-by: Mauro Carvalho Chehab (v5)
---
drivers/gpu/drm/i915/i915_utils.h | 5 +--
include/linux/overflow.h | 54 +++
2 files changed, 55 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_utils.h
b/drivers/gpu/drm/i915/i915_utils.h
index c10d68cdc3ca..eb0ded23fa9c 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -32,6 +32,7 @@
#include
#include
#include
+#include
#ifdef CONFIG_X86
#include
@@ -111,10 +112,6 @@ bool i915_error_injected(void);
#define range_overflows_end_t(type, start, size, max) \
range_overflows_end((type)(start), (type)(size), (type)(max))
-/* Note we don't consider signbits :| */
-#define overflows_type(x, T) \
- (sizeof(x) > sizeof(T) && (x) >> BITS_PER_TYPE(T))
-
#define ptr_mask_bits(ptr, n) ({ \
unsigned long __v = (unsigned long)(ptr); \
(typeof(ptr))(__v & -BIT(n)); \
diff --git a/include/linux/overflow.h b/include/linux/overflow.h
index f1221d11f8e5..462a03454377 100644
--- a/include/linux/overflow.h
+++ b/include/linux/overflow.h
@@ -35,6 +35,60 @@
#define type_max(T) ((T)((__type_half_max(T) - 1) + __type_half_max(T)))
#define type_min(T) ((T)((T)-type_max(T)-(T)1))
+/**
+ * is_unsigned_type - helper for checking data type which is an unsigned data
+ * type or not
+ * @x: The data type to check
+ *
+ * Returns:
+ * True if the data type is an unsigned data type, false otherwise.
+ */
+#define is_unsigned_type(x) ((typeof(x))-1 >= (typeof(x))0)
I'd rather not have separate logic for this. Instead, I'd like it to be:
#define is_unsigned_type(x) (!is_signed_type(x))
+
+/**
+ * overflows_type - helper for checking the truncation between data types
+ * @x: Source for overflow type comparison
+ * @T: Destination for overflow type comparison
+ *
+ * It compares the values and size of each data type between the first and
+ * second argument to check whether truncation can occur when assigning the
+ * first argument to the variable of the second argument.
+ * Source and Destination can be used with or without sign bit.
+ * Composite data structures such as union and structure are not considered.
+ * Enum data types are not considered.
+ * Floating point data types are not considered.
+ *
+ * Returns:
+ * True if truncation can occur, false otherwise.
+ */
+#define overflows_type(x, T) \
+ (is_unsigned_type(x) ? \
+ is_unsigned_type(T) ? \
+ (sizeof(x) > sizeof(T) && (x) >> BITS_PER_TYPE(T)) ? 1
: 0 \
+ : (sizeof(x) >= sizeof(T) && (x) >> (BITS_PER_TYPE(T) -
1)) ? 1 : 0 \
+ : is_unsigned_type(T) ? \
+ ((x) < 0) ? 1 : (sizeof(x) > sizeof(T) && (x) >>
BITS_PER_TYPE(T)) ? 1 : 0 \
+ : (sizeof(x) > sizeof(T)) ? \
+ ((x) < 0) ? (((x) * -1) >> BITS_PER_TYPE(T)) ? 1 : 0 \
+ : ((x) >> BITS_PER_TYPE(T)) ? 1 : 0 \
+ : 0)
Like the other, I'd much rather this was rephrased in terms of the
existing macros (e.g. type_min()/type_max().)
I am not sure how it could be rephrased with type_(min|max), but I guess
the shortest could be sth like:
#define overflows_type(x, T) __builtin_add_overflow_p(x, (typeof(T))0,
(typeof(T))0)
Regards
Andrzej
+
+/**
+ * safe_conversion - perform a type conversion (cast) of an source value into
+ * a new variable, checking that the destination is large enough to hold the
+ * source value.
+ * @ptr: Destination poi
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/combo_phy: Set DCC_MODE to one time update mode
== Series Details ==
Series: drm/i915/combo_phy: Set DCC_MODE to one time update mode
URL : https://patchwork.freedesktop.org/series/107551/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12009 -> Patchwork_107551v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107551v1/index.html
Participating hosts (34 -> 35)
--
Additional (3): fi-kbl-soraka bat-dg2-8 fi-hsw-4770
Missing(2): bat-dg2-10 bat-dg2-9
Known issues
Here are the changes found in Patchwork_107551v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#3012])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107551v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][2] ([i915#4785])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107551v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
- bat-dg1-6: [PASS][3] -> [DMESG-FAIL][4] ([i915#4494] /
[i915#4957])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107551v1/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271]) +9 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107551v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +7
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107551v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1072]) +3
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107551v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
* igt@runner@aborted:
- fi-kbl-soraka: NOTRUN -> [FAIL][8] ([i915#6219])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107551v1/fi-kbl-soraka/igt@run...@aborted.html
Possible fixes
* igt@fbdev@read:
- {bat-rpls-2}: [SKIP][9] ([i915#2582]) -> [PASS][10] +4 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/bat-rpls-2/igt@fb...@read.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107551v1/bat-rpls-2/igt@fb...@read.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-cfl-8109u: [DMESG-FAIL][11] ([i915#5334]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/fi-cfl-8109u/igt@i915_selftest@live@gt_heartbeat.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107551v1/fi-cfl-8109u/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_frontbuffer_tracking@basic:
- {bat-rpls-2}: [SKIP][13] ([i915#1849]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/bat-rpls-2/igt@kms_frontbuffer_track...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107551v1/bat-rpls-2/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-fence-flip:
- {bat-rpls-2}: [SKIP][15] ([fdo#109295] / [i915#1845] / [i915#3708])
-> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/bat-rpls-2/igt@prime_v...@basic-fence-flip.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107551v1/bat-rpls-2/igt@prime_v...@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3708]: https:/
[Intel-gfx] ✓ Fi.CI.BAT: success for Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes
== Series Details ==
Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes
URL : https://patchwork.freedesktop.org/series/107550/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12009 -> Patchwork_107550v1
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_107550v1 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_107550v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/index.html
Participating hosts (34 -> 36)
--
Additional (3): fi-kbl-soraka bat-dg2-8 fi-hsw-4770
Missing(1): bat-dg2-10
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_107550v1:
### IGT changes ###
Warnings
* igt@i915_suspend@basic-s3-without-i915:
- fi-kbl-7567u: [INCOMPLETE][1] ([i915#6598]) -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/fi-kbl-7567u/igt@i915_susp...@basic-s3-without-i915.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/fi-kbl-7567u/igt@i915_susp...@basic-s3-without-i915.html
- fi-hsw-g3258: [INCOMPLETE][3] ([i915#4817] / [i915#6598]) ->
[INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/fi-hsw-g3258/igt@i915_susp...@basic-s3-without-i915.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/fi-hsw-g3258/igt@i915_susp...@basic-s3-without-i915.html
Known issues
Here are the changes found in Patchwork_107550v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_softpin@allocator-basic-reserve:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271]) +9 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/fi-hsw-4770/igt@gem_soft...@allocator-basic-reserve.html
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#3012])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][7] ([i915#4785])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
- bat-dg1-6: [PASS][8] -> [DMESG-FAIL][9] ([i915#4494] /
[i915#4957])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-pnv-d510:NOTRUN -> [INCOMPLETE][10] ([i915#6598] / [i915#6601])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/fi-pnv-d510/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +7
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1072]) +3
similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
* igt@runner@aborted:
- fi-kbl-soraka: NOTRUN -> [FAIL][13] ([i915#6219])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/fi-kbl-soraka/igt@run...@aborted.html
Possible fixes
* igt@fbdev@read:
- {bat-rpls-2}: [SKIP][14] ([i915#2582]) -> [PASS][15] +4 similar
issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/bat-rpls-2/igt@fb...@read.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/bat-rpls-2/igt@fb...@read.html
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rplp-1}: [DMESG-WARN][16] ([i915#2867]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-cfl-8109u: [DMESG-FAIL][18] ([i915#5334]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/fi-cfl-8109u/igt@i915_selftest@live@gt_heartbeat.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/fi-cfl-8109u/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@requests:
- {bat-rpls-1}: [INCOMPLETE][20
[Intel-gfx] ✓ Fi.CI.BAT: success for Add DP MST DSC support to i915 (rev7)
== Series Details ==
Series: Add DP MST DSC support to i915 (rev7)
URL : https://patchwork.freedesktop.org/series/101492/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12009 -> Patchwork_101492v7
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v7/index.html
Participating hosts (34 -> 37)
--
Additional (3): fi-kbl-soraka bat-dg2-8 fi-hsw-4770
Known issues
Here are the changes found in Patchwork_101492v7 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_softpin@allocator-basic-reserve:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271]) +9 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v7/fi-hsw-4770/igt@gem_soft...@allocator-basic-reserve.html
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#3012])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v7/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [PASS][3] -> [DMESG-FAIL][4] ([i915#4494] /
[i915#4957])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v7/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][5] ([i915#4817] / [i915#6598])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v7/fi-hsw-4770/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +7
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v7/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1072]) +3
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v7/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
* igt@runner@aborted:
- fi-kbl-soraka: NOTRUN -> [FAIL][8] ([i915#6219])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v7/fi-kbl-soraka/igt@run...@aborted.html
Possible fixes
* igt@fbdev@read:
- {bat-rpls-2}: [SKIP][9] ([i915#2582]) -> [PASS][10] +4 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/bat-rpls-2/igt@fb...@read.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v7/bat-rpls-2/igt@fb...@read.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-cfl-8109u: [DMESG-FAIL][11] ([i915#5334]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/fi-cfl-8109u/igt@i915_selftest@live@gt_heartbeat.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v7/fi-cfl-8109u/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_frontbuffer_tracking@basic:
- {bat-rpls-2}: [SKIP][13] ([i915#1849]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/bat-rpls-2/igt@kms_frontbuffer_track...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v7/bat-rpls-2/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-fence-flip:
- {bat-rpls-2}: [SKIP][15] ([fdo#109295] / [i915#1845] / [i915#3708])
-> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/bat-rpls-2/igt@prime_v...@basic-fence-flip.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v7/bat-rpls-2/igt@prime_v...@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.free
[Intel-gfx] [RFC 08/10] cpuhp: Replace cpumask_any_but(cpu_online_mask, cpu)
In a kexec quick reboot path, the dying cpus are still on
cpu_online_mask. During the teardown of cpu, a subsystem needs to
migrate its broker to a real online cpu.
This patch replaces cpumask_any_but(cpu_online_mask, cpu) in a teardown
procedure with cpumask_not_dying_but(cpu_online_mask, cpu).
Signed-off-by: Pingfan Liu
Cc: Russell King
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Pengutronix Kernel Team
Cc: Fabio Estevam
Cc: NXP Linux Team
Cc: Fenghua Yu
Cc: Dave Jiang
Cc: Vinod Koul
Cc: Wu Hao
Cc: Tom Rix
Cc: Moritz Fischer
Cc: Xu Yilun
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
Cc: David Airlie
Cc: Daniel Vetter
Cc: Will Deacon
Cc: Mark Rutland
Cc: Frank Li
Cc: Shaokun Zhang
Cc: Qi Liu
Cc: Andy Gross
Cc: Bjorn Andersson
Cc: Konrad Dybcio
Cc: Khuong Dinh
Cc: Li Yang
Cc: Yury Norov
To: linux-arm-ker...@lists.infradead.org
To: dmaeng...@vger.kernel.org
To: linux-f...@vger.kernel.org
To: intel-gfx@lists.freedesktop.org
To: dri-de...@lists.freedesktop.org
To: linux-arm-...@vger.kernel.org
To: linuxppc-...@lists.ozlabs.org
To: linux-ker...@vger.kernel.org
---
arch/arm/mach-imx/mmdc.c | 2 +-
arch/arm/mm/cache-l2x0-pmu.c | 2 +-
drivers/dma/idxd/perfmon.c | 2 +-
drivers/fpga/dfl-fme-perf.c | 2 +-
drivers/gpu/drm/i915/i915_pmu.c | 2 +-
drivers/perf/arm-cci.c | 2 +-
drivers/perf/arm-ccn.c | 2 +-
drivers/perf/arm-cmn.c | 4 ++--
drivers/perf/arm_dmc620_pmu.c| 2 +-
drivers/perf/arm_dsu_pmu.c | 2 +-
drivers/perf/arm_smmuv3_pmu.c| 2 +-
drivers/perf/fsl_imx8_ddr_perf.c | 2 +-
drivers/perf/hisilicon/hisi_uncore_pmu.c | 2 +-
drivers/perf/marvell_cn10k_tad_pmu.c | 2 +-
drivers/perf/qcom_l2_pmu.c | 2 +-
drivers/perf/qcom_l3_pmu.c | 2 +-
drivers/perf/xgene_pmu.c | 2 +-
drivers/soc/fsl/qbman/bman_portal.c | 2 +-
drivers/soc/fsl/qbman/qman_portal.c | 2 +-
19 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c
index af12668d0bf5..a109a7ea8613 100644
--- a/arch/arm/mach-imx/mmdc.c
+++ b/arch/arm/mach-imx/mmdc.c
@@ -220,7 +220,7 @@ static int mmdc_pmu_offline_cpu(unsigned int cpu, struct
hlist_node *node)
if (!cpumask_test_and_clear_cpu(cpu, &pmu_mmdc->cpu))
return 0;
- target = cpumask_any_but(cpu_online_mask, cpu);
+ target = cpumask_not_dying_but(cpu_online_mask, cpu);
if (target >= nr_cpu_ids)
return 0;
diff --git a/arch/arm/mm/cache-l2x0-pmu.c b/arch/arm/mm/cache-l2x0-pmu.c
index 993fefdc167a..1b0037ef7fa5 100644
--- a/arch/arm/mm/cache-l2x0-pmu.c
+++ b/arch/arm/mm/cache-l2x0-pmu.c
@@ -428,7 +428,7 @@ static int l2x0_pmu_offline_cpu(unsigned int cpu)
if (!cpumask_test_and_clear_cpu(cpu, &pmu_cpu))
return 0;
- target = cpumask_any_but(cpu_online_mask, cpu);
+ target = cpumask_not_dying_but(cpu_online_mask, cpu);
if (target >= nr_cpu_ids)
return 0;
diff --git a/drivers/dma/idxd/perfmon.c b/drivers/dma/idxd/perfmon.c
index d73004f47cf4..f3f1ccb55f73 100644
--- a/drivers/dma/idxd/perfmon.c
+++ b/drivers/dma/idxd/perfmon.c
@@ -528,7 +528,7 @@ static int perf_event_cpu_offline(unsigned int cpu, struct
hlist_node *node)
if (!cpumask_test_and_clear_cpu(cpu, &perfmon_dsa_cpu_mask))
return 0;
- target = cpumask_any_but(cpu_online_mask, cpu);
+ target = cpumask_not_dying_but(cpu_online_mask, cpu);
/* migrate events if there is a valid target */
if (target < nr_cpu_ids)
diff --git a/drivers/fpga/dfl-fme-perf.c b/drivers/fpga/dfl-fme-perf.c
index 587c82be12f7..57804f28357e 100644
--- a/drivers/fpga/dfl-fme-perf.c
+++ b/drivers/fpga/dfl-fme-perf.c
@@ -948,7 +948,7 @@ static int fme_perf_offline_cpu(unsigned int cpu, struct
hlist_node *node)
if (cpu != priv->cpu)
return 0;
- target = cpumask_any_but(cpu_online_mask, cpu);
+ target = cpumask_not_dying_but(cpu_online_mask, cpu);
if (target >= nr_cpu_ids)
return 0;
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 958b37123bf1..f866f9223492 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -1068,7 +1068,7 @@ static int i915_pmu_cpu_offline(unsigned int cpu, struct
hlist_node *node)
return 0;
if (cpumask_test_and_clear_cpu(cpu, &i915_pmu_cpumask)) {
- target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
+ target = cpumask_not_dying_but(topology_sibling_cpumask(cpu),
cpu);
/* Migrate events if there is a valid target */
if (target < nr_cpu_ids) {
diff --git a/drivers/perf/arm-cci.c b/drivers/perf/arm-cci.c
index 03b1309875ae..481
[Intel-gfx] [PATCH] drm/i915/combo_phy: Set DCC_MODE to one time update mode
As per Bspec:49291 update, the DCC Mode select is to be set to one time update mode, instead of continuous DCC calibration mode for Display > 12 combo phy. This change is required to avoid glitches that occur, during on the fly updates to DCC code, with continuous mode, resulting in flickers seen with eDP HBR3 panels. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_combo_phy.c | 4 ++-- drivers/gpu/drm/i915/display/intel_combo_phy_regs.h | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 64890f39c3cc..76e4e748823a 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -244,7 +244,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy), DCC_MODE_SELECT_MASK, -DCC_MODE_SELECT_CONTINUOSLY); +DCC_MODE_SELECT_ONCE); } ret &= icl_verify_procmon_ref_values(dev_priv, phy); @@ -367,7 +367,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); val &= ~DCC_MODE_SELECT_MASK; - val |= DCC_MODE_SELECT_CONTINUOSLY; + val |= DCC_MODE_SELECT_ONCE; intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); } diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h index 2ed65193ca19..cf46f13401d1 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h @@ -92,6 +92,7 @@ #define ICL_PORT_PCS_DW1_LN(ln, phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy)) #define DCC_MODE_SELECT_MASK (0x3 << 20) #define DCC_MODE_SELECT_CONTINUOSLY (0x3 << 20) +#define DCC_MODE_SELECT_ONCE (0x0 << 20) #define COMMON_KEEPER_EN (1 << 26) #define LATENCY_OPTIM_MASK (0x3 << 2) #define LATENCY_OPTIM_VAL(x) ((x) << 2) -- 2.25.1
Re: [Intel-gfx] [PATCH v2] drm/i915/combo_phy: Add Workaround to avoid flicker with HBR3 eDP Panels
The Bspec:49291 is now changed to reflect that for all platforms the
DCC_MODE will be programmed to DCC_MODE_SELECT_ONCE,
rather than DCC_MODE_SELECT_CONTINUOUSLY.
I will send new patch for the same.
Regards,
Ankit
On 8/10/2022 8:26 PM, Ankit Nautiyal wrote:
Wa_22012718247 : When Display PHY is configured in continuous
DCC calibration mode, the DCC (duty cycle correction) for the clock
erroneously goes through a state where the DCC code is 0x00 when it is
supposed to be transitioning from 0x10 to 0x0F. This glitch causes a
distortion in the clock, which leads to a bit error. The issue is known
to be causing flickering with eDP HBR3 panels.
The work around configures the DCC in one-time-update mode.
This mode updates the DCC code one time during training and then
it does not change. This will prevent on-the-fly updates so that the
glitch does not occur.
v2: Added helper function for DCC_MODE (Imre).
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_combo_phy.c | 16 ++--
.../gpu/drm/i915/display/intel_combo_phy_regs.h | 1 +
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 64890f39c3cc..b3be0e3ca984 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -226,6 +226,17 @@ static bool phy_is_master(struct drm_i915_private
*dev_priv, enum phy phy)
return false;
}
+static u32 tgl_dcc_calibration_mode(struct drm_i915_private *dev_priv)
+{
+ /* Wa_22012718247:tgl,adlp,adls */
+ if (IS_TIGERLAKE(dev_priv) ||
+ IS_ALDERLAKE_P(dev_priv) ||
+ IS_ALDERLAKE_S(dev_priv))
+ return DCC_MODE_SELECT_ONCE;
+
+ return DCC_MODE_SELECT_CONTINUOSLY;
+}
+
static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
enum phy phy)
{
@@ -244,7 +255,7 @@ static bool icl_combo_phy_verify_state(struct
drm_i915_private *dev_priv,
ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy),
DCC_MODE_SELECT_MASK,
-DCC_MODE_SELECT_CONTINUOSLY);
+tgl_dcc_calibration_mode(dev_priv));
}
ret &= icl_verify_procmon_ref_values(dev_priv, phy);
@@ -366,8 +377,9 @@ static void icl_combo_phys_init(struct drm_i915_private
*dev_priv)
intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);
val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
+
val &= ~DCC_MODE_SELECT_MASK;
- val |= DCC_MODE_SELECT_CONTINUOSLY;
+ val |= tgl_dcc_calibration_mode(dev_priv);
intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy),
val);
}
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
index 2ed65193ca19..cf46f13401d1 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
@@ -92,6 +92,7 @@
#define ICL_PORT_PCS_DW1_LN(ln, phy) _MMIO(_ICL_PORT_PCS_DW_LN(1,
ln, phy))
#define DCC_MODE_SELECT_MASK(0x3 << 20)
#define DCC_MODE_SELECT_CONTINUOSLY (0x3 << 20)
+#define DCC_MODE_SELECT_ONCE (0x0 << 20)
#define COMMON_KEEPER_EN(1 << 26)
#define LATENCY_OPTIM_MASK (0x3 << 2)
#define LATENCY_OPTIM_VAL(x)((x) << 2)
Re: [Intel-gfx] [PATCH v7 1/8] overflow: Move and add few utility macros into overflow
On Wed, 17 Aug 2022, Kees Cook wrote:
> On Thu, Aug 18, 2022 at 01:07:29AM +0200, Andi Shyti wrote:
>> Hi Kees,
>>
>> would you mind taking a look at this patch?
>
> Hi! Thanks for the heads-up!
Thanks for your review. This actually reaffirms my belief that we need
to get these macros out of i915_utils.h and into the common headers,
where we can get more eyes on them.
BR,
Jani.
>
>>
>> Thanks,
>> Andi
>>
>> On Tue, Aug 16, 2022 at 06:35:18PM +0900, Gwan-gyeong Mun wrote:
>> > It moves overflows_type utility macro into overflow header from i915_utils
>> > header. The overflows_type can be used to catch the truncation between data
>> > types. And it adds safe_conversion() macro which performs a type conversion
>> > (cast) of an source value into a new variable, checking that the
>> > destination is large enough to hold the source value. And the functionality
>> > of overflows_type has been improved to handle the signbit.
>> > The is_unsigned_type macro has been added to check the sign bit of the
>> > built-in type.
>> >
>> > v3: Add is_type_unsigned() macro (Mauro)
>> > Modify overflows_type() macro to consider signed data types (Mauro)
>> > Fix the problem that safe_conversion() macro always returns true
>> > v4: Fix kernel-doc markups
>> > v6: Move macro addition location so that it can be used by other than drm
>> > subsystem (Jani, Mauro, Andi)
>> > Change is_type_unsigned to is_unsigned_type to have the same name form
>> > as is_signed_type macro
>> >
>> > Signed-off-by: Gwan-gyeong Mun
>> > Cc: Thomas Hellström
>> > Cc: Matthew Auld
>> > Cc: Nirmoy Das
>> > Cc: Jani Nikula
>> > Cc: Andi Shyti
>> > Reviewed-by: Mauro Carvalho Chehab (v5)
>> > ---
>> > drivers/gpu/drm/i915/i915_utils.h | 5 +--
>> > include/linux/overflow.h | 54 +++
>> > 2 files changed, 55 insertions(+), 4 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_utils.h
>> > b/drivers/gpu/drm/i915/i915_utils.h
>> > index c10d68cdc3ca..eb0ded23fa9c 100644
>> > --- a/drivers/gpu/drm/i915/i915_utils.h
>> > +++ b/drivers/gpu/drm/i915/i915_utils.h
>> > @@ -32,6 +32,7 @@
>> > #include
>> > #include
>> > #include
>> > +#include
>> >
>> > #ifdef CONFIG_X86
>> > #include
>> > @@ -111,10 +112,6 @@ bool i915_error_injected(void);
>> > #define range_overflows_end_t(type, start, size, max) \
>> >range_overflows_end((type)(start), (type)(size), (type)(max))
>> >
>> > -/* Note we don't consider signbits :| */
>> > -#define overflows_type(x, T) \
>> > - (sizeof(x) > sizeof(T) && (x) >> BITS_PER_TYPE(T))
>> > -
>> > #define ptr_mask_bits(ptr, n) ({ \
>> >unsigned long __v = (unsigned long)(ptr); \
>> >(typeof(ptr))(__v & -BIT(n)); \
>> > diff --git a/include/linux/overflow.h b/include/linux/overflow.h
>> > index f1221d11f8e5..462a03454377 100644
>> > --- a/include/linux/overflow.h
>> > +++ b/include/linux/overflow.h
>> > @@ -35,6 +35,60 @@
>> > #define type_max(T) ((T)((__type_half_max(T) - 1) + __type_half_max(T)))
>> > #define type_min(T) ((T)((T)-type_max(T)-(T)1))
>> >
>> > +/**
>> > + * is_unsigned_type - helper for checking data type which is an unsigned
>> > data
>> > + * type or not
>> > + * @x: The data type to check
>> > + *
>> > + * Returns:
>> > + * True if the data type is an unsigned data type, false otherwise.
>> > + */
>> > +#define is_unsigned_type(x) ((typeof(x))-1 >= (typeof(x))0)
>
> I'd rather not have separate logic for this. Instead, I'd like it to be:
>
> #define is_unsigned_type(x) (!is_signed_type(x))
>
>> > +
>> > +/**
>> > + * overflows_type - helper for checking the truncation between data types
>> > + * @x: Source for overflow type comparison
>> > + * @T: Destination for overflow type comparison
>> > + *
>> > + * It compares the values and size of each data type between the first and
>> > + * second argument to check whether truncation can occur when assigning
>> > the
>> > + * first argument to the variable of the second argument.
>> > + * Source and Destination can be used with or without sign bit.
>> > + * Composite data structures such as union and structure are not
>> > considered.
>> > + * Enum data types are not considered.
>> > + * Floating point data types are not considered.
>> > + *
>> > + * Returns:
>> > + * True if truncation can occur, false otherwise.
>> > + */
>> > +#define overflows_type(x, T) \
>> > + (is_unsigned_type(x) ? \
>> > + is_unsigned_type(T) ? \
>> > + (sizeof(x) > sizeof(T) && (x) >> BITS_PER_TYPE(T)) ? 1
>> > : 0 \
>> > + : (sizeof(x) >= sizeof(T) && (x) >> (BITS_PER_TYPE(T) -
>> > 1)) ? 1 : 0 \
>> > + : is_unsigned_type(T) ? \
>> > + ((x) < 0) ? 1 : (sizeof(x) > sizeof(T) && (x) >>
>> > BITS_PER_TYPE(T)) ? 1 : 0 \
>> > + : (sizeof(x) > sizeof(T)) ? \
>> > + ((x) < 0) ? (((x) * -1) >> BITS_PER_TYPE(T)) ? 1
[Intel-gfx] [PATCH 5/5] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP
During FRL bandwidth check for downstream HDMI2.1 sink,
the min BPC supported is incorrectly taken for DP, and the check does
not consider ybcr420 only modes.
This patch fixes the bandwidth calculation similar to the TMDS case, by
taking min 8Bpc and considering Ycbcr420 only modes.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 52 ++---
1 file changed, 39 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f0a62f71904e..7f24f7633078 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -118,6 +118,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp);
+static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp);
static bool
is_dfp_hdmi_sink_dsc_1_2(struct intel_dp *intel_dp)
@@ -917,6 +918,32 @@ intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
return MODE_OK;
}
+static int
+intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock,
+ int bpc, bool ycbcr_420_only)
+{
+ int target_bw;
+ int max_frl_bw;
+ int bpp = bpc * 3;
+
+ if (ycbcr_420_only)
+ target_clock /= 2;
+
+ target_bw = bpp * target_clock;
+
+ /* check for MAX FRL BW for both PCON and HDMI2.1 sink */
+ max_frl_bw = min(intel_dp->dfp.pcon_max_frl_bw,
+intel_dp_hdmi_sink_max_frl(intel_dp));
+
+ /* converting bw from Gbps to Kbps*/
+ max_frl_bw = max_frl_bw * 100;
+
+ if (target_bw > max_frl_bw)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
static enum drm_mode_status
intel_dp_mode_valid_downstream(struct intel_connector *connector,
const struct drm_display_mode *mode,
@@ -925,23 +952,24 @@ intel_dp_mode_valid_downstream(struct intel_connector
*connector,
struct intel_dp *intel_dp = intel_attached_dp(connector);
const struct drm_display_info *info = &connector->base.display_info;
enum drm_mode_status status;
- bool ycbcr_420_only;
+ bool ycbcr_420_only = drm_mode_is_420_only(info, mode);
/* If PCON supports FRL MODE, check FRL bandwidth constraints */
if (intel_dp->dfp.pcon_max_frl_bw) {
- int target_bw;
- int max_frl_bw;
- int bpp = intel_dp_mode_min_output_bpp(connector, mode);
-
- target_bw = bpp * target_clock;
- max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
+ /* Assume 8bpc for the HDMI2.1 FRL BW check */
+ status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8,
ycbcr_420_only);
- /* converting bw from Gbps to Kbps*/
- max_frl_bw = max_frl_bw * 100;
+ if (status != MODE_OK) {
+ if (ycbcr_420_only ||
+ !connector->base.ycbcr_420_allowed ||
+ !drm_mode_is_420_also(info, mode))
+ return status;
- if (target_bw > max_frl_bw)
- return MODE_CLOCK_HIGH;
+ status = intel_dp_frl_bw_valid(intel_dp, target_clock,
8, true);
+ if (status != MODE_OK)
+ return status;
+ }
return MODE_OK;
}
@@ -950,8 +978,6 @@ intel_dp_mode_valid_downstream(struct intel_connector
*connector,
target_clock > intel_dp->dfp.max_dotclock)
return MODE_CLOCK_HIGH;
- ycbcr_420_only = drm_mode_is_420_only(info, mode);
-
/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
8, ycbcr_420_only, true);
--
2.25.1
[Intel-gfx] [PATCH 2/5] drm/i915/dp: Reset frl trained flag before restarting FRL training
For cases where DP has HDMI2.1 sink and FRL Link issues are detected,
reset the flag to state FRL trained status before restarting FRL
training.
Fixes: 9488a030ac91 ("drm/i915: Add support for enabling link status and
recovery")
Cc: Swati Sharma
Cc: Ankit Nautiyal
Cc: Uma Shankar (v2)
Cc: Jani Nikula
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index fdf82373a22d..fc082a933d59 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3957,6 +3957,8 @@ intel_dp_handle_hdmi_link_status_change(struct intel_dp
*intel_dp)
drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux,
&intel_dp->attached_connector->base);
+ intel_dp->frl.is_trained = false;
+
/* Restart FRL training or fall back to TMDS mode */
intel_dp_check_frl_training(intel_dp);
}
--
2.25.1
[Intel-gfx] [PATCH 4/5] drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC
Currently we use the highest input BPC supported by DP sink while using
DSC.In cases where PCON with HDMI2.1 as branch device, if PCON supports
DSC but HDMI2.1 sink does not supports DSC, The PCON tries to use same
input BPC that is used between Source and the PCON without DSC, which
might not work even with the maximum FRL rate supported by HDMI2.1
sink.
This patch calculates the max BPC that can be sufficient with either
RGB or YCBCR420 format for the maximum FRL rate supported.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 90 -
1 file changed, 89 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 8ccbe591b9e2..f0a62f71904e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -117,6 +117,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
+static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp);
static bool
is_dfp_hdmi_sink_dsc_1_2(struct intel_dp *intel_dp)
@@ -1455,6 +1456,74 @@ static int intel_dp_dsc_compute_params(struct
intel_encoder *encoder,
return drm_dsc_compute_rc_parameters(vdsc_cfg);
}
+static int
+_intel_dp_pcon_hdmi21_get_bpp_nodsc(struct intel_dp *intel_dp,
+ const struct drm_display_mode
*adjusted_mode,
+ int max_bpc, bool is_ycbcr420)
+{
+ struct intel_connector *intel_connector = intel_dp->attached_connector;
+ struct drm_connector *connector = &intel_connector->base;
+ int i, num_bpc;
+ u8 dsc_bpc[3] = {0};
+ int req_rate_gbps;
+ int max_frl_rate = connector->display_info.hdmi.max_lanes *
+ connector->display_info.hdmi.max_frl_rate_per_lane;
+
+ /*
+* Currently DSC with Ycbcr420 is not supported. So for modes with
Ycbcr420,
+* DSC will use RGB and support for RGB->YCBCR444->YCBCR420 conversion
is
+* required from DP HDMI2.1 PCON.
+*/
+ if (is_ycbcr420 && !(intel_dp->dfp.rgb_to_ycbcr ||
intel_dp->dfp.ycbcr_444_to_420))
+ return 0;
+
+ num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
+ dsc_bpc);
+ for (i = 0; i < num_bpc; i++) {
+ if (dsc_bpc[i] > max_bpc)
+ continue;
+
+ req_rate_gbps = DIV_ROUND_UP(dsc_bpc[i] * 3 *
adjusted_mode->clock, 100);
+
+ /* YCBCR420 reduces data rate by 2 */
+ if (is_ycbcr420)
+ req_rate_gbps /= 2;
+
+ if (req_rate_gbps < max_frl_rate)
+ return dsc_bpc[i] * 3;
+ }
+
+ return 0;
+}
+
+static int
+intel_dp_pcon_hdmi21_get_bpp_nodsc(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ int max_bpc)
+{
+ const struct drm_display_mode *adjusted_mode =
+ &pipe_config->hw.adjusted_mode;
+ struct intel_connector *connector = intel_dp->attached_connector;
+ const struct drm_display_info *info = &connector->base.display_info;
+ bool is_ycbcr420 = drm_mode_is_420_only(info, adjusted_mode);
+ int pipe_bpp;
+
+ pipe_bpp = _intel_dp_pcon_hdmi21_get_bpp_nodsc(intel_dp, adjusted_mode,
+ max_bpc, is_ycbcr420);
+ if (!pipe_bpp && !is_ycbcr420 && drm_mode_is_420_also(info,
adjusted_mode)) {
+ is_ycbcr420 = true;
+ pipe_bpp = _intel_dp_pcon_hdmi21_get_bpp_nodsc(intel_dp,
adjusted_mode,
+ max_bpc,
is_ycbcr420);
+ }
+
+ if (!pipe_bpp && is_ycbcr420) {
+ pipe_config->dp_dfp_config.rgb_to_ycbcr = true;
+ pipe_config->dp_dfp_config.ycbcr_444_to_420 = true;
+ }
+
+ return pipe_bpp;
+}
+
static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -1473,7 +1542,26 @@ static int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
conn_state->max_requested_bpc);
+ /*
+* In cases where PCON with HDMI2.1 as branch device, if PCON supports
+* DSC but HDMI2.1 sink does not supports DSC, The PCON tries to use
same
+* input DSC bpc that is used between Source and PCON with Ycbcr420
+* format.
+* So use the max BPC that will be sufficient
[Intel-gfx] [PATCH 1/5] drm/i915/dp: Add helper to check DSC1.2 for HDMI2.1 DFP
Add helper function to check if Downstream HDMI 2.1 sink supports
DSC1.2.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 32292c0be2bd..fdf82373a22d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -118,6 +118,15 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
+static bool
+is_dfp_hdmi_sink_dsc_1_2(struct intel_dp *intel_dp)
+{
+ struct intel_connector *intel_connector = intel_dp->attached_connector;
+ struct drm_connector *connector = &intel_connector->base;
+
+ return connector->display_info.hdmi.dsc_cap.v_1p2;
+}
+
/* Is link rate UHBR and thus 128b/132b? */
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
{
@@ -2393,7 +2402,7 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp
*intel_dp)
rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
max_frl_rate = max_lanes * rate_per_lane;
- if (connector->display_info.hdmi.dsc_cap.v_1p2) {
+ if (is_dfp_hdmi_sink_dsc_1_2(intel_dp)) {
max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
dsc_rate_per_lane =
connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
if (max_dsc_lanes && dsc_rate_per_lane)
@@ -2605,7 +2614,7 @@ intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
if (!intel_connector)
return;
connector = &intel_connector->base;
- hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
+ hdmi_is_dsc_1_2 = is_dfp_hdmi_sink_dsc_1_2(intel_dp);
if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
!hdmi_is_dsc_1_2)
--
2.25.1
[Intel-gfx] [PATCH 3/5] drm/i915/dp: Fix DFP RGB->YCBCR conversion
The decision to use DFP output format conversion capabilities should be
during compute_config phase.
This patch:
-uses the members of intel_dp->dfp to only store the
format conversion capabilities of the DP device.
-adds new members to crtc_state to help configure the DFP
output related conversions.
-pulls the decision making to use DFP conversion capabilities
for every mode during compute config.
Signed-off-by: Ankit Nautiyal
---
.../drm/i915/display/intel_display_types.h| 7 ++
drivers/gpu/drm/i915/display/intel_dp.c | 88 +++
2 files changed, 59 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0da9b208d56e..065ed19a5dd3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1311,6 +1311,12 @@ struct intel_crtc_state {
/* for loading single buffered registers during vblank */
struct drm_vblank_work vblank_work;
+
+ /* DP DFP color configuration */
+ struct {
+ bool rgb_to_ycbcr;
+ bool ycbcr_444_to_420;
+ } dp_dfp_config;
};
enum intel_pipe_crc_source {
@@ -1704,6 +1710,7 @@ struct intel_dp {
int pcon_max_frl_bw;
u8 max_bpc;
bool ycbcr_444_to_420;
+ bool ycbcr420_passthrough;
bool rgb_to_ycbcr;
} dfp;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index fc082a933d59..8ccbe591b9e2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1201,19 +1201,21 @@ static bool intel_dp_supports_dsc(struct intel_dp
*intel_dp,
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
}
-static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
-const struct intel_crtc_state *crtc_state)
+static bool intel_dp_is_ycbcr420(const struct intel_crtc_state *crtc_state)
{
return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
(crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
-intel_dp->dfp.ycbcr_444_to_420);
+crtc_state->dp_dfp_config.ycbcr_444_to_420) ||
+ (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB &&
+crtc_state->dp_dfp_config.ycbcr_444_to_420 &&
+crtc_state->dp_dfp_config.rgb_to_ycbcr);
}
static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
int bpc, bool respect_downstream_limits)
{
- bool ycbcr420_output = intel_dp_is_ycbcr420(intel_dp, crtc_state);
+ bool ycbcr420_output = intel_dp_is_ycbcr420(crtc_state);
int clock = crtc_state->hw.adjusted_mode.crtc_clock;
/*
@@ -1966,6 +1968,30 @@ static bool intel_dp_has_audio(struct intel_encoder
*encoder,
return intel_conn_state->force_audio == HDMI_AUDIO_ON;
}
+static void
+intel_dp_compute_dfp_ycbcr420(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ if (!drm_dp_is_branch(intel_dp->dpcd))
+ return;
+
+ /* Mode is YCBCR420, output_format is also YCBCR420: Passthrough */
+ if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ return;
+
+ /* Mode is YCBCR420, output_format is YCBCR444: Downsample */
+ if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
+ crtc_state->dp_dfp_config.ycbcr_444_to_420 = true;
+ return;
+ }
+
+ /* Mode is YCBCR420, output_format is RGB: Convert to YCBCR444 and
Downsample */
+ crtc_state->dp_dfp_config.rgb_to_ycbcr = true;
+ crtc_state->dp_dfp_config.ycbcr_444_to_420 = true;
+}
+
static int
intel_dp_compute_output_format(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
@@ -1984,7 +2010,10 @@ intel_dp_compute_output_format(struct intel_encoder
*encoder,
crtc_state->output_format = intel_dp_output_format(connector,
ycbcr_420_only);
- if (ycbcr_420_only && !intel_dp_is_ycbcr420(intel_dp, crtc_state)) {
+ if (ycbcr_420_only)
+ intel_dp_compute_dfp_ycbcr420(encoder, crtc_state);
+
+ if (ycbcr_420_only && !intel_dp_is_ycbcr420(crtc_state)) {
drm_dbg_kms(&i915->drm,
"YCbCr 4:2:0 mode but YCbCr 4:2:0 output not
possible. Falling back to RGB.\n");
crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
@@ -1993,12 +2022,13 @@ intel_dp_compute_output_format(struct intel_encoder
*encoder,
ret = intel_dp_compute_link_config(encoder, crtc_state, conn
[Intel-gfx] [PATCH 0/5] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes
This series fixes issues faced when HDMI2.1 sink connected via HDMI2.1 PCON does not support DSC, and other minor HDMI2.1 PCON fixes/refactoring. Patch 1 Adds helper to check HDMI2.1 DSC1.2 Patch 2 resets 'frl trained' flag before restarting FRL training. Patch 3 Pulls the decision making to use DFP conversion capabilities for every mode during compute config, instead of having that decision during DP initializing phase. Patch 4-5 calculate the max BPC that can be sufficient with either RGB or YCbcr420 format for the maximum FRL rate supported. Ankit Nautiyal (5): drm/i915/dp: Add helper to check DSC1.2 for HDMI2.1 DFP drm/i915/dp: Reset frl trained flag before restarting FRL training drm/i915/dp: Fix DFP RGB->YCBCR conversion drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP .../drm/i915/display/intel_display_types.h| 7 + drivers/gpu/drm/i915/display/intel_dp.c | 245 ++ 2 files changed, 200 insertions(+), 52 deletions(-) -- 2.25.1
Re: [Intel-gfx] [PATCH 1/2] drm/i915/dsc/mtl: Update the DSC minor version
On Mon, 22 Aug 2022, "Nautiyal, Ankit K" wrote: > On 8/22/2022 3:32 PM, Jani Nikula wrote: >> On Mon, 22 Aug 2022, "Nautiyal, Ankit K" wrote: >>> LGTM. >>> >>> Reviewed-by: Ankit Nautiyal >> Thanks; does this apply to both patches? > > I have given RB on the other patch separately. Thanks, both pushed to drm-intel-next. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 1/2] drm/i915/dsc/mtl: Update the DSC minor version
On 8/22/2022 3:32 PM, Jani Nikula wrote:
On Mon, 22 Aug 2022, "Nautiyal, Ankit K" wrote:
LGTM.
Reviewed-by: Ankit Nautiyal
Thanks; does this apply to both patches?
I have given RB on the other patch separately.
Regards,
Ankit
BR,
Jani.
On 8/17/2022 6:15 PM, Jani Nikula wrote:
From: Vandita Kulkarni
From MTL onwards we support DSC1.2, since there is hardcoding
to minor version 1, update it.
Cc: Ankit Nautiyal
Signed-off-by: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 32292c0be2bd..db5f536bde05 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1377,7 +1377,18 @@ static int intel_dp_dsc_compute_bpp(struct intel_dp
*intel_dp, u8 max_req_bpc)
return 0;
}
-#define DSC_SUPPORTED_VERSION_MIN 1
+static int intel_dp_source_dsc_version_minor(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+ return DISPLAY_VER(i915) >= 14 ? 2 : 1;
+}
+
+static int intel_dp_sink_dsc_version_minor(struct intel_dp *intel_dp)
+{
+ return (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK)
>>
+ DP_DSC_MINOR_SHIFT;
+}
static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
@@ -1416,9 +1427,8 @@ static int intel_dp_dsc_compute_params(struct
intel_encoder *encoder,
(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
vdsc_cfg->dsc_version_minor =
- min(DSC_SUPPORTED_VERSION_MIN,
- (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
-DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
+ min(intel_dp_source_dsc_version_minor(intel_dp),
+ intel_dp_sink_dsc_version_minor(intel_dp));
vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
DP_DSC_RGB;
Re: [Intel-gfx] [PATCH 2/2] drm/i915/dsc/mtl: Enable alternate ICH method
LGTM.
Reviewed-by: Ankit Nautiyal
On 8/17/2022 6:15 PM, Jani Nikula wrote:
From: Vandita Kulkarni
DSC 1.2 is supported from MTL, hence program ICH accordingly.
Cc: Ankit Nautiyal
Signed-off-by: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 43e1bbc1e303..ac4ba7ac85c6 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -597,6 +597,8 @@ static void intel_dsc_pps_configure(const struct
intel_crtc_state *crtc_state)
DSC_VER_MIN_SHIFT |
vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
+ if (vdsc_cfg->dsc_version_minor == 2)
+ pps_val |= DSC_ALT_ICH_SEL;
if (vdsc_cfg->block_pred_enable)
pps_val |= DSC_BLOCK_PREDICTION;
if (vdsc_cfg->convert_rgb)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 50d7bfd541ad..2e3aa684cf1b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8003,6 +8003,7 @@ enum skl_power_gate {
#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)_MMIO_PIPE((pipe) -
PIPE_B, \
_ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
+#define DSC_ALT_ICH_SEL (1 << 20)
#define DSC_VBR_ENABLE (1 << 19)
#define DSC_422_ENABLE (1 << 18)
#define DSC_COLOR_SPACE_CONVERSION (1 << 17)
Re: [Intel-gfx] [PATCH 1/2] drm/i915/dsc/mtl: Update the DSC minor version
On Mon, 22 Aug 2022, "Nautiyal, Ankit K" wrote:
> LGTM.
>
> Reviewed-by: Ankit Nautiyal
Thanks; does this apply to both patches?
BR,
Jani.
>
> On 8/17/2022 6:15 PM, Jani Nikula wrote:
>> From: Vandita Kulkarni
>>
>> From MTL onwards we support DSC1.2, since there is hardcoding
>> to minor version 1, update it.
>>
>> Cc: Ankit Nautiyal
>> Signed-off-by: Vandita Kulkarni
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/display/intel_dp.c | 18 ++
>> 1 file changed, 14 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 32292c0be2bd..db5f536bde05 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -1377,7 +1377,18 @@ static int intel_dp_dsc_compute_bpp(struct intel_dp
>> *intel_dp, u8 max_req_bpc)
>> return 0;
>> }
>>
>> -#define DSC_SUPPORTED_VERSION_MIN 1
>> +static int intel_dp_source_dsc_version_minor(struct intel_dp *intel_dp)
>> +{
>> +struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>> +
>> +return DISPLAY_VER(i915) >= 14 ? 2 : 1;
>> +}
>> +
>> +static int intel_dp_sink_dsc_version_minor(struct intel_dp *intel_dp)
>> +{
>> +return (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
>> DP_DSC_MINOR_MASK) >>
>> +DP_DSC_MINOR_SHIFT;
>> +}
>>
>> static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
>> struct intel_crtc_state *crtc_state)
>> @@ -1416,9 +1427,8 @@ static int intel_dp_dsc_compute_params(struct
>> intel_encoder *encoder,
>> (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
>> DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
>> vdsc_cfg->dsc_version_minor =
>> -min(DSC_SUPPORTED_VERSION_MIN,
>> -(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
>> - DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
>> +min(intel_dp_source_dsc_version_minor(intel_dp),
>> +intel_dp_sink_dsc_version_minor(intel_dp));
>>
>> vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP
>> - DP_DSC_SUPPORT] &
>> DP_DSC_RGB;
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 1/2] drm/i915/dsc/mtl: Update the DSC minor version
LGTM.
Reviewed-by: Ankit Nautiyal
On 8/17/2022 6:15 PM, Jani Nikula wrote:
From: Vandita Kulkarni
From MTL onwards we support DSC1.2, since there is hardcoding
to minor version 1, update it.
Cc: Ankit Nautiyal
Signed-off-by: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 32292c0be2bd..db5f536bde05 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1377,7 +1377,18 @@ static int intel_dp_dsc_compute_bpp(struct intel_dp
*intel_dp, u8 max_req_bpc)
return 0;
}
-#define DSC_SUPPORTED_VERSION_MIN 1
+static int intel_dp_source_dsc_version_minor(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+ return DISPLAY_VER(i915) >= 14 ? 2 : 1;
+}
+
+static int intel_dp_sink_dsc_version_minor(struct intel_dp *intel_dp)
+{
+ return (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK)
>>
+ DP_DSC_MINOR_SHIFT;
+}
static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
@@ -1416,9 +1427,8 @@ static int intel_dp_dsc_compute_params(struct
intel_encoder *encoder,
(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
vdsc_cfg->dsc_version_minor =
- min(DSC_SUPPORTED_VERSION_MIN,
- (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
-DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
+ min(intel_dp_source_dsc_version_minor(intel_dp),
+ intel_dp_sink_dsc_version_minor(intel_dp));
vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
DP_DSC_RGB;
[Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path
Whenever we are not able to get enough timeslots
for required PBN, let's try to allocate those
using DSC, just same way as we do for SST.
v2: Removed intel_dp_mst_dsc_compute_config and refactored
intel_dp_dsc_compute_config to support timeslots as a
parameter(Ville Syrjälä)
v3: - Rebased
- Added a debug to see that we at least try reserving
VCPI slots using DSC, because currently its not visible
from the logs, thus making debugging more tricky.
- Moved timeslots to numerator, where it should be.
v4: - Call drm_dp_mst_atomic_check already during link
config computation, because we need to know already
by this moment if uncompressed amount of VCPI slots
needed can fit, otherwise we need to use DSC.
(thanks to Vinod Govindapillai for pointing this out)
v5: - Put pipe_config->bigjoiner_pipes back to original
condition in intel_dp_dsc_compute_config
(don't remember when I lost it)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 73 -
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 157
3 files changed, 205 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 32292c0be2bd..519b436fc530 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -116,7 +116,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
}
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
/* Is link rate UHBR and thus 128b/132b? */
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
@@ -687,11 +686,12 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
return 6144 * 8;
}
-static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- u32 pipe_bpp)
+u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ u32 pipe_bpp,
+ u32 timeslots)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
int i;
@@ -702,8 +702,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
* for SST -> TimeSlotsPerMTP is 1,
* for MST -> TimeSlotsPerMTP has to be calculated
*/
- bits_per_pixel = (link_clock * lane_count * 8) /
+ bits_per_pixel = (link_clock * lane_count * 8) * timeslots /
intel_dp_mode_to_fec_clock(mode_clock);
+ drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
@@ -752,9 +753,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
return bits_per_pixel << 4;
}
-static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
- int mode_clock, int mode_hdisplay,
- bool bigjoiner)
+u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
+ int mode_clock, int mode_hdisplay,
+ bool bigjoiner)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 min_slice_count, i;
@@ -961,8 +962,8 @@ intel_dp_mode_valid_downstream(struct intel_connector
*connector,
return MODE_OK;
}
-static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
- int hdisplay, int clock)
+bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
+int hdisplay, int clock)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -1049,7 +1050,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
target_clock,
mode->hdisplay,
bigjoiner,
- pipe_bpp) >> 4;
+ pipe_bpp, 1) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1354,7 +1355,7 @@ intel_dp_compute_link_config_wide(struct intel_dp
[Intel-gfx] [PATCH 1/2] drm: Add missing DP DSC extended capability definitions.
Adding DP DSC register definitions, we might need for further DSC implementation, supporting MST and DP branch pass-through mode. v2: - Fixed checkpatch comment warning v3: - Removed function which is not yet used(Jani Nikula) Signed-off-by: Stanislav Lisovskiy --- include/drm/display/drm_dp.h | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 9e3aff7e68bb..0d05e3172f96 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -239,6 +239,9 @@ #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) +# define DP_DSC_PASS_THROUGH_IS_SUPPORTED (1 << 1) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP(1 << 2) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3) #define DP_DSC_REV 0x061 # define DP_DSC_MAJOR_MASK (0xf << 0) @@ -277,12 +280,15 @@ #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) +# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1) #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ #define DP_DSC_MAX_BITS_PER_PIXEL_HI0x068 /* eDP 1.4 */ # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 +# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK 0x06 +# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY 0x08 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 # define DP_DSC_RGB (1 << 0) @@ -344,11 +350,13 @@ # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) #define DP_DSC_BITS_PER_PIXEL_INC 0x06F +# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f +# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 -# define DP_DSC_BITS_PER_PIXEL_10x4 +# define DP_DSC_BITS_PER_PIXEL_1_1 0x4 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED1 -- 2.24.1.485.gad05a3d8e5
[Intel-gfx] [PATCH 0/2] Add DP MST DSC support to i915
Currently we have only DSC support for DP SST. Stanislav Lisovskiy (2): drm: Add missing DP DSC extended capability definitions. drm/i915: Add DSC support to MST path drivers/gpu/drm/i915/display/intel_dp.c | 73 - drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 157 include/drm/display/drm_dp.h| 10 +- 4 files changed, 214 insertions(+), 43 deletions(-) -- 2.24.1.485.gad05a3d8e5
Re: [Intel-gfx] [PATCHv3] drm/i915/display: add support for dual panel backlight
On Mon, 08 Aug 2022, Arun R Murthy wrote:
> The patch with commit 20f85ef89d94 ("drm/i915/backlight: use unique
> backlight device names") already adds support for dual panel backlight
> but with error prints. Since the patch tried to create the backlight
> device with the same name and upon failure will try with a different
> name it leads to failure logs in dmesg inturn getting caught by CI.
>
> This patch alternately will check if the backlight class of same name
> exists, will use a different name.
Thanks for the patch, pushed to drm-intel-next.
I took the liberty of rewriting the commit message a bit while pushing.
BR,
Jani.
>
> v2: reworked on top of the patch commit 20f85ef89d94
> ("drm/i915/backlight: use unique backlight device names")
> v3: fixed the ref count leak(Jani N)
>
> Signed-off-by: Arun R Murthy
> ---
> .../gpu/drm/i915/display/intel_backlight.c| 26 +--
> 1 file changed, 12 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c
> b/drivers/gpu/drm/i915/display/intel_backlight.c
> index 110fc98ec280..931446413372 100644
> --- a/drivers/gpu/drm/i915/display/intel_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_backlight.c
> @@ -971,26 +971,24 @@ int intel_backlight_device_register(struct
> intel_connector *connector)
> if (!name)
> return -ENOMEM;
>
> - bd = backlight_device_register(name, connector->base.kdev, connector,
> -&intel_backlight_device_ops, &props);
> -
> - /*
> - * Using the same name independent of the drm device or connector
> - * prevents registration of multiple backlight devices in the
> - * driver. However, we need to use the default name for backward
> - * compatibility. Use unique names for subsequent backlight devices as a
> - * fallback when the default name already exists.
> - */
> - if (IS_ERR(bd) && PTR_ERR(bd) == -EEXIST) {
> + bd = backlight_device_get_by_name(name);
> + if (bd) {
> + put_device(&bd->dev);
> + /*
> + * Using the same name independent of the drm device or
> connector
> + * prevents registration of multiple backlight devices in the
> + * driver. However, we need to use the default name for backward
> + * compatibility. Use unique names for subsequent backlight
> devices as a
> + * fallback when the default name already exists.
> + */
> kfree(name);
> name = kasprintf(GFP_KERNEL, "card%d-%s-backlight",
>i915->drm.primary->index,
> connector->base.name);
> if (!name)
> return -ENOMEM;
> -
> - bd = backlight_device_register(name, connector->base.kdev,
> connector,
> -&intel_backlight_device_ops,
> &props);
> }
> + bd = backlight_device_register(name, connector->base.kdev, connector,
> +&intel_backlight_device_ops, &props);
>
> if (IS_ERR(bd)) {
> drm_err(&i915->drm,
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH v2 1/3] drm/i915: Define WD trancoder for i915
From: Suraj Kandpal
Adding WD Types, WD transcoder to enum list and WD Transcoder offsets.
Adding i915 register definitions related to WD transcoder
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_display.h | 6 +
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/i915_reg.h | 139 ++
3 files changed, 146 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index fa5371036239..4e9f22954a41 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -120,6 +120,8 @@ enum transcoder {
TRANSCODER_DSI_1,
TRANSCODER_DSI_A = TRANSCODER_DSI_0,/* legacy DSI */
TRANSCODER_DSI_C = TRANSCODER_DSI_1,/* legacy DSI */
+ TRANSCODER_WD_0,
+ TRANSCODER_WD_1,
I915_MAX_TRANSCODERS
};
@@ -141,6 +143,10 @@ static inline const char *transcoder_name(enum transcoder
transcoder)
return "DSI A";
case TRANSCODER_DSI_C:
return "DSI C";
+ case TRANSCODER_WD_0:
+ return "WD 0";
+ case TRANSCODER_WD_1:
+ return "WD 1";
default:
return "";
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0da9b208d56e..0e94bd430bcb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -79,6 +79,7 @@ enum intel_output_type {
INTEL_OUTPUT_DSI = 9,
INTEL_OUTPUT_DDI = 10,
INTEL_OUTPUT_DP_MST = 11,
+ INTEL_OUTPUT_WD = 12,
};
enum hdmi_force_audio {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf5c39d9f953..e3fced4b9980 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2059,6 +2059,8 @@
#define TRANSCODER_EDP_OFFSET 0x6f000
#define TRANSCODER_DSI0_OFFSET 0x6b000
#define TRANSCODER_DSI1_OFFSET 0x6b800
+#define TRANSCODER_WD0_OFFSET 0x6e000
+#define TRANSCODER_WD1_OFFSET 0x6e800
#define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
#define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
@@ -3831,6 +3833,11 @@
#define PIPE_DSI0_OFFSET 0x7b000
#define PIPE_DSI1_OFFSET 0x7b800
+/* WD 0 and 1 */
+#define PIPE_WD0_OFFSET0x7e000
+#define PIPE_WD1_OFFSET0x7d000
+
+
#define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
#define PIPEFRAME(pipe)_MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
@@ -4495,6 +4502,10 @@
#define _PIPEDSI0CONF 0x7b008
#define _PIPEDSI1CONF 0x7b808
+/* WD 0 and 1 */
+#define _PIPEWD0CONF 0x7e008
+#define _PIPEWD1CONF 0x7d008
+
/* Sprite A control */
#define _DVSACNTR 0x72180
#define DVS_ENABLE REG_BIT(31)
@@ -5720,6 +5731,7 @@
#define GEN8_DE_MISC_IER _MMIO(0x4446c)
#define GEN8_DE_MISC_GSE (1 << 27)
#define GEN8_DE_EDP_PSR (1 << 19)
+#define GEN8_DE_MISC_WD0 (1 << 23)
#define GEN8_PCU_ISR _MMIO(0x444e0)
#define GEN8_PCU_IMR _MMIO(0x444e4)
@@ -8714,6 +8726,133 @@ enum skl_power_gate {
#define DSB_ENABLE (1 << 31)
#define DSB_STATUS (1 << 0)
+#define TGL_ROOT_DEVICE_ID 0x9A00
+#define TGL_ROOT_DEVICE_MASK 0xFF00
+#define TGL_ROOT_DEVICE_SKU_MASK 0xF
+#define TGL_ROOT_DEVICE_SKU_ULX0x2
+#define TGL_ROOT_DEVICE_SKU_ULT0x4
+
+/* Gen12 WD */
+#define _MMIO_WD(tc, wd0, wd1) _MMIO_TRANS((tc) - TRANSCODER_WD_0, \
+ wd0, wd1)
+
+#define WD_TRANS_ENABLE(1 << 31)
+#define WD_TRANS_DISABLE 0
+#define WD_TRANS_ACTIVE(1 << 30)
+
+/* WD transcoder control */
+#define _WD_TRANS_FUNC_CTL_0 0x6e400
+#define _WD_TRANS_FUNC_CTL_1 0x6ec00
+#define WD_TRANS_FUNC_CTL(tc) _MMIO_WD(tc,\
+ _WD_TRANS_FUNC_CTL_0,\
+ _WD_TRANS_FUNC_CTL_1)
+
+#define TRANS_WD_FUNC_ENABLE (1 << 31)
+#define WD_TRIGGERED_CAP_MODE_ENABLE (1 << 30)
+#define START_TRIGGER_FRAME(1 << 29)
+#define STOP_TRIGGER_FRAME (1 << 28)
+#define WD_CTL_POINTER_ETEH(0 << 18)
+#define WD_CTL_POINTER_ETDH(1 << 18)
+#define WD_CTL_POINTER_DTDH(2 << 18)
+#define WD_INPUT_SELECT_MASK (7 << 12)
+#define WD_INPUT_PIPE_A(0 << 12)
+#define WD_INPUT_PIPE_B(5 << 12)
+#define WD_INPUT_PIPE_C(6 << 12)
+#define WD_INPUT_PIPE_D(7 << 12)
+
+#def
[Intel-gfx] [PATCH v2 2/3] drm/i915 : Changing intel_connector iterators
From: Suraj Kandpal
Changing intel_connector iterators as with writeback introduction
not all drm_connector will be embedded within intel_connector.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_display.h | 7 ++---
.../drm/i915/display/intel_display_types.h| 26 ++-
.../drm/i915/display/intel_modeset_setup.c| 16 +---
3 files changed, 40 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 4e9f22954a41..3b9987b5f304 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -52,6 +52,7 @@ struct intel_crtc_state;
struct intel_digital_port;
struct intel_dp;
struct intel_encoder;
+struct intel_connector;
struct intel_initial_plane_config;
struct intel_load_detect_pipe;
struct intel_plane;
@@ -469,16 +470,12 @@ enum hpd_pin {
for_each_if(intel_encoder_can_psr(intel_encoder))
#define for_each_intel_connector_iter(intel_connector, iter) \
- while ((intel_connector =
to_intel_connector(drm_connector_list_iter_next(iter
+ while ((intel_connector = intel_connector_list_iter_next(iter)))
#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list,
base.head) \
for_each_if((intel_encoder)->base.crtc == (__crtc))
-#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
- list_for_each_entry((intel_connector),
&(dev)->mode_config.connector_list, base.head) \
- for_each_if((intel_connector)->base.encoder == (__encoder))
-
#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state,
__i) \
for ((__i) = 0; \
(__i) < (__state)->base.dev->mode_config.num_total_plane && \
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0e94bd430bcb..7a82b7acbaf2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1497,12 +1497,14 @@ struct cxsr_latency {
#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state,
base)
#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
-#define to_intel_connector(x) container_of(x, struct intel_connector, base)
+#define to_intel_wb_connector(x) container_of(x, struct intel_wb_connector,
base)
#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
#define to_intel_plane(x) container_of(x, struct intel_plane, base)
#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
#define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
+#define to_intel_connector(x) (((x->connector_type ==
DRM_MODE_CONNECTOR_WRITEBACK)) ? \
+ NULL : container_of(x, struct intel_connector,
base))
struct intel_hdmi {
i915_reg_t hdmi_reg;
@@ -2068,4 +2070,26 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
}
+static inline struct intel_connector *
+intel_connector_list_iter_next(struct drm_connector_list_iter *iter)
+{
+ struct drm_connector *connector;
+ bool flag = true;
+ /*
+* Skipping connector that are Writeback connector as they will
+* not be embedded in intel connector
+*/
+ while (flag) {
+ connector = drm_connector_list_iter_next(iter);
+ if (connector && !to_intel_connector(connector))
+ continue;
+
+ flag = false;
+
+ if (connector)
+ return to_intel_connector(connector);
+
+ }
+ return NULL;
+}
#endif /* __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index f0e04d3904c6..985dfa5f7aa1 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -204,12 +204,22 @@ static bool intel_crtc_has_encoders(struct intel_crtc
*crtc)
static struct intel_connector *intel_encoder_find_connector(struct
intel_encoder *encoder)
{
- struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_connector *connector;
+ struct drm_connector_list_iter conn_iter;
+ bool found_connector = false;
- for_each_connector_on_encoder(dev, &encoder->base, connector)
- return connector;
+ drm_connector_list_iter_begin(&i915->drm, &conn_iter);
+ for_each_intel_connector_iter(connector, &conn_iter
[Intel-gfx] [PATCH v2 0/3] Enable Pipewriteback
A patch series was floated in the drm mailing list which aimed to change the drm_connector and drm_encoder fields to pointer in the drm_connector_writeback structure, this received a huge pushback from the community but since i915 expects each connector present in the drm_device list to be a intel_connector but drm_writeback framework makes us have a connector which cannot be embedded in an intel_connector structure. [1] https://patchwork.kernel.org/project/dri-devel/patch/20220202081702.22119-1-suraj.kand...@intel.com/ [2] https://patchwork.kernel.org/project/dri-devel/patch/20220202085429.22261-6-suraj.kand...@intel.com/ Since no one had an issue with encoder field being changed into a pointer it was decided to break the connector and encoder pointer changes into two different series.The encoder field changes is currently being worked upon by Abhinav Kumar and the changes have been merged. [3]https://patchwork.kernel.org/project/dri-devel/list/?series=633565 Going forward we use a drm_connector which is not embedded in intel_connector. We also create a intel_encoder to avoid changes to many iterators but no intel_connector. We also changed all iterators that go through connectors and add a check to only cast connectors which are not writeback connectors. I had also floated a previous series to Enable writeback but floating a new one as i created an extra patch in this series as suggested by Jani, Nikula for intel_connector iterator changes. Please go check the below link if interested. [4]https://patchwork.freedesktop.org/series/106902/ v2--- solving BAT issues Suraj Kandpal (3): drm/i915: Define WD trancoder for i915 drm/i915 : Changing intel_connector iterators drm/i915: Enabling WD Transcoder drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_acpi.c | 1 + drivers/gpu/drm/i915/display/intel_crtc.c | 6 + .../drm/i915/display/intel_crtc_state_dump.c | 1 + drivers/gpu/drm/i915/display/intel_ddi.c | 6 + drivers/gpu/drm/i915/display/intel_display.c | 65 +- drivers/gpu/drm/i915/display/intel_display.h | 18 +- .../drm/i915/display/intel_display_debugfs.c | 13 +- .../drm/i915/display/intel_display_types.h| 33 +- drivers/gpu/drm/i915/display/intel_dpll.c | 6 + .../drm/i915/display/intel_modeset_setup.c| 119 ++- .../drm/i915/display/intel_modeset_verify.c | 17 +- drivers/gpu/drm/i915/display/intel_opregion.c | 3 + .../gpu/drm/i915/display/intel_wb_connector.h | 20 + drivers/gpu/drm/i915/display/intel_wd.c | 699 ++ drivers/gpu/drm/i915/display/intel_wd.h | 48 ++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_irq.c | 8 +- drivers/gpu/drm/i915/i915_pci.c | 7 +- drivers/gpu/drm/i915/i915_reg.h | 139 20 files changed, 1156 insertions(+), 55 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_wb_connector.h create mode 100644 drivers/gpu/drm/i915/display/intel_wd.c create mode 100644 drivers/gpu/drm/i915/display/intel_wd.h -- 2.25.1
