✓ Fi.CI.BAT: success for Enable Aux Based EDP HDR
== Series Details == Series: Enable Aux Based EDP HDR URL : https://patchwork.freedesktop.org/series/132009/ State : success == Summary == CI Bug Log - changes from CI_DRM_14522 -> Patchwork_132009v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132009v1/index.html Participating hosts (36 -> 34) -- Additional (2): bat-dg1-7 bat-mtlp-8 Missing(4): fi-cfl-8109u bat-jsl-1 fi-snb-2520m bat-arls-3 Known issues Here are the changes found in Patchwork_132009v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-mtlp-8: NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132009v1/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html * igt@gem_lmem_swapping@basic@lmem0: - bat-dg2-9: [PASS][2] -> [FAIL][3] ([i915#10378]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14522/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132009v1/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html * igt@gem_lmem_swapping@verify-random: - bat-mtlp-8: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132009v1/bat-mtlp-8/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-dg1-7: NOTRUN -> [SKIP][5] ([i915#4083]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132009v1/bat-dg1-7/igt@gem_m...@basic.html - bat-mtlp-8: NOTRUN -> [SKIP][6] ([i915#4083]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132009v1/bat-mtlp-8/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-mtlp-8: NOTRUN -> [SKIP][7] ([i915#4077]) +2 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132009v1/bat-mtlp-8/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-mtlp-8: NOTRUN -> [SKIP][8] ([i915#4079]) +1 other test skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132009v1/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-7: NOTRUN -> [SKIP][9] ([i915#4077]) +2 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132009v1/bat-dg1-7/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-dg1-7: NOTRUN -> [SKIP][10] ([i915#4079]) +1 other test skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132009v1/bat-dg1-7/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-dg1-7: NOTRUN -> [SKIP][11] ([i915#6621]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132009v1/bat-dg1-7/igt@i915_pm_...@basic-api.html - bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#6621]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132009v1/bat-mtlp-8/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy: - bat-dg1-7: NOTRUN -> [SKIP][13] ([i915#4212]) +7 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132009v1/bat-dg1-7/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#5190]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132009v1/bat-mtlp-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][15] ([i915#4212]) +8 other tests skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132009v1/bat-mtlp-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html - bat-dg1-7: NOTRUN -> [SKIP][16] ([i915#4215]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132009v1/bat-dg1-7/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][17] ([i915#4213]) +1 other test skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132009v1/bat-mtlp-8/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html - bat-dg1-7: NOTRUN -> [SKIP][18] ([i915#4103] / [i915#4213]) +1 other test skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132009v1/bat-dg1-7/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_dsc@dsc-basic: - bat-mtlp-8: NOTRUN -> [SKIP][19] ([i915#3555] / [i915#3840] / [i915#9159]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132009v1/bat-mtlp-8/igt@kms_...@dsc-basic.html - bat-dg1-7: NOTRUN -> [SKIP][20] ([i915#3555] / [i915#3840]) [20]:
✗ Fi.CI.SPARSE: warning for Enable Aux Based EDP HDR
== Series Details == Series: Enable Aux Based EDP HDR URL : https://patchwork.freedesktop.org/series/132009/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
[PATCH 7/7] drm/i915/dp: Limit brightness level to 20
Limit minimum brightness to 20 when using aux based brightness
control to avoid letting the screen going completely blank.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 20dd5a6a0f3f..b54ea7e46954 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -211,6 +211,9 @@ intel_dp_aux_hdr_set_aux_backlight(const struct
drm_connector_state *conn_state,
struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
u8 buf[4] = {};
+ if (level < 20)
+ level = 20;
+
buf[0] = level & 0xFF;
buf[1] = (level & 0xFF00) >> 8;
--
2.43.2
[PATCH 6/7] drm/i915/dp: Write panel override luminance values
Write panel override luminance values which helps the TCON decide
if tone mapping needs to be enabled or not.
Signed-off-by: Suraj Kandpal
---
.../drm/i915/display/intel_dp_aux_backlight.c | 25 +++
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 7af876e2d210..20dd5a6a0f3f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -381,6 +381,29 @@ static const char *dpcd_vs_pwm_str(bool aux)
return aux ? "DPCD" : "PWM";
}
+static void
+intel_dp_aux_write_panel_luminance_override(struct intel_connector *connector)
+{
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_panel *panel = >panel;
+ struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
+ int ret;
+ u8 buf[4] = {};
+
+ buf[0] = panel->backlight.min & 0xFF;
+ buf[1] = (panel->backlight.min & 0xFF00) >> 8;
+ buf[2] = panel->backlight.max & 0xFF;
+ buf[3] = (panel->backlight.max & 0xFF00) >> 8;
+
+ ret = drm_dp_dpcd_write(_dp->aux,
+ INTEL_EDP_HDR_PANEL_LUMINANCE_OVERRIDE,
+ buf, sizeof(buf));
+ if (ret < 0)
+ drm_dbg_kms(>drm,
+ "Panel Luminance DPCD reg write failed, err:-%d\n",
+ ret);
+}
+
static int
intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe
pipe)
{
@@ -412,6 +435,8 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector
*connector, enum pipe pi
panel->backlight.min = 0;
}
+ intel_dp_aux_write_panel_luminance_override(connector);
+
drm_dbg_kms(>drm, "[CONNECTOR:%d:%s] Using AUX HDR interface for
backlight control (range %d..%d)\n",
connector->base.base.id, connector->base.name,
panel->backlight.min, panel->backlight.max);
--
2.43.2
[PATCH 5/7] drm/i915/dp: Enable AUX based backlight for HDR
As of now whenerver HDR is switched on we use the PWM to change the
backlight as opposed to AUX based backlight changes in terms of nits.
This patch writes to the appropriate DPCD registers to enable aux
based backlight using values in nits.
--v2
-Fix max_cll and max_fall assignment [Jani]
-Fix the size sent in drm_dpcd_write [Jani]
--v3
-Content Luminance needs to be sent only for pre-ICL after that
it is directly picked up from hdr metadata [Ville]
--v4
-Add checks for HDR TCON cap bits [Ville]
-Check eotf of hdr_output_data and sets bits base of that value.
--v5
-Fix capability check bits.
-Check colorspace before setting BT2020
--v6
-Use intel_dp_has_gamut_dip to check if we have capability
to send sdp [Ville]
-Seprate filling of all hdr tcon related bits into it's
own function.
-Check eotf data to make sure we are in HDR mode [Sebastian]
Signed-off-by: Suraj Kandpal
---
.../drm/i915/display/intel_dp_aux_backlight.c | 105 --
1 file changed, 94 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 2d50a4734823..7af876e2d210 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -40,11 +40,6 @@
#include "intel_dp.h"
#include "intel_dp_aux_backlight.h"
-/* TODO:
- * Implement HDR, right now we just implement the bare minimum to bring us
back into SDR mode so we
- * can make people's backlights work in the mean time
- */
-
/*
* DP AUX registers for Intel's proprietary HDR backlight interface. We define
* them here since we'll likely be the only driver to ever use these.
@@ -127,9 +122,6 @@ intel_dp_aux_supports_hdr_backlight(struct intel_connector
*connector)
if (ret != sizeof(tcon_cap))
return false;
- if (!(tcon_cap[1] & INTEL_EDP_HDR_TCON_BRIGHTNESS_NITS_CAP))
- return false;
-
drm_dbg_kms(>drm, "[CONNECTOR:%d:%s] Detected %s HDR backlight
interface version %d\n",
connector->base.base.id, connector->base.name,
is_intel_tcon_cap(tcon_cap) ? "Intel" : "unsupported",
tcon_cap[0]);
@@ -137,6 +129,9 @@ intel_dp_aux_supports_hdr_backlight(struct intel_connector
*connector)
if (!is_intel_tcon_cap(tcon_cap))
return false;
+ if (!(tcon_cap[1] & INTEL_EDP_HDR_TCON_BRIGHTNESS_NITS_CAP))
+ return false;
+
/*
* If we don't have HDR static metadata there is no way to
* runtime detect used range for nits based control. For now
@@ -225,13 +220,27 @@ intel_dp_aux_hdr_set_aux_backlight(const struct
drm_connector_state *conn_state,
connector->base.base.id, connector->base.name);
}
+static bool
+intel_dp_aux_in_hdr_mode(const struct drm_connector_state *conn_state)
+{
+ struct hdr_output_metadata *hdr_metadata;
+
+ if (!conn_state->hdr_output_metadata)
+ return false;
+
+ hdr_metadata = conn_state->hdr_output_metadata->data;
+
+ return hdr_metadata->hdmi_metadata_type1.eotf !=
HDMI_EOTF_TRADITIONAL_GAMMA_SDR;
+}
+
static void
intel_dp_aux_hdr_set_backlight(const struct drm_connector_state *conn_state,
u32 level)
{
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
struct intel_panel *panel = >panel;
- if (panel->backlight.edp.intel.sdr_uses_aux) {
+ if (intel_dp_aux_in_hdr_mode(conn_state) ||
+ panel->backlight.edp.intel.sdr_uses_aux) {
intel_dp_aux_hdr_set_aux_backlight(conn_state, level);
} else {
const u32 pwm_level = intel_backlight_level_to_pwm(connector,
level);
@@ -240,6 +249,70 @@ intel_dp_aux_hdr_set_backlight(const struct
drm_connector_state *conn_state, u32
}
}
+static void
+intel_dp_aux_write_content_luminance(struct intel_connector *connector,
+struct hdr_output_metadata *hdr_metadata)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ int ret;
+ u8 buf[4];
+
+ if (!intel_dp_has_gamut_metadata_dip(connector->encoder))
+ return;
+
+ buf[0] = hdr_metadata->hdmi_metadata_type1.max_cll & 0xFF;
+ buf[1] = (hdr_metadata->hdmi_metadata_type1.max_cll & 0xFF00) >> 8;
+ buf[2] = hdr_metadata->hdmi_metadata_type1.max_fall & 0xFF;
+ buf[3] = (hdr_metadata->hdmi_metadata_type1.max_fall & 0xFF00) >> 8;
+
+ ret = drm_dp_dpcd_write(_dp->aux,
+ INTEL_EDP_HDR_CONTENT_LUMINANCE,
+ buf, sizeof(buf));
+ if (ret < 0)
+ drm_dbg_kms(>drm,
+ "Content Luminance DPCD reg write failed,
err:-%d\n",
+ ret);
+}
+
+static void
[PATCH 4/7] drm/i915/dp: Fix comments on EDP HDR DPCD registers
Change comments from Pre-TGL+ to Pre-ICL as mentioned in specs Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c index 3d9723714c96..2d50a4734823 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c @@ -69,14 +69,14 @@ #define INTEL_EDP_HDR_GETSET_CTRL_PARAMS 0x344 # define INTEL_EDP_HDR_TCON_2084_DECODE_ENABLEBIT(0) # define INTEL_EDP_HDR_TCON_2020_GAMUT_ENABLE BIT(1) -# define INTEL_EDP_HDR_TCON_TONE_MAPPING_ENABLE BIT(2) /* Pre-TGL+ */ +# define INTEL_EDP_HDR_TCON_TONE_MAPPING_ENABLE BIT(2) /* Pre-ICL */ # define INTEL_EDP_HDR_TCON_SEGMENTED_BACKLIGHT_ENABLEBIT(3) # define INTEL_EDP_HDR_TCON_BRIGHTNESS_AUX_ENABLE BIT(4) # define INTEL_EDP_HDR_TCON_SRGB_TO_PANEL_GAMUT_ENABLEBIT(5) /* Bit 6 is reserved */ # define INTEL_EDP_HDR_TCON_SDP_OVERRIDE_AUX BIT(7) -#define INTEL_EDP_HDR_CONTENT_LUMINANCE0x346 /* Pre-TGL+ */ +#define INTEL_EDP_HDR_CONTENT_LUMINANCE0x346 /* Pre-ICL */ #define INTEL_EDP_HDR_PANEL_LUMINANCE_OVERRIDE 0x34A #define INTEL_EDP_SDR_LUMINANCE_LEVEL 0x352 #define INTEL_EDP_BRIGHTNESS_NITS_LSB 0x354 -- 2.43.2
[PATCH 3/7] drm/i915/dp: Fix Register bit naming
Change INTEL_EDP_HDR_TCON_SDP_COLORIMETRY enable to INTEL_EDP_HDR_TCON_SDP_OVERRIDE_AUX as this bit is tells TCON to ignore DPCD colorimetry values and take the one's sent through SDP. Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c index 94edf982eff8..3d9723714c96 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c @@ -74,7 +74,7 @@ # define INTEL_EDP_HDR_TCON_BRIGHTNESS_AUX_ENABLE BIT(4) # define INTEL_EDP_HDR_TCON_SRGB_TO_PANEL_GAMUT_ENABLEBIT(5) /* Bit 6 is reserved */ -# define INTEL_EDP_HDR_TCON_SDP_COLORIMETRY_ENABLEBIT(7) +# define INTEL_EDP_HDR_TCON_SDP_OVERRIDE_AUX BIT(7) #define INTEL_EDP_HDR_CONTENT_LUMINANCE0x346 /* Pre-TGL+ */ #define INTEL_EDP_HDR_PANEL_LUMINANCE_OVERRIDE 0x34A -- 2.43.2
[PATCH 2/7] drm/i915/dp: Add TCON HDR capability checks
Add checks to see the HDR capability of TCON panel.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_display_types.h| 5 +
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 10 ++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 4ef1f5f709d8..ebee6ebf1fdb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -401,6 +401,11 @@ struct intel_panel {
} vesa;
struct {
bool sdr_uses_aux;
+ bool supports_2084_decode;
+ bool supports_2020_gamut;
+ bool supports_segmented_backlight;
+ bool supports_sdp_colorimetry;
+ bool supports_tone_mapping;
} intel;
} edp;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 4f58efdc688a..94edf982eff8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -158,6 +158,16 @@ intel_dp_aux_supports_hdr_backlight(struct intel_connector
*connector)
panel->backlight.edp.intel.sdr_uses_aux =
tcon_cap[2] & INTEL_EDP_SDR_TCON_BRIGHTNESS_AUX_CAP;
+ panel->backlight.edp.intel.supports_2084_decode =
+ tcon_cap[1] & INTEL_EDP_HDR_TCON_2084_DECODE_CAP;
+ panel->backlight.edp.intel.supports_2020_gamut =
+ tcon_cap[1] & INTEL_EDP_HDR_TCON_2020_GAMUT_CAP;
+ panel->backlight.edp.intel.supports_segmented_backlight =
+ tcon_cap[1] & INTEL_EDP_HDR_TCON_SEGMENTED_BACKLIGHT_CAP;
+ panel->backlight.edp.intel.supports_sdp_colorimetry =
+ tcon_cap[1] & INTEL_EDP_HDR_TCON_SDP_COLORIMETRY_CAP;
+ panel->backlight.edp.intel.supports_tone_mapping =
+ tcon_cap[1] & INTEL_EDP_HDR_TCON_TONE_MAPPING_CAP;
return true;
}
--
2.43.2
[PATCH 1/7] drm/i915/dp: Make has_gamut_metadata_dip() non static
Make has_gamut_metadata_dip() non static so it can also be used to
at other places eg in intel_dp_aux_backlight.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index a11bc4fd3d65..26ccd4cc0d48 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6226,8 +6226,8 @@ bool intel_dp_is_port_edp(struct drm_i915_private *i915,
enum port port)
return _intel_dp_is_port_edp(i915, devdata, port);
}
-static bool
-has_gamut_metadata_dip(struct intel_encoder *encoder)
+bool
+intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum port port = encoder->port;
@@ -6274,7 +6274,7 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct
drm_connector *connect
intel_attach_dp_colorspace_property(connector);
}
- if (has_gamut_metadata_dip(_to_dig_port(intel_dp)->base))
+ if (intel_dp_has_gamut_metadata_dip(_to_dig_port(intel_dp)->base))
drm_connector_attach_hdr_output_metadata_property(connector);
if (HAS_VRR(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index c540d3a73fe7..bbd61cbedc4f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -193,5 +193,6 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp
*intel_dp,
struct link_config_limits *limits);
void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector);
+bool intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder);
#endif /* __INTEL_DP_H__ */
--
2.43.2
[PATCH 0/7] Enable Aux Based EDP HDR
This series enables Aux based EDP HDR and backlight controls. The DPCD written to are intel proprietary and are filled based on the specs that were provided to TCON vendors. Signed-off-by: Suraj Kandpal Suraj Kandpal (7): drm/i915/dp: Make has_gamut_metadata_dip() non static drm/i915/dp: Add TCON HDR capability checks drm/i915/dp: Fix Register bit naming drm/i915/dp: Fix comments on EDP HDR DPCD registers drm/i915/dp: Enable AUX based backlight for HDR drm/i915/dp: Write panel override luminance values drm/i915/dp: Limit brightness level to 20 .../drm/i915/display/intel_display_types.h| 5 + drivers/gpu/drm/i915/display/intel_dp.c | 6 +- drivers/gpu/drm/i915/display/intel_dp.h | 1 + .../drm/i915/display/intel_dp_aux_backlight.c | 149 -- 4 files changed, 144 insertions(+), 17 deletions(-) -- 2.43.2
Re: [PATCH] drm/i915/guc: Fix the fix for reset lock confusion
Hi John,
On Fri, Mar 29, 2024 at 04:53:05PM -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> The previous fix for the circlular lock splat about the busyness
> worker wasn't quite complete. Even though the reset-in-progress flag
> is cleared at the start of intel_uc_reset_finish, the entire function
> is still inside the reset mutex lock. Not sure why the patch appeared
> to fix the issue both locally and in CI. However, it is now back
> again.
>
> There is a further complication the wedge code path within
> intel_gt_reset() jumps around so much it results in nested
> reset_prepare/_finish calls. That is, the call sequence is:
> intel_gt_reset
> | reset_prepare
> | __intel_gt_set_wedged
> | | reset_prepare
> | | reset_finish
> | reset_finish
>
> The nested finish means that even if the clear of the in-progress flag
> was moved to the end of _finish, it would still be clear for the
> entire second call. Surprisingly, this does not seem to be causing any
> other problems at present.
>
> As an aside, a wedge on fini does not call the finish functions at
> all. The reset_in_progress flag is left set (twice).
>
> So instead of trying to cancel the worker anywhere at all in the reset
> path, just add a cancel to intel_guc_submission_fini instead. Note
> that it is not a problem if the worker is still active during a reset.
> Either it will run before the reset path starts locking things and
> will simply block the reset code for a tiny amount of time. Or it will
> run after the locks have been acquired and will early exit due to the
> try-lock.
>
> Also, do not use the reset-in-progress flag to decide whether a
> synchronous cancel is safe (from a lockdep perspective) or not.
> Instead, use the actual reset mutex state (both the genuine one and
> the custom rolled BACKOFF one).
>
> Fixes: 0e00a8814eec ("drm/i915/guc: Avoid circular locking issue on busyness
> flush")
> Signed-off-by: John Harrison
> Cc: Zhanjun Dong
> Cc: John Harrison
> Cc: Andi Shyti
> Cc: Daniel Vetter
> Cc: Daniel Vetter
> Cc: Rodrigo Vivi
> Cc: Nirmoy Das
> Cc: Tvrtko Ursulin
> Cc: Umesh Nerlige Ramappa
> Cc: Andrzej Hajda
> Cc: Matt Roper
> Cc: Jonathan Cavitt
> Cc: Prathap Kumar Valsan
> Cc: Alan Previn
> Cc: Madhumitha Tolakanahalli Pradeep
>
> Cc: Daniele Ceraolo Spurio
> Cc: Ashutosh Dixit
> Cc: Dnyaneshwar Bhadane
Looks good:
Reviewed-by: Andi Shyti
Thanks,
Andi
Re: [PATCH v2 19/25] drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits
On Wed, Apr 03, 2024 at 04:52:47PM +0530, Balasubramani Vivekanandan wrote:
> From: José Roberto de Souza
>
> Xe2_HPD doesn't have DBOX BW credits, so here programing it with
> zero.
>
> BSpec: 49213
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Balasubramani Vivekanandan
>
> ---
> drivers/gpu/drm/i915/display/skl_watermark.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index bc341abcab2f..22ae782e89f4 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3733,7 +3733,7 @@ void intel_mbus_dbox_update(struct intel_atomic_state
> *state)
> if (!new_crtc_state->hw.active)
> continue;
>
> - if (DISPLAY_VER(i915) >= 14) {
> + if (DISPLAY_VER(i915) >= 14 && !IS_BATTLEMAGE(i915)) {
It looks like the "BW Credits" field from MBUS_DBOX_CTL doesn't exist on
any platform past Xe_LPD+. I.e., it isn't there on Xe2_LPD (version 20)
either. So we should probably make this block an exact match on version
14.0 only.
if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0))
so that it doesn't execute on anything else.
Matt
> if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
>
> new_dbuf_state->active_pipes))
> pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [PATCH v2 13/25] drm/i915/xe2hpd: Add display info
On Wed, Apr 03, 2024 at 04:52:41PM +0530, Balasubramani Vivekanandan wrote:
> From: Lucas De Marchi
>
> Add initial display info for xe2hpd. It is similar to xelpd, but with no
> PORT_B.
>
> Bspec: 67066
> Signed-off-by: Lucas De Marchi
> Signed-off-by: Balasubramani Vivekanandan
>
> ---
> .../gpu/drm/i915/display/intel_display_device.c | 16
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index b8903bd0e82a..0a26012041e9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -771,6 +771,21 @@ static const struct intel_display_device_info
> xe2_lpd_display = {
> BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D),
> };
>
> +static const struct intel_display_device_info xe2_hpd_display = {
> + XE_LPD_FEATURES,
Don't we want to derive from XE_LPDP_FEATURES rather than
XE_LPD_FEATURES? If so, that takes care of initializing most of this
structure, aside from port_mask.
> + .has_cdclk_crawl = 1,
> + .has_cdclk_squash = 1,
> +
> + .__runtime_defaults.ip.ver = 14,
> + .__runtime_defaults.ip.rel = 1,
We're not supposed to have version numbers in these structures for
platforms that have GMD_ID (there might not even be just one version
number associated with the IP). The gmdid_display_map[] is the only
place where we need to map one or more version numbers to an info
structure.
Matt
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> + .__runtime_defaults.port_mask = BIT(PORT_A) |
> + BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
> +};
> +
> __diag_pop();
>
> /*
> @@ -852,6 +867,7 @@ static const struct {
> const struct intel_display_device_info *display;
> } gmdid_display_map[] = {
> { 14, 0, _lpdp_display },
> + { 14, 1, _hpd_display },
> { 20, 0, _lpd_display },
> };
>
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [PATCH v2 14/25] drm/i915/xe2hpd: Add missing chicken bit register programming
On Wed, Apr 03, 2024 at 04:52:42PM +0530, Balasubramani Vivekanandan wrote: > From: Anusha Srivatsa > > Add step 9 from initialize display sequence. > > Bpsec: 49189 > Signed-off-by: Anusha Srivatsa > Signed-off-by: Balasubramani Vivekanandan > I think the title here is misleading since "missing" makes it sound like we overlooked something previously, whereas in reality this is just a new required step on Xe2_HPD. A title like "Configure CHICKEN_MISC_2 before enabling planes" would probably be more accurate. With updated wording, Reviewed-by: Matt Roper Matt > --- > drivers/gpu/drm/i915/display/intel_display_power.c | 4 > drivers/gpu/drm/i915/i915_reg.h| 1 + > 2 files changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c > b/drivers/gpu/drm/i915/display/intel_display_power.c > index 6fd4fa52253a..bf9685acf75a 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -1694,6 +1694,10 @@ static void icl_display_core_init(struct > drm_i915_private *dev_priv, > if (IS_DG2(dev_priv)) > intel_snps_phy_wait_for_calibration(dev_priv); > > + /* 9. XE2_HPD: Program CHICKEN_MISC_2 before any cursor or planes are > enabled */ > + if (DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 1)) > + intel_de_rmw(dev_priv, CHICKEN_MISC_2, > BMG_DARB_HALF_BLK_END_BURST, 1); > + > if (resume) > intel_dmc_load_program(dev_priv); > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 58f3e4bfe254..875d76fb8cd0 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4548,6 +4548,7 @@ > > #define CHICKEN_MISC_2 _MMIO(0x42084) > #define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */ > +#define BMG_DARB_HALF_BLK_END_BURSTREG_BIT(27) > #define KBL_ARB_FILL_SPARE_14 REG_BIT(14) > #define KBL_ARB_FILL_SPARE_13 REG_BIT(13) > #define GLK_CL2_PWR_DOWN REG_BIT(12) > -- > 2.25.1 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
Re: [PATCH v2 12/25] drm/i915/xe2hpd: update pll values in sync with Bspec
On Wed, Apr 03, 2024 at 04:52:40PM +0530, Balasubramani Vivekanandan wrote:
> From: Ravi Kumar Vodapalli
>
> DP/eDP and HDMI pll values are updated for Xe2_HPD platform
>
> Bspec: 74165
> Signed-off-by: Ravi Kumar Vodapalli
> Signed-off-by: Balasubramani Vivekanandan
>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 47 +++-
> 1 file changed, 45 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index d948035f07ad..20035be015c3 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -1109,6 +1109,42 @@ static const struct intel_c20pll_state * const
> xe2hpd_c20_edp_tables[] = {
> NULL,
> };
>
> +static const struct intel_c20pll_state xe2hpd_c20_dp_uhbr13_5 = {
> + .clock = 135, /* 13.5 Gbps */
> + .tx = { 0xbea0, /* tx cfg0 */
> + 0x4800, /* tx cfg1 */
> + 0x, /* tx cfg2 */
> + },
> + .cmn = {0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x, /* cmn cfg2 */
> + 0x, /* cmn cfg3 */
> + },
> + .mpllb = { 0x015f, /* mpllb cfg0 */
> + 0x2205, /* mpllb cfg1 */
> + 0x1b17, /* mpllb cfg2 */
> + 0xffc1, /* mpllb cfg3 */
> + 0xbd00, /* mpllb cfg4 */
> + 0x9ec3, /* mpllb cfg5 */
> + 0x2000, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x4800, /* mpllb cfg8 */
> + 0x, /* mpllb cfg9 */
> + 0x, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state * const xe2hpd_c20_dp_tables[] = {
> + _c20_dp_rbr,
> + _c20_dp_hbr1,
> + _c20_dp_hbr2,
> + _c20_dp_hbr3,
> + _c20_dp_uhbr10,
> + _c20_dp_uhbr13_5,
> + _c20_dp_uhbr20,
According to bspec 67066, I don't think we need the UHBR20 table for
Xe2_HPD (even though there are data values given on page 74165).
Otherwise,
Reviewed-by: Matt Roper
Matt
> + NULL,
> +};
> +
> /*
> * HDMI link rates with 38.4 MHz reference clock.
> */
> @@ -2225,13 +2261,20 @@ static const struct intel_c20pll_state * const *
> intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
>struct intel_encoder *encoder)
> {
> - if (intel_crtc_has_dp_encoder(crtc_state))
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> +
> + if (intel_crtc_has_dp_encoder(crtc_state)) {
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> return xe2hpd_c20_edp_tables;
> +
> + if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
> + return xe2hpd_c20_dp_tables;
> else
> return mtl_c20_dp_tables;
> - else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> +
> + } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> return mtl_c20_hdmi_tables;
> + }
>
> MISSING_CASE(encoder->type);
> return NULL;
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [PATCH v2 11/25] drm/i915/xe2hpd: Add support for eDP PLL configuration
On Wed, Apr 03, 2024 at 04:52:39PM +0530, Balasubramani Vivekanandan wrote:
> Tables for eDP PHY PLL configuration for different link rates added for
> Xe2_HPD. Previous platforms were using C10 PHY for eDP port whereas
> Xe2_HPD has C20 PHY.
>
> Bpsec: 64568
I think 74165 would be more accurate?
Otherwise the tables below match the current spec, so
Reviewed-by: Matt Roper
>
> CC: Clint Taylor
> Signed-off-by: Balasubramani Vivekanandan
>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 147 ++-
> 1 file changed, 146 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 6e4647859fc6..d948035f07ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -967,6 +967,148 @@ static const struct intel_c20pll_state * const
> mtl_c20_dp_tables[] = {
> NULL,
> };
>
> +/*
> + * eDP link rates with 38.4 MHz reference clock.
> + */
> +
> +static const struct intel_c20pll_state xe2hpd_c20_edp_r216 = {
> + .clock = 216000,
> + .tx = { 0xbe88,
> + 0x4800,
> + 0x,
> + },
> + .cmn = { 0x0500,
> + 0x0005,
> + 0x,
> + 0x,
> + },
> + .mpllb = { 0x50e1,
> +0x2120,
> +0x8e18,
> +0xbfc1,
> +0x9000,
> +0x78f6,
> +0x,
> +0x,
> +0x,
> +0x,
> +0x,
> + },
> +};
> +
> +static const struct intel_c20pll_state xe2hpd_c20_edp_r243 = {
> + .clock = 243000,
> + .tx = { 0xbe88,
> + 0x4800,
> + 0x,
> + },
> + .cmn = { 0x0500,
> + 0x0005,
> + 0x,
> + 0x,
> + },
> + .mpllb = { 0x50fd,
> +0x2120,
> +0x8f18,
> +0xbfc1,
> +0xa200,
> +0x8814,
> +0x2000,
> +0x0001,
> +0x1000,
> +0x,
> +0x,
> + },
> +};
> +
> +static const struct intel_c20pll_state xe2hpd_c20_edp_r324 = {
> + .clock = 324000,
> + .tx = { 0xbe88,
> + 0x4800,
> + 0x,
> + },
> + .cmn = { 0x0500,
> + 0x0005,
> + 0x,
> + 0x,
> + },
> + .mpllb = { 0x30a8,
> +0x2110,
> +0xcd9a,
> +0xbfc1,
> +0x6c00,
> +0x5ab8,
> +0x2000,
> +0x0001,
> +0x6000,
> +0x,
> +0x,
> + },
> +};
> +
> +static const struct intel_c20pll_state xe2hpd_c20_edp_r432 = {
> + .clock = 432000,
> + .tx = { 0xbe88,
> + 0x4800,
> + 0x,
> + },
> + .cmn = { 0x0500,
> + 0x0005,
> + 0x,
> + 0x,
> + },
> + .mpllb = { 0x30e1,
> +0x2110,
> +0x8e18,
> +0xbfc1,
> +0x9000,
> +0x78f6,
> +0x,
> +0x,
> +0x,
> +0x,
> +0x,
> + },
> +};
> +
> +static const struct intel_c20pll_state xe2hpd_c20_edp_r675 = {
> + .clock = 675000,
> + .tx = { 0xbe88,
> + 0x4800,
> + 0x,
> + },
> + .cmn = { 0x0500,
> + 0x0005,
> + 0x,
> + 0x,
> + },
> + .mpllb = { 0x10af,
> +0x2108,
> +0xce1a,
> +0xbfc1,
> +0x7080,
> +0x5e80,
> +0x2000,
> +0x0001,
> +0x6400,
> +0x,
> +0x,
> + },
> +};
> +
> +static const struct intel_c20pll_state * const xe2hpd_c20_edp_tables[] = {
> + _c20_dp_rbr,
> + _c20_edp_r216,
> + _c20_edp_r243,
> + _c20_dp_hbr1,
> + _c20_edp_r324,
> + _c20_edp_r432,
> + _c20_dp_hbr2,
> + _c20_edp_r675,
> + _c20_dp_hbr3,
> + NULL,
> +};
> +
> /*
> * HDMI link rates with 38.4 MHz reference clock.
> */
> @@ -2084,7 +2226,10 @@ intel_c20_pll_tables_get(struct intel_crtc_state
> *crtc_state,
>struct intel_encoder *encoder)
> {
> if (intel_crtc_has_dp_encoder(crtc_state))
> - return mtl_c20_dp_tables;
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> + return xe2hpd_c20_edp_tables;
> + else
> + return mtl_c20_dp_tables;
>
Re: [PATCH v2 09/25] drm/i915/xe2hpd: Properly disable power in port A
On Wed, Apr 03, 2024 at 04:52:37PM +0530, Balasubramani Vivekanandan wrote:
> From: José Roberto de Souza
>
> Xe2_HPD has a different value to power down port A.
>
> BSpec: 65450
> CC: Matt Roper
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Balasubramani Vivekanandan
>
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 17 ++---
> 1 file changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 13a2e3db2812..caaae5d3758e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2921,17 +2921,28 @@ void intel_mtl_pll_enable(struct intel_encoder
> *encoder,
> intel_cx0pll_enable(encoder, crtc_state);
> }
>
> +static u8 cx0_power_control_disable_val(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> +
> + if (intel_encoder_is_c10phy(encoder))
> + return CX0_P2PG_STATE_DISABLE;
> +
> + if (IS_BATTLEMAGE(i915) && encoder->port == PORT_A)
> + return CX0_P2PG_STATE_DISABLE;
> +
> + return CX0_P4PG_STATE_DISABLE;
> +}
> +
> static void intel_cx0pll_disable(struct intel_encoder *encoder)
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> enum phy phy = intel_encoder_to_phy(encoder);
> - bool is_c10 = intel_encoder_is_c10phy(encoder);
> intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);
>
> /* 1. Change owned PHY lane power to Disable state. */
> intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
> - is_c10 ? CX0_P2PG_STATE_DISABLE :
> - CX0_P4PG_STATE_DISABLE);
> +
> cx0_power_control_disable_val(encoder));
>
> /*
>* 2. Follow the Display Voltage Frequency Switching Sequence Before
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [PATCH v2 08/25] drm/i915/bmg: Extend DG2 tc check to future
On Wed, Apr 03, 2024 at 04:52:36PM +0530, Balasubramani Vivekanandan wrote:
> From: Radhakrishna Sripada
>
> Discrete cards use the Port numbers TC1-4 for the offsets. The regular
> flow for type-c subsystem port initialization can be skipped. This check
> is present in DG2. Extend this to future discrete products.
>
> Signed-off-by: Radhakrishna Sripada
> Signed-off-by: Balasubramani Vivekanandan
>
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 614e60420a29..aed25890b6f5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1861,11 +1861,10 @@ bool intel_phy_is_combo(struct drm_i915_private
> *dev_priv, enum phy phy)
> bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
> {
> /*
> - * DG2's "TC1", although TC-capable output, doesn't share the same flow
> - * as other platforms on the display engine side and rather rely on the
> - * SNPS PHY, that is programmed separately
> + * Discrete GPU phy's are not attached to FIA's to support TC
> + * subsystem Legacy or non-legacy, and only support native DP/HDMI
>*/
> - if (IS_DG2(dev_priv))
> + if (IS_DGFX(dev_priv))
> return false;
>
> if (DISPLAY_VER(dev_priv) >= 13)
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [PATCH v2 07/25] Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping"
On Wed, Apr 03, 2024 at 04:52:35PM +0530, Balasubramani Vivekanandan wrote:
> From: Ankit Nautiyal
>
> This reverts commit 562f33836f519a235e5c5e71bcc723ab1faccd2f.
> For BMG it seems that the VBT to DDI mapping does not follow DG1, and
> DG2, but follows ADLP mapping given in Bspec:20124.
>
> Signed-off-by: Ankit Nautiyal
> Signed-off-by: Balasubramani Vivekanandan
>
Matches our experimental findings, so
Reviewed-by: Matt Roper
I've pinged the internal ticket to try to get the documentation for this
clarified.
BTW, if you send another version of this series it might make more sense
to re-order this to be after patch #20, since that's where we define
which south display (i.e., "fake pch") is used on BMG.
Matt
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 2abd2d7ceda2..03fbd6c73f3f 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2238,15 +2238,14 @@ static u8 map_ddc_pin(struct drm_i915_private *i915,
> u8 vbt_pin)
> const u8 *ddc_pin_map;
> int i, n_entries;
>
> - if (IS_DGFX(i915))
> - return vbt_pin;
> -
> if (INTEL_PCH_TYPE(i915) >= PCH_MTL || IS_ALDERLAKE_P(i915)) {
> ddc_pin_map = adlp_ddc_pin_map;
> n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
> } else if (IS_ALDERLAKE_S(i915)) {
> ddc_pin_map = adls_ddc_pin_map;
> n_entries = ARRAY_SIZE(adls_ddc_pin_map);
> + } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
> + return vbt_pin;
> } else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) {
> ddc_pin_map = rkl_pch_tgp_ddc_pin_map;
> n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [PATCH v2 06/25] drm/i915/xe2hpd: Initial cdclk table
On Wed, Apr 03, 2024 at 04:52:34PM +0530, Balasubramani Vivekanandan wrote:
> From: Clint Taylor
>
> Add Xe2_HPD specific CDCLK table and use MTL Funcs.
>
> Bspec: 65243
> Cc: Matt Roper
> CC: Lucas De Marchi
> Signed-off-by: Clint Taylor
> Signed-off-by: Balasubramani Vivekanandan
>
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 31aaa9780dfc..da16c308670f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1444,6 +1444,14 @@ static const struct intel_cdclk_vals
> xe2lpd_cdclk_table[] = {
> {}
> };
>
> +/*
> + * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771
> + */
> +static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = {
> + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x },
> + {}
> +};
> +
> static const int cdclk_squash_len = 16;
>
> static int cdclk_squash_divider(u16 waveform)
> @@ -3768,6 +3776,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private
> *dev_priv)
> if (DISPLAY_VER(dev_priv) >= 20) {
> dev_priv->display.funcs.cdclk = _cdclk_funcs;
> dev_priv->display.cdclk.table = xe2lpd_cdclk_table;
> + } else if (DISPLAY_VER_FULL(dev_priv) >= IP_VER(14, 1)) {
> + dev_priv->display.funcs.cdclk = _cdclk_funcs;
> + dev_priv->display.cdclk.table = xe2hpd_cdclk_table;
> } else if (DISPLAY_VER(dev_priv) >= 14) {
> dev_priv->display.funcs.cdclk = _cdclk_funcs;
> dev_priv->display.cdclk.table = mtl_cdclk_table;
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [PATCH v2 05/25] drm/i915/xe2: Skip CCS modifiers for Xe2 platforms
On Wed, Apr 03, 2024 at 04:52:33PM +0530, Balasubramani Vivekanandan wrote:
> Xe2 platforms doesn't support Aux CCS and the Flat CCS is enabled
> through PAT. No CCS modifiers required for Xe2 platforms.
The change looks correct, but you might want to elaborate on this
description a bit to help clarify why having the compression status of a
buffer in the page table entries (via PAT) allows us to avoid the need
for dedicated framebuffer modifiers.
Matt
>
> Signed-off-by: Balasubramani Vivekanandan
>
> ---
> drivers/gpu/drm/i915/display/intel_fb.c | 14 +++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
> b/drivers/gpu/drm/i915/display/intel_fb.c
> index 3ea6470d6d92..923e97c3aa6c 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -431,9 +431,17 @@ static bool plane_has_modifier(struct drm_i915_private
> *i915,
>* Separate AuxCCS and Flat CCS modifiers to be run only on platforms
>* where supported.
>*/
> - if (intel_fb_is_ccs_modifier(md->modifier) &&
> - HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes)
> - return false;
> + if (intel_fb_is_ccs_modifier(md->modifier)) {
> + /*
> + * No CCS modifiers available on Xe2 platforms as they don't
> + * support Aux CCS and the Flat CCS is enabled via PAT
> + */
> + if ((DISPLAY_VER(i915) >= 20) || IS_BATTLEMAGE(i915))
> + return false;
> +
> + if (HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes)
> + return false;
> + }
>
> return true;
> }
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [PATCH] drm/xe/display: fix potential overflow when multiplying 2 u32
On Wed, Apr 03, 2024 at 03:39:19PM +, Murthy, Arun R wrote:
> Gentle Reminder!
Thanks for your patch. I'm convinced we really need something like this.
At least to shout the static analyzers.
Or this or using the mul_u32_u32 or casting one of the right operands,
otherwise the
result of the multiplication of a 32 vs 32 can overflow the 32 bits
before it is then moved to the u64 at the left. And this is undefined
behavior depending on the compiler and all.
But the commit message mentioning 'overflow' as it is kind of suggests
a true overflow issue on the result itself and a protection against that,
what is not true and likely kept the reviewers away from this patch.
Some commit message update like Himal did here [1] would be appreciated.
[1] https://patchwork.freedesktop.org/patch/586036/?series=131896=1
>
> Thanks and Regards,
> Arun R Murthy
>
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of
> > Murthy,
> > Arun R
> > Sent: Thursday, March 28, 2024 10:34 AM
> > To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> > Subject: RE: [PATCH] drm/xe/display: fix potential overflow when
> > multiplying 2
> > u32
> >
> > Any comments?
> >
> > Thanks and Regards,
> > Arun R Murthy
> >
> >
> > > -Original Message-
> > > From: Murthy, Arun R
> > > Sent: Monday, March 18, 2024 4:31 PM
> > > To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> > > Cc: Murthy, Arun R
> > > Subject: [PATCH] drm/xe/display: fix potential overflow when
> > > multiplying 2 u32
> > >
> > > Multiplying XE_PAGE_SIZE with another u32 and the product stored in
> > > u64 can potentially lead to overflow, use mul_u32_u32 instead.
> > >
> > > Signed-off-by: Arun R Murthy
> > > ---
> > > drivers/gpu/drm/xe/display/xe_fb_pin.c | 10 +-
> > > 1 file changed, 5 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c
> > > b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> > > index 722c84a56607..e0b511ff7eab 100644
> > > --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
> > > +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> > > @@ -29,7 +29,7 @@ write_dpt_rotated(struct xe_bo *bo, struct iosys_map
> > > *map, u32 *dpt_ofs, u32 bo_
> > > u32 src_idx = src_stride * (height - 1) + column + bo_ofs;
> > >
> > > for (row = 0; row < height; row++) {
> > > - u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx *
> > > XE_PAGE_SIZE,
> > > + u64 pte = ggtt->pt_ops->pte_encode_bo(bo,
> > > mul_u32_u32(src_idx,
> > > +XE_PAGE_SIZE),
> > > xe-
> > > >pat.idx[XE_CACHE_WB]);
> > >
> > > iosys_map_wr(map, *dpt_ofs, u64, pte); @@ -61,7
> > > +61,7 @@ write_dpt_remapped(struct xe_bo *bo, struct iosys_map *map,
> > > +u32
> > > *dpt_ofs,
> > >
> > > for (column = 0; column < width; column++) {
> > > iosys_map_wr(map, *dpt_ofs, u64,
> > > - pte_encode_bo(bo, src_idx * XE_PAGE_SIZE,
> > > + pte_encode_bo(bo, mul_u32_u32(src_idx,
> > > XE_PAGE_SIZE),
> > >xe->pat.idx[XE_CACHE_WB]));
> > >
> > > *dpt_ofs += 8;
> > > @@ -118,7 +118,7 @@ static int __xe_pin_fb_vma_dpt(struct
> > > intel_framebuffer *fb,
> > > u32 x;
> > >
> > > for (x = 0; x < size / XE_PAGE_SIZE; x++) {
> > > - u64 pte = ggtt->pt_ops->pte_encode_bo(bo, x *
> > > XE_PAGE_SIZE,
> > > + u64 pte = ggtt->pt_ops->pte_encode_bo(bo,
> > > mul_u32_u32(x,
> > > +XE_PAGE_SIZE),
> > > xe-
> > > >pat.idx[XE_CACHE_WB]);
> > >
> > > iosys_map_wr(>vmap, x * 8, u64, pte); @@ -
> > > 164,7 +164,7 @@ write_ggtt_rotated(struct xe_bo *bo, struct xe_ggtt
> > > *ggtt,
> > > u32 *ggtt_ofs, u32 bo
> > > u32 src_idx = src_stride * (height - 1) + column + bo_ofs;
> > >
> > > for (row = 0; row < height; row++) {
> > > - u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx *
> > > XE_PAGE_SIZE,
> > > + u64 pte = ggtt->pt_ops->pte_encode_bo(bo,
> > > mul_u32_u32(src_idx,
> > > +XE_PAGE_SIZE),
> > > xe-
> > > >pat.idx[XE_CACHE_WB]);
> > >
> > > xe_ggtt_set_pte(ggtt, *ggtt_ofs, pte); @@ -381,4
> > > +381,4 @@ struct i915_address_space *intel_dpt_create(struct
> > > intel_framebuffer *fb) void intel_dpt_destroy(struct
> > > i915_address_space *vm) {
> > > return;
> > > -}
> > > \ No newline at end of file
> > > +}
> > > --
> > > 2.25.1
>
Re: [PATCH] drm/i915/guc: Remove bogus null check
On Fri, Mar 29, 2024 at 07:38:11PM +0300, Dan Carpenter wrote:
> On Fri, Mar 29, 2024 at 08:09:38AM +0100, Andi Shyti wrote:
> > Hi Rodrigo,
> >
> > On Thu, Mar 28, 2024 at 09:39:17PM -0400, Rodrigo Vivi wrote:
> > > On Thu, Mar 28, 2024 at 10:41:55PM +0100, Andi Shyti wrote:
> > > > On Thu, Mar 28, 2024 at 05:31:07PM -0400, Rodrigo Vivi wrote:
> > > > > This null check is bogus because we are already using 'ce' stuff
> > > > > in many places before this function is called.
> > > > >
> > > > > Having this here is useless and confuses static analyzer tools
> > > > > that can see:
> > > > >
> > > > > struct intel_engine_cs *engine = ce->engine;
> > > > >
> > > > > before this check, in the same function.
> > > > >
> > > > > Fixes: cec82816d0d0 ("drm/i915/guc: Use context hints for GT
> > > > > frequency")
> > > >
> > > > there is no need to have the Fixes tag here.
> > >
> > > why not? I imagine distros that have this commit cec82816d0d0 and use
> > > static analyzers would also want this patch ported to silent those, no?!
> >
> > Still... it's not a bug. The tag "Fixes:" should be used when a
> > bug is fixed, but not for harmless static analyzer reports.
> >
> > Besides, if we want to keep the Fixes tag we should also Cc
> > stable, i guess checkpatch.pl complains about it.
> >
> > (BTW, Cc'ed in this mail we have the inventor of the tag and he
> > can confirm after having had his morning coffee :-) ).
> >
>
> Good. I keep reminding people that I invented the Fixes tag because it
> is my proudest achievement. :)
>
> No. Only use Fixes tags for bug fixes.
Thanks for the clarifications and reviews. I have removed the 'Fixes:' tag
and pushed the patch as is.
>
> regards,
> dan carpenter
>
Re: [PATCH v2 04/25] drm/i915/bmg: Define IS_BATTLEMAGE macro
On Wed, Apr 03, 2024 at 04:52:32PM +0530, Balasubramani Vivekanandan wrote: > Display code uses IS_BATTLEMAGE macro but the platform support doesn't > still exist in i915. So fake IS_BATTLEMAGE macro defined to enable I'd drop the "still" here since that wording would incorrectly imply that i915 had Battlemage support previously. Otherwise, Reviewed-by: Matt Roper Matt > building i915 code. We should make sure the macro parameter is used in > the always-false expression so that we don't run into "unused variable" > warnings from i915 builds if the IS_BATTLEMAGE() check is the only place > the i915 pointer gets used in a function. > > While we're at it, also update the IS_LUNARLAKE macro to include the > parameter in the false expression for consistency. > > Signed-off-by: Balasubramani Vivekanandan > > --- > drivers/gpu/drm/i915/i915_drv.h | 10 +- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index cf52d4adaa20..b41a414079f4 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -546,7 +546,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P) > #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2) > #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE) > -#define IS_LUNARLAKE(i915) 0 > +/* > + * Display code shared by i915 and Xe relies on macros like IS_LUNARLAKE, > + * so we need to define these even on platforms that the i915 base driver > + * doesn't support. Ensure the parameter is used in the definition to > + * avoid 'unused variable' warnings when compiling the shared display code > + * for i915. > + */ > +#define IS_LUNARLAKE(i915) (0 && i915) > +#define IS_BATTLEMAGE(i915) (0 && i915) > > #define IS_DG2_G10(i915) \ > IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10) > -- > 2.25.1 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
Re: [PATCH v2 03/25] drm/xe/bmg: Define IS_BATTLEMAGE macro
On Wed, Apr 03, 2024 at 04:52:31PM +0530, Balasubramani Vivekanandan wrote: > Common display code requires IS_BATTLEMAGE macro. Defined the macro. > > Signed-off-by: Balasubramani Vivekanandan > Reviewed-by: Matt Roper > --- > drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h > b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h > index a01d1b869c2d..9161d1fdf239 100644 > --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h > +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h > @@ -88,6 +88,7 @@ static inline struct drm_i915_private *kdev_to_i915(struct > device *kdev) > #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2) > #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE) > #define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE) > +#define IS_BATTLEMAGE(dev_priv) IS_PLATFORM(dev_priv, XE_BATTLEMAGE) > > #define IS_HASWELL_ULT(dev_priv) (dev_priv && 0) > #define IS_BROADWELL_ULT(dev_priv) (dev_priv && 0) > -- > 2.25.1 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
Re: [PATCH v2 18/25] drm/i915/display: Enable RM timeout detection
On Wed, Apr 03, 2024 at 04:52:46PM +0530, Balasubramani Vivekanandan wrote:
> From: Mitul Golani
>
> Enable RM timeout interrupt to detect any hang during display engine
> register access. This interrupt is supported only on Display version 14.
This doesn't seem to be true. Bit 29 of the IIR register is still there
on Xe2_LPD (version 20) and I see no reason to believe it won't continue
to be present after that.
It doesn't seem like this patch should even be part of the BMG series.
This was a new interrupt bit first added back on MTL/ARL and continuing
onward from there. It's basically a "hardware is broken" interrupt that
might be useful for debugging, but we hope to never actually see it show
up. It isn't something that's related to the general enabling of any
specific platform, especially since it's something the hardware already
supports on a few other platforms already present in the Xe driver.
> Current default timeout is 2ms.
>
> WA: 14012195489
As Jani noted, this doesn't belong as a trailer. But it's also untrue;
this isn't related to any kind of workaround and the number here doesn't
reference anything in the workaround database.
> Bspec: 50110
>
> CC: Suraj Kandpal
> Signed-off-by: Mitul Golani
> Signed-off-by: Balasubramani Vivekanandan
>
> ---
> drivers/gpu/drm/i915/display/intel_display_irq.c | 10 ++
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
> b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index f846c5b108b5..3035b50fcad9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -851,6 +851,13 @@ gen8_de_misc_irq_handler(struct drm_i915_private
> *dev_priv, u32 iir)
> {
> bool found = false;
>
> + if (iir & GEN8_DE_RM_TIMEOUT) {
> + u32 val = intel_uncore_read(_priv->uncore,
> + RMTIMEOUTREG_CAPTURE);
> + drm_warn(_priv->drm, "Register Access Timeout = 0x%x\n",
> val);
> + found = true;
> + }
> +
> if (DISPLAY_VER(dev_priv) >= 14) {
> if (iir & (XELPDP_PMDEMAND_RSP |
> XELPDP_PMDEMAND_RSPTOUT_ERR)) {
> @@ -1666,6 +1673,9 @@ void gen8_de_irq_postinstall(struct drm_i915_private
> *dev_priv)
> de_port_masked |= DSI0_TE | DSI1_TE;
> }
>
> + if (DISPLAY_VER(dev_priv) == 14)
> + de_misc_masked |= GEN8_DE_RM_TIMEOUT;
> +
> de_pipe_enables = de_pipe_masked |
> GEN8_PIPE_VBLANK |
> gen8_de_pipe_underrun_mask(dev_priv) |
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 875d76fb8cd0..d1692b32bb8a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4212,6 +4212,8 @@
> #define RM_TIMEOUT _MMIO(0x42060)
> #define MMIO_TIMEOUT_US(us) ((us) << 0)
>
> +#define RMTIMEOUTREG_CAPTURE _MMIO(0x420e0)
> +
> /* interrupts */
> #define DE_MASTER_IRQ_CONTROL (1 << 31)
> #define DE_SPRITEB_FLIP_DONE(1 << 29)
> @@ -4398,6 +4400,7 @@
> #define GEN8_DE_MISC_IMR _MMIO(0x44464)
> #define GEN8_DE_MISC_IIR _MMIO(0x44468)
> #define GEN8_DE_MISC_IER _MMIO(0x4446c)
> +#define GEN8_DE_RM_TIMEOUT REG_BIT(29)
Given that this was first introduced in Xe_LPD+, the "GEN8" prefix here
is inappropriate.
Matt
> #define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27)
> #define GEN8_DE_MISC_GSEREG_BIT(27)
> #define GEN8_DE_EDP_PSR REG_BIT(19)
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
[linux-next:master] BUILD REGRESSION 727900b675b749c40ba1f6669c7ae5eb7eb8e837
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: 727900b675b749c40ba1f6669c7ae5eb7eb8e837 Add linux-next specific files for 20240403 Error/Warning reports: https://lore.kernel.org/oe-kbuild-all/202404031246.aq5yr5ko-...@intel.com https://lore.kernel.org/oe-kbuild-all/202404031346.wpihnpyf-...@intel.com https://lore.kernel.org/oe-kbuild-all/202404032101.skzrxcwh-...@intel.com Error/Warning: (recently discovered and may have been fixed) fs/smb/client/file.c:728:12: warning: variable 'rc' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized] mm/kasan/hw_tags.c:280:14: warning: assignment to 'struct vm_struct *' from 'int' makes pointer from integer without a cast [-Wint-conversion] mm/kasan/hw_tags.c:280:16: error: implicit declaration of function 'find_vm_area'; did you mean 'find_vma_prev'? [-Werror=implicit-function-declaration] mm/kasan/hw_tags.c:284:29: error: invalid use of undefined type 'struct vm_struct' riscv32-linux-ld: section .data LMA [001f9000,009465d7] overlaps section .text LMA [000a7e84,0177d68b] Unverified Error/Warning (likely false positive, please contact us if interested): fs/smb/client/file.c:619 serverclose_work() error: uninitialized symbol 'rc'. fs/smb/client/file.c:732 _cifsFileInfo_put() error: uninitialized symbol 'rc'. Error/Warning ids grouped by kconfigs: gcc_recent_errors |-- alpha-allnoconfig | |-- mm-mempool.c:warning:Function-parameter-or-struct-member-gfp_mask-not-described-in-mempool_create_node | `-- mm-mempool.c:warning:Function-parameter-or-struct-member-node_id-not-described-in-mempool_create_node |-- alpha-allyesconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | |-- mm-mempool.c:warning:Function-parameter-or-struct-member-gfp_mask-not-described-in-mempool_create_node | `-- mm-mempool.c:warning:Function-parameter-or-struct-member-node_id-not-described-in-mempool_create_node |-- alpha-defconfig | |-- mm-mempool.c:warning:Function-parameter-or-struct-member-gfp_mask-not-described-in-mempool_create_node | `-- mm-mempool.c:warning:Function-parameter-or-struct-member-node_id-not-described-in-mempool_create_node |-- arm-allmodconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | |-- mm-mempool.c:warning:Function-parameter-or-struct-member-gfp_mask-not-described-in-mempool_create_node | `-- mm-mempool.c:warning:Function-parameter-or-struct-member-node_id-not-described-in-mempool_create_node |-- arm-allyesconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | |-- mm-mempool.c:warning:Function-parameter-or-struct-member-gfp_mask-not-described-in-mempool_create_node | `-- mm-mempool.c:warning:Function-parameter-or-struct-member-node_id-not-described-in-mempool_create_node |-- arm-aspeed_g5_defconfig | |-- mm-mempool.c:warning:Function-parameter-or-struct-member-gfp_mask-not-described-in-mempool_create_node | `-- mm-mempool.c:warning:Function-parameter-or-struct-member-node_id-not-described-in-mempool_create_node |-- arm-randconfig-001-20240403 | |-- mm-mempool.c:warning:Function-parameter-or-struct-member-gfp_mask-not-described-in-mempool_create_node | `-- mm-mempool.c:warning:Function-parameter-or-struct-member-node_id-not-described-in-mempool_create_node |-- arm-randconfig-002-20240403 | |-- mm-mempool.c:warning:Function-parameter-or-struct-member-gfp_mask-not-described-in-mempool_create_node | `-- mm-mempool.c:warning:Function-parameter-or-struct-member-node_id-not-described-in-mempool_create_node |-- arm-randconfig-004-20240403 | |-- mm-mempool.c:warning:Function-parameter-or-struct-member-gfp_mask-not-described-in-mempool_create_node | `-- mm-mempool.c:warning:Function-parameter-or-struct-member-node_id-not-described-in-mempool_create_node |-- arm-randconfig-r061-20240403 | |-- mm-mempool.c:warning:Function-parameter-or-struct-member-gfp_mask-not-described-in-mempool_create_node | `-- mm-mempool.c:warning:Function-parameter-or-struct-member-node_id-not-described-in-mempool_create_node |-- arm64-allnoconfig | |-- mm-mempool.c:warning:Function-parameter-or-struct-member-gfp_mask-not-described-in-mempool_create_node | `-- mm-mempool.c:warning:Function-parameter-or-struct-member-node_id-not-described
Re: [PATCH 01/13] drm/i915/cdclk: Fix CDCLK programming order when pipes are active
On Fri, Mar 29, 2024 at 12:29:09PM -0300, Gustavo Sousa wrote: > Quoting Ville Syrjala (2024-03-27 14:45:32-03:00) > >From: Ville Syrjälä > > > >Currently we always reprogram CDCLK from the > >intel_set_cdclk_pre_plane_update() when using squahs/crawl. > >The code only works correctly for the cd2x update or full > >modeset cases, and it was simply never updated to deal with > >squash/crawl. > > > >If the CDCLK frequency is increasing we must reprogram it > >before we do anything else that might depend on the new > >higher frequency, and conversely we must not decrease > >the frequency until everything that might still depend > >on the old higher frequency has been dealt with. > > > >Since cdclk_state->pipe is only relevant when doing a cd2x > >update we can't use it to determine the correct sequence > >during squash/crawl. To that end introduce cdclk_state->disable_pipes > >which simply indicates that we must perform the update > >while the pipes are disable (ie. during > >intel_set_cdclk_pre_plane_update()). Otherwise we use the > >same old vs. new CDCLK frequency comparsiong as for cd2x > >updates. > > > >The only remaining problem case is when the voltage_level > >needs to increase due to a DDI port, but the CDCLK frequency > >is decreasing (and not all pipes are being disabled). The > >current approach will not bump the voltage level up until > >after the port has already been enabled, which is too late. > >But we'll take care of that case separately. > > Yep. Maybe that's another reason to have that logic detached from the > cdclk sequence in the future? Perhaps. The cdclk sequence is typically specified as 1. request max voltage 2. change cdclk 3. request final voltage We don't actually know whether step 1 has any other side effects beyond changing the voltage. Eg. it might also do some other magic to prepare the hardware/firmware for the cdclk change, and so we might not be able to decouple it from the cdclk sequence 100%. One solution could be to bump the voltage to the max in the pre plane voltage hook whenever cdclk is also changing. We would definitely end up spreading the voltage requests further out from the actual cdclk programming (they'd have to be the outermost pre/post plane hooks), which may or may not have some other side effects as well. -- Ville Syrjälä Intel
✗ Fi.CI.BAT: failure for drm/xe/display: check for error on drmm_mutex_init (rev4)
== Series Details == Series: drm/xe/display: check for error on drmm_mutex_init (rev4) URL : https://patchwork.freedesktop.org/series/131301/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14521 -> Patchwork_131301v4 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_131301v4 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_131301v4, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131301v4/index.html Participating hosts (35 -> 31) -- Missing(4): fi-glk-j4005 fi-cfl-8109u fi-bsw-nick fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_131301v4: ### IGT changes ### Possible regressions * igt@i915_selftest@live@hangcheck: - bat-arls-1: [PASS][1] -> [ABORT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14521/bat-arls-1/igt@i915_selftest@l...@hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131301v4/bat-arls-1/igt@i915_selftest@l...@hangcheck.html Build changes - * Linux: CI_DRM_14521 -> Patchwork_131301v4 CI-20190529: 20190529 CI_DRM_14521: c8dc2a19ae7157e065d5f0c78bc4d3f83165fdef @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7797: e88ebc17ec12b503aab380b08c1213af9cc7a97c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_131301v4: c8dc2a19ae7157e065d5f0c78bc4d3f83165fdef @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits d1643168a57e drm/xe/display: check for error on drmm_mutex_init == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131301v4/index.html
RE: [PATCH] drm/xe/display: fix potential overflow when multiplying 2 u32
Gentle Reminder!
Thanks and Regards,
Arun R Murthy
> -Original Message-
> From: Intel-gfx On Behalf Of Murthy,
> Arun R
> Sent: Thursday, March 28, 2024 10:34 AM
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Subject: RE: [PATCH] drm/xe/display: fix potential overflow when multiplying 2
> u32
>
> Any comments?
>
> Thanks and Regards,
> Arun R Murthy
>
>
> > -Original Message-
> > From: Murthy, Arun R
> > Sent: Monday, March 18, 2024 4:31 PM
> > To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> > Cc: Murthy, Arun R
> > Subject: [PATCH] drm/xe/display: fix potential overflow when
> > multiplying 2 u32
> >
> > Multiplying XE_PAGE_SIZE with another u32 and the product stored in
> > u64 can potentially lead to overflow, use mul_u32_u32 instead.
> >
> > Signed-off-by: Arun R Murthy
> > ---
> > drivers/gpu/drm/xe/display/xe_fb_pin.c | 10 +-
> > 1 file changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c
> > b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> > index 722c84a56607..e0b511ff7eab 100644
> > --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
> > +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> > @@ -29,7 +29,7 @@ write_dpt_rotated(struct xe_bo *bo, struct iosys_map
> > *map, u32 *dpt_ofs, u32 bo_
> > u32 src_idx = src_stride * (height - 1) + column + bo_ofs;
> >
> > for (row = 0; row < height; row++) {
> > - u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx *
> > XE_PAGE_SIZE,
> > + u64 pte = ggtt->pt_ops->pte_encode_bo(bo,
> > mul_u32_u32(src_idx,
> > +XE_PAGE_SIZE),
> > xe-
> > >pat.idx[XE_CACHE_WB]);
> >
> > iosys_map_wr(map, *dpt_ofs, u64, pte); @@ -61,7
> > +61,7 @@ write_dpt_remapped(struct xe_bo *bo, struct iosys_map *map,
> > +u32
> > *dpt_ofs,
> >
> > for (column = 0; column < width; column++) {
> > iosys_map_wr(map, *dpt_ofs, u64,
> > -pte_encode_bo(bo, src_idx * XE_PAGE_SIZE,
> > +pte_encode_bo(bo, mul_u32_u32(src_idx,
> > XE_PAGE_SIZE),
> > xe->pat.idx[XE_CACHE_WB]));
> >
> > *dpt_ofs += 8;
> > @@ -118,7 +118,7 @@ static int __xe_pin_fb_vma_dpt(struct
> > intel_framebuffer *fb,
> > u32 x;
> >
> > for (x = 0; x < size / XE_PAGE_SIZE; x++) {
> > - u64 pte = ggtt->pt_ops->pte_encode_bo(bo, x *
> > XE_PAGE_SIZE,
> > + u64 pte = ggtt->pt_ops->pte_encode_bo(bo,
> > mul_u32_u32(x,
> > +XE_PAGE_SIZE),
> > xe-
> > >pat.idx[XE_CACHE_WB]);
> >
> > iosys_map_wr(>vmap, x * 8, u64, pte); @@ -
> > 164,7 +164,7 @@ write_ggtt_rotated(struct xe_bo *bo, struct xe_ggtt
> > *ggtt,
> > u32 *ggtt_ofs, u32 bo
> > u32 src_idx = src_stride * (height - 1) + column + bo_ofs;
> >
> > for (row = 0; row < height; row++) {
> > - u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx *
> > XE_PAGE_SIZE,
> > + u64 pte = ggtt->pt_ops->pte_encode_bo(bo,
> > mul_u32_u32(src_idx,
> > +XE_PAGE_SIZE),
> > xe-
> > >pat.idx[XE_CACHE_WB]);
> >
> > xe_ggtt_set_pte(ggtt, *ggtt_ofs, pte); @@ -381,4
> > +381,4 @@ struct i915_address_space *intel_dpt_create(struct
> > intel_framebuffer *fb) void intel_dpt_destroy(struct
> > i915_address_space *vm) {
> > return;
> > -}
> > \ No newline at end of file
> > +}
> > --
> > 2.25.1
Re: [PATCHv2] drm/xe/display: check for error on drmm_mutex_init
On Thu, Mar 28, 2024 at 12:33:09PM +0200, Jani Nikula wrote:
On Thu, 28 Mar 2024, Andi Shyti wrote:
Hi Arun,
...
- drmm_mutex_init(>drm, >sb_lock);
- drmm_mutex_init(>drm, >display.backlight.lock);
- drmm_mutex_init(>drm, >display.audio.mutex);
- drmm_mutex_init(>drm, >display.wm.wm_mutex);
- drmm_mutex_init(>drm, >display.pps.mutex);
- drmm_mutex_init(>drm, >display.hdcp.hdcp_mutex);
+ if (drmm_mutex_init(>drm, >sb_lock) ||
+ drmm_mutex_init(>drm, >display.backlight.lock) ||
+ drmm_mutex_init(>drm, >display.audio.mutex) ||
+ drmm_mutex_init(>drm, >display.wm.wm_mutex) ||
+ drmm_mutex_init(>drm, >display.pps.mutex) ||
+ drmm_mutex_init(>drm, >display.hdcp.hdcp_mutex))
+ return -ENOMEM;
My suggestion from v1 was to assign and check the return value, not to
hardcode the return like done here. Now we have a v3 going back to v1
and we never had what was suggested. Why? Let me be explicit and type
it:
if ((err = drmm_mutex_init(>drm, >sb_lock)) ||
(err = drmm_mutex_init(>drm, >display.backlight.lock)) ||
(err = drmm_mutex_init(>drm, >display.audio.mutex)) ||
(err = drmm_mutex_init(>drm, >display.wm.wm_mutex)) ||
(err = drmm_mutex_init(>drm, >display.pps.mutex)) ||
(err = drmm_mutex_init(>drm, >display.hdcp.hdcp_mutex)))
return err;
I also said I usually don't like assign + check in the same statement,
but all the alternatives I've seen here are worse.
However it turns out all of these display mutex initializations are
actually wrong after commit 3fef3e6ff86a ("drm/i915: move display mutex
inits to display code"), which predates xe in the tree.
drivers/gpu/drm/i915/i915_driver.c:
intel_display_driver_early_probe(dev_priv);
drivers/gpu/drm/xe/display/xe_display.c:
intel_display_driver_early_probe(xe);
So intel_display_driver_early_probe() is actually called from xe, which
does the mutex_init() (and misses the mutex_destroy()). Am I missing
anything?
why not extract the value from drmm_mutex_init()? it would make
the code a bit more complex, but better than forcing a -ENOMEM
return.
err = drmm_mutex_init(...)
if (err)
return err;
err = drmm_mutex_init(...)
if (err)
return err;
err = drmm_mutex_init(...)
if (err)
return err;
...
On the other hand drmm_mutex_init(), as of now returns only
-ENOMEM, but it's a bad practice to assume it will always do. I'd
rather prefer not to check the error value at all.
And round and round we go. This is exactly what v1 was [1], but it's not
clear because the patch doesn't have a changelog.
This is all utterly ridiculous compared to *why* we even have or use
drmm_mutex_init(). Managed initialization causes more trouble here than
it gains us. Gah.
I think managed initialization make sense to keep the teardown/unwind
part sane (which is often not tested). However drmm_mutex_init() maybe
is overkill indeed. We started using it because people often forget the
mutex_destroy() and drm/ as whole started using it. Compare:
git grep mutex_init -- drivers/gpu/drm/i915/
git grep mutex_destroy -- drivers/gpu/drm/i915/
This is only an issue when mutex_init does more than init, which is the
case with CONFIG_PREEMPT_RT + CONFIG_DEBUG_MUTEXES, which most people
don't have set so they don't see it, CI doesn't see it, but it causes
problems for people who have that set. Maybe what we could have would be
a drmm_mutex_vinit(mutex, ...) so we can do:
err = drmm_mutex_vinit(>drm,
>sb_lock,
>display.backlight.lock,
...,
NULL);
if (err)
return err;
or... just stop using drmm_mutex_init and add the destroy. No need for
unwind as mutex_init() can't fail. We still need to keep the destroy
explicit, but I think that would be fine (and doesn't cause 1 allocation
per mutex).
Lucas De Marchi
BR,
Jani.
[1]
https://lore.kernel.org/r/ki4ynsl4nmhavf63vzdlt2xkedjo7p7iouzvcksvki3okgz6ak@twlznnlo3g22
Andi
xe->enabled_irq_mask = ~0;
err = drmm_add_action_or_reset(>drm, display_destroy, NULL);
--
2.25.1
--
Jani Nikula, Intel
[PATCHv3] drm/xe/display: check for error on drmm_mutex_init
Check return value for drmm_mutex_init as it can fail and return on
failure.
v2: Removed nested if (Lucas)
v3: Revert back to nested if (Andi)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/xe/display/xe_display.c | 30 -
1 file changed, 24 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c
b/drivers/gpu/drm/xe/display/xe_display.c
index e4db069f0db3..04b83ca5168c 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -107,12 +107,30 @@ int xe_display_create(struct xe_device *xe)
xe->display.hotplug.dp_wq = alloc_ordered_workqueue("xe-dp", 0);
- drmm_mutex_init(>drm, >sb_lock);
- drmm_mutex_init(>drm, >display.backlight.lock);
- drmm_mutex_init(>drm, >display.audio.mutex);
- drmm_mutex_init(>drm, >display.wm.wm_mutex);
- drmm_mutex_init(>drm, >display.pps.mutex);
- drmm_mutex_init(>drm, >display.hdcp.hdcp_mutex);
+ err = drmm_mutex_init(>drm, >sb_lock);
+ if (err)
+ return err;
+
+ err = drmm_mutex_init(>drm, >display.backlight.lock);
+ if (err)
+ return err;
+
+ err = drmm_mutex_init(>drm, >display.audio.mutex);
+ if (err)
+ return err;
+
+ err = drmm_mutex_init(>drm, >display.wm.wm_mutex);
+ if (err)
+ return err;
+
+ err = drmm_mutex_init(>drm, >display.pps.mutex);
+ if (err)
+ return err;
+
+ err = drmm_mutex_init(>drm, >display.hdcp.hdcp_mutex);
+ if (err)
+ return err;
+
xe->enabled_irq_mask = ~0;
err = drmm_add_action_or_reset(>drm, display_destroy, NULL);
--
2.25.1
✗ Fi.CI.SPARSE: warning for drm/i915: Implemnt vblank sycnhronized mbus joining changes (rev4)
== Series Details == Series: drm/i915: Implemnt vblank sycnhronized mbus joining changes (rev4) URL : https://patchwork.freedesktop.org/series/131700/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [PATCH v2 02/25] drm/xe/bmg: Add BMG platform definition
On Wed, Apr 03, 2024 at 04:52:30PM +0530, Balasubramani Vivekanandan wrote: diff --git a/include/drm/xe_pciids.h b/include/drm/xe_pciids.h index c7fc288dacee..73d972a8aca1 100644 --- a/include/drm/xe_pciids.h +++ b/include/drm/xe_pciids.h @@ -208,4 +208,11 @@ MACRO__(0x64A0, ## __VA_ARGS__), \ MACRO__(0x64B0, ## __VA_ARGS__) +#define XE_BMG_IDS(MACRO__, ...) \ + MACRO__(0xE202, ## __VA_ARGS__), \ + MACRO__(0xE20B, ## __VA_ARGS__), \ + MACRO__(0xE20C, ## __VA_ARGS__), \ + MACRO__(0xE20D, ## __VA_ARGS__), \ + MACRO__(0xE212, ## __VA_ARGS__) see my previous review. I don't think these patches are split correctly. We should postpone the PCI additions and let this one be only about adding the platform descriptor and definitions. The next patch adding IS_BATTLEMAGE() could be squashed in this one, while the PCI additions be separate in another patch. Lucas De Marchi
[PATCH v4] drm/i915: limit eDP MSO pipe only for display version 20 and below
The pipes that can be used for eDP MSO are limited to pipe A (and
sometimes also pipe B) only for display version 20 and below.
Modify the function that returns the pipe mask for eDP MSO so that
these limitations only apply to version 20 and below, enabling all
pipes otherwise.
Bspec: 68923
Cc: Jani Nikula
Cc: James Ausmus
Cc: Ville Syrj�l�
Signed-off-by: Luca Coelho
---
In v4:
* actually go back to unrestricting only for > 20. I sent the
wrong patch version in v3.
In v3:
* go back to unrestricing only for > 20, since the change for
versions 14 to 20 should be tested separately;
* simplify the if blocks [Ville].
In v2:
* allow pipes A and B from ver 14 to 20 [Gustavo]
drivers/gpu/drm/i915/display/intel_ddi.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index a3d3d4942eb1..5d2863c43296 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2336,10 +2336,15 @@ static void intel_ddi_power_up_lanes(struct
intel_encoder *encoder,
}
}
-/* Splitter enable for eDP MSO is limited to certain pipes. */
+/*
+ * Splitter enable for eDP MSO is limited to certain pipes, on certain
+ * platforms.
+ */
static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915)
{
- if (IS_ALDERLAKE_P(i915))
+ if (DISPLAY_VER(i915) > 20)
+ return ~0;
+ else if (IS_ALDERLAKE_P(i915))
return BIT(PIPE_A) | BIT(PIPE_B);
else
return BIT(PIPE_A);
--
2.39.2
Re: [PATCH v2 23/25] drm/xe/device: implement transient flush
Hi Bala,
On 4/3/2024 1:22 PM, Balasubramani Vivekanandan wrote:
From: Nirmoy Das
Display surfaces can be tagged as transient by mapping it using one of
the various L3:XD PAT index modes on Xe2. The expectation is that KMD
needs to request transient data flush at the start of flip sequence to
ensure all transient data in L3 cache is flushed to memory. Add a
routine for this which we can then call from the display code.
Signed-off-by: Nirmoy Das
Co-developed-by: Matthew Auld
Signed-off-by: Matthew Auld
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 ++
drivers/gpu/drm/xe/xe_device.c | 52
drivers/gpu/drm/xe/xe_device.h | 2 ++
3 files changed, 57 insertions(+)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 6617c86a096b..7afe810b3441 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -306,6 +306,9 @@
#define XE2LPM_L3SQCREG5 XE_REG_MCR(0xb658)
+#define XE2_TDF_CTRLXE_REG(0xb418)
+#define TRANSIENT_FLUSH_REQUEST REG_BIT(0)
+
#define XEHP_MERT_MOD_CTRLXE_REG_MCR(0xcf28)
#define RENDER_MOD_CTRL XE_REG_MCR(0xcf2c)
#define COMP_MOD_CTRL XE_REG_MCR(0xcf30)
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 01bd5ccf05ca..0c9769fe04f6 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -641,6 +641,58 @@ void xe_device_wmb(struct xe_device *xe)
xe_mmio_write32(gt, SOFTWARE_FLAGS_SPR33, 0);
}
+/**
+ * xe_device_td_flush() - Flush transient L3 cache entries
+ * @xe: The device
+ *
+ * Display engine has direct access to memory and is never coherent with L3/L4
+ * caches (or CPU caches), however KMD is responsible for specifically flushing
+ * transient L3 GPU cache entries prior to the flip sequence to ensure scanout
+ * can happen from such a surface without seeing corruption.
+ *
+ * Display surfaces can be tagged as transient by mapping it using one of the
+ * various L3:XD PAT index modes on Xe2.
+ *
+ * Note: On non-discrete xe2 platforms, like LNL, the entire L3 cache is
flushed
+ * at the end of each submission via PIPE_CONTROL for compute/render, since SA
+ * Media is not coherent with L3 and we want to support render-vs-media
+ * usescases. For other engines like copy/blt the HW internally forces uncached
+ * behaviour, hence why we can skip the TDF on such platforms.
+ */
+void xe_device_td_flush(struct xe_device *xe)
+{
+ struct xe_gt *gt;
+ int err;
+ u8 id;
+
+ if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20)
+ return;
+
+ for_each_gt(gt, xe, id) {
+ if (xe_gt_is_media_type(gt))
+ continue;
+
+ err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
+ if (err)
+ return;
This can be if (xe_force_wake_get()..) without needing the err variable.
Sorry, this was my oversight from this morning.
Regards,
Nirmoy
+
+ xe_mmio_write32(gt, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST);
+ /*
+* FIXME: We can likely do better here with our choice of
+* timeout. Currently we just assume the worst case, but really
+* we should make this dependent on how much actual L3 there is
+* for this system. Recomendation is to allow ~64us in the worst
+* case for 8M of L3 (assumes all entries are transient and need
+* to be flushed).
+*/
+ if (xe_mmio_wait32(gt, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST, 0,
+ 150, NULL, false))
+ xe_gt_err_once(gt, "TD flush timeout\n");
+
+ xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
+ }
+}
+
u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size)
{
return xe_device_has_flat_ccs(xe) ?
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index d413bc2c6be5..d3430f4b820a 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -176,4 +176,6 @@ void xe_device_snapshot_print(struct xe_device *xe, struct
drm_printer *p);
u64 xe_device_canonicalize_addr(struct xe_device *xe, u64 address);
u64 xe_device_uncanonicalize_addr(struct xe_device *xe, u64 address);
+void xe_device_td_flush(struct xe_device *xe);
+
#endif
Re: [PATCH v2 24/25] drm/i915/display: perform transient flush
+Jouni
On 4/3/2024 1:22 PM, Balasubramani Vivekanandan wrote:
From: Matthew Auld
Perform manual transient cache flush prior to flip and at the end of
frontbuffer_flush. This is needed to ensure display engine doesn't see
garbage if the surface is L3:XD dirty.
Testcase: igt@xe-pat@display-vs-wb-transient
Signed-off-by: Matthew Auld
Signed-off-by: Balasubramani Vivekanandan
Acked-by: Nirmoy Das
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
.../gpu/drm/i915/display/intel_frontbuffer.c | 2 ++
drivers/gpu/drm/i915/display/intel_tdf.h | 25 +++
drivers/gpu/drm/xe/Makefile | 3 ++-
drivers/gpu/drm/xe/display/xe_tdf.c | 13 ++
5 files changed, 45 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_tdf.h
create mode 100644 drivers/gpu/drm/xe/display/xe_tdf.c
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index aed25890b6f5..0a720e9d12a7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -110,6 +110,7 @@
#include "intel_sdvo.h"
#include "intel_snps_phy.h"
#include "intel_tc.h"
+#include "intel_tdf.h"
#include "intel_tv.h"
#include "intel_vblank.h"
#include "intel_vdsc.h"
@@ -7095,6 +7096,8 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
intel_atomic_commit_fence_wait(state);
+ intel_td_flush(dev_priv);
+
drm_atomic_helper_wait_for_dependencies(>base);
drm_dp_mst_atomic_wait_for_dependencies(>base);
intel_atomic_global_state_wait_for_dependencies(state);
diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
index 2ea37c0414a9..4923c340a0b6 100644
--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
@@ -65,6 +65,7 @@
#include "intel_fbc.h"
#include "intel_frontbuffer.h"
#include "intel_psr.h"
+#include "intel_tdf.h"
/**
* frontbuffer_flush - flush frontbuffer
@@ -93,6 +94,7 @@ static void frontbuffer_flush(struct drm_i915_private *i915,
trace_intel_frontbuffer_flush(i915, frontbuffer_bits, origin);
might_sleep();
+ intel_td_flush(i915);
intel_drrs_flush(i915, frontbuffer_bits);
intel_psr_flush(i915, frontbuffer_bits, origin);
intel_fbc_flush(i915, frontbuffer_bits, origin);
diff --git a/drivers/gpu/drm/i915/display/intel_tdf.h
b/drivers/gpu/drm/i915/display/intel_tdf.h
new file mode 100644
index ..353cde21f6c2
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_tdf.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef __INTEL_TDF_H__
+#define __INTEL_TDF_H__
+
+/*
+ * TDF (Transient-Data-Flush) is needed for Xe2+ where special L3:XD caching
can
+ * be enabled through various PAT index modes. Idea is to use this caching mode
+ * when for example rendering onto the display surface, with the promise that
+ * KMD will ensure transient cache entries are always flushed by the time we do
+ * the display flip, since display engine is never coherent with CPU/GPU
caches.
+ */
+
+struct drm_i915_private;
+
+#ifdef I915
+static inline void intel_td_flush(struct drm_i915_private *i915) {}
+#else
+void intel_td_flush(struct drm_i915_private *i915);
+#endif
+
+#endif
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index e5b1715f721e..401a4492c625 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -196,7 +196,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
display/xe_dsb_buffer.o \
display/xe_fb_pin.o \
display/xe_hdcp_gsc.o \
- display/xe_plane_initial.o
+ display/xe_plane_initial.o \
+ display/xe_tdf.o
# SOC code shared with i915
xe-$(CONFIG_DRM_XE_DISPLAY) += \
diff --git a/drivers/gpu/drm/xe/display/xe_tdf.c
b/drivers/gpu/drm/xe/display/xe_tdf.c
new file mode 100644
index ..2c0d4e144e09
--- /dev/null
+++ b/drivers/gpu/drm/xe/display/xe_tdf.c
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#include "xe_device.h"
+#include "intel_display_types.h"
+#include "intel_tdf.h"
+
+void intel_td_flush(struct drm_i915_private *i915)
+{
+ xe_device_td_flush(i915);
+}
Re: [PATCH 01/11] drm/i915/dp: Fix DSC line buffer depth programming
On Thu, 28 Mar 2024, Imre Deak wrote:
> On Wed, Mar 20, 2024 at 10:11:41PM +0200, Imre Deak wrote:
>> Fix the calculation of the DSC line buffer depth. This is limited both
>> by the source's and sink's maximum line buffer depth, but the former one
>> was not taken into account. On all Intel platform's the source's maximum
>> buffer depth is 13, so the overall limit is simply the minimum of the
>> source/sink's limit, regardless of the DSC version.
>>
>> This leaves the DSI DSC line buffer depth calculation as-is, trusting
>> VBT.
>>
>> On DSC version 1.2 for sinks reporting a maximum line buffer depth of 16
>> the line buffer depth was incorrectly programmed as 0, leading to a
>> corruption in color gradients / lines on the decompressed screen image.
>>
>> Cc: dri-de...@lists.freedesktop.org
>> Signed-off-by: Imre Deak
>
> Hi Maarten, Thomas, Maxime,
>
> are you ok to merge the DRM DP-DSC/MST changes in patches 1, 7-9, 11 via
> drm-intel-next?
Ping? Ack for merging via drm-intel-next, please?
BR,
Jani.
>
> --Imre
>
>> ---
>> drivers/gpu/drm/i915/display/intel_dp.c | 16 ++--
>> include/drm/display/drm_dsc.h | 3 ---
>> 2 files changed, 6 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index af7ca00e9bc0a..dbe65651bf277 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -89,6 +89,9 @@
>> #define DP_DSC_MAX_ENC_THROUGHPUT_0 34
>> #define DP_DSC_MAX_ENC_THROUGHPUT_1 40
>>
>> +/* Max DSC line buffer depth supported by HW. */
>> +#define INTEL_DP_DSC_MAX_LINE_BUF_DEPTH 13
>> +
>> /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */
>> #define DP_DSC_FEC_OVERHEAD_FACTOR 1028530
>>
>> @@ -1703,7 +1706,6 @@ static int intel_dp_dsc_compute_params(const struct
>> intel_connector *connector,
>> {
>> struct drm_i915_private *i915 = to_i915(connector->base.dev);
>> struct drm_dsc_config *vdsc_cfg = _state->dsc.config;
>> -u8 line_buf_depth;
>> int ret;
>>
>> /*
>> @@ -1732,20 +1734,14 @@ static int intel_dp_dsc_compute_params(const struct
>> intel_connector *connector,
>> connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP -
>> DP_DSC_SUPPORT] &
>> DP_DSC_RGB;
>>
>> -line_buf_depth = drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd);
>> -if (!line_buf_depth) {
>> +vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH,
>> +
>> drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd));
>> +if (!vdsc_cfg->line_buf_depth) {
>> drm_dbg_kms(>drm,
>> "DSC Sink Line Buffer Depth invalid\n");
>> return -EINVAL;
>> }
>>
>> -if (vdsc_cfg->dsc_version_minor == 2)
>> -vdsc_cfg->line_buf_depth = (line_buf_depth ==
>> DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
>> -DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
>> -else
>> -vdsc_cfg->line_buf_depth = (line_buf_depth >
>> DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
>> -DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
>> -
>> vdsc_cfg->block_pred_enable =
>> connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT -
>> DP_DSC_SUPPORT] &
>> DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
>> diff --git a/include/drm/display/drm_dsc.h b/include/drm/display/drm_dsc.h
>> index bc90273d06a62..bbbe7438473d3 100644
>> --- a/include/drm/display/drm_dsc.h
>> +++ b/include/drm/display/drm_dsc.h
>> @@ -40,9 +40,6 @@
>> #define DSC_PPS_RC_RANGE_MINQP_SHIFT11
>> #define DSC_PPS_RC_RANGE_MAXQP_SHIFT6
>> #define DSC_PPS_NATIVE_420_SHIFT1
>> -#define DSC_1_2_MAX_LINEBUF_DEPTH_BITS 16
>> -#define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0
>> -#define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13
>>
>> /**
>> * struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters
>> --
>> 2.43.3
>>
--
Jani Nikula, Intel
Re: [PATCH v2 22/25] drm/xe/gt_print: add xe_gt_err_once()
On 4/3/2024 1:22 PM, Balasubramani Vivekanandan wrote: From: Matthew Auld Needed in an upcoming patch, where we want GT level print, but only which to trigger once to avoid flooding dmesg. Signed-off-by: Matthew Auld Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Nirmoy Das --- drivers/gpu/drm/xe/xe_gt_printk.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_gt_printk.h b/drivers/gpu/drm/xe/xe_gt_printk.h index c2b004d3f48e..d6228baaff1e 100644 --- a/drivers/gpu/drm/xe/xe_gt_printk.h +++ b/drivers/gpu/drm/xe/xe_gt_printk.h @@ -13,6 +13,9 @@ #define xe_gt_printk(_gt, _level, _fmt, ...) \ drm_##_level(_to_xe(_gt)->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__) +#define xe_gt_err_once(_gt, _fmt, ...) \ + xe_gt_printk((_gt), err_once, _fmt, ##__VA_ARGS__) + #define xe_gt_err(_gt, _fmt, ...) \ xe_gt_printk((_gt), err, _fmt, ##__VA_ARGS__)
Re: [PATCH v2 10/25] drm/i915/xe2hpd: Add new C20 PLL register address
On Wed, 03 Apr 2024, Balasubramani Vivekanandan
wrote:
> Xe2_HPD has different address for C20 PLL registers. Enable the support
> to use the right PLL register address based on display version.
>
> Note that Xe2_LPD uses the same C20 SRAM offsets used by Xe_LPDP (i.e.
> MTL's display). According to the BSpec, currently, only Xe2_HPD has
> different offsets, so make sure it is the only display using them in the
> driver.
Even less of a fan of the register handling after seeing this patch.
BR,
Jani.
>
> Bspec: 67610
> Cc: Clint Taylor
> Cc: Gustavo Sousa
> Signed-off-by: Balasubramani Vivekanandan
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27 +--
> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 9 +++
> 2 files changed, 34 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index caaae5d3758e..6e4647859fc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -770,6 +770,17 @@ static struct intel_c20pll_reg mtl_c20_reg = {
> .mpllb_b = MTL_C20_B_MPLLB_CFG_ADDR
> };
>
> +static struct intel_c20pll_reg xe2hpd_c20_reg = {
> + .tx_cnt_a = XE2HPD_C20_A_TX_CNTX_CFG_ADDR,
> + .tx_cnt_b = XE2HPD_C20_B_TX_CNTX_CFG_ADDR,
> + .cmn_cnt_a = XE2HPD_C20_A_CMN_CNTX_CFG_ADDR,
> + .cmn_cnt_b = XE2HPD_C20_B_CMN_CNTX_CFG_ADDR,
> + .mplla_a = XE2HPD_C20_A_MPLLA_CFG_ADDR,
> + .mplla_b = XE2HPD_C20_B_MPLLA_CFG_ADDR,
> + .mpllb_a = XE2HPD_C20_A_MPLLB_CFG_ADDR,
> + .mpllb_b = XE2HPD_C20_B_MPLLB_CFG_ADDR,
> +};
> +
> /* C20 basic DP 1.4 tables */
> static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> .clock = 162000,
> @@ -2166,19 +2177,29 @@ static int intel_c20pll_calc_port_clock(struct
> intel_encoder *encoder,
> return vco << tx_rate_mult >> tx_clk_div >> tx_rate;
> }
>
> +static struct intel_c20pll_reg *intel_c20_get_pll_reg(struct
> drm_i915_private *i915)
> +{
> + if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
> + return _c20_reg;
> + else
> + return _c20_reg;
> +}
> +
> static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
> struct intel_c20pll_state *pll_state)
> {
> bool cntx;
> intel_wakeref_t wakeref;
> int i;
> - struct intel_c20pll_reg *pll_reg = _c20_reg;
> + struct intel_c20pll_reg *pll_reg;
>
> wakeref = intel_cx0_phy_transaction_begin(encoder);
>
> /* 1. Read current context selection */
> cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0,
> PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;
>
> + pll_reg = intel_c20_get_pll_reg(to_i915(encoder->base.dev));
> +
> /* Read Tx configuration */
> for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
> if (cntx)
> @@ -2353,7 +2374,7 @@ static void intel_c20_pll_program(struct
> drm_i915_private *i915,
> u32 clock = crtc_state->port_clock;
> bool cntx;
> int i;
> - const struct intel_c20pll_reg *pll_reg = _c20_reg;
> + const struct intel_c20pll_reg *pll_reg;
>
> if (intel_crtc_has_dp_encoder(crtc_state))
> dp = true;
> @@ -2372,6 +2393,8 @@ static void intel_c20_pll_program(struct
> drm_i915_private *i915,
> usleep_range(4000, 4100);
> }
>
> + pll_reg = intel_c20_get_pll_reg(i915);
> +
> /* 3. Write SRAM configuration context. If A in use, write
> configuration to B context */
> /* 3.1 Tx configuration */
> for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 882b98dc347b..8e5fd605b99e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -292,6 +292,15 @@ struct intel_c20pll_reg {
> #define MTL_C20_A_MPLLB_CFG_ADDR 0xCB5A
> #define MTL_C20_B_MPLLB_CFG_ADDR 0xCB4E
>
> +#define XE2HPD_C20_A_TX_CNTX_CFG_ADDR0xCF5E
> +#define XE2HPD_C20_B_TX_CNTX_CFG_ADDR0xCF5A
> +#define XE2HPD_C20_A_CMN_CNTX_CFG_ADDR 0xCE8E
> +#define XE2HPD_C20_B_CMN_CNTX_CFG_ADDR 0xCE89
> +#define XE2HPD_C20_A_MPLLA_CFG_ADDR 0xCE58
> +#define XE2HPD_C20_B_MPLLA_CFG_ADDR 0xCE4D
> +#define XE2HPD_C20_A_MPLLB_CFG_ADDR 0xCCC2
> +#define XE2HPD_C20_B_MPLLB_CFG_ADDR 0xCCB6
> +
> /* C20 Phy VSwing Masks */
> #define C20_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(5, 0)
> #define C20_PHY_VSWING_PREEMPH(val)
> REG_FIELD_PREP8(C20_PHY_VSWING_PREEMPH_MASK, val)
--
Jani Nikula, Intel
Re: [PATCH v2 18/25] drm/i915/display: Enable RM timeout detection
On Wed, 03 Apr 2024, Balasubramani Vivekanandan
wrote:
> From: Mitul Golani
>
> Enable RM timeout interrupt to detect any hang during display engine
> register access. This interrupt is supported only on Display version 14.
> Current default timeout is 2ms.
>
> WA: 14012195489
Please don't invent new trailers. Add proper wa descriptions in
comments.
> Bspec: 50110
>
There should be no blank line here.
> CC: Suraj Kandpal
> Signed-off-by: Mitul Golani
> Signed-off-by: Balasubramani Vivekanandan
>
> ---
> drivers/gpu/drm/i915/display/intel_display_irq.c | 10 ++
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
> b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index f846c5b108b5..3035b50fcad9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -851,6 +851,13 @@ gen8_de_misc_irq_handler(struct drm_i915_private
> *dev_priv, u32 iir)
> {
> bool found = false;
>
> + if (iir & GEN8_DE_RM_TIMEOUT) {
> + u32 val = intel_uncore_read(_priv->uncore,
> + RMTIMEOUTREG_CAPTURE);
> + drm_warn(_priv->drm, "Register Access Timeout = 0x%x\n",
> val);
What good does this do with no information on the register?
> + found = true;
> + }
> +
> if (DISPLAY_VER(dev_priv) >= 14) {
> if (iir & (XELPDP_PMDEMAND_RSP |
> XELPDP_PMDEMAND_RSPTOUT_ERR)) {
> @@ -1666,6 +1673,9 @@ void gen8_de_irq_postinstall(struct drm_i915_private
> *dev_priv)
> de_port_masked |= DSI0_TE | DSI1_TE;
> }
>
> + if (DISPLAY_VER(dev_priv) == 14)
> + de_misc_masked |= GEN8_DE_RM_TIMEOUT;
> +
> de_pipe_enables = de_pipe_masked |
> GEN8_PIPE_VBLANK |
> gen8_de_pipe_underrun_mask(dev_priv) |
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 875d76fb8cd0..d1692b32bb8a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4212,6 +4212,8 @@
> #define RM_TIMEOUT _MMIO(0x42060)
> #define MMIO_TIMEOUT_US(us) ((us) << 0)
>
> +#define RMTIMEOUTREG_CAPTURE _MMIO(0x420e0)
> +
> /* interrupts */
> #define DE_MASTER_IRQ_CONTROL (1 << 31)
> #define DE_SPRITEB_FLIP_DONE(1 << 29)
> @@ -4398,6 +4400,7 @@
> #define GEN8_DE_MISC_IMR _MMIO(0x44464)
> #define GEN8_DE_MISC_IIR _MMIO(0x44468)
> #define GEN8_DE_MISC_IER _MMIO(0x4446c)
> +#define GEN8_DE_RM_TIMEOUT REG_BIT(29)
> #define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27)
> #define GEN8_DE_MISC_GSEREG_BIT(27)
> #define GEN8_DE_EDP_PSR REG_BIT(19)
--
Jani Nikula, Intel
✓ Fi.CI.BAT: success for Enable dislay support for Battlemage (rev2)
== Series Details ==
Series: Enable dislay support for Battlemage (rev2)
URL : https://patchwork.freedesktop.org/series/131984/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14520 -> Patchwork_131984v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131984v2/index.html
Participating hosts (39 -> 30)
--
Missing(9): bat-arls-4 fi-snb-2520m fi-glk-j4005 bat-atsm-1 fi-cfl-8109u
bat-dg2-11 fi-bsw-nick bat-jsl-1 bat-arls-3
Known issues
Here are the changes found in Patchwork_131984v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-9: [PASS][1] -> [FAIL][2] ([i915#10378])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14520/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131984v2/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html
- bat-dg2-8: [PASS][3] -> [FAIL][4] ([i915#10378])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14520/bat-dg2-8/igt@gem_lmem_swapping@ba...@lmem0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131984v2/bat-dg2-8/igt@gem_lmem_swapping@ba...@lmem0.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-adlm-1: NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131984v2/bat-adlm-1/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@i915_pm_rps@basic-api:
- bat-adlm-1: NOTRUN -> [SKIP][6] ([i915#6621])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131984v2/bat-adlm-1/igt@i915_pm_...@basic-api.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-adlm-1: NOTRUN -> [SKIP][7]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131984v2/bat-adlm-1/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- bat-adlm-1: NOTRUN -> [SKIP][8] ([i915#1849] / [i915#4342])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131984v2/bat-adlm-1/igt@kms_frontbuffer_track...@basic.html
* igt@kms_pipe_crc_basic@hang-read-crc:
- bat-adlm-1: NOTRUN -> [SKIP][9] ([i915#9875] / [i915#9900]) +6
other tests skip
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131984v2/bat-adlm-1/igt@kms_pipe_crc_ba...@hang-read-crc.html
* igt@kms_pm_backlight@basic-brightness:
- bat-adlm-1: NOTRUN -> [SKIP][10] ([i915#5354])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131984v2/bat-adlm-1/igt@kms_pm_backli...@basic-brightness.html
* igt@kms_psr@psr-sprite-plane-onoff:
- bat-adlm-1: NOTRUN -> [SKIP][11] ([i915#1072] / [i915#9673] /
[i915#9732]) +3 other tests skip
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131984v2/bat-adlm-1/igt@kms_...@psr-sprite-plane-onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-adlm-1: NOTRUN -> [SKIP][12] ([i915#3555])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131984v2/bat-adlm-1/igt@kms_setm...@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-adlm-1: NOTRUN -> [SKIP][13] ([i915#3708] / [i915#9900])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131984v2/bat-adlm-1/igt@prime_v...@basic-fence-flip.html
* igt@prime_vgem@basic-write:
- bat-adlm-1: NOTRUN -> [SKIP][14] ([i915#3708]) +2 other tests skip
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131984v2/bat-adlm-1/igt@prime_v...@basic-write.html
Possible fixes
* igt@i915_pm_rpm@module-reload:
- {bat-mtlp-9}: [WARN][15] ([i915#10436]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14520/bat-mtlp-9/igt@i915_pm_...@module-reload.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131984v2/bat-mtlp-9/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live@hangcheck:
- bat-rpls-3: [DMESG-WARN][17] ([i915#5591]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14520/bat-rpls-3/igt@i915_selftest@l...@hangcheck.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131984v2/bat-rpls-3/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10378]: https://gitlab.freedesktop.org/drm/intel/issues/10378
[i915#10436]: https://gitlab.freedesktop.org/drm/intel/issues/10436
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]:
Re: [PATCH v2 16/25] drm/xe/xe2hpd: Define a new DRAM type INTEL_DRAM_GDDR
On Wed, 03 Apr 2024, Balasubramani Vivekanandan
wrote:
> Defined a new DRAM type to be used in the following patches.
> The following patch first makes use of this new type in the i915
> display. So without this define, build would fail when the shared
> display code is built for Xe.
Just make it part of that patch I think.
>
> Signed-off-by: Balasubramani Vivekanandan
>
> ---
> drivers/gpu/drm/xe/xe_device_types.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h
> b/drivers/gpu/drm/xe/xe_device_types.h
> index 1df3dcc17d75..e7aa2dd3df8d 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -480,6 +480,7 @@ struct xe_device {
> INTEL_DRAM_LPDDR4,
> INTEL_DRAM_DDR5,
> INTEL_DRAM_LPDDR5,
> + INTEL_DRAM_GDDR,
> } type;
> u8 num_qgv_points;
> u8 num_psf_gv_points;
--
Jani Nikula, Intel
Re: [PATCH v2 15/25] drm/xe/display: Lane reversal requires writes to both context lanes
On Wed, 03 Apr 2024, Balasubramani Vivekanandan
wrote:
> From: Clint Taylor
>
> Write both CX0 Lanes for Context Toggle for all except TC pin assignment D.
Seems like a fix that should be the first patch in the series, no?
> BSPEC: 64539
The spelling is "Bspec".
> Signed-off-by: Clint Taylor
> Signed-off-by: Balasubramani Vivekanandan
>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 20035be015c3..cbcb6651dfed 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2558,7 +2558,7 @@ static void intel_c20_pll_program(struct
> drm_i915_private *i915,
> {
> const struct intel_c20pll_state *pll_state =
> _state->cx0pll_state.c20;
> bool dp = false;
> - int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES :
> INTEL_CX0_LANE0;
> + u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
> u32 clock = crtc_state->port_clock;
> bool cntx;
> int i;
> @@ -2634,19 +2634,19 @@ static void intel_c20_pll_program(struct
> drm_i915_private *i915,
> }
>
> /* 4. Program custom width to match the link protocol */
> - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_WIDTH,
> + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_WIDTH,
> PHY_C20_CUSTOM_WIDTH_MASK,
> PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(clock,
> dp)),
> MB_WRITE_COMMITTED);
>
> /* 5. For DP or 6. For HDMI */
> if (dp) {
> - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,
> + intel_cx0_rmw(encoder, owned_lane_mask,
> PHY_C20_VDR_CUSTOM_SERDES_RATE,
> BIT(6) | PHY_C20_CUSTOM_SERDES_MASK,
> BIT(6) |
> PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(clock)),
> MB_WRITE_COMMITTED);
> } else {
> - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,
> + intel_cx0_rmw(encoder, owned_lane_mask,
> PHY_C20_VDR_CUSTOM_SERDES_RATE,
> BIT(7) | PHY_C20_CUSTOM_SERDES_MASK,
> is_hdmi_frl(clock) ? BIT(7) : 0,
> MB_WRITE_COMMITTED);
> @@ -2660,7 +2660,7 @@ static void intel_c20_pll_program(struct
> drm_i915_private *i915,
>* 7. Write Vendor specific registers to toggle context setting to load
>* the updated programming toggle context bit
>*/
> - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,
> + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
> BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED);
> }
--
Jani Nikula, Intel
✗ Fi.CI.SPARSE: warning for Enable dislay support for Battlemage (rev2)
== Series Details == Series: Enable dislay support for Battlemage (rev2) URL : https://patchwork.freedesktop.org/series/131984/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
✗ Fi.CI.CHECKPATCH: warning for Enable dislay support for Battlemage (rev2)
== Series Details == Series: Enable dislay support for Battlemage (rev2) URL : https://patchwork.freedesktop.org/series/131984/ State : warning == Summary == Error: dim checkpatch failed 240c4657f7c1 drm/i915/display: Prepare to handle new C20 PLL register address -:75: WARNING:LONG_LINE: line length of 112 exceeds 100 columns #75: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2207: + PHY_C20_B_MPLLB_CNTX_CFG(pll_reg, i)); -:79: WARNING:LONG_LINE: line length of 112 exceeds 100 columns #79: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2210: + PHY_C20_A_MPLLB_CNTX_CFG(pll_reg, i)); -:87: WARNING:LONG_LINE: line length of 112 exceeds 100 columns #87: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2217: + PHY_C20_B_MPLLA_CNTX_CFG(pll_reg, i)); -:91: WARNING:LONG_LINE: line length of 112 exceeds 100 columns #91: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2220: + PHY_C20_A_MPLLA_CNTX_CFG(pll_reg, i)); total: 0 errors, 4 warnings, 0 checks, 186 lines checked 69c8facefd41 drm/xe/bmg: Add BMG platform definition -:57: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #57: FILE: include/drm/xe_pciids.h:211: +#define XE_BMG_IDS(MACRO__, ...) \ + MACRO__(0xE202, ## __VA_ARGS__), \ + MACRO__(0xE20B, ## __VA_ARGS__), \ + MACRO__(0xE20C, ## __VA_ARGS__), \ + MACRO__(0xE20D, ## __VA_ARGS__), \ + MACRO__(0xE212, ## __VA_ARGS__) -:57: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects? #57: FILE: include/drm/xe_pciids.h:211: +#define XE_BMG_IDS(MACRO__, ...) \ + MACRO__(0xE202, ## __VA_ARGS__), \ + MACRO__(0xE20B, ## __VA_ARGS__), \ + MACRO__(0xE20C, ## __VA_ARGS__), \ + MACRO__(0xE20D, ## __VA_ARGS__), \ + MACRO__(0xE212, ## __VA_ARGS__) total: 1 errors, 0 warnings, 1 checks, 37 lines checked 96d20b1616b6 drm/xe/bmg: Define IS_BATTLEMAGE macro 289221f8cd6f drm/i915/bmg: Define IS_BATTLEMAGE macro -:34: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'i915' may be better as '(i915)' to avoid precedence issues #34: FILE: drivers/gpu/drm/i915/i915_drv.h:556: +#define IS_LUNARLAKE(i915) (0 && i915) -:35: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'i915' may be better as '(i915)' to avoid precedence issues #35: FILE: drivers/gpu/drm/i915/i915_drv.h:557: +#define IS_BATTLEMAGE(i915) (0 && i915) total: 0 errors, 0 warnings, 2 checks, 16 lines checked d0359d937ce9 drm/i915/xe2: Skip CCS modifiers for Xe2 platforms 487e9de9ff69 drm/i915/xe2hpd: Initial cdclk table d5968cd0e607 Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping" 5e5f6a49f006 drm/i915/bmg: Extend DG2 tc check to future 64f2ae260499 drm/i915/xe2hpd: Properly disable power in port A 0846089eb132 drm/i915/xe2hpd: Add new C20 PLL register address 6d865ce2bdff drm/i915/xe2hpd: Add support for eDP PLL configuration da173b635b04 drm/i915/xe2hpd: update pll values in sync with Bspec 46b58969e857 drm/i915/xe2hpd: Add display info 39264a92b94a drm/i915/xe2hpd: Add missing chicken bit register programming a753cef507fd drm/xe/display: Lane reversal requires writes to both context lanes d23f6312d2ae drm/xe/xe2hpd: Define a new DRAM type INTEL_DRAM_GDDR 18932a957663 drm/i915/xe2hpd: Add max memory bandwidth algorithm 1fdfeb28e9af drm/i915/display: Enable RM timeout detection 843ab6f8bd36 drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits ac29ab1c1868 drm/i915/bmg: BMG should re-use MTL's south display logic ac359ca58fc0 drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5 390515c6 drm/xe/gt_print: add xe_gt_err_once() d13dbec17ace drm/xe/device: implement transient flush e03d533dcefd drm/i915/display: perform transient flush Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:56: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #56: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 76 lines checked c5a7b285569d drm/xe/bmg: Enable the display support
Re: [PATCH v2 01/25] drm/i915/display: Prepare to handle new C20 PLL register address
On Wed, 03 Apr 2024, Balasubramani Vivekanandan
wrote:
> New platforms have different addresses for C20 PLL registers. This patch
> prepares the driver to work with different register addresses.
> New structure `struct intel_c20pll_reg` is created to hold the register
> addresses for each platform with different register address.
Absolutely not a fan. We have so many ways to handle register offsets,
and this adds another one, completely different from the rest.
Most other places that have complex conditions for choosing a register
have a function to pick the register offset.
BR,
Jani.
>
> CC: Clint Taylor
> Signed-off-by: Balasubramani Vivekanandan
>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 53 +--
> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 36 ++---
> 2 files changed, 65 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index a2c4bf33155f..13a2e3db2812 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -759,6 +759,17 @@ static const struct intel_c10pll_state * const
> mtl_c10_edp_tables[] = {
> NULL,
> };
>
> +static struct intel_c20pll_reg mtl_c20_reg = {
> + .tx_cnt_a = MTL_C20_A_TX_CNTX_CFG_ADDR,
> + .tx_cnt_b = MTL_C20_B_TX_CNTX_CFG_ADDR,
> + .cmn_cnt_a = MTL_C20_A_CMN_CNTX_CFG_ADDR,
> + .cmn_cnt_b = MTL_C20_B_CMN_CNTX_CFG_ADDR,
> + .mplla_a = MTL_C20_A_MPLLA_CFG_ADDR,
> + .mplla_b = MTL_C20_B_MPLLA_CFG_ADDR,
> + .mpllb_a = MTL_C20_A_MPLLB_CFG_ADDR,
> + .mpllb_b = MTL_C20_B_MPLLB_CFG_ADDR
> +};
> +
> /* C20 basic DP 1.4 tables */
> static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> .clock = 162000,
> @@ -2161,6 +2172,7 @@ static void intel_c20pll_readout_hw_state(struct
> intel_encoder *encoder,
> bool cntx;
> intel_wakeref_t wakeref;
> int i;
> + struct intel_c20pll_reg *pll_reg = _c20_reg;
>
> wakeref = intel_cx0_phy_transaction_begin(encoder);
>
> @@ -2171,20 +2183,20 @@ static void intel_c20pll_readout_hw_state(struct
> intel_encoder *encoder,
> for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
> if (cntx)
> pll_state->tx[i] = intel_c20_sram_read(encoder,
> INTEL_CX0_LANE0,
> -
> PHY_C20_B_TX_CNTX_CFG(i));
> +
> PHY_C20_B_TX_CNTX_CFG(pll_reg, i));
> else
> pll_state->tx[i] = intel_c20_sram_read(encoder,
> INTEL_CX0_LANE0,
> -
> PHY_C20_A_TX_CNTX_CFG(i));
> +
> PHY_C20_A_TX_CNTX_CFG(pll_reg, i));
> }
>
> /* Read common configuration */
> for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
> if (cntx)
> pll_state->cmn[i] = intel_c20_sram_read(encoder,
> INTEL_CX0_LANE0,
> -
> PHY_C20_B_CMN_CNTX_CFG(i));
> +
> PHY_C20_B_CMN_CNTX_CFG(pll_reg, i));
> else
> pll_state->cmn[i] = intel_c20_sram_read(encoder,
> INTEL_CX0_LANE0,
> -
> PHY_C20_A_CMN_CNTX_CFG(i));
> +
> PHY_C20_A_CMN_CNTX_CFG(pll_reg, i));
> }
>
> if (intel_c20phy_use_mpllb(pll_state)) {
> @@ -2192,20 +2204,20 @@ static void intel_c20pll_readout_hw_state(struct
> intel_encoder *encoder,
> for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
> if (cntx)
> pll_state->mpllb[i] =
> intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
> -
> PHY_C20_B_MPLLB_CNTX_CFG(i));
> +
> PHY_C20_B_MPLLB_CNTX_CFG(pll_reg, i));
> else
> pll_state->mpllb[i] =
> intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
> -
> PHY_C20_A_MPLLB_CNTX_CFG(i));
> +
> PHY_C20_A_MPLLB_CNTX_CFG(pll_reg, i));
> }
> } else {
> /* MPLLA configuration */
> for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
> if (cntx)
> pll_state->mplla[i] =
> intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
> -
> PHY_C20_B_MPLLA_CNTX_CFG(i));
> +
[PATCH v2 25/25] drm/xe/bmg: Enable the display support
Enable the display support for Battlemage
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/xe/xe_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index b3158053baee..835c18ec8fb9 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -340,6 +340,7 @@ static const struct xe_device_desc lnl_desc = {
static const struct xe_device_desc bmg_desc = {
DGFX_FEATURES,
PLATFORM(XE_BATTLEMAGE),
+ .has_display = true,
.require_force_probe = true,
};
--
2.25.1
[PATCH v2 24/25] drm/i915/display: perform transient flush
From: Matthew Auld
Perform manual transient cache flush prior to flip and at the end of
frontbuffer_flush. This is needed to ensure display engine doesn't see
garbage if the surface is L3:XD dirty.
Testcase: igt@xe-pat@display-vs-wb-transient
Signed-off-by: Matthew Auld
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
.../gpu/drm/i915/display/intel_frontbuffer.c | 2 ++
drivers/gpu/drm/i915/display/intel_tdf.h | 25 +++
drivers/gpu/drm/xe/Makefile | 3 ++-
drivers/gpu/drm/xe/display/xe_tdf.c | 13 ++
5 files changed, 45 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_tdf.h
create mode 100644 drivers/gpu/drm/xe/display/xe_tdf.c
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index aed25890b6f5..0a720e9d12a7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -110,6 +110,7 @@
#include "intel_sdvo.h"
#include "intel_snps_phy.h"
#include "intel_tc.h"
+#include "intel_tdf.h"
#include "intel_tv.h"
#include "intel_vblank.h"
#include "intel_vdsc.h"
@@ -7095,6 +7096,8 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
intel_atomic_commit_fence_wait(state);
+ intel_td_flush(dev_priv);
+
drm_atomic_helper_wait_for_dependencies(>base);
drm_dp_mst_atomic_wait_for_dependencies(>base);
intel_atomic_global_state_wait_for_dependencies(state);
diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
index 2ea37c0414a9..4923c340a0b6 100644
--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
@@ -65,6 +65,7 @@
#include "intel_fbc.h"
#include "intel_frontbuffer.h"
#include "intel_psr.h"
+#include "intel_tdf.h"
/**
* frontbuffer_flush - flush frontbuffer
@@ -93,6 +94,7 @@ static void frontbuffer_flush(struct drm_i915_private *i915,
trace_intel_frontbuffer_flush(i915, frontbuffer_bits, origin);
might_sleep();
+ intel_td_flush(i915);
intel_drrs_flush(i915, frontbuffer_bits);
intel_psr_flush(i915, frontbuffer_bits, origin);
intel_fbc_flush(i915, frontbuffer_bits, origin);
diff --git a/drivers/gpu/drm/i915/display/intel_tdf.h
b/drivers/gpu/drm/i915/display/intel_tdf.h
new file mode 100644
index ..353cde21f6c2
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_tdf.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef __INTEL_TDF_H__
+#define __INTEL_TDF_H__
+
+/*
+ * TDF (Transient-Data-Flush) is needed for Xe2+ where special L3:XD caching
can
+ * be enabled through various PAT index modes. Idea is to use this caching mode
+ * when for example rendering onto the display surface, with the promise that
+ * KMD will ensure transient cache entries are always flushed by the time we do
+ * the display flip, since display engine is never coherent with CPU/GPU
caches.
+ */
+
+struct drm_i915_private;
+
+#ifdef I915
+static inline void intel_td_flush(struct drm_i915_private *i915) {}
+#else
+void intel_td_flush(struct drm_i915_private *i915);
+#endif
+
+#endif
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index e5b1715f721e..401a4492c625 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -196,7 +196,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
display/xe_dsb_buffer.o \
display/xe_fb_pin.o \
display/xe_hdcp_gsc.o \
- display/xe_plane_initial.o
+ display/xe_plane_initial.o \
+ display/xe_tdf.o
# SOC code shared with i915
xe-$(CONFIG_DRM_XE_DISPLAY) += \
diff --git a/drivers/gpu/drm/xe/display/xe_tdf.c
b/drivers/gpu/drm/xe/display/xe_tdf.c
new file mode 100644
index ..2c0d4e144e09
--- /dev/null
+++ b/drivers/gpu/drm/xe/display/xe_tdf.c
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#include "xe_device.h"
+#include "intel_display_types.h"
+#include "intel_tdf.h"
+
+void intel_td_flush(struct drm_i915_private *i915)
+{
+ xe_device_td_flush(i915);
+}
--
2.25.1
[PATCH v2 23/25] drm/xe/device: implement transient flush
From: Nirmoy Das
Display surfaces can be tagged as transient by mapping it using one of
the various L3:XD PAT index modes on Xe2. The expectation is that KMD
needs to request transient data flush at the start of flip sequence to
ensure all transient data in L3 cache is flushed to memory. Add a
routine for this which we can then call from the display code.
Signed-off-by: Nirmoy Das
Co-developed-by: Matthew Auld
Signed-off-by: Matthew Auld
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 ++
drivers/gpu/drm/xe/xe_device.c | 52
drivers/gpu/drm/xe/xe_device.h | 2 ++
3 files changed, 57 insertions(+)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 6617c86a096b..7afe810b3441 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -306,6 +306,9 @@
#define XE2LPM_L3SQCREG5 XE_REG_MCR(0xb658)
+#define XE2_TDF_CTRL XE_REG(0xb418)
+#define TRANSIENT_FLUSH_REQUEST REG_BIT(0)
+
#define XEHP_MERT_MOD_CTRL XE_REG_MCR(0xcf28)
#define RENDER_MOD_CTRLXE_REG_MCR(0xcf2c)
#define COMP_MOD_CTRL XE_REG_MCR(0xcf30)
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 01bd5ccf05ca..0c9769fe04f6 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -641,6 +641,58 @@ void xe_device_wmb(struct xe_device *xe)
xe_mmio_write32(gt, SOFTWARE_FLAGS_SPR33, 0);
}
+/**
+ * xe_device_td_flush() - Flush transient L3 cache entries
+ * @xe: The device
+ *
+ * Display engine has direct access to memory and is never coherent with L3/L4
+ * caches (or CPU caches), however KMD is responsible for specifically flushing
+ * transient L3 GPU cache entries prior to the flip sequence to ensure scanout
+ * can happen from such a surface without seeing corruption.
+ *
+ * Display surfaces can be tagged as transient by mapping it using one of the
+ * various L3:XD PAT index modes on Xe2.
+ *
+ * Note: On non-discrete xe2 platforms, like LNL, the entire L3 cache is
flushed
+ * at the end of each submission via PIPE_CONTROL for compute/render, since SA
+ * Media is not coherent with L3 and we want to support render-vs-media
+ * usescases. For other engines like copy/blt the HW internally forces uncached
+ * behaviour, hence why we can skip the TDF on such platforms.
+ */
+void xe_device_td_flush(struct xe_device *xe)
+{
+ struct xe_gt *gt;
+ int err;
+ u8 id;
+
+ if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20)
+ return;
+
+ for_each_gt(gt, xe, id) {
+ if (xe_gt_is_media_type(gt))
+ continue;
+
+ err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
+ if (err)
+ return;
+
+ xe_mmio_write32(gt, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST);
+ /*
+* FIXME: We can likely do better here with our choice of
+* timeout. Currently we just assume the worst case, but really
+* we should make this dependent on how much actual L3 there is
+* for this system. Recomendation is to allow ~64us in the worst
+* case for 8M of L3 (assumes all entries are transient and need
+* to be flushed).
+*/
+ if (xe_mmio_wait32(gt, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST, 0,
+ 150, NULL, false))
+ xe_gt_err_once(gt, "TD flush timeout\n");
+
+ xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
+ }
+}
+
u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size)
{
return xe_device_has_flat_ccs(xe) ?
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index d413bc2c6be5..d3430f4b820a 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -176,4 +176,6 @@ void xe_device_snapshot_print(struct xe_device *xe, struct
drm_printer *p);
u64 xe_device_canonicalize_addr(struct xe_device *xe, u64 address);
u64 xe_device_uncanonicalize_addr(struct xe_device *xe, u64 address);
+void xe_device_td_flush(struct xe_device *xe);
+
#endif
--
2.25.1
[PATCH v2 22/25] drm/xe/gt_print: add xe_gt_err_once()
From: Matthew Auld Needed in an upcoming patch, where we want GT level print, but only which to trigger once to avoid flooding dmesg. Signed-off-by: Matthew Auld Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/xe/xe_gt_printk.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_gt_printk.h b/drivers/gpu/drm/xe/xe_gt_printk.h index c2b004d3f48e..d6228baaff1e 100644 --- a/drivers/gpu/drm/xe/xe_gt_printk.h +++ b/drivers/gpu/drm/xe/xe_gt_printk.h @@ -13,6 +13,9 @@ #define xe_gt_printk(_gt, _level, _fmt, ...) \ drm_##_level(_to_xe(_gt)->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__) +#define xe_gt_err_once(_gt, _fmt, ...) \ + xe_gt_printk((_gt), err_once, _fmt, ##__VA_ARGS__) + #define xe_gt_err(_gt, _fmt, ...) \ xe_gt_printk((_gt), err, _fmt, ##__VA_ARGS__) -- 2.25.1
[PATCH v2 21/25] drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5
Max supported speed by xe2hpd is UHBR13.5. Limit the max DP source rate to it. Bspec: 67066 Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index b393ddbb7b35..d9d37f4971dd 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -466,6 +466,9 @@ static int mtl_max_source_rate(struct intel_dp *intel_dp) if (intel_encoder_is_c10phy(encoder)) return 81; + if (DISPLAY_VER_FULL(to_i915(encoder->base.dev)) == IP_VER(14, 1)) + return 135; + return 200; } -- 2.25.1
[PATCH v2 20/25] drm/i915/bmg: BMG should re-use MTL's south display logic
From: Matt Roper
Battlemage's south display is the same as Meteor Lake's, including the
need to invert the HPD pins, which Lunar Lake does not need.
Signed-off-by: Matt Roper
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/soc/intel_pch.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c
b/drivers/gpu/drm/i915/soc/intel_pch.c
index 3cad6dac06b0..542eea50093c 100644
--- a/drivers/gpu/drm/i915/soc/intel_pch.c
+++ b/drivers/gpu/drm/i915/soc/intel_pch.c
@@ -218,10 +218,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
if (DISPLAY_VER(dev_priv) >= 20) {
dev_priv->pch_type = PCH_LNL;
return;
- } else if (IS_METEORLAKE(dev_priv)) {
+ } else if (IS_BATTLEMAGE(dev_priv) || IS_METEORLAKE(dev_priv)) {
/*
* Both north display and south display are on the SoC die.
-* The real PCH is uninvolved in display.
+* The real PCH (if it even exists) is uninvolved in display.
*/
dev_priv->pch_type = PCH_MTL;
return;
--
2.25.1
[PATCH v2 19/25] drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits
From: José Roberto de Souza
Xe2_HPD doesn't have DBOX BW credits, so here programing it with
zero.
BSpec: 49213
Signed-off-by: José Roberto de Souza
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/skl_watermark.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index bc341abcab2f..22ae782e89f4 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3733,7 +3733,7 @@ void intel_mbus_dbox_update(struct intel_atomic_state
*state)
if (!new_crtc_state->hw.active)
continue;
- if (DISPLAY_VER(i915) >= 14) {
+ if (DISPLAY_VER(i915) >= 14 && !IS_BATTLEMAGE(i915)) {
if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
new_dbuf_state->active_pipes))
pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;
--
2.25.1
[PATCH v2 18/25] drm/i915/display: Enable RM timeout detection
From: Mitul Golani
Enable RM timeout interrupt to detect any hang during display engine
register access. This interrupt is supported only on Display version 14.
Current default timeout is 2ms.
WA: 14012195489
Bspec: 50110
CC: Suraj Kandpal
Signed-off-by: Mitul Golani
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 10 ++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
b/drivers/gpu/drm/i915/display/intel_display_irq.c
index f846c5b108b5..3035b50fcad9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -851,6 +851,13 @@ gen8_de_misc_irq_handler(struct drm_i915_private
*dev_priv, u32 iir)
{
bool found = false;
+ if (iir & GEN8_DE_RM_TIMEOUT) {
+ u32 val = intel_uncore_read(_priv->uncore,
+ RMTIMEOUTREG_CAPTURE);
+ drm_warn(_priv->drm, "Register Access Timeout = 0x%x\n",
val);
+ found = true;
+ }
+
if (DISPLAY_VER(dev_priv) >= 14) {
if (iir & (XELPDP_PMDEMAND_RSP |
XELPDP_PMDEMAND_RSPTOUT_ERR)) {
@@ -1666,6 +1673,9 @@ void gen8_de_irq_postinstall(struct drm_i915_private
*dev_priv)
de_port_masked |= DSI0_TE | DSI1_TE;
}
+ if (DISPLAY_VER(dev_priv) == 14)
+ de_misc_masked |= GEN8_DE_RM_TIMEOUT;
+
de_pipe_enables = de_pipe_masked |
GEN8_PIPE_VBLANK |
gen8_de_pipe_underrun_mask(dev_priv) |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 875d76fb8cd0..d1692b32bb8a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4212,6 +4212,8 @@
#define RM_TIMEOUT _MMIO(0x42060)
#define MMIO_TIMEOUT_US(us) ((us) << 0)
+#define RMTIMEOUTREG_CAPTURE _MMIO(0x420e0)
+
/* interrupts */
#define DE_MASTER_IRQ_CONTROL (1 << 31)
#define DE_SPRITEB_FLIP_DONE(1 << 29)
@@ -4398,6 +4400,7 @@
#define GEN8_DE_MISC_IMR _MMIO(0x44464)
#define GEN8_DE_MISC_IIR _MMIO(0x44468)
#define GEN8_DE_MISC_IER _MMIO(0x4446c)
+#define GEN8_DE_RM_TIMEOUTREG_BIT(29)
#define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27)
#define GEN8_DE_MISC_GSE REG_BIT(27)
#define GEN8_DE_EDP_PSR REG_BIT(19)
--
2.25.1
[PATCH v2 17/25] drm/i915/xe2hpd: Add max memory bandwidth algorithm
From: Matt Roper
Unlike DG2, Xe2_HPD does support multiple GV points with different
maximum memory bandwidths, but uses a much simpler algorithm than igpu
platforms use.
Bspec: 64631
Signed-off-by: Matt Roper
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_bw.c | 65 -
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/soc/intel_dram.c | 4 ++
3 files changed, 68 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 7f2a50b4f494..dc9ac4831065 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -22,6 +22,8 @@ struct intel_qgv_point {
u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
};
+#define DEPROGBWPCLIMIT60
+
struct intel_psf_gv_point {
u8 clk; /* clock in multiples of 16. MHz */
};
@@ -239,6 +241,9 @@ static int icl_get_qgv_points(struct drm_i915_private
*dev_priv,
qi->channel_width = 16;
qi->deinterleave = 4;
break;
+ case INTEL_DRAM_GDDR:
+ qi->channel_width = 32;
+ break;
default:
MISSING_CASE(dram_info->type);
return -EINVAL;
@@ -383,6 +388,12 @@ static const struct intel_sa_info mtl_sa_info = {
.derating = 10,
};
+static const struct intel_sa_info xe2_hpd_sa_info = {
+ .derating = 30,
+ .deprogbwlimit = 53,
+ /* Other values not used by simplified algorithm */
+};
+
static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct
intel_sa_info *sa)
{
struct intel_qgv_info qi = {};
@@ -489,7 +500,7 @@ static int tgl_get_bw_info(struct drm_i915_private
*dev_priv, const struct intel
dclk_max = icl_sagv_max_dclk();
peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
- maxdebw = min(sa->deprogbwlimit * 1000, peakbw * 6 / 10); /* 60% */
+ maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
/*
@@ -594,6 +605,54 @@ static void dg2_get_bw_info(struct drm_i915_private *i915)
i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
}
+static int xe2_hpd_get_bw_info(struct drm_i915_private *i915,
+ const struct intel_sa_info *sa)
+{
+ struct intel_qgv_info qi = {};
+ int num_channels = i915->dram_info.num_channels;
+ int peakbw, maxdebw;
+ int ret, i;
+
+ ret = icl_get_qgv_points(i915, , true);
+ if (ret) {
+ drm_dbg_kms(>drm,
+ "Failed to get memory subsystem information,
ignoring bandwidth limits");
+ return ret;
+ }
+
+ peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk();
+ maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
+
+ for (i = 0; i < qi.num_points; i++) {
+ const struct intel_qgv_point *point = [i];
+ int bw = num_channels * (qi.channel_width / 8) * point->dclk;
+
+ i915->display.bw.max[0].deratedbw[i] =
+ min(maxdebw, (100 - sa->derating) * bw / 100);
+ i915->display.bw.max[0].peakbw[i] = bw;
+
+ drm_dbg_kms(>drm, "QGV %d: deratedbw=%u peakbw: %u\n",
+ i, i915->display.bw.max[0].deratedbw[i],
+ i915->display.bw.max[0].peakbw[i]);
+ }
+
+ /* Bandwidth does not depend on # of planes; set all groups the same */
+ i915->display.bw.max[0].num_planes = 1;
+ i915->display.bw.max[0].num_qgv_points = qi.num_points;
+ for (i = 1; i < ARRAY_SIZE(i915->display.bw.max); i++)
+ memcpy(>display.bw.max[i], >display.bw.max[0],
+ sizeof(i915->display.bw.max[0]));
+
+ /*
+* Xe2_HPD should always have exactly two QGV points representing
+* battery and plugged-in operation.
+*/
+ drm_WARN_ON(>drm, qi.num_points != 2);
+ i915->display.sagv.status = I915_SAGV_ENABLED;
+
+ return 0;
+}
+
static unsigned int icl_max_bw_index(struct drm_i915_private *dev_priv,
int num_planes, int qgv_point)
{
@@ -664,7 +723,9 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (DISPLAY_VER(dev_priv) >= 14)
+ if (DISPLAY_VER_FULL(dev_priv) >= IP_VER(14, 1) && IS_DGFX(dev_priv))
+ xe2_hpd_get_bw_info(dev_priv, _hpd_sa_info);
+ else if (DISPLAY_VER(dev_priv) >= 14)
tgl_get_bw_info(dev_priv, _sa_info);
else if (IS_DG2(dev_priv))
dg2_get_bw_info(dev_priv);
diff --git
[PATCH v2 16/25] drm/xe/xe2hpd: Define a new DRAM type INTEL_DRAM_GDDR
Defined a new DRAM type to be used in the following patches.
The following patch first makes use of this new type in the i915
display. So without this define, build would fail when the shared
display code is built for Xe.
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/xe/xe_device_types.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h
b/drivers/gpu/drm/xe/xe_device_types.h
index 1df3dcc17d75..e7aa2dd3df8d 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -480,6 +480,7 @@ struct xe_device {
INTEL_DRAM_LPDDR4,
INTEL_DRAM_DDR5,
INTEL_DRAM_LPDDR5,
+ INTEL_DRAM_GDDR,
} type;
u8 num_qgv_points;
u8 num_psf_gv_points;
--
2.25.1
[PATCH v2 15/25] drm/xe/display: Lane reversal requires writes to both context lanes
From: Clint Taylor
Write both CX0 Lanes for Context Toggle for all except TC pin assignment D.
BSPEC: 64539
Signed-off-by: Clint Taylor
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 20035be015c3..cbcb6651dfed 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2558,7 +2558,7 @@ static void intel_c20_pll_program(struct drm_i915_private
*i915,
{
const struct intel_c20pll_state *pll_state =
_state->cx0pll_state.c20;
bool dp = false;
- int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES :
INTEL_CX0_LANE0;
+ u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
u32 clock = crtc_state->port_clock;
bool cntx;
int i;
@@ -2634,19 +2634,19 @@ static void intel_c20_pll_program(struct
drm_i915_private *i915,
}
/* 4. Program custom width to match the link protocol */
- intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_WIDTH,
+ intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_WIDTH,
PHY_C20_CUSTOM_WIDTH_MASK,
PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(clock,
dp)),
MB_WRITE_COMMITTED);
/* 5. For DP or 6. For HDMI */
if (dp) {
- intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,
+ intel_cx0_rmw(encoder, owned_lane_mask,
PHY_C20_VDR_CUSTOM_SERDES_RATE,
BIT(6) | PHY_C20_CUSTOM_SERDES_MASK,
BIT(6) |
PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(clock)),
MB_WRITE_COMMITTED);
} else {
- intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,
+ intel_cx0_rmw(encoder, owned_lane_mask,
PHY_C20_VDR_CUSTOM_SERDES_RATE,
BIT(7) | PHY_C20_CUSTOM_SERDES_MASK,
is_hdmi_frl(clock) ? BIT(7) : 0,
MB_WRITE_COMMITTED);
@@ -2660,7 +2660,7 @@ static void intel_c20_pll_program(struct drm_i915_private
*i915,
* 7. Write Vendor specific registers to toggle context setting to load
* the updated programming toggle context bit
*/
- intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,
+ intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED);
}
--
2.25.1
[PATCH v2 14/25] drm/i915/xe2hpd: Add missing chicken bit register programming
From: Anusha Srivatsa Add step 9 from initialize display sequence. Bpsec: 49189 Signed-off-by: Anusha Srivatsa Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_display_power.c | 4 drivers/gpu/drm/i915/i915_reg.h| 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 6fd4fa52253a..bf9685acf75a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1694,6 +1694,10 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, if (IS_DG2(dev_priv)) intel_snps_phy_wait_for_calibration(dev_priv); + /* 9. XE2_HPD: Program CHICKEN_MISC_2 before any cursor or planes are enabled */ + if (DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 1)) + intel_de_rmw(dev_priv, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1); + if (resume) intel_dmc_load_program(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 58f3e4bfe254..875d76fb8cd0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4548,6 +4548,7 @@ #define CHICKEN_MISC_2 _MMIO(0x42084) #define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */ +#define BMG_DARB_HALF_BLK_END_BURST REG_BIT(27) #define KBL_ARB_FILL_SPARE_14REG_BIT(14) #define KBL_ARB_FILL_SPARE_13REG_BIT(13) #define GLK_CL2_PWR_DOWN REG_BIT(12) -- 2.25.1
[PATCH v2 13/25] drm/i915/xe2hpd: Add display info
From: Lucas De Marchi
Add initial display info for xe2hpd. It is similar to xelpd, but with no
PORT_B.
Bspec: 67066
Signed-off-by: Lucas De Marchi
Signed-off-by: Balasubramani Vivekanandan
---
.../gpu/drm/i915/display/intel_display_device.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index b8903bd0e82a..0a26012041e9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -771,6 +771,21 @@ static const struct intel_display_device_info
xe2_lpd_display = {
BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D),
};
+static const struct intel_display_device_info xe2_hpd_display = {
+ XE_LPD_FEATURES,
+ .has_cdclk_crawl = 1,
+ .has_cdclk_squash = 1,
+
+ .__runtime_defaults.ip.ver = 14,
+ .__runtime_defaults.ip.rel = 1,
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
+ .__runtime_defaults.port_mask = BIT(PORT_A) |
+ BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
+};
+
__diag_pop();
/*
@@ -852,6 +867,7 @@ static const struct {
const struct intel_display_device_info *display;
} gmdid_display_map[] = {
{ 14, 0, _lpdp_display },
+ { 14, 1, _hpd_display },
{ 20, 0, _lpd_display },
};
--
2.25.1
[PATCH v2 12/25] drm/i915/xe2hpd: update pll values in sync with Bspec
From: Ravi Kumar Vodapalli
DP/eDP and HDMI pll values are updated for Xe2_HPD platform
Bspec: 74165
Signed-off-by: Ravi Kumar Vodapalli
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 47 +++-
1 file changed, 45 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index d948035f07ad..20035be015c3 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -1109,6 +1109,42 @@ static const struct intel_c20pll_state * const
xe2hpd_c20_edp_tables[] = {
NULL,
};
+static const struct intel_c20pll_state xe2hpd_c20_dp_uhbr13_5 = {
+ .clock = 135, /* 13.5 Gbps */
+ .tx = { 0xbea0, /* tx cfg0 */
+ 0x4800, /* tx cfg1 */
+ 0x, /* tx cfg2 */
+ },
+ .cmn = {0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x, /* cmn cfg2 */
+ 0x, /* cmn cfg3 */
+ },
+ .mpllb = { 0x015f, /* mpllb cfg0 */
+ 0x2205, /* mpllb cfg1 */
+ 0x1b17, /* mpllb cfg2 */
+ 0xffc1, /* mpllb cfg3 */
+ 0xbd00, /* mpllb cfg4 */
+ 0x9ec3, /* mpllb cfg5 */
+ 0x2000, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x4800, /* mpllb cfg8 */
+ 0x, /* mpllb cfg9 */
+ 0x, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state * const xe2hpd_c20_dp_tables[] = {
+ _c20_dp_rbr,
+ _c20_dp_hbr1,
+ _c20_dp_hbr2,
+ _c20_dp_hbr3,
+ _c20_dp_uhbr10,
+ _c20_dp_uhbr13_5,
+ _c20_dp_uhbr20,
+ NULL,
+};
+
/*
* HDMI link rates with 38.4 MHz reference clock.
*/
@@ -2225,13 +2261,20 @@ static const struct intel_c20pll_state * const *
intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
- if (intel_crtc_has_dp_encoder(crtc_state))
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+ if (intel_crtc_has_dp_encoder(crtc_state)) {
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
return xe2hpd_c20_edp_tables;
+
+ if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
+ return xe2hpd_c20_dp_tables;
else
return mtl_c20_dp_tables;
- else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+
+ } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
return mtl_c20_hdmi_tables;
+ }
MISSING_CASE(encoder->type);
return NULL;
--
2.25.1
[PATCH v2 11/25] drm/i915/xe2hpd: Add support for eDP PLL configuration
Tables for eDP PHY PLL configuration for different link rates added for
Xe2_HPD. Previous platforms were using C10 PHY for eDP port whereas
Xe2_HPD has C20 PHY.
Bpsec: 64568
CC: Clint Taylor
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 147 ++-
1 file changed, 146 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 6e4647859fc6..d948035f07ad 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -967,6 +967,148 @@ static const struct intel_c20pll_state * const
mtl_c20_dp_tables[] = {
NULL,
};
+/*
+ * eDP link rates with 38.4 MHz reference clock.
+ */
+
+static const struct intel_c20pll_state xe2hpd_c20_edp_r216 = {
+ .clock = 216000,
+ .tx = { 0xbe88,
+ 0x4800,
+ 0x,
+ },
+ .cmn = { 0x0500,
+0x0005,
+0x,
+0x,
+ },
+ .mpllb = { 0x50e1,
+ 0x2120,
+ 0x8e18,
+ 0xbfc1,
+ 0x9000,
+ 0x78f6,
+ 0x,
+ 0x,
+ 0x,
+ 0x,
+ 0x,
+ },
+};
+
+static const struct intel_c20pll_state xe2hpd_c20_edp_r243 = {
+ .clock = 243000,
+ .tx = { 0xbe88,
+ 0x4800,
+ 0x,
+ },
+ .cmn = { 0x0500,
+0x0005,
+0x,
+0x,
+ },
+ .mpllb = { 0x50fd,
+ 0x2120,
+ 0x8f18,
+ 0xbfc1,
+ 0xa200,
+ 0x8814,
+ 0x2000,
+ 0x0001,
+ 0x1000,
+ 0x,
+ 0x,
+ },
+};
+
+static const struct intel_c20pll_state xe2hpd_c20_edp_r324 = {
+ .clock = 324000,
+ .tx = { 0xbe88,
+ 0x4800,
+ 0x,
+ },
+ .cmn = { 0x0500,
+0x0005,
+0x,
+0x,
+ },
+ .mpllb = { 0x30a8,
+ 0x2110,
+ 0xcd9a,
+ 0xbfc1,
+ 0x6c00,
+ 0x5ab8,
+ 0x2000,
+ 0x0001,
+ 0x6000,
+ 0x,
+ 0x,
+ },
+};
+
+static const struct intel_c20pll_state xe2hpd_c20_edp_r432 = {
+ .clock = 432000,
+ .tx = { 0xbe88,
+ 0x4800,
+ 0x,
+ },
+ .cmn = { 0x0500,
+0x0005,
+0x,
+0x,
+ },
+ .mpllb = { 0x30e1,
+ 0x2110,
+ 0x8e18,
+ 0xbfc1,
+ 0x9000,
+ 0x78f6,
+ 0x,
+ 0x,
+ 0x,
+ 0x,
+ 0x,
+ },
+};
+
+static const struct intel_c20pll_state xe2hpd_c20_edp_r675 = {
+ .clock = 675000,
+ .tx = { 0xbe88,
+ 0x4800,
+ 0x,
+ },
+ .cmn = { 0x0500,
+0x0005,
+0x,
+0x,
+ },
+ .mpllb = { 0x10af,
+ 0x2108,
+ 0xce1a,
+ 0xbfc1,
+ 0x7080,
+ 0x5e80,
+ 0x2000,
+ 0x0001,
+ 0x6400,
+ 0x,
+ 0x,
+ },
+};
+
+static const struct intel_c20pll_state * const xe2hpd_c20_edp_tables[] = {
+ _c20_dp_rbr,
+ _c20_edp_r216,
+ _c20_edp_r243,
+ _c20_dp_hbr1,
+ _c20_edp_r324,
+ _c20_edp_r432,
+ _c20_dp_hbr2,
+ _c20_edp_r675,
+ _c20_dp_hbr3,
+ NULL,
+};
+
/*
* HDMI link rates with 38.4 MHz reference clock.
*/
@@ -2084,7 +2226,10 @@ intel_c20_pll_tables_get(struct intel_crtc_state
*crtc_state,
struct intel_encoder *encoder)
{
if (intel_crtc_has_dp_encoder(crtc_state))
- return mtl_c20_dp_tables;
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+ return xe2hpd_c20_edp_tables;
+ else
+ return mtl_c20_dp_tables;
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
return mtl_c20_hdmi_tables;
--
2.25.1
[PATCH v2 10/25] drm/i915/xe2hpd: Add new C20 PLL register address
Xe2_HPD has different address for C20 PLL registers. Enable the support
to use the right PLL register address based on display version.
Note that Xe2_LPD uses the same C20 SRAM offsets used by Xe_LPDP (i.e.
MTL's display). According to the BSpec, currently, only Xe2_HPD has
different offsets, so make sure it is the only display using them in the
driver.
Bspec: 67610
Cc: Clint Taylor
Cc: Gustavo Sousa
Signed-off-by: Balasubramani Vivekanandan
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27 +--
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 9 +++
2 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index caaae5d3758e..6e4647859fc6 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -770,6 +770,17 @@ static struct intel_c20pll_reg mtl_c20_reg = {
.mpllb_b = MTL_C20_B_MPLLB_CFG_ADDR
};
+static struct intel_c20pll_reg xe2hpd_c20_reg = {
+ .tx_cnt_a = XE2HPD_C20_A_TX_CNTX_CFG_ADDR,
+ .tx_cnt_b = XE2HPD_C20_B_TX_CNTX_CFG_ADDR,
+ .cmn_cnt_a = XE2HPD_C20_A_CMN_CNTX_CFG_ADDR,
+ .cmn_cnt_b = XE2HPD_C20_B_CMN_CNTX_CFG_ADDR,
+ .mplla_a = XE2HPD_C20_A_MPLLA_CFG_ADDR,
+ .mplla_b = XE2HPD_C20_B_MPLLA_CFG_ADDR,
+ .mpllb_a = XE2HPD_C20_A_MPLLB_CFG_ADDR,
+ .mpllb_b = XE2HPD_C20_B_MPLLB_CFG_ADDR,
+};
+
/* C20 basic DP 1.4 tables */
static const struct intel_c20pll_state mtl_c20_dp_rbr = {
.clock = 162000,
@@ -2166,19 +2177,29 @@ static int intel_c20pll_calc_port_clock(struct
intel_encoder *encoder,
return vco << tx_rate_mult >> tx_clk_div >> tx_rate;
}
+static struct intel_c20pll_reg *intel_c20_get_pll_reg(struct drm_i915_private
*i915)
+{
+ if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
+ return _c20_reg;
+ else
+ return _c20_reg;
+}
+
static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
struct intel_c20pll_state *pll_state)
{
bool cntx;
intel_wakeref_t wakeref;
int i;
- struct intel_c20pll_reg *pll_reg = _c20_reg;
+ struct intel_c20pll_reg *pll_reg;
wakeref = intel_cx0_phy_transaction_begin(encoder);
/* 1. Read current context selection */
cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0,
PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;
+ pll_reg = intel_c20_get_pll_reg(to_i915(encoder->base.dev));
+
/* Read Tx configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
if (cntx)
@@ -2353,7 +2374,7 @@ static void intel_c20_pll_program(struct drm_i915_private
*i915,
u32 clock = crtc_state->port_clock;
bool cntx;
int i;
- const struct intel_c20pll_reg *pll_reg = _c20_reg;
+ const struct intel_c20pll_reg *pll_reg;
if (intel_crtc_has_dp_encoder(crtc_state))
dp = true;
@@ -2372,6 +2393,8 @@ static void intel_c20_pll_program(struct drm_i915_private
*i915,
usleep_range(4000, 4100);
}
+ pll_reg = intel_c20_get_pll_reg(i915);
+
/* 3. Write SRAM configuration context. If A in use, write
configuration to B context */
/* 3.1 Tx configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 882b98dc347b..8e5fd605b99e 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -292,6 +292,15 @@ struct intel_c20pll_reg {
#define MTL_C20_A_MPLLB_CFG_ADDR 0xCB5A
#define MTL_C20_B_MPLLB_CFG_ADDR 0xCB4E
+#define XE2HPD_C20_A_TX_CNTX_CFG_ADDR 0xCF5E
+#define XE2HPD_C20_B_TX_CNTX_CFG_ADDR 0xCF5A
+#define XE2HPD_C20_A_CMN_CNTX_CFG_ADDR 0xCE8E
+#define XE2HPD_C20_B_CMN_CNTX_CFG_ADDR 0xCE89
+#define XE2HPD_C20_A_MPLLA_CFG_ADDR0xCE58
+#define XE2HPD_C20_B_MPLLA_CFG_ADDR0xCE4D
+#define XE2HPD_C20_A_MPLLB_CFG_ADDR0xCCC2
+#define XE2HPD_C20_B_MPLLB_CFG_ADDR0xCCB6
+
/* C20 Phy VSwing Masks */
#define C20_PHY_VSWING_PREEMPH_MASKREG_GENMASK8(5, 0)
#define C20_PHY_VSWING_PREEMPH(val)
REG_FIELD_PREP8(C20_PHY_VSWING_PREEMPH_MASK, val)
--
2.25.1
[PATCH v2 09/25] drm/i915/xe2hpd: Properly disable power in port A
From: José Roberto de Souza
Xe2_HPD has a different value to power down port A.
BSpec: 65450
CC: Matt Roper
Signed-off-by: José Roberto de Souza
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 13a2e3db2812..caaae5d3758e 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2921,17 +2921,28 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder,
intel_cx0pll_enable(encoder, crtc_state);
}
+static u8 cx0_power_control_disable_val(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+ if (intel_encoder_is_c10phy(encoder))
+ return CX0_P2PG_STATE_DISABLE;
+
+ if (IS_BATTLEMAGE(i915) && encoder->port == PORT_A)
+ return CX0_P2PG_STATE_DISABLE;
+
+ return CX0_P4PG_STATE_DISABLE;
+}
+
static void intel_cx0pll_disable(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_encoder_to_phy(encoder);
- bool is_c10 = intel_encoder_is_c10phy(encoder);
intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);
/* 1. Change owned PHY lane power to Disable state. */
intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
- is_c10 ? CX0_P2PG_STATE_DISABLE :
- CX0_P4PG_STATE_DISABLE);
+
cx0_power_control_disable_val(encoder));
/*
* 2. Follow the Display Voltage Frequency Switching Sequence Before
--
2.25.1
[PATCH v2 08/25] drm/i915/bmg: Extend DG2 tc check to future
From: Radhakrishna Sripada
Discrete cards use the Port numbers TC1-4 for the offsets. The regular
flow for type-c subsystem port initialization can be skipped. This check
is present in DG2. Extend this to future discrete products.
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_display.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 614e60420a29..aed25890b6f5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1861,11 +1861,10 @@ bool intel_phy_is_combo(struct drm_i915_private
*dev_priv, enum phy phy)
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
/*
-* DG2's "TC1", although TC-capable output, doesn't share the same flow
-* as other platforms on the display engine side and rather rely on the
-* SNPS PHY, that is programmed separately
+* Discrete GPU phy's are not attached to FIA's to support TC
+* subsystem Legacy or non-legacy, and only support native DP/HDMI
*/
- if (IS_DG2(dev_priv))
+ if (IS_DGFX(dev_priv))
return false;
if (DISPLAY_VER(dev_priv) >= 13)
--
2.25.1
[PATCH v2 07/25] Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping"
From: Ankit Nautiyal
This reverts commit 562f33836f519a235e5c5e71bcc723ab1faccd2f.
For BMG it seems that the VBT to DDI mapping does not follow DG1, and
DG2, but follows ADLP mapping given in Bspec:20124.
Signed-off-by: Ankit Nautiyal
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_bios.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 2abd2d7ceda2..03fbd6c73f3f 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2238,15 +2238,14 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8
vbt_pin)
const u8 *ddc_pin_map;
int i, n_entries;
- if (IS_DGFX(i915))
- return vbt_pin;
-
if (INTEL_PCH_TYPE(i915) >= PCH_MTL || IS_ALDERLAKE_P(i915)) {
ddc_pin_map = adlp_ddc_pin_map;
n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
} else if (IS_ALDERLAKE_S(i915)) {
ddc_pin_map = adls_ddc_pin_map;
n_entries = ARRAY_SIZE(adls_ddc_pin_map);
+ } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
+ return vbt_pin;
} else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) {
ddc_pin_map = rkl_pch_tgp_ddc_pin_map;
n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);
--
2.25.1
[PATCH v2 06/25] drm/i915/xe2hpd: Initial cdclk table
From: Clint Taylor
Add Xe2_HPD specific CDCLK table and use MTL Funcs.
Bspec: 65243
Cc: Matt Roper
CC: Lucas De Marchi
Signed-off-by: Clint Taylor
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 31aaa9780dfc..da16c308670f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1444,6 +1444,14 @@ static const struct intel_cdclk_vals
xe2lpd_cdclk_table[] = {
{}
};
+/*
+ * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771
+ */
+static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x },
+ {}
+};
+
static const int cdclk_squash_len = 16;
static int cdclk_squash_divider(u16 waveform)
@@ -3768,6 +3776,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private
*dev_priv)
if (DISPLAY_VER(dev_priv) >= 20) {
dev_priv->display.funcs.cdclk = _cdclk_funcs;
dev_priv->display.cdclk.table = xe2lpd_cdclk_table;
+ } else if (DISPLAY_VER_FULL(dev_priv) >= IP_VER(14, 1)) {
+ dev_priv->display.funcs.cdclk = _cdclk_funcs;
+ dev_priv->display.cdclk.table = xe2hpd_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 14) {
dev_priv->display.funcs.cdclk = _cdclk_funcs;
dev_priv->display.cdclk.table = mtl_cdclk_table;
--
2.25.1
[PATCH v2 05/25] drm/i915/xe2: Skip CCS modifiers for Xe2 platforms
Xe2 platforms doesn't support Aux CCS and the Flat CCS is enabled
through PAT. No CCS modifiers required for Xe2 platforms.
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_fb.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 3ea6470d6d92..923e97c3aa6c 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -431,9 +431,17 @@ static bool plane_has_modifier(struct drm_i915_private
*i915,
* Separate AuxCCS and Flat CCS modifiers to be run only on platforms
* where supported.
*/
- if (intel_fb_is_ccs_modifier(md->modifier) &&
- HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes)
- return false;
+ if (intel_fb_is_ccs_modifier(md->modifier)) {
+ /*
+* No CCS modifiers available on Xe2 platforms as they don't
+* support Aux CCS and the Flat CCS is enabled via PAT
+*/
+ if ((DISPLAY_VER(i915) >= 20) || IS_BATTLEMAGE(i915))
+ return false;
+
+ if (HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes)
+ return false;
+ }
return true;
}
--
2.25.1
[PATCH v2 04/25] drm/i915/bmg: Define IS_BATTLEMAGE macro
Display code uses IS_BATTLEMAGE macro but the platform support doesn't still exist in i915. So fake IS_BATTLEMAGE macro defined to enable building i915 code. We should make sure the macro parameter is used in the always-false expression so that we don't run into "unused variable" warnings from i915 builds if the IS_BATTLEMAGE() check is the only place the i915 pointer gets used in a function. While we're at it, also update the IS_LUNARLAKE macro to include the parameter in the false expression for consistency. Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/i915_drv.h | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index cf52d4adaa20..b41a414079f4 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -546,7 +546,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P) #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2) #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE) -#define IS_LUNARLAKE(i915) 0 +/* + * Display code shared by i915 and Xe relies on macros like IS_LUNARLAKE, + * so we need to define these even on platforms that the i915 base driver + * doesn't support. Ensure the parameter is used in the definition to + * avoid 'unused variable' warnings when compiling the shared display code + * for i915. + */ +#define IS_LUNARLAKE(i915) (0 && i915) +#define IS_BATTLEMAGE(i915) (0 && i915) #define IS_DG2_G10(i915) \ IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10) -- 2.25.1
[PATCH v2 03/25] drm/xe/bmg: Define IS_BATTLEMAGE macro
Common display code requires IS_BATTLEMAGE macro. Defined the macro. Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h index a01d1b869c2d..9161d1fdf239 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h @@ -88,6 +88,7 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2) #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE) #define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE) +#define IS_BATTLEMAGE(dev_priv) IS_PLATFORM(dev_priv, XE_BATTLEMAGE) #define IS_HASWELL_ULT(dev_priv) (dev_priv && 0) #define IS_BROADWELL_ULT(dev_priv) (dev_priv && 0) -- 2.25.1
[PATCH v2 02/25] drm/xe/bmg: Add BMG platform definition
From: Matt Roper
BMG is a discrete GPU based on the Xe2 architecture.
Bspec: 68090
Signed-off-by: Matt Roper
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/xe/xe_pci.c| 7 +++
drivers/gpu/drm/xe/xe_platform_types.h | 1 +
include/drm/xe_pciids.h| 7 +++
3 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index c47ab4b67467..b3158053baee 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -337,6 +337,12 @@ static const struct xe_device_desc lnl_desc = {
.require_force_probe = true,
};
+static const struct xe_device_desc bmg_desc = {
+ DGFX_FEATURES,
+ PLATFORM(XE_BATTLEMAGE),
+ .require_force_probe = true,
+};
+
#undef PLATFORM
__diag_pop();
@@ -379,6 +385,7 @@ static const struct pci_device_id pciidlist[] = {
XE_PVC_IDS(INTEL_VGA_DEVICE, _desc),
XE_MTL_IDS(INTEL_VGA_DEVICE, _desc),
XE_LNL_IDS(INTEL_VGA_DEVICE, _desc),
+ XE_BMG_IDS(INTEL_VGA_DEVICE, _desc),
{ }
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/xe/xe_platform_types.h
b/drivers/gpu/drm/xe/xe_platform_types.h
index 553f53dbd093..79b7042c4534 100644
--- a/drivers/gpu/drm/xe/xe_platform_types.h
+++ b/drivers/gpu/drm/xe/xe_platform_types.h
@@ -22,6 +22,7 @@ enum xe_platform {
XE_PVC,
XE_METEORLAKE,
XE_LUNARLAKE,
+ XE_BATTLEMAGE,
};
enum xe_subplatform {
diff --git a/include/drm/xe_pciids.h b/include/drm/xe_pciids.h
index c7fc288dacee..73d972a8aca1 100644
--- a/include/drm/xe_pciids.h
+++ b/include/drm/xe_pciids.h
@@ -208,4 +208,11 @@
MACRO__(0x64A0, ## __VA_ARGS__), \
MACRO__(0x64B0, ## __VA_ARGS__)
+#define XE_BMG_IDS(MACRO__, ...) \
+ MACRO__(0xE202, ## __VA_ARGS__), \
+ MACRO__(0xE20B, ## __VA_ARGS__), \
+ MACRO__(0xE20C, ## __VA_ARGS__), \
+ MACRO__(0xE20D, ## __VA_ARGS__), \
+ MACRO__(0xE212, ## __VA_ARGS__)
+
#endif
--
2.25.1
[PATCH v2 01/25] drm/i915/display: Prepare to handle new C20 PLL register address
New platforms have different addresses for C20 PLL registers. This patch
prepares the driver to work with different register addresses.
New structure `struct intel_c20pll_reg` is created to hold the register
addresses for each platform with different register address.
CC: Clint Taylor
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 53 +--
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 36 ++---
2 files changed, 65 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index a2c4bf33155f..13a2e3db2812 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -759,6 +759,17 @@ static const struct intel_c10pll_state * const
mtl_c10_edp_tables[] = {
NULL,
};
+static struct intel_c20pll_reg mtl_c20_reg = {
+ .tx_cnt_a = MTL_C20_A_TX_CNTX_CFG_ADDR,
+ .tx_cnt_b = MTL_C20_B_TX_CNTX_CFG_ADDR,
+ .cmn_cnt_a = MTL_C20_A_CMN_CNTX_CFG_ADDR,
+ .cmn_cnt_b = MTL_C20_B_CMN_CNTX_CFG_ADDR,
+ .mplla_a = MTL_C20_A_MPLLA_CFG_ADDR,
+ .mplla_b = MTL_C20_B_MPLLA_CFG_ADDR,
+ .mpllb_a = MTL_C20_A_MPLLB_CFG_ADDR,
+ .mpllb_b = MTL_C20_B_MPLLB_CFG_ADDR
+};
+
/* C20 basic DP 1.4 tables */
static const struct intel_c20pll_state mtl_c20_dp_rbr = {
.clock = 162000,
@@ -2161,6 +2172,7 @@ static void intel_c20pll_readout_hw_state(struct
intel_encoder *encoder,
bool cntx;
intel_wakeref_t wakeref;
int i;
+ struct intel_c20pll_reg *pll_reg = _c20_reg;
wakeref = intel_cx0_phy_transaction_begin(encoder);
@@ -2171,20 +2183,20 @@ static void intel_c20pll_readout_hw_state(struct
intel_encoder *encoder,
for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
if (cntx)
pll_state->tx[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
-
PHY_C20_B_TX_CNTX_CFG(i));
+
PHY_C20_B_TX_CNTX_CFG(pll_reg, i));
else
pll_state->tx[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
-
PHY_C20_A_TX_CNTX_CFG(i));
+
PHY_C20_A_TX_CNTX_CFG(pll_reg, i));
}
/* Read common configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
if (cntx)
pll_state->cmn[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
-
PHY_C20_B_CMN_CNTX_CFG(i));
+
PHY_C20_B_CMN_CNTX_CFG(pll_reg, i));
else
pll_state->cmn[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
-
PHY_C20_A_CMN_CNTX_CFG(i));
+
PHY_C20_A_CMN_CNTX_CFG(pll_reg, i));
}
if (intel_c20phy_use_mpllb(pll_state)) {
@@ -2192,20 +2204,20 @@ static void intel_c20pll_readout_hw_state(struct
intel_encoder *encoder,
for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
if (cntx)
pll_state->mpllb[i] =
intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
-
PHY_C20_B_MPLLB_CNTX_CFG(i));
+
PHY_C20_B_MPLLB_CNTX_CFG(pll_reg, i));
else
pll_state->mpllb[i] =
intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
-
PHY_C20_A_MPLLB_CNTX_CFG(i));
+
PHY_C20_A_MPLLB_CNTX_CFG(pll_reg, i));
}
} else {
/* MPLLA configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
if (cntx)
pll_state->mplla[i] =
intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
-
PHY_C20_B_MPLLA_CNTX_CFG(i));
+
PHY_C20_B_MPLLA_CNTX_CFG(pll_reg, i));
else
pll_state->mplla[i] =
intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
-
PHY_C20_A_MPLLA_CNTX_CFG(i));
+
PHY_C20_A_MPLLA_CNTX_CFG(pll_reg, i));
[PATCH v2 00/25] Enable dislay support for Battlemage
Adds display support for Battlemage. Reuses the patch "drm/xe/bmg: Add BMG platform definition" from the patch series to help build this series. So that review on this series can continue without blocking on . v2: Rebased on latest drm-tip Ankit Nautiyal (1): Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping" Anusha Srivatsa (1): drm/i915/xe2hpd: Add missing chicken bit register programming Balasubramani Vivekanandan (9): drm/i915/display: Prepare to handle new C20 PLL register address drm/xe/bmg: Define IS_BATTLEMAGE macro drm/i915/bmg: Define IS_BATTLEMAGE macro drm/i915/xe2: Skip CCS modifiers for Xe2 platforms drm/i915/xe2hpd: Add new C20 PLL register address drm/i915/xe2hpd: Add support for eDP PLL configuration drm/xe/xe2hpd: Define a new DRAM type INTEL_DRAM_GDDR drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5 drm/xe/bmg: Enable the display support Clint Taylor (2): drm/i915/xe2hpd: Initial cdclk table drm/xe/display: Lane reversal requires writes to both context lanes José Roberto de Souza (2): drm/i915/xe2hpd: Properly disable power in port A drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits Lucas De Marchi (1): drm/i915/xe2hpd: Add display info Matt Roper (3): drm/xe/bmg: Add BMG platform definition drm/i915/xe2hpd: Add max memory bandwidth algorithm drm/i915/bmg: BMG should re-use MTL's south display logic Matthew Auld (2): drm/xe/gt_print: add xe_gt_err_once() drm/i915/display: perform transient flush Mitul Golani (1): drm/i915/display: Enable RM timeout detection Nirmoy Das (1): drm/xe/device: implement transient flush Radhakrishna Sripada (1): drm/i915/bmg: Extend DG2 tc check to future Ravi Kumar Vodapalli (1): drm/i915/xe2hpd: update pll values in sync with Bspec drivers/gpu/drm/i915/display/intel_bios.c | 5 +- drivers/gpu/drm/i915/display/intel_bw.c | 65 +++- drivers/gpu/drm/i915/display/intel_cdclk.c| 11 + drivers/gpu/drm/i915/display/intel_cx0_phy.c | 297 -- .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 45 ++- drivers/gpu/drm/i915/display/intel_display.c | 10 +- .../drm/i915/display/intel_display_device.c | 16 + .../gpu/drm/i915/display/intel_display_irq.c | 10 + .../drm/i915/display/intel_display_power.c| 4 + drivers/gpu/drm/i915/display/intel_dp.c | 3 + drivers/gpu/drm/i915/display/intel_fb.c | 14 +- .../gpu/drm/i915/display/intel_frontbuffer.c | 2 + drivers/gpu/drm/i915/display/intel_tdf.h | 25 ++ drivers/gpu/drm/i915/display/skl_watermark.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 11 +- drivers/gpu/drm/i915/i915_reg.h | 4 + drivers/gpu/drm/i915/soc/intel_dram.c | 4 + drivers/gpu/drm/i915/soc/intel_pch.c | 4 +- drivers/gpu/drm/xe/Makefile | 3 +- .../gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 + drivers/gpu/drm/xe/display/xe_tdf.c | 13 + drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 + drivers/gpu/drm/xe/xe_device.c| 52 +++ drivers/gpu/drm/xe/xe_device.h| 2 + drivers/gpu/drm/xe/xe_device_types.h | 1 + drivers/gpu/drm/xe/xe_gt_printk.h | 3 + drivers/gpu/drm/xe/xe_pci.c | 8 + drivers/gpu/drm/xe/xe_platform_types.h| 1 + include/drm/xe_pciids.h | 7 + 29 files changed, 574 insertions(+), 52 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_tdf.h create mode 100644 drivers/gpu/drm/xe/display/xe_tdf.c -- 2.25.1
✗ Fi.CI.BUILD: failure for Enable dislay support for Battlemage
== Series Details == Series: Enable dislay support for Battlemage URL : https://patchwork.freedesktop.org/series/131984/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/131984/revisions/1/mbox/ not applied Applying: drm/i915/display: Prepare to handle new C20 PLL register address Applying: drm/xe/bmg: Add BMG platform definition Applying: drm/xe/bmg: Define IS_BATTLEMAGE macro Applying: drm/i915/bmg: Define IS_BATTLEMAGE macro Applying: drm/i915/xe2: Skip CCS modifiers for Xe2 platforms Applying: drm/i915/xe2hpd: Initial cdclk table Applying: Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping" Applying: drm/i915/bmg: Extend DG2 tc check to future Applying: drm/i915/xe2hpd: Properly disable power in port A Applying: drm/i915/xe2hpd: Add new C20 PLL register address Applying: drm/i915/xe2hpd: Add support for eDP PLL configuration Applying: drm/i915/xe2hpd: update pll values in sync with Bspec Applying: drm/i915/xe2hpd: Add display info Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_display_device.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/display/intel_display_device.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_display_device.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0013 drm/i915/xe2hpd: Add display info When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". Build failed, no error log produced
Re: [PATCH 23/25] drm/xe/device: implement transient flush
There is new fixup patch(PR#630) which modifies this patch. Could you
please bring that in as well.
Regards,
Nirmoy
On 4/3/2024 12:51 PM, Balasubramani Vivekanandan wrote:
From: Nirmoy Das
Display surfaces can be tagged as transient by mapping it using one of
the various L3:XD PAT index modes on Xe2. The expectation is that KMD
needs to request transient data flush at the start of flip sequence to
ensure all transient data in L3 cache is flushed to memory. Add a
routine for this which we can then call from the display code.
Signed-off-by: Nirmoy Das
Co-developed-by: Matthew Auld
Signed-off-by: Matthew Auld
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 ++
drivers/gpu/drm/xe/xe_device.c | 49
drivers/gpu/drm/xe/xe_device.h | 2 ++
3 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index d5b21f03beaa..9c6549830e24 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -305,6 +305,9 @@
#define XE2LPM_L3SQCREG5 XE_REG_MCR(0xb658)
+#define XE2_TDF_CTRLXE_REG(0xb418)
+#define TRANSIENT_FLUSH_REQUEST REG_BIT(0)
+
#define XEHP_MERT_MOD_CTRLXE_REG_MCR(0xcf28)
#define RENDER_MOD_CTRL XE_REG_MCR(0xcf2c)
#define COMP_MOD_CTRL XE_REG_MCR(0xcf30)
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 01bd5ccf05ca..66182220e663 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -641,6 +641,55 @@ void xe_device_wmb(struct xe_device *xe)
xe_mmio_write32(gt, SOFTWARE_FLAGS_SPR33, 0);
}
+/**
+ * xe_device_td_flush() - Flush transient L3 cache entries
+ * @xe: The device
+ *
+ * Display engine has direct access to memory and is never coherent with L3/L4
+ * caches (or CPU caches), however KMD is responsible for specifically flushing
+ * transient L3 GPU cache entries prior to the flip sequence to ensure scanout
+ * can happen from such a surface without seeing corruption.
+ *
+ * Display surfaces can be tagged as transient by mapping it using one of the
+ * various L3:XD PAT index modes on Xe2.
+ *
+ * Note: On non-discrete xe2 platforms, like LNL, the entire L3 cache is
flushed
+ * at the end of each submission via PIPE_CONTROL for compute/render, since SA
+ * Media is not coherent with L3 and we want to support render-vs-media
+ * usescases. For other engines like copy/blt the HW internally forces uncached
+ * behaviour, hence why we can skip the TDF on such platforms.
+ */
+void xe_device_td_flush(struct xe_device *xe)
+{
+ struct xe_gt *gt;
+ u8 id;
+
+ if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20)
+ return;
+
+ for_each_gt(gt, xe, id) {
+ if (xe_gt_is_media_type(gt))
+ continue;
+
+ xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
+
+ xe_mmio_write32(gt, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST);
+ /*
+* FIXME: We can likely do better here with our choice of
+* timeout. Currently we just assume the worst case, but really
+* we should make this dependent on how much actual L3 there is
+* for this system. Recomendation is to allow ~64us in the worst
+* case for 8M of L3 (assumes all entries are transient and need
+* to be flushed).
+*/
+ if (xe_mmio_wait32(gt, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST, 0,
+ 150, NULL, false))
+ xe_gt_err_once(gt, "TD flush timeout\n");
+
+ xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
+ }
+}
+
u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size)
{
return xe_device_has_flat_ccs(xe) ?
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index d413bc2c6be5..d3430f4b820a 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -176,4 +176,6 @@ void xe_device_snapshot_print(struct xe_device *xe, struct
drm_printer *p);
u64 xe_device_canonicalize_addr(struct xe_device *xe, u64 address);
u64 xe_device_uncanonicalize_addr(struct xe_device *xe, u64 address);
+void xe_device_td_flush(struct xe_device *xe);
+
#endif
[PATCH 25/25] drm/xe/bmg: Enable the display support
Enable the display support for Battlemage
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/xe/xe_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index b3158053baee..835c18ec8fb9 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -340,6 +340,7 @@ static const struct xe_device_desc lnl_desc = {
static const struct xe_device_desc bmg_desc = {
DGFX_FEATURES,
PLATFORM(XE_BATTLEMAGE),
+ .has_display = true,
.require_force_probe = true,
};
--
2.25.1
[PATCH 24/25] drm/i915/display: perform transient flush
From: Matthew Auld
Perform manual transient cache flush prior to flip and at the end of
frontbuffer_flush. This is needed to ensure display engine doesn't see
garbage if the surface is L3:XD dirty.
Testcase: igt@xe-pat@display-vs-wb-transient
Signed-off-by: Matthew Auld
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
.../gpu/drm/i915/display/intel_frontbuffer.c | 2 ++
drivers/gpu/drm/i915/display/intel_tdf.h | 25 +++
drivers/gpu/drm/xe/Makefile | 3 ++-
drivers/gpu/drm/xe/display/xe_tdf.c | 13 ++
5 files changed, 45 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_tdf.h
create mode 100644 drivers/gpu/drm/xe/display/xe_tdf.c
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index aed25890b6f5..0a720e9d12a7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -110,6 +110,7 @@
#include "intel_sdvo.h"
#include "intel_snps_phy.h"
#include "intel_tc.h"
+#include "intel_tdf.h"
#include "intel_tv.h"
#include "intel_vblank.h"
#include "intel_vdsc.h"
@@ -7095,6 +7096,8 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
intel_atomic_commit_fence_wait(state);
+ intel_td_flush(dev_priv);
+
drm_atomic_helper_wait_for_dependencies(>base);
drm_dp_mst_atomic_wait_for_dependencies(>base);
intel_atomic_global_state_wait_for_dependencies(state);
diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
index 2ea37c0414a9..4923c340a0b6 100644
--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
@@ -65,6 +65,7 @@
#include "intel_fbc.h"
#include "intel_frontbuffer.h"
#include "intel_psr.h"
+#include "intel_tdf.h"
/**
* frontbuffer_flush - flush frontbuffer
@@ -93,6 +94,7 @@ static void frontbuffer_flush(struct drm_i915_private *i915,
trace_intel_frontbuffer_flush(i915, frontbuffer_bits, origin);
might_sleep();
+ intel_td_flush(i915);
intel_drrs_flush(i915, frontbuffer_bits);
intel_psr_flush(i915, frontbuffer_bits, origin);
intel_fbc_flush(i915, frontbuffer_bits, origin);
diff --git a/drivers/gpu/drm/i915/display/intel_tdf.h
b/drivers/gpu/drm/i915/display/intel_tdf.h
new file mode 100644
index ..353cde21f6c2
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_tdf.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef __INTEL_TDF_H__
+#define __INTEL_TDF_H__
+
+/*
+ * TDF (Transient-Data-Flush) is needed for Xe2+ where special L3:XD caching
can
+ * be enabled through various PAT index modes. Idea is to use this caching mode
+ * when for example rendering onto the display surface, with the promise that
+ * KMD will ensure transient cache entries are always flushed by the time we do
+ * the display flip, since display engine is never coherent with CPU/GPU
caches.
+ */
+
+struct drm_i915_private;
+
+#ifdef I915
+static inline void intel_td_flush(struct drm_i915_private *i915) {}
+#else
+void intel_td_flush(struct drm_i915_private *i915);
+#endif
+
+#endif
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 21316ee47026..71847e33f4c2 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -199,7 +199,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
display/xe_dsb_buffer.o \
display/xe_fb_pin.o \
display/xe_hdcp_gsc.o \
- display/xe_plane_initial.o
+ display/xe_plane_initial.o \
+ display/xe_tdf.o
# SOC code shared with i915
xe-$(CONFIG_DRM_XE_DISPLAY) += \
diff --git a/drivers/gpu/drm/xe/display/xe_tdf.c
b/drivers/gpu/drm/xe/display/xe_tdf.c
new file mode 100644
index ..2c0d4e144e09
--- /dev/null
+++ b/drivers/gpu/drm/xe/display/xe_tdf.c
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#include "xe_device.h"
+#include "intel_display_types.h"
+#include "intel_tdf.h"
+
+void intel_td_flush(struct drm_i915_private *i915)
+{
+ xe_device_td_flush(i915);
+}
--
2.25.1
[PATCH 23/25] drm/xe/device: implement transient flush
From: Nirmoy Das
Display surfaces can be tagged as transient by mapping it using one of
the various L3:XD PAT index modes on Xe2. The expectation is that KMD
needs to request transient data flush at the start of flip sequence to
ensure all transient data in L3 cache is flushed to memory. Add a
routine for this which we can then call from the display code.
Signed-off-by: Nirmoy Das
Co-developed-by: Matthew Auld
Signed-off-by: Matthew Auld
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 ++
drivers/gpu/drm/xe/xe_device.c | 49
drivers/gpu/drm/xe/xe_device.h | 2 ++
3 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index d5b21f03beaa..9c6549830e24 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -305,6 +305,9 @@
#define XE2LPM_L3SQCREG5 XE_REG_MCR(0xb658)
+#define XE2_TDF_CTRL XE_REG(0xb418)
+#define TRANSIENT_FLUSH_REQUEST REG_BIT(0)
+
#define XEHP_MERT_MOD_CTRL XE_REG_MCR(0xcf28)
#define RENDER_MOD_CTRLXE_REG_MCR(0xcf2c)
#define COMP_MOD_CTRL XE_REG_MCR(0xcf30)
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 01bd5ccf05ca..66182220e663 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -641,6 +641,55 @@ void xe_device_wmb(struct xe_device *xe)
xe_mmio_write32(gt, SOFTWARE_FLAGS_SPR33, 0);
}
+/**
+ * xe_device_td_flush() - Flush transient L3 cache entries
+ * @xe: The device
+ *
+ * Display engine has direct access to memory and is never coherent with L3/L4
+ * caches (or CPU caches), however KMD is responsible for specifically flushing
+ * transient L3 GPU cache entries prior to the flip sequence to ensure scanout
+ * can happen from such a surface without seeing corruption.
+ *
+ * Display surfaces can be tagged as transient by mapping it using one of the
+ * various L3:XD PAT index modes on Xe2.
+ *
+ * Note: On non-discrete xe2 platforms, like LNL, the entire L3 cache is
flushed
+ * at the end of each submission via PIPE_CONTROL for compute/render, since SA
+ * Media is not coherent with L3 and we want to support render-vs-media
+ * usescases. For other engines like copy/blt the HW internally forces uncached
+ * behaviour, hence why we can skip the TDF on such platforms.
+ */
+void xe_device_td_flush(struct xe_device *xe)
+{
+ struct xe_gt *gt;
+ u8 id;
+
+ if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20)
+ return;
+
+ for_each_gt(gt, xe, id) {
+ if (xe_gt_is_media_type(gt))
+ continue;
+
+ xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
+
+ xe_mmio_write32(gt, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST);
+ /*
+* FIXME: We can likely do better here with our choice of
+* timeout. Currently we just assume the worst case, but really
+* we should make this dependent on how much actual L3 there is
+* for this system. Recomendation is to allow ~64us in the worst
+* case for 8M of L3 (assumes all entries are transient and need
+* to be flushed).
+*/
+ if (xe_mmio_wait32(gt, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST, 0,
+ 150, NULL, false))
+ xe_gt_err_once(gt, "TD flush timeout\n");
+
+ xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
+ }
+}
+
u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size)
{
return xe_device_has_flat_ccs(xe) ?
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index d413bc2c6be5..d3430f4b820a 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -176,4 +176,6 @@ void xe_device_snapshot_print(struct xe_device *xe, struct
drm_printer *p);
u64 xe_device_canonicalize_addr(struct xe_device *xe, u64 address);
u64 xe_device_uncanonicalize_addr(struct xe_device *xe, u64 address);
+void xe_device_td_flush(struct xe_device *xe);
+
#endif
--
2.25.1
[PATCH 22/25] drm/xe/gt_print: add xe_gt_err_once()
From: Matthew Auld Needed in an upcoming patch, where we want GT level print, but only which to trigger once to avoid flooding dmesg. Signed-off-by: Matthew Auld Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/xe/xe_gt_printk.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_gt_printk.h b/drivers/gpu/drm/xe/xe_gt_printk.h index c2b004d3f48e..d6228baaff1e 100644 --- a/drivers/gpu/drm/xe/xe_gt_printk.h +++ b/drivers/gpu/drm/xe/xe_gt_printk.h @@ -13,6 +13,9 @@ #define xe_gt_printk(_gt, _level, _fmt, ...) \ drm_##_level(_to_xe(_gt)->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__) +#define xe_gt_err_once(_gt, _fmt, ...) \ + xe_gt_printk((_gt), err_once, _fmt, ##__VA_ARGS__) + #define xe_gt_err(_gt, _fmt, ...) \ xe_gt_printk((_gt), err, _fmt, ##__VA_ARGS__) -- 2.25.1
[PATCH 21/25] drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5
Max supported speed by xe2hpd is UHBR13.5. Limit the max DP source rate to it. Bspec: 67066 Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index b393ddbb7b35..d9d37f4971dd 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -466,6 +466,9 @@ static int mtl_max_source_rate(struct intel_dp *intel_dp) if (intel_encoder_is_c10phy(encoder)) return 81; + if (DISPLAY_VER_FULL(to_i915(encoder->base.dev)) == IP_VER(14, 1)) + return 135; + return 200; } -- 2.25.1
[PATCH 20/25] drm/i915/bmg: BMG should re-use MTL's south display logic
From: Matt Roper
Battlemage's south display is the same as Meteor Lake's, including the
need to invert the HPD pins, which Lunar Lake does not need.
Signed-off-by: Matt Roper
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/soc/intel_pch.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c
b/drivers/gpu/drm/i915/soc/intel_pch.c
index 3cad6dac06b0..542eea50093c 100644
--- a/drivers/gpu/drm/i915/soc/intel_pch.c
+++ b/drivers/gpu/drm/i915/soc/intel_pch.c
@@ -218,10 +218,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
if (DISPLAY_VER(dev_priv) >= 20) {
dev_priv->pch_type = PCH_LNL;
return;
- } else if (IS_METEORLAKE(dev_priv)) {
+ } else if (IS_BATTLEMAGE(dev_priv) || IS_METEORLAKE(dev_priv)) {
/*
* Both north display and south display are on the SoC die.
-* The real PCH is uninvolved in display.
+* The real PCH (if it even exists) is uninvolved in display.
*/
dev_priv->pch_type = PCH_MTL;
return;
--
2.25.1
[PATCH 19/25] drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits
From: José Roberto de Souza
Xe2_HPD doesn't have DBOX BW credits, so here programing it with
zero.
BSpec: 49213
Signed-off-by: José Roberto de Souza
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/skl_watermark.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index bc341abcab2f..22ae782e89f4 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3733,7 +3733,7 @@ void intel_mbus_dbox_update(struct intel_atomic_state
*state)
if (!new_crtc_state->hw.active)
continue;
- if (DISPLAY_VER(i915) >= 14) {
+ if (DISPLAY_VER(i915) >= 14 && !IS_BATTLEMAGE(i915)) {
if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
new_dbuf_state->active_pipes))
pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;
--
2.25.1
[PATCH 15/25] drm/xe/display: Lane reversal requires writes to both context lanes
From: Clint Taylor
Write both CX0 Lanes for Context Toggle for all except TC pin assignment D.
BSPEC: 64539
Signed-off-by: Clint Taylor
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 20035be015c3..cbcb6651dfed 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2558,7 +2558,7 @@ static void intel_c20_pll_program(struct drm_i915_private
*i915,
{
const struct intel_c20pll_state *pll_state =
_state->cx0pll_state.c20;
bool dp = false;
- int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES :
INTEL_CX0_LANE0;
+ u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
u32 clock = crtc_state->port_clock;
bool cntx;
int i;
@@ -2634,19 +2634,19 @@ static void intel_c20_pll_program(struct
drm_i915_private *i915,
}
/* 4. Program custom width to match the link protocol */
- intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_WIDTH,
+ intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_WIDTH,
PHY_C20_CUSTOM_WIDTH_MASK,
PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(clock,
dp)),
MB_WRITE_COMMITTED);
/* 5. For DP or 6. For HDMI */
if (dp) {
- intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,
+ intel_cx0_rmw(encoder, owned_lane_mask,
PHY_C20_VDR_CUSTOM_SERDES_RATE,
BIT(6) | PHY_C20_CUSTOM_SERDES_MASK,
BIT(6) |
PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(clock)),
MB_WRITE_COMMITTED);
} else {
- intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,
+ intel_cx0_rmw(encoder, owned_lane_mask,
PHY_C20_VDR_CUSTOM_SERDES_RATE,
BIT(7) | PHY_C20_CUSTOM_SERDES_MASK,
is_hdmi_frl(clock) ? BIT(7) : 0,
MB_WRITE_COMMITTED);
@@ -2660,7 +2660,7 @@ static void intel_c20_pll_program(struct drm_i915_private
*i915,
* 7. Write Vendor specific registers to toggle context setting to load
* the updated programming toggle context bit
*/
- intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,
+ intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED);
}
--
2.25.1
[PATCH 18/25] drm/i915/display: Enable RM timeout detection
From: Mitul Golani
Enable RM timeout interrupt to detect any hang during display engine
register access. This interrupt is supported only on Display version 14.
Current default timeout is 2ms.
WA: 14012195489
Bspec: 50110
CC: Suraj Kandpal
Signed-off-by: Mitul Golani
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 10 ++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
b/drivers/gpu/drm/i915/display/intel_display_irq.c
index f846c5b108b5..3035b50fcad9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -851,6 +851,13 @@ gen8_de_misc_irq_handler(struct drm_i915_private
*dev_priv, u32 iir)
{
bool found = false;
+ if (iir & GEN8_DE_RM_TIMEOUT) {
+ u32 val = intel_uncore_read(_priv->uncore,
+ RMTIMEOUTREG_CAPTURE);
+ drm_warn(_priv->drm, "Register Access Timeout = 0x%x\n",
val);
+ found = true;
+ }
+
if (DISPLAY_VER(dev_priv) >= 14) {
if (iir & (XELPDP_PMDEMAND_RSP |
XELPDP_PMDEMAND_RSPTOUT_ERR)) {
@@ -1666,6 +1673,9 @@ void gen8_de_irq_postinstall(struct drm_i915_private
*dev_priv)
de_port_masked |= DSI0_TE | DSI1_TE;
}
+ if (DISPLAY_VER(dev_priv) == 14)
+ de_misc_masked |= GEN8_DE_RM_TIMEOUT;
+
de_pipe_enables = de_pipe_masked |
GEN8_PIPE_VBLANK |
gen8_de_pipe_underrun_mask(dev_priv) |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 875d76fb8cd0..d1692b32bb8a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4212,6 +4212,8 @@
#define RM_TIMEOUT _MMIO(0x42060)
#define MMIO_TIMEOUT_US(us) ((us) << 0)
+#define RMTIMEOUTREG_CAPTURE _MMIO(0x420e0)
+
/* interrupts */
#define DE_MASTER_IRQ_CONTROL (1 << 31)
#define DE_SPRITEB_FLIP_DONE(1 << 29)
@@ -4398,6 +4400,7 @@
#define GEN8_DE_MISC_IMR _MMIO(0x44464)
#define GEN8_DE_MISC_IIR _MMIO(0x44468)
#define GEN8_DE_MISC_IER _MMIO(0x4446c)
+#define GEN8_DE_RM_TIMEOUTREG_BIT(29)
#define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27)
#define GEN8_DE_MISC_GSE REG_BIT(27)
#define GEN8_DE_EDP_PSR REG_BIT(19)
--
2.25.1
[PATCH 17/25] drm/i915/xe2hpd: Add max memory bandwidth algorithm
From: Matt Roper
Unlike DG2, Xe2_HPD does support multiple GV points with different
maximum memory bandwidths, but uses a much simpler algorithm than igpu
platforms use.
Bspec: 64631
Signed-off-by: Matt Roper
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_bw.c | 65 -
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/soc/intel_dram.c | 4 ++
3 files changed, 68 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 7f2a50b4f494..dc9ac4831065 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -22,6 +22,8 @@ struct intel_qgv_point {
u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
};
+#define DEPROGBWPCLIMIT60
+
struct intel_psf_gv_point {
u8 clk; /* clock in multiples of 16. MHz */
};
@@ -239,6 +241,9 @@ static int icl_get_qgv_points(struct drm_i915_private
*dev_priv,
qi->channel_width = 16;
qi->deinterleave = 4;
break;
+ case INTEL_DRAM_GDDR:
+ qi->channel_width = 32;
+ break;
default:
MISSING_CASE(dram_info->type);
return -EINVAL;
@@ -383,6 +388,12 @@ static const struct intel_sa_info mtl_sa_info = {
.derating = 10,
};
+static const struct intel_sa_info xe2_hpd_sa_info = {
+ .derating = 30,
+ .deprogbwlimit = 53,
+ /* Other values not used by simplified algorithm */
+};
+
static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct
intel_sa_info *sa)
{
struct intel_qgv_info qi = {};
@@ -489,7 +500,7 @@ static int tgl_get_bw_info(struct drm_i915_private
*dev_priv, const struct intel
dclk_max = icl_sagv_max_dclk();
peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
- maxdebw = min(sa->deprogbwlimit * 1000, peakbw * 6 / 10); /* 60% */
+ maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
/*
@@ -594,6 +605,54 @@ static void dg2_get_bw_info(struct drm_i915_private *i915)
i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
}
+static int xe2_hpd_get_bw_info(struct drm_i915_private *i915,
+ const struct intel_sa_info *sa)
+{
+ struct intel_qgv_info qi = {};
+ int num_channels = i915->dram_info.num_channels;
+ int peakbw, maxdebw;
+ int ret, i;
+
+ ret = icl_get_qgv_points(i915, , true);
+ if (ret) {
+ drm_dbg_kms(>drm,
+ "Failed to get memory subsystem information,
ignoring bandwidth limits");
+ return ret;
+ }
+
+ peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk();
+ maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
+
+ for (i = 0; i < qi.num_points; i++) {
+ const struct intel_qgv_point *point = [i];
+ int bw = num_channels * (qi.channel_width / 8) * point->dclk;
+
+ i915->display.bw.max[0].deratedbw[i] =
+ min(maxdebw, (100 - sa->derating) * bw / 100);
+ i915->display.bw.max[0].peakbw[i] = bw;
+
+ drm_dbg_kms(>drm, "QGV %d: deratedbw=%u peakbw: %u\n",
+ i, i915->display.bw.max[0].deratedbw[i],
+ i915->display.bw.max[0].peakbw[i]);
+ }
+
+ /* Bandwidth does not depend on # of planes; set all groups the same */
+ i915->display.bw.max[0].num_planes = 1;
+ i915->display.bw.max[0].num_qgv_points = qi.num_points;
+ for (i = 1; i < ARRAY_SIZE(i915->display.bw.max); i++)
+ memcpy(>display.bw.max[i], >display.bw.max[0],
+ sizeof(i915->display.bw.max[0]));
+
+ /*
+* Xe2_HPD should always have exactly two QGV points representing
+* battery and plugged-in operation.
+*/
+ drm_WARN_ON(>drm, qi.num_points != 2);
+ i915->display.sagv.status = I915_SAGV_ENABLED;
+
+ return 0;
+}
+
static unsigned int icl_max_bw_index(struct drm_i915_private *dev_priv,
int num_planes, int qgv_point)
{
@@ -664,7 +723,9 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (DISPLAY_VER(dev_priv) >= 14)
+ if (DISPLAY_VER_FULL(dev_priv) >= IP_VER(14, 1) && IS_DGFX(dev_priv))
+ xe2_hpd_get_bw_info(dev_priv, _hpd_sa_info);
+ else if (DISPLAY_VER(dev_priv) >= 14)
tgl_get_bw_info(dev_priv, _sa_info);
else if (IS_DG2(dev_priv))
dg2_get_bw_info(dev_priv);
diff --git
[PATCH 16/25] drm/xe/xe2hpd: Define a new DRAM type INTEL_DRAM_GDDR
Defined a new DRAM type to be used in the following patches.
The following patch first makes use of this new type in the i915
display. So without this define, build would fail when the shared
display code is built for Xe.
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/xe/xe_device_types.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h
b/drivers/gpu/drm/xe/xe_device_types.h
index 1df3dcc17d75..e7aa2dd3df8d 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -480,6 +480,7 @@ struct xe_device {
INTEL_DRAM_LPDDR4,
INTEL_DRAM_DDR5,
INTEL_DRAM_LPDDR5,
+ INTEL_DRAM_GDDR,
} type;
u8 num_qgv_points;
u8 num_psf_gv_points;
--
2.25.1
[PATCH 08/25] drm/i915/bmg: Extend DG2 tc check to future
From: Radhakrishna Sripada
Discrete cards use the Port numbers TC1-4 for the offsets. The regular
flow for type-c subsystem port initialization can be skipped. This check
is present in DG2. Extend this to future discrete products.
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_display.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 614e60420a29..aed25890b6f5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1861,11 +1861,10 @@ bool intel_phy_is_combo(struct drm_i915_private
*dev_priv, enum phy phy)
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
/*
-* DG2's "TC1", although TC-capable output, doesn't share the same flow
-* as other platforms on the display engine side and rather rely on the
-* SNPS PHY, that is programmed separately
+* Discrete GPU phy's are not attached to FIA's to support TC
+* subsystem Legacy or non-legacy, and only support native DP/HDMI
*/
- if (IS_DG2(dev_priv))
+ if (IS_DGFX(dev_priv))
return false;
if (DISPLAY_VER(dev_priv) >= 13)
--
2.25.1
[PATCH 12/25] drm/i915/xe2hpd: update pll values in sync with Bspec
From: Ravi Kumar Vodapalli
DP/eDP and HDMI pll values are updated for Xe2_HPD platform
Bspec: 74165
Signed-off-by: Ravi Kumar Vodapalli
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 47 +++-
1 file changed, 45 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index d948035f07ad..20035be015c3 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -1109,6 +1109,42 @@ static const struct intel_c20pll_state * const
xe2hpd_c20_edp_tables[] = {
NULL,
};
+static const struct intel_c20pll_state xe2hpd_c20_dp_uhbr13_5 = {
+ .clock = 135, /* 13.5 Gbps */
+ .tx = { 0xbea0, /* tx cfg0 */
+ 0x4800, /* tx cfg1 */
+ 0x, /* tx cfg2 */
+ },
+ .cmn = {0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x, /* cmn cfg2 */
+ 0x, /* cmn cfg3 */
+ },
+ .mpllb = { 0x015f, /* mpllb cfg0 */
+ 0x2205, /* mpllb cfg1 */
+ 0x1b17, /* mpllb cfg2 */
+ 0xffc1, /* mpllb cfg3 */
+ 0xbd00, /* mpllb cfg4 */
+ 0x9ec3, /* mpllb cfg5 */
+ 0x2000, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x4800, /* mpllb cfg8 */
+ 0x, /* mpllb cfg9 */
+ 0x, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state * const xe2hpd_c20_dp_tables[] = {
+ _c20_dp_rbr,
+ _c20_dp_hbr1,
+ _c20_dp_hbr2,
+ _c20_dp_hbr3,
+ _c20_dp_uhbr10,
+ _c20_dp_uhbr13_5,
+ _c20_dp_uhbr20,
+ NULL,
+};
+
/*
* HDMI link rates with 38.4 MHz reference clock.
*/
@@ -2225,13 +2261,20 @@ static const struct intel_c20pll_state * const *
intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
- if (intel_crtc_has_dp_encoder(crtc_state))
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+ if (intel_crtc_has_dp_encoder(crtc_state)) {
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
return xe2hpd_c20_edp_tables;
+
+ if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
+ return xe2hpd_c20_dp_tables;
else
return mtl_c20_dp_tables;
- else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+
+ } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
return mtl_c20_hdmi_tables;
+ }
MISSING_CASE(encoder->type);
return NULL;
--
2.25.1
[PATCH 14/25] drm/i915/xe2hpd: Add missing chicken bit register programming
From: Anusha Srivatsa Add step 9 from initialize display sequence. Bpsec: 49189 Signed-off-by: Anusha Srivatsa Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_display_power.c | 4 drivers/gpu/drm/i915/i915_reg.h| 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 6fd4fa52253a..bf9685acf75a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1694,6 +1694,10 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, if (IS_DG2(dev_priv)) intel_snps_phy_wait_for_calibration(dev_priv); + /* 9. XE2_HPD: Program CHICKEN_MISC_2 before any cursor or planes are enabled */ + if (DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 1)) + intel_de_rmw(dev_priv, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1); + if (resume) intel_dmc_load_program(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 58f3e4bfe254..875d76fb8cd0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4548,6 +4548,7 @@ #define CHICKEN_MISC_2 _MMIO(0x42084) #define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */ +#define BMG_DARB_HALF_BLK_END_BURST REG_BIT(27) #define KBL_ARB_FILL_SPARE_14REG_BIT(14) #define KBL_ARB_FILL_SPARE_13REG_BIT(13) #define GLK_CL2_PWR_DOWN REG_BIT(12) -- 2.25.1
[PATCH 09/25] drm/i915/xe2hpd: Properly disable power in port A
From: José Roberto de Souza
Xe2_HPD has a different value to power down port A.
BSpec: 65450
CC: Matt Roper
Signed-off-by: José Roberto de Souza
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 13a2e3db2812..caaae5d3758e 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2921,17 +2921,28 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder,
intel_cx0pll_enable(encoder, crtc_state);
}
+static u8 cx0_power_control_disable_val(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+ if (intel_encoder_is_c10phy(encoder))
+ return CX0_P2PG_STATE_DISABLE;
+
+ if (IS_BATTLEMAGE(i915) && encoder->port == PORT_A)
+ return CX0_P2PG_STATE_DISABLE;
+
+ return CX0_P4PG_STATE_DISABLE;
+}
+
static void intel_cx0pll_disable(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_encoder_to_phy(encoder);
- bool is_c10 = intel_encoder_is_c10phy(encoder);
intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);
/* 1. Change owned PHY lane power to Disable state. */
intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
- is_c10 ? CX0_P2PG_STATE_DISABLE :
- CX0_P4PG_STATE_DISABLE);
+
cx0_power_control_disable_val(encoder));
/*
* 2. Follow the Display Voltage Frequency Switching Sequence Before
--
2.25.1
[PATCH 13/25] drm/i915/xe2hpd: Add display info
From: Lucas De Marchi
Add initial display info for xe2hpd. It is similar to xelpd, but with no
PORT_B.
Bspec: 67066
Signed-off-by: Lucas De Marchi
Signed-off-by: Balasubramani Vivekanandan
---
.../gpu/drm/i915/display/intel_display_device.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index c02d79b50006..2c505c480337 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -768,6 +768,21 @@ static const struct intel_display_device_info
xe2_lpd_display = {
BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D),
};
+static const struct intel_display_device_info xe2_hpd_display = {
+ XE_LPD_FEATURES,
+ .has_cdclk_crawl = 1,
+ .has_cdclk_squash = 1,
+
+ .__runtime_defaults.ip.ver = 14,
+ .__runtime_defaults.ip.rel = 1,
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
+ .__runtime_defaults.cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
+ .__runtime_defaults.port_mask = BIT(PORT_A) |
+ BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
+};
+
/*
* Separate detection for no display cases to keep the display id array simple.
*
@@ -847,6 +862,7 @@ static const struct {
const struct intel_display_device_info *display;
} gmdid_display_map[] = {
{ 14, 0, _lpdp_display },
+ { 14, 1, _hpd_display },
{ 20, 0, _lpd_display },
};
--
2.25.1
[PATCH 10/25] drm/i915/xe2hpd: Add new C20 PLL register address
Xe2_HPD has different address for C20 PLL registers. Enable the support
to use the right PLL register address based on display version.
Note that Xe2_LPD uses the same C20 SRAM offsets used by Xe_LPDP (i.e.
MTL's display). According to the BSpec, currently, only Xe2_HPD has
different offsets, so make sure it is the only display using them in the
driver.
Bspec: 67610
Cc: Clint Taylor
Cc: Gustavo Sousa
Signed-off-by: Balasubramani Vivekanandan
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27 +--
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 9 +++
2 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index caaae5d3758e..6e4647859fc6 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -770,6 +770,17 @@ static struct intel_c20pll_reg mtl_c20_reg = {
.mpllb_b = MTL_C20_B_MPLLB_CFG_ADDR
};
+static struct intel_c20pll_reg xe2hpd_c20_reg = {
+ .tx_cnt_a = XE2HPD_C20_A_TX_CNTX_CFG_ADDR,
+ .tx_cnt_b = XE2HPD_C20_B_TX_CNTX_CFG_ADDR,
+ .cmn_cnt_a = XE2HPD_C20_A_CMN_CNTX_CFG_ADDR,
+ .cmn_cnt_b = XE2HPD_C20_B_CMN_CNTX_CFG_ADDR,
+ .mplla_a = XE2HPD_C20_A_MPLLA_CFG_ADDR,
+ .mplla_b = XE2HPD_C20_B_MPLLA_CFG_ADDR,
+ .mpllb_a = XE2HPD_C20_A_MPLLB_CFG_ADDR,
+ .mpllb_b = XE2HPD_C20_B_MPLLB_CFG_ADDR,
+};
+
/* C20 basic DP 1.4 tables */
static const struct intel_c20pll_state mtl_c20_dp_rbr = {
.clock = 162000,
@@ -2166,19 +2177,29 @@ static int intel_c20pll_calc_port_clock(struct
intel_encoder *encoder,
return vco << tx_rate_mult >> tx_clk_div >> tx_rate;
}
+static struct intel_c20pll_reg *intel_c20_get_pll_reg(struct drm_i915_private
*i915)
+{
+ if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
+ return _c20_reg;
+ else
+ return _c20_reg;
+}
+
static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
struct intel_c20pll_state *pll_state)
{
bool cntx;
intel_wakeref_t wakeref;
int i;
- struct intel_c20pll_reg *pll_reg = _c20_reg;
+ struct intel_c20pll_reg *pll_reg;
wakeref = intel_cx0_phy_transaction_begin(encoder);
/* 1. Read current context selection */
cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0,
PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;
+ pll_reg = intel_c20_get_pll_reg(to_i915(encoder->base.dev));
+
/* Read Tx configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
if (cntx)
@@ -2353,7 +2374,7 @@ static void intel_c20_pll_program(struct drm_i915_private
*i915,
u32 clock = crtc_state->port_clock;
bool cntx;
int i;
- const struct intel_c20pll_reg *pll_reg = _c20_reg;
+ const struct intel_c20pll_reg *pll_reg;
if (intel_crtc_has_dp_encoder(crtc_state))
dp = true;
@@ -2372,6 +2393,8 @@ static void intel_c20_pll_program(struct drm_i915_private
*i915,
usleep_range(4000, 4100);
}
+ pll_reg = intel_c20_get_pll_reg(i915);
+
/* 3. Write SRAM configuration context. If A in use, write
configuration to B context */
/* 3.1 Tx configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 882b98dc347b..8e5fd605b99e 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -292,6 +292,15 @@ struct intel_c20pll_reg {
#define MTL_C20_A_MPLLB_CFG_ADDR 0xCB5A
#define MTL_C20_B_MPLLB_CFG_ADDR 0xCB4E
+#define XE2HPD_C20_A_TX_CNTX_CFG_ADDR 0xCF5E
+#define XE2HPD_C20_B_TX_CNTX_CFG_ADDR 0xCF5A
+#define XE2HPD_C20_A_CMN_CNTX_CFG_ADDR 0xCE8E
+#define XE2HPD_C20_B_CMN_CNTX_CFG_ADDR 0xCE89
+#define XE2HPD_C20_A_MPLLA_CFG_ADDR0xCE58
+#define XE2HPD_C20_B_MPLLA_CFG_ADDR0xCE4D
+#define XE2HPD_C20_A_MPLLB_CFG_ADDR0xCCC2
+#define XE2HPD_C20_B_MPLLB_CFG_ADDR0xCCB6
+
/* C20 Phy VSwing Masks */
#define C20_PHY_VSWING_PREEMPH_MASKREG_GENMASK8(5, 0)
#define C20_PHY_VSWING_PREEMPH(val)
REG_FIELD_PREP8(C20_PHY_VSWING_PREEMPH_MASK, val)
--
2.25.1
[PATCH 07/25] Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping"
From: Ankit Nautiyal
This reverts commit 562f33836f519a235e5c5e71bcc723ab1faccd2f.
For BMG it seems that the VBT to DDI mapping does not follow DG1, and
DG2, but follows ADLP mapping given in Bspec:20124.
Signed-off-by: Ankit Nautiyal
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_bios.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 2abd2d7ceda2..03fbd6c73f3f 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2238,15 +2238,14 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8
vbt_pin)
const u8 *ddc_pin_map;
int i, n_entries;
- if (IS_DGFX(i915))
- return vbt_pin;
-
if (INTEL_PCH_TYPE(i915) >= PCH_MTL || IS_ALDERLAKE_P(i915)) {
ddc_pin_map = adlp_ddc_pin_map;
n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
} else if (IS_ALDERLAKE_S(i915)) {
ddc_pin_map = adls_ddc_pin_map;
n_entries = ARRAY_SIZE(adls_ddc_pin_map);
+ } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
+ return vbt_pin;
} else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) {
ddc_pin_map = rkl_pch_tgp_ddc_pin_map;
n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);
--
2.25.1
[PATCH 11/25] drm/i915/xe2hpd: Add support for eDP PLL configuration
Tables for eDP PHY PLL configuration for different link rates added for
Xe2_HPD. Previous platforms were using C10 PHY for eDP port whereas
Xe2_HPD has C20 PHY.
Bpsec: 64568
CC: Clint Taylor
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 147 ++-
1 file changed, 146 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 6e4647859fc6..d948035f07ad 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -967,6 +967,148 @@ static const struct intel_c20pll_state * const
mtl_c20_dp_tables[] = {
NULL,
};
+/*
+ * eDP link rates with 38.4 MHz reference clock.
+ */
+
+static const struct intel_c20pll_state xe2hpd_c20_edp_r216 = {
+ .clock = 216000,
+ .tx = { 0xbe88,
+ 0x4800,
+ 0x,
+ },
+ .cmn = { 0x0500,
+0x0005,
+0x,
+0x,
+ },
+ .mpllb = { 0x50e1,
+ 0x2120,
+ 0x8e18,
+ 0xbfc1,
+ 0x9000,
+ 0x78f6,
+ 0x,
+ 0x,
+ 0x,
+ 0x,
+ 0x,
+ },
+};
+
+static const struct intel_c20pll_state xe2hpd_c20_edp_r243 = {
+ .clock = 243000,
+ .tx = { 0xbe88,
+ 0x4800,
+ 0x,
+ },
+ .cmn = { 0x0500,
+0x0005,
+0x,
+0x,
+ },
+ .mpllb = { 0x50fd,
+ 0x2120,
+ 0x8f18,
+ 0xbfc1,
+ 0xa200,
+ 0x8814,
+ 0x2000,
+ 0x0001,
+ 0x1000,
+ 0x,
+ 0x,
+ },
+};
+
+static const struct intel_c20pll_state xe2hpd_c20_edp_r324 = {
+ .clock = 324000,
+ .tx = { 0xbe88,
+ 0x4800,
+ 0x,
+ },
+ .cmn = { 0x0500,
+0x0005,
+0x,
+0x,
+ },
+ .mpllb = { 0x30a8,
+ 0x2110,
+ 0xcd9a,
+ 0xbfc1,
+ 0x6c00,
+ 0x5ab8,
+ 0x2000,
+ 0x0001,
+ 0x6000,
+ 0x,
+ 0x,
+ },
+};
+
+static const struct intel_c20pll_state xe2hpd_c20_edp_r432 = {
+ .clock = 432000,
+ .tx = { 0xbe88,
+ 0x4800,
+ 0x,
+ },
+ .cmn = { 0x0500,
+0x0005,
+0x,
+0x,
+ },
+ .mpllb = { 0x30e1,
+ 0x2110,
+ 0x8e18,
+ 0xbfc1,
+ 0x9000,
+ 0x78f6,
+ 0x,
+ 0x,
+ 0x,
+ 0x,
+ 0x,
+ },
+};
+
+static const struct intel_c20pll_state xe2hpd_c20_edp_r675 = {
+ .clock = 675000,
+ .tx = { 0xbe88,
+ 0x4800,
+ 0x,
+ },
+ .cmn = { 0x0500,
+0x0005,
+0x,
+0x,
+ },
+ .mpllb = { 0x10af,
+ 0x2108,
+ 0xce1a,
+ 0xbfc1,
+ 0x7080,
+ 0x5e80,
+ 0x2000,
+ 0x0001,
+ 0x6400,
+ 0x,
+ 0x,
+ },
+};
+
+static const struct intel_c20pll_state * const xe2hpd_c20_edp_tables[] = {
+ _c20_dp_rbr,
+ _c20_edp_r216,
+ _c20_edp_r243,
+ _c20_dp_hbr1,
+ _c20_edp_r324,
+ _c20_edp_r432,
+ _c20_dp_hbr2,
+ _c20_edp_r675,
+ _c20_dp_hbr3,
+ NULL,
+};
+
/*
* HDMI link rates with 38.4 MHz reference clock.
*/
@@ -2084,7 +2226,10 @@ intel_c20_pll_tables_get(struct intel_crtc_state
*crtc_state,
struct intel_encoder *encoder)
{
if (intel_crtc_has_dp_encoder(crtc_state))
- return mtl_c20_dp_tables;
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+ return xe2hpd_c20_edp_tables;
+ else
+ return mtl_c20_dp_tables;
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
return mtl_c20_hdmi_tables;
--
2.25.1
[PATCH 05/25] drm/i915/xe2: Skip CCS modifiers for Xe2 platforms
Xe2 platforms doesn't support Aux CCS and the Flat CCS is enabled
through PAT. No CCS modifiers required for Xe2 platforms.
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_fb.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 3ea6470d6d92..923e97c3aa6c 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -431,9 +431,17 @@ static bool plane_has_modifier(struct drm_i915_private
*i915,
* Separate AuxCCS and Flat CCS modifiers to be run only on platforms
* where supported.
*/
- if (intel_fb_is_ccs_modifier(md->modifier) &&
- HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes)
- return false;
+ if (intel_fb_is_ccs_modifier(md->modifier)) {
+ /*
+* No CCS modifiers available on Xe2 platforms as they don't
+* support Aux CCS and the Flat CCS is enabled via PAT
+*/
+ if ((DISPLAY_VER(i915) >= 20) || IS_BATTLEMAGE(i915))
+ return false;
+
+ if (HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes)
+ return false;
+ }
return true;
}
--
2.25.1
[PATCH 06/25] drm/i915/xe2hpd: Initial cdclk table
From: Clint Taylor
Add Xe2_HPD specific CDCLK table and use MTL Funcs.
Bspec: 65243
Cc: Matt Roper
CC: Lucas De Marchi
Signed-off-by: Clint Taylor
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 31aaa9780dfc..da16c308670f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1444,6 +1444,14 @@ static const struct intel_cdclk_vals
xe2lpd_cdclk_table[] = {
{}
};
+/*
+ * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771
+ */
+static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x },
+ {}
+};
+
static const int cdclk_squash_len = 16;
static int cdclk_squash_divider(u16 waveform)
@@ -3768,6 +3776,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private
*dev_priv)
if (DISPLAY_VER(dev_priv) >= 20) {
dev_priv->display.funcs.cdclk = _cdclk_funcs;
dev_priv->display.cdclk.table = xe2lpd_cdclk_table;
+ } else if (DISPLAY_VER_FULL(dev_priv) >= IP_VER(14, 1)) {
+ dev_priv->display.funcs.cdclk = _cdclk_funcs;
+ dev_priv->display.cdclk.table = xe2hpd_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 14) {
dev_priv->display.funcs.cdclk = _cdclk_funcs;
dev_priv->display.cdclk.table = mtl_cdclk_table;
--
2.25.1
[PATCH 03/25] drm/xe/bmg: Define IS_BATTLEMAGE macro
Common display code requires IS_BATTLEMAGE macro. Defined the macro. Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h index a01d1b869c2d..9161d1fdf239 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h @@ -88,6 +88,7 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2) #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE) #define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE) +#define IS_BATTLEMAGE(dev_priv) IS_PLATFORM(dev_priv, XE_BATTLEMAGE) #define IS_HASWELL_ULT(dev_priv) (dev_priv && 0) #define IS_BROADWELL_ULT(dev_priv) (dev_priv && 0) -- 2.25.1
[PATCH 04/25] drm/i915/bmg: Define IS_BATTLEMAGE macro
Display code uses IS_BATTLEMAGE macro but the platform support doesn't still exist in i915. So fake IS_BATTLEMAGE macro defined to enable building i915 code. We should make sure the macro parameter is used in the always-false expression so that we don't run into "unused variable" warnings from i915 builds if the IS_BATTLEMAGE() check is the only place the i915 pointer gets used in a function. While we're at it, also update the IS_LUNARLAKE macro to include the parameter in the false expression for consistency. Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/i915_drv.h | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index cf52d4adaa20..b41a414079f4 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -546,7 +546,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P) #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2) #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE) -#define IS_LUNARLAKE(i915) 0 +/* + * Display code shared by i915 and Xe relies on macros like IS_LUNARLAKE, + * so we need to define these even on platforms that the i915 base driver + * doesn't support. Ensure the parameter is used in the definition to + * avoid 'unused variable' warnings when compiling the shared display code + * for i915. + */ +#define IS_LUNARLAKE(i915) (0 && i915) +#define IS_BATTLEMAGE(i915) (0 && i915) #define IS_DG2_G10(i915) \ IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10) -- 2.25.1
[PATCH 02/25] drm/xe/bmg: Add BMG platform definition
From: Matt Roper
BMG is a discrete GPU based on the Xe2 architecture.
Bspec: 68090
Signed-off-by: Matt Roper
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/xe/xe_pci.c| 7 +++
drivers/gpu/drm/xe/xe_platform_types.h | 1 +
include/drm/xe_pciids.h| 7 +++
3 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index c47ab4b67467..b3158053baee 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -337,6 +337,12 @@ static const struct xe_device_desc lnl_desc = {
.require_force_probe = true,
};
+static const struct xe_device_desc bmg_desc = {
+ DGFX_FEATURES,
+ PLATFORM(XE_BATTLEMAGE),
+ .require_force_probe = true,
+};
+
#undef PLATFORM
__diag_pop();
@@ -379,6 +385,7 @@ static const struct pci_device_id pciidlist[] = {
XE_PVC_IDS(INTEL_VGA_DEVICE, _desc),
XE_MTL_IDS(INTEL_VGA_DEVICE, _desc),
XE_LNL_IDS(INTEL_VGA_DEVICE, _desc),
+ XE_BMG_IDS(INTEL_VGA_DEVICE, _desc),
{ }
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/xe/xe_platform_types.h
b/drivers/gpu/drm/xe/xe_platform_types.h
index 553f53dbd093..79b7042c4534 100644
--- a/drivers/gpu/drm/xe/xe_platform_types.h
+++ b/drivers/gpu/drm/xe/xe_platform_types.h
@@ -22,6 +22,7 @@ enum xe_platform {
XE_PVC,
XE_METEORLAKE,
XE_LUNARLAKE,
+ XE_BATTLEMAGE,
};
enum xe_subplatform {
diff --git a/include/drm/xe_pciids.h b/include/drm/xe_pciids.h
index c7fc288dacee..73d972a8aca1 100644
--- a/include/drm/xe_pciids.h
+++ b/include/drm/xe_pciids.h
@@ -208,4 +208,11 @@
MACRO__(0x64A0, ## __VA_ARGS__), \
MACRO__(0x64B0, ## __VA_ARGS__)
+#define XE_BMG_IDS(MACRO__, ...) \
+ MACRO__(0xE202, ## __VA_ARGS__), \
+ MACRO__(0xE20B, ## __VA_ARGS__), \
+ MACRO__(0xE20C, ## __VA_ARGS__), \
+ MACRO__(0xE20D, ## __VA_ARGS__), \
+ MACRO__(0xE212, ## __VA_ARGS__)
+
#endif
--
2.25.1
[PATCH 01/25] drm/i915/display: Prepare to handle new C20 PLL register address
New platforms have different addresses for C20 PLL registers. This patch
prepares the driver to work with different register addresses.
New structure `struct intel_c20pll_reg` is created to hold the register
addresses for each platform with different register address.
CC: Clint Taylor
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 53 +--
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 36 ++---
2 files changed, 65 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index a2c4bf33155f..13a2e3db2812 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -759,6 +759,17 @@ static const struct intel_c10pll_state * const
mtl_c10_edp_tables[] = {
NULL,
};
+static struct intel_c20pll_reg mtl_c20_reg = {
+ .tx_cnt_a = MTL_C20_A_TX_CNTX_CFG_ADDR,
+ .tx_cnt_b = MTL_C20_B_TX_CNTX_CFG_ADDR,
+ .cmn_cnt_a = MTL_C20_A_CMN_CNTX_CFG_ADDR,
+ .cmn_cnt_b = MTL_C20_B_CMN_CNTX_CFG_ADDR,
+ .mplla_a = MTL_C20_A_MPLLA_CFG_ADDR,
+ .mplla_b = MTL_C20_B_MPLLA_CFG_ADDR,
+ .mpllb_a = MTL_C20_A_MPLLB_CFG_ADDR,
+ .mpllb_b = MTL_C20_B_MPLLB_CFG_ADDR
+};
+
/* C20 basic DP 1.4 tables */
static const struct intel_c20pll_state mtl_c20_dp_rbr = {
.clock = 162000,
@@ -2161,6 +2172,7 @@ static void intel_c20pll_readout_hw_state(struct
intel_encoder *encoder,
bool cntx;
intel_wakeref_t wakeref;
int i;
+ struct intel_c20pll_reg *pll_reg = _c20_reg;
wakeref = intel_cx0_phy_transaction_begin(encoder);
@@ -2171,20 +2183,20 @@ static void intel_c20pll_readout_hw_state(struct
intel_encoder *encoder,
for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
if (cntx)
pll_state->tx[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
-
PHY_C20_B_TX_CNTX_CFG(i));
+
PHY_C20_B_TX_CNTX_CFG(pll_reg, i));
else
pll_state->tx[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
-
PHY_C20_A_TX_CNTX_CFG(i));
+
PHY_C20_A_TX_CNTX_CFG(pll_reg, i));
}
/* Read common configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
if (cntx)
pll_state->cmn[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
-
PHY_C20_B_CMN_CNTX_CFG(i));
+
PHY_C20_B_CMN_CNTX_CFG(pll_reg, i));
else
pll_state->cmn[i] = intel_c20_sram_read(encoder,
INTEL_CX0_LANE0,
-
PHY_C20_A_CMN_CNTX_CFG(i));
+
PHY_C20_A_CMN_CNTX_CFG(pll_reg, i));
}
if (intel_c20phy_use_mpllb(pll_state)) {
@@ -2192,20 +2204,20 @@ static void intel_c20pll_readout_hw_state(struct
intel_encoder *encoder,
for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
if (cntx)
pll_state->mpllb[i] =
intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
-
PHY_C20_B_MPLLB_CNTX_CFG(i));
+
PHY_C20_B_MPLLB_CNTX_CFG(pll_reg, i));
else
pll_state->mpllb[i] =
intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
-
PHY_C20_A_MPLLB_CNTX_CFG(i));
+
PHY_C20_A_MPLLB_CNTX_CFG(pll_reg, i));
}
} else {
/* MPLLA configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
if (cntx)
pll_state->mplla[i] =
intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
-
PHY_C20_B_MPLLA_CNTX_CFG(i));
+
PHY_C20_B_MPLLA_CNTX_CFG(pll_reg, i));
else
pll_state->mplla[i] =
intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
-
PHY_C20_A_MPLLA_CNTX_CFG(i));
+
PHY_C20_A_MPLLA_CNTX_CFG(pll_reg, i));
