[Intel-gfx] [PATCH 04/15] drm/i915: Stage scaler request for NV12 as src format
This patch stages a scaler request when input format
is NV12. The same scaler does both chroma-upsampling
and resolution scaling as needed.
v2:
-Added helper function for need_scaling (Ville)
v3:
-Rebased to current kernel version 4.2.0.rc4 (me)
v4:
-minor updates (Ville)
v5:
-updated scaler helper function (Ville)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 29 ++---
1 file changed, 22 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 356f071..cf6c31d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4345,20 +4345,33 @@ static void cpt_verify_modeset(struct drm_device *dev,
int pipe)
}
}
+static bool skl_need_scaling(int src_w, int src_h, int dst_w, int dst_h,
+ unsigned int rotation, uint32_t pixel_format)
+{
+ /* need a scaler for nv12 */
+ if (pixel_format == DRM_FORMAT_NV12)
+ return true;
+
+ /* need a scaler when sizes doesn't match */
+ if (intel_rotation_90_or_270(rotation))
+ return (src_h != dst_w || src_w != dst_h);
+ else
+ return (src_w != dst_w || src_h != dst_h);
+}
+
static int
skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
unsigned scaler_user, int *scaler_id, unsigned int rotation,
- int src_w, int src_h, int dst_w, int dst_h)
+ int src_w, int src_h, int dst_w, int dst_h, uint32_t
pixel_format)
{
struct intel_crtc_scaler_state *scaler_state =
_state->scaler_state;
struct intel_crtc *intel_crtc =
to_intel_crtc(crtc_state->base.crtc);
- int need_scaling;
+ bool need_scaling;
- need_scaling = intel_rotation_90_or_270(rotation) ?
- (src_h != dst_w || src_w != dst_h):
- (src_w != dst_w || src_h != dst_h);
+ need_scaling = skl_need_scaling(src_w, src_h, dst_w, dst_h, rotation,
+ pixel_format);
/*
* if plane is being disabled or scaler is no more required or force
detach
@@ -4427,7 +4440,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state)
return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
>scaler_state.scaler_id, DRM_ROTATE_0,
state->pipe_src_w, state->pipe_src_h,
- adjusted_mode->hdisplay, adjusted_mode->vdisplay);
+ adjusted_mode->hdisplay, adjusted_mode->vdisplay, 0);
}
/**
@@ -4463,7 +4476,8 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
drm_rect_width(_state->src) >> 16,
drm_rect_height(_state->src) >> 16,
drm_rect_width(_state->dst),
- drm_rect_height(_state->dst));
+ drm_rect_height(_state->dst),
+ fb ? fb->pixel_format : 0);
if (ret || plane_state->scaler_id < 0)
return ret;
@@ -4488,6 +4502,7 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+ case DRM_FORMAT_NV12:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format
0x%x\n",
--
1.7.9.5
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[Intel-gfx] [PATCH 07/15] drm/i915: Add NV12 as supported format for primary plane
This patch adds NV12 to list of supported formats for
primary plane.
v2:
-Rebased (me)
v3:
-Rebased on top of primary plane YUV support patch (Ville)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4122359..2a5170e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -78,6 +78,23 @@ static const uint32_t skl_primary_formats[] = {
DRM_FORMAT_VYUY,
};
+/* Primary plane formats for gen >= 9 with NV12 */
+static const uint32_t skl_primary_formats_with_nv12[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+};
+
/* Cursor formats */
static const uint32_t intel_cursor_formats[] = {
DRM_FORMAT_ARGB,
@@ -13611,8 +13628,13 @@ static struct drm_plane
*intel_primary_plane_create(struct drm_device *dev,
primary->plane = !pipe;
if (INTEL_INFO(dev)->gen >= 9) {
- intel_primary_formats = skl_primary_formats;
- num_formats = ARRAY_SIZE(skl_primary_formats);
+ if (pipe == PIPE_A || pipe == PIPE_B) {
+ intel_primary_formats = skl_primary_formats_with_nv12;
+ num_formats = ARRAY_SIZE(skl_primary_formats_with_nv12);
+ } else {
+ intel_primary_formats = skl_primary_formats;
+ num_formats = ARRAY_SIZE(skl_primary_formats);
+ }
} else if (INTEL_INFO(dev)->gen >= 4) {
intel_primary_formats = i965_primary_formats;
num_formats = ARRAY_SIZE(i965_primary_formats);
--
1.7.9.5
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[Intel-gfx] [PATCH 09/15] drm/i915: Add NV12 support to intel_framebuffer_init
This patch adds NV12 as supported format to
intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (me)
v3:
-cosmetic update, split checks into two (Ville)
v4:
-Add stride alignment and modifier checks for UV subplane (Ville)
v5:
-Make modifier check general (Ville)
-Check tile-y uv start alignment from begining of page (Ville)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 66 +++---
drivers/gpu/drm/i915/intel_drv.h |2 +-
drivers/gpu/drm/i915/intel_sprite.c |2 +-
3 files changed, 55 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 2a5170e..af28ca9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2914,9 +2914,9 @@ static void ironlake_update_primary_plane(struct drm_crtc
*crtc,
}
u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
- uint32_t pixel_format)
+ uint32_t pixel_format, int plane)
{
- u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
+ u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, plane) * 8;
/*
* The stride is either expressed as a multiple of 64 bytes
@@ -3125,7 +3125,7 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
obj = intel_fb_obj(fb);
stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
- fb->pixel_format);
+ fb->pixel_format, 0);
surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
/*
@@ -9104,7 +9104,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
val = I915_READ(PLANE_STRIDE(pipe, 0));
stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
- fb->pixel_format);
+ fb->pixel_format, 0);
fb->pitches[0] = (val & 0x3ff) * stride_mult;
aligned_height = intel_fb_align_height(dev, fb->height,
@@ -11175,7 +11175,7 @@ static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc)
*/
stride = fb->pitches[0] /
intel_fb_stride_alignment(dev, fb->modifier[0],
- fb->pixel_format);
+ fb->pixel_format, 0);
/*
* Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
@@ -14241,6 +14241,7 @@ static int intel_framebuffer_init(struct drm_device
*dev,
{
unsigned int aligned_height;
int ret;
+ int i;
u32 pitch_limit, stride_alignment;
WARN_ON(!mutex_is_locked(>struct_mutex));
@@ -14255,7 +14256,8 @@ static int intel_framebuffer_init(struct drm_device
*dev,
}
} else {
if (obj->tiling_mode == I915_TILING_X)
- mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
+ for (i = 0; i <
drm_format_num_planes(mode_cmd->pixel_format); i++)
+ mode_cmd->modifier[i] = I915_FORMAT_MOD_X_TILED;
else if (obj->tiling_mode == I915_TILING_Y) {
DRM_DEBUG("No Y tiling for legacy addfb\n");
return -EINVAL;
@@ -14280,12 +14282,15 @@ static int intel_framebuffer_init(struct drm_device
*dev,
return -EINVAL;
}
- stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
-mode_cmd->pixel_format);
- if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
- DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
- mode_cmd->pitches[0], stride_alignment);
- return -EINVAL;
+ /* check stride alignment for sub-planes */
+ for (i = 0; i < drm_format_num_planes(mode_cmd->pixel_format); i++) {
+ stride_alignment = intel_fb_stride_alignment(dev,
mode_cmd->modifier[i],
+mode_cmd->pixel_format, i);
+ if (mode_cmd->pitches[i] & (stride_alignment - 1)) {
+ DRM_DEBUG("subplane %d pitch (%d) must be at least %u
bytes "
+ "aligned\n", i, mode_cmd->pitches[i],
stride_alignment);
+ return -EINVAL;
+ }
}
pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
@@ -14352,9 +14357,44 @@ static int intel_framebuffer_init(struct drm_device
*dev,
[Intel-gfx] [PATCH 09/15] drm/i915: Add NV12 support to intel_framebuffer_init
This patch adds NV12 as supported format to
intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (me)
v3:
-cosmetic update, split checks into two (Ville)
v4:
-Add stride alignment and modifier checks for UV subplane (Ville)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 67 --
drivers/gpu/drm/i915/intel_drv.h |2 +-
drivers/gpu/drm/i915/intel_sprite.c |2 +-
3 files changed, 57 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 84dad95..6124339 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2906,9 +2906,9 @@ static void ironlake_update_primary_plane(struct drm_crtc
*crtc,
}
u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
- uint32_t pixel_format)
+ uint32_t pixel_format, int plane)
{
- u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
+ u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, plane) * 8;
/*
* The stride is either expressed as a multiple of 64 bytes
@@ -3117,7 +3117,7 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
obj = intel_fb_obj(fb);
stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
- fb->pixel_format);
+ fb->pixel_format, 0);
surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
/*
@@ -9101,7 +9101,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
val = I915_READ(PLANE_STRIDE(pipe, 0));
stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
- fb->pixel_format);
+ fb->pixel_format, 0);
fb->pitches[0] = (val & 0x3ff) * stride_mult;
aligned_height = intel_fb_align_height(dev, fb->height,
@@ -11172,7 +11172,7 @@ static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc)
*/
stride = fb->pitches[0] /
intel_fb_stride_alignment(dev, fb->modifier[0],
- fb->pixel_format);
+ fb->pixel_format, 0);
/*
* Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
@@ -14238,6 +14238,7 @@ static int intel_framebuffer_init(struct drm_device
*dev,
{
unsigned int aligned_height;
int ret;
+ int i;
u32 pitch_limit, stride_alignment;
WARN_ON(!mutex_is_locked(>struct_mutex));
@@ -14277,12 +14278,15 @@ static int intel_framebuffer_init(struct drm_device
*dev,
return -EINVAL;
}
- stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
-mode_cmd->pixel_format);
- if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
- DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
- mode_cmd->pitches[0], stride_alignment);
- return -EINVAL;
+ /* check stride alignment for sub-planes */
+ for (i = 0; i < drm_format_num_planes(mode_cmd->pixel_format); i++) {
+ stride_alignment = intel_fb_stride_alignment(dev,
mode_cmd->modifier[i],
+mode_cmd->pixel_format, i);
+ if (mode_cmd->pitches[i] & (stride_alignment - 1)) {
+ DRM_DEBUG("subplane %d pitch (%d) must be at least %u
bytes "
+ "aligned\n", i, mode_cmd->pitches[i],
stride_alignment);
+ return -EINVAL;
+ }
}
pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
@@ -14349,9 +14353,48 @@ static int intel_framebuffer_init(struct drm_device
*dev,
return -EINVAL;
}
break;
+ case DRM_FORMAT_NV12:
+ if (INTEL_INFO(dev)->gen < 9) {
+ DRM_DEBUG("unsupported pixel format: %s\n",
+ drm_get_format_name(mode_cmd->pixel_format));
+ return -EINVAL;
+ }
+ if (obj->tiling_mode == I915_TILING_X &&
+ !(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) {
+ mode_cmd->modifier[1] = I915_FORMAT_MOD_X_TILED;
+ }
+ if (!mode_cmd->offsets[1]) {
+ DRM_DEBUG("uv start offset not set\n");
+
[Intel-gfx] [PATCH i-g-t 2/2] Adding kms_nv12 to test display NV12 feature
From: chandra konduru <chandra.kond...@intel.com>
This patch adds kms_nv12 test case. It covers testing NV12
in linear/tile-X/tile-Y tiling formats in 0/90/180/270
orientations. For each tiling format, it tests several
combinations of planes and its scaling.
v2:
-Added 90/270 tests (me)
-took out crc test as it isn't adding much value due to chroma upsampling (me)
v3:
-Make --list-subtests option work (Tvrtko)
-Make nv12 unsupported test run properly either as a sub test
or along with all other tests (me)
-Added nv12 fb with invalid params (Daniel)
v4:
-Avoid modeset for invalid tests (Daniel)
v5:
-Added negative nv12 addfb tests for modifier and stride alignment (me)
Signed-off-by: chandra konduru <chandra.kond...@intel.com>
---
tests/.gitignore | 1 +
tests/Makefile.sources | 1 +
tests/kms_nv12.c | 761 +
3 files changed, 763 insertions(+)
create mode 100644 tests/kms_nv12.c
diff --git a/tests/.gitignore b/tests/.gitignore
index d6d05ff..2de4712 100644
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -155,6 +155,7 @@ kms_setmode
kms_sink_crc_basic
kms_universal_plane
kms_vblank
+kms_nv12
pm_backlight
pm_lpsp
pm_rc6_residency
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index ef69299..a7804fa 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -85,6 +85,7 @@ TESTS_progs_M = \
kms_crtc_background_color \
kms_plane_scaling \
kms_panel_fitting \
+ kms_nv12 \
pm_backlight \
pm_lpsp \
pm_rpm \
diff --git a/tests/kms_nv12.c b/tests/kms_nv12.c
new file mode 100644
index 000..bad6862
--- /dev/null
+++ b/tests/kms_nv12.c
@@ -0,0 +1,761 @@
+/*
+ * Copyright © 2013,2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+#include
+#include
+
+#include "drmtest.h"
+#include "igt_debugfs.h"
+#include "igt_kms.h"
+#include "igt_core.h"
+#include "intel_chipset.h"
+#include "ioctl_wrappers.h"
+
+IGT_TEST_DESCRIPTION("Test display NV12 support");
+
+uint32_t devid;
+typedef struct {
+ int drm_fd;
+ igt_display_t display;
+ int num_scalers;
+ int num_planes;
+
+ struct igt_fb fb1;
+ struct igt_fb fb1_nv12;
+ struct igt_fb fb2;
+ struct igt_fb fb2_nv12;
+ struct igt_fb fb3;
+ struct igt_fb fb3_nv12;
+ int fb_id1;
+ int fb_id1_nv12;
+ int fb_id2;
+ int fb_id2_nv12;
+ int fb_id3;
+ int fb_id3_nv12;
+
+ igt_plane_t *plane1;
+ igt_plane_t *plane2;
+ igt_plane_t *plane3;
+
+ uint64_t tiled;
+ int rotation;
+} data_t;
+
+typedef struct {
+ int width;
+ int height;
+} res_t;
+
+#define IMG_FILE "1080p-left.png"
+
+static void
+paint_pattern(data_t *d, struct igt_fb *fb, uint16_t w, uint16_t h)
+{
+ cairo_t *cr;
+
+ cr = igt_get_cairo_ctx(d->drm_fd, fb);
+ igt_paint_test_pattern(cr, w, h);
+ cairo_destroy(cr);
+}
+
+static void
+paint_image(data_t *d, struct igt_fb *fb, uint16_t w, uint16_t h)
+{
+ cairo_t *cr;
+
+ cr = igt_get_cairo_ctx(d->drm_fd, fb);
+ igt_paint_image(cr, IMG_FILE, 0, 0, w, h);
+ cairo_destroy(cr);
+}
+
+static void prepare_crtc(data_t *data, igt_output_t *output, enum pipe pipe,
+ igt_plane_t *plane, drmModeModeInfo *mode, enum
igt_commit_style s)
+{
+ igt_display_t *display = >display;
+
+ igt_output_set_pipe(output, pipe);
+
+ /* before allocating, free if any older fb */
+ if (data->fb_id1) {
+ igt_remove_fb(data->drm_fd, >fb1);
+ data->fb_id1 = 0;
+ }
+
+ /* allocate fb for plane 1 */
+ data->fb_id1 = igt_create_fb(data->drm_f
[Intel-gfx] [PATCH 14/15] drm/i915: skl nv12 wa - NV12 to RGB switch
Switching format from NV12 to RGB can result in display underrun
and corruption. This workaround sets bits 15 & 19 to 1 in
CLKGATE_DIS_PSL register to address transition underrun.
v2:
-Move workaround to init clock gating (Ville)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h |8
drivers/gpu/drm/i915/intel_pm.c |8
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d20f235..2e2636d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5366,6 +5366,14 @@ enum skl_disp_power_wells {
#define CHICKEN_DCPR_1 0x46430
#define IDLE_WAKEMEM_MASK (1 << 13)
+#define CLKGATE_DIS_PSL_A0x46520
+#define CLKGATE_DIS_PSL_B0x46524
+#define CLKGATE_DIS_PSL_C0x46528
+#define DUPS1_GATING_DIS (1 << 15)
+#define DUPS2_GATING_DIS (1 << 19)
+#define DUPS3_GATING_DIS (1 << 23)
+#define CLKGATE_DIS_PSL(pipe) _PIPE(pipe, CLKGATE_DIS_PSL_A,
CLKGATE_DIS_PSL_B)
+
/* SKL new cursor registers */
#define _CUR_BUF_CFG_A 0x7017c
#define _CUR_BUF_CFG_B 0x7117c
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8a36ab9..9a3deed 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -63,6 +63,14 @@ static void gen9_init_clock_gating(struct drm_device *dev)
/* WaDisableKillLogic:bxt,skl */
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
ECOCHK_DIS_TLB);
+
+ /*
+* Switching format from NV12 to RGB can result in display underrun
+* and corruption. This workaround sets bits 15 & 19 to 1 in
+* CLKGATE_DIS_PSL register to address transition underrun.
+*/
+ I915_WRITE(CLKGATE_DIS_PSL(PIPE_A), DUPS1_GATING_DIS |
DUPS2_GATING_DIS);
+ I915_WRITE(CLKGATE_DIS_PSL(PIPE_B), DUPS1_GATING_DIS |
DUPS2_GATING_DIS);
}
static void skl_init_clock_gating(struct drm_device *dev)
--
1.7.9.5
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[Intel-gfx] [PATCH 11/15] drm/i915: Add NV12 to sprite plane programming.
This patch is adding NV12 support to skylake sprite plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.
For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. Once GEM adds support
for seperate remappings for two subplanes, 90/270 support
to be added to plane programming.
v2:
-Use round up division for aux_stride calculation (me)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_sprite.c | 31 +--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 797594e..347fb1f 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -188,6 +188,8 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
int x_offset, y_offset;
struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config;
int scaler_id;
+ u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ u32 tile_row_adjustment = 0;
plane_ctl = PLANE_CTL_ENABLE |
PLANE_CTL_PIPE_CSC_ENABLE;
@@ -234,24 +236,48 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
plane_size = (src_w << 16) | src_h;
x_offset = stride * tile_height - y - (src_h + 1);
y_offset = x;
+
+ /*
+* TBD: For NV12 90/270 rotation, Y and UV subplanes should
+* be treated as separate surfaces and GTT remapping for
+* rotation should be done separately for each subplane.
+* Enable support once seperate remappings are available.
+*/
} else {
stride = fb->pitches[0] / stride_div;
plane_size = (src_h << 16) | src_w;
x_offset = x;
y_offset = y;
+ tile_height = PAGE_SIZE / stride_div;
+
+ if (fb->pixel_format == DRM_FORMAT_NV12) {
+ int height_in_mem = (fb->offsets[1]/fb->pitches[0]);
+ /*
+* If UV starts from middle of a page, then UV start
should
+* be programmed to beginning of that page. And offset
into that
+* page to be programmed into y-offset
+*/
+ tile_row_adjustment = height_in_mem % tile_height;
+ aux_dist = fb->pitches[0] * (height_in_mem -
tile_row_adjustment);
+ aux_x_offset = DIV_ROUND_UP(x, 2);
+ aux_y_offset = DIV_ROUND_UP(y, 2) + tile_row_adjustment;
+ /* For tile-Yf, uv-subplane tile width is 2x of
Y-subplane */
+ aux_stride = fb->modifier[0] ==
I915_FORMAT_MOD_Yf_TILED ?
+ DIV_ROUND_UP(stride, 2) : stride;
+ }
}
plane_offset = y_offset << 16 | x_offset;
I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
+ I915_WRITE(PLANE_AUX_DIST(pipe, plane), aux_dist | aux_stride);
+ I915_WRITE(PLANE_AUX_OFFSET(pipe, plane), aux_y_offset<<16 |
aux_x_offset);
/* program plane scaler */
if (scaler_id >= 0) {
uint32_t ps_ctrl = 0;
- DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
- PS_PLANE_SEL(plane));
ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) |
crtc_state->scaler_state.scalers[scaler_id].mode;
I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
@@ -262,6 +288,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
I915_WRITE(PLANE_POS(pipe, plane), 0);
} else {
+ WARN_ON(fb->pixel_format == DRM_FORMAT_NV12);
I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
}
--
1.7.9.5
___
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[Intel-gfx] [PATCH 13/15] drm/i915: skl nv12 wa - disable streamer fix
When the plane source pixel format is NV12, the CHICKEN_PIPESL
register bit 22 must be set to 1
v2:
-one wa per commit with comments, and function headers (Daniel)
v3:
-moved intel stepping helper functions to i915_drv.c (Daniel)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 43 ++
drivers/gpu/drm/i915/i915_reg.h | 12 ++
drivers/gpu/drm/i915/intel_csr.c | 29 ---
drivers/gpu/drm/i915/intel_display.c | 11 +
drivers/gpu/drm/i915/intel_drv.h |2 ++
drivers/gpu/drm/i915/intel_sprite.c | 11 +
6 files changed, 79 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1d88745..0006369 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -391,6 +391,49 @@ static const struct intel_device_info intel_broxton_info =
{
IVB_CURSOR_OFFSETS,
};
+/* stepping info */
+struct stepping_info {
+ char stepping;
+ char substepping;
+};
+
+/* skl stepping info */
+static const struct stepping_info skl_stepping_info[] = {
+ {'A', '0'}, {'B', '0'}, {'C', '0'},
+ {'D', '0'}, {'E', '0'}, {'F', '0'},
+ {'G', '0'}, {'H', '0'}, {'I', '0'},
+};
+
+/**
+ * intel_get_stepping() - get stepping info
+ * @dev: drm device.
+ *
+ * Returns stepping id 'A', 'B', 'C', etc.
+ */
+char intel_get_stepping(struct drm_device *dev)
+{
+ if (IS_SKYLAKE(dev) && (dev->pdev->revision <
+ ARRAY_SIZE(skl_stepping_info)))
+ return skl_stepping_info[dev->pdev->revision].stepping;
+ else
+ return -ENODATA;
+}
+
+/**
+ * intel_get_substepping() - get substepping info
+ * @dev: drm device.
+ *
+ * Returns substepping id '0', '1', '2', etc.
+ */
+char intel_get_substepping(struct drm_device *dev)
+{
+ if (IS_SKYLAKE(dev) && (dev->pdev->revision <
+ ARRAY_SIZE(skl_stepping_info)))
+ return skl_stepping_info[dev->pdev->revision].substepping;
+ else
+ return -ENODATA;
+}
+
/*
* Make sure any device matches here are from most specific to most
* general. For example, since the Quanta match is based on the subsystem
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ae40b22..d20f235 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5354,6 +5354,18 @@ enum skl_disp_power_wells {
#define PLANE_NV12_BUF_CFG(pipe, plane)\
_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
+/*
+ * Skylake Chicken registers
+ */
+#define _CHICKEN_PIPESL_A 0x420B0
+#define _CHICKEN_PIPESL_B 0x420B4
+#define _CHICKEN_PIPESL_C 0x420B8
+#define DISABLE_STREAMER_FIX (1 << 22)
+#define CHICKEN_PIPESL(pipe) _PIPE(pipe, _CHICKEN_PIPESL_A, _CHICKEN_PIPESL_B)
+
+#define CHICKEN_DCPR_1 0x46430
+#define IDLE_WAKEMEM_MASK (1 << 13)
+
/* SKL new cursor registers */
#define _CUR_BUF_CFG_A 0x7017c
#define _CUR_BUF_CFG_B 0x7117c
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index ba1ae03..9577727 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -170,35 +170,6 @@ struct intel_dmc_header {
uint32_t reserved1[2];
} __packed;
-struct stepping_info {
- char stepping;
- char substepping;
-};
-
-static const struct stepping_info skl_stepping_info[] = {
- {'A', '0'}, {'B', '0'}, {'C', '0'},
- {'D', '0'}, {'E', '0'}, {'F', '0'},
- {'G', '0'}, {'H', '0'}, {'I', '0'}
-};
-
-static char intel_get_stepping(struct drm_device *dev)
-{
- if (IS_SKYLAKE(dev) && (dev->pdev->revision <
- ARRAY_SIZE(skl_stepping_info)))
- return skl_stepping_info[dev->pdev->revision].stepping;
- else
- return -ENODATA;
-}
-
-static char intel_get_substepping(struct drm_device *dev)
-{
- if (IS_SKYLAKE(dev) && (dev->pdev->revision <
- ARRAY_SIZE(skl_stepping_info)))
- return skl_stepping_info[dev->pdev->revision].substepping;
- else
- return -ENODATA;
-}
-
/**
* intel_csr_load_status_get() - to get firmware loading status.
* @dev_priv: i915 device.
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3296d16..9e11439 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3196,6 +3196,17 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
I915_WRITE(PLANE_AUX_DIST(pipe, 0), aux_dist | aux_stride);
I915_WRITE(PLANE_
[Intel-gfx] [PATCH 14/15] drm/i915: skl nv12 wa - NV12 to RGB switch
Switching format from NV12 to RGB can result in display underrun
and corruption. This workaround sets bits 15 & 19 to 1 in
CLKGATE_DIS_PSL register to address transition underrun.
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h |8
drivers/gpu/drm/i915/intel_display.c | 25 +
2 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d20f235..2e2636d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5366,6 +5366,14 @@ enum skl_disp_power_wells {
#define CHICKEN_DCPR_1 0x46430
#define IDLE_WAKEMEM_MASK (1 << 13)
+#define CLKGATE_DIS_PSL_A0x46520
+#define CLKGATE_DIS_PSL_B0x46524
+#define CLKGATE_DIS_PSL_C0x46528
+#define DUPS1_GATING_DIS (1 << 15)
+#define DUPS2_GATING_DIS (1 << 19)
+#define DUPS3_GATING_DIS (1 << 23)
+#define CLKGATE_DIS_PSL(pipe) _PIPE(pipe, CLKGATE_DIS_PSL_A,
CLKGATE_DIS_PSL_B)
+
/* SKL new cursor registers */
#define _CUR_BUF_CFG_A 0x7017c
#define _CUR_BUF_CFG_B 0x7117c
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 9e11439..457b79b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5017,6 +5017,25 @@ static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc)
return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
}
+/*
+ * Switching format from NV12 to RGB can result in display underrun
+ * and corruption. Workaround is to set bits 15 & 19 to 1 in
+ * CLKGATE_DIS_PSL register.
+ */
+static void skl_wa_clkgate(struct drm_i915_private *dev_priv,
+ int pipe, int enable)
+{
+ if (pipe == PIPE_A || pipe == PIPE_B) {
+ if (enable)
+ I915_WRITE(CLKGATE_DIS_PSL(pipe),
+ DUPS1_GATING_DIS | DUPS2_GATING_DIS);
+ else
+ I915_WRITE(CLKGATE_DIS_PSL(pipe),
+ I915_READ(CLKGATE_DIS_PSL(pipe) &
+ ~(DUPS1_GATING_DIS|DUPS2_GATING_DIS)));
+ }
+}
+
static void haswell_crtc_enable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
@@ -5107,6 +5126,9 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_wait_for_vblank(dev, hsw_workaround_pipe);
intel_wait_for_vblank(dev, hsw_workaround_pipe);
}
+
+ /* workaround for NV12 */
+ skl_wa_clkgate(dev_priv, pipe, 1);
}
static void ironlake_pfit_disable(struct intel_crtc *crtc)
@@ -5224,6 +5246,9 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
intel_crtc->active = false;
intel_update_watermarks(crtc);
+
+ /* workaround for NV12 */
+ skl_wa_clkgate(dev_priv, intel_crtc->pipe, 0);
}
static void i9xx_pfit_enable(struct intel_crtc *crtc)
--
1.7.9.5
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[Intel-gfx] [PATCH 10/15] drm/i915: Add NV12 to primary plane programming.
This patch is adding NV12 support to skylake primary plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.
For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. Once GEM adds support
for seperate remappings for two subplanes, 90/270 support
to be added to plane programming.
v2:
-Use regular int instead of 16.16 in aux_offset calculations (me)
v3:
-Allow 90/270 for NV12 as its remapping is now supported (me)
v4:
-Rebased to current kernel version 4.2.0.rc4 (me)
v5:
-Used round up division for aux_stride calculation,
adjusted dst rect as part of macro pixel boundary calculation (Ville)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/i915_reg.h | 25 ++
drivers/gpu/drm/i915/intel_display.c | 59 --
2 files changed, 82 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 825d721..ae40b22 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5602,6 +5602,31 @@ enum skl_disp_power_wells {
_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)
+/*
+ * Skylake NV12 Register
+ */
+#define PLANE_AUX_DIST_1_A 0x701c0
+#define PLANE_AUX_DIST_2_A 0x702c0
+#define PLANE_AUX_DIST_1_B 0x711c0
+#define PLANE_AUX_DIST_2_B 0x712c0
+#define _PLANE_AUX_DIST_1(pipe)\
+ _PIPE(pipe, PLANE_AUX_DIST_1_A, PLANE_AUX_DIST_1_B)
+#define _PLANE_AUX_DIST_2(pipe)\
+ _PIPE(pipe, PLANE_AUX_DIST_2_A, PLANE_AUX_DIST_2_B)
+#define PLANE_AUX_DIST(pipe, plane)\
+ _PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
+
+#define PLANE_AUX_OFFSET_1_A 0x701c4
+#define PLANE_AUX_OFFSET_2_A 0x702c4
+#define PLANE_AUX_OFFSET_1_B 0x711c4
+#define PLANE_AUX_OFFSET_2_B 0x712c4
+#define _PLANE_AUX_OFFSET_1(pipe) \
+ _PIPE(pipe, PLANE_AUX_OFFSET_1_A, PLANE_AUX_OFFSET_1_B)
+#define _PLANE_AUX_OFFSET_2(pipe) \
+ _PIPE(pipe, PLANE_AUX_OFFSET_2_A, PLANE_AUX_OFFSET_2_B)
+#define PLANE_AUX_OFFSET(pipe, plane) \
+ _PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
+
/* legacy palette */
#define _LGC_PALETTE_A 0x4a000
#define _LGC_PALETTE_B 0x4a800
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5433c6d..6714066 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3026,6 +3026,8 @@ u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
case DRM_FORMAT_VYUY:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
+ case DRM_FORMAT_NV12:
+ return PLANE_CTL_FORMAT_NV12;
default:
MISSING_CASE(pixel_format);
}
@@ -3094,6 +3096,8 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
int scaler_id = -1;
+ u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ u32 tile_row_adjustment = 0;
plane_state = to_intel_plane_state(plane->state);
@@ -3150,11 +3154,34 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
x_offset = stride * tile_height - y - src_h;
y_offset = x;
plane_size = (src_w - 1) << 16 | (src_h - 1);
+ /*
+* TBD: For NV12 90/270 rotation, Y and UV subplanes should
+* be treated as separate surfaces and GTT remapping for
+* rotation should be done separately for each subplane.
+* Enable support once seperate remappings are available.
+*/
} else {
stride = fb->pitches[0] / stride_div;
x_offset = x;
y_offset = y;
plane_size = (src_h - 1) << 16 | (src_w - 1);
+ tile_height = PAGE_SIZE / stride_div;
+
+ if (fb->pixel_format == DRM_FORMAT_NV12) {
+ int height_in_mem = (fb->offsets[1]/fb->pitches[0]);
+ /*
+* If UV starts from middle of a page, then UV start
should
+* be programmed to beginning of that page. And offset
into that
+* page to be programmed into y-offset
+*/
+ tile_row_adjustment = height_in_mem % tile_height;
+ aux_dist = fb->pitches[0] * (
[Intel-gfx] [PATCH 07/15] drm/i915: Add NV12 as supported format for primary plane
This patch adds NV12 to list of supported formats for
primary plane.
v2:
-Rebased (me)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3f9111e..84dad95 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -74,6 +74,19 @@ static const uint32_t skl_primary_formats[] = {
DRM_FORMAT_XBGR2101010,
};
+/* Primary plane formats for gen >= 9 with NV12 */
+static const uint32_t skl_primary_formats_with_nv12[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_NV12,
+};
+
/* Cursor formats */
static const uint32_t intel_cursor_formats[] = {
DRM_FORMAT_ARGB,
@@ -13612,8 +13625,13 @@ static struct drm_plane
*intel_primary_plane_create(struct drm_device *dev,
primary->plane = !pipe;
if (INTEL_INFO(dev)->gen >= 9) {
- intel_primary_formats = skl_primary_formats;
- num_formats = ARRAY_SIZE(skl_primary_formats);
+ if (pipe == PIPE_A || pipe == PIPE_B) {
+ intel_primary_formats = skl_primary_formats_with_nv12;
+ num_formats = ARRAY_SIZE(skl_primary_formats_with_nv12);
+ } else {
+ intel_primary_formats = skl_primary_formats;
+ num_formats = ARRAY_SIZE(skl_primary_formats);
+ }
} else if (INTEL_INFO(dev)->gen >= 4) {
intel_primary_formats = i965_primary_formats;
num_formats = ARRAY_SIZE(i965_primary_formats);
--
1.7.9.5
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[Intel-gfx] [PATCH 06/15] drm/i915: Upscale scaler max scale for NV12.
This patch updates max supported scaler limits for NV12.
v2:
-Rebased to current kernel version 4.2.0.rc4 (me)
v3:
-simplified max_scale calculation (Ville)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 17 +
drivers/gpu/drm/i915/intel_drv.h |3 ++-
drivers/gpu/drm/i915/intel_sprite.c |2 +-
3 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8869779..3f9111e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13423,7 +13423,9 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
}
int
-skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state
*crtc_state)
+skl_max_scale(struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *crtc_state,
+ uint32_t pixel_format)
{
int max_scale;
struct drm_device *dev;
@@ -13443,11 +13445,17 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct
intel_crtc_state *crtc_state
/*
* skl max scale is lower of:
-*close to 3 but not 3, -1 is for that purpose
+*close to 2 or 3 (NV12: 2, other formats: 3) but not equal,
+* -1 is for that purpose
*or
*cdclk/crtc_clock
*/
- max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) /
crtc_clock));
+ if (pixel_format == DRM_FORMAT_NV12)
+ max_scale = (2 << 16) - 1;
+ else
+ max_scale = (3 << 16) - 1;
+
+ max_scale = min(max_scale, (1 << 8) * ((cdclk << 8) / crtc_clock));
return max_scale;
}
@@ -13467,7 +13475,8 @@ intel_check_primary_plane(struct drm_plane *plane,
if (INTEL_INFO(plane->dev)->gen >= 9 &&
state->ckey.flags == I915_SET_COLORKEY_NONE) {
min_scale = 1;
- max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
+ max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state,
+ fb ? fb->pixel_format : 0);
can_position = true;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 18632a4..d50b8cb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1140,7 +1140,8 @@ void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc);
void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
-int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state
*crtc_state);
+int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
+ uint32_t pixel_format);
unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 8b73bb8..66d60ae 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -780,7 +780,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
can_scale = 1;
min_scale = 1;
- max_scale = skl_max_scale(intel_crtc, crtc_state);
+ max_scale = skl_max_scale(intel_crtc, crtc_state,
fb->pixel_format);
} else {
can_scale = 0;
min_scale = DRM_PLANE_HELPER_NO_SCALING;
--
1.7.9.5
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[Intel-gfx] [PATCH 04/15] drm/i915: Stage scaler request for NV12 as src format
This patch stages a scaler request when input format
is NV12. The same scaler does both chroma-upsampling
and resolution scaling as needed.
v2:
-Added helper function for need_scaling (Ville)
v3:
-Rebased to current kernel version 4.2.0.rc4 (me)
v4:
-minor updates (Ville)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 34 +++---
1 file changed, 27 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3ee1c17..8869779 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4341,20 +4341,38 @@ static void cpt_verify_modeset(struct drm_device *dev,
int pipe)
}
}
+static bool skl_need_scaling(int src_w, int src_h, int dst_w, int dst_h,
+ unsigned int rotation, uint32_t pixel_format)
+{
+ /* need a scaler when sizes doesn't match */
+ if (src_w != dst_w || src_h != dst_h)
+ return true;
+
+ /* in case of 90/270 rotation, check src width with dst height and so */
+ if (intel_rotation_90_or_270(rotation) &&
+ (src_h != dst_w || src_w != dst_h))
+ return true;
+
+ /* need a scaler for nv12 */
+ if (pixel_format == DRM_FORMAT_NV12)
+ return true;
+
+ return false;
+}
+
static int
skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
unsigned scaler_user, int *scaler_id, unsigned int rotation,
- int src_w, int src_h, int dst_w, int dst_h)
+ int src_w, int src_h, int dst_w, int dst_h, uint32_t
pixel_format)
{
struct intel_crtc_scaler_state *scaler_state =
_state->scaler_state;
struct intel_crtc *intel_crtc =
to_intel_crtc(crtc_state->base.crtc);
- int need_scaling;
+ bool need_scaling;
- need_scaling = intel_rotation_90_or_270(rotation) ?
- (src_h != dst_w || src_w != dst_h):
- (src_w != dst_w || src_h != dst_h);
+ need_scaling = skl_need_scaling(src_w, src_h, dst_w, dst_h, rotation,
+ pixel_format);
/*
* if plane is being disabled or scaler is no more required or force
detach
@@ -4423,7 +4441,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state)
return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
>scaler_state.scaler_id, DRM_ROTATE_0,
state->pipe_src_w, state->pipe_src_h,
- adjusted_mode->hdisplay, adjusted_mode->vdisplay);
+ adjusted_mode->hdisplay, adjusted_mode->vdisplay, 0);
}
/**
@@ -4459,7 +4477,8 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
drm_rect_width(_state->src) >> 16,
drm_rect_height(_state->src) >> 16,
drm_rect_width(_state->dst),
- drm_rect_height(_state->dst));
+ drm_rect_height(_state->dst),
+ fb ? fb->pixel_format : 0);
if (ret || plane_state->scaler_id < 0)
return ret;
@@ -4484,6 +4503,7 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+ case DRM_FORMAT_NV12:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format
0x%x\n",
--
1.7.9.5
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[Intel-gfx] [PATCH 03/15] drm/i915: Set scaler mode for NV12
This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling.
v2:
- new reg defines squashed into patches used them (Ville)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_atomic.c |5 -
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1fa0554..825d721 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5498,6 +5498,7 @@ enum skl_disp_power_wells {
#define PS_SCALER_MODE_MASK (3 << 28)
#define PS_SCALER_MODE_DYN (0 << 28)
#define PS_SCALER_MODE_HQ (1 << 28)
+#define PS_SCALER_MODE_NV12 (2 << 28)
#define PS_PLANE_SEL_MASK (7 << 25)
#define PS_PLANE_SEL(plane) ((plane + 1) << 25)
#define PS_FILTER_MASK (3 << 23)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm/i915/intel_atomic.c
index 9336e80..fd3972c 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -247,7 +247,10 @@ int intel_atomic_setup_scalers(struct drm_device *dev,
}
/* set scaler mode */
- if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
+ if (plane_state && plane_state->base.fb &&
+ plane_state->base.fb->pixel_format == DRM_FORMAT_NV12) {
+ scaler_state->scalers[*scaler_id].mode =
PS_SCALER_MODE_NV12;
+ } else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C)
{
/*
* when only 1 scaler is in use on either pipe A or B,
* scaler 0 operates in high quality (HQ) mode.
--
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[Intel-gfx] [PATCH 08/15] drm/i915: Add NV12 as supported format for sprite plane
This patch adds NV12 to list of supported formats for
sprite plane.
v2:
- made supported format list const, fixed a leftover -1. (Ville)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_sprite.c | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 66d60ae..797594e 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1029,7 +1029,7 @@ static const uint32_t vlv_plane_formats[] = {
DRM_FORMAT_VYUY,
};
-static uint32_t skl_plane_formats[] = {
+static const uint32_t skl_plane_formats[] = {
DRM_FORMAT_RGB565,
DRM_FORMAT_ABGR,
DRM_FORMAT_ARGB,
@@ -1041,6 +1041,19 @@ static uint32_t skl_plane_formats[] = {
DRM_FORMAT_VYUY,
};
+static const uint32_t skl_plane_formats_with_nv12[] = {
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+};
+
int
intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
{
@@ -1112,8 +1125,14 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe,
int plane)
intel_plane->disable_plane = skl_disable_plane;
state->scaler_id = -1;
- plane_formats = skl_plane_formats;
- num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+ if ((pipe == PIPE_A || pipe == PIPE_B) && (plane == 0)) {
+ plane_formats = skl_plane_formats_with_nv12;
+ num_plane_formats =
ARRAY_SIZE(skl_plane_formats_with_nv12);
+ } else {
+ plane_formats = skl_plane_formats;
+ num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+ }
+
break;
default:
kfree(intel_plane);
--
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[Intel-gfx] [PATCH 09/15] drm/i915: Add NV12 support to intel_framebuffer_init
This patch adds NV12 as supported format to
intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (me)
v3:
-cosmetic update, split checks into two (Ville)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 33 -
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 84dad95..5433c6d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14349,9 +14349,40 @@ static int intel_framebuffer_init(struct drm_device
*dev,
return -EINVAL;
}
break;
+ case DRM_FORMAT_NV12:
+ if (INTEL_INFO(dev)->gen < 9) {
+ DRM_DEBUG("unsupported pixel format: %s\n",
+ drm_get_format_name(mode_cmd->pixel_format));
+ return -EINVAL;
+ }
+ if (!mode_cmd->offsets[1]) {
+ DRM_DEBUG("uv start offset not set\n");
+ return -EINVAL;
+ }
+ if (mode_cmd->pitches[0] != mode_cmd->pitches[1]) {
+ DRM_DEBUG("y and uv subplanes have different
pitches\n");
+ return -EINVAL;
+ }
+ if (mode_cmd->handles[0] != mode_cmd->handles[1]) {
+ DRM_DEBUG("y and uv subplanes have different
handles\n");
+ return -EINVAL;
+ }
+ if (mode_cmd->modifier[1] == I915_FORMAT_MOD_Yf_TILED &&
+ (mode_cmd->offsets[1] & 0xFFF)) {
+ DRM_DEBUG("tile-Yf uv offset 0x%x isn't starting on new
tile-row\n",
+ mode_cmd->offsets[1]);
+ return -EINVAL;
+ }
+ if (mode_cmd->modifier[1] == I915_FORMAT_MOD_Y_TILED &&
+ ((mode_cmd->offsets[1] / mode_cmd->pitches[1]) % 4)) {
+ DRM_DEBUG("tile-Y uv offset 0x%x isn't 4-line
aligned\n",
+ mode_cmd->offsets[1]);
+ return -EINVAL;
+ }
+ break;
default:
DRM_DEBUG("unsupported pixel format: %s\n",
- drm_get_format_name(mode_cmd->pixel_format));
+ drm_get_format_name(mode_cmd->pixel_format));
return -EINVAL;
}
--
1.7.9.5
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[Intel-gfx] [PATCH 00/15] drm/i915: Adding NV12 for skylake display
This patch series is adding initial NV12 support for Skylake display after rebasing on latest drm-intel-nightly. Earlier I had two patch series one for 0/180 and another for 90/270. Some of the patches were already merged. This is combined series to support 0/90/180/270 and removing the ones that are already merged. Feature is tested with igt/kms_nv12 testcases. Feature is unit tested for linear/X/Y formats in 0, 90, 180, 270 orientations with combinations of 1 or 2 planes enabled along with scaling. Also negatively tested for enabling NV12 on unsupported plane. The last patch in this series depends on Tvrtko's GEM remapping for NV12 format patch series. First two patches fixing couple things in dbuf logic to allocate correct min number of dbuf blocks and use correct source width and height in 90/270 rotation cases. Update from last rev: -Resolved Ville's full review comments. -Changes were described in individual patch headers. So far R-B tag was issued for 1, 4, 6, 9 (in old series) That changes to 1, 3, 5, 8 because older 3rd patch was squashed. As number of patches are changed from previous rev due to some code refactoring, squashing and various minor updates, sending full series to keep patch numbering consistent. Chandra Konduru (15): drm/i915: Allocate min dbuf blocks per bspec drm/i915: In DBUF/WM calcs for 90/270, swap w & h drm/i915: Set scaler mode for NV12 drm/i915: Stage scaler request for NV12 as src format drm/i915: Update format_is_yuv() to include NV12 drm/i915: Upscale scaler max scale for NV12. drm/i915: Add NV12 as supported format for primary plane drm/i915: Add NV12 as supported format for sprite plane drm/i915: Add NV12 support to intel_framebuffer_init drm/i915: Add NV12 to primary plane programming. drm/i915: Add NV12 to sprite plane programming. drm/i915: Set initial phase & trip for NV12 scaler drm/i915: skl nv12 wa - disable streamer fix drm/i915: skl nv12 wa - NV12 to RGB switch drm/i915: Add 90/270 rotation for NV12 format. drivers/gpu/drm/i915/i915_drv.c | 43 +++ drivers/gpu/drm/i915/i915_reg.h | 46 +++ drivers/gpu/drm/i915/intel_atomic.c |5 +- drivers/gpu/drm/i915/intel_csr.c | 29 - drivers/gpu/drm/i915/intel_display.c | 226 +++--- drivers/gpu/drm/i915/intel_drv.h |6 +- drivers/gpu/drm/i915/intel_pm.c | 57 - drivers/gpu/drm/i915/intel_sprite.c | 127 +++ 8 files changed, 464 insertions(+), 75 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/15] drm/i915: In DBUF/WM calcs for 90/270, swap w & h
This patch swaps src width and height for dbuf/wm calculations
when rotation is 90/270 as per hw requirements.
v2:
- minor/cosmetic changes, removed plane_state check kludge (Ville)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 28
1 file changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4d3aca0..8a36ab9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3187,10 +3187,14 @@ static void skl_compute_wm_pipe_parameters(struct
drm_crtc *crtc,
p->active = intel_crtc->active;
if (p->active) {
+ const struct intel_plane_state *plane_state;
+ int src_w, src_h;
+
p->pipe_htotal =
intel_crtc->config->base.adjusted_mode.crtc_htotal;
p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
fb = crtc->primary->state->fb;
+ plane_state = to_intel_plane_state(crtc->primary->state);
/* For planar: Bpp is for uv plane, y_Bpp is for y plane */
if (fb) {
p->plane[0].enabled = true;
@@ -3205,8 +3209,17 @@ static void skl_compute_wm_pipe_parameters(struct
drm_crtc *crtc,
p->plane[0].y_bytes_per_pixel = 0;
p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
}
- p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
- p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
+
+ src_w = drm_rect_width(_state->src) >> 16;
+ src_h = drm_rect_height(_state->src) >> 16;
+
+ if (intel_rotation_90_or_270(crtc->primary->state->rotation)) {
+ p->plane[0].horiz_pixels = src_h;
+ p->plane[0].vert_pixels = src_w;
+ } else {
+ p->plane[0].horiz_pixels = src_w;
+ p->plane[0].vert_pixels = src_h;
+ }
p->plane[0].rotation = crtc->primary->state->rotation;
fb = crtc->cursor->state->fb;
@@ -3740,8 +3753,15 @@ skl_update_sprite_wm(struct drm_plane *plane, struct
drm_crtc *crtc,
intel_plane->wm.enabled = enabled;
intel_plane->wm.scaled = scaled;
- intel_plane->wm.horiz_pixels = sprite_width;
- intel_plane->wm.vert_pixels = sprite_height;
+
+ if (intel_rotation_90_or_270(plane->state->rotation)) {
+ intel_plane->wm.horiz_pixels = sprite_height;
+ intel_plane->wm.vert_pixels = sprite_width;
+ } else {
+ intel_plane->wm.horiz_pixels = sprite_width;
+ intel_plane->wm.vert_pixels = sprite_height;
+ }
+
intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
/* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
--
1.7.9.5
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[Intel-gfx] [PATCH 05/15] drm/i915: Update format_is_yuv() to include NV12
This patch adds NV12 to format_is_yuv() function
and made it available for both primary and sprite
planes.
v2:
-Use intel_ prefix for format_is_yuv (Ville)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
---
drivers/gpu/drm/i915/intel_drv.h|1 +
drivers/gpu/drm/i915/intel_sprite.c |9 +
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f44941b..18632a4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1394,6 +1394,7 @@ int intel_sprite_set_colorkey(struct drm_device *dev,
void *data,
void intel_pipe_update_start(struct intel_crtc *crtc,
uint32_t *start_vbl_count);
void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
+bool intel_format_is_yuv(uint32_t format);
/* intel_tv.c */
void intel_tv_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index c13c529..8b73bb8 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -39,14 +39,15 @@
#include
#include "i915_drv.h"
-static bool
-format_is_yuv(uint32_t format)
+bool
+intel_format_is_yuv(uint32_t format)
{
switch (format) {
case DRM_FORMAT_YUYV:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_YVYU:
+ case DRM_FORMAT_NV12:
return true;
default:
return false;
@@ -293,7 +294,7 @@ chv_update_csc(struct intel_plane *intel_plane, uint32_t
format)
int plane = intel_plane->plane;
/* Seems RGB data bypasses the CSC always */
- if (!format_is_yuv(format))
+ if (!intel_format_is_yuv(format))
return;
/*
@@ -857,7 +858,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
src_y = src->y1 >> 16;
src_h = drm_rect_height(src) >> 16;
- if (format_is_yuv(fb->pixel_format)) {
+ if (intel_format_is_yuv(fb->pixel_format)) {
src_x &= ~1;
src_w &= ~1;
--
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[Intel-gfx] [PATCH 15/15] drm/i915: Add 90/270 rotation for NV12 format.
Adding NV12 90/270 rotation support for primary and sprite planes.
v2:
-For 90/270 adjust pixel boundary only in Y-direction (bspec)
v3:
-Rebased (me)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 46 +++-
drivers/gpu/drm/i915/intel_sprite.c | 56 ++
2 files changed, 69 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 457b79b..4501e48 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3096,7 +3096,8 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
int scaler_id = -1;
- u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ unsigned long aux_dist = 0;
+ u32 aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
u32 tile_row_adjustment = 0;
u32 hphase = 0, vphase = 0;
@@ -3155,12 +3156,16 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
x_offset = stride * tile_height - y - src_h;
y_offset = x;
plane_size = (src_w - 1) << 16 | (src_h - 1);
- /*
-* TBD: For NV12 90/270 rotation, Y and UV subplanes should
-* be treated as separate surfaces and GTT remapping for
-* rotation should be done separately for each subplane.
-* Enable support once seperate remappings are available.
-*/
+
+ if (fb->pixel_format == DRM_FORMAT_NV12) {
+ u32 uv_tile_height = intel_tile_height(dev,
fb->pixel_format,
+ fb->modifier[0], 1);
+ aux_stride = DIV_ROUND_UP(fb->height / 2,
uv_tile_height);
+ aux_dist =
intel_plane_obj_offset(to_intel_plane(plane), obj, 1) -
+ surf_addr;
+ aux_x_offset = aux_stride * uv_tile_height - y / 2 -
fb->height / 2;
+ aux_y_offset = x / 2;
+ }
} else {
stride = fb->pitches[0] / stride_div;
x_offset = x;
@@ -11708,8 +11713,13 @@ int intel_plane_atomic_calc_changes(struct
drm_crtc_state *crtc_state,
if (fb && intel_format_is_yuv(fb->pixel_format)) {
bool can_scale = false;
- intel_plane_state->src.x1 &= ~0x1;
- intel_plane_state->src.x2 &= ~0x1;
+ if (intel_rotation_90_or_270(plane_state->rotation)) {
+ intel_plane_state->src.y1 &= ~0x1;
+ intel_plane_state->src.y2 &= ~0x1;
+ } else {
+ intel_plane_state->src.x1 &= ~0x1;
+ intel_plane_state->src.x2 &= ~0x1;
+ }
/* scaler use allowed when colorkey isn't requested */
if ((INTEL_INFO(dev)->gen >= 9) &&
@@ -11718,12 +11728,20 @@ int intel_plane_atomic_calc_changes(struct
drm_crtc_state *crtc_state,
/* Must keep src and dst the same if we can't scale. */
if (!can_scale) {
- intel_plane_state->dst.x1 &= ~1;
- intel_plane_state->dst.x2 &= ~1;
+ if (intel_rotation_90_or_270(plane_state->rotation)) {
+ intel_plane_state->dst.y1 &= ~1;
+ intel_plane_state->dst.y2 &= ~1;
+
+ if (drm_rect_height(_plane_state->dst) ==
0)
+ intel_plane_state->visible = false;
+ } else {
+ intel_plane_state->dst.x1 &= ~1;
+ intel_plane_state->dst.x2 &= ~1;
+
+ if (drm_rect_width(_plane_state->dst) ==
0)
+ intel_plane_state->visible = false;
+ }
}
-
- if (drm_rect_width(_plane_state->dst) == 0)
- intel_plane_state->visible = false;
}
if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 07f88f3..3cf601d 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -188,7 +188,8 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
int x_offset, y_offset;
struct intel_crtc_state *crtc_
[Intel-gfx] [PATCH 01/15] drm/i915: Allocate min dbuf blocks per bspec
Properly allocate min blocks per hw requirements.
v2:
- changed helper functional param to bool, some code simplification (Ville)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fff0c22..4d3aca0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2959,6 +2959,31 @@ skl_get_total_relative_data_rate(struct intel_crtc
*intel_crtc,
return total_data_rate;
}
+static uint16_t
+skl_dbuf_min_alloc(const struct intel_plane_wm_parameters *p, bool y_plane)
+{
+ uint16_t min_alloc;
+
+ /* For packed formats, no y-plane, return 0 */
+ if (y_plane && !p->y_bytes_per_pixel)
+ return 0;
+
+ if (p->tiling == I915_FORMAT_MOD_Y_TILED ||
+ p->tiling == I915_FORMAT_MOD_Yf_TILED) {
+ uint32_t min_scanlines = 8;
+ uint8_t bytes_per_pixel =
+ y_plane ? p->y_bytes_per_pixel : p->bytes_per_pixel;
+
+ min_scanlines = 32 / bytes_per_pixel;
+ min_alloc = DIV_ROUND_UP((4 * p->horiz_pixels/(y_plane ? 1 : 2)
*
+ bytes_per_pixel), 512) * min_scanlines/4 + 3;
+ } else {
+ min_alloc = 8;
+ }
+
+ return min_alloc;
+}
+
static void
skl_allocate_pipe_ddb(struct drm_crtc *crtc,
const struct intel_wm_config *config,
@@ -2999,9 +3024,9 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
if (!p->enabled)
continue;
- minimum[plane] = 8;
+ minimum[plane] = skl_dbuf_min_alloc(p, false); /*
uv-plane/packed */
alloc_size -= minimum[plane];
- y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
+ y_minimum[plane] = skl_dbuf_min_alloc(p, true); /* y-plane */
alloc_size -= y_minimum[plane];
}
--
1.7.9.5
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[Intel-gfx] [PATCH 12/15] drm/i915: Set initial phase & trip for NV12 scaler
This patch sets default initial phase and trip to scale NV12 content. In future, if needed these can be set via properties or other means depending on incoming stream request. Until then defaults are fine. Signed-off-by: Chandra Konduru <chandra.kond...@intel.com> --- drivers/gpu/drm/i915/intel_display.c |7 +++ drivers/gpu/drm/i915/intel_sprite.c |7 +++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 6714066..3296d16 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3098,6 +3098,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, int scaler_id = -1; u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0; u32 tile_row_adjustment = 0; + u32 hphase = 0, vphase = 0; plane_state = to_intel_plane_state(plane->state); @@ -3181,6 +3182,9 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, /* For tile-Yf, uv-subplane tile width is 2x of Y-subplane */ aux_stride = fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED ? DIV_ROUND_UP(stride, 2) : stride; + + hphase = 0x00010001; /* use trip for both Y and UV */ + vphase = 0x00012000; /* use trip for Y and phase 0.5 for UV */ } } plane_offset = y_offset << 16 | x_offset; @@ -3209,6 +3213,9 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); } + I915_WRITE(SKL_PS_HPHASE(pipe, scaler_id), hphase); + I915_WRITE(SKL_PS_VPHASE(pipe, scaler_id), vphase); + I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); POSTING_READ(PLANE_SURF(pipe, 0)); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 347fb1f..5ca62b6 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -190,6 +190,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, int scaler_id; u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0; u32 tile_row_adjustment = 0; + u32 hphase = 0, vphase = 0; plane_ctl = PLANE_CTL_ENABLE | PLANE_CTL_PIPE_CSC_ENABLE; @@ -264,6 +265,9 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, /* For tile-Yf, uv-subplane tile width is 2x of Y-subplane */ aux_stride = fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED ? DIV_ROUND_UP(stride, 2) : stride; + + hphase = 0x00010001; /* use trip for both Y and UV */ + vphase = 0x00012000; /* use trip for Y and phase 0.5 for UV */ } } plane_offset = y_offset << 16 | x_offset; @@ -292,6 +296,9 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); } + I915_WRITE(SKL_PS_HPHASE(pipe, scaler_id), hphase); + I915_WRITE(SKL_PS_VPHASE(pipe, scaler_id), vphase); + I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); I915_WRITE(PLANE_SURF(pipe, plane), surf_addr); POSTING_READ(PLANE_SURF(pipe, plane)); -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 2/2] Adding kms_nv12 to test display NV12 feature
From: chandra konduru <chandra.kond...@intel.com>
This patch adds kms_nv12 test case. It covers testing NV12
in linear/tile-X/tile-Y tiling formats in 0/90/180/270
orientations. For each tiling format, it tests several
combinations of planes and its scaling.
v2:
-Added 90/270 tests (me)
-took out crc test as it isn't adding much value due to chroma upsampling (me)
v3:
-Make --list-subtests option work (Tvrtko)
-Make nv12 unsupported test run properly either as a sub test
or along with all other tests (me)
-Added nv12 fb with invalid params (Daniel)
v4:
-Avoid modeset for invalid tests (Daniel)
Signed-off-by: chandra konduru <chandra.kond...@intel.com>
---
tests/.gitignore | 1 +
tests/Makefile.sources | 1 +
tests/kms_nv12.c | 753 +
3 files changed, 755 insertions(+)
create mode 100644 tests/kms_nv12.c
diff --git a/tests/.gitignore b/tests/.gitignore
index d6d05ff..2de4712 100644
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -155,6 +155,7 @@ kms_setmode
kms_sink_crc_basic
kms_universal_plane
kms_vblank
+kms_nv12
pm_backlight
pm_lpsp
pm_rc6_residency
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index ef69299..a7804fa 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -85,6 +85,7 @@ TESTS_progs_M = \
kms_crtc_background_color \
kms_plane_scaling \
kms_panel_fitting \
+ kms_nv12 \
pm_backlight \
pm_lpsp \
pm_rpm \
diff --git a/tests/kms_nv12.c b/tests/kms_nv12.c
new file mode 100644
index 000..61f826a
--- /dev/null
+++ b/tests/kms_nv12.c
@@ -0,0 +1,753 @@
+/*
+ * Copyright © 2013,2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+#include
+#include
+
+#include "drmtest.h"
+#include "igt_debugfs.h"
+#include "igt_kms.h"
+#include "igt_core.h"
+#include "intel_chipset.h"
+#include "ioctl_wrappers.h"
+
+IGT_TEST_DESCRIPTION("Test display NV12 support");
+
+uint32_t devid;
+typedef struct {
+ int drm_fd;
+ igt_display_t display;
+ int num_scalers;
+ int num_planes;
+
+ struct igt_fb fb1;
+ struct igt_fb fb1_nv12;
+ struct igt_fb fb2;
+ struct igt_fb fb2_nv12;
+ struct igt_fb fb3;
+ struct igt_fb fb3_nv12;
+ int fb_id1;
+ int fb_id1_nv12;
+ int fb_id2;
+ int fb_id2_nv12;
+ int fb_id3;
+ int fb_id3_nv12;
+
+ igt_plane_t *plane1;
+ igt_plane_t *plane2;
+ igt_plane_t *plane3;
+
+ uint64_t tiled;
+ int rotation;
+} data_t;
+
+typedef struct {
+ int width;
+ int height;
+} res_t;
+
+#define IMG_FILE "1080p-left.png"
+
+static void
+paint_pattern(data_t *d, struct igt_fb *fb, uint16_t w, uint16_t h)
+{
+ cairo_t *cr;
+
+ cr = igt_get_cairo_ctx(d->drm_fd, fb);
+ igt_paint_test_pattern(cr, w, h);
+ cairo_destroy(cr);
+}
+
+static void
+paint_image(data_t *d, struct igt_fb *fb, uint16_t w, uint16_t h)
+{
+ cairo_t *cr;
+
+ cr = igt_get_cairo_ctx(d->drm_fd, fb);
+ igt_paint_image(cr, IMG_FILE, 0, 0, w, h);
+ cairo_destroy(cr);
+}
+
+static void prepare_crtc(data_t *data, igt_output_t *output, enum pipe pipe,
+ igt_plane_t *plane, drmModeModeInfo *mode, enum
igt_commit_style s)
+{
+ igt_display_t *display = >display;
+
+ igt_output_set_pipe(output, pipe);
+
+ /* before allocating, free if any older fb */
+ if (data->fb_id1) {
+ igt_remove_fb(data->drm_fd, >fb1);
+ data->fb_id1 = 0;
+ }
+
+ /* allocate fb for plane 1 */
+ data->fb_id1 = igt_create_fb(data->drm_fd,
+ mode->hdisplay, mode->vdisplay,
+
[Intel-gfx] [PATCH 00/16] drm/i915: Adding NV12 for skylake display
This patch series is adding initial NV12 support for Skylake display after rebasing on latest drm-intel-nightly. Earlier I had two patch series one for 0/180 and another for 90/270. Some of the patches were already merged. This is combined series to support 0/90/180/270 and removing the ones that are already merged. Feature is tested with igt/kms_nv12 testcases. Feature is unit tested for linear/X/Y formats in 0, 90, 180, 270 orientations with combinations of 1 or 2 planes enabled along with scaling. Also negatively tested for enabling NV12 on unsupported plane. The last patch in this series depends on Tvrtko's GEM remapping for NV12 format patch series. First two patches fixing couple things in dbuf logic to allocate correct min number of dbuf blocks and use correct source width and height in 90/270 rotation cases. Update from last rev: Resolved Daniel's review feedback - Did one WA per commit - Moved get stepping functions better place - Added comments Chandra Konduru (16): drm/i915: Allocate min dbuf blocks per bspec drm/i915: In DBUF/WM calcs for 90/270, swap w & h drm/i915: Add register definitions for NV12 support drm/i915: Set scaler mode for NV12 drm/i915: Stage scaler request for NV12 as src format drm/i915: Update format_is_yuv() to include NV12 drm/i915: Upscale scaler max scale for NV12. drm/i915: Add NV12 as supported format for primary plane drm/i915: Add NV12 as supported format for sprite plane drm/i915: Add NV12 support to intel_framebuffer_init drm/i915: Add NV12 to primary plane programming. drm/i915: Add NV12 to sprite plane programming. drm/i915: Set initial phase & trip for NV12 scaler drm/i915: skl nv12 wa - disable streamer fix drm/i915: skl nv12 wa - NV12 to RGB switch drm/i915: Add 90/270 rotation for NV12 format. drivers/gpu/drm/i915/i915_reg.h | 47 +++ drivers/gpu/drm/i915/intel_atomic.c |5 +- drivers/gpu/drm/i915/intel_csr.c | 29 - drivers/gpu/drm/i915/intel_display.c | 226 -- drivers/gpu/drm/i915/intel_drv.h |6 +- drivers/gpu/drm/i915/intel_pm.c | 71 ++- drivers/gpu/drm/i915/intel_sprite.c | 125 +++ 7 files changed, 439 insertions(+), 70 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/16] drm/i915: In DBUF/WM calcs for 90/270, swap w & h
This patch swaps src width and height for dbuf/wm calculations
when rotation is 90/270 as per hw requirements.
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 32
1 file changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index da3046f..c455946 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3193,6 +3193,8 @@ static void skl_compute_wm_pipe_parameters(struct
drm_crtc *crtc,
enum pipe pipe = intel_crtc->pipe;
struct drm_plane *plane;
struct drm_framebuffer *fb;
+ struct intel_plane_state *plane_state;
+ int src_w, src_h;
int i = 1; /* Index for sprite planes start */
p->active = intel_crtc->active;
@@ -3201,6 +3203,7 @@ static void skl_compute_wm_pipe_parameters(struct
drm_crtc *crtc,
p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
fb = crtc->primary->state->fb;
+ plane_state = to_intel_plane_state(crtc->primary->state);
/* For planar: Bpp is for uv plane, y_Bpp is for y plane */
if (fb) {
p->plane[0].enabled = true;
@@ -3215,8 +3218,22 @@ static void skl_compute_wm_pipe_parameters(struct
drm_crtc *crtc,
p->plane[0].y_bytes_per_pixel = 0;
p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
}
- p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
- p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
+
+ if (drm_rect_width(_state->src)) {
+ src_w = drm_rect_width(_state->src) >> 16;
+ src_h = drm_rect_height(_state->src) >> 16;
+ } else {
+ src_w = intel_crtc->config->pipe_src_w;
+ src_h = intel_crtc->config->pipe_src_h;
+ }
+
+ if (intel_rotation_90_or_270(crtc->primary->state->rotation)) {
+ p->plane[0].horiz_pixels = src_h;
+ p->plane[0].vert_pixels = src_w;
+ } else {
+ p->plane[0].horiz_pixels = src_w;
+ p->plane[0].vert_pixels = src_h;
+ }
p->plane[0].rotation = crtc->primary->state->rotation;
fb = crtc->cursor->state->fb;
@@ -3750,8 +3767,15 @@ skl_update_sprite_wm(struct drm_plane *plane, struct
drm_crtc *crtc,
intel_plane->wm.enabled = enabled;
intel_plane->wm.scaled = scaled;
- intel_plane->wm.horiz_pixels = sprite_width;
- intel_plane->wm.vert_pixels = sprite_height;
+
+ if (intel_rotation_90_or_270(plane->state->rotation)) {
+ intel_plane->wm.horiz_pixels = sprite_height;
+ intel_plane->wm.vert_pixels = sprite_width;
+ } else {
+ intel_plane->wm.horiz_pixels = sprite_width;
+ intel_plane->wm.vert_pixels = sprite_height;
+ }
+
intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
/* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
--
1.7.9.5
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[Intel-gfx] [PATCH 01/16] drm/i915: Allocate min dbuf blocks per bspec
Properly allocate min blocks per hw requirements.
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 39 +--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fff0c22..da3046f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2959,6 +2959,41 @@ skl_get_total_relative_data_rate(struct intel_crtc
*intel_crtc,
return total_data_rate;
}
+static uint16_t
+skl_dbuf_min_alloc(const struct intel_plane_wm_parameters *p, int y_plane)
+{
+ uint16_t min_alloc;
+
+ /* For packed formats, no y-plane, return 0 */
+ if (y_plane && !p->y_bytes_per_pixel)
+ return 0;
+
+
+ if (p->tiling == I915_FORMAT_MOD_Y_TILED ||
+ p->tiling == I915_FORMAT_MOD_Yf_TILED) {
+ uint32_t min_scanlines = 8;
+ uint8_t bytes_per_pixel =
+ y_plane ? p->y_bytes_per_pixel : p->bytes_per_pixel;
+
+ switch (bytes_per_pixel) {
+ case 1:
+ min_scanlines = 32;
+ break;
+ case 2:
+ min_scanlines = 16;
+ break;
+ case 8:
+ WARN(1, "Unsupported pixel depth for rotation");
+ }
+ min_alloc = DIV_ROUND_UP((4 * p->horiz_pixels/(y_plane ? 1 : 2)
*
+ bytes_per_pixel), 512) * min_scanlines/4 + 3;
+ } else {
+ min_alloc = 8;
+ }
+
+ return min_alloc;
+}
+
static void
skl_allocate_pipe_ddb(struct drm_crtc *crtc,
const struct intel_wm_config *config,
@@ -2999,9 +3034,9 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
if (!p->enabled)
continue;
- minimum[plane] = 8;
+ minimum[plane] = skl_dbuf_min_alloc(p, 0);/*
uv-plane/packed */
alloc_size -= minimum[plane];
- y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
+ y_minimum[plane] = skl_dbuf_min_alloc(p, 1); /* y-plane */
alloc_size -= y_minimum[plane];
}
--
1.7.9.5
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[Intel-gfx] [PATCH 05/16] drm/i915: Stage scaler request for NV12 as src format
This patch stages a scaler request when input format
is NV12. The same scaler does both chroma-upsampling
and resolution scaling as needed.
v2:
-Added helper function for need_scaling (Ville)
v3:
-Rebased to current kernel version 4.2.0.rc4 (me)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 30 --
1 file changed, 24 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3ee1c17..411b211 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4341,10 +4341,27 @@ static void cpt_verify_modeset(struct drm_device *dev,
int pipe)
}
}
+static int skl_need_scaling(int src_w, int dst_w, int src_h, int dst_h,
+ int rotation, uint32_t pixel_format)
+{
+ /* scaling is required when src dst sizes doesn't match or format is
NV12 */
+ if (src_w != dst_w || src_h != dst_h)
+ return 1;
+
+ if (intel_rotation_90_or_270(rotation) &&
+ (src_h != dst_w || src_w != dst_h))
+ return 1;
+
+ if (pixel_format == DRM_FORMAT_NV12)
+ return 1;
+
+ return 0;
+}
+
static int
skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
unsigned scaler_user, int *scaler_id, unsigned int rotation,
- int src_w, int src_h, int dst_w, int dst_h)
+ int src_w, int src_h, int dst_w, int dst_h, uint32_t
pixel_format)
{
struct intel_crtc_scaler_state *scaler_state =
_state->scaler_state;
@@ -4352,9 +4369,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state,
bool force_detach,
to_intel_crtc(crtc_state->base.crtc);
int need_scaling;
- need_scaling = intel_rotation_90_or_270(rotation) ?
- (src_h != dst_w || src_w != dst_h):
- (src_w != dst_w || src_h != dst_h);
+ need_scaling = skl_need_scaling(src_w, dst_w, src_h, dst_h, rotation,
+ pixel_format);
/*
* if plane is being disabled or scaler is no more required or force
detach
@@ -4423,7 +4439,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state)
return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
>scaler_state.scaler_id, DRM_ROTATE_0,
state->pipe_src_w, state->pipe_src_h,
- adjusted_mode->hdisplay, adjusted_mode->vdisplay);
+ adjusted_mode->hdisplay, adjusted_mode->vdisplay, 0);
}
/**
@@ -4459,7 +4475,8 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
drm_rect_width(_state->src) >> 16,
drm_rect_height(_state->src) >> 16,
drm_rect_width(_state->dst),
- drm_rect_height(_state->dst));
+ drm_rect_height(_state->dst),
+ fb ? fb->pixel_format : 0);
if (ret || plane_state->scaler_id < 0)
return ret;
@@ -4484,6 +4501,7 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+ case DRM_FORMAT_NV12:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format
0x%x\n",
--
1.7.9.5
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[Intel-gfx] [PATCH 06/16] drm/i915: Update format_is_yuv() to include NV12
This patch adds NV12 to format_is_yuv() function
and made it available for both primary and sprite
planes.
v2:
-Use intel_ prefix for format_is_yuv (Ville)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
---
drivers/gpu/drm/i915/intel_drv.h|1 +
drivers/gpu/drm/i915/intel_sprite.c |9 +
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f44941b..18632a4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1394,6 +1394,7 @@ int intel_sprite_set_colorkey(struct drm_device *dev,
void *data,
void intel_pipe_update_start(struct intel_crtc *crtc,
uint32_t *start_vbl_count);
void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
+bool intel_format_is_yuv(uint32_t format);
/* intel_tv.c */
void intel_tv_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index c13c529..8b73bb8 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -39,14 +39,15 @@
#include
#include "i915_drv.h"
-static bool
-format_is_yuv(uint32_t format)
+bool
+intel_format_is_yuv(uint32_t format)
{
switch (format) {
case DRM_FORMAT_YUYV:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_YVYU:
+ case DRM_FORMAT_NV12:
return true;
default:
return false;
@@ -293,7 +294,7 @@ chv_update_csc(struct intel_plane *intel_plane, uint32_t
format)
int plane = intel_plane->plane;
/* Seems RGB data bypasses the CSC always */
- if (!format_is_yuv(format))
+ if (!intel_format_is_yuv(format))
return;
/*
@@ -857,7 +858,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
src_y = src->y1 >> 16;
src_h = drm_rect_height(src) >> 16;
- if (format_is_yuv(fb->pixel_format)) {
+ if (intel_format_is_yuv(fb->pixel_format)) {
src_x &= ~1;
src_w &= ~1;
--
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[Intel-gfx] [PATCH 07/16] drm/i915: Upscale scaler max scale for NV12.
This patch updates max supported scaler limits for NV12.
v2:
-Rebased to current kernel version 4.2.0.rc4 (me)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 13 +
drivers/gpu/drm/i915/intel_drv.h |3 ++-
drivers/gpu/drm/i915/intel_sprite.c |2 +-
3 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 411b211..b1d9edf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13421,7 +13421,9 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
}
int
-skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state
*crtc_state)
+skl_max_scale(struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *crtc_state,
+ uint32_t pixel_format)
{
int max_scale;
struct drm_device *dev;
@@ -13441,11 +13443,13 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct
intel_crtc_state *crtc_state
/*
* skl max scale is lower of:
-*close to 3 but not 3, -1 is for that purpose
+*close to 2 or 3 (NV12: 2, other formats: 3) but not equal,
+* -1 is for that purpose
*or
*cdclk/crtc_clock
*/
- max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) /
crtc_clock));
+ max_scale = min((1 << 16) * (pixel_format == DRM_FORMAT_NV12 ? 2 : 3) -
1,
+ (1 << 8) * ((cdclk << 8) / crtc_clock));
return max_scale;
}
@@ -13465,7 +13469,8 @@ intel_check_primary_plane(struct drm_plane *plane,
if (INTEL_INFO(plane->dev)->gen >= 9 &&
state->ckey.flags == I915_SET_COLORKEY_NONE) {
min_scale = 1;
- max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
+ max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state,
+ fb ? fb->pixel_format : 0);
can_position = true;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 18632a4..d50b8cb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1140,7 +1140,8 @@ void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc);
void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
-int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state
*crtc_state);
+int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
+ uint32_t pixel_format);
unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 8b73bb8..66d60ae 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -780,7 +780,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
can_scale = 1;
min_scale = 1;
- max_scale = skl_max_scale(intel_crtc, crtc_state);
+ max_scale = skl_max_scale(intel_crtc, crtc_state,
fb->pixel_format);
} else {
can_scale = 0;
min_scale = DRM_PLANE_HELPER_NO_SCALING;
--
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[Intel-gfx] [PATCH 14/16] drm/i915: skl nv12 wa - disable streamer fix
When the plane source pixel format is NV12, the CHICKEN_PIPESL
register bit 22 must be set to 1
v2:
-one wa per commit with comments, and function headers (Daniel)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 12
drivers/gpu/drm/i915/intel_csr.c | 29 --
drivers/gpu/drm/i915/intel_display.c | 54 ++
drivers/gpu/drm/i915/intel_drv.h |2 ++
drivers/gpu/drm/i915/intel_sprite.c | 11 +++
5 files changed, 79 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c4d732f..84c5db6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5354,6 +5354,18 @@ enum skl_disp_power_wells {
#define PLANE_NV12_BUF_CFG(pipe, plane)\
_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
+/*
+ * Skylake Chicken registers
+ */
+#define _CHICKEN_PIPESL_A 0x420B0
+#define _CHICKEN_PIPESL_B 0x420B4
+#define _CHICKEN_PIPESL_C 0x420B8
+#define DISABLE_STREAMER_FIX (1 << 22)
+#define CHICKEN_PIPESL(pipe) _PIPE(pipe, _CHICKEN_PIPESL_A, _CHICKEN_PIPESL_B)
+
+#define CHICKEN_DCPR_1 0x46430
+#define IDLE_WAKEMEM_MASK (1 << 13)
+
/* SKL new cursor registers */
#define _CUR_BUF_CFG_A 0x7017c
#define _CUR_BUF_CFG_B 0x7117c
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index ba1ae03..9577727 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -170,35 +170,6 @@ struct intel_dmc_header {
uint32_t reserved1[2];
} __packed;
-struct stepping_info {
- char stepping;
- char substepping;
-};
-
-static const struct stepping_info skl_stepping_info[] = {
- {'A', '0'}, {'B', '0'}, {'C', '0'},
- {'D', '0'}, {'E', '0'}, {'F', '0'},
- {'G', '0'}, {'H', '0'}, {'I', '0'}
-};
-
-static char intel_get_stepping(struct drm_device *dev)
-{
- if (IS_SKYLAKE(dev) && (dev->pdev->revision <
- ARRAY_SIZE(skl_stepping_info)))
- return skl_stepping_info[dev->pdev->revision].stepping;
- else
- return -ENODATA;
-}
-
-static char intel_get_substepping(struct drm_device *dev)
-{
- if (IS_SKYLAKE(dev) && (dev->pdev->revision <
- ARRAY_SIZE(skl_stepping_info)))
- return skl_stepping_info[dev->pdev->revision].substepping;
- else
- return -ENODATA;
-}
-
/**
* intel_csr_load_status_get() - to get firmware loading status.
* @dev_priv: i915 device.
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 419660d..35e9f89 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -92,6 +92,19 @@ static const uint32_t intel_cursor_formats[] = {
DRM_FORMAT_ARGB,
};
+/* stepping info */
+struct stepping_info {
+ char stepping;
+ char substepping;
+};
+
+/* skl stepping info */
+static const struct stepping_info skl_stepping_info[] = {
+ {'A', '0'}, {'B', '0'}, {'C', '0'},
+ {'D', '0'}, {'E', '0'}, {'F', '0'},
+ {'G', '0'}, {'H', '0'}, {'I', '0'},
+};
+
static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
@@ -138,6 +151,36 @@ struct intel_limit {
intel_p2_t p2;
};
+/**
+ * intel_get_stepping() - get stepping info
+ * @dev: drm device.
+ *
+ * Returns stepping id 'A', 'B', 'C', etc.
+ */
+char intel_get_stepping(struct drm_device *dev)
+{
+ if (IS_SKYLAKE(dev) && (dev->pdev->revision <
+ ARRAY_SIZE(skl_stepping_info)))
+ return skl_stepping_info[dev->pdev->revision].stepping;
+ else
+ return -ENODATA;
+}
+
+/**
+ * intel_get_substepping() - get substepping info
+ * @dev: drm device.
+ *
+ * Returns substepping id '0', '1', '2', etc.
+ */
+char intel_get_substepping(struct drm_device *dev)
+{
+ if (IS_SKYLAKE(dev) && (dev->pdev->revision <
+ ARRAY_SIZE(skl_stepping_info)))
+ return skl_stepping_info[dev->pdev->revision].substepping;
+ else
+ return -ENODATA;
+}
+
int
intel_pch_rawclk(struct drm_device *dev)
{
@@ -3196,6 +3239,17 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
I915_WRITE(PLANE_AUX_DIST(pipe, 0), aux_dist | aux_stride);
I915_WRITE(PLANE_AUX_OFFSET(pipe, 0), aux_y_offset << 16 |
aux_x_offset);
+ /*
+* Per bspec, for SKL C and BXT A steppings, when the plane source pixel
+* format is NV12, the CHICKE
[Intel-gfx] [PATCH 03/16] drm/i915: Add register definitions for NV12 support
This patch adds register definitions for skylake
display NV12 support.
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1fa0554..c4d732f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5498,6 +5498,7 @@ enum skl_disp_power_wells {
#define PS_SCALER_MODE_MASK (3 << 28)
#define PS_SCALER_MODE_DYN (0 << 28)
#define PS_SCALER_MODE_HQ (1 << 28)
+#define PS_SCALER_MODE_NV12 (2 << 28)
#define PS_PLANE_SEL_MASK (7 << 25)
#define PS_PLANE_SEL(plane) ((plane + 1) << 25)
#define PS_FILTER_MASK (3 << 23)
@@ -5601,6 +5602,32 @@ enum skl_disp_power_wells {
_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)
+
+/*
+ * Skylake NV12 Register
+ */
+#define PLANE_AUX_DIST_1_A 0x701c0
+#define PLANE_AUX_DIST_2_A 0x702c0
+#define PLANE_AUX_DIST_1_B 0x711c0
+#define PLANE_AUX_DIST_2_B 0x712c0
+#define _PLANE_AUX_DIST_1(pipe)\
+ _PIPE(pipe, PLANE_AUX_DIST_1_A, PLANE_AUX_DIST_1_B)
+#define _PLANE_AUX_DIST_2(pipe)\
+ _PIPE(pipe, PLANE_AUX_DIST_2_A, PLANE_AUX_DIST_2_B)
+#define PLANE_AUX_DIST(pipe, plane)\
+ _PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
+
+#define PLANE_AUX_OFFSET_1_A 0x701c4
+#define PLANE_AUX_OFFSET_2_A 0x702c4
+#define PLANE_AUX_OFFSET_1_B 0x711c4
+#define PLANE_AUX_OFFSET_2_B 0x712c4
+#define _PLANE_AUX_OFFSET_1(pipe) \
+ _PIPE(pipe, PLANE_AUX_OFFSET_1_A, PLANE_AUX_OFFSET_1_B)
+#define _PLANE_AUX_OFFSET_2(pipe) \
+ _PIPE(pipe, PLANE_AUX_OFFSET_2_A, PLANE_AUX_OFFSET_2_B)
+#define PLANE_AUX_OFFSET(pipe, plane) \
+ _PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
+
/* legacy palette */
#define _LGC_PALETTE_A 0x4a000
#define _LGC_PALETTE_B 0x4a800
--
1.7.9.5
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[Intel-gfx] [PATCH 12/16] drm/i915: Add NV12 to sprite plane programming.
This patch is adding NV12 support to skylake sprite plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.
For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. Once GEM adds support
for seperate remappings for two subplanes, 90/270 support
to be added to plane programming.
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_sprite.c | 31 +--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 4e8c020..a1384a7 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -188,6 +188,8 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
int x_offset, y_offset;
struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config;
int scaler_id;
+ u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ u32 tile_row_adjustment = 0;
plane_ctl = PLANE_CTL_ENABLE |
PLANE_CTL_PIPE_CSC_ENABLE;
@@ -234,24 +236,48 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
plane_size = (src_w << 16) | src_h;
x_offset = stride * tile_height - y - (src_h + 1);
y_offset = x;
+
+ /*
+* TBD: For NV12 90/270 rotation, Y and UV subplanes should
+* be treated as separate surfaces and GTT remapping for
+* rotation should be done separately for each subplane.
+* Enable support once seperate remappings are available.
+*/
} else {
stride = fb->pitches[0] / stride_div;
plane_size = (src_h << 16) | src_w;
x_offset = x;
y_offset = y;
+ tile_height = PAGE_SIZE / stride_div;
+
+ if (fb->pixel_format == DRM_FORMAT_NV12) {
+ int height_in_mem = (fb->offsets[1]/fb->pitches[0]);
+ /*
+* If UV starts from middle of a page, then UV start
should
+* be programmed to beginning of that page. And offset
into that
+* page to be programmed into y-offset
+*/
+ tile_row_adjustment = height_in_mem % tile_height;
+ aux_dist = fb->pitches[0] * (height_in_mem -
tile_row_adjustment);
+ aux_x_offset = DIV_ROUND_UP(x, 2);
+ aux_y_offset = DIV_ROUND_UP(y, 2) + tile_row_adjustment;
+ /* For tile-Yf, uv-subplane tile width is 2x of
Y-subplane */
+ aux_stride = fb->modifier[0] ==
I915_FORMAT_MOD_Yf_TILED ?
+ stride / 2 : stride;
+ }
}
plane_offset = y_offset << 16 | x_offset;
I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
+ I915_WRITE(PLANE_AUX_DIST(pipe, plane), aux_dist | aux_stride);
+ I915_WRITE(PLANE_AUX_OFFSET(pipe, plane), aux_y_offset<<16 |
aux_x_offset);
/* program plane scaler */
if (scaler_id >= 0) {
uint32_t ps_ctrl = 0;
- DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
- PS_PLANE_SEL(plane));
ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) |
crtc_state->scaler_state.scalers[scaler_id].mode;
I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
@@ -262,6 +288,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
I915_WRITE(PLANE_POS(pipe, plane), 0);
} else {
+ WARN_ON(fb->pixel_format == DRM_FORMAT_NV12);
I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
}
--
1.7.9.5
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[Intel-gfx] [PATCH 04/16] drm/i915: Set scaler mode for NV12
This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling.
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
---
drivers/gpu/drm/i915/intel_atomic.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm/i915/intel_atomic.c
index 9336e80..fd3972c 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -247,7 +247,10 @@ int intel_atomic_setup_scalers(struct drm_device *dev,
}
/* set scaler mode */
- if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
+ if (plane_state && plane_state->base.fb &&
+ plane_state->base.fb->pixel_format == DRM_FORMAT_NV12) {
+ scaler_state->scalers[*scaler_id].mode =
PS_SCALER_MODE_NV12;
+ } else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C)
{
/*
* when only 1 scaler is in use on either pipe A or B,
* scaler 0 operates in high quality (HQ) mode.
--
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[Intel-gfx] [PATCH 09/16] drm/i915: Add NV12 as supported format for sprite plane
This patch adds NV12 to list of supported formats for
sprite plane.
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_sprite.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 66d60ae..4e8c020 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1041,6 +1041,19 @@ static uint32_t skl_plane_formats[] = {
DRM_FORMAT_VYUY,
};
+static uint32_t skl_plane_formats_with_nv12[] = {
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+};
+
int
intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
{
@@ -1112,8 +1125,14 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe,
int plane)
intel_plane->disable_plane = skl_disable_plane;
state->scaler_id = -1;
- plane_formats = skl_plane_formats;
- num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+ if ((pipe == PIPE_A || pipe == PIPE_B) && (plane == 0)) {
+ plane_formats = skl_plane_formats_with_nv12;
+ num_plane_formats =
ARRAY_SIZE(skl_plane_formats_with_nv12);
+ } else {
+ plane_formats = skl_plane_formats;
+ num_plane_formats = ARRAY_SIZE(skl_plane_formats) - 1;
+ }
+
break;
default:
kfree(intel_plane);
--
1.7.9.5
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[Intel-gfx] [PATCH 16/16] drm/i915: Add 90/270 rotation for NV12 format.
Adding NV12 90/270 rotation support for primary and sprite planes.
v2:
-For 90/270 adjust pixel boundary only in Y-direction (bspec)
v3:
-Rebased (me)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 28 +++--
drivers/gpu/drm/i915/intel_sprite.c | 56 ++
2 files changed, 56 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e8fb15b..8602432 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3139,7 +3139,8 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
int scaler_id = -1;
- u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ unsigned long aux_dist = 0;
+ u32 aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
u32 tile_row_adjustment = 0;
u32 hphase = 0, vphase = 0;
@@ -3198,12 +3199,16 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
x_offset = stride * tile_height - y - src_h;
y_offset = x;
plane_size = (src_w - 1) << 16 | (src_h - 1);
- /*
-* TBD: For NV12 90/270 rotation, Y and UV subplanes should
-* be treated as separate surfaces and GTT remapping for
-* rotation should be done separately for each subplane.
-* Enable support once seperate remappings are available.
-*/
+
+ if (fb->pixel_format == DRM_FORMAT_NV12) {
+ u32 uv_tile_height = intel_tile_height(dev,
fb->pixel_format,
+ fb->modifier[0], 1);
+ aux_stride = DIV_ROUND_UP(fb->height / 2,
uv_tile_height);
+ aux_dist =
intel_plane_obj_offset(to_intel_plane(plane), obj, 1) -
+ surf_addr;
+ aux_x_offset = aux_stride * uv_tile_height - y / 2 -
fb->height / 2;
+ aux_y_offset = x / 2;
+ }
} else {
stride = fb->pitches[0] / stride_div;
x_offset = x;
@@ -11745,8 +11750,13 @@ int intel_plane_atomic_calc_changes(struct
drm_crtc_state *crtc_state,
/* Adjust (macro)pixel boundary */
if (fb && intel_format_is_yuv(fb->pixel_format)) {
- to_intel_plane_state(plane_state)->src.x1 &= ~0x1;
- to_intel_plane_state(plane_state)->src.x2 &= ~0x1;
+ if (intel_rotation_90_or_270(plane_state->rotation)) {
+ to_intel_plane_state(plane_state)->src.y1 &= ~0x1;
+ to_intel_plane_state(plane_state)->src.y2 &= ~0x1;
+ } else {
+ to_intel_plane_state(plane_state)->src.x1 &= ~0x1;
+ to_intel_plane_state(plane_state)->src.x2 &= ~0x1;
+ }
}
if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index b2346b0..7602be0 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -188,7 +188,8 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
int x_offset, y_offset;
struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config;
int scaler_id;
- u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ unsigned long aux_dist = 0;
+ u32 aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
u32 tile_row_adjustment = 0;
u32 hphase = 0, vphase = 0;
@@ -238,12 +239,14 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
x_offset = stride * tile_height - y - (src_h + 1);
y_offset = x;
- /*
-* TBD: For NV12 90/270 rotation, Y and UV subplanes should
-* be treated as separate surfaces and GTT remapping for
-* rotation should be done separately for each subplane.
-* Enable support once seperate remappings are available.
-*/
+ if (fb->pixel_format == DRM_FORMAT_NV12) {
+ u32 uv_tile_height = intel_tile_height(dev,
fb->pixel_format,
+ fb->modifier[0], 1);
+ aux_stride = DIV_ROUND_UP(fb->height / 2,
uv_tile_height);
+ aux_dist = intel_plane_obj_offset(intel_plane, obj, 1)
- surf_addr;
+
[Intel-gfx] [PATCH 13/16] drm/i915: Set initial phase & trip for NV12 scaler
This patch sets default initial phase and trip to scale NV12 content. In future, if needed these can be set via properties or other means depending on incoming stream request. Until then defaults are fine. Signed-off-by: Chandra Konduru <chandra.kond...@intel.com> --- drivers/gpu/drm/i915/intel_display.c |7 +++ drivers/gpu/drm/i915/intel_sprite.c |7 +++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 329651e..419660d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3098,6 +3098,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, int scaler_id = -1; u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0; u32 tile_row_adjustment = 0; + u32 hphase = 0, vphase = 0; plane_state = to_intel_plane_state(plane->state); @@ -3181,6 +3182,9 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, /* For tile-Yf, uv-subplane tile width is 2x of Y-subplane */ aux_stride = fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED ? stride / 2 : stride; + + hphase = 0x00010001; /* use trip for both Y and UV */ + vphase = 0x00012000; /* use trip for Y and phase 0.5 for UV */ } } plane_offset = y_offset << 16 | x_offset; @@ -3209,6 +3213,9 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); } + I915_WRITE(SKL_PS_HPHASE(pipe, scaler_id), hphase); + I915_WRITE(SKL_PS_VPHASE(pipe, scaler_id), vphase); + I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); POSTING_READ(PLANE_SURF(pipe, 0)); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index a1384a7..0ea9273 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -190,6 +190,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, int scaler_id; u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0; u32 tile_row_adjustment = 0; + u32 hphase = 0, vphase = 0; plane_ctl = PLANE_CTL_ENABLE | PLANE_CTL_PIPE_CSC_ENABLE; @@ -264,6 +265,9 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, /* For tile-Yf, uv-subplane tile width is 2x of Y-subplane */ aux_stride = fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED ? stride / 2 : stride; + + hphase = 0x00010001; /* use trip for both Y and UV */ + vphase = 0x00012000; /* use trip for Y and phase 0.5 for UV */ } } plane_offset = y_offset << 16 | x_offset; @@ -292,6 +296,9 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); } + I915_WRITE(SKL_PS_HPHASE(pipe, scaler_id), hphase); + I915_WRITE(SKL_PS_VPHASE(pipe, scaler_id), vphase); + I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); I915_WRITE(PLANE_SURF(pipe, plane), surf_addr); POSTING_READ(PLANE_SURF(pipe, plane)); -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/16] drm/i915: Add NV12 as supported format for primary plane
This patch adds NV12 to list of supported formats for
primary plane.
v2:
-Rebased (me)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index b1d9edf..e4a6a91 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -74,6 +74,19 @@ static const uint32_t skl_primary_formats[] = {
DRM_FORMAT_XBGR2101010,
};
+/* Primary plane formats for gen >= 9 with NV12 */
+static const uint32_t skl_primary_formats_with_nv12[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_NV12,
+};
+
/* Cursor formats */
static const uint32_t intel_cursor_formats[] = {
DRM_FORMAT_ARGB,
@@ -13606,8 +13619,13 @@ static struct drm_plane
*intel_primary_plane_create(struct drm_device *dev,
primary->plane = !pipe;
if (INTEL_INFO(dev)->gen >= 9) {
- intel_primary_formats = skl_primary_formats;
- num_formats = ARRAY_SIZE(skl_primary_formats);
+ if (pipe == PIPE_A || pipe == PIPE_B) {
+ intel_primary_formats = skl_primary_formats_with_nv12;
+ num_formats = ARRAY_SIZE(skl_primary_formats_with_nv12);
+ } else {
+ intel_primary_formats = skl_primary_formats;
+ num_formats = ARRAY_SIZE(skl_primary_formats);
+ }
} else if (INTEL_INFO(dev)->gen >= 4) {
intel_primary_formats = i965_primary_formats;
num_formats = ARRAY_SIZE(i965_primary_formats);
--
1.7.9.5
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[Intel-gfx] [PATCH 11/16] drm/i915: Add NV12 to primary plane programming.
This patch is adding NV12 support to skylake primary plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.
For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. Once GEM adds support
for seperate remappings for two subplanes, 90/270 support
to be added to plane programming.
v2:
-Use regular int instead of 16.16 in aux_offset calculations (me)
v3:
-Allow 90/270 for NV12 as its remapping is now supported (me)
v4:
-Rebased to current kernel version 4.2.0.rc4 (me)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 37 ++
1 file changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4df4d77..329651e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3026,6 +3026,8 @@ u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
case DRM_FORMAT_VYUY:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
+ case DRM_FORMAT_NV12:
+ return PLANE_CTL_FORMAT_NV12;
default:
MISSING_CASE(pixel_format);
}
@@ -3094,6 +3096,8 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
int scaler_id = -1;
+ u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ u32 tile_row_adjustment = 0;
plane_state = to_intel_plane_state(plane->state);
@@ -3150,11 +3154,34 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
x_offset = stride * tile_height - y - src_h;
y_offset = x;
plane_size = (src_w - 1) << 16 | (src_h - 1);
+ /*
+* TBD: For NV12 90/270 rotation, Y and UV subplanes should
+* be treated as separate surfaces and GTT remapping for
+* rotation should be done separately for each subplane.
+* Enable support once seperate remappings are available.
+*/
} else {
stride = fb->pitches[0] / stride_div;
x_offset = x;
y_offset = y;
plane_size = (src_h - 1) << 16 | (src_w - 1);
+ tile_height = PAGE_SIZE / stride_div;
+
+ if (fb->pixel_format == DRM_FORMAT_NV12) {
+ int height_in_mem = (fb->offsets[1]/fb->pitches[0]);
+ /*
+* If UV starts from middle of a page, then UV start
should
+* be programmed to beginning of that page. And offset
into that
+* page to be programmed into y-offset
+*/
+ tile_row_adjustment = height_in_mem % tile_height;
+ aux_dist = fb->pitches[0] * (height_in_mem -
tile_row_adjustment);
+ aux_x_offset = DIV_ROUND_UP(x, 2);
+ aux_y_offset = DIV_ROUND_UP(y, 2) + tile_row_adjustment;
+ /* For tile-Yf, uv-subplane tile width is 2x of
Y-subplane */
+ aux_stride = fb->modifier[0] ==
I915_FORMAT_MOD_Yf_TILED ?
+ stride / 2 : stride;
+ }
}
plane_offset = y_offset << 16 | x_offset;
@@ -3162,11 +3189,14 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
+ I915_WRITE(PLANE_AUX_DIST(pipe, 0), aux_dist | aux_stride);
+ I915_WRITE(PLANE_AUX_OFFSET(pipe, 0), aux_y_offset << 16 |
aux_x_offset);
if (scaler_id >= 0) {
uint32_t ps_ctrl = 0;
WARN_ON(!dst_w || !dst_h);
+
ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
crtc_state->scaler_state.scalers[scaler_id].mode;
I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
@@ -3175,6 +3205,7 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) |
dst_h);
I915_WRITE(PLANE_POS(pipe, 0), 0);
} else {
+ WARN_ON(fb->pixel_format == DRM_FORMAT_NV12);
I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
}
@@ -11626,6 +11657,12 @@ int intel_plane_atomic_calc_changes(struct
drm_crtc_state *crtc_state,
bool turn_off, turn_on, vi
[Intel-gfx] [PATCH 15/16] drm/i915: skl nv12 wa - NV12 to RGB switch
Switching format from NV12 to RGB can result in display underrun
and corruption. This workaround sets bits 15 & 19 to 1 in
CLKGATE_DIS_PSL register to address transition underrun.
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h |8
drivers/gpu/drm/i915/intel_display.c | 25 +
2 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 84c5db6..3192837 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5366,6 +5366,14 @@ enum skl_disp_power_wells {
#define CHICKEN_DCPR_1 0x46430
#define IDLE_WAKEMEM_MASK (1 << 13)
+#define CLKGATE_DIS_PSL_A0x46520
+#define CLKGATE_DIS_PSL_B0x46524
+#define CLKGATE_DIS_PSL_C0x46528
+#define DUPS1_GATING_DIS (1 << 15)
+#define DUPS2_GATING_DIS (1 << 19)
+#define DUPS3_GATING_DIS (1 << 23)
+#define CLKGATE_DIS_PSL(pipe) _PIPE(pipe, CLKGATE_DIS_PSL_A,
CLKGATE_DIS_PSL_B)
+
/* SKL new cursor registers */
#define _CUR_BUF_CFG_A 0x7017c
#define _CUR_BUF_CFG_B 0x7117c
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 35e9f89..e8fb15b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5058,6 +5058,25 @@ static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc)
return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
}
+/*
+ * Switching format from NV12 to RGB can result in display underrun
+ * and corruption. Workaround is to set bits 15 & 19 to 1 in
+ * CLKGATE_DIS_PSL register.
+ */
+static void skl_wa_clkgate(struct drm_i915_private *dev_priv,
+ int pipe, int enable)
+{
+ if (pipe == PIPE_A || pipe == PIPE_B) {
+ if (enable)
+ I915_WRITE(CLKGATE_DIS_PSL(pipe),
+ DUPS1_GATING_DIS | DUPS2_GATING_DIS);
+ else
+ I915_WRITE(CLKGATE_DIS_PSL(pipe),
+ I915_READ(CLKGATE_DIS_PSL(pipe) &
+ ~(DUPS1_GATING_DIS|DUPS2_GATING_DIS)));
+ }
+}
+
static void haswell_crtc_enable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
@@ -5148,6 +5167,9 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_wait_for_vblank(dev, hsw_workaround_pipe);
intel_wait_for_vblank(dev, hsw_workaround_pipe);
}
+
+ /* workaround for NV12 */
+ skl_wa_clkgate(dev_priv, pipe, 1);
}
static void ironlake_pfit_disable(struct intel_crtc *crtc)
@@ -5265,6 +5287,9 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
intel_crtc->active = false;
intel_update_watermarks(crtc);
+
+ /* workaround for NV12 */
+ skl_wa_clkgate(dev_priv, intel_crtc->pipe, 0);
}
static void i9xx_pfit_enable(struct intel_crtc *crtc)
--
1.7.9.5
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[Intel-gfx] [PATCH 10/16] drm/i915: Add NV12 support to intel_framebuffer_init
This patch adds NV12 as supported format to
intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (me)
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e4a6a91..4df4d77 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14343,6 +14343,34 @@ static int intel_framebuffer_init(struct drm_device
*dev,
return -EINVAL;
}
break;
+ case DRM_FORMAT_NV12:
+ if (INTEL_INFO(dev)->gen < 9) {
+ DRM_DEBUG("unsupported pixel format: %s\n",
+ drm_get_format_name(mode_cmd->pixel_format));
+ return -EINVAL;
+ }
+ if (!mode_cmd->offsets[1]) {
+ DRM_DEBUG("uv start offset not set\n");
+ return -EINVAL;
+ }
+ if (mode_cmd->pitches[0] != mode_cmd->pitches[1] ||
+ mode_cmd->handles[0] != mode_cmd->handles[1]) {
+ DRM_DEBUG("y and uv subplanes have different
parameters\n");
+ return -EINVAL;
+ }
+ if (mode_cmd->modifier[1] == I915_FORMAT_MOD_Yf_TILED &&
+ (mode_cmd->offsets[1] & 0xFFF)) {
+ DRM_DEBUG("tile-Yf uv offset 0x%x isn't starting on new
tile-row\n",
+ mode_cmd->offsets[1]);
+ return -EINVAL;
+ }
+ if (mode_cmd->modifier[1] == I915_FORMAT_MOD_Y_TILED &&
+ ((mode_cmd->offsets[1] / mode_cmd->pitches[1]) % 4)) {
+ DRM_DEBUG("tile-Y uv offset 0x%x isn't 4-line
aligned\n",
+ mode_cmd->offsets[1]);
+ return -EINVAL;
+ }
+ break;
default:
DRM_DEBUG("unsupported pixel format: %s\n",
drm_get_format_name(mode_cmd->pixel_format));
--
1.7.9.5
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[Intel-gfx] [PATCH 07/15] drm/i915: Upscale scaler max scale for NV12.
This patch updates max supported scaler limits for NV12.
v2:
-Rebased to current kernel version 4.2.0.rc4 (me)
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 13 +
drivers/gpu/drm/i915/intel_drv.h |3 ++-
drivers/gpu/drm/i915/intel_sprite.c |2 +-
3 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 411b211..b1d9edf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13421,7 +13421,9 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
}
int
-skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state
*crtc_state)
+skl_max_scale(struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *crtc_state,
+ uint32_t pixel_format)
{
int max_scale;
struct drm_device *dev;
@@ -13441,11 +13443,13 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct
intel_crtc_state *crtc_state
/*
* skl max scale is lower of:
-*close to 3 but not 3, -1 is for that purpose
+*close to 2 or 3 (NV12: 2, other formats: 3) but not equal,
+* -1 is for that purpose
*or
*cdclk/crtc_clock
*/
- max_scale = min((1 16) * 3 - 1, (1 8) * ((cdclk 8) /
crtc_clock));
+ max_scale = min((1 16) * (pixel_format == DRM_FORMAT_NV12 ? 2 : 3) -
1,
+ (1 8) * ((cdclk 8) / crtc_clock));
return max_scale;
}
@@ -13465,7 +13469,8 @@ intel_check_primary_plane(struct drm_plane *plane,
if (INTEL_INFO(plane-dev)-gen = 9
state-ckey.flags == I915_SET_COLORKEY_NONE) {
min_scale = 1;
- max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
+ max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state,
+ fb ? fb-pixel_format : 0);
can_position = true;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 18632a4..d50b8cb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1140,7 +1140,8 @@ void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc);
void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
-int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state
*crtc_state);
+int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
+ uint32_t pixel_format);
unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 8b73bb8..66d60ae 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -780,7 +780,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
if (state-ckey.flags == I915_SET_COLORKEY_NONE) {
can_scale = 1;
min_scale = 1;
- max_scale = skl_max_scale(intel_crtc, crtc_state);
+ max_scale = skl_max_scale(intel_crtc, crtc_state,
fb-pixel_format);
} else {
can_scale = 0;
min_scale = DRM_PLANE_HELPER_NO_SCALING;
--
1.7.9.5
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[Intel-gfx] [PATCH 12/15] drm/i915: Add NV12 to sprite plane programming.
This patch is adding NV12 support to skylake sprite plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.
For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. Once GEM adds support
for seperate remappings for two subplanes, 90/270 support
to be added to plane programming.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_sprite.c | 31 +--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 4e8c020..a1384a7 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -188,6 +188,8 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
int x_offset, y_offset;
struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)-config;
int scaler_id;
+ u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ u32 tile_row_adjustment = 0;
plane_ctl = PLANE_CTL_ENABLE |
PLANE_CTL_PIPE_CSC_ENABLE;
@@ -234,24 +236,48 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
plane_size = (src_w 16) | src_h;
x_offset = stride * tile_height - y - (src_h + 1);
y_offset = x;
+
+ /*
+* TBD: For NV12 90/270 rotation, Y and UV subplanes should
+* be treated as separate surfaces and GTT remapping for
+* rotation should be done separately for each subplane.
+* Enable support once seperate remappings are available.
+*/
} else {
stride = fb-pitches[0] / stride_div;
plane_size = (src_h 16) | src_w;
x_offset = x;
y_offset = y;
+ tile_height = PAGE_SIZE / stride_div;
+
+ if (fb-pixel_format == DRM_FORMAT_NV12) {
+ int height_in_mem = (fb-offsets[1]/fb-pitches[0]);
+ /*
+* If UV starts from middle of a page, then UV start
should
+* be programmed to beginning of that page. And offset
into that
+* page to be programmed into y-offset
+*/
+ tile_row_adjustment = height_in_mem % tile_height;
+ aux_dist = fb-pitches[0] * (height_in_mem -
tile_row_adjustment);
+ aux_x_offset = DIV_ROUND_UP(x, 2);
+ aux_y_offset = DIV_ROUND_UP(y, 2) + tile_row_adjustment;
+ /* For tile-Yf, uv-subplane tile width is 2x of
Y-subplane */
+ aux_stride = fb-modifier[0] ==
I915_FORMAT_MOD_Yf_TILED ?
+ stride / 2 : stride;
+ }
}
plane_offset = y_offset 16 | x_offset;
I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
+ I915_WRITE(PLANE_AUX_DIST(pipe, plane), aux_dist | aux_stride);
+ I915_WRITE(PLANE_AUX_OFFSET(pipe, plane), aux_y_offset16 |
aux_x_offset);
/* program plane scaler */
if (scaler_id = 0) {
uint32_t ps_ctrl = 0;
- DRM_DEBUG_KMS(plane = %d PS_PLANE_SEL(plane) = 0x%x\n, plane,
- PS_PLANE_SEL(plane));
ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) |
crtc_state-scaler_state.scalers[scaler_id].mode;
I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
@@ -262,6 +288,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
I915_WRITE(PLANE_POS(pipe, plane), 0);
} else {
+ WARN_ON(fb-pixel_format == DRM_FORMAT_NV12);
I915_WRITE(PLANE_POS(pipe, plane), (crtc_y 16) | crtc_x);
}
--
1.7.9.5
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[Intel-gfx] [PATCH 11/15] drm/i915: Add NV12 to primary plane programming.
This patch is adding NV12 support to skylake primary plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.
For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. Once GEM adds support
for seperate remappings for two subplanes, 90/270 support
to be added to plane programming.
v2:
-Use regular int instead of 16.16 in aux_offset calculations (me)
v3:
-Allow 90/270 for NV12 as its remapping is now supported (me)
v4:
-Rebased to current kernel version 4.2.0.rc4 (me)
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 37 ++
1 file changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4df4d77..329651e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3026,6 +3026,8 @@ u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
case DRM_FORMAT_VYUY:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
+ case DRM_FORMAT_NV12:
+ return PLANE_CTL_FORMAT_NV12;
default:
MISSING_CASE(pixel_format);
}
@@ -3094,6 +3096,8 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
int scaler_id = -1;
+ u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ u32 tile_row_adjustment = 0;
plane_state = to_intel_plane_state(plane-state);
@@ -3150,11 +3154,34 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
x_offset = stride * tile_height - y - src_h;
y_offset = x;
plane_size = (src_w - 1) 16 | (src_h - 1);
+ /*
+* TBD: For NV12 90/270 rotation, Y and UV subplanes should
+* be treated as separate surfaces and GTT remapping for
+* rotation should be done separately for each subplane.
+* Enable support once seperate remappings are available.
+*/
} else {
stride = fb-pitches[0] / stride_div;
x_offset = x;
y_offset = y;
plane_size = (src_h - 1) 16 | (src_w - 1);
+ tile_height = PAGE_SIZE / stride_div;
+
+ if (fb-pixel_format == DRM_FORMAT_NV12) {
+ int height_in_mem = (fb-offsets[1]/fb-pitches[0]);
+ /*
+* If UV starts from middle of a page, then UV start
should
+* be programmed to beginning of that page. And offset
into that
+* page to be programmed into y-offset
+*/
+ tile_row_adjustment = height_in_mem % tile_height;
+ aux_dist = fb-pitches[0] * (height_in_mem -
tile_row_adjustment);
+ aux_x_offset = DIV_ROUND_UP(x, 2);
+ aux_y_offset = DIV_ROUND_UP(y, 2) + tile_row_adjustment;
+ /* For tile-Yf, uv-subplane tile width is 2x of
Y-subplane */
+ aux_stride = fb-modifier[0] ==
I915_FORMAT_MOD_Yf_TILED ?
+ stride / 2 : stride;
+ }
}
plane_offset = y_offset 16 | x_offset;
@@ -3162,11 +3189,14 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
+ I915_WRITE(PLANE_AUX_DIST(pipe, 0), aux_dist | aux_stride);
+ I915_WRITE(PLANE_AUX_OFFSET(pipe, 0), aux_y_offset 16 |
aux_x_offset);
if (scaler_id = 0) {
uint32_t ps_ctrl = 0;
WARN_ON(!dst_w || !dst_h);
+
ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
crtc_state-scaler_state.scalers[scaler_id].mode;
I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
@@ -3175,6 +3205,7 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w 16) |
dst_h);
I915_WRITE(PLANE_POS(pipe, 0), 0);
} else {
+ WARN_ON(fb-pixel_format == DRM_FORMAT_NV12);
I915_WRITE(PLANE_POS(pipe, 0), (dst_y 16) | dst_x);
}
@@ -11626,6 +11657,12 @@ int intel_plane_atomic_calc_changes(struct
drm_crtc_state *crtc_state,
bool turn_off, turn_on, visible, was_visible;
struct drm_framebuffer *fb = plane_state-fb;
+ /* Adjust (macro)pixel boundary
[Intel-gfx] [PATCH 05/15] drm/i915: Stage scaler request for NV12 as src format
This patch stages a scaler request when input format
is NV12. The same scaler does both chroma-upsampling
and resolution scaling as needed.
v2:
-Added helper function for need_scaling (Ville)
v3:
-Rebased to current kernel version 4.2.0.rc4 (me)
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 30 --
1 file changed, 24 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3ee1c17..411b211 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4341,10 +4341,27 @@ static void cpt_verify_modeset(struct drm_device *dev,
int pipe)
}
}
+static int skl_need_scaling(int src_w, int dst_w, int src_h, int dst_h,
+ int rotation, uint32_t pixel_format)
+{
+ /* scaling is required when src dst sizes doesn't match or format is
NV12 */
+ if (src_w != dst_w || src_h != dst_h)
+ return 1;
+
+ if (intel_rotation_90_or_270(rotation)
+ (src_h != dst_w || src_w != dst_h))
+ return 1;
+
+ if (pixel_format == DRM_FORMAT_NV12)
+ return 1;
+
+ return 0;
+}
+
static int
skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
unsigned scaler_user, int *scaler_id, unsigned int rotation,
- int src_w, int src_h, int dst_w, int dst_h)
+ int src_w, int src_h, int dst_w, int dst_h, uint32_t
pixel_format)
{
struct intel_crtc_scaler_state *scaler_state =
crtc_state-scaler_state;
@@ -4352,9 +4369,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state,
bool force_detach,
to_intel_crtc(crtc_state-base.crtc);
int need_scaling;
- need_scaling = intel_rotation_90_or_270(rotation) ?
- (src_h != dst_w || src_w != dst_h):
- (src_w != dst_w || src_h != dst_h);
+ need_scaling = skl_need_scaling(src_w, dst_w, src_h, dst_h, rotation,
+ pixel_format);
/*
* if plane is being disabled or scaler is no more required or force
detach
@@ -4423,7 +4439,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state)
return skl_update_scaler(state, !state-base.active, SKL_CRTC_INDEX,
state-scaler_state.scaler_id, DRM_ROTATE_0,
state-pipe_src_w, state-pipe_src_h,
- adjusted_mode-hdisplay, adjusted_mode-vdisplay);
+ adjusted_mode-hdisplay, adjusted_mode-vdisplay, 0);
}
/**
@@ -4459,7 +4475,8 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
drm_rect_width(plane_state-src) 16,
drm_rect_height(plane_state-src) 16,
drm_rect_width(plane_state-dst),
- drm_rect_height(plane_state-dst));
+ drm_rect_height(plane_state-dst),
+ fb ? fb-pixel_format : 0);
if (ret || plane_state-scaler_id 0)
return ret;
@@ -4484,6 +4501,7 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+ case DRM_FORMAT_NV12:
break;
default:
DRM_DEBUG_KMS([PLANE:%d] FB:%d unsupported scaling format
0x%x\n,
--
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[Intel-gfx] [PATCH 00/15] drm/i915: Adding NV12 for skylake display
This patch series is adding initial NV12 support for Skylake display after rebasing on latest drm-intel-nightly. Earlier I had two patch series one for 0/180 and another for 90/270. Some of the patches were already merged. This is combined series to support 0/90/180/270 and removing the ones that are already merged. Feature is tested with igt/kms_nv12 testcases. Feature is unit tested for linear/X/Y formats in 0, 90, 180, 270 orientations with combinations of 1 or 2 planes enabled along with scaling. Also negatively tested for enabling NV12 on unsupported plane. The last patch in this series depends on Tvrtko's GEM remapping for NV12 format patch series. First two patches fixing couple things in dbuf logic to allocate correct min number of dbuf blocks and use correct source width and height in 90/270 rotation cases. Chandra Konduru (15): drm/i915: Allocate min dbuf blocks per bspec drm/i915: In DBUF/WM calcs for 90/270, swap w h drm/i915: Add register definitions for NV12 support drm/i915: Set scaler mode for NV12 drm/i915: Stage scaler request for NV12 as src format drm/i915: Update format_is_yuv() to include NV12 drm/i915: Upscale scaler max scale for NV12. drm/i915: Add NV12 as supported format for primary plane drm/i915: Add NV12 as supported format for sprite plane drm/i915: Add NV12 support to intel_framebuffer_init drm/i915: Add NV12 to primary plane programming. drm/i915: Add NV12 to sprite plane programming. drm/i915: Set initial phase trip for NV12 scaler drm/i915: skl nv12 workarounds drm/i915: Add 90/270 rotation for NV12 format. drivers/gpu/drm/i915/i915_reg.h | 47 + drivers/gpu/drm/i915/intel_atomic.c |5 +- drivers/gpu/drm/i915/intel_csr.c |2 +- drivers/gpu/drm/i915/intel_display.c | 178 +++--- drivers/gpu/drm/i915/intel_drv.h |5 +- drivers/gpu/drm/i915/intel_pm.c | 71 -- drivers/gpu/drm/i915/intel_sprite.c | 121 +++ 7 files changed, 387 insertions(+), 42 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/15] drm/i915: Add register definitions for NV12 support
This patch adds register definitions for skylake
display NV12 support.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1fa0554..c4d732f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5498,6 +5498,7 @@ enum skl_disp_power_wells {
#define PS_SCALER_MODE_MASK (3 28)
#define PS_SCALER_MODE_DYN (0 28)
#define PS_SCALER_MODE_HQ (1 28)
+#define PS_SCALER_MODE_NV12 (2 28)
#define PS_PLANE_SEL_MASK (7 25)
#define PS_PLANE_SEL(plane) ((plane + 1) 25)
#define PS_FILTER_MASK (3 23)
@@ -5601,6 +5602,32 @@ enum skl_disp_power_wells {
_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)
+
+/*
+ * Skylake NV12 Register
+ */
+#define PLANE_AUX_DIST_1_A 0x701c0
+#define PLANE_AUX_DIST_2_A 0x702c0
+#define PLANE_AUX_DIST_1_B 0x711c0
+#define PLANE_AUX_DIST_2_B 0x712c0
+#define _PLANE_AUX_DIST_1(pipe)\
+ _PIPE(pipe, PLANE_AUX_DIST_1_A, PLANE_AUX_DIST_1_B)
+#define _PLANE_AUX_DIST_2(pipe)\
+ _PIPE(pipe, PLANE_AUX_DIST_2_A, PLANE_AUX_DIST_2_B)
+#define PLANE_AUX_DIST(pipe, plane)\
+ _PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
+
+#define PLANE_AUX_OFFSET_1_A 0x701c4
+#define PLANE_AUX_OFFSET_2_A 0x702c4
+#define PLANE_AUX_OFFSET_1_B 0x711c4
+#define PLANE_AUX_OFFSET_2_B 0x712c4
+#define _PLANE_AUX_OFFSET_1(pipe) \
+ _PIPE(pipe, PLANE_AUX_OFFSET_1_A, PLANE_AUX_OFFSET_1_B)
+#define _PLANE_AUX_OFFSET_2(pipe) \
+ _PIPE(pipe, PLANE_AUX_OFFSET_2_A, PLANE_AUX_OFFSET_2_B)
+#define PLANE_AUX_OFFSET(pipe, plane) \
+ _PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
+
/* legacy palette */
#define _LGC_PALETTE_A 0x4a000
#define _LGC_PALETTE_B 0x4a800
--
1.7.9.5
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[Intel-gfx] [PATCH 04/15] drm/i915: Set scaler mode for NV12
This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_atomic.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm/i915/intel_atomic.c
index 9336e80..fd3972c 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -247,7 +247,10 @@ int intel_atomic_setup_scalers(struct drm_device *dev,
}
/* set scaler mode */
- if (num_scalers_need == 1 intel_crtc-pipe != PIPE_C) {
+ if (plane_state plane_state-base.fb
+ plane_state-base.fb-pixel_format == DRM_FORMAT_NV12) {
+ scaler_state-scalers[*scaler_id].mode =
PS_SCALER_MODE_NV12;
+ } else if (num_scalers_need == 1 intel_crtc-pipe != PIPE_C)
{
/*
* when only 1 scaler is in use on either pipe A or B,
* scaler 0 operates in high quality (HQ) mode.
--
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[Intel-gfx] [PATCH 09/15] drm/i915: Add NV12 as supported format for sprite plane
This patch adds NV12 to list of supported formats for
sprite plane.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_sprite.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 66d60ae..4e8c020 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1041,6 +1041,19 @@ static uint32_t skl_plane_formats[] = {
DRM_FORMAT_VYUY,
};
+static uint32_t skl_plane_formats_with_nv12[] = {
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+};
+
int
intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
{
@@ -1112,8 +1125,14 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe,
int plane)
intel_plane-disable_plane = skl_disable_plane;
state-scaler_id = -1;
- plane_formats = skl_plane_formats;
- num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+ if ((pipe == PIPE_A || pipe == PIPE_B) (plane == 0)) {
+ plane_formats = skl_plane_formats_with_nv12;
+ num_plane_formats =
ARRAY_SIZE(skl_plane_formats_with_nv12);
+ } else {
+ plane_formats = skl_plane_formats;
+ num_plane_formats = ARRAY_SIZE(skl_plane_formats) - 1;
+ }
+
break;
default:
kfree(intel_plane);
--
1.7.9.5
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[Intel-gfx] [PATCH 01/15] drm/i915: Allocate min dbuf blocks per bspec
Properly allocate min blocks per hw requirements.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 39 +--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fff0c22..da3046f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2959,6 +2959,41 @@ skl_get_total_relative_data_rate(struct intel_crtc
*intel_crtc,
return total_data_rate;
}
+static uint16_t
+skl_dbuf_min_alloc(const struct intel_plane_wm_parameters *p, int y_plane)
+{
+ uint16_t min_alloc;
+
+ /* For packed formats, no y-plane, return 0 */
+ if (y_plane !p-y_bytes_per_pixel)
+ return 0;
+
+
+ if (p-tiling == I915_FORMAT_MOD_Y_TILED ||
+ p-tiling == I915_FORMAT_MOD_Yf_TILED) {
+ uint32_t min_scanlines = 8;
+ uint8_t bytes_per_pixel =
+ y_plane ? p-y_bytes_per_pixel : p-bytes_per_pixel;
+
+ switch (bytes_per_pixel) {
+ case 1:
+ min_scanlines = 32;
+ break;
+ case 2:
+ min_scanlines = 16;
+ break;
+ case 8:
+ WARN(1, Unsupported pixel depth for rotation);
+ }
+ min_alloc = DIV_ROUND_UP((4 * p-horiz_pixels/(y_plane ? 1 : 2)
*
+ bytes_per_pixel), 512) * min_scanlines/4 + 3;
+ } else {
+ min_alloc = 8;
+ }
+
+ return min_alloc;
+}
+
static void
skl_allocate_pipe_ddb(struct drm_crtc *crtc,
const struct intel_wm_config *config,
@@ -2999,9 +3034,9 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
if (!p-enabled)
continue;
- minimum[plane] = 8;
+ minimum[plane] = skl_dbuf_min_alloc(p, 0);/*
uv-plane/packed */
alloc_size -= minimum[plane];
- y_minimum[plane] = p-y_bytes_per_pixel ? 8 : 0;
+ y_minimum[plane] = skl_dbuf_min_alloc(p, 1); /* y-plane */
alloc_size -= y_minimum[plane];
}
--
1.7.9.5
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[Intel-gfx] [PATCH 08/15] drm/i915: Add NV12 as supported format for primary plane
This patch adds NV12 to list of supported formats for
primary plane.
v2:
-Rebased (me)
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index b1d9edf..e4a6a91 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -74,6 +74,19 @@ static const uint32_t skl_primary_formats[] = {
DRM_FORMAT_XBGR2101010,
};
+/* Primary plane formats for gen = 9 with NV12 */
+static const uint32_t skl_primary_formats_with_nv12[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_NV12,
+};
+
/* Cursor formats */
static const uint32_t intel_cursor_formats[] = {
DRM_FORMAT_ARGB,
@@ -13606,8 +13619,13 @@ static struct drm_plane
*intel_primary_plane_create(struct drm_device *dev,
primary-plane = !pipe;
if (INTEL_INFO(dev)-gen = 9) {
- intel_primary_formats = skl_primary_formats;
- num_formats = ARRAY_SIZE(skl_primary_formats);
+ if (pipe == PIPE_A || pipe == PIPE_B) {
+ intel_primary_formats = skl_primary_formats_with_nv12;
+ num_formats = ARRAY_SIZE(skl_primary_formats_with_nv12);
+ } else {
+ intel_primary_formats = skl_primary_formats;
+ num_formats = ARRAY_SIZE(skl_primary_formats);
+ }
} else if (INTEL_INFO(dev)-gen = 4) {
intel_primary_formats = i965_primary_formats;
num_formats = ARRAY_SIZE(i965_primary_formats);
--
1.7.9.5
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[Intel-gfx] [PATCH 10/15] drm/i915: Add NV12 support to intel_framebuffer_init
This patch adds NV12 as supported format to
intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (me)
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e4a6a91..4df4d77 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14343,6 +14343,34 @@ static int intel_framebuffer_init(struct drm_device
*dev,
return -EINVAL;
}
break;
+ case DRM_FORMAT_NV12:
+ if (INTEL_INFO(dev)-gen 9) {
+ DRM_DEBUG(unsupported pixel format: %s\n,
+ drm_get_format_name(mode_cmd-pixel_format));
+ return -EINVAL;
+ }
+ if (!mode_cmd-offsets[1]) {
+ DRM_DEBUG(uv start offset not set\n);
+ return -EINVAL;
+ }
+ if (mode_cmd-pitches[0] != mode_cmd-pitches[1] ||
+ mode_cmd-handles[0] != mode_cmd-handles[1]) {
+ DRM_DEBUG(y and uv subplanes have different
parameters\n);
+ return -EINVAL;
+ }
+ if (mode_cmd-modifier[1] == I915_FORMAT_MOD_Yf_TILED
+ (mode_cmd-offsets[1] 0xFFF)) {
+ DRM_DEBUG(tile-Yf uv offset 0x%x isn't starting on new
tile-row\n,
+ mode_cmd-offsets[1]);
+ return -EINVAL;
+ }
+ if (mode_cmd-modifier[1] == I915_FORMAT_MOD_Y_TILED
+ ((mode_cmd-offsets[1] / mode_cmd-pitches[1]) % 4)) {
+ DRM_DEBUG(tile-Y uv offset 0x%x isn't 4-line
aligned\n,
+ mode_cmd-offsets[1]);
+ return -EINVAL;
+ }
+ break;
default:
DRM_DEBUG(unsupported pixel format: %s\n,
drm_get_format_name(mode_cmd-pixel_format));
--
1.7.9.5
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[Intel-gfx] [PATCH 06/15] drm/i915: Update format_is_yuv() to include NV12
This patch adds NV12 to format_is_yuv() function
and made it available for both primary and sprite
planes.
v2:
-Use intel_ prefix for format_is_yuv (Ville)
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_drv.h|1 +
drivers/gpu/drm/i915/intel_sprite.c |9 +
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f44941b..18632a4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1394,6 +1394,7 @@ int intel_sprite_set_colorkey(struct drm_device *dev,
void *data,
void intel_pipe_update_start(struct intel_crtc *crtc,
uint32_t *start_vbl_count);
void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
+bool intel_format_is_yuv(uint32_t format);
/* intel_tv.c */
void intel_tv_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index c13c529..8b73bb8 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -39,14 +39,15 @@
#include drm/i915_drm.h
#include i915_drv.h
-static bool
-format_is_yuv(uint32_t format)
+bool
+intel_format_is_yuv(uint32_t format)
{
switch (format) {
case DRM_FORMAT_YUYV:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_YVYU:
+ case DRM_FORMAT_NV12:
return true;
default:
return false;
@@ -293,7 +294,7 @@ chv_update_csc(struct intel_plane *intel_plane, uint32_t
format)
int plane = intel_plane-plane;
/* Seems RGB data bypasses the CSC always */
- if (!format_is_yuv(format))
+ if (!intel_format_is_yuv(format))
return;
/*
@@ -857,7 +858,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
src_y = src-y1 16;
src_h = drm_rect_height(src) 16;
- if (format_is_yuv(fb-pixel_format)) {
+ if (intel_format_is_yuv(fb-pixel_format)) {
src_x = ~1;
src_w = ~1;
--
1.7.9.5
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[Intel-gfx] [PATCH 13/15] drm/i915: Set initial phase trip for NV12 scaler
This patch sets default initial phase and trip to scale NV12 content. In future, if needed these can be set via properties or other means depending on incoming stream request. Until then defaults are fine. Signed-off-by: Chandra Konduru chandra.kond...@intel.com --- drivers/gpu/drm/i915/intel_display.c |7 +++ drivers/gpu/drm/i915/intel_sprite.c |7 +++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 329651e..419660d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3098,6 +3098,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, int scaler_id = -1; u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0; u32 tile_row_adjustment = 0; + u32 hphase = 0, vphase = 0; plane_state = to_intel_plane_state(plane-state); @@ -3181,6 +3182,9 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, /* For tile-Yf, uv-subplane tile width is 2x of Y-subplane */ aux_stride = fb-modifier[0] == I915_FORMAT_MOD_Yf_TILED ? stride / 2 : stride; + + hphase = 0x00010001; /* use trip for both Y and UV */ + vphase = 0x00012000; /* use trip for Y and phase 0.5 for UV */ } } plane_offset = y_offset 16 | x_offset; @@ -3209,6 +3213,9 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, I915_WRITE(PLANE_POS(pipe, 0), (dst_y 16) | dst_x); } + I915_WRITE(SKL_PS_HPHASE(pipe, scaler_id), hphase); + I915_WRITE(SKL_PS_VPHASE(pipe, scaler_id), vphase); + I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); POSTING_READ(PLANE_SURF(pipe, 0)); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index a1384a7..0ea9273 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -190,6 +190,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, int scaler_id; u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0; u32 tile_row_adjustment = 0; + u32 hphase = 0, vphase = 0; plane_ctl = PLANE_CTL_ENABLE | PLANE_CTL_PIPE_CSC_ENABLE; @@ -264,6 +265,9 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, /* For tile-Yf, uv-subplane tile width is 2x of Y-subplane */ aux_stride = fb-modifier[0] == I915_FORMAT_MOD_Yf_TILED ? stride / 2 : stride; + + hphase = 0x00010001; /* use trip for both Y and UV */ + vphase = 0x00012000; /* use trip for Y and phase 0.5 for UV */ } } plane_offset = y_offset 16 | x_offset; @@ -292,6 +296,9 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, I915_WRITE(PLANE_POS(pipe, plane), (crtc_y 16) | crtc_x); } + I915_WRITE(SKL_PS_HPHASE(pipe, scaler_id), hphase); + I915_WRITE(SKL_PS_VPHASE(pipe, scaler_id), vphase); + I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); I915_WRITE(PLANE_SURF(pipe, plane), surf_addr); POSTING_READ(PLANE_SURF(pipe, plane)); -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 14/15] drm/i915: skl nv12 workarounds
Adding driver workarounds for nv12.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 20
drivers/gpu/drm/i915/intel_csr.c |2 +-
drivers/gpu/drm/i915/intel_display.c | 31 +++
drivers/gpu/drm/i915/intel_drv.h |1 +
drivers/gpu/drm/i915/intel_sprite.c |7 +++
5 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c4d732f..3192837 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5354,6 +5354,26 @@ enum skl_disp_power_wells {
#define PLANE_NV12_BUF_CFG(pipe, plane)\
_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
+/*
+ * Skylake Chicken registers
+ */
+#define _CHICKEN_PIPESL_A 0x420B0
+#define _CHICKEN_PIPESL_B 0x420B4
+#define _CHICKEN_PIPESL_C 0x420B8
+#define DISABLE_STREAMER_FIX (1 22)
+#define CHICKEN_PIPESL(pipe) _PIPE(pipe, _CHICKEN_PIPESL_A, _CHICKEN_PIPESL_B)
+
+#define CHICKEN_DCPR_1 0x46430
+#define IDLE_WAKEMEM_MASK (1 13)
+
+#define CLKGATE_DIS_PSL_A0x46520
+#define CLKGATE_DIS_PSL_B0x46524
+#define CLKGATE_DIS_PSL_C0x46528
+#define DUPS1_GATING_DIS (1 15)
+#define DUPS2_GATING_DIS (1 19)
+#define DUPS3_GATING_DIS (1 23)
+#define CLKGATE_DIS_PSL(pipe) _PIPE(pipe, CLKGATE_DIS_PSL_A,
CLKGATE_DIS_PSL_B)
+
/* SKL new cursor registers */
#define _CUR_BUF_CFG_A 0x7017c
#define _CUR_BUF_CFG_B 0x7117c
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index ba1ae03..559a7f5 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -181,7 +181,7 @@ static const struct stepping_info skl_stepping_info[] = {
{'G', '0'}, {'H', '0'}, {'I', '0'}
};
-static char intel_get_stepping(struct drm_device *dev)
+char intel_get_stepping(struct drm_device *dev)
{
if (IS_SKYLAKE(dev) (dev-pdev-revision
ARRAY_SIZE(skl_stepping_info)))
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 419660d..2158b8f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3196,6 +3196,16 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
I915_WRITE(PLANE_AUX_DIST(pipe, 0), aux_dist | aux_stride);
I915_WRITE(PLANE_AUX_OFFSET(pipe, 0), aux_y_offset 16 |
aux_x_offset);
+ DRM_DEBUG_KMS(KCM: is_skl = %d is_bxt = %d\n,
+ IS_SKYLAKE(dev), IS_BROXTON(dev));
+
+ if (((IS_SKYLAKE(dev) intel_get_stepping(dev) == 'C') ||
+ (IS_BROXTON(dev) intel_get_stepping(dev) == 'A'))
+ fb-pixel_format == DRM_FORMAT_NV12) {
+ I915_WRITE(CHICKEN_PIPESL(pipe),
+ I915_READ(CHICKEN_PIPESL(pipe)) |
DISABLE_STREAMER_FIX);
+ }
+
if (scaler_id = 0) {
uint32_t ps_ctrl = 0;
@@ -5004,6 +5014,21 @@ static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc)
return HAS_IPS(crtc-base.dev) crtc-pipe == PIPE_A;
}
+
+static void skl_wa_clkgate(struct drm_i915_private *dev_priv,
+ int pipe, int enable)
+{
+ if (pipe == PIPE_A || pipe == PIPE_B) {
+ if (enable)
+ I915_WRITE(CLKGATE_DIS_PSL(pipe),
+ DUPS1_GATING_DIS | DUPS2_GATING_DIS);
+ else
+ I915_WRITE(CLKGATE_DIS_PSL(pipe),
+ I915_READ(CLKGATE_DIS_PSL(pipe)
+ ~(DUPS1_GATING_DIS|DUPS2_GATING_DIS)));
+ }
+}
+
static void haswell_crtc_enable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc-dev;
@@ -5094,6 +5119,9 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_wait_for_vblank(dev, hsw_workaround_pipe);
intel_wait_for_vblank(dev, hsw_workaround_pipe);
}
+
+ /* workaround for NV12 */
+ skl_wa_clkgate(dev_priv, pipe, 1);
}
static void ironlake_pfit_disable(struct intel_crtc *crtc)
@@ -5211,6 +5239,9 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
intel_crtc-active = false;
intel_update_watermarks(crtc);
+
+ /* workaround for NV12 */
+ skl_wa_clkgate(dev_priv, intel_crtc-pipe, 0);
}
static void i9xx_pfit_enable(struct intel_crtc *crtc)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d50b8cb..63750d5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1158,6 +1158,7 @@ void intel_csr_load_status_set(struct drm_i915_private
*dev_priv,
enum csr_state state);
void intel_csr_load_program
[Intel-gfx] [PATCH 15/15] drm/i915: Add 90/270 rotation for NV12 format.
Adding NV12 90/270 rotation support for primary and sprite planes.
v2:
-For 90/270 adjust pixel boundary only in Y-direction (bspec)
v3:
-Rebased (me)
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 28 +++--
drivers/gpu/drm/i915/intel_sprite.c | 56 ++
2 files changed, 56 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 2158b8f..19d0f8b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3096,7 +3096,8 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
int scaler_id = -1;
- u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ unsigned long aux_dist = 0;
+ u32 aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
u32 tile_row_adjustment = 0;
u32 hphase = 0, vphase = 0;
@@ -3155,12 +3156,16 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
x_offset = stride * tile_height - y - src_h;
y_offset = x;
plane_size = (src_w - 1) 16 | (src_h - 1);
- /*
-* TBD: For NV12 90/270 rotation, Y and UV subplanes should
-* be treated as separate surfaces and GTT remapping for
-* rotation should be done separately for each subplane.
-* Enable support once seperate remappings are available.
-*/
+
+ if (fb-pixel_format == DRM_FORMAT_NV12) {
+ u32 uv_tile_height = intel_tile_height(dev,
fb-pixel_format,
+ fb-modifier[0], 1);
+ aux_stride = DIV_ROUND_UP(fb-height / 2,
uv_tile_height);
+ aux_dist =
intel_plane_obj_offset(to_intel_plane(plane), obj, 1) -
+ surf_addr;
+ aux_x_offset = aux_stride * uv_tile_height - y / 2 -
fb-height / 2;
+ aux_y_offset = x / 2;
+ }
} else {
stride = fb-pitches[0] / stride_div;
x_offset = x;
@@ -11697,8 +11702,13 @@ int intel_plane_atomic_calc_changes(struct
drm_crtc_state *crtc_state,
/* Adjust (macro)pixel boundary */
if (fb intel_format_is_yuv(fb-pixel_format)) {
- to_intel_plane_state(plane_state)-src.x1 = ~0x1;
- to_intel_plane_state(plane_state)-src.x2 = ~0x1;
+ if (intel_rotation_90_or_270(plane_state-rotation)) {
+ to_intel_plane_state(plane_state)-src.y1 = ~0x1;
+ to_intel_plane_state(plane_state)-src.y2 = ~0x1;
+ } else {
+ to_intel_plane_state(plane_state)-src.x1 = ~0x1;
+ to_intel_plane_state(plane_state)-src.x2 = ~0x1;
+ }
}
if (crtc_state INTEL_INFO(dev)-gen = 9
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 9d1c5b9..3522cb0 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -188,7 +188,8 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
int x_offset, y_offset;
struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)-config;
int scaler_id;
- u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ unsigned long aux_dist = 0;
+ u32 aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
u32 tile_row_adjustment = 0;
u32 hphase = 0, vphase = 0;
@@ -238,12 +239,14 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
x_offset = stride * tile_height - y - (src_h + 1);
y_offset = x;
- /*
-* TBD: For NV12 90/270 rotation, Y and UV subplanes should
-* be treated as separate surfaces and GTT remapping for
-* rotation should be done separately for each subplane.
-* Enable support once seperate remappings are available.
-*/
+ if (fb-pixel_format == DRM_FORMAT_NV12) {
+ u32 uv_tile_height = intel_tile_height(dev,
fb-pixel_format,
+ fb-modifier[0], 1);
+ aux_stride = DIV_ROUND_UP(fb-height / 2,
uv_tile_height);
+ aux_dist = intel_plane_obj_offset(intel_plane, obj, 1)
- surf_addr;
+ aux_x_offset = aux_stride * uv_tile_height - y / 2 -
fb-height / 2;
+ aux_y_offset = x / 2;
+ }
} else {
stride = fb
[Intel-gfx] [PATCH i-g-t 2/2] Adding kms_nv12 to test display NV12 feature
From: chandra konduru chandra.kond...@intel.com
This patch adds kms_nv12 test case. It covers testing NV12
in linear/tile-X/tile-Y tiling formats in 0/90/180/270
orientations. For each tiling format, it tests several
combinations of planes and its scaling.
v2:
-Added 90/270 tests (me)
-took out crc test as it isn't adding much value due to chroma upsampling (me)
v3:
-Make --list-subtests option work (Tvrtko)
-Make nv12 unsupported test run properly either as a sub test
or along with all other tests (me)
-Added nv12 fb with invalid params (Daniel)
Signed-off-by: chandra konduru chandra.kond...@intel.com
---
tests/.gitignore | 1 +
tests/Makefile.sources | 1 +
tests/kms_nv12.c | 759 +
3 files changed, 761 insertions(+)
create mode 100644 tests/kms_nv12.c
diff --git a/tests/.gitignore b/tests/.gitignore
index d6d05ff..2de4712 100644
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -155,6 +155,7 @@ kms_setmode
kms_sink_crc_basic
kms_universal_plane
kms_vblank
+kms_nv12
pm_backlight
pm_lpsp
pm_rc6_residency
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index ef69299..a7804fa 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -85,6 +85,7 @@ TESTS_progs_M = \
kms_crtc_background_color \
kms_plane_scaling \
kms_panel_fitting \
+ kms_nv12 \
pm_backlight \
pm_lpsp \
pm_rpm \
diff --git a/tests/kms_nv12.c b/tests/kms_nv12.c
new file mode 100644
index 000..9f90a85
--- /dev/null
+++ b/tests/kms_nv12.c
@@ -0,0 +1,759 @@
+/*
+ * Copyright © 2013,2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include math.h
+#include fcntl.h
+#include sys/stat.h
+
+#include drmtest.h
+#include igt_debugfs.h
+#include igt_kms.h
+#include igt_core.h
+#include intel_chipset.h
+#include ioctl_wrappers.h
+
+IGT_TEST_DESCRIPTION(Test display NV12 support);
+
+uint32_t devid;
+typedef struct {
+ int drm_fd;
+ igt_display_t display;
+ int num_scalers;
+ int num_planes;
+
+ struct igt_fb fb1;
+ struct igt_fb fb1_nv12;
+ struct igt_fb fb2;
+ struct igt_fb fb2_nv12;
+ struct igt_fb fb3;
+ struct igt_fb fb3_nv12;
+ int fb_id1;
+ int fb_id1_nv12;
+ int fb_id2;
+ int fb_id2_nv12;
+ int fb_id3;
+ int fb_id3_nv12;
+
+ igt_plane_t *plane1;
+ igt_plane_t *plane2;
+ igt_plane_t *plane3;
+
+ uint64_t tiled;
+ int rotation;
+} data_t;
+
+typedef struct {
+ int width;
+ int height;
+} res_t;
+
+#define IMG_FILE 1080p-left.png
+
+static void
+paint_pattern(data_t *d, struct igt_fb *fb, uint16_t w, uint16_t h)
+{
+ cairo_t *cr;
+
+ cr = igt_get_cairo_ctx(d-drm_fd, fb);
+ igt_paint_test_pattern(cr, w, h);
+ cairo_destroy(cr);
+}
+
+static void
+paint_image(data_t *d, struct igt_fb *fb, uint16_t w, uint16_t h)
+{
+ cairo_t *cr;
+
+ cr = igt_get_cairo_ctx(d-drm_fd, fb);
+ igt_paint_image(cr, IMG_FILE, 0, 0, w, h);
+ cairo_destroy(cr);
+}
+
+static void prepare_crtc(data_t *data, igt_output_t *output, enum pipe pipe,
+ igt_plane_t *plane, drmModeModeInfo *mode, enum
igt_commit_style s)
+{
+ igt_display_t *display = data-display;
+
+ igt_output_set_pipe(output, pipe);
+
+ /* before allocating, free if any older fb */
+ if (data-fb_id1) {
+ igt_remove_fb(data-drm_fd, data-fb1);
+ data-fb_id1 = 0;
+ }
+
+ /* allocate fb for plane 1 */
+ data-fb_id1 = igt_create_fb(data-drm_fd,
+ mode-hdisplay, mode-vdisplay,
+ DRM_FORMAT_XRGB,
+ data-tiled, /* tiled */
+ data-fb1);
+ igt_assert(data-fb_id1);
+
+ paint_pattern(data, data-fb1, mode
[Intel-gfx] [PATCH i-g-t 0/2] patches for testing nv12
From: chandra konduru chandra.kond...@intel.com This patch series made some necessary igt framework changes to support nv12 format. And adds kms_nv12 to test nv12 format. It is having several initial test combinations but any additional tests can be added as needed. chandra konduru (2): Prep work for adding NV12 testcase Adding kms_nv12 to test display NV12 feature lib/igt_fb.c| 316 +++- lib/igt_fb.h| 9 +- lib/intel_batchbuffer.c | 16 +- lib/intel_batchbuffer.h | 3 +- lib/intel_reg.h | 1 + lib/ioctl_wrappers.c| 10 +- lib/ioctl_wrappers.h| 2 +- tests/.gitignore| 1 + tests/Makefile.sources | 1 + tests/kms_nv12.c| 759 tests/kms_render.c | 4 +- 11 files changed, 1095 insertions(+), 27 deletions(-) create mode 100644 tests/kms_nv12.c -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 1/2] Prep work for adding NV12 testcase
From: chandra konduru chandra.kond...@intel.com
This patch adds necessary prep work for nv12 testcase:
- updated fb allocation functions to handle NV12 format
- igt helper function to return png image size
- igt helper function to calculate start of uv in a given NV12 buffer
- igt helper function to map buffer for host access
- populates fb-...[4] parameters for NV12
- igt helper function to convert RGB data to NV12
- updated drm_format to bpp to handle NV12
- updated fast copy blit function to deal NV12 subplanes
- made an update to kms_render testcase due to above changes
Signed-off-by: chandra konduru chandra.kond...@intel.com
---
lib/igt_fb.c| 316 +---
lib/igt_fb.h| 9 +-
lib/intel_batchbuffer.c | 16 ++-
lib/intel_batchbuffer.h | 3 +-
lib/intel_reg.h | 1 +
lib/ioctl_wrappers.c| 10 +-
lib/ioctl_wrappers.h| 2 +-
tests/kms_render.c | 4 +-
8 files changed, 334 insertions(+), 27 deletions(-)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 134dbd2..788bb61 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -74,7 +74,7 @@ static struct format_desc_struct {
/* helpers to create nice-looking framebuffers */
-static int create_bo_for_fb(int fd, int width, int height, int bpp,
+static int create_bo_for_fb(int fd, int width, int height, int bpp, int bpp2,
uint64_t tiling, unsigned bo_size,
uint32_t *gem_handle_ret,
unsigned *size_ret,
@@ -99,13 +99,17 @@ static int create_bo_for_fb(int fd, int width, int height,
int bpp,
for (stride = 512; stride v; stride *= 2)
;
- v = stride * height;
+ /* planar formats height is 1.5x */
+ v = stride * (bpp2 ? (height * 3) / 2 : height);
+
for (size = 1024*1024; size v; size *= 2)
;
} else {
/* Scan-out has a 64 byte alignment restriction */
stride = (width * (bpp / 8) + 63) ~63;
- size = stride * height;
+
+ /* planar formats height is 1.5x */
+ size = stride * (bpp2 ? (height * 3) / 2 : height);
}
if (bo_size == 0)
@@ -393,6 +397,75 @@ void igt_paint_image(cairo_t *cr, const char *filename,
}
/**
+ * igt_get_image_size:
+ * @filename: filename of the png image
+ * @width: width of the image
+ * @height: height of the image
+ *
+ * This function returns @width and @height of the png image in @filename,
+ * which is loaded from the package data directory.
+ */
+void
+igt_get_image_size(const char *filename, int *width, int *height)
+{
+ cairo_surface_t *image;
+ FILE* f;
+
+ f = igt_fopen_data(filename);
+
+ image = cairo_image_surface_create_from_png_stream(stdio_read_func, f);
+ igt_assert(cairo_surface_status(image) == CAIRO_STATUS_SUCCESS);
+
+ *width = cairo_image_surface_get_width(image);
+ *height = cairo_image_surface_get_height(image);
+
+ cairo_surface_destroy(image);
+
+ fclose(f);
+}
+
+
+/**
+ * igt_fb_calc_uv:
+ * @fb: pointer to an #igt_fb structure
+ *
+ * This function calculates UV offset in bytes and UV starting line number
+ * for requested NV12 @fb.
+ */
+void
+igt_fb_calc_uv(struct igt_fb *fb)
+{
+ if (fb-drm_format != DRM_FORMAT_NV12)
+ return;
+
+ switch (fb-tiling) {
+ case LOCAL_DRM_FORMAT_MOD_NONE:
+ fb-uv_y_start = fb-height;
+ break;
+ case LOCAL_I915_FORMAT_MOD_X_TILED:
+ fb-uv_y_start = fb-height;
+ break;
+ case LOCAL_I915_FORMAT_MOD_Y_TILED:
+ fb-uv_y_start = fb-height;
+ break;
+ case LOCAL_I915_FORMAT_MOD_Yf_TILED:
+ /* tile-Yf requires uv to start on a new tile row */
+ if (fb-height % 64)
+ fb-uv_y_start = (fb-height + 63) ~63;
+ else
+ fb-uv_y_start = fb-height;
+ break;
+ default:
+ igt_assert(0);
+ }
+
+ fb-uv_offset = fb-uv_y_start * fb-stride;
+
+ /* assert that fb has enough lines to hold y and uv sub-planes */
+ igt_assert(fb-size / fb-stride = fb-uv_y_start + fb-height / 2);
+}
+
+/**
* igt_create_fb_with_bo_size:
* @fd: open i915 drm file descriptor
* @width: width of the framebuffer in pixel
@@ -418,24 +491,32 @@ igt_create_fb_with_bo_size(int fd, int width, int height,
struct igt_fb *fb, unsigned bo_size)
{
uint32_t fb_id;
- int bpp;
+ int bpp, bpp2;
memset(fb, 0, sizeof(*fb));
- bpp = igt_drm_format_to_bpp(format);
+ bpp = igt_drm_format_to_bpp(format, 0);
+ bpp2 = igt_drm_format_to_bpp(format, 1);
- igt_debug(%s(width=%d, height=%d, format=0x%x [bpp=%d],
tiling=0x%PRIx64
[Intel-gfx] [PATCH v4] drm/i915: Add support for SKL background color
This patch adds support for Skylake display pipe background color.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
Documentation/DocBook/drm.tmpl | 10 -
drivers/gpu/drm/i915/i915_reg.h | 10 +
drivers/gpu/drm/i915/intel_display.c | 73 ++
drivers/gpu/drm/i915/intel_drv.h |2 +
include/drm/drm_crtc.h |3 ++
5 files changed, 97 insertions(+), 1 deletion(-)
diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index 7d03a74..1f6f4f0 100644
--- a/Documentation/DocBook/drm.tmpl
+++ b/Documentation/DocBook/drm.tmpl
@@ -2663,7 +2663,7 @@ void intel_crt_init(struct drm_device *dev)
td valign=top TBD/td
/tr
tr
- td rowspan=21 valign=top i915/td
+ td rowspan=22 valign=top i915/td
td rowspan=2 valign=top Generic/td
td valign=top Broadcast RGB/td
td valign=top ENUM/td
@@ -2687,6 +2687,14 @@ void intel_crt_init(struct drm_device *dev)
td valign=top TBD/td
/tr
tr
+ td rowspan=1 valign=top CRTC/td
+ td valign=top “background_color”/td
+ td valign=top Range/td
+ td valign=top Min=0, Max=0xFF/td
+ td valign=top CRTC/td
+ td valign=top Background color in 16bpc BGR (B-MSB, R-LSB)/td
+ /tr
+ tr
td rowspan=17 valign=top SDVO-TV/td
td valign=top “mode”/td
td valign=top ENUM/td
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 84b37d7..795b53f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6579,6 +6579,16 @@ enum kdiv {
#define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME,
_PIPE_B_CSC_POSTOFF_ME)
#define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO,
_PIPE_B_CSC_POSTOFF_LO)
+/* Skylake pipe bottom color */
+#define _PIPE_BOTTOM_COLOR_A0x70034
+#define _PIPE_BOTTOM_COLOR_B0x71034
+#define _PIPE_BOTTOM_COLOR_C0x72034
+#define PIPE_BOTTOM_GAMMA_ENABLE (1 31)
+#define PIPE_BOTTOM_CSC_ENABLE (1 30)
+#define PIPE_BOTTOM_COLOR_MASK 0x3FFF
+#define PIPE_BOTTOM_COLOR(pipe) _PIPE3(pipe, _PIPE_BOTTOM_COLOR_A, \
+ _PIPE_BOTTOM_COLOR_B, _PIPE_BOTTOM_COLOR_C)
+
/* VLV MIPI registers */
#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d162dca..d4b7c0c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6951,6 +6951,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_crtc-pipe;
uint16_t coeff = 0x7800; /* 1.0 */
+ uint32_t color;
/*
* TODO: Check what kind of values actually come out of the pipe
@@ -6999,6 +7000,14 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
I915_WRITE(PIPE_CSC_MODE(pipe), mode);
}
+
+ /* set csc for bottom color */
+ if (INTEL_INFO(dev)-gen = 9) {
+ color = I915_READ(PIPE_BOTTOM_COLOR(pipe));
+ color |= PIPE_BOTTOM_CSC_ENABLE;
+ I915_WRITE(PIPE_BOTTOM_COLOR(pipe), color);
+ intel_crtc-background_color |= PIPE_BOTTOM_CSC_ENABLE;
+ }
}
static void haswell_set_pipeconf(struct drm_crtc *crtc)
@@ -8568,6 +8577,9 @@ static void intel_crtc_gamma_set(struct drm_crtc *crtc,
u16 *red, u16 *green,
{
int end = (start + size 256) ? 256 : start + size, i;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct drm_device *dev = crtc-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ uint32_t color;
for (i = start; i end; i++) {
intel_crtc-lut_r[i] = red[i] 8;
@@ -8576,6 +8588,14 @@ static void intel_crtc_gamma_set(struct drm_crtc *crtc,
u16 *red, u16 *green,
}
intel_crtc_load_lut(crtc);
+
+ if (INTEL_INFO(dev)-gen = 9) {
+ /* set gamma for bottom color */
+ color = I915_READ(PIPE_BOTTOM_COLOR(intel_crtc-pipe));
+ color |= PIPE_BOTTOM_GAMMA_ENABLE;
+ I915_WRITE(PIPE_BOTTOM_COLOR(intel_crtc-pipe), color);
+ intel_crtc-background_color |= PIPE_BOTTOM_GAMMA_ENABLE;
+ }
}
/* VESA 640x480x72Hz mode to set on the pipe */
@@ -9350,6 +9370,12 @@ static void intel_crtc_destroy(struct drm_crtc *crtc)
kfree(work);
}
+ if (dev-mode_config.background_color_property) {
+ drm_property_destroy(crtc-dev,
+ dev-mode_config.background_color_property);
+ dev-mode_config.background_color_property = NULL;
+ }
+
drm_crtc_cleanup(crtc);
kfree(intel_crtc);
@@ -10131,6 +10157,33 @@ out_hang:
return ret;
}
+static int
[Intel-gfx] [PATCH 0/2] Fix min dbuf, 90/270 wm calcs
This patch series allocates minimum dbuf blocks required for tile-y, tile-yf buffers correctly as per bspec. Also in WM calculations, for 90/270, swaps source width and height. Chandra Konduru (2): drm/i915: Allocate min dbuf blocks per bspec drm/i915: In DBUF/WM calcs for 90/270, swap w h drivers/gpu/drm/i915/intel_pm.c | 71 +++ 1 file changed, 65 insertions(+), 6 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Allocate min dbuf blocks per bspec
Properly allocate min blocks per hw requirements.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 39 +--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 32ff034..ea3e435 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2679,6 +2679,41 @@ skl_get_total_relative_data_rate(struct intel_crtc
*intel_crtc,
return total_data_rate;
}
+static uint16_t
+skl_dbuf_min_alloc(const struct intel_plane_wm_parameters *p, int y_plane)
+{
+ uint16_t min_alloc;
+
+ /* For packed formats, no y-plane, return 0 */
+ if (y_plane !p-y_bytes_per_pixel)
+ return 0;
+
+
+ if (p-tiling == I915_FORMAT_MOD_Y_TILED ||
+ p-tiling == I915_FORMAT_MOD_Yf_TILED) {
+ uint32_t min_scanlines = 8;
+ uint8_t bytes_per_pixel =
+ y_plane ? p-y_bytes_per_pixel : p-bytes_per_pixel;
+
+ switch (bytes_per_pixel) {
+ case 1:
+ min_scanlines = 32;
+ break;
+ case 2:
+ min_scanlines = 16;
+ break;
+ case 8:
+ WARN(1, Unsupported pixel depth for rotation);
+ }
+ min_alloc = DIV_ROUND_UP((4 * p-horiz_pixels/(y_plane ? 1 : 2)
*
+ bytes_per_pixel), 512) * min_scanlines/4 + 3;
+ } else {
+ min_alloc = 8;
+ }
+
+ return min_alloc;
+}
+
static void
skl_allocate_pipe_ddb(struct drm_crtc *crtc,
const struct intel_wm_config *config,
@@ -2719,9 +2754,9 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
if (!p-enabled)
continue;
- minimum[plane] = 8;
+ minimum[plane] = skl_dbuf_min_alloc(p, 0);/*
uv-plane/packed */
alloc_size -= minimum[plane];
- y_minimum[plane] = p-y_bytes_per_pixel ? 8 : 0;
+ y_minimum[plane] = skl_dbuf_min_alloc(p, 1); /* y-plane */
alloc_size -= y_minimum[plane];
}
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: In DBUF/WM calcs for 90/270, swap w h
This patch swaps src width and height for dbuf/wm calculations
when rotation is 90/270 as per hw requirements.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 32
1 file changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ea3e435..767313b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2913,6 +2913,8 @@ static void skl_compute_wm_pipe_parameters(struct
drm_crtc *crtc,
enum pipe pipe = intel_crtc-pipe;
struct drm_plane *plane;
struct drm_framebuffer *fb;
+ struct intel_plane_state *plane_state;
+ int src_w, src_h;
int i = 1; /* Index for sprite planes start */
p-active = intel_crtc-active;
@@ -2921,6 +2923,7 @@ static void skl_compute_wm_pipe_parameters(struct
drm_crtc *crtc,
p-pixel_rate = skl_pipe_pixel_rate(intel_crtc-config);
fb = crtc-primary-state-fb;
+ plane_state = to_intel_plane_state(crtc-primary-state);
/* For planar: Bpp is for uv plane, y_Bpp is for y plane */
if (fb) {
p-plane[0].enabled = true;
@@ -2935,8 +2938,22 @@ static void skl_compute_wm_pipe_parameters(struct
drm_crtc *crtc,
p-plane[0].y_bytes_per_pixel = 0;
p-plane[0].tiling = DRM_FORMAT_MOD_NONE;
}
- p-plane[0].horiz_pixels = intel_crtc-config-pipe_src_w;
- p-plane[0].vert_pixels = intel_crtc-config-pipe_src_h;
+
+ if (drm_rect_width(plane_state-src)) {
+ src_w = drm_rect_width(plane_state-src) 16;
+ src_h = drm_rect_height(plane_state-src) 16;
+ } else {
+ src_w = intel_crtc-config-pipe_src_w;
+ src_h = intel_crtc-config-pipe_src_h;
+ }
+
+ if (intel_rotation_90_or_270(crtc-primary-state-rotation)) {
+ p-plane[0].horiz_pixels = src_h;
+ p-plane[0].vert_pixels = src_w;
+ } else {
+ p-plane[0].horiz_pixels = src_w;
+ p-plane[0].vert_pixels = src_h;
+ }
p-plane[0].rotation = crtc-primary-state-rotation;
fb = crtc-cursor-state-fb;
@@ -3468,8 +3485,15 @@ skl_update_sprite_wm(struct drm_plane *plane, struct
drm_crtc *crtc,
intel_plane-wm.enabled = enabled;
intel_plane-wm.scaled = scaled;
- intel_plane-wm.horiz_pixels = sprite_width;
- intel_plane-wm.vert_pixels = sprite_height;
+
+ if (intel_rotation_90_or_270(plane-state-rotation)) {
+ intel_plane-wm.horiz_pixels = sprite_height;
+ intel_plane-wm.vert_pixels = sprite_width;
+ } else {
+ intel_plane-wm.horiz_pixels = sprite_width;
+ intel_plane-wm.vert_pixels = sprite_height;
+ }
+
intel_plane-wm.tiling = DRM_FORMAT_MOD_NONE;
/* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
--
1.7.9.5
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[Intel-gfx] [PATCH 0/2] Fix min dbuf, 90/270 wm calcs
Resending with correct patches. This patch series allocates minimum dbuf blocks required for tile-y, tile-yf buffers correctly as per bspec. Also in WM calculations, for 90/270, swaps source width and height. Chandra Konduru (2): drm/i915: Allocate min dbuf blocks per bspec drm/i915: In DBUF/WM calcs for 90/270, swap w h drivers/gpu/drm/i915/intel_pm.c | 71 +++ 1 file changed, 65 insertions(+), 6 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Allocate min dbuf blocks per bspec
Properly allocate min blocks per hw requirements.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 39 +--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 32ff034..ea3e435 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2679,6 +2679,41 @@ skl_get_total_relative_data_rate(struct intel_crtc
*intel_crtc,
return total_data_rate;
}
+static uint16_t
+skl_dbuf_min_alloc(const struct intel_plane_wm_parameters *p, int y_plane)
+{
+ uint16_t min_alloc;
+
+ /* For packed formats, no y-plane, return 0 */
+ if (y_plane !p-y_bytes_per_pixel)
+ return 0;
+
+
+ if (p-tiling == I915_FORMAT_MOD_Y_TILED ||
+ p-tiling == I915_FORMAT_MOD_Yf_TILED) {
+ uint32_t min_scanlines = 8;
+ uint8_t bytes_per_pixel =
+ y_plane ? p-y_bytes_per_pixel : p-bytes_per_pixel;
+
+ switch (bytes_per_pixel) {
+ case 1:
+ min_scanlines = 32;
+ break;
+ case 2:
+ min_scanlines = 16;
+ break;
+ case 8:
+ WARN(1, Unsupported pixel depth for rotation);
+ }
+ min_alloc = DIV_ROUND_UP((4 * p-horiz_pixels/(y_plane ? 1 : 2)
*
+ bytes_per_pixel), 512) * min_scanlines/4 + 3;
+ } else {
+ min_alloc = 8;
+ }
+
+ return min_alloc;
+}
+
static void
skl_allocate_pipe_ddb(struct drm_crtc *crtc,
const struct intel_wm_config *config,
@@ -2719,9 +2754,9 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
if (!p-enabled)
continue;
- minimum[plane] = 8;
+ minimum[plane] = skl_dbuf_min_alloc(p, 0);/*
uv-plane/packed */
alloc_size -= minimum[plane];
- y_minimum[plane] = p-y_bytes_per_pixel ? 8 : 0;
+ y_minimum[plane] = skl_dbuf_min_alloc(p, 1); /* y-plane */
alloc_size -= y_minimum[plane];
}
--
1.7.9.5
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[Intel-gfx] [PATCH 2/2] drm/i915: In DBUF/WM calcs for 90/270, swap w h
This patch swaps src width and height for dbuf/wm calculations
when rotation is 90/270 as per hw requirements.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 32
1 file changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ea3e435..767313b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2913,6 +2913,8 @@ static void skl_compute_wm_pipe_parameters(struct
drm_crtc *crtc,
enum pipe pipe = intel_crtc-pipe;
struct drm_plane *plane;
struct drm_framebuffer *fb;
+ struct intel_plane_state *plane_state;
+ int src_w, src_h;
int i = 1; /* Index for sprite planes start */
p-active = intel_crtc-active;
@@ -2921,6 +2923,7 @@ static void skl_compute_wm_pipe_parameters(struct
drm_crtc *crtc,
p-pixel_rate = skl_pipe_pixel_rate(intel_crtc-config);
fb = crtc-primary-state-fb;
+ plane_state = to_intel_plane_state(crtc-primary-state);
/* For planar: Bpp is for uv plane, y_Bpp is for y plane */
if (fb) {
p-plane[0].enabled = true;
@@ -2935,8 +2938,22 @@ static void skl_compute_wm_pipe_parameters(struct
drm_crtc *crtc,
p-plane[0].y_bytes_per_pixel = 0;
p-plane[0].tiling = DRM_FORMAT_MOD_NONE;
}
- p-plane[0].horiz_pixels = intel_crtc-config-pipe_src_w;
- p-plane[0].vert_pixels = intel_crtc-config-pipe_src_h;
+
+ if (drm_rect_width(plane_state-src)) {
+ src_w = drm_rect_width(plane_state-src) 16;
+ src_h = drm_rect_height(plane_state-src) 16;
+ } else {
+ src_w = intel_crtc-config-pipe_src_w;
+ src_h = intel_crtc-config-pipe_src_h;
+ }
+
+ if (intel_rotation_90_or_270(crtc-primary-state-rotation)) {
+ p-plane[0].horiz_pixels = src_h;
+ p-plane[0].vert_pixels = src_w;
+ } else {
+ p-plane[0].horiz_pixels = src_w;
+ p-plane[0].vert_pixels = src_h;
+ }
p-plane[0].rotation = crtc-primary-state-rotation;
fb = crtc-cursor-state-fb;
@@ -3468,8 +3485,15 @@ skl_update_sprite_wm(struct drm_plane *plane, struct
drm_crtc *crtc,
intel_plane-wm.enabled = enabled;
intel_plane-wm.scaled = scaled;
- intel_plane-wm.horiz_pixels = sprite_width;
- intel_plane-wm.vert_pixels = sprite_height;
+
+ if (intel_rotation_90_or_270(plane-state-rotation)) {
+ intel_plane-wm.horiz_pixels = sprite_height;
+ intel_plane-wm.vert_pixels = sprite_width;
+ } else {
+ intel_plane-wm.horiz_pixels = sprite_width;
+ intel_plane-wm.vert_pixels = sprite_height;
+ }
+
intel_plane-wm.tiling = DRM_FORMAT_MOD_NONE;
/* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
--
1.7.9.5
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[Intel-gfx] [PATCH] drm/i915: Delete duplicate #defines added for DCx
Delete the duplicate #defines introduced by:
commit 6b457d31ea0465fcadcf6d5044f5f71398954727
Author: A.Sunil Kamath sunil.kam...@intel.com
Date: Thu Apr 16 14:22:09 2015 +0530
drm/i915/skl: Implement enable/disable for Display C5 state.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 40a3a64..741cd32 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7281,12 +7281,6 @@ enum skl_disp_power_wells {
#define DC_STATE_EN0x45504
#define DC_STATE_EN_UPTO_DC5 (10)
#define DC_STATE_EN_DC9 (13)
-
-/*
-* SKL DC
-*/
-#define DC_STATE_EN 0x45504
-#define DC_STATE_EN_UPTO_DC5 (10)
#define DC_STATE_EN_UPTO_DC6 (20)
#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
--
1.7.9.5
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[Intel-gfx] [PATCH] drm/i915/skl: don't fail colorkey + scaler request
There is a mplayer video failure reported with xv.
This is because there is a request to do both plane scaling
and colorkey. Because skl hw doesn't support plane scaling
and colorkey at the same time, request is failed which is expected
behavior.
To make xv operate, this patch allows colorkey continue to work
without using scaler. Then behavior would be similar to platforms
without plane scaler support.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90449
---
drivers/gpu/drm/i915/intel_display.c | 14 +-
drivers/gpu/drm/i915/intel_sprite.c | 31 +--
2 files changed, 30 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 7ab75c0..fc5cef0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4505,9 +4505,10 @@ skl_update_scaler_users(
}
/* check colorkey */
- if (intel_plane intel_plane-ckey.flags != I915_SET_COLORKEY_NONE) {
- DRM_DEBUG_KMS(PLANE:%d scaling with color key not allowed,
- intel_plane-base.base.id);
+ if (WARN_ON(intel_plane
+ intel_plane-ckey.flags != I915_SET_COLORKEY_NONE)) {
+ DRM_DEBUG_KMS(PLANE:%d scaling %ux%u-%ux%u not allowed with
colorkey,
+ intel_plane-base.base.id, src_w, src_h, dst_w, dst_h);
return -EINVAL;
}
@@ -13049,8 +13050,11 @@ intel_check_primary_plane(struct drm_plane *plane,
intel_atomic_get_crtc_state(state-base.state, intel_crtc) :
NULL;
if (INTEL_INFO(dev)-gen = 9) {
- min_scale = 1;
- max_scale = skl_max_scale(intel_crtc, crtc_state);
+ /* use scaler when colorkey is not required */
+ if (to_intel_plane(plane)-ckey.flags ==
I915_SET_COLORKEY_NONE) {
+ min_scale = 1;
+ max_scale = skl_max_scale(intel_crtc, crtc_state);
+ }
can_position = true;
}
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 16d0e48..9004e47 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -775,7 +775,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
struct drm_rect *dst = state-dst;
const struct drm_rect *clip = state-clip;
int hscale, vscale;
- int max_scale, min_scale;
+ int max_scale, min_scale, can_scale;
int pixel_size;
int ret;
@@ -800,18 +800,29 @@ intel_check_sprite_plane(struct drm_plane *plane,
return -EINVAL;
}
+ /* setup can_scale, min_scale, max_scale */
+ if (INTEL_INFO(dev)-gen = 9) {
+ /* use scaler when colorkey is not required */
+ if (intel_plane-ckey.flags == I915_SET_COLORKEY_NONE) {
+ can_scale = 1;
+ min_scale = 1;
+ max_scale = skl_max_scale(intel_crtc, crtc_state);
+ } else {
+ can_scale = 0;
+ min_scale = DRM_PLANE_HELPER_NO_SCALING;
+ max_scale = DRM_PLANE_HELPER_NO_SCALING;
+ }
+ } else {
+ can_scale = intel_plane-can_scale;
+ max_scale = intel_plane-max_downscale 16;
+ min_scale = intel_plane-can_scale ? 1 : (1 16);
+ }
+
/*
* FIXME the following code does a bunch of fuzzy adjustments to the
* coordinates and sizes. We probably need some way to decide whether
* more strict checking should be done instead.
*/
- max_scale = intel_plane-max_downscale 16;
- min_scale = intel_plane-can_scale ? 1 : (1 16);
-
- if (INTEL_INFO(dev)-gen = 9) {
- min_scale = 1;
- max_scale = skl_max_scale(intel_crtc, crtc_state);
- }
drm_rect_rotate(src, fb-width 16, fb-height 16,
state-base.rotation);
@@ -882,7 +893,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
* Must keep src and dst the
* same if we can't scale.
*/
- if (!intel_plane-can_scale)
+ if (!can_scale)
crtc_w = ~1;
if (crtc_w == 0)
@@ -894,7 +905,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
if (state-visible (src_w != crtc_w || src_h != crtc_h)) {
unsigned int width_bytes;
- WARN_ON(!intel_plane-can_scale);
+ WARN_ON(!can_scale);
/* FIXME interlacing min height is 6 */
--
1.7.9.5
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[Intel-gfx] [PATCH 10/12] drm/i915: Add NV12 to primary plane programming.
This patch is adding NV12 support to skylake primary plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.
For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. Once GEM adds support
for seperate remappings for two subplanes, 90/270 support
to be added to plane programming.
v2:
-Use regular int instead of 16.16 in aux_offset calculations (me)
v3:
-Allow 90/270 for NV12 as its remapping is now supported (me)
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index b31f0fe..cb3a0fc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3028,6 +3028,9 @@ u32 skl_plane_ctl_format(uint32_t pixel_format)
case DRM_FORMAT_VYUY:
format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
break;
+ case DRM_FORMAT_NV12:
+ format = PLANE_CTL_FORMAT_NV12;
+ break;
default:
MISSING_CASE(pixel_format);
}
@@ -3102,6 +3105,8 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
int scaler_id = -1;
+ u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ u32 tile_row_adjustment = 0;
plane_state = to_intel_plane_state(plane-state);
@@ -3158,11 +3163,34 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
x_offset = stride * tile_height - y - src_h;
y_offset = x;
plane_size = (src_w - 1) 16 | (src_h - 1);
+ /*
+* TBD: For NV12 90/270 rotation, Y and UV subplanes should
+* be treated as separate surfaces and GTT remapping for
+* rotation should be done separately for each subplane.
+* Enable support once seperate remappings are available.
+*/
} else {
stride = fb-pitches[0] / stride_div;
x_offset = x;
y_offset = y;
plane_size = (src_h - 1) 16 | (src_w - 1);
+ tile_height = PAGE_SIZE / stride_div;
+
+ if (fb-pixel_format == DRM_FORMAT_NV12) {
+ int height_in_mem = (fb-offsets[1]/fb-pitches[0]);
+ /*
+* If UV starts from middle of a page, then UV start
should
+* be programmed to beginning of that page. And offset
into that
+* page to be programmed into y-offset
+*/
+ tile_row_adjustment = height_in_mem % tile_height;
+ aux_dist = fb-pitches[0] * (height_in_mem -
tile_row_adjustment);
+ aux_x_offset = DIV_ROUND_UP(x, 2);
+ aux_y_offset = DIV_ROUND_UP(y, 2) + tile_row_adjustment;
+ /* For tile-Yf, uv-subplane tile width is 2x of
Y-subplane */
+ aux_stride = fb-modifier[0] ==
I915_FORMAT_MOD_Yf_TILED ?
+ stride / 2 : stride;
+ }
}
plane_offset = y_offset 16 | x_offset;
@@ -3170,11 +3198,14 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
+ I915_WRITE(PLANE_AUX_DIST(pipe, 0), aux_dist | aux_stride);
+ I915_WRITE(PLANE_AUX_OFFSET(pipe, 0), aux_y_offset 16 |
aux_x_offset);
if (scaler_id = 0) {
uint32_t ps_ctrl = 0;
WARN_ON(!dst_w || !dst_h);
+
ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
crtc_state-scaler_state.scalers[scaler_id].mode;
I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
@@ -3183,6 +3214,7 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w 16) |
dst_h);
I915_WRITE(PLANE_POS(pipe, 0), 0);
} else {
+ WARN_ON(fb-pixel_format == DRM_FORMAT_NV12);
I915_WRITE(PLANE_POS(pipe, 0), (dst_y 16) | dst_x);
}
@@ -13136,6 +13168,12 @@ intel_check_primary_plane(struct drm_plane *plane,
intel_crtc-atomic.update_wm = true;
}
+ /* Adjust (macro)pixel boundary */
+ if (fb format_is_yuv(fb-pixel_format)) {
+ src-x1 = ~0x1;
+ src-x2 = ~0x1
[Intel-gfx] [PATCH 11/12] drm/i915: Add NV12 to sprite plane programming.
This patch is adding NV12 support to skylake sprite plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.
For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. Once GEM adds support
for seperate remappings for two subplanes, 90/270 support
to be added to plane programming.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_sprite.c | 31 +--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 84755c6..42cfac8 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -190,6 +190,8 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
int x_offset, y_offset;
struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)-config;
int scaler_id;
+ u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ u32 tile_row_adjustment = 0;
plane_ctl = PLANE_CTL_ENABLE |
PLANE_CTL_PIPE_CSC_ENABLE;
@@ -236,24 +238,48 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
plane_size = (src_w 16) | src_h;
x_offset = stride * tile_height - y - (src_h + 1);
y_offset = x;
+
+ /*
+* TBD: For NV12 90/270 rotation, Y and UV subplanes should
+* be treated as separate surfaces and GTT remapping for
+* rotation should be done separately for each subplane.
+* Enable support once seperate remappings are available.
+*/
} else {
stride = fb-pitches[0] / stride_div;
plane_size = (src_h 16) | src_w;
x_offset = x;
y_offset = y;
+ tile_height = PAGE_SIZE / stride_div;
+
+ if (fb-pixel_format == DRM_FORMAT_NV12) {
+ int height_in_mem = (fb-offsets[1]/fb-pitches[0]);
+ /*
+* If UV starts from middle of a page, then UV start
should
+* be programmed to beginning of that page. And offset
into that
+* page to be programmed into y-offset
+*/
+ tile_row_adjustment = height_in_mem % tile_height;
+ aux_dist = fb-pitches[0] * (height_in_mem -
tile_row_adjustment);
+ aux_x_offset = DIV_ROUND_UP(x, 2);
+ aux_y_offset = DIV_ROUND_UP(y, 2) + tile_row_adjustment;
+ /* For tile-Yf, uv-subplane tile width is 2x of
Y-subplane */
+ aux_stride = fb-modifier[0] ==
I915_FORMAT_MOD_Yf_TILED ?
+ stride / 2 : stride;
+ }
}
plane_offset = y_offset 16 | x_offset;
I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
+ I915_WRITE(PLANE_AUX_DIST(pipe, plane), aux_dist | aux_stride);
+ I915_WRITE(PLANE_AUX_OFFSET(pipe, plane), aux_y_offset16 |
aux_x_offset);
/* program plane scaler */
if (scaler_id = 0) {
uint32_t ps_ctrl = 0;
- DRM_DEBUG_KMS(plane = %d PS_PLANE_SEL(plane) = 0x%x\n, plane,
- PS_PLANE_SEL(plane));
ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) |
crtc_state-scaler_state.scalers[scaler_id].mode;
I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
@@ -264,6 +290,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
I915_WRITE(PLANE_POS(pipe, plane), 0);
} else {
+ WARN_ON(fb-pixel_format == DRM_FORMAT_NV12);
I915_WRITE(PLANE_POS(pipe, plane), (crtc_y 16) | crtc_x);
}
--
1.7.9.5
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[Intel-gfx] [PATCH 07/12] drm/i915: Add NV12 as supported format for sprite plane
This patch adds NV12 to list of supported formats for
sprite plane.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_sprite.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index b2491ad..84755c6 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1096,6 +1096,19 @@ static uint32_t skl_plane_formats[] = {
DRM_FORMAT_VYUY,
};
+static uint32_t skl_plane_formats_with_nv12[] = {
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+};
+
int
intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
{
@@ -1167,8 +1180,14 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe,
int plane)
intel_plane-disable_plane = skl_disable_plane;
state-scaler_id = -1;
- plane_formats = skl_plane_formats;
- num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+ if ((pipe == PIPE_A || pipe == PIPE_B) (plane == 0)) {
+ plane_formats = skl_plane_formats_with_nv12;
+ num_plane_formats =
ARRAY_SIZE(skl_plane_formats_with_nv12);
+ } else {
+ plane_formats = skl_plane_formats;
+ num_plane_formats = ARRAY_SIZE(skl_plane_formats) - 1;
+ }
+
break;
default:
kfree(intel_plane);
--
1.7.9.5
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[Intel-gfx] [PATCH 00/12] drm/i915: Adding NV12 for skylake display
This patch series is adding NV12 support for Skylake display after rebasing on latest drm-intel-nightly. Earlier I had two patch series one for 0/180 and another for 90/270. Some of the patches were already merged. This is combined series to support 0/90/180/270 and removing the ones that are already merged. Feature is tested with igt/kms_nv12 testcase. Feature is unit tested for linear/X/Y/Yf formats in 0, 90, 180, 270 orientations with combinations of 1, 2 or 3 planes enabled along with scaling. Also negatively tested for enabling NV12 on unsupported plane. The last patch in this series depends on Tvrtko's GEM remapping for NV12 format patch series. Chandra Konduru (12): drm/i915: Add register definitions for NV12 support drm/i915: Set scaler mode for NV12 drm/i915: Stage scaler request for NV12 as src format drm/i915: Update format_is_yuv() to include NV12 drm/i915: Upscale scaler max scale for NV12. drm/i915: Add NV12 as supported format for primary plane drm/i915: Add NV12 as supported format for sprite plane drm/i915: Add NV12 support to intel_framebuffer_init drm/i915: Enable NV12 primary plane via crtc set config drm/i915: Add NV12 to primary plane programming. drm/i915: Add NV12 to sprite plane programming. drm/i915: Add 90/270 rotation for NV12 format. drivers/gpu/drm/i915/i915_reg.h | 27 drivers/gpu/drm/i915/intel_atomic.c |5 +- drivers/gpu/drm/i915/intel_display.c | 121 -- drivers/gpu/drm/i915/intel_drv.h |4 +- drivers/gpu/drm/i915/intel_sprite.c | 77 -- 5 files changed, 219 insertions(+), 15 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/12] drm/i915: Add NV12 support to intel_framebuffer_init
This patch adds NV12 as supported format to
intel_framebuffer_init and performs various checks.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 42924a6..41cd26f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14043,6 +14043,33 @@ static int intel_framebuffer_init(struct drm_device
*dev,
return -EINVAL;
}
break;
+ case DRM_FORMAT_NV12:
+ if (INTEL_INFO(dev)-gen 9) {
+ DRM_DEBUG(unsupported pixel format: %s\n,
+ drm_get_format_name(mode_cmd-pixel_format));
+ return -EINVAL;
+ }
+ if (!mode_cmd-offsets[1]) {
+ DRM_DEBUG(uv start offset not set\n);
+ return -EINVAL;
+ }
+ if (mode_cmd-pitches[0] != mode_cmd-pitches[1] ||
+ mode_cmd-handles[0] != mode_cmd-handles[1]) {
+ DRM_DEBUG(y and uv subplanes have different
parameters\n);
+ return -EINVAL;
+ }
+ if (mode_cmd-modifier[1] == I915_FORMAT_MOD_Yf_TILED
+ (mode_cmd-offsets[1] 0xFFF)) {
+ DRM_DEBUG(tile-Yf uv offset 0x%x isn't starting on new
tile-row\n,
+ mode_cmd-offsets[1]);
+ return -EINVAL;
+ }
+ if (mode_cmd-modifier[1] == I915_FORMAT_MOD_Y_TILED
+ ((mode_cmd-offsets[1] % mode_cmd-pitches[1]) % 4)) {
+ DRM_DEBUG(tile-Y uv offset 0x%x isn't 4-line
aligned\n,
+ mode_cmd-offsets[1]);
+ }
+ break;
default:
DRM_DEBUG(unsupported pixel format: %s\n,
drm_get_format_name(mode_cmd-pixel_format));
--
1.7.9.5
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[Intel-gfx] [PATCH 09/12] drm/i915: Enable NV12 primary plane via crtc set config
Setup a scaler for primary plane if its FB is in NV12 format in legacy crtc set config path. Signed-off-by: Chandra Konduru chandra.kond...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 41cd26f..b31f0fe 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12292,6 +12292,16 @@ intel_modeset_compute_config(struct drm_crtc *crtc, if (ret) return ERR_PTR(ret); + /* +* FIXME: Until full atomic_crtc is available and hooked up for +* legacy APIs, setup scaler for primary plane with NV12 fb coming +* in those paths (e.g., crtc_setconfig). +*/ + ret = intel_atomic_setup_scalers(state-dev, to_intel_crtc(crtc), + pipe_config); + if (ret) + return ERR_PTR(ret); + return pipe_config; } -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/12] drm/i915: Add register definitions for NV12 support
This patch adds register definitions for skylake
display NV12 support.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 77055b9..e9ec5e2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5408,6 +5408,7 @@ enum skl_disp_power_wells {
#define PS_SCALER_MODE_MASK (3 28)
#define PS_SCALER_MODE_DYN (0 28)
#define PS_SCALER_MODE_HQ (1 28)
+#define PS_SCALER_MODE_NV12 (2 28)
#define PS_PLANE_SEL_MASK (7 25)
#define PS_PLANE_SEL(plane) ((plane + 1) 25)
#define PS_FILTER_MASK (3 23)
@@ -5511,6 +5512,32 @@ enum skl_disp_power_wells {
_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)
+
+/*
+ * Skylake NV12 Register
+ */
+#define PLANE_AUX_DIST_1_A 0x701c0
+#define PLANE_AUX_DIST_2_A 0x702c0
+#define PLANE_AUX_DIST_1_B 0x711c0
+#define PLANE_AUX_DIST_2_B 0x712c0
+#define _PLANE_AUX_DIST_1(pipe)\
+ _PIPE(pipe, PLANE_AUX_DIST_1_A, PLANE_AUX_DIST_1_B)
+#define _PLANE_AUX_DIST_2(pipe)\
+ _PIPE(pipe, PLANE_AUX_DIST_2_A, PLANE_AUX_DIST_2_B)
+#define PLANE_AUX_DIST(pipe, plane)\
+ _PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
+
+#define PLANE_AUX_OFFSET_1_A 0x701c4
+#define PLANE_AUX_OFFSET_2_A 0x702c4
+#define PLANE_AUX_OFFSET_1_B 0x711c4
+#define PLANE_AUX_OFFSET_2_B 0x712c4
+#define _PLANE_AUX_OFFSET_1(pipe) \
+ _PIPE(pipe, PLANE_AUX_OFFSET_1_A, PLANE_AUX_OFFSET_1_B)
+#define _PLANE_AUX_OFFSET_2(pipe) \
+ _PIPE(pipe, PLANE_AUX_OFFSET_2_A, PLANE_AUX_OFFSET_2_B)
+#define PLANE_AUX_OFFSET(pipe, plane) \
+ _PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
+
/* legacy palette */
#define _LGC_PALETTE_A 0x4a000
#define _LGC_PALETTE_B 0x4a800
--
1.7.9.5
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[Intel-gfx] [PATCH 06/12] drm/i915: Add NV12 as supported format for primary plane
This patch adds NV12 to list of supported formats for
primary plane.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index b7e4b3b..42924a6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -70,6 +70,18 @@ static const uint32_t i965_primary_formats[] = {
DRM_FORMAT_ABGR2101010,
};
+/* Primary plane formats for gen = 9 with NV12 */
+static const uint32_t skl_primary_formats_with_nv12[] = {
+ COMMON_PRIMARY_FORMATS, \
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ABGR2101010,
+ DRM_FORMAT_NV12,
+};
+
/* Cursor formats */
static const uint32_t intel_cursor_formats[] = {
DRM_FORMAT_ARGB,
@@ -13315,6 +13327,10 @@ static struct drm_plane
*intel_primary_plane_create(struct drm_device *dev,
if (INTEL_INFO(dev)-gen = 3) {
intel_primary_formats = i8xx_primary_formats;
num_formats = ARRAY_SIZE(i8xx_primary_formats);
+ } else if (INTEL_INFO(dev)-gen = 9
+ (pipe == PIPE_A || pipe == PIPE_B)) {
+ intel_primary_formats = skl_primary_formats_with_nv12;
+ num_formats = ARRAY_SIZE(skl_primary_formats_with_nv12);
} else {
intel_primary_formats = i965_primary_formats;
num_formats = ARRAY_SIZE(i965_primary_formats);
--
1.7.9.5
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[Intel-gfx] [PATCH 12/12] drm/i915: Add 90/270 rotation for NV12 format.
Adding NV12 90/270 rotation support for primary and sprite planes.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 23 ---
drivers/gpu/drm/i915/intel_sprite.c | 32 +---
2 files changed, 41 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index cb3a0fc..d108a97 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3105,7 +3105,8 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
int scaler_id = -1;
- u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ unsigned long aux_dist = 0;
+ u32 aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
u32 tile_row_adjustment = 0;
plane_state = to_intel_plane_state(plane-state);
@@ -3163,12 +3164,16 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
x_offset = stride * tile_height - y - src_h;
y_offset = x;
plane_size = (src_w - 1) 16 | (src_h - 1);
- /*
-* TBD: For NV12 90/270 rotation, Y and UV subplanes should
-* be treated as separate surfaces and GTT remapping for
-* rotation should be done separately for each subplane.
-* Enable support once seperate remappings are available.
-*/
+
+ if (fb-pixel_format == DRM_FORMAT_NV12) {
+ u32 uv_tile_height = intel_tile_height(dev,
fb-pixel_format,
+ fb-modifier[0], 1);
+ aux_stride = DIV_ROUND_UP(fb-height / 2,
uv_tile_height);
+ aux_dist =
intel_plane_obj_offset(to_intel_plane(plane), obj, 1) -
+ surf_addr;
+ aux_x_offset = aux_stride * uv_tile_height - y / 2 -
fb-height / 2;
+ aux_y_offset = x / 2;
+ }
} else {
stride = fb-pitches[0] / stride_div;
x_offset = x;
@@ -13172,6 +13177,10 @@ intel_check_primary_plane(struct drm_plane *plane,
if (fb format_is_yuv(fb-pixel_format)) {
src-x1 = ~0x1;
src-x2 = ~0x1;
+ if (intel_rotation_90_or_270(state-base.rotation)) {
+ src-y1 = ~0x1;
+ src-y2 = ~0x1;
+ }
}
if (INTEL_INFO(dev)-gen = 9) {
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 42cfac8..8b5be50 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -190,7 +190,8 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
int x_offset, y_offset;
struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)-config;
int scaler_id;
- u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ unsigned long aux_dist = 0;
+ u32 aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
u32 tile_row_adjustment = 0;
plane_ctl = PLANE_CTL_ENABLE |
@@ -239,12 +240,14 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
x_offset = stride * tile_height - y - (src_h + 1);
y_offset = x;
- /*
-* TBD: For NV12 90/270 rotation, Y and UV subplanes should
-* be treated as separate surfaces and GTT remapping for
-* rotation should be done separately for each subplane.
-* Enable support once seperate remappings are available.
-*/
+ if (fb-pixel_format == DRM_FORMAT_NV12) {
+ u32 uv_tile_height = intel_tile_height(dev,
fb-pixel_format,
+ fb-modifier[0], 1);
+ aux_stride = DIV_ROUND_UP(fb-height / 2,
uv_tile_height);
+ aux_dist = intel_plane_obj_offset(intel_plane, obj, 1)
- surf_addr;
+ aux_x_offset = aux_stride * uv_tile_height - y / 2 -
fb-height / 2;
+ aux_y_offset = x / 2;
+ }
} else {
stride = fb-pitches[0] / stride_div;
plane_size = (src_h 16) | src_w;
@@ -909,6 +912,21 @@ intel_check_sprite_plane(struct drm_plane *plane,
if (crtc_w == 0)
state-visible = false;
+
+ if (intel_rotation_90_or_270(state-base.rotation)) {
+ src_y = ~1;
+ src_h = ~1
[Intel-gfx] [PATCH 05/12] drm/i915: Upscale scaler max scale for NV12.
This patch updates max supported scaler limits for NV12.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 12
drivers/gpu/drm/i915/intel_drv.h |3 ++-
drivers/gpu/drm/i915/intel_sprite.c |2 +-
3 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 1ad7d13..b7e4b3b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13001,7 +13001,8 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
}
int
-skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state
*crtc_state)
+skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state
*crtc_state,
+ uint32_t pixel_format)
{
int max_scale;
struct drm_device *dev;
@@ -13021,11 +13022,13 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct
intel_crtc_state *crtc_state
/*
* skl max scale is lower of:
-*close to 3 but not 3, -1 is for that purpose
+*close to 2 or 3 (NV12: 2, other formats: 3) but not equal,
+* -1 is for that purpose
*or
*cdclk/crtc_clock
*/
- max_scale = min((1 16) * 3 - 1, (1 8) * ((cdclk 8) /
crtc_clock));
+ max_scale = min((1 16) * (pixel_format == DRM_FORMAT_NV12 ? 2 : 3) -
1,
+ (1 8) * ((cdclk 8) / crtc_clock));
return max_scale;
}
@@ -13055,7 +13058,8 @@ intel_check_primary_plane(struct drm_plane *plane,
if (INTEL_INFO(dev)-gen = 9) {
min_scale = 1;
- max_scale = skl_max_scale(intel_crtc, crtc_state);
+ max_scale = skl_max_scale(intel_crtc, crtc_state,
+ fb ? fb-pixel_format :0);
can_position = true;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 754172f..aa77af7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1139,7 +1139,8 @@ void skl_detach_scalers(struct intel_crtc *intel_crtc);
int skl_update_scaler_users(struct intel_crtc *intel_crtc,
struct intel_crtc_state *crtc_state, struct intel_plane *intel_plane,
struct intel_plane_state *plane_state, int force_detach);
-int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state
*crtc_state);
+int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
+ uint32_t pixel_format);
unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 80ae21f..b2491ad 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -805,7 +805,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
if (INTEL_INFO(dev)-gen = 9) {
min_scale = 1;
- max_scale = skl_max_scale(intel_crtc, crtc_state);
+ max_scale = skl_max_scale(intel_crtc, crtc_state,
fb-pixel_format);
}
drm_rect_rotate(src, fb-width 16, fb-height 16,
--
1.7.9.5
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[Intel-gfx] [PATCH 02/12] drm/i915: Set scaler mode for NV12
This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_atomic.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm/i915/intel_atomic.c
index 7ed8033..13f8a95 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -404,7 +404,10 @@ int intel_atomic_setup_scalers(struct drm_device *dev,
}
/* set scaler mode */
- if (num_scalers_need == 1 intel_crtc-pipe != PIPE_C) {
+ if (plane_state plane_state-base.fb
+ plane_state-base.fb-pixel_format == DRM_FORMAT_NV12) {
+ scaler_state-scalers[*scaler_id].mode =
PS_SCALER_MODE_NV12;
+ } else if (num_scalers_need == 1 intel_crtc-pipe != PIPE_C)
{
/*
* when only 1 scaler is in use on either pipe A or B,
* scaler 0 operates in high quality (HQ) mode.
--
1.7.9.5
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[Intel-gfx] [PATCH 03/12] drm/i915: Stage scaler request for NV12 as src format
This patch stages a scaler request when input format is NV12. The same scaler does both chroma-upsampling and resolution scaling as needed. Signed-off-by: Chandra Konduru chandra.kond...@intel.com --- drivers/gpu/drm/i915/intel_display.c |9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0a2e883..1ad7d13 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4499,9 +4499,11 @@ skl_update_scaler_users( rotation = DRM_ROTATE_0; } - need_scaling = intel_rotation_90_or_270(rotation) ? - (src_h != dst_w || src_w != dst_h): - (src_w != dst_w || src_h != dst_h); + /* scaling is required when src dst sizes doesn't match or format is NV12 */ + need_scaling = (src_w != dst_w || src_h != dst_h || + (intel_rotation_90_or_270(rotation) + (src_h != dst_w || src_w != dst_h)) || + (fb fb-pixel_format == DRM_FORMAT_NV12)); /* * if plane is being disabled or scaler is no more required or force detach @@ -4567,6 +4569,7 @@ skl_update_scaler_users( case DRM_FORMAT_YVYU: case DRM_FORMAT_UYVY: case DRM_FORMAT_VYUY: + case DRM_FORMAT_NV12: break; default: DRM_DEBUG_KMS(PLANE:%d FB:%d unsupported scaling format 0x%x\n, -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] i-g-t: Update kms_panel_fitting to work on other platforms
From: chandra konduru chandra.kond...@intel.com
kms_panel_fitting currently enabled for SKL only, but as
panel_fitters are available on prior platforms, enable this
kms test for them too.
Signed-off-by: chandra konduru chandra.kond...@intel.com
---
tests/kms_panel_fitting.c |8
1 file changed, 8 deletions(-)
diff --git a/tests/kms_panel_fitting.c b/tests/kms_panel_fitting.c
index 4dc3bff..2d079b4 100644
--- a/tests/kms_panel_fitting.c
+++ b/tests/kms_panel_fitting.c
@@ -43,8 +43,6 @@ typedef struct {
int image_w;
int image_h;
- int num_scalers;
-
struct igt_fb fb1;
struct igt_fb fb2;
struct igt_fb fb3;
@@ -176,10 +174,6 @@ static void test_panel_fitting(data_t *d)
enum pipe pipe;
int valid_tests = 0;
- igt_require(d-display.has_universal_planes);
- igt_require(d-num_scalers);
- igt_require(d-num_scalers);
-
for_each_connected_output(display, output) {
drmModeModeInfo *mode, native_mode;
@@ -261,8 +255,6 @@ igt_simple_main
igt_display_init(data.display, data.drm_fd);
data.devid = intel_get_drm_devid(data.drm_fd);
- data.num_scalers = intel_gen(data.devid) = 9 ? 2 : 0;
-
test_panel_fitting(data);
igt_display_fini(data.display);
--
1.7.9.5
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[Intel-gfx] [PATCH] drm/i915: Make scaler_id check in check_crtc_state work for all gens
During check_crtc_state, scaler_id mispatch is being reported for HSW.
This is applicable for skl+ and not for HSW. It is introduced by
commit id:
commit a1b2278e4dfcd2dbea85e319ebf73a6b7b2f180b
Author: Chandra Konduru chandra.kond...@intel.com
Date: Tue Apr 7 15:28:45 2015 -0700
drm/i915: skylake panel fitting using shared scalers
This patch will make sure that we leave scaler_id as 0 for platforms
before skl and set for skl+ only. This way scaler_id check during
check_crtc_state will pass for both prior to skl and skl+ platforms.
v2:
-Leave scaler_id as 0 for gen 9 (Daniel)
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
References: http://lists.freedesktop.org/archives/intel-gfx/2015-May/065741.html
---
drivers/gpu/drm/i915/intel_display.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c297cdc..5c9f358 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9351,6 +9351,12 @@ static bool haswell_get_pipe_config(struct intel_crtc
*crtc,
}
pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc-pipe);
+
+ if (INTEL_INFO(dev)-gen = 9) {
+ pipe_config-scaler_state.scaler_id = -1;
+ pipe_config-scaler_state.scaler_users = ~(1
SKL_CRTC_INDEX);
+ }
+
if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
if (INTEL_INFO(dev)-gen == 9)
skylake_get_pfit_config(crtc, pipe_config);
@@ -9358,10 +9364,6 @@ static bool haswell_get_pipe_config(struct intel_crtc
*crtc,
ironlake_get_pfit_config(crtc, pipe_config);
else
MISSING_CASE(INTEL_INFO(dev)-gen);
-
- } else {
- pipe_config-scaler_state.scaler_id = -1;
- pipe_config-scaler_state.scaler_users = ~(1
SKL_CRTC_INDEX);
}
if (IS_HASWELL(dev))
@@ -13248,8 +13250,8 @@ static struct drm_plane
*intel_primary_plane_create(struct drm_device *dev,
primary-max_downscale = 1;
if (INTEL_INFO(dev)-gen = 9) {
primary-can_scale = true;
+ state-scaler_id = -1;
}
- state-scaler_id = -1;
primary-pipe = pipe;
primary-plane = pipe;
primary-check_plane = intel_check_primary_plane;
@@ -13431,7 +13433,6 @@ static struct drm_plane
*intel_cursor_plane_create(struct drm_device *dev,
cursor-max_downscale = 1;
cursor-pipe = pipe;
cursor-plane = pipe;
- state-scaler_id = -1;
cursor-check_plane = intel_check_cursor_plane;
cursor-commit_plane = intel_commit_cursor_plane;
cursor-disable_plane = intel_disable_cursor_plane;
@@ -13454,6 +13455,9 @@ static struct drm_plane
*intel_cursor_plane_create(struct drm_device *dev,
state-base.rotation);
}
+ if (INTEL_INFO(dev)-gen =9)
+ state-scaler_id = -1;
+
drm_plane_helper_add(cursor-base, intel_plane_helper_funcs);
return cursor-base;
--
1.7.9.5
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[Intel-gfx] [PATCH] Improvements to kms_plane_scaling
From: chandra konduru chandra.kond...@intel.com
This patch has below improvements:
- use tile-Y for fb1 which is used for 90/270 rotation
- add 90/270 rotation tests along with scaling
- remove primary_plane_scaling flag which isn't required anymore
- use helper igt_get_image_size() to get image size
- use fb's width/height to initialize fb1 in prepare_crtc
- position fb3 at (0,0) and set its src size to fb size
Depends on Prep work for adding NV12 testcase patch which adds
helper function igt_get_image_size().
v2:
-Remove primary_plane_scaling flag (Thomas)
-Fix running the test from any directory (Tvrtko)
Signed-off-by: chandra konduru chandra.kond...@intel.com
---
tests/kms_plane_scaling.c | 88 ---
1 file changed, 45 insertions(+), 43 deletions(-)
diff --git a/tests/kms_plane_scaling.c b/tests/kms_plane_scaling.c
index 00db5cb..aa88040 100644
--- a/tests/kms_plane_scaling.c
+++ b/tests/kms_plane_scaling.c
@@ -101,11 +101,11 @@ static void prepare_crtc(data_t *data, igt_output_t
*output, enum pipe pipe,
data-fb_id1 = igt_create_fb(data-drm_fd,
mode-hdisplay, mode-vdisplay,
DRM_FORMAT_XRGB,
- LOCAL_I915_FORMAT_MOD_X_TILED, /* tiled */
+ LOCAL_I915_FORMAT_MOD_Y_TILED, /* tiled */
data-fb1);
igt_assert(data-fb_id1);
- paint_color(data, data-fb1, mode-hdisplay, mode-vdisplay);
+ paint_color(data, data-fb1, data-fb1.width, data-fb1.height);
/*
* We always set the primary plane to actually enable the pipe as
@@ -206,10 +206,8 @@ static void test_plane_scaling(data_t *d)
{
igt_display_t *display = d-display;
igt_output_t *output;
- cairo_surface_t *image;
enum pipe pipe;
int valid_tests = 0;
- int primary_plane_scaling = 0; /* For now */
igt_require(d-display.has_universal_planes);
igt_require(d-num_scalers);
@@ -223,12 +221,7 @@ static void test_plane_scaling(data_t *d)
mode = igt_output_get_mode(output);
/* allocate fb2 with image size */
- image = cairo_image_surface_create_from_png(FILE_NAME);
- igt_assert(cairo_surface_status(image) == CAIRO_STATUS_SUCCESS);
- d-image_w = cairo_image_surface_get_width(image);
- d-image_h = cairo_image_surface_get_height(image);
- cairo_surface_destroy(image);
-
+ igt_get_image_size(FILE_NAME, d-image_w, d-image_h);
d-fb_id2 = igt_create_fb(d-drm_fd,
d-image_w, d-image_h,
DRM_FORMAT_XRGB,
@@ -249,22 +242,35 @@ static void test_plane_scaling(data_t *d)
d-plane1 = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
prepare_crtc(d, output, pipe, d-plane1, mode,
COMMIT_UNIVERSAL);
- if (primary_plane_scaling) {
- /* Primary plane upscaling */
- igt_fb_set_position(d-fb1, d-plane1, 100, 100);
- igt_fb_set_size(d-fb1, d-plane1, 500, 500);
- igt_plane_set_position(d-plane1, 0, 0);
- igt_plane_set_size(d-plane1, mode-hdisplay,
mode-vdisplay);
- igt_display_commit2(display, COMMIT_UNIVERSAL);
+ /* Primary plane upscaling with 90 rotation */
+ paint_color(d, d-fb1, 360, 640);
+ igt_fb_set_position(d-fb1, d-plane1, 0, 0);
+ igt_fb_set_size(d-fb1, d-plane1, 360, 640);
+ igt_plane_set_position(d-plane1, 0, 0);
+ igt_plane_set_size(d-plane1, mode-hdisplay, mode-vdisplay);
+ igt_plane_set_rotation(d-plane1, IGT_ROTATION_90);
+ igt_display_commit2(display, COMMIT_UNIVERSAL);
- /* Primary plane 1:1 no scaling */
+ /* Primary plane upscaling with 270 rotation */
+ if (d-fb1.width = 720 d-fb1.height = 1280) {
+ paint_color(d, d-fb1, 720, 1280);
igt_fb_set_position(d-fb1, d-plane1, 0, 0);
- igt_fb_set_size(d-fb1, d-plane1, d-fb1.width,
d-fb1.height);
+ igt_fb_set_size(d-fb1, d-plane1, 720, 1280);
igt_plane_set_position(d-plane1, 0, 0);
igt_plane_set_size(d-plane1, mode-hdisplay,
mode-vdisplay);
+ igt_plane_set_rotation(d-plane1, IGT_ROTATION_270);
igt_display_commit2(display, COMMIT_UNIVERSAL);
}
+ /* Primary plane 1:1 no scaling no rotation */
+ paint_color(d, d-fb1, d-fb1.width, d-fb1.height);
+ igt_fb_set_position(d-fb1, d-plane1, 0, 0);
+ igt_fb_set_size(d-fb1, d-plane1, d-fb1.width,
d-fb1.height
[Intel-gfx] [PREFIX i-g-t] Improvements to kms_plane_scaling
From: chandra konduru chandra.kond...@intel.com
Resending with correct subject-prefix.
This patch has below improvements:
- use tile-Y for fb1 which is used for 90/270 rotation
- add 90/270 rotation tests along with scaling
- remove primary_plane_scaling flag which isn't required anymore
- use helper igt_get_image_size() to get image size
- use fb's width/height to initialize fb1 in prepare_crtc
- position fb3 at (0,0) and set its src size to fb size
Depends on Prep work for adding NV12 testcase patch which adds
helper function igt_get_image_size().
v2:
-Remove primary_plane_scaling flag (Thomas)
-Fix running the test from any directory (Tvrtko)
Signed-off-by: chandra konduru chandra.kond...@intel.com
---
tests/kms_plane_scaling.c | 88 ---
1 file changed, 45 insertions(+), 43 deletions(-)
diff --git a/tests/kms_plane_scaling.c b/tests/kms_plane_scaling.c
index 00db5cb..aa88040 100644
--- a/tests/kms_plane_scaling.c
+++ b/tests/kms_plane_scaling.c
@@ -101,11 +101,11 @@ static void prepare_crtc(data_t *data, igt_output_t
*output, enum pipe pipe,
data-fb_id1 = igt_create_fb(data-drm_fd,
mode-hdisplay, mode-vdisplay,
DRM_FORMAT_XRGB,
- LOCAL_I915_FORMAT_MOD_X_TILED, /* tiled */
+ LOCAL_I915_FORMAT_MOD_Y_TILED, /* tiled */
data-fb1);
igt_assert(data-fb_id1);
- paint_color(data, data-fb1, mode-hdisplay, mode-vdisplay);
+ paint_color(data, data-fb1, data-fb1.width, data-fb1.height);
/*
* We always set the primary plane to actually enable the pipe as
@@ -206,10 +206,8 @@ static void test_plane_scaling(data_t *d)
{
igt_display_t *display = d-display;
igt_output_t *output;
- cairo_surface_t *image;
enum pipe pipe;
int valid_tests = 0;
- int primary_plane_scaling = 0; /* For now */
igt_require(d-display.has_universal_planes);
igt_require(d-num_scalers);
@@ -223,12 +221,7 @@ static void test_plane_scaling(data_t *d)
mode = igt_output_get_mode(output);
/* allocate fb2 with image size */
- image = cairo_image_surface_create_from_png(FILE_NAME);
- igt_assert(cairo_surface_status(image) == CAIRO_STATUS_SUCCESS);
- d-image_w = cairo_image_surface_get_width(image);
- d-image_h = cairo_image_surface_get_height(image);
- cairo_surface_destroy(image);
-
+ igt_get_image_size(FILE_NAME, d-image_w, d-image_h);
d-fb_id2 = igt_create_fb(d-drm_fd,
d-image_w, d-image_h,
DRM_FORMAT_XRGB,
@@ -249,22 +242,35 @@ static void test_plane_scaling(data_t *d)
d-plane1 = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
prepare_crtc(d, output, pipe, d-plane1, mode,
COMMIT_UNIVERSAL);
- if (primary_plane_scaling) {
- /* Primary plane upscaling */
- igt_fb_set_position(d-fb1, d-plane1, 100, 100);
- igt_fb_set_size(d-fb1, d-plane1, 500, 500);
- igt_plane_set_position(d-plane1, 0, 0);
- igt_plane_set_size(d-plane1, mode-hdisplay,
mode-vdisplay);
- igt_display_commit2(display, COMMIT_UNIVERSAL);
+ /* Primary plane upscaling with 90 rotation */
+ paint_color(d, d-fb1, 360, 640);
+ igt_fb_set_position(d-fb1, d-plane1, 0, 0);
+ igt_fb_set_size(d-fb1, d-plane1, 360, 640);
+ igt_plane_set_position(d-plane1, 0, 0);
+ igt_plane_set_size(d-plane1, mode-hdisplay, mode-vdisplay);
+ igt_plane_set_rotation(d-plane1, IGT_ROTATION_90);
+ igt_display_commit2(display, COMMIT_UNIVERSAL);
- /* Primary plane 1:1 no scaling */
+ /* Primary plane upscaling with 270 rotation */
+ if (d-fb1.width = 720 d-fb1.height = 1280) {
+ paint_color(d, d-fb1, 720, 1280);
igt_fb_set_position(d-fb1, d-plane1, 0, 0);
- igt_fb_set_size(d-fb1, d-plane1, d-fb1.width,
d-fb1.height);
+ igt_fb_set_size(d-fb1, d-plane1, 720, 1280);
igt_plane_set_position(d-plane1, 0, 0);
igt_plane_set_size(d-plane1, mode-hdisplay,
mode-vdisplay);
+ igt_plane_set_rotation(d-plane1, IGT_ROTATION_270);
igt_display_commit2(display, COMMIT_UNIVERSAL);
}
+ /* Primary plane 1:1 no scaling no rotation */
+ paint_color(d, d-fb1, d-fb1.width, d-fb1.height);
+ igt_fb_set_position(d-fb1, d-plane1, 0, 0);
+ igt_fb_set_size(d-fb1, d-plane1, d
[Intel-gfx] [PATCH 10/11] drm/i915: Add NV12 to primary plane programming.
This patch is adding NV12 support to skylake primary plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.
For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. Once GEM adds support
for seperate remappings for two subplanes, 90/270 support
to be added to plane programming.
v2:
-Use regular int instead of 16.16 in aux_offset calculations (me)
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_atomic_plane.c |2 ++
drivers/gpu/drm/i915/intel_display.c | 38 +
2 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 86ba4b2..119439d 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -185,10 +185,12 @@ static int intel_plane_atomic_check(struct drm_plane
*plane,
* 90/270 is not allowed with RGB64 16:16:16:16,
* RGB 16-bit 5:6:5, and Indexed 8-bit.
* TBD: Add RGB64 case once its added in supported format list.
+* TBD: Remove NV12, once its 90/270 remapping is supported
*/
switch (state-fb-pixel_format) {
case DRM_FORMAT_C8:
case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_NV12:
DRM_DEBUG_KMS(Unsupported pixel format %s for
90/270!\n,
drm_get_format_name(state-fb-pixel_format));
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3ae646e..943a835 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3015,6 +3015,9 @@ u32 skl_plane_ctl_format(uint32_t pixel_format)
case DRM_FORMAT_VYUY:
plane_ctl_format = PLANE_CTL_FORMAT_YUV422 |
PLANE_CTL_YUV422_VYUY;
break;
+ case DRM_FORMAT_NV12:
+ plane_ctl_format = PLANE_CTL_FORMAT_NV12;
+ break;
default:
BUG();
}
@@ -3085,6 +3088,8 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
int scaler_id = -1;
+ u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ u32 tile_row_adjustment = 0;
plane_state = to_intel_plane_state(plane-state);
@@ -3141,11 +3146,34 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
x_offset = stride * tile_height - y - src_h;
y_offset = x;
plane_size = (src_w - 1) 16 | (src_h - 1);
+ /*
+* TBD: For NV12 90/270 rotation, Y and UV subplanes should
+* be treated as separate surfaces and GTT remapping for
+* rotation should be done separately for each subplane.
+* Enable support once seperate remappings are available.
+*/
} else {
stride = fb-pitches[0] / stride_div;
x_offset = x;
y_offset = y;
plane_size = (src_h - 1) 16 | (src_w - 1);
+ tile_height = PAGE_SIZE / stride_div;
+
+ if (fb-pixel_format == DRM_FORMAT_NV12) {
+ int height_in_mem = (fb-offsets[1]/fb-pitches[0]);
+ /*
+* If UV starts from middle of a page, then UV start
should
+* be programmed to beginning of that page. And offset
into that
+* page to be programmed into y-offset
+*/
+ tile_row_adjustment = height_in_mem % tile_height;
+ aux_dist = fb-pitches[0] * (height_in_mem -
tile_row_adjustment);
+ aux_x_offset = DIV_ROUND_UP(x, 2);
+ aux_y_offset = DIV_ROUND_UP(y, 2) + tile_row_adjustment;
+ /* For tile-Yf, uv-subplane tile width is 2x of
Y-subplane */
+ aux_stride = fb-modifier[0] ==
I915_FORMAT_MOD_Yf_TILED ?
+ stride / 2 : stride;
+ }
}
plane_offset = y_offset 16 | x_offset;
@@ -3153,11 +3181,14 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
+ I915_WRITE(PLANE_AUX_DIST(pipe, 0), aux_dist | aux_stride);
+ I915_WRITE(PLANE_AUX_OFFSET(pipe, 0), aux_y_offset 16 |
aux_x_offset);
if (scaler_id = 0
[Intel-gfx] [PATCH 2/2] drm/i915: Add 90/270 rotation for NV12 format.
Adding NV12 90/270 rotation support for primary and sprite planes.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 23 ---
drivers/gpu/drm/i915/intel_sprite.c | 32 +---
2 files changed, 41 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c385a3b..77d7f69 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3105,7 +3105,8 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
int scaler_id = -1;
- u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ unsigned long aux_dist = 0;
+ u32 aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
u32 tile_row_adjustment = 0;
plane_state = to_intel_plane_state(plane-state);
@@ -3163,12 +3164,16 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
x_offset = stride * tile_height - y - src_h;
y_offset = x;
plane_size = (src_w - 1) 16 | (src_h - 1);
- /*
-* TBD: For NV12 90/270 rotation, Y and UV subplanes should
-* be treated as separate surfaces and GTT remapping for
-* rotation should be done separately for each subplane.
-* Enable support once seperate remappings are available.
-*/
+
+ if (fb-pixel_format == DRM_FORMAT_NV12) {
+ u32 uv_tile_height = intel_tile_height(dev,
fb-pixel_format,
+ fb-modifier[0], 1);
+ aux_stride = DIV_ROUND_UP(fb-height / 2,
uv_tile_height);
+ aux_dist =
intel_plane_obj_offset(to_intel_plane(plane), obj, 1) -
+ surf_addr;
+ aux_x_offset = aux_stride * uv_tile_height - y / 2 -
fb-height / 2;
+ aux_y_offset = x / 2;
+ }
} else {
stride = fb-pitches[0] / stride_div;
x_offset = x;
@@ -13144,6 +13149,10 @@ intel_check_primary_plane(struct drm_plane *plane,
if (fb format_is_yuv(fb-pixel_format)) {
src-x1 = ~0x1;
src-x2 = ~0x1;
+ if (intel_rotation_90_or_270(state-base.rotation)) {
+ src-y1 = ~0x1;
+ src-y2 = ~0x1;
+ }
}
if (INTEL_INFO(dev)-gen = 9) {
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index e23fe8e..d4ce7eb 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -190,7 +190,8 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
int x_offset, y_offset;
struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)-config;
int scaler_id;
- u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ unsigned long aux_dist = 0;
+ u32 aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
u32 tile_row_adjustment = 0;
plane_ctl = PLANE_CTL_ENABLE |
@@ -239,12 +240,14 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
x_offset = stride * tile_height - y - (src_h + 1);
y_offset = x;
- /*
-* TBD: For NV12 90/270 rotation, Y and UV subplanes should
-* be treated as separate surfaces and GTT remapping for
-* rotation should be done separately for each subplane.
-* Enable support once seperate remappings are available.
-*/
+ if (fb-pixel_format == DRM_FORMAT_NV12) {
+ u32 uv_tile_height = intel_tile_height(dev,
fb-pixel_format,
+ fb-modifier[0], 1);
+ aux_stride = DIV_ROUND_UP(fb-height / 2,
uv_tile_height);
+ aux_dist = intel_plane_obj_offset(intel_plane, obj, 1)
- surf_addr;
+ aux_x_offset = aux_stride * uv_tile_height - y / 2 -
fb-height / 2;
+ aux_y_offset = x / 2;
+ }
} else {
stride = fb-pitches[0] / stride_div;
plane_size = (src_h 16) | src_w;
@@ -909,6 +912,21 @@ intel_check_sprite_plane(struct drm_plane *plane,
if (crtc_w == 0)
state-visible = false;
+
+ if (intel_rotation_90_or_270(state-base.rotation)) {
+ src_y = ~1;
+ src_h = ~1
[Intel-gfx] [PATCH 1/2] drm/i915: call intel_tile_height with correct parameter
In skylake update plane functions, intel_tile_height() is called with
bits_per_pixel instead of pixel_format. Correcting it.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |2 +-
drivers/gpu/drm/i915/intel_sprite.c |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 66c78b6..c385a3b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3157,7 +3157,7 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
if (intel_rotation_90_or_270(rotation)) {
/* stride = Surface height in tiles */
- tile_height = intel_tile_height(dev, fb-bits_per_pixel,
+ tile_height = intel_tile_height(dev, fb-pixel_format,
fb-modifier[0], 0);
stride = DIV_ROUND_UP(fb-height, tile_height);
x_offset = stride * tile_height - y - src_h;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index fc1505b7..e23fe8e 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -232,7 +232,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
if (intel_rotation_90_or_270(rotation)) {
/* stride: Surface height in tiles */
- tile_height = intel_tile_height(dev, fb-bits_per_pixel,
+ tile_height = intel_tile_height(dev, fb-pixel_format,
fb-modifier[0], 0);
stride = DIV_ROUND_UP(fb-height, tile_height);
plane_size = (src_w 16) | src_h;
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/2] Add NV12 90/270 support for skl planes
First attempt to enabling 90/270 rotation for NV12 format using Tvrtko's recent rotated mapping for NV12. Calling intel_plane_obj_offset(plane, obj, 1) is causing kernel NULL pointer reference. Sending early out early for Tvrtko to work on the issue. Very first NV12 flip with 90/270 rotation giving rotated image but UV isn't there because of above issue. Also subsequent flips are causing crashes and lockups. Pending work: * few changes are need to DDB calcuations for NV12 90/270. Chandra Konduru (2): drm/i915: call intel_tile_height with correct parameter drm/i915: Add 90/270 rotation for NV12 format. drivers/gpu/drm/i915/intel_display.c | 25 + drivers/gpu/drm/i915/intel_sprite.c | 34 ++ 2 files changed, 43 insertions(+), 16 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] i-g-t: Adding display NV12 testcase
From: chandra konduru chandra.kond...@intel.com
This patch adds kms_nv12 test case. It covers testing NV12 in
all supported linear/tile-X/tile-Y/tile-Yf tile formats in
0 and 180 orientations. For each tiling format, it tests
various combinations of planes and scaling.
v2:
-Added 90/270 tests (me)
-took out crc test as it isn't adding much value due to chroma upsampling (me)
Signed-off-by: chandra konduru chandra.kond...@intel.com
---
tests/.gitignore | 1 +
tests/Android.mk | 1 +
tests/Makefile.sources | 1 +
tests/kms_nv12.c | 619 +
4 files changed, 622 insertions(+)
create mode 100644 tests/kms_nv12.c
diff --git a/tests/.gitignore b/tests/.gitignore
index 86795c0..b03647a 100644
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -149,6 +149,7 @@ kms_vblank
kms_crtc_background_color
kms_plane_scaling
kms_panel_fitting
+kms_nv12
pm_lpsp
pm_rc6_residency
pm_rpm
diff --git a/tests/Android.mk b/tests/Android.mk
index fac9931..c0c6383 100644
--- a/tests/Android.mk
+++ b/tests/Android.mk
@@ -81,6 +81,7 @@ else
kms_pwrite_crc \
kms_pipe_b_c_ivb \
kms_legacy_colorkey
+ kms_nv12 \
IGT_LOCAL_CFLAGS += -DANDROID_HAS_CAIRO=0
endif
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 12f27f9..32c1b25 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -79,6 +79,7 @@ TESTS_progs_M = \
kms_crtc_background_color \
kms_plane_scaling \
kms_panel_fitting \
+ kms_nv12 \
pm_lpsp \
pm_rpm \
pm_rps \
diff --git a/tests/kms_nv12.c b/tests/kms_nv12.c
new file mode 100644
index 000..616cf6e
--- /dev/null
+++ b/tests/kms_nv12.c
@@ -0,0 +1,619 @@
+/*
+ * Copyright © 2013,2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include math.h
+#include fcntl.h
+#include sys/stat.h
+
+#include drmtest.h
+#include igt_debugfs.h
+#include igt_kms.h
+#include igt_core.h
+#include intel_chipset.h
+#include ioctl_wrappers.h
+
+IGT_TEST_DESCRIPTION(Test display NV12 support);
+
+uint32_t devid;
+typedef struct {
+ int drm_fd;
+ igt_display_t display;
+ int num_scalers;
+
+ struct igt_fb fb1;
+ struct igt_fb fb1_nv12;
+ struct igt_fb fb2;
+ struct igt_fb fb2_nv12;
+ struct igt_fb fb3;
+ struct igt_fb fb3_nv12;
+ int fb_id1;
+ int fb_id1_nv12;
+ int fb_id2;
+ int fb_id2_nv12;
+ int fb_id3;
+ int fb_id3_nv12;
+
+ igt_plane_t *plane1;
+ igt_plane_t *plane2;
+ igt_plane_t *plane3;
+
+ uint64_t tiled;
+ int rotation;
+} data_t;
+
+typedef struct {
+ int width;
+ int height;
+} res_t;
+
+#define IMG_FILE 1080p-left.png
+
+static void
+paint_pattern(data_t *d, struct igt_fb *fb, uint16_t w, uint16_t h)
+{
+ cairo_t *cr;
+
+ cr = igt_get_cairo_ctx(d-drm_fd, fb);
+ igt_paint_test_pattern(cr, w, h);
+ cairo_destroy(cr);
+}
+
+static void
+paint_image(data_t *d, struct igt_fb *fb, uint16_t w, uint16_t h)
+{
+ cairo_t *cr;
+
+ cr = igt_get_cairo_ctx(d-drm_fd, fb);
+ igt_paint_image(cr, IMG_FILE, 0, 0, w, h);
+ cairo_destroy(cr);
+}
+
+static void prepare_crtc(data_t *data, igt_output_t *output, enum pipe pipe,
+ igt_plane_t *plane, drmModeModeInfo *mode, enum
igt_commit_style s)
+{
+ igt_display_t *display = data-display;
+
+ igt_output_set_pipe(output, pipe);
+
+ /* before allocating, free if any older fb */
+ if (data-fb_id1) {
+ igt_remove_fb(data-drm_fd, data-fb1);
+ data-fb_id1 = 0;
+ }
+
+ /* allocate fb for plane 1 */
+ data-fb_id1 = igt_create_fb(data-drm_fd,
+ mode-hdisplay, mode-vdisplay,
+ DRM_FORMAT_XRGB,
+ data-tiled
[Intel-gfx] [PATCH] drm/i915: perform scaler_id check for skl+
Scaler id is added for skylake to handle its shared scalers.
This is not applicable for platforms before SKL. This patch limits
the scaler_id check during intel_pipe_config_compare to platforms
SKL and above.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c297cdc..fc1b7f9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11846,7 +11846,9 @@ intel_pipe_config_compare(struct drm_device *dev,
PIPE_CONF_CHECK_I(pch_pfit.size);
}
- PIPE_CONF_CHECK_I(scaler_state.scaler_id);
+ if (INTEL_INFO(dev)-gen = 9) {
+ PIPE_CONF_CHECK_I(scaler_state.scaler_id);
+ }
/* BDW+ don't expose a synchronous way to read the state */
if (IS_HASWELL(dev))
--
1.7.9.5
___
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] i-g-t: Prep work for adding NV12 testcase
From: chandra konduru chandra.kond...@intel.com
This patch adds necessary prep work for nv12 testcase:
- updated fb allocation functions to handle NV12 format
- igt helper function to return png image size
- igt helper function to calculate start of uv in a given NV12 buffer
- igt helper function to map buffer for host access
- populates fb-...[4] parameters for NV12
- igt helper function to convert RGB data to NV12
- updated drm_format to bpp to handle NV12
- updated fast copy blit function to deal NV12 subplanes
- made an update to kms_render testcase due to above changes
Signed-off-by: chandra konduru chandra.kond...@intel.com
---
lib/igt_fb.c| 316 +---
lib/igt_fb.h| 9 +-
lib/intel_batchbuffer.c | 16 ++-
lib/intel_batchbuffer.h | 3 +-
lib/intel_reg.h | 1 +
lib/ioctl_wrappers.c| 10 +-
lib/ioctl_wrappers.h| 2 +-
tests/kms_render.c | 4 +-
8 files changed, 334 insertions(+), 27 deletions(-)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index cc4b8ee..dedee9e 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -74,7 +74,7 @@ static struct format_desc_struct {
/* helpers to create nice-looking framebuffers */
-static int create_bo_for_fb(int fd, int width, int height, int bpp,
+static int create_bo_for_fb(int fd, int width, int height, int bpp, int bpp2,
uint64_t tiling, unsigned bo_size,
uint32_t *gem_handle_ret,
unsigned *size_ret,
@@ -99,13 +99,17 @@ static int create_bo_for_fb(int fd, int width, int height,
int bpp,
for (stride = 512; stride v; stride *= 2)
;
- v = stride * height;
+ /* planar formats height is 1.5x */
+ v = stride * (bpp2 ? (height * 3) / 2 : height);
+
for (size = 1024*1024; size v; size *= 2)
;
} else {
/* Scan-out has a 64 byte alignment restriction */
stride = (width * (bpp / 8) + 63) ~63;
- size = stride * height;
+
+ /* planar formats height is 1.5x */
+ size = stride * (bpp2 ? (height * 3) / 2 : height);
}
if (bo_size == 0)
@@ -393,6 +397,75 @@ void igt_paint_image(cairo_t *cr, const char *filename,
}
/**
+ * igt_get_image_size:
+ * @filename: filename of the png image
+ * @width: width of the image
+ * @height: height of the image
+ *
+ * This function returns @width and @height of the png image in @filename,
+ * which is loaded from the package data directory.
+ */
+void
+igt_get_image_size(const char *filename, int *width, int *height)
+{
+ cairo_surface_t *image;
+ FILE* f;
+
+ f = igt_fopen_data(filename);
+
+ image = cairo_image_surface_create_from_png_stream(stdio_read_func, f);
+ igt_assert(cairo_surface_status(image) == CAIRO_STATUS_SUCCESS);
+
+ *width = cairo_image_surface_get_width(image);
+ *height = cairo_image_surface_get_height(image);
+
+ cairo_surface_destroy(image);
+
+ fclose(f);
+}
+
+
+/**
+ * igt_fb_calc_uv:
+ * @fb: pointer to an #igt_fb structure
+ *
+ * This function calculates UV offset in bytes and UV starting line number
+ * for requested NV12 @fb.
+ */
+void
+igt_fb_calc_uv(struct igt_fb *fb)
+{
+ if (fb-drm_format != DRM_FORMAT_NV12)
+ return;
+
+ switch (fb-tiling) {
+ case LOCAL_DRM_FORMAT_MOD_NONE:
+ fb-uv_y_start = fb-height;
+ break;
+ case LOCAL_I915_FORMAT_MOD_X_TILED:
+ fb-uv_y_start = fb-height;
+ break;
+ case LOCAL_I915_FORMAT_MOD_Y_TILED:
+ fb-uv_y_start = fb-height;
+ break;
+ case LOCAL_I915_FORMAT_MOD_Yf_TILED:
+ /* tile-Yf requires uv to start on a new tile row */
+ if (fb-height % 64)
+ fb-uv_y_start = (fb-height + 63) ~63;
+ else
+ fb-uv_y_start = fb-height;
+ break;
+ default:
+ igt_assert(0);
+ }
+
+ fb-uv_offset = fb-uv_y_start * fb-stride;
+
+ /* assert that fb has enough lines to hold y and uv sub-planes */
+ igt_assert(fb-size / fb-stride = fb-uv_y_start + fb-height / 2);
+}
+
+/**
* igt_create_fb_with_bo_size:
* @fd: open i915 drm file descriptor
* @width: width of the framebuffer in pixel
@@ -418,24 +491,32 @@ igt_create_fb_with_bo_size(int fd, int width, int height,
struct igt_fb *fb, unsigned bo_size)
{
uint32_t fb_id;
- int bpp;
+ int bpp, bpp2;
memset(fb, 0, sizeof(*fb));
- bpp = igt_drm_format_to_bpp(format);
+ bpp = igt_drm_format_to_bpp(format, 0);
+ bpp2 = igt_drm_format_to_bpp(format, 1);
- igt_debug(%s(width=%d, height=%d, format=0x%x [bpp=%d],
tiling=0x%PRIx64
[Intel-gfx] [PATCH 2/2] i-g-t: Adding display NV12 testcase
From: chandra konduru chandra.kond...@intel.com
This patch adds kms_nv12 test case. It covers testing NV12 in
all supported linear/tile-X/tile-Y/tile-Yf tile formats in
0 and 180 orientations. For each tiling format, it tests
various combinations of planes and scaling.
It has some very preliminary crc support and it is bit flaky.
Though I have seen once-in-a-while crc check failures, most of the
time they pass, so enabled by-default. If they cause headaches
they can be disabled as needed.
Signed-off-by: chandra konduru chandra.kond...@intel.com
---
tests/.gitignore | 1 +
tests/Android.mk | 1 +
tests/Makefile.sources | 1 +
tests/kms_nv12.c | 529 +
4 files changed, 532 insertions(+)
create mode 100644 tests/kms_nv12.c
diff --git a/tests/.gitignore b/tests/.gitignore
index 796e330..35c0e6e 100644
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -147,6 +147,7 @@ kms_vblank
kms_crtc_background_color
kms_plane_scaling
kms_panel_fitting
+kms_nv12
pm_lpsp
pm_rc6_residency
pm_rpm
diff --git a/tests/Android.mk b/tests/Android.mk
index fac9931..c0c6383 100644
--- a/tests/Android.mk
+++ b/tests/Android.mk
@@ -81,6 +81,7 @@ else
kms_pwrite_crc \
kms_pipe_b_c_ivb \
kms_legacy_colorkey
+ kms_nv12 \
IGT_LOCAL_CFLAGS += -DANDROID_HAS_CAIRO=0
endif
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 4cbc50d..b68224e 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -78,6 +78,7 @@ TESTS_progs_M = \
kms_crtc_background_color \
kms_plane_scaling \
kms_panel_fitting \
+ kms_nv12 \
pm_lpsp \
pm_rpm \
pm_rps \
diff --git a/tests/kms_nv12.c b/tests/kms_nv12.c
new file mode 100644
index 000..e88c934
--- /dev/null
+++ b/tests/kms_nv12.c
@@ -0,0 +1,529 @@
+/*
+ * Copyright © 2013,2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include math.h
+#include fcntl.h
+#include sys/stat.h
+
+#include drmtest.h
+#include igt_debugfs.h
+#include igt_kms.h
+#include igt_core.h
+#include intel_chipset.h
+#include ioctl_wrappers.h
+
+IGT_TEST_DESCRIPTION(Test display NV12 support);
+
+uint32_t devid;
+typedef struct {
+ int drm_fd;
+ igt_display_t display;
+ igt_crc_t crc1;
+ igt_crc_t crc2;
+ igt_pipe_crc_t *pipe_crc;
+ int num_scalers;
+
+ struct igt_fb fb1;
+ struct igt_fb fb1_nv12;
+ struct igt_fb fb2;
+ struct igt_fb fb2_nv12;
+ struct igt_fb fb3;
+ struct igt_fb fb3_nv12;
+ int fb_id1;
+ int fb_id1_nv12;
+ int fb_id2;
+ int fb_id2_nv12;
+ int fb_id3;
+ int fb_id3_nv12;
+
+ igt_plane_t *plane1;
+ igt_plane_t *plane2;
+ igt_plane_t *plane3;
+
+ uint64_t tiled;
+ int rotation;
+ int crc;
+} data_t;
+
+#define IMG_FILE 1080p-left.png
+#define SOLID_COLOR 0xFF /* BGR 8bpc */
+
+static void
+paint_pattern(data_t *d, struct igt_fb *fb, uint16_t w, uint16_t h)
+{
+ cairo_t *cr;
+
+ cr = igt_get_cairo_ctx(d-drm_fd, fb);
+ igt_paint_test_pattern(cr, w, h);
+ cairo_destroy(cr);
+}
+
+static void
+paint_image(data_t *d, struct igt_fb *fb, uint16_t w, uint16_t h)
+{
+ cairo_t *cr;
+
+ cr = igt_get_cairo_ctx(d-drm_fd, fb);
+ igt_paint_image(cr, IMG_FILE, 0, 0, w, h);
+ cairo_destroy(cr);
+}
+
+static void
+paint_solid_color(data_t *d, struct igt_fb *fb, uint16_t w, uint16_t h,
+ uint32_t color)
+{
+ cairo_t *cr;
+ double r, g, b;
+
+ cr = igt_get_cairo_ctx(d-drm_fd, fb);
+
+ /* Paint with solid color */
+ r = (double) (color 0xFF) / 255.0;
+ g = (double) ((color 0xFF00) 8) / 255.0;
+ b = (double) ((color 0xFF) 16) / 255.0;
+ igt_paint_color(cr, 0, 0, w, h, r, g, b);
+
+ cairo_destroy(cr
[Intel-gfx] [PATCH 0/2] i-g-t: kms testcase for NV12 feature
From: chandra konduru chandra.kond...@intel.com This patch series adds necessary prep work for NV12 support to igt lib and actual testcase to test NV12 feature. Refer to individual patch header and comments in code for details. chandra konduru (2): i-g-t: Prep work for adding NV12 testcase i-g-t: Adding display NV12 testcase lib/igt_fb.c| 316 +++-- lib/igt_fb.h| 9 +- lib/intel_batchbuffer.c | 16 +- lib/intel_batchbuffer.h | 3 +- lib/intel_reg.h | 1 + lib/ioctl_wrappers.c| 10 +- lib/ioctl_wrappers.h| 2 +- tests/.gitignore| 1 + tests/Android.mk| 1 + tests/Makefile.sources | 1 + tests/kms_nv12.c| 529 tests/kms_render.c | 4 +- 12 files changed, 866 insertions(+), 27 deletions(-) create mode 100644 tests/kms_nv12.c -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/11] drm/i915: Add NV12 to sprite plane programming.
This patch is adding NV12 support to skylake sprite plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.
For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. Once GEM adds support
for seperate remappings for two subplanes, 90/270 support
to be added to plane programming.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_sprite.c | 31 +--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index aa2998f..2a03905 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -201,6 +201,8 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
int x_offset, y_offset;
struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)-config;
int scaler_id;
+ u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ u32 tile_row_adjustment = 0;
plane_ctl = PLANE_CTL_ENABLE |
PLANE_CTL_PIPE_CSC_ENABLE;
@@ -247,24 +249,48 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
plane_size = (src_w 16) | src_h;
x_offset = stride * tile_height - y - (src_h + 1);
y_offset = x;
+
+ /*
+* TBD: For NV12 90/270 rotation, Y and UV subplanes should
+* be treated as separate surfaces and GTT remapping for
+* rotation should be done separately for each subplane.
+* Enable support once seperate remappings are available.
+*/
} else {
stride = fb-pitches[0] / stride_div;
plane_size = (src_h 16) | src_w;
x_offset = x;
y_offset = y;
+ tile_height = PAGE_SIZE / stride_div;
+
+ if (fb-pixel_format == DRM_FORMAT_NV12) {
+ int height_in_mem = (fb-offsets[1]/fb-pitches[0]);
+ /*
+* If UV starts from middle of a page, then UV start
should
+* be programmed to beginning of that page. And offset
into that
+* page to be programmed into y-offset
+*/
+ tile_row_adjustment = height_in_mem % tile_height;
+ aux_dist = fb-pitches[0] * (height_in_mem -
tile_row_adjustment);
+ aux_x_offset = DIV_ROUND_UP(x, 2);
+ aux_y_offset = DIV_ROUND_UP(y, 2) + tile_row_adjustment;
+ /* For tile-Yf, uv-subplane tile width is 2x of
Y-subplane */
+ aux_stride = fb-modifier[0] ==
I915_FORMAT_MOD_Yf_TILED ?
+ stride / 2 : stride;
+ }
}
plane_offset = y_offset 16 | x_offset;
I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
+ I915_WRITE(PLANE_AUX_DIST(pipe, plane), aux_dist | aux_stride);
+ I915_WRITE(PLANE_AUX_OFFSET(pipe, plane), aux_y_offset16 |
aux_x_offset);
/* program plane scaler */
if (scaler_id = 0) {
uint32_t ps_ctrl = 0;
- DRM_DEBUG_KMS(plane = %d PS_PLANE_SEL(plane) = 0x%x\n, plane,
- PS_PLANE_SEL(plane));
ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) |
crtc_state-scaler_state.scalers[scaler_id].mode;
I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
@@ -275,6 +301,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
I915_WRITE(PLANE_POS(pipe, plane), 0);
} else {
+ WARN_ON(fb-pixel_format == DRM_FORMAT_NV12);
I915_WRITE(PLANE_POS(pipe, plane), (crtc_y 16) | crtc_x);
}
--
1.7.9.5
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[Intel-gfx] [PATCH 06/11] drm/i915: Add NV12 as supported format for primary plane
This patch adds NV12 to list of supported formats for
primary plane.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 32 +++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c235a66..d3773d2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -59,7 +59,7 @@ static const uint32_t intel_primary_formats_gen2[] = {
DRM_FORMAT_ARGB1555,
};
-/* Primary plane formats for gen = 4 */
+/* Primary plane formats for gen 4 to 8 */
static const uint32_t intel_primary_formats_gen4[] = {
COMMON_PRIMARY_FORMATS, \
DRM_FORMAT_XBGR,
@@ -70,6 +70,28 @@ static const uint32_t intel_primary_formats_gen4[] = {
DRM_FORMAT_ABGR2101010,
};
+/* Primary plane formats for gen = 9 */
+static const uint32_t intel_primary_formats_gen9[] = {
+ COMMON_PRIMARY_FORMATS, \
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ABGR2101010,
+};
+
+static const uint32_t intel_primary_formats_with_nv12_gen9[] = {
+ COMMON_PRIMARY_FORMATS, \
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ABGR2101010,
+ DRM_FORMAT_NV12,
+};
+
/* Cursor formats */
static const uint32_t intel_cursor_formats[] = {
DRM_FORMAT_ARGB,
@@ -13204,6 +13226,14 @@ static struct drm_plane
*intel_primary_plane_create(struct drm_device *dev,
if (INTEL_INFO(dev)-gen = 3) {
intel_primary_formats = intel_primary_formats_gen2;
num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
+ } else if (INTEL_INFO(dev)-gen = 9) {
+ if (pipe == PIPE_A || pipe == PIPE_B) {
+ intel_primary_formats =
intel_primary_formats_with_nv12_gen9;
+ num_formats =
ARRAY_SIZE(intel_primary_formats_with_nv12_gen9);
+ } else {
+ intel_primary_formats = intel_primary_formats_gen9;
+ num_formats = ARRAY_SIZE(intel_primary_formats_gen9);
+ }
} else {
intel_primary_formats = intel_primary_formats_gen4;
num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
--
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[Intel-gfx] [PATCH 04/11] drm/i915: Update format_is_yuv() to include NV12
This patch adds NV12 to format_is_yuv() function
and made it available for both primary and sprite
planes.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_drv.h|1 +
drivers/gpu/drm/i915/intel_sprite.c |3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8079865..ccf89f8 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1376,6 +1376,7 @@ bool intel_pipe_update_start(struct intel_crtc *crtc,
void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
void intel_post_enable_primary(struct drm_crtc *crtc);
void intel_pre_disable_primary(struct drm_crtc *crtc);
+bool format_is_yuv(uint32_t format);
/* intel_tv.c */
void intel_tv_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 68de97c..5698a07 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -39,7 +39,7 @@
#include drm/i915_drm.h
#include i915_drv.h
-static bool
+bool
format_is_yuv(uint32_t format)
{
switch (format) {
@@ -47,6 +47,7 @@ format_is_yuv(uint32_t format)
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_YVYU:
+ case DRM_FORMAT_NV12:
return true;
default:
return false;
--
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[Intel-gfx] [PATCH 10/11] drm/i915: Add NV12 to primary plane programming.
This patch is adding NV12 support to skylake primary plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.
For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. Once GEM adds support
for seperate remappings for two subplanes, 90/270 support
to be added to plane programming.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_atomic_plane.c |2 ++
drivers/gpu/drm/i915/intel_display.c | 39 +
2 files changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index a27ee8c..84cd9fc 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -173,10 +173,12 @@ static int intel_plane_atomic_check(struct drm_plane
*plane,
* 90/270 is not allowed with RGB64 16:16:16:16,
* RGB 16-bit 5:6:5, and Indexed 8-bit.
* TBD: Add RGB64 case once its added in supported format list.
+* TBD: Remove NV12, once its 90/270 remapping is supported
*/
switch (state-fb-pixel_format) {
case DRM_FORMAT_C8:
case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_NV12:
DRM_DEBUG_KMS(Unsupported pixel format %s for
90/270!\n,
drm_get_format_name(state-fb-pixel_format));
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e747766..c9d5cc9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3026,6 +3026,9 @@ u32 skl_plane_ctl_format(uint32_t pixel_format)
case DRM_FORMAT_VYUY:
plane_ctl_format = PLANE_CTL_FORMAT_YUV422 |
PLANE_CTL_YUV422_VYUY;
break;
+ case DRM_FORMAT_NV12:
+ plane_ctl_format = PLANE_CTL_FORMAT_NV12;
+ break;
default:
BUG();
}
@@ -3095,6 +3098,8 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
int scaler_id = -1;
+ u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+ u32 tile_row_adjustment = 0;
plane = crtc-primary;
plane_state = to_intel_plane_state(plane-state);
@@ -3152,11 +3157,35 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
x_offset = stride * tile_height - y - src_h;
y_offset = x;
plane_size = (src_w - 1) 16 | (src_h - 1);
+ /*
+* TBD: For NV12 90/270 rotation, Y and UV subplanes should
+* be treated as separate surfaces and GTT remapping for
+* rotation should be done separately for each subplane.
+* Enable support once seperate remappings are available.
+*/
} else {
stride = fb-pitches[0] / stride_div;
x_offset = x;
y_offset = y;
plane_size = (src_h - 1) 16 | (src_w - 1);
+ tile_height = PAGE_SIZE / stride_div;
+
+ if (fb-pixel_format == DRM_FORMAT_NV12) {
+ int height_in_mem = (fb-offsets[1]/fb-pitches[0]);
+ /*
+* If UV starts from middle of a page, then UV start
should
+* be programmed to beginning of that page. And offset
into that
+* page to be programmed into y-offset
+*/
+ tile_row_adjustment = height_in_mem % tile_height;
+ aux_dist = fb-pitches[0] * (height_in_mem -
tile_row_adjustment);
+ aux_x_offset = DIV_ROUND_UP(plane_state-src.x1, 2);
+ aux_y_offset = DIV_ROUND_UP(plane_state-src.y1, 2) +
+ tile_row_adjustment;
+ /* For tile-Yf, uv-subplane tile width is 2x of
Y-subplane */
+ aux_stride = fb-modifier[0] ==
I915_FORMAT_MOD_Yf_TILED ?
+ stride / 2 : stride;
+ }
}
plane_offset = y_offset 16 | x_offset;
@@ -3164,11 +3193,14 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
+ I915_WRITE(PLANE_AUX_DIST(pipe, 0), aux_dist | aux_stride);
+ I915_WRITE(PLANE_AUX_OFFSET(pipe, 0), aux_y_offset 16 |
aux_x_offset);
if (scaler_id = 0
[Intel-gfx] [PATCH 07/11] drm/i915: Add NV12 as supported format for sprite plane
This patch adds NV12 to list of supported formats for
sprite plane.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_sprite.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 59846f8..aa2998f 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1207,6 +1207,19 @@ static uint32_t skl_plane_formats[] = {
DRM_FORMAT_VYUY,
};
+static uint32_t skl_plane_formats_with_nv12[] = {
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+};
+
int
intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
{
@@ -1278,8 +1291,14 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe,
int plane)
intel_plane-disable_plane = skl_disable_plane;
state-scaler_id = -1;
- plane_formats = skl_plane_formats;
- num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+ if ((pipe == PIPE_A || pipe == PIPE_B) (plane == 0)) {
+ plane_formats = skl_plane_formats_with_nv12;
+ num_plane_formats =
ARRAY_SIZE(skl_plane_formats_with_nv12);
+ } else {
+ plane_formats = skl_plane_formats;
+ num_plane_formats = ARRAY_SIZE(skl_plane_formats) - 1;
+ }
+
break;
default:
kfree(intel_plane);
--
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[Intel-gfx] [PATCH 00/11] Skylake display NV12 feature addition
This patch series adding NV12 support for Skylake display. Feature is tested with igt/kms_nv12 testcase. I will be sending the igt patches shortly. Feature is unit tested for linear/X/Y/Yf formats in 0 and 180 orientations with combinations of 1, 2 or 3 planes enabled along with scaling. Also negatively tested for enabling NV12 on unsupported plane. Chandra Konduru (11): drm/i915: Add register definitions for NV12 support drm/i915: Set scaler mode for NV12 drm/i915: Stage scaler request for NV12 as src format drm/i915: Update format_is_yuv() to include NV12 drm/i915: Upscale scaler max scale for NV12. drm/i915: Add NV12 as supported format for primary plane drm/i915: Add NV12 as supported format for sprite plane drm/i915: Add NV12 support to intel_framebuffer_init drm/i915: Update compute_baseline_bpp for NV12. drm/i915: Add NV12 to primary plane programming. drm/i915: Add NV12 to sprite plane programming. drivers/gpu/drm/i915/i915_reg.h | 27 +++ drivers/gpu/drm/i915/intel_atomic.c |5 +- drivers/gpu/drm/i915/intel_atomic_plane.c |2 + drivers/gpu/drm/i915/intel_display.c | 120 +++-- drivers/gpu/drm/i915/intel_drv.h |4 +- drivers/gpu/drm/i915/intel_sprite.c | 59 -- 6 files changed, 201 insertions(+), 16 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/11] drm/i915: Add register definitions for NV12 support
This patch adds register definitions for skylake
display NV12 support.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index aa2a0de..504d967 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5121,6 +5121,7 @@ enum skl_disp_power_wells {
#define PS_SCALER_MODE_MASK (3 28)
#define PS_SCALER_MODE_DYN (0 28)
#define PS_SCALER_MODE_HQ (1 28)
+#define PS_SCALER_MODE_NV12 (2 28)
#define PS_PLANE_SEL_MASK (7 25)
#define PS_PLANE_SEL(plane) ((plane + 1) 25)
#define PS_FILTER_MASK (3 23)
@@ -5224,6 +5225,32 @@ enum skl_disp_power_wells {
_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)
+
+/*
+ * Skylake NV12 Register
+ */
+#define PLANE_AUX_DIST_1_A 0x701c0
+#define PLANE_AUX_DIST_2_A 0x702c0
+#define PLANE_AUX_DIST_1_B 0x711c0
+#define PLANE_AUX_DIST_2_B 0x712c0
+#define _PLANE_AUX_DIST_1(pipe)\
+ _PIPE(pipe, PLANE_AUX_DIST_1_A, PLANE_AUX_DIST_1_B)
+#define _PLANE_AUX_DIST_2(pipe)\
+ _PIPE(pipe, PLANE_AUX_DIST_2_A, PLANE_AUX_DIST_2_B)
+#define PLANE_AUX_DIST(pipe, plane)\
+ _PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
+
+#define PLANE_AUX_OFFSET_1_A 0x701c4
+#define PLANE_AUX_OFFSET_2_A 0x702c4
+#define PLANE_AUX_OFFSET_1_B 0x711c4
+#define PLANE_AUX_OFFSET_2_B 0x712c4
+#define _PLANE_AUX_OFFSET_1(pipe) \
+ _PIPE(pipe, PLANE_AUX_OFFSET_1_A, PLANE_AUX_OFFSET_1_B)
+#define _PLANE_AUX_OFFSET_2(pipe) \
+ _PIPE(pipe, PLANE_AUX_OFFSET_2_A, PLANE_AUX_OFFSET_2_B)
+#define PLANE_AUX_OFFSET(pipe, plane) \
+ _PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
+
/* legacy palette */
#define _LGC_PALETTE_A 0x4a000
#define _LGC_PALETTE_B 0x4a800
--
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[Intel-gfx] [PATCH 08/11] drm/i915: Add NV12 support to intel_framebuffer_init
This patch adds NV12 as supported format to
intel_framebuffer_init and performs various checks.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d3773d2..6e693c4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13953,6 +13953,33 @@ static int intel_framebuffer_init(struct drm_device
*dev,
return -EINVAL;
}
break;
+ case DRM_FORMAT_NV12:
+ if (INTEL_INFO(dev)-gen 9) {
+ DRM_DEBUG(unsupported pixel format: %s\n,
+ drm_get_format_name(mode_cmd-pixel_format));
+ return -EINVAL;
+ }
+ if (!mode_cmd-offsets[1]) {
+ DRM_DEBUG(uv start offset not set\n);
+ return -EINVAL;
+ }
+ if (mode_cmd-pitches[0] != mode_cmd-pitches[1] ||
+ mode_cmd-handles[0] != mode_cmd-handles[1]) {
+ DRM_DEBUG(y and uv subplanes have different
parameters\n);
+ return -EINVAL;
+ }
+ if (mode_cmd-modifier[1] == I915_FORMAT_MOD_Yf_TILED
+ (mode_cmd-offsets[1] 0xFFF)) {
+ DRM_DEBUG(tile-Yf uv offset 0x%x isn't starting on new
tile-row\n,
+ mode_cmd-offsets[1]);
+ return -EINVAL;
+ }
+ if (mode_cmd-modifier[1] == I915_FORMAT_MOD_Y_TILED
+ ((mode_cmd-offsets[1] % mode_cmd-pitches[1]) % 4)) {
+ DRM_DEBUG(tile-Y uv offset 0x%x isn't 4-line
aligned\n,
+ mode_cmd-offsets[1]);
+ }
+ break;
default:
DRM_DEBUG(unsupported pixel format: %s\n,
drm_get_format_name(mode_cmd-pixel_format));
--
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