Re: [PATCH 07/11] drm/gma500: Use fbdev client helpers
On Tue, May 7, 2024 at 2:04 PM Thomas Zimmermann wrote:
>
> Implement struct drm_client_funcs with the respective helpers and
> remove the custom code from the emulation. The generic helpers are
> equivalent in functionality.
>
> Signed-off-by: Thomas Zimmermann
Acked-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/gma500/fbdev.c | 58 ++
> 1 file changed, 3 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/gpu/drm/gma500/fbdev.c b/drivers/gpu/drm/gma500/fbdev.c
> index 98b44974d42dd..8a6cb47e83f8f 100644
> --- a/drivers/gpu/drm/gma500/fbdev.c
> +++ b/drivers/gpu/drm/gma500/fbdev.c
> @@ -8,7 +8,6 @@
> #include
> #include
>
> -#include
> #include
> #include
> #include
> @@ -252,63 +251,12 @@ static const struct drm_fb_helper_funcs
> psb_fbdev_fb_helper_funcs = {
> };
>
> /*
> - * struct drm_client_funcs and setup code
> + * struct drm_client_funcs
> */
>
> -static void psb_fbdev_client_unregister(struct drm_client_dev *client)
> -{
> - struct drm_fb_helper *fb_helper = drm_fb_helper_from_client(client);
> -
> - if (fb_helper->info) {
> - drm_fb_helper_unregister_info(fb_helper);
> - } else {
> - drm_fb_helper_unprepare(fb_helper);
> - drm_client_release(&fb_helper->client);
> - kfree(fb_helper);
> - }
> -}
> -
> -static int psb_fbdev_client_restore(struct drm_client_dev *client)
> -{
> - drm_fb_helper_lastclose(client->dev);
> -
> - return 0;
> -}
> -
> -static int psb_fbdev_client_hotplug(struct drm_client_dev *client)
> -{
> - struct drm_fb_helper *fb_helper = drm_fb_helper_from_client(client);
> - struct drm_device *dev = client->dev;
> - int ret;
> -
> - if (dev->fb_helper)
> - return drm_fb_helper_hotplug_event(dev->fb_helper);
> -
> - ret = drm_fb_helper_init(dev, fb_helper);
> - if (ret)
> - goto err_drm_err;
> -
> - if (!drm_drv_uses_atomic_modeset(dev))
> - drm_helper_disable_unused_functions(dev);
> -
> - ret = drm_fb_helper_initial_config(fb_helper);
> - if (ret)
> - goto err_drm_fb_helper_fini;
> -
> - return 0;
> -
> -err_drm_fb_helper_fini:
> - drm_fb_helper_fini(fb_helper);
> -err_drm_err:
> - drm_err(dev, "Failed to setup gma500 fbdev emulation (ret=%d)\n",
> ret);
> - return ret;
> -}
> -
> static const struct drm_client_funcs psb_fbdev_client_funcs = {
> - .owner = THIS_MODULE,
> - .unregister = psb_fbdev_client_unregister,
> - .restore= psb_fbdev_client_restore,
> - .hotplug= psb_fbdev_client_hotplug,
> + .owner = THIS_MODULE,
> + DRM_FBDEV_HELPER_CLIENT_FUNCS,
> };
>
> void psb_fbdev_setup(struct drm_psb_private *dev_priv)
> --
> 2.44.0
>
Re: [Intel-gfx] [PATCH 1/8] drm/gma500: Use drm_aperture_remove_conflicting_pci_framebuffers
On Thu, Apr 6, 2023 at 9:32 AM Daniel Vetter wrote:
>
> On Wed, 5 Apr 2023 at 19:46, Patrik Jakobsson
> wrote:
> >
> > On Wed, Apr 5, 2023 at 7:15 PM Daniel Vetter wrote:
> > >
> > > On Wed, 5 Apr 2023 at 18:54, Javier Martinez Canillas
> > > wrote:
> > > >
> > > > Daniel Vetter writes:
> > > >
> > > > > On Wed, Apr 05, 2023 at 04:32:19PM +0200, Thomas Zimmermann wrote:
> > > >
> > > > [...]
> > > >
> > > > >> > > >/*
> > > > >> > > > * WARNING: Apparently we must kick fbdev drivers
> > > > >> > > > before vgacon,
> > > > >> > > > * otherwise the vga fbdev driver falls over.
> > > > >> > > > */
> > > > >> > > >ret = vga_remove_vgacon(pdev);
> > > > >> >
> > > > >> > This isn't enough, we also nuke stuff that's mapping the vga fb
> > > > >> > range.
> > > >
> > > > Ah, also need aperture_detach_devices(VGA_FB_PHYS_BASE,
> > > > VGA_FB_PHYS_SIZE) then.
> > > >
> > > > [...]
> > > >
> > > > >> int aperture_remove_legacy_vga_devices(struct pci_dev *pdev)
> > > > >> {
> > > > >> aperture_detach_devices(VGA_FB_PHYS_BASE, VGA_FB_PHYS_SIZE);
> > > > >>
> > > > >> return vga_remove_vgacon(pdev);
> > > > >> }
> > > > >>
> > > > >> And that can be called from gma500 and the pci aperture helper.
> > > > >
> > > > > But you still pass a pci_dev to that helper. Which just doesn't make
> > > > > any
> > > > > sense to me (assuming your entire point is that this isn't just a
> > > > > normal
> > > > > pci device but some special legacy vga thing), but if we go with
> > > > > (void)
> > > > > then there's more refactoring to do because the vga_remove_vgacon also
> > > > > wants a pdev.
> > > > >
> > > > > All so that we don't call aperture_detach_devices() on a bunch of pci
> > > > > bars, which apparently is not problem for any other driver, but
> > > > > absolutely
> > > > > is a huge problem for gma500 somehow.
> > > > >
> > > > > I don't understand why.
> > > > >
> > > >
> > > > Yeah, agreed that if vga_remove_vgacon() isn't enough and another helper
> > > > is needed then starts to get a little silly. Maybe one option is to add
> > > > a
> > > > 3rd param to aperture_remove_conflicting_pci_devices() and skip the
> > > > logic
> > > > to iterate over PCI bars and call aperture_remove_conflicting_devices()
> > > > ?
> > >
> > > The thing I don't get: Why does this matter for gma500 and not any of
> > > the other pci devices? Look at your gpu, realize there's a lot more
> > > than the one pci bar for vram or stolen memory, realize that we're
> > > nuking bars that cannot possible contain the framebuffer for everyone
> > > else too. Like the entire "gpus have a lot of bars" thing is the
> > > reason why I pulled the sysfb_disable one level up, because we've been
> > > doing that quite a few times before this patch (yes it's not the main
> > > thing, but the side-effect cleanup is why I've gone down this rabbit
> > > hole and wrote the entire series here):
> > >
> > > https://lore.kernel.org/dri-devel/20230404201842.567344-7-daniel.vet...@ffwll.ch/
> > >
> > > But somehow for gma500 it's a problem, while for everyone else it's
> > > fine. That's the part I dont get, or Thomas&me have been talking past
> > > each another and there's another issue that I'm missing.
> > > -Daniel
> >
> > I'm also getting confused here.
> >
> > AFAIK the stolen memory works the same for gma500 hardware as other
> > Intel GPUs. Are you saying that there is a difference in how gma500
> > hardware works? I always assumed that i915 got away with not dealing
> > much with stolen memory because it simply doesn't use it for
> > allocations. In gma500 we use it for fbdev and cursors. The actual
> > pages reserved by the bios can be accessed thr
Re: [Intel-gfx] [PATCH 1/8] drm/gma500: Use drm_aperture_remove_conflicting_pci_framebuffers
On Wed, Apr 5, 2023 at 7:15 PM Daniel Vetter wrote:
>
> On Wed, 5 Apr 2023 at 18:54, Javier Martinez Canillas
> wrote:
> >
> > Daniel Vetter writes:
> >
> > > On Wed, Apr 05, 2023 at 04:32:19PM +0200, Thomas Zimmermann wrote:
> >
> > [...]
> >
> > >> > > >/*
> > >> > > > * WARNING: Apparently we must kick fbdev drivers before
> > >> > > > vgacon,
> > >> > > > * otherwise the vga fbdev driver falls over.
> > >> > > > */
> > >> > > >ret = vga_remove_vgacon(pdev);
> > >> >
> > >> > This isn't enough, we also nuke stuff that's mapping the vga fb range.
> >
> > Ah, also need aperture_detach_devices(VGA_FB_PHYS_BASE, VGA_FB_PHYS_SIZE)
> > then.
> >
> > [...]
> >
> > >> int aperture_remove_legacy_vga_devices(struct pci_dev *pdev)
> > >> {
> > >> aperture_detach_devices(VGA_FB_PHYS_BASE, VGA_FB_PHYS_SIZE);
> > >>
> > >> return vga_remove_vgacon(pdev);
> > >> }
> > >>
> > >> And that can be called from gma500 and the pci aperture helper.
> > >
> > > But you still pass a pci_dev to that helper. Which just doesn't make any
> > > sense to me (assuming your entire point is that this isn't just a normal
> > > pci device but some special legacy vga thing), but if we go with (void)
> > > then there's more refactoring to do because the vga_remove_vgacon also
> > > wants a pdev.
> > >
> > > All so that we don't call aperture_detach_devices() on a bunch of pci
> > > bars, which apparently is not problem for any other driver, but absolutely
> > > is a huge problem for gma500 somehow.
> > >
> > > I don't understand why.
> > >
> >
> > Yeah, agreed that if vga_remove_vgacon() isn't enough and another helper
> > is needed then starts to get a little silly. Maybe one option is to add a
> > 3rd param to aperture_remove_conflicting_pci_devices() and skip the logic
> > to iterate over PCI bars and call aperture_remove_conflicting_devices() ?
>
> The thing I don't get: Why does this matter for gma500 and not any of
> the other pci devices? Look at your gpu, realize there's a lot more
> than the one pci bar for vram or stolen memory, realize that we're
> nuking bars that cannot possible contain the framebuffer for everyone
> else too. Like the entire "gpus have a lot of bars" thing is the
> reason why I pulled the sysfb_disable one level up, because we've been
> doing that quite a few times before this patch (yes it's not the main
> thing, but the side-effect cleanup is why I've gone down this rabbit
> hole and wrote the entire series here):
>
> https://lore.kernel.org/dri-devel/20230404201842.567344-7-daniel.vet...@ffwll.ch/
>
> But somehow for gma500 it's a problem, while for everyone else it's
> fine. That's the part I dont get, or Thomas&me have been talking past
> each another and there's another issue that I'm missing.
> -Daniel
I'm also getting confused here.
AFAIK the stolen memory works the same for gma500 hardware as other
Intel GPUs. Are you saying that there is a difference in how gma500
hardware works? I always assumed that i915 got away with not dealing
much with stolen memory because it simply doesn't use it for
allocations. In gma500 we use it for fbdev and cursors. The actual
pages reserved by the bios can be accessed through a pci bar if you
map it so (which IIRC we do) but I suppose that doesn't help
identifying it as a range reserved by other drivers.
The reason I've kept the stolen allocation logic is because some
gma500 systems don't have a lot of memory. But that is mostly the old
Pouslbo systems. Perhaps it is time to ditch the stolen allocation
code?
-Patrik
>
> > > Consider this me throwing in the towel. If you&Javier are convinced this
> > > makes sense please type it up and merge it, but I'm not going to type
> > > something that just doesn't make sense to me.
> >
> > Honestly, I would just go with the double drm_aperture_remove_*() helper
> > calls (your original patch) unless that causes real issues. There is no
> > point on blocking all your series just for this IMO.
> >
> > Then latter if Thomas has strong opinions can send a follow-up patch for
> > the gma500 driver and the aperture helpers.
> >
> > > -Daniel
> > >
> >
> > --
> > Best regards,
> >
> > Javier Martinez Canillas
> > Core Platforms
> > Red Hat
> >
>
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
Re: [Intel-gfx] [PATCH 1/8] drm/gma500: Use drm_aperture_remove_conflicting_pci_framebuffers
On Wed, Apr 5, 2023 at 9:49 AM Thomas Zimmermann wrote: > > Hi > > Am 04.04.23 um 22:18 schrieb Daniel Vetter: > > This one nukes all framebuffers, which is a bit much. In reality > > gma500 is igpu and never shipped with anything discrete, so there should > > not be any difference. > > > > v2: Unfortunately the framebuffer sits outside of the pci bars for > > gma500, and so only using the pci helpers won't be enough. Otoh if we > > only use non-pci helper, then we don't get the vga handling, and > > subsequent refactoring to untangle these special cases won't work. > > > > It's not pretty, but the simplest fix (since gma500 really is the only > > quirky pci driver like this we have) is to just have both calls. > > > > Signed-off-by: Daniel Vetter > > Cc: Patrik Jakobsson > > Cc: Thomas Zimmermann > > Cc: Javier Martinez Canillas > > --- > > drivers/gpu/drm/gma500/psb_drv.c | 9 +++-- > > 1 file changed, 7 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/gma500/psb_drv.c > > b/drivers/gpu/drm/gma500/psb_drv.c > > index 2ce96b1b9c74..f1e0eed8fea4 100644 > > --- a/drivers/gpu/drm/gma500/psb_drv.c > > +++ b/drivers/gpu/drm/gma500/psb_drv.c > > @@ -422,12 +422,17 @@ static int psb_pci_probe(struct pci_dev *pdev, const > > struct pci_device_id *ent) > > > > /* > >* We cannot yet easily find the framebuffer's location in memory. So > > - * remove all framebuffers here. > > + * remove all framebuffers here. Note that we still want the pci > > special > > + * handling to kick out vgacon. > >* > >* TODO: Refactor psb_driver_load() to map vdc_reg earlier. Then we > >* might be able to read the framebuffer range from the device. > >*/ > > - ret = drm_aperture_remove_framebuffers(true, &driver); > > + ret = drm_aperture_remove_framebuffers(false, &driver); > > + if (ret) > > + return ret; > > + > > + ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &driver); > > This simply isn't it. If you have to work around your own API, it's time > to rethink the API. Would it help if we figure out the stolen range here? It can supposedly be found by reading pci config space, so no need to map vdc regs first. GBSM is the stolen base and TOLUD - GBSM = stolen size. Or read the size out from GGC. Not sure which one is more reliable. -Patrik > > Best regards > Thomas > > > if (ret) > > return ret; > > > > -- > Thomas Zimmermann > Graphics Driver Developer > SUSE Software Solutions Germany GmbH > Maxfeldstr. 5, 90409 Nürnberg, Germany > (HRB 36809, AG Nürnberg) > Geschäftsführer: Ivo Totev
Re: [Intel-gfx] [PATCH 07/22] drm/gma500: Use drm_mode_copy()
On Fri, Feb 18, 2022 at 11:04 AM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> struct drm_display_mode embeds a list head, so overwriting
> the full struct with another one will corrupt the list
> (if the destination mode is on a list). Use drm_mode_copy()
> instead which explicitly preserves the list head of
> the destination mode.
>
> Even if we know the destination mode is not on any list
> using drm_mode_copy() seems decent as it sets a good
> example. Bad examples of not using it might eventually
> get copied into code where preserving the list head
> actually matters.
>
> Obviously one case not covered here is when the mode
> itself is embedded in a larger structure and the whole
> structure is copied. But if we are careful when copying
> into modes embedded in structures I think we can be a
> little more reassured that bogus list heads haven't been
> propagated in.
>
> @is_mode_copy@
> @@
> drm_mode_copy(...)
> {
> ...
> }
>
> @depends on !is_mode_copy@
> struct drm_display_mode *mode;
> expression E, S;
> @@
> (
> - *mode = E
> + drm_mode_copy(mode, &E)
> |
> - memcpy(mode, E, S)
> + drm_mode_copy(mode, E)
> )
>
> @depends on !is_mode_copy@
> struct drm_display_mode mode;
> expression E;
> @@
> (
> - mode = E
> + drm_mode_copy(&mode, &E)
> |
> - memcpy(&mode, E, S)
> + drm_mode_copy(&mode, E)
> )
>
> @@
> struct drm_display_mode *mode;
> @@
> - &*mode
> + mode
>
> Cc: Patrik Jakobsson
> Signed-off-by: Ville Syrjälä
Looks good. Thanks!
Acked-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/gma500/oaktrail_crtc.c | 8 ++--
> 1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/gma500/oaktrail_crtc.c
> b/drivers/gpu/drm/gma500/oaktrail_crtc.c
> index 36c7c2686c90..79fc602b35bc 100644
> --- a/drivers/gpu/drm/gma500/oaktrail_crtc.c
> +++ b/drivers/gpu/drm/gma500/oaktrail_crtc.c
> @@ -385,12 +385,8 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc,
> if (!gma_power_begin(dev, true))
> return 0;
>
> - memcpy(&gma_crtc->saved_mode,
> - mode,
> - sizeof(struct drm_display_mode));
> - memcpy(&gma_crtc->saved_adjusted_mode,
> - adjusted_mode,
> - sizeof(struct drm_display_mode));
> + drm_mode_copy(&gma_crtc->saved_mode, mode);
> + drm_mode_copy(&gma_crtc->saved_adjusted_mode, adjusted_mode);
>
> list_for_each_entry(connector, &mode_config->connector_list, head) {
> if (!connector->encoder || connector->encoder->crtc != crtc)
> --
> 2.34.1
>
Re: [Intel-gfx] linux-next: manual merge of the drivers-x86 tree with the drm-misc tree
On Fri, Feb 5, 2021 at 12:07 PM Andy Shevchenko wrote: > > On Thu, Feb 4, 2021 at 11:04 AM Andy Shevchenko > wrote: > >> Today's linux-next merge of the drivers-x86 tree got a conflict in: > > > > Thanks. I already asked Patrik yesterday day if DRM missed to pull an > > immutable tag I provided. I think they can pull and resolve conflicts > > themselves. Alternatively it would be easy to resolve by Linus by removing > > Kconfig lines along with mentioned files, > > Patrik, I have sent a PR again, so you may consider pulling it, thanks! Daniel, is this something you can pull into drm or ask one of the drm-misc maintainers to do? ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v1 1/2] drm/gma500: Convert to use new SCU IPC API
On Fri, Jan 22, 2021 at 3:51 PM Andy Shevchenko wrote: > > On Fri, Jan 22, 2021 at 03:16:55PM +0100, Patrik Jakobsson wrote: > > On Fri, Jan 22, 2021 at 12:39 PM Andy Shevchenko > > wrote: > > > > > > Convert the GMA500 driver to use the new SCU IPC API. This allows us > > > to get rid of the duplicate PMC IPC implementation which is now covered > > > in SCU IPC driver. > > > > > > Signed-off-by: Andy Shevchenko > > > Acked-by: Linus Walleij > > > > Both patches look good. Do you want me to take them through drm-misc? > > Otherwise: > > Acked-by: Patrik Jakobsson > > I guess it's fine to go via drm-misc, but we might need an immutable > branch/tag > in the future (in case the rest cleanups that are dependent but have not sent > yet will pending v5.12). Right, so you need this included before you remove the duplicate PMC IPC implementation? Then I think it's better you take the patches through whatever tree the PMC IPC changes go. You have my ack. -Patrik ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v1 1/2] drm/gma500: Convert to use new SCU IPC API
On Fri, Jan 22, 2021 at 12:39 PM Andy Shevchenko wrote: > > Convert the GMA500 driver to use the new SCU IPC API. This allows us > to get rid of the duplicate PMC IPC implementation which is now covered > in SCU IPC driver. > > Signed-off-by: Andy Shevchenko > Acked-by: Linus Walleij Both patches look good. Do you want me to take them through drm-misc? Otherwise: Acked-by: Patrik Jakobsson ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 06/22] drm/gma500: Convert to CRTC VBLANK callbacks
On Mon, Jan 20, 2020 at 9:23 AM Thomas Zimmermann wrote:
>
> VBLANK callbacks in struct drm_driver are deprecated in favor of
> their equivalents in struct drm_crtc_funcs. Convert gma500 over.
>
> Signed-off-by: Thomas Zimmermann
Looks good. For this patch:
Acked-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/gma500/cdv_intel_display.c | 3 +++
> drivers/gpu/drm/gma500/psb_drv.c | 4
> drivers/gpu/drm/gma500/psb_drv.h | 6 +++---
> drivers/gpu/drm/gma500/psb_intel_display.c | 3 +++
> drivers/gpu/drm/gma500/psb_irq.c | 12 +---
> drivers/gpu/drm/gma500/psb_irq.h | 7 ---
> 6 files changed, 22 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/gma500/cdv_intel_display.c
> b/drivers/gpu/drm/gma500/cdv_intel_display.c
> index 1ed854f498b7..686385a66167 100644
> --- a/drivers/gpu/drm/gma500/cdv_intel_display.c
> +++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
> @@ -977,6 +977,9 @@ const struct drm_crtc_funcs cdv_intel_crtc_funcs = {
> .set_config = gma_crtc_set_config,
> .destroy = gma_crtc_destroy,
> .page_flip = gma_crtc_page_flip,
> + .enable_vblank = psb_enable_vblank,
> + .disable_vblank = psb_disable_vblank,
> + .get_vblank_counter = psb_get_vblank_counter,
> };
>
> const struct gma_clock_funcs cdv_clock_funcs = {
> diff --git a/drivers/gpu/drm/gma500/psb_drv.c
> b/drivers/gpu/drm/gma500/psb_drv.c
> index 52591416f8fe..36cb292fdebe 100644
> --- a/drivers/gpu/drm/gma500/psb_drv.c
> +++ b/drivers/gpu/drm/gma500/psb_drv.c
> @@ -363,7 +363,6 @@ static int psb_driver_load(struct drm_device *dev,
> unsigned long flags)
> drm_irq_install(dev, dev->pdev->irq);
>
> dev->max_vblank_count = 0xff; /* only 24 bits of frame count */
> - dev->driver->get_vblank_counter = psb_get_vblank_counter;
>
> psb_modeset_init(dev);
> psb_fbdev_init(dev);
> @@ -507,9 +506,6 @@ static struct drm_driver driver = {
> .irq_postinstall = psb_irq_postinstall,
> .irq_uninstall = psb_irq_uninstall,
> .irq_handler = psb_irq_handler,
> - .enable_vblank = psb_enable_vblank,
> - .disable_vblank = psb_disable_vblank,
> - .get_vblank_counter = psb_get_vblank_counter,
>
> .gem_free_object = psb_gem_free_object,
> .gem_vm_ops = &psb_gem_vm_ops,
> diff --git a/drivers/gpu/drm/gma500/psb_drv.h
> b/drivers/gpu/drm/gma500/psb_drv.h
> index 3d4ef3071d45..956926341316 100644
> --- a/drivers/gpu/drm/gma500/psb_drv.h
> +++ b/drivers/gpu/drm/gma500/psb_drv.h
> @@ -681,15 +681,15 @@ extern void psb_irq_turn_off_dpst(struct drm_device
> *dev);
> extern void psb_irq_uninstall_islands(struct drm_device *dev, int
> hw_islands);
> extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
> extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
> -extern int psb_enable_vblank(struct drm_device *dev, unsigned int pipe);
> -extern void psb_disable_vblank(struct drm_device *dev, unsigned int pipe);
> +extern int psb_enable_vblank(struct drm_crtc *crtc);
> +extern void psb_disable_vblank(struct drm_crtc *crtc);
> void
> psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
>
> void
> psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
>
> -extern u32 psb_get_vblank_counter(struct drm_device *dev, unsigned int pipe);
> +extern u32 psb_get_vblank_counter(struct drm_crtc *crtc);
>
> /* framebuffer.c */
> extern int psbfb_probed(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/gma500/psb_intel_display.c
> b/drivers/gpu/drm/gma500/psb_intel_display.c
> index fed3b563e62e..531c5485be17 100644
> --- a/drivers/gpu/drm/gma500/psb_intel_display.c
> +++ b/drivers/gpu/drm/gma500/psb_intel_display.c
> @@ -433,6 +433,9 @@ const struct drm_crtc_funcs psb_intel_crtc_funcs = {
> .set_config = gma_crtc_set_config,
> .destroy = gma_crtc_destroy,
> .page_flip = gma_crtc_page_flip,
> + .enable_vblank = psb_enable_vblank,
> + .disable_vblank = psb_disable_vblank,
> + .get_vblank_counter = psb_get_vblank_counter,
> };
>
> const struct gma_clock_funcs psb_clock_funcs = {
> diff --git a/drivers/gpu/drm/gma500/psb_irq.c
> b/drivers/gpu/drm/gma500/psb_irq.c
> index 91f90016dba9..15eb3770d817 100644
> --- a/drivers/gpu/drm/gma500/psb_irq.c
> +++ b/drivers/gpu/drm/gma500/psb_irq.c
> @@ -506,8 +506,10 @@ int psb_irq_disable_dpst(struct drm_device *dev)
> /*
> * It is used to enable VBLANK interrupt
> */
> -int psb_enable_vblank(struct drm_device *dev, unsigned int pipe)
> +int psb_enable_vbl
Re: [Intel-gfx] [PATCH v3 0/5] drm/gma500: drop use of drmP.h
On Sat, May 25, 2019 at 10:43 PM Sam Ravnborg wrote: > > Just a quick (final) probe. If there are no further feedback I will > commit this set sunday. > Added intel-gfx@lists.freedesktop.org just to get a bit more coverage. Hi Sam v2 of this series is already applied to drm-misc-next Thanks Patrik > > > The following patchset remove use of the deprecated drmP.h > header file in the gma500 driver. > > As preparation an empty header file is removed and a dependency on > drm_os_linux.h is dropped. > The local header files are made more self-contained to allow > them to be included in alphabetical order in the files where they are used. > > When removing drmP.h the include files are divided up in blocks: > \#include > > \#include > > \#include > > \#include "" > > Within each block the include files are sorted alphabetically > > Build tested with allmodconfig and allyesconfig for x86, arm, alpha and more. > > Patchset made on top of drm-misc-next > > v2: > - Be consitent in dividing includes files into blocks > - Sort all include files, not only the blocks touched > - Made local header files more self-contained > To allow them to be included in alphabetically order > > v3: > - Collect acks from Daniel and Patrik > > Sam > > Sam Ravnborg (5): > drm/gma500: remove empty gma_drm.h header file > drm/gma500: drop drmP.h from header files > drm/gma500: make local header files more self-contained > drm/gma500: drop use of DRM_UDELAY wrapper > drm/gma500: drop drmp.h include from all .c files > > > drivers/gpu/drm/gma500/accel_2d.c | 18 +++ > drivers/gpu/drm/gma500/blitter.h | 2 ++ > drivers/gpu/drm/gma500/cdv_device.c | 13 ++- > drivers/gpu/drm/gma500/cdv_device.h | 4 > drivers/gpu/drm/gma500/cdv_intel_crt.c| 8 +++ > drivers/gpu/drm/gma500/cdv_intel_display.c| 10 > drivers/gpu/drm/gma500/cdv_intel_dp.c | 9 > drivers/gpu/drm/gma500/cdv_intel_hdmi.c | 9 > drivers/gpu/drm/gma500/cdv_intel_lvds.c | 9 > drivers/gpu/drm/gma500/framebuffer.c | 24 +-- > drivers/gpu/drm/gma500/framebuffer.h | 1 - > drivers/gpu/drm/gma500/gem.c | 5 ++-- > drivers/gpu/drm/gma500/gma_device.c | 1 - > drivers/gpu/drm/gma500/gma_device.h | 1 + > drivers/gpu/drm/gma500/gma_display.c | 12 +++--- > drivers/gpu/drm/gma500/gma_display.h | 3 +++ > drivers/gpu/drm/gma500/gtt.c | 5 ++-- > drivers/gpu/drm/gma500/gtt.h | 1 - > drivers/gpu/drm/gma500/intel_bios.c | 6 ++--- > drivers/gpu/drm/gma500/intel_bios.h | 3 +-- > drivers/gpu/drm/gma500/intel_gmbus.c | 11 + > drivers/gpu/drm/gma500/intel_i2c.c| 4 +++- > drivers/gpu/drm/gma500/mdfld_device.c | 16 +++-- > drivers/gpu/drm/gma500/mdfld_dsi_dpi.c| 4 +++- > drivers/gpu/drm/gma500/mdfld_dsi_output.c | 12 ++ > drivers/gpu/drm/gma500/mdfld_dsi_output.h | 8 +++ > drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c | 4 +++- > drivers/gpu/drm/gma500/mdfld_intel_display.c | 11 + > drivers/gpu/drm/gma500/mdfld_tmd_vid.c| 2 ++ > drivers/gpu/drm/gma500/mid_bios.c | 5 ++-- > drivers/gpu/drm/gma500/mid_bios.h | 1 + > drivers/gpu/drm/gma500/mmu.c | 6 +++-- > drivers/gpu/drm/gma500/oaktrail.h | 2 ++ > drivers/gpu/drm/gma500/oaktrail_crtc.c| 8 --- > drivers/gpu/drm/gma500/oaktrail_device.c | 20 > drivers/gpu/drm/gma500/oaktrail_hdmi.c| 8 --- > drivers/gpu/drm/gma500/oaktrail_lvds.c| 6 ++--- > drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c| 11 - > drivers/gpu/drm/gma500/power.h| 4 +++- > drivers/gpu/drm/gma500/psb_device.c | 12 +- > drivers/gpu/drm/gma500/psb_drv.c | 33 > +-- > drivers/gpu/drm/gma500/psb_drv.h | 16 ++--- > drivers/gpu/drm/gma500/psb_intel_display.c| 7 +++--- > drivers/gpu/drm/gma500/psb_intel_lvds.c | 5 ++-- > drivers/gpu/drm/gma500/psb_intel_modes.c | 2 +- > drivers/gpu/drm/gma500/psb_intel_sdvo.c | 15 ++-- > drivers/gpu/drm/gma500/psb_irq.c | 9 > drivers/gpu/drm/gma500/psb_irq.h | 2 +- > drivers/gpu/drm/gma500/psb_lid.c | 6 ++--- > drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c| 13 +++ > include/drm/gma_drm.h | 25 > 51 files changed, 233 insertions(+), 199 deletions(-) > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] gpu: drm: drivers: Convert printk(KERN_ to pr_
On Tue, Feb 28, 2017 at 1:55 PM, Joe Perches wrote:
> Use a more common logging style.
>
> Miscellanea:
>
> o Coalesce formats and realign arguments
> o Neaten a few macros now using pr_
>
> Signed-off-by: Joe Perches
For the gma500 changes:
Acked-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/gma500/cdv_intel_lvds.c | 9 -
> drivers/gpu/drm/gma500/oaktrail_lvds.c| 18 +-
> drivers/gpu/drm/gma500/psb_drv.h | 5 ++---
> drivers/gpu/drm/gma500/psb_intel_lvds.c | 7 +++
> drivers/gpu/drm/i915/i915_sw_fence.c | 8
> drivers/gpu/drm/mgag200/mgag200_mode.c| 2 +-
> drivers/gpu/drm/msm/msm_drv.c | 2 +-
> drivers/gpu/drm/nouveau/nouveau_acpi.c| 7 ---
> drivers/gpu/drm/nouveau/nouveau_vga.c | 4 ++--
> drivers/gpu/drm/nouveau/nv50_display.c| 22 +++---
> drivers/gpu/drm/nouveau/nvkm/core/mm.c| 10 +-
> drivers/gpu/drm/omapdrm/dss/dsi.c | 17 -
> drivers/gpu/drm/omapdrm/dss/dss.c | 3 +--
> drivers/gpu/drm/omapdrm/dss/dss.h | 15 ++-
> drivers/gpu/drm/omapdrm/omap_gem.c| 5 ++---
> drivers/gpu/drm/r128/r128_cce.c | 7 +++
> drivers/gpu/drm/ttm/ttm_bo.c | 2 +-
> drivers/gpu/drm/vmwgfx/vmwgfx_fence.c | 6 ++
> drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c | 3 +--
> drivers/gpu/drm/vmwgfx/vmwgfx_resource.c | 4 ++--
> 20 files changed, 72 insertions(+), 84 deletions(-)
>
> diff --git a/drivers/gpu/drm/gma500/cdv_intel_lvds.c
> b/drivers/gpu/drm/gma500/cdv_intel_lvds.c
> index 5efdb7fbb7ee..e64960db3224 100644
> --- a/drivers/gpu/drm/gma500/cdv_intel_lvds.c
> +++ b/drivers/gpu/drm/gma500/cdv_intel_lvds.c
> @@ -284,8 +284,7 @@ static bool cdv_intel_lvds_mode_fixup(struct drm_encoder
> *encoder,
> head) {
> if (tmp_encoder != encoder
> && tmp_encoder->crtc == encoder->crtc) {
> - printk(KERN_ERR "Can't enable LVDS and another "
> - "encoder on the same pipe\n");
> + pr_err("Can't enable LVDS and another encoder on the
> same pipe\n");
> return false;
> }
> }
> @@ -756,13 +755,13 @@ void cdv_intel_lvds_init(struct drm_device *dev,
>
> failed_find:
> mutex_unlock(&dev->mode_config.mutex);
> - printk(KERN_ERR "Failed find\n");
> + pr_err("Failed find\n");
> psb_intel_i2c_destroy(gma_encoder->ddc_bus);
> failed_ddc:
> - printk(KERN_ERR "Failed DDC\n");
> + pr_err("Failed DDC\n");
> psb_intel_i2c_destroy(gma_encoder->i2c_bus);
> failed_blc_i2c:
> - printk(KERN_ERR "Failed BLC\n");
> + pr_err("Failed BLC\n");
> drm_encoder_cleanup(encoder);
> drm_connector_cleanup(connector);
> kfree(lvds_priv);
> diff --git a/drivers/gpu/drm/gma500/oaktrail_lvds.c
> b/drivers/gpu/drm/gma500/oaktrail_lvds.c
> index f7038f12ac76..e6943fef0611 100644
> --- a/drivers/gpu/drm/gma500/oaktrail_lvds.c
> +++ b/drivers/gpu/drm/gma500/oaktrail_lvds.c
> @@ -255,15 +255,15 @@ static void oaktrail_lvds_get_configuration_mode(struct
> drm_device *dev,
> ((ti->vblank_hi << 8) | ti->vblank_lo);
> mode->clock = ti->pixel_clock * 10;
> #if 0
> - printk(KERN_INFO "hdisplay is %d\n", mode->hdisplay);
> - printk(KERN_INFO "vdisplay is %d\n", mode->vdisplay);
> - printk(KERN_INFO "HSS is %d\n", mode->hsync_start);
> - printk(KERN_INFO "HSE is %d\n", mode->hsync_end);
> - printk(KERN_INFO "htotal is %d\n", mode->htotal);
> - printk(KERN_INFO "VSS is %d\n", mode->vsync_start);
> - printk(KERN_INFO "VSE is %d\n", mode->vsync_end);
> - printk(KERN_INFO "vtotal is %d\n", mode->vtotal);
> - printk(KERN_INFO "clock is %d\n", mode->clock);
> + pr_info("hdisplay is %d\n", mode->hdisplay);
> + pr_info("vdisplay is %d\n", mode->vdisplay);
> + pr_info("HSS is %d\n", mode->hsync_start);
> + pr_info("HSE is %d\n", mode->hsync_end);
> + pr_info("htotal is %d\n", mode->
Re: [Intel-gfx] [PATCH 07/15] drm/gma500: Nuke device_is_agp callback
On Wed, Jan 25, 2017 at 7:26 AM, Daniel Vetter wrote:
> Returning 0 for an on-chip gpu doesn't change anything at all.
>
> Cc: Patrik Jakobsson
> Signed-off-by: Daniel Vetter
Acked-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/gma500/psb_drv.c | 6 --
> 1 file changed, 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/gma500/psb_drv.c
> b/drivers/gpu/drm/gma500/psb_drv.c
> index 0dc7ba2fdc22..5ee93ff55608 100644
> --- a/drivers/gpu/drm/gma500/psb_drv.c
> +++ b/drivers/gpu/drm/gma500/psb_drv.c
> @@ -406,11 +406,6 @@ static int psb_driver_load(struct drm_device *dev,
> unsigned long flags)
> return ret;
> }
>
> -static int psb_driver_device_is_agp(struct drm_device *dev)
> -{
> - return 0;
> -}
> -
> static inline void get_brightness(struct backlight_device *bd)
> {
> #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
> @@ -487,7 +482,6 @@ static struct drm_driver driver = {
> .set_busid = drm_pci_set_busid,
>
> .num_ioctls = ARRAY_SIZE(psb_ioctls),
> - .device_is_agp = psb_driver_device_is_agp,
> .irq_preinstall = psb_irq_preinstall,
> .irq_postinstall = psb_irq_postinstall,
> .irq_uninstall = psb_irq_uninstall,
> --
> 2.11.0
>
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Re: [Intel-gfx] [RFC PATCH] drm: define drm_compat_ioctl NULL on CONFIG_COMPAT=n and reduce #ifdefs
On Tue, Nov 1, 2016 at 4:40 PM, Jani Nikula wrote:
> If we define drm_compat_ioctl NULL on CONFIG_COMPAT=n, we don't have to
> check for the config everywhere.
>
> Signed-off-by: Jani Nikula
Looks good and I like the idea.
Reviewed-by: Patrik Jakobsson
> ---
>
> Just an idea on top of Patrik's patch.
> ---
> drivers/gpu/drm/arc/arcpgu_drv.c| 2 --
> drivers/gpu/drm/arm/hdlcd_drv.c | 2 --
> drivers/gpu/drm/arm/malidp_drv.c| 2 --
> drivers/gpu/drm/ast/ast_drv.c | 2 --
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c| 2 --
> drivers/gpu/drm/bochs/bochs_drv.c | 2 --
> drivers/gpu/drm/cirrus/cirrus_drv.c | 2 --
> drivers/gpu/drm/drm_fops.c | 13 ++---
> drivers/gpu/drm/etnaviv/etnaviv_drv.c | 2 --
> drivers/gpu/drm/exynos/exynos_drm_drv.c | 2 --
> drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 2 --
> drivers/gpu/drm/gma500/psb_drv.c| 2 --
> drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c | 2 --
> drivers/gpu/drm/i810/i810_dma.c | 2 --
> drivers/gpu/drm/i810/i810_drv.c | 2 --
> drivers/gpu/drm/i915/i915_drv.c | 2 --
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 --
> drivers/gpu/drm/mgag200/mgag200_drv.c | 2 --
> drivers/gpu/drm/msm/msm_drv.c | 2 --
> drivers/gpu/drm/rcar-du/rcar_du_drv.c | 2 --
> drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 2 --
> drivers/gpu/drm/savage/savage_drv.c | 2 --
> drivers/gpu/drm/shmobile/shmob_drm_drv.c| 2 --
> drivers/gpu/drm/sis/sis_drv.c | 2 --
> drivers/gpu/drm/sti/sti_drv.c | 2 --
> drivers/gpu/drm/sun4i/sun4i_drv.c | 2 --
> drivers/gpu/drm/tdfx/tdfx_drv.c | 2 --
> drivers/gpu/drm/tegra/drm.c | 2 --
> drivers/gpu/drm/tilcdc/tilcdc_drv.c | 2 --
> drivers/gpu/drm/udl/udl_drv.c | 2 --
> drivers/gpu/drm/vc4/vc4_drv.c | 2 --
> drivers/gpu/drm/via/via_drv.c | 2 --
> drivers/gpu/drm/virtio/virtgpu_drv.c| 2 --
> include/drm/drmP.h | 5 +
> 35 files changed, 13 insertions(+), 71 deletions(-)
>
> diff --git a/drivers/gpu/drm/arc/arcpgu_drv.c
> b/drivers/gpu/drm/arc/arcpgu_drv.c
> index 28e6471257d0..0b6eaa49a1db 100644
> --- a/drivers/gpu/drm/arc/arcpgu_drv.c
> +++ b/drivers/gpu/drm/arc/arcpgu_drv.c
> @@ -65,9 +65,7 @@ static const struct file_operations arcpgu_drm_ops = {
> .open = drm_open,
> .release = drm_release,
> .unlocked_ioctl = drm_ioctl,
> -#ifdef CONFIG_COMPAT
> .compat_ioctl = drm_compat_ioctl,
> -#endif
> .poll = drm_poll,
> .read = drm_read,
> .llseek = no_llseek,
> diff --git a/drivers/gpu/drm/arm/hdlcd_drv.c b/drivers/gpu/drm/arm/hdlcd_drv.c
> index 6477d1a65266..59747ecaad54 100644
> --- a/drivers/gpu/drm/arm/hdlcd_drv.c
> +++ b/drivers/gpu/drm/arm/hdlcd_drv.c
> @@ -268,9 +268,7 @@ static const struct file_operations fops = {
> .open = drm_open,
> .release= drm_release,
> .unlocked_ioctl = drm_ioctl,
> -#ifdef CONFIG_COMPAT
> .compat_ioctl = drm_compat_ioctl,
> -#endif
> .poll = drm_poll,
> .read = drm_read,
> .llseek = noop_llseek,
> diff --git a/drivers/gpu/drm/arm/malidp_drv.c
> b/drivers/gpu/drm/arm/malidp_drv.c
> index 9f4739452a25..d53b625b14fe 100644
> --- a/drivers/gpu/drm/arm/malidp_drv.c
> +++ b/drivers/gpu/drm/arm/malidp_drv.c
> @@ -197,9 +197,7 @@ static const struct file_operations fops = {
> .open = drm_open,
> .release = drm_release,
> .unlocked_ioctl = drm_ioctl,
> -#ifdef CONFIG_COMPAT
> .compat_ioctl = drm_compat_ioctl,
> -#endif
> .poll = drm_poll,
> .read = drm_read,
> .llseek = noop_llseek,
> diff --git a/drivers/gpu/drm/ast/ast_drv.c b/drivers/gpu/drm/ast/ast_drv.c
> index f54afd2113a9..fd7c9eec92e4 100644
> --- a/drivers/gpu/drm/ast/ast_drv.c
> +++ b/drivers/gpu/drm/ast/ast_drv.c
> @@ -188,9 +188,7 @@ static const struct file_operations ast_fops = {
> .unlocked_ioctl = drm_ioctl,
> .mmap = ast_mmap,
> .poll = drm_poll,
> -#ifdef CONFIG_COMPAT
> .compat_ioctl = drm_compat_ioctl,
> -#endif
> .read = drm_read,
> };
>
> diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
&g
Re: [Intel-gfx] [PATCH v4 2/5] drm: Add private data field to trace control block
On Jul 20, 2016 4:50 PM, "Dmitry V. Levin" wrote:
>
> On Mon, Sep 07, 2015 at 08:23:57PM +0200, Patrik Jakobsson wrote:
> > On Mon, Sep 7, 2015 at 6:51 PM, Dmitry V. Levin wrote:
> > > On Mon, Aug 31, 2015 at 02:37:07PM +0200, Patrik Jakobsson wrote:
> > > [...]
> > >> Here's my take on it (I assume it needs some discussion):
> > >>
> > >> int
> > >> set_tcb_priv_data(struct tcb *tcp, void *priv_data)
> > >> {
> > >> /* A free callback is required before setting private data and
private
> > >>* data must be set back to NULL before being set again.
> > >>*/
> > >
> > > I think a single function initializing both _priv_data and
_free_priv_data
> > > would suffice:
> > >
> > > int
> > > set_tcb_priv_data(struct tcb *tcp, void *priv_data,
> > > void (*free_priv_data)(void *))
> > > {
> > > if (tcp->_priv_data)
> > > return -1;
> > >
> > > tcp->_free_priv_data = free_priv_data;
> > > tcp->_priv_data = priv_data;
> > >
> > > return 0;
> > > }
> >
> > Sure, and since they always come in a pairs it might be even better. If
it turns
> > out we need it split up it is easily done later.
>
> JFYI, I've finalized and merged this set_tcb_priv_data interface.
Thanks Dmitry
-Patrik
>
>
> --
> ldv
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Re: [Intel-gfx] [PATCH v2] drm/i915/dmc: Step away from symbolic links
On Mon, Jun 27, 2016 at 7:12 PM, Vivi, Rodrigo wrote: > On Mon, 2016-06-27 at 19:51 +0300, Imre Deak wrote: >> On Mon, 2016-06-27 at 19:32 +0300, Vivi, Rodrigo wrote: >> > >> > On Mon, 2016-06-27 at 14:20 +0300, Imre Deak wrote: >> > > >> > > Adding Christophe, he was supposed to make the release after >> > > validation. >> > Apparently we are almost ready to release and one latest round of >> > final >> > validation was pending. >> > >> > Christophe, any news on this front? >> > >> > > >> > > I don't think it prevents merging this patch though, the >> > > result is failure to load the firmware in either case. >> > I was going to say that I agree, but I believe Patrik might be >> > right. >> > Without this patch we load the 1.06 while with this patch we start >> > loading only the 1.07 that is not available. >> > Although 1.06 might have issues the failures would be different. So >> > or >> > we blacklist 1.06 with a separated patch and then merge this one or >> > we >> > release the 1.07 before. >> 1.06 is already blacklisted, it has known problems. > > Oh! So I agree with the first statement. Let's merge this patch ;) That was new info for me as well. I don't have commit access so anyone who can, feel free to merge. -Patrik > >> >> --Imre >> >> > >> > > >> > > On ma, 2016-06-27 at 12:57 +0200, Patrik Jakobsson wrote: >> > > > >> > > > >> > > > On Wed, Jun 15, 2016 at 12:11:55AM +, Vivi, Rodrigo wrote: >> > > > > >> > > > > >> > > > > On Mon, 2016-05-23 at 10:57 +0200, Patrik Jakobsson wrote: >> > > > > > >> > > > > > >> > > > > > On Wed, May 18, 2016 at 01:24:12PM +0300, Mika Kuoppala >> > > > > > wrote: >> > > > > > > >> > > > > > > >> > > > > > > Patrik Jakobsson >> > > > > > > writes: >> > > > > > > >> > > > > > > > >> > > > > > > > >> > > > > > > > [ text/plain ] >> > > > > > > > Load specific firmware versions for the DMC instead of >> > > > > > > > using >> > > > > > > > symbolic >> > > > > > > > links. The currently recommended versions are: SKL >> > > > > > > > 1.26, >> > > > > > > > KBL 1.01 >> > > > > > > > and >> > > > > > > > BXT 1.07. >> > > > > > > > >> > > > > > > > Certain DMC versions need workarounds in the driver >> > > > > > > > which >> > > > > > > > forces >> > > > > > > > us to >> > > > > > > > have a tight dependency between firmware and driver. In >> > > > > > > > order to >> > > > > > > > be able >> > > > > > > > to provide a tested and known working configuration we >> > > > > > > > must >> > > > > > > > lock >> > > > > > > > down on >> > > > > > > > a specific DMC firmware version. >> > > > > > > > >> > > > > > > > Cc: Rodrigo Vivi >> > > > > > > > Cc: Imre Deak >> > > > > > > > Cc: Mika Kuoppala >> > > > > > > > Signed-off-by: Patrik Jakobsson >> > > > > > > > > >> > > > > > > > > >> > > > > > > > > >> > > > > > > Reviewed-by: Mika Kuoppala >> > > > > > > >> > > > > > > We need ack from Rodrigo and/or whomever is handling >> > > > > > > the fw releasing side. >> > > > > > > >> > > > > > > -Mika >> > > > > > > >> > > > > > As discussed on IRC, Rodrigo is currently away but since he >> > > > > > requested >> > > > > > this >> > > > > > feature we indirectly have his ACK. >> > > > > indeed! ;) >> > > > I assume we need BXT
Re: [Intel-gfx] [PATCH v2] drm/i915/dmc: Step away from symbolic links
On Wed, Jun 15, 2016 at 12:11:55AM +, Vivi, Rodrigo wrote:
> On Mon, 2016-05-23 at 10:57 +0200, Patrik Jakobsson wrote:
> > On Wed, May 18, 2016 at 01:24:12PM +0300, Mika Kuoppala wrote:
> > > Patrik Jakobsson writes:
> > >
> > > > [ text/plain ]
> > > > Load specific firmware versions for the DMC instead of using
> > > > symbolic
> > > > links. The currently recommended versions are: SKL 1.26, KBL 1.01
> > > > and
> > > > BXT 1.07.
> > > >
> > > > Certain DMC versions need workarounds in the driver which forces
> > > > us to
> > > > have a tight dependency between firmware and driver. In order to
> > > > be able
> > > > to provide a tested and known working configuration we must lock
> > > > down on
> > > > a specific DMC firmware version.
> > > >
> > > > Cc: Rodrigo Vivi
> > > > Cc: Imre Deak
> > > > Cc: Mika Kuoppala
> > > > Signed-off-by: Patrik Jakobsson > > > >
> > >
> > > Reviewed-by: Mika Kuoppala
> > >
> > > We need ack from Rodrigo and/or whomever is handling
> > > the fw releasing side.
> > >
> > > -Mika
> > >
> >
> > As discussed on IRC, Rodrigo is currently away but since he requested
> > this
> > feature we indirectly have his ACK.
>
> indeed! ;)
I assume we need BXT 1.07 released on 01.org before merging this. Any status on
that?
-Patrik
>
>
> Acked-by: Rodrigo Vivi
>
> > -Patrik
> >
> > > > ---
> > > > drivers/gpu/drm/i915/intel_csr.c | 29 ++
> > > > ---
> > > > 1 file changed, 14 insertions(+), 15 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_csr.c
> > > > b/drivers/gpu/drm/i915/intel_csr.c
> > > > index 2b3b428..ea047cd 100644
> > > > --- a/drivers/gpu/drm/i915/intel_csr.c
> > > > +++ b/drivers/gpu/drm/i915/intel_csr.c
> > > > @@ -41,15 +41,15 @@
> > > > * be moved to FW_FAILED.
> > > > */
> > > >
> > > > -#define I915_CSR_KBL "i915/kbl_dmc_ver1.bin"
> > > > +#define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin"
> > > > MODULE_FIRMWARE(I915_CSR_KBL);
> > > > #define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1)
> > > >
> > > > -#define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
> > > > +#define I915_CSR_SKL "i915/skl_dmc_ver1_26.bin"
> > > > MODULE_FIRMWARE(I915_CSR_SKL);
> > > > -#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23)
> > > > +#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 26)
> > > >
> > > > -#define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
> > > > +#define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin"
> > > > MODULE_FIRMWARE(I915_CSR_BXT);
> > > > #define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
> > > >
> > > > @@ -286,7 +286,7 @@ static uint32_t *parse_csr_fw(struct
> > > > drm_i915_private *dev_priv,
> > > > uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount =
> > > > 0, nbytes;
> > > > uint32_t i;
> > > > uint32_t *dmc_payload;
> > > > - uint32_t required_min_version;
> > > > + uint32_t required_version;
> > > >
> > > > if (!fw)
> > > > return NULL;
> > > > @@ -303,24 +303,23 @@ static uint32_t *parse_csr_fw(struct
> > > > drm_i915_private *dev_priv,
> > > > csr->version = css_header->version;
> > > >
> > > > if (IS_KABYLAKE(dev_priv)) {
> > > > - required_min_version = KBL_CSR_VERSION_REQUIRED;
> > > > + required_version = KBL_CSR_VERSION_REQUIRED;
> > > > } else if (IS_SKYLAKE(dev_priv)) {
> > > > - required_min_version = SKL_CSR_VERSION_REQUIRED;
> > > > + required_version = SKL_CSR_VERSION_REQUIRED;
> > > > } else if (IS_BROXTON(dev_priv)) {
> > > > - required_min_version = BXT_CSR_VERSION_REQUIRED;
> > > > + required_version = BXT_CSR_VERSION_REQUIRED;
> > > > } else {
> > > > MISSING_CASE(INTEL_REVID(dev_priv));
> > > > - re
Re: [Intel-gfx] [PATCH v2] drm/core: Change declaration for gamma_set.
On Tue, Jun 7, 2016 at 12:49 PM, Maarten Lankhorst
wrote:
> Change return value to int to propagate errors from gamma_set,
> and remove start parameter. Updates always use the full size,
> and some drivers even ignore the start parameter altogether.
>
> This is needed for atomic drivers, where an atomic commit can
> fail with -EINTR or -ENOMEM and should be restarted.
>
> Changes since v1:
> - Fix compiler warning. (Emil)
> - Fix commit message (Daniel)
>
> Cc: Alex Deucher
> Acked-by: Alex Deucher
> Cc: Christian König
> Cc: David Airlie
> Cc: Patrik Jakobsson
> Cc: Ben Skeggs
> Cc: Eric Anholt
> Cc: VMware Graphics
> Cc: Mathieu Larouche
> Cc: Thierry Reding
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 10 ++
> drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 10 ++
> drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 10 ++
> drivers/gpu/drm/ast/ast_mode.c | 10 ++
> drivers/gpu/drm/cirrus/cirrus_mode.c| 8 +---
> drivers/gpu/drm/drm_atomic_helper.c | 13 ++---
> drivers/gpu/drm/drm_crtc.c | 2 +-
> drivers/gpu/drm/drm_fb_helper.c | 2 +-
> drivers/gpu/drm/gma500/gma_display.c| 9 +
> drivers/gpu/drm/gma500/gma_display.h| 4 ++--
> drivers/gpu/drm/mgag200/mgag200_mode.c | 9 +
> drivers/gpu/drm/nouveau/dispnv04/crtc.c | 12 +++-
> drivers/gpu/drm/nouveau/nv50_display.c | 9 +
> drivers/gpu/drm/radeon/radeon_display.c | 11 +++
> drivers/gpu/drm/vc4/vc4_crtc.c | 8 +---
> drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 8 +---
> drivers/gpu/drm/vmwgfx/vmwgfx_kms.h | 4 ++--
> include/drm/drm_atomic_helper.h | 6 +++---
> include/drm/drm_crtc.h | 4 ++--
> 19 files changed, 85 insertions(+), 64 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> index 7e57447bf5f4..112e358f0f9b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> @@ -2667,19 +2667,21 @@ static void dce_v10_0_cursor_reset(struct drm_crtc
> *crtc)
> }
> }
>
> -static void dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16
> *green,
> - u16 *blue, uint32_t start, uint32_t size)
> +static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16
> *green,
> + u16 *blue, uint32_t size)
> {
> struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
> - int end = (start + size > 256) ? 256 : start + size, i;
> + int i;
>
> /* userspace palettes are always correct as is */
> - for (i = start; i < end; i++) {
> + for (i = 0; i < size; i++) {
> amdgpu_crtc->lut_r[i] = red[i] >> 6;
> amdgpu_crtc->lut_g[i] = green[i] >> 6;
> amdgpu_crtc->lut_b[i] = blue[i] >> 6;
> }
> dce_v10_0_crtc_load_lut(crtc);
> +
> + return 0;
> }
>
> static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> index da101551960b..b522fa2435a8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> @@ -2678,19 +2678,21 @@ static void dce_v11_0_cursor_reset(struct drm_crtc
> *crtc)
> }
> }
>
> -static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16
> *green,
> - u16 *blue, uint32_t start, uint32_t size)
> +static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16
> *green,
> + u16 *blue, uint32_t size)
> {
> struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
> - int end = (start + size > 256) ? 256 : start + size, i;
> + int i;
>
> /* userspace palettes are always correct as is */
> - for (i = start; i < end; i++) {
> + for (i = 0; i < size; i++) {
> amdgpu_crtc->lut_r[i] = red[i] >> 6;
> amdgpu_crtc->lut_g[i] = green[i] >> 6;
> amdgpu_crtc->lut_b[i] = blue[i] >> 6;
> }
> dce_v11_0_crtc_load_lut(crtc);
> +
> + return 0;
> }
>
> static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> index 41d9bc5f9c0e..b50ed72feedb 100644
> --- a/drivers/gpu/drm/amd/
Re: [Intel-gfx] [PATCH v2] drm/i915/dmc: Step away from symbolic links
On Wed, May 18, 2016 at 01:24:12PM +0300, Mika Kuoppala wrote:
> Patrik Jakobsson writes:
>
> > [ text/plain ]
> > Load specific firmware versions for the DMC instead of using symbolic
> > links. The currently recommended versions are: SKL 1.26, KBL 1.01 and
> > BXT 1.07.
> >
> > Certain DMC versions need workarounds in the driver which forces us to
> > have a tight dependency between firmware and driver. In order to be able
> > to provide a tested and known working configuration we must lock down on
> > a specific DMC firmware version.
> >
> > Cc: Rodrigo Vivi
> > Cc: Imre Deak
> > Cc: Mika Kuoppala
> > Signed-off-by: Patrik Jakobsson
>
> Reviewed-by: Mika Kuoppala
>
> We need ack from Rodrigo and/or whomever is handling
> the fw releasing side.
>
> -Mika
>
As discussed on IRC, Rodrigo is currently away but since he requested this
feature we indirectly have his ACK.
-Patrik
> > ---
> > drivers/gpu/drm/i915/intel_csr.c | 29 ++---
> > 1 file changed, 14 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_csr.c
> > b/drivers/gpu/drm/i915/intel_csr.c
> > index 2b3b428..ea047cd 100644
> > --- a/drivers/gpu/drm/i915/intel_csr.c
> > +++ b/drivers/gpu/drm/i915/intel_csr.c
> > @@ -41,15 +41,15 @@
> > * be moved to FW_FAILED.
> > */
> >
> > -#define I915_CSR_KBL "i915/kbl_dmc_ver1.bin"
> > +#define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin"
> > MODULE_FIRMWARE(I915_CSR_KBL);
> > #define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1)
> >
> > -#define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
> > +#define I915_CSR_SKL "i915/skl_dmc_ver1_26.bin"
> > MODULE_FIRMWARE(I915_CSR_SKL);
> > -#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23)
> > +#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 26)
> >
> > -#define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
> > +#define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin"
> > MODULE_FIRMWARE(I915_CSR_BXT);
> > #define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
> >
> > @@ -286,7 +286,7 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
> > *dev_priv,
> > uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
> > uint32_t i;
> > uint32_t *dmc_payload;
> > - uint32_t required_min_version;
> > + uint32_t required_version;
> >
> > if (!fw)
> > return NULL;
> > @@ -303,24 +303,23 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
> > *dev_priv,
> > csr->version = css_header->version;
> >
> > if (IS_KABYLAKE(dev_priv)) {
> > - required_min_version = KBL_CSR_VERSION_REQUIRED;
> > + required_version = KBL_CSR_VERSION_REQUIRED;
> > } else if (IS_SKYLAKE(dev_priv)) {
> > - required_min_version = SKL_CSR_VERSION_REQUIRED;
> > + required_version = SKL_CSR_VERSION_REQUIRED;
> > } else if (IS_BROXTON(dev_priv)) {
> > - required_min_version = BXT_CSR_VERSION_REQUIRED;
> > + required_version = BXT_CSR_VERSION_REQUIRED;
> > } else {
> > MISSING_CASE(INTEL_REVID(dev_priv));
> > - required_min_version = 0;
> > + required_version = 0;
> > }
> >
> > - if (csr->version < required_min_version) {
> > - DRM_INFO("Refusing to load old DMC firmware v%u.%u,"
> > -" please upgrade to v%u.%u or later"
> > - " [" FIRMWARE_URL "].\n",
> > + if (csr->version != required_version) {
> > + DRM_INFO("Refusing to load DMC firmware v%u.%u,"
> > +" please use v%u.%u [" FIRMWARE_URL "].\n",
> > CSR_VERSION_MAJOR(csr->version),
> > CSR_VERSION_MINOR(csr->version),
> > -CSR_VERSION_MAJOR(required_min_version),
> > -CSR_VERSION_MINOR(required_min_version));
> > +CSR_VERSION_MAJOR(required_version),
> > +CSR_VERSION_MINOR(required_version));
> > return NULL;
> > }
> >
> > --
> > 2.5.0
--
Intel Sweden AB Registered Office: Knarrarnasgatan 15, 164 40 Kista, Stockholm,
Sweden Registration Number: 556189-6027
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 00/21] Rework page flip, remove cs flips, async unpin and unified pageflip.
On Tue, May 17, 2016 at 03:07:43PM +0200, Maarten Lankhorst wrote: > Connector lifetime patches forced a rethinking for handling connectors. > Instead of flushing modesets from the connector destroy function this > meant destroying the connector state inside the unpin_work function, > similar to the other states destroyed there. This is only done if the > state is actually needed. > > Some minor updates have been done to clean up the mmio page flip > completion, they're now separated from cs flip completion. > > Convert flip_work to a list has been reworked to incorporate the > feedback. It should now probably work with multiple flips without > waiting, but is currently only used for unpinning legacy cursor > updates. I've reviewed the entire series now and I think we're good to go. With that said, the series is quite non-trivial and I have not worn my bikeshedding glasses while reviewing due to the fact that these are highly requested features. We will likely see minor issues that we didn't catch in review but we really need to expose this to real world testing now so fingers crossed. -Patrik > > Maarten Lankhorst (21): > drm/core: Add drm_accurate_vblank_count, v5. > drm/i915: Remove stallcheck special handling, v3. > drm/i915: Remove intel_finish_page_flip_plane. > drm/i915: Remove intel_prepare_page_flip, v3. > drm/i915: Add support for detecting vblanks when hw frame counter is > unavailable. > drm/i915: Unify unpin_work and mmio_work into flip_work, v2. > Revert "drm/i915: Avoid stalling on pending flips for legacy cursor > updates" > drm/i915: Allow mmio updates on all platforms, v2. > drm/i915: Convert flip_work to a list. > drm/i915: Add the exclusive fence to plane_state. > drm/i915: Rework intel_crtc_page_flip to be almost atomic, v3. > drm/i915: Remove cs based page flip support. > drm/i915: Remove use_mmio_flip kernel parameter. > drm/i915: Remove queue_flip pointer. > drm/i915: Remove reset_counter from intel_crtc. > drm/i915: Pass atomic states to fbc update functions. > drm/i915: Prepare connectors for nonblocking checks. > drm/i915: Make unpin async. > Reapply "drm/i915: Avoid stalling on pending flips for legacy cursor > updates" > drm/i915: Check for unpin correctness. > drm/i915: Allow async update of pageflips. > > drivers/gpu/drm/drm_irq.c | 31 + > drivers/gpu/drm/i915/i915_debugfs.c | 93 +- > drivers/gpu/drm/i915/i915_drv.h |5 - > drivers/gpu/drm/i915/i915_irq.c | 142 +-- > drivers/gpu/drm/i915/i915_params.c|5 - > drivers/gpu/drm/i915/i915_params.h|1 - > drivers/gpu/drm/i915/intel_atomic.c | 11 + > drivers/gpu/drm/i915/intel_atomic_plane.c |1 + > drivers/gpu/drm/i915/intel_display.c | 1725 > + > drivers/gpu/drm/i915/intel_drv.h | 68 +- > drivers/gpu/drm/i915/intel_fbc.c | 39 +- > drivers/gpu/drm/i915/intel_lrc.c |4 +- > drivers/gpu/drm/i915/intel_sprite.c | 16 +- > include/drm/drmP.h|1 + > 14 files changed, 742 insertions(+), 1400 deletions(-) > > -- > 2.5.5 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Intel Sweden AB Registered Office: Knarrarnasgatan 15, 164 40 Kista, Stockholm, Sweden Registration Number: 556189-6027 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 21/21] drm/i915: Allow async update of pageflips.
On Tue, May 17, 2016 at 03:08:04PM +0200, Maarten Lankhorst wrote:
> Signed-off-by: Maarten Lankhorst
We could have had a short note on what the patch does, though reading it is
quite straight forward. Either way is fine by me.
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 350
> +--
> 1 file changed, 84 insertions(+), 266 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 330a6397f07c..79759cdfada3 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -108,8 +108,6 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
> const struct intel_crtc_state *pipe_config);
> static void chv_prepare_pll(struct intel_crtc *crtc,
> const struct intel_crtc_state *pipe_config);
> -static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state
> *);
> -static void intel_finish_crtc_commit(struct drm_crtc *, struct
> drm_crtc_state *);
> static void skl_init_scalers(struct drm_device *dev, struct intel_crtc
> *intel_crtc,
> struct intel_crtc_state *crtc_state);
> static void skylake_pfit_enable(struct intel_crtc *crtc);
> @@ -10981,7 +10979,7 @@ static void intel_mmio_flip_work_func(struct
> work_struct *w)
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct drm_i915_gem_request *req;
> - int i;
> + int i, ret;
>
> if (!needs_modeset(&crtc_state->base) && crtc_state->update_pipe) {
> work->put_power_domains =
> @@ -11003,7 +11001,14 @@ static void intel_mmio_flip_work_func(struct
> work_struct *w)
> &dev_priv->rps.mmioflips));
> }
>
> - intel_frontbuffer_flip_prepare(dev, crtc_state->fb_bits);
> + ret = drm_crtc_vblank_get(crtc);
> + I915_STATE_WARN(ret < 0, "enabling vblank failed with %i\n", ret);
> +
> + if (work->num_planes &&
> + work->old_plane_state[0]->base.plane == crtc->primary)
> + intel_fbc_enable(intel_crtc, work->new_crtc_state,
> work->new_plane_state[0]);
> +
> + intel_frontbuffer_flip_prepare(dev, work->fb_bits);
>
> intel_pipe_update_start(intel_crtc);
> if (!needs_modeset(&crtc_state->base)) {
> @@ -11022,206 +11027,15 @@ static void intel_mmio_flip_work_func(struct
> work_struct *w)
> struct intel_plane_state *new_plane_state =
> work->new_plane_state[i];
> struct intel_plane *plane =
> to_intel_plane(new_plane_state->base.plane);
>
> - plane->update_plane(&plane->base, crtc_state, new_plane_state);
> + if (new_plane_state->visible)
> + plane->update_plane(&plane->base, crtc_state,
> new_plane_state);
> + else
> + plane->disable_plane(&plane->base, crtc);
> }
>
> intel_pipe_update_end(intel_crtc, work);
> }
>
> -static struct fence *intel_get_excl_fence(struct drm_i915_gem_object *obj)
> -{
> - struct reservation_object *resv;
> -
> -
> - if (!obj->base.dma_buf)
> - return NULL;
> -
> - resv = obj->base.dma_buf->resv;
> -
> - /* For framebuffer backed by dmabuf, wait for fence */
> - while (1) {
> - struct fence *fence_excl, *ret = NULL;
> -
> - rcu_read_lock();
> -
> - fence_excl = rcu_dereference(resv->fence_excl);
> - if (fence_excl)
> - ret = fence_get_rcu(fence_excl);
> -
> - rcu_read_unlock();
> -
> - if (ret == fence_excl)
> - return ret;
> - }
> -}
> -
> -static int intel_crtc_page_flip(struct drm_crtc *crtc,
> - struct drm_framebuffer *fb,
> - struct drm_pending_vblank_event *event,
> - uint32_t page_flip_flags)
> -{
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct drm_plane_state *old_state, *new_state = NULL;
> - struct drm_crtc_state *new_crtc_state = NULL;
> - struct drm_framebuffer *old_fb = crtc->primary->state->fb;
> - struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - struct drm_plane *primary = crtc->primary;
> - struct intel_flip_work
Re: [Intel-gfx] [PATCH v2 18/21] drm/i915: Make unpin async.
On Tue, May 17, 2016 at 03:08:01PM +0200, Maarten Lankhorst wrote:
> All of intel_post_plane_update is handled there now, so move it over.
> This is run after the hw state checker because it can't handle checking
> crtc's separately yet.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_atomic.c | 11 ++
> drivers/gpu/drm/i915/intel_display.c | 344
> ++-
> drivers/gpu/drm/i915/intel_drv.h | 5 +-
> 3 files changed, 228 insertions(+), 132 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c
> b/drivers/gpu/drm/i915/intel_atomic.c
> index 50ff90aea721..b4927f6bbeac 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -311,6 +311,17 @@ intel_atomic_state_alloc(struct drm_device *dev)
> void intel_atomic_state_clear(struct drm_atomic_state *s)
> {
> struct intel_atomic_state *state = to_intel_atomic_state(s);
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(state->work); i++) {
> + struct intel_flip_work *work = state->work[i];
> +
> + if (work)
> + intel_free_flip_work(work);
> +
> + state->work[i] = NULL;
> + }
> +
> drm_atomic_state_default_clear(&state->base);
> state->dpll_set = state->modeset = false;
> }
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 69abc808a2c4..16d8e24d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4537,39 +4537,6 @@ intel_pre_disable_primary_noatomic(struct drm_crtc
> *crtc)
> }
> }
>
> -static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
> -{
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> - struct drm_atomic_state *old_state = old_crtc_state->base.state;
> - struct intel_crtc_state *pipe_config =
> - to_intel_crtc_state(crtc->base.state);
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_plane *primary = crtc->base.primary;
> - struct drm_plane_state *old_pri_state =
> - drm_atomic_get_existing_plane_state(old_state, primary);
> -
> - intel_frontbuffer_flip(dev, pipe_config->fb_bits);
> -
> - crtc->wm.cxsr_allowed = true;
> -
> - if (pipe_config->update_wm_post && pipe_config->base.active)
> - intel_update_watermarks(&crtc->base);
> -
> - if (old_pri_state) {
> - struct intel_plane_state *primary_state =
> - to_intel_plane_state(primary->state);
> - struct intel_plane_state *old_primary_state =
> - to_intel_plane_state(old_pri_state);
> -
> - intel_fbc_post_update(crtc);
> -
> - if (primary_state->visible &&
> - (needs_modeset(&pipe_config->base) ||
> - !old_primary_state->visible))
> - intel_post_enable_primary(&crtc->base);
> - }
> -}
> -
> static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> @@ -5179,18 +5146,21 @@ modeset_get_crtc_power_domains(struct drm_crtc *crtc,
> struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> enum intel_display_power_domain domain;
> - unsigned long domains, new_domains, old_domains;
> + unsigned long domains, new_domains, old_domains, ms_domain = 0;
>
> old_domains = intel_crtc->enabled_power_domains;
> intel_crtc->enabled_power_domains = new_domains =
> get_crtc_power_domains(crtc, crtc_state);
>
> - domains = new_domains & ~old_domains;
> + if (needs_modeset(&crtc_state->base))
> + ms_domain = BIT(POWER_DOMAIN_MODESET);
> +
> + domains = (new_domains & ~old_domains) | ms_domain;
>
> for_each_power_domain(domain, domains)
> intel_display_power_get(dev_priv, domain);
>
> - return old_domains & ~new_domains;
> + return (old_domains & ~new_domains) | ms_domain;
> }
>
> static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
> @@ -6236,6 +6206,12 @@ int intel_display_suspend(struct drm_device *dev)
> DRM_ERROR("Suspending crtc's failed with %i\n", ret);
> else
> dev_priv->modese
Re: [Intel-gfx] [PATCH v2 17/21] drm/i915: Prepare connectors for nonblocking checks.
On Tue, May 17, 2016 at 03:08:00PM +0200, Maarten Lankhorst wrote:
> intel_unpin_work may not take the list lock because it requires the
> connector_mutex.
> To prevent taking locks we add an array of old and new state. The old state
> to free,
> the new state to commit and verify.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 53
> ++--
> drivers/gpu/drm/i915/intel_drv.h | 4 +++
> 2 files changed, 43 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 15ab4a6f1556..69abc808a2c4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6249,9 +6249,10 @@ void intel_encoder_destroy(struct drm_encoder *encoder)
>
> /* Cross check the actual hw state with our own modeset state tracking (and
> it's
> * internal consistency). */
> -static void intel_connector_verify_state(struct intel_connector *connector)
> +static void intel_connector_verify_state(struct intel_connector *connector,
> + struct drm_connector_state *conn_state)
> {
> - struct drm_crtc *crtc = connector->base.state->crtc;
> + struct drm_crtc *crtc = conn_state->crtc;
>
> DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
> connector->base.base.id,
> @@ -6259,7 +6260,6 @@ static void intel_connector_verify_state(struct
> intel_connector *connector)
>
> if (connector->get_hw_state(connector)) {
> struct intel_encoder *encoder = connector->encoder;
> - struct drm_connector_state *conn_state = connector->base.state;
>
> I915_STATE_WARN(!crtc,
>"connector enabled without attached crtc\n");
> @@ -6281,7 +6281,7 @@ static void intel_connector_verify_state(struct
> intel_connector *connector)
> } else {
> I915_STATE_WARN(crtc && crtc->state->active,
> "attached crtc is active, but connector isn't\n");
> - I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
> + I915_STATE_WARN(!crtc && conn_state->best_encoder,
> "best encoder set without crtc!\n");
> }
> }
> @@ -10776,6 +10776,14 @@ void intel_mark_idle(struct drm_i915_private
> *dev_priv)
> intel_runtime_pm_put(dev_priv);
> }
>
> +static void
> +intel_free_flip_work(struct intel_flip_work *work)
> +{
> + kfree(work->old_connector_state);
> + kfree(work->new_connector_state);
> + kfree(work);
> +}
> +
> static void intel_crtc_destroy(struct drm_crtc *crtc)
> {
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -10791,7 +10799,7 @@ static void intel_crtc_destroy(struct drm_crtc *crtc)
>
> cancel_work_sync(&work->mmio_work);
> cancel_work_sync(&work->unpin_work);
> - kfree(work);
> + intel_free_flip_work(work);
>
> spin_lock_irq(&dev->event_lock);
> }
> @@ -10856,11 +10864,32 @@ static void intel_unpin_work_fn(struct work_struct
> *__work)
> /* Make sure mmio work is completely finished before freeing all state
> here. */
> flush_work(&work->mmio_work);
>
> - if (!work->can_async_unpin)
> + if (!work->can_async_unpin &&
> + (work->new_crtc_state->update_pipe ||
> + needs_modeset(&work->new_crtc_state->base))) {
> /* This must be called before work is unpinned for
> serialization. */
> intel_modeset_verify_crtc(crtc, &work->old_crtc_state->base,
> &work->new_crtc_state->base);
>
> + for (i = 0; i < work->num_new_connectors; i++) {
> + struct drm_connector_state *conn_state =
> + work->new_connector_state[i];
> + struct drm_connector *con = conn_state->connector;
> +
> + intel_connector_verify_state(to_intel_connector(con),
> + conn_state);
> + }
> + }
> +
> + for (i = 0; i < work->num_old_connectors; i++) {
> + struct drm_connector_state *old_con_state =
> + work->old_connector_state[i];
> + struct drm_connector *con =
> + old_con_
Re: [Intel-gfx] [PATCH v2 11/21] drm/i915: Rework intel_crtc_page_flip to be almost atomic, v3.
On Tue, May 17, 2016 at 03:07:54PM +0200, Maarten Lankhorst wrote:
> Create a work structure that will be used for all changes. This will
> be used later on in the atomic commit function.
>
> Changes since v1:
> - Free old_crtc_state from unpin_work_fn properly.
> Changes since v2:
> - Add hunk for calling hw state verifier.
> - Add missing support for color spaces.
>
> Signed-off-by: Maarten Lankhorst
I would have liked this one to be split into smaller pieces but since I can't
find any good points to split at, I think this is good enough.
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 36 +-
> drivers/gpu/drm/i915/intel_display.c | 672
> +--
> drivers/gpu/drm/i915/intel_drv.h | 13 +-
> 3 files changed, 441 insertions(+), 280 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 220ec15e9864..6bce4fd8aaf4 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -598,29 +598,43 @@ static void i915_dump_pageflip(struct seq_file *m,
> struct intel_flip_work *work)
> {
> const char pipe = pipe_name(crtc->pipe);
> - const char plane = plane_name(crtc->plane);
> u32 pending;
> u32 addr;
> + int i;
>
> pending = atomic_read(&work->pending);
> if (pending) {
> seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
> -pipe, plane);
> +pipe, plane_name(crtc->plane));
> } else {
> seq_printf(m, "Flip pending (waiting for vsync) on pipe %c
> (plane %c)\n",
> -pipe, plane);
> +pipe, plane_name(crtc->plane));
> }
> - if (work->flip_queued_req) {
> - struct intel_engine_cs *engine =
> i915_gem_request_get_engine(work->flip_queued_req);
>
> - seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x
> [current breadcrumb %x], completed? %d\n",
> +
> + for (i = 0; i < work->num_planes; i++) {
> + struct intel_plane_state *old_plane_state =
> work->old_plane_state[i];
> + struct drm_plane *plane = old_plane_state->base.plane;
> + struct drm_i915_gem_request *req = old_plane_state->wait_req;
> + struct intel_engine_cs *engine;
> +
> + seq_printf(m, "[PLANE:%i] part of flip.\n", plane->base.id);
> +
> + if (!req) {
> + seq_printf(m, "Plane not associated with any engine\n");
> + continue;
> + }
> +
> + engine = i915_gem_request_get_engine(req);
> +
> + seq_printf(m, "Plane blocked on %s at seqno %x, next seqno %x
> [current breadcrumb %x], completed? %d\n",
> engine->name,
> -i915_gem_request_get_seqno(work->flip_queued_req),
> +i915_gem_request_get_seqno(req),
> dev_priv->next_seqno,
> engine->get_seqno(engine),
> -i915_gem_request_completed(work->flip_queued_req,
> true));
> - } else
> - seq_printf(m, "Flip not associated with any ring\n");
> +i915_gem_request_completed(req, true));
> + }
> +
> seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now
> %d\n",
> work->flip_queued_vblank,
> work->flip_ready_vblank,
> @@ -633,7 +647,7 @@ static void i915_dump_pageflip(struct seq_file *m,
> addr = I915_READ(DSPADDR(crtc->plane));
> seq_printf(m, "Current scanout address 0x%08x\n", addr);
>
> - if (work->pending_flip_obj) {
> + if (work->flip_queued_req) {
> seq_printf(m, "New framebuffer address 0x%08lx\n",
> (long)work->gtt_offset);
> seq_printf(m, "MMIO update completed? %d\n", addr ==
> work->gtt_offset);
> }
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index b7888ad331bb..b8b12177f1f0 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -50,7 +50,7 @@
>
> static bool is_mmio_work(struct intel_flip_work *work)
> {
> - return work->mmio_work.func;
> + return !work->flip_queued_req;
> }
>
> /* Primary pl
Re: [Intel-gfx] [PATCH v2 20/21] drm/i915: Check for unpin correctness.
On Tue, May 17, 2016 at 03:08:03PM +0200, Maarten Lankhorst wrote:
> If planes are added to the state after the call to
> drm_atomic_helper_check_planes planes_changed may not be set
> and we will not unpin the old framebuffer. This results in a
> pin leak long after the framebuffer is destroyed, so to find
> this add some checks when it happens.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 9236407e9b13..330a6397f07c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13373,11 +13373,20 @@ intel_prepare_plane_fb(struct drm_plane *plane,
> struct intel_plane *intel_plane = to_intel_plane(plane);
> struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
> + struct drm_crtc *crtc = new_state->crtc ?: plane->state->crtc;
> int ret = 0;
>
> if (!obj && !old_obj)
> return 0;
>
> + if (WARN_ON(!new_state->state) || WARN_ON(!crtc) ||
> +
> WARN_ON(!to_intel_atomic_state(new_state->state)->work[to_intel_crtc(crtc)->pipe]))
> {
> + if (WARN_ON(old_obj != obj))
> + return -EINVAL;
> +
> + return 0;
> + }
> +
> if (old_obj) {
> struct drm_crtc_state *crtc_state =
> drm_atomic_get_existing_crtc_state(new_state->state,
> plane->state->crtc);
> --
> 2.5.5
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Intel Sweden AB Registered Office: Knarrarnasgatan 15, 164 40 Kista, Stockholm,
Sweden Registration Number: 556189-6027
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 19/21] Reapply "drm/i915: Avoid stalling on pending flips for legacy cursor updates"
On Tue, May 17, 2016 at 03:08:02PM +0200, Maarten Lankhorst wrote:
> This reapplies commit acf4e84d6167317ff21be5c03e1ea76ea5783701.
> With async unpin this should no longer break.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 12 +++-
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 16d8e24d..9236407e9b13 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12930,12 +12930,14 @@ static int intel_atomic_prepare_commit(struct
> drm_device *dev,
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_flip_work *work;
>
> - ret = intel_crtc_wait_for_pending_flips(crtc);
> - if (ret)
> - return ret;
> + if (!state->legacy_cursor_update) {
> + ret = intel_crtc_wait_for_pending_flips(crtc);
> + if (ret)
> + return ret;
>
> - if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
> - flush_workqueue(dev_priv->wq);
> + if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
> + flush_workqueue(dev_priv->wq);
> + }
>
> /* test if we need to update something */
> if (!needs_work(crtc_state))
> --
> 2.5.5
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Intel Sweden AB Registered Office: Knarrarnasgatan 15, 164 40 Kista, Stockholm,
Sweden Registration Number: 556189-6027
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 16/21] drm/i915: Pass atomic states to fbc update functions.
On Tue, May 17, 2016 at 03:07:59PM +0200, Maarten Lankhorst wrote:
> This is required to let fbc updates run async. It has a lot of
> checks whether certain locks are taken, which can be removed when
> the relevant states are passed in as pointers.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 8 +---
> drivers/gpu/drm/i915/intel_drv.h | 8 ++--
> drivers/gpu/drm/i915/intel_fbc.c | 39
> +---
> 3 files changed, 29 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index db8c6d905007..15ab4a6f1556 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4589,7 +4589,7 @@ static void intel_pre_plane_update(struct
> intel_crtc_state *old_crtc_state)
> struct intel_plane_state *old_primary_state =
> to_intel_plane_state(old_pri_state);
>
> - intel_fbc_pre_update(crtc);
> + intel_fbc_pre_update(crtc, pipe_config, primary_state);
>
> if (old_primary_state->visible &&
> (modeset || !primary_state->visible))
> @@ -11169,7 +11169,9 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
> if (obj->base.dma_buf)
> work->old_plane_state[0]->base.fence =
> intel_get_excl_fence(obj);
>
> - intel_fbc_pre_update(intel_crtc);
> + intel_fbc_pre_update(intel_crtc,
> + to_intel_crtc_state(new_crtc_state),
> + to_intel_plane_state(new_state));
>
> schedule_work(&work->mmio_work);
>
> @@ -13128,7 +13130,7 @@ static int intel_atomic_commit(struct drm_device *dev,
>
> if (crtc->state->active &&
> drm_atomic_get_existing_plane_state(state, crtc->primary))
> - intel_fbc_enable(intel_crtc);
> + intel_fbc_enable(intel_crtc, pipe_config,
> to_intel_plane_state(crtc->primary->state));
>
> if (crtc->state->active &&
> (crtc->state->planes_changed || update_pipe))
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 11dae90b7168..b2900d659dff 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1418,11 +1418,15 @@ static inline void intel_fbdev_restore_mode(struct
> drm_device *dev)
> void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
> struct drm_atomic_state *state);
> bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
> -void intel_fbc_pre_update(struct intel_crtc *crtc);
> +void intel_fbc_pre_update(struct intel_crtc *crtc,
> + struct intel_crtc_state *crtc_state,
> + struct intel_plane_state *plane_state);
> void intel_fbc_post_update(struct intel_crtc *crtc);
> void intel_fbc_init(struct drm_i915_private *dev_priv);
> void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
> -void intel_fbc_enable(struct intel_crtc *crtc);
> +void intel_fbc_enable(struct intel_crtc *crtc,
> + struct intel_crtc_state *crtc_state,
> + struct intel_plane_state *plane_state);
> void intel_fbc_disable(struct intel_crtc *crtc);
> void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
> void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c
> b/drivers/gpu/drm/i915/intel_fbc.c
> index 0dea5fbcd8aa..d2b0269b2fe4 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -480,10 +480,10 @@ static void intel_fbc_deactivate(struct
> drm_i915_private *dev_priv)
> intel_fbc_hw_deactivate(dev_priv);
> }
>
> -static bool multiple_pipes_ok(struct intel_crtc *crtc)
> +static bool multiple_pipes_ok(struct intel_crtc *crtc,
> + struct intel_plane_state *plane_state)
> {
> - struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
> - struct drm_plane *primary = crtc->base.primary;
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_fbc *fbc = &dev_priv->fbc;
> enum pipe pipe = crtc->pipe;
>
> @@ -491,9 +491,7 @@ static bool multiple_pipes_ok(struct intel_crtc *crtc)
> if (!no_fbc_on_multiple_pipes(dev_priv))
> return true;
>
> - WARN_ON(!drm_modeset_is_locked(&primary->mutex));
> -
Re: [Intel-gfx] [PATCH v2 15/21] drm/i915: Remove reset_counter from intel_crtc.
On Tue, May 17, 2016 at 03:07:58PM +0200, Maarten Lankhorst wrote:
> With the removal of cs-based flips all mmio waits will
> finish without requiring the reset counter, because the
> waits will complete during gpu reset.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 9 -
> drivers/gpu/drm/i915/intel_drv.h | 3 ---
> 2 files changed, 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index d96f6a86d6f6..db8c6d905007 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3179,14 +3179,6 @@ void intel_finish_reset(struct drm_i915_private
> *dev_priv)
>
> static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
> {
> - struct drm_device *dev = crtc->dev;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - unsigned reset_counter;
> -
> - reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
> - if (intel_crtc->reset_counter != reset_counter)
> - return false;
> -
> return !list_empty_careful(&to_intel_crtc(crtc)->flip_work);
> }
>
> @@ -11179,7 +11171,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
>
> intel_fbc_pre_update(intel_crtc);
>
> - intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
> schedule_work(&work->mmio_work);
>
> mutex_unlock(&dev->struct_mutex);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index c538d821a728..11dae90b7168 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -659,9 +659,6 @@ struct intel_crtc {
>
> struct intel_crtc_state *config;
>
> - /* reset counter value when the last flip was submitted */
> - unsigned int reset_counter;
> -
> /* Access to these should be protected by dev_priv->irq_lock. */
> bool cpu_fifo_underrun_disabled;
> bool pch_fifo_underrun_disabled;
> --
> 2.5.5
>
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Re: [Intel-gfx] [PATCH v2 14/21] drm/i915: Remove queue_flip pointer.
On Tue, May 17, 2016 at 03:07:57PM +0200, Maarten Lankhorst wrote:
> With the removal of cs support this is no longer reachable.
> Can be revived if needed.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_drv.h | 5 -
> drivers/gpu/drm/i915/intel_display.c | 259
> ---
> 2 files changed, 264 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 26c0525fc546..ea35a432bb68 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -618,11 +618,6 @@ struct drm_i915_display_funcs {
> void (*audio_codec_disable)(struct intel_encoder *encoder);
> void (*fdi_link_train)(struct drm_crtc *crtc);
> void (*init_clock_gating)(struct drm_device *dev);
> - int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
> - struct drm_framebuffer *fb,
> - struct drm_i915_gem_object *obj,
> - struct drm_i915_gem_request *req,
> - uint64_t gtt_offset);
> void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
> /* clock updates for mode set */
> /* cursor updates */
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 19a382445306..d96f6a86d6f6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10964,237 +10964,6 @@ void intel_finish_page_flip_mmio(struct
> drm_i915_private *dev_priv, int pipe)
> spin_unlock_irqrestore(&dev->event_lock, flags);
> }
>
> -static int intel_gen2_queue_flip(struct drm_device *dev,
> - struct drm_crtc *crtc,
> - struct drm_framebuffer *fb,
> - struct drm_i915_gem_object *obj,
> - struct drm_i915_gem_request *req,
> - uint64_t gtt_offset)
> -{
> - struct intel_engine_cs *engine = req->engine;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - u32 flip_mask;
> - int ret;
> -
> - ret = intel_ring_begin(req, 6);
> - if (ret)
> - return ret;
> -
> - /* Can't queue multiple flips, so wait for the previous
> - * one to finish before executing the next.
> - */
> - if (intel_crtc->plane)
> - flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
> - else
> - flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
> - intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
> - intel_ring_emit(engine, MI_NOOP);
> - intel_ring_emit(engine, MI_DISPLAY_FLIP |
> - MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
> - intel_ring_emit(engine, fb->pitches[0]);
> - intel_ring_emit(engine, gtt_offset);
> - intel_ring_emit(engine, 0); /* aux display base address, unused */
> -
> - return 0;
> -}
> -
> -static int intel_gen3_queue_flip(struct drm_device *dev,
> - struct drm_crtc *crtc,
> - struct drm_framebuffer *fb,
> - struct drm_i915_gem_object *obj,
> - struct drm_i915_gem_request *req,
> - uint64_t gtt_offset)
> -{
> - struct intel_engine_cs *engine = req->engine;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - u32 flip_mask;
> - int ret;
> -
> - ret = intel_ring_begin(req, 6);
> - if (ret)
> - return ret;
> -
> - if (intel_crtc->plane)
> - flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
> - else
> - flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
> - intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
> - intel_ring_emit(engine, MI_NOOP);
> - intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
> - MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
> - intel_ring_emit(engine, fb->pitches[0]);
> - intel_ring_emit(engine, gtt_offset);
> - intel_ring_emit(engine, MI_NOOP);
> -
> - return 0;
> -}
> -
> -static int intel_gen4_queue_flip(struct drm_device *dev,
> - struct drm_crtc *crtc,
> - struct drm_framebuffer *fb,
> - struct drm_i915_gem_object *obj,
> - struct drm_i915_gem_request *req,
> - uint64_t gtt_offset)
> -{
> - struct intel_engine_cs *engine = req->engine;
> - struct drm_i915_private *dev_pr
Re: [Intel-gfx] [PATCH v2 13/21] drm/i915: Remove use_mmio_flip kernel parameter.
On Tue, May 17, 2016 at 03:07:56PM +0200, Maarten Lankhorst wrote:
> With the removal of cs flips this is always force enabled.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_params.c | 5 -
> drivers/gpu/drm/i915/i915_params.h | 1 -
> drivers/gpu/drm/i915/intel_lrc.c | 4 +---
> 3 files changed, 1 insertion(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_params.c
> b/drivers/gpu/drm/i915/i915_params.c
> index 383c076919ed..cd74fb8e9387 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -49,7 +49,6 @@ struct i915_params i915 __read_mostly = {
> .invert_brightness = 0,
> .disable_display = 0,
> .enable_cmd_parser = 1,
> - .use_mmio_flip = 0,
> .mmio_debug = 0,
> .verbose_state_checks = 1,
> .nuclear_pageflip = 0,
> @@ -174,10 +173,6 @@ module_param_named_unsafe(enable_cmd_parser,
> i915.enable_cmd_parser, int, 0600);
> MODULE_PARM_DESC(enable_cmd_parser,
>"Enable command parsing (1=enabled [default], 0=disabled)");
>
> -module_param_named_unsafe(use_mmio_flip, i915.use_mmio_flip, int, 0600);
> -MODULE_PARM_DESC(use_mmio_flip,
> - "use MMIO flips (-1=never, 0=driver discretion [default],
> 1=always)");
> -
> module_param_named(mmio_debug, i915.mmio_debug, int, 0600);
> MODULE_PARM_DESC(mmio_debug,
> "Enable the MMIO debug code for the first N failures (default: off). "
> diff --git a/drivers/gpu/drm/i915/i915_params.h
> b/drivers/gpu/drm/i915/i915_params.h
> index 65e73dd7d970..dd0d0bbcc05b 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -46,7 +46,6 @@ struct i915_params {
> int invert_brightness;
> int enable_cmd_parser;
> int guc_log_level;
> - int use_mmio_flip;
> int mmio_debug;
> int edp_vswing;
> unsigned int inject_load_failure;
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index db10c961e0f4..affca6d5ce7e 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -260,9 +260,7 @@ int intel_sanitize_enable_execlists(struct
> drm_i915_private *dev_priv, int enabl
> if (enable_execlists == 0)
> return 0;
>
> - if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) &&
> - USES_PPGTT(dev_priv) &&
> - i915.use_mmio_flip >= 0)
> + if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && USES_PPGTT(dev_priv))
> return 1;
>
> return 0;
> --
> 2.5.5
>
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Re: [Intel-gfx] [PATCH v2 12/21] drm/i915: Remove cs based page flip support.
On Tue, May 17, 2016 at 03:07:55PM +0200, Maarten Lankhorst wrote:
> With mmio flips now available on all platforms it's time to remove
> support for cs flips.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 19 +-
> drivers/gpu/drm/i915/i915_irq.c | 120 ++-
> drivers/gpu/drm/i915/intel_display.c | 392
> +--
> drivers/gpu/drm/i915/intel_drv.h | 9 +-
> 4 files changed, 33 insertions(+), 507 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 6bce4fd8aaf4..4c6b48dbd6e2 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -599,7 +599,6 @@ static void i915_dump_pageflip(struct seq_file *m,
> {
> const char pipe = pipe_name(crtc->pipe);
> u32 pending;
> - u32 addr;
> int i;
>
> pending = atomic_read(&work->pending);
> @@ -611,7 +610,6 @@ static void i915_dump_pageflip(struct seq_file *m,
> pipe, plane_name(crtc->plane));
> }
>
> -
> for (i = 0; i < work->num_planes; i++) {
> struct intel_plane_state *old_plane_state =
> work->old_plane_state[i];
> struct drm_plane *plane = old_plane_state->base.plane;
> @@ -635,22 +633,9 @@ static void i915_dump_pageflip(struct seq_file *m,
> i915_gem_request_completed(req, true));
> }
>
> - seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now
> %d\n",
> -work->flip_queued_vblank,
> -work->flip_ready_vblank,
> + seq_printf(m, "Flip queued on frame %d, now %d\n",
> +pending ? work->flip_queued_vblank : -1,
> intel_crtc_get_vblank_counter(crtc));
> - seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
> -
> - if (INTEL_INFO(dev_priv)->gen >= 4)
> - addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
> - else
> - addr = I915_READ(DSPADDR(crtc->plane));
> - seq_printf(m, "Current scanout address 0x%08x\n", addr);
> -
> - if (work->flip_queued_req) {
> - seq_printf(m, "New framebuffer address 0x%08lx\n",
> (long)work->gtt_offset);
> - seq_printf(m, "MMIO update completed? %d\n", addr ==
> work->gtt_offset);
> - }
> }
>
> static int i915_gem_pageflip_info(struct seq_file *m, void *data)
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 3242a37fb304..5513c4cb02e0 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -136,6 +136,12 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
> POSTING_READ(type##IIR); \
> } while (0)
>
> +static void
> +intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, unsigned pipe)
> +{
> + DRM_DEBUG_KMS("Finished page flip\n");
> +}
> +
> /*
> * We should clear IMR at preinstall/uninstall, and just check at
> postinstall.
> */
> @@ -1631,16 +1637,11 @@ static void gen6_rps_irq_handler(struct
> drm_i915_private *dev_priv, u32 pm_iir)
> }
> }
>
> -static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
> +static void intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
>enum pipe pipe)
> {
> - bool ret;
> -
> - ret = drm_handle_vblank(dev_priv->dev, pipe);
> - if (ret)
> + if (drm_handle_vblank(dev_priv->dev, pipe))
> intel_finish_page_flip_mmio(dev_priv, pipe);
> -
> - return ret;
> }
>
> static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
> @@ -1707,9 +1708,8 @@ static void valleyview_pipestat_irq_handler(struct
> drm_i915_private *dev_priv,
> enum pipe pipe;
>
> for_each_pipe(dev_priv, pipe) {
> - if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
> - intel_pipe_handle_vblank(dev_priv, pipe))
> - intel_check_page_flip(dev_priv, pipe);
> + if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
> + intel_pipe_handle_vblank(dev_priv, pipe);
>
> if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
> intel_finish_page_flip_cs(dev_priv, pipe);
> @@ -2155,9 +2155,8 @@ static void ilk_display_irq_handler(struct
> drm_i915_private *dev_priv,
&
Re: [Intel-gfx] [PATCH v2 10/21] drm/i915: Add the exclusive fence to plane_state.
On Tue, May 17, 2016 at 03:07:53PM +0200, Maarten Lankhorst wrote:
> Set plane_state->base.fence to the dma_buf exclusive fence,
> and add a wait to the mmio function. This will make it easier
> to unify plane updates later on.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_atomic_plane.c | 1 +
> drivers/gpu/drm/i915/intel_display.c | 54
> +++
> 2 files changed, 42 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index 7de7721f65bc..2ab45f16fa65 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -102,6 +102,7 @@ intel_plane_destroy_state(struct drm_plane *plane,
> struct drm_plane_state *state)
> {
> WARN_ON(state && to_intel_plane_state(state)->wait_req);
> + WARN_ON(state && state->fence);
> drm_atomic_helper_plane_destroy_state(plane, state);
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index ece259de6ff2..b7888ad331bb 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13358,6 +13358,15 @@ static int intel_atomic_prepare_commit(struct
> drm_device *dev,
> struct intel_plane_state *intel_plane_state =
> to_intel_plane_state(plane_state);
>
> + if (plane_state->fence) {
> + long lret = fence_wait(plane_state->fence,
> true);
> +
> + if (lret < 0) {
> + ret = lret;
> + break;
> + }
> + }
> +
> if (!intel_plane_state->wait_req)
> continue;
>
> @@ -13683,6 +13692,33 @@ static const struct drm_crtc_funcs intel_crtc_funcs
> = {
> .atomic_destroy_state = intel_crtc_destroy_state,
> };
>
> +static struct fence *intel_get_excl_fence(struct drm_i915_gem_object *obj)
> +{
> + struct reservation_object *resv;
> +
> +
> + if (!obj->base.dma_buf)
> + return NULL;
> +
> + resv = obj->base.dma_buf->resv;
> +
> + /* For framebuffer backed by dmabuf, wait for fence */
> + while (1) {
> + struct fence *fence_excl, *ret = NULL;
> +
> + rcu_read_lock();
> +
> + fence_excl = rcu_dereference(resv->fence_excl);
> + if (fence_excl)
> + ret = fence_get_rcu(fence_excl);
> +
> + rcu_read_unlock();
> +
> + if (ret == fence_excl)
> + return ret;
> + }
> +}
> +
> /**
> * intel_prepare_plane_fb - Prepare fb for usage on plane
> * @plane: drm plane to prepare for
> @@ -13735,19 +13771,6 @@ intel_prepare_plane_fb(struct drm_plane *plane,
> }
> }
>
> - /* For framebuffer backed by dmabuf, wait for fence */
> - if (obj && obj->base.dma_buf) {
> - long lret;
> -
> - lret =
> reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
> -false, true,
> -
> MAX_SCHEDULE_TIMEOUT);
> - if (lret == -ERESTARTSYS)
> - return lret;
> -
> - WARN(lret < 0, "waiting returns %li\n", lret);
> - }
> -
> if (!obj) {
> ret = 0;
> } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
> @@ -13767,6 +13790,8 @@ intel_prepare_plane_fb(struct drm_plane *plane,
>
> i915_gem_request_assign(&plane_state->wait_req,
> obj->last_write_req);
> +
> + plane_state->base.fence = intel_get_excl_fence(obj);
> }
>
> i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
> @@ -13809,6 +13834,9 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
> i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
>
> i915_gem_request_assign(&old_intel_state->wait_req, NULL);
> +
> + fence_put(old_intel_state->base.fence);
> + old_intel_state->base.fence = NULL;
> }
>
> int
> --
> 2.5.5
>
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Re: [Intel-gfx] [PATCH v2 09/21] drm/i915: Convert flip_work to a list.
On Tue, May 17, 2016 at 03:07:52PM +0200, Maarten Lankhorst wrote:
> This will be required to allow more than 1 update in the future.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 90 +++--
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 146
> +--
> drivers/gpu/drm/i915/intel_drv.h | 4 +-
> 4 files changed, 142 insertions(+), 100 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 0a4bedb96d65..220ec15e9864 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -592,6 +592,53 @@ static int i915_gem_gtt_info(struct seq_file *m, void
> *data)
> return 0;
> }
>
> +static void i915_dump_pageflip(struct seq_file *m,
> +struct drm_i915_private *dev_priv,
> +struct intel_crtc *crtc,
> +struct intel_flip_work *work)
> +{
> + const char pipe = pipe_name(crtc->pipe);
> + const char plane = plane_name(crtc->plane);
> + u32 pending;
> + u32 addr;
> +
> + pending = atomic_read(&work->pending);
> + if (pending) {
> + seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
> +pipe, plane);
> + } else {
> + seq_printf(m, "Flip pending (waiting for vsync) on pipe %c
> (plane %c)\n",
> +pipe, plane);
> + }
> + if (work->flip_queued_req) {
> + struct intel_engine_cs *engine =
> i915_gem_request_get_engine(work->flip_queued_req);
> +
> + seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x
> [current breadcrumb %x], completed? %d\n",
> +engine->name,
> +i915_gem_request_get_seqno(work->flip_queued_req),
> +dev_priv->next_seqno,
> +engine->get_seqno(engine),
> +i915_gem_request_completed(work->flip_queued_req,
> true));
> + } else
> + seq_printf(m, "Flip not associated with any ring\n");
> + seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now
> %d\n",
> +work->flip_queued_vblank,
> +work->flip_ready_vblank,
> +intel_crtc_get_vblank_counter(crtc));
> + seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
> +
> + if (INTEL_INFO(dev_priv)->gen >= 4)
> + addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
> + else
> + addr = I915_READ(DSPADDR(crtc->plane));
> + seq_printf(m, "Current scanout address 0x%08x\n", addr);
> +
> + if (work->pending_flip_obj) {
> + seq_printf(m, "New framebuffer address 0x%08lx\n",
> (long)work->gtt_offset);
> + seq_printf(m, "MMIO update completed? %d\n", addr ==
> work->gtt_offset);
> + }
> +}
> +
> static int i915_gem_pageflip_info(struct seq_file *m, void *data)
> {
> struct drm_info_node *node = m->private;
> @@ -610,48 +657,13 @@ static int i915_gem_pageflip_info(struct seq_file *m,
> void *data)
> struct intel_flip_work *work;
>
> spin_lock_irq(&dev->event_lock);
> - work = crtc->flip_work;
> - if (work == NULL) {
> + if (list_empty(&crtc->flip_work)) {
> seq_printf(m, "No flip due on pipe %c (plane %c)\n",
> pipe, plane);
> } else {
> - u32 pending;
> - u32 addr;
> -
> - pending = atomic_read(&work->pending);
> - if (pending) {
> - seq_printf(m, "Flip ioctl preparing on pipe %c
> (plane %c)\n",
> -pipe, plane);
> - } else {
> - seq_printf(m, "Flip pending (waiting for vsync)
> on pipe %c (plane %c)\n",
> -pipe, plane);
> - }
> - if (work->flip_queued_req) {
> - struct intel_engine_cs *engine =
> i915_gem_request_get_engine(work->flip_queued_req);
> -
> - seq_printf(m, "Flip queued
Re: [Intel-gfx] [PATCH v2 08/21] drm/i915: Allow mmio updates on all platforms, v2.
On Tue, May 17, 2016 at 03:07:51PM +0200, Maarten Lankhorst wrote:
> With intel_pipe_update begin/end we ensure that the mmio updates
> don't run during vblank interrupt, using the hw counter we can
> be sure that when current vblank count != vblank count at the time
> of pipe_update_end the mmio update is complete.
>
> This allows us to use mmio updates on all platforms, using the
> update_plane call.
>
> With Chris Wilson's patch to skip waiting for vblanks for
> legacy_cursor_update this potentially leaves a small race
> condition, in which update_plane can be called with a freed
> crtc_state. Because of this commit acf4e84d61673
> ("drm/i915: Avoid stalling on pending flips for legacy cursor updates")
> is temporarily reverted.
>
> Changes since v1:
> - Split out the flip_work rename.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 99
> +++-
> drivers/gpu/drm/i915/intel_drv.h | 1 -
> 2 files changed, 7 insertions(+), 93 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 6526bb5a7afb..6d2af42a86c1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11269,9 +11269,6 @@ static bool use_mmio_flip(struct intel_engine_cs
> *engine,
> if (engine == NULL)
> return true;
>
> - if (INTEL_GEN(engine->i915) < 5)
> - return false;
> -
> if (i915.use_mmio_flip < 0)
> return false;
> else if (i915.use_mmio_flip > 0)
> @@ -11286,92 +11283,15 @@ static bool use_mmio_flip(struct intel_engine_cs
> *engine,
> return engine !=
> i915_gem_request_get_engine(obj->last_write_req);
> }
>
> -static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
> - unsigned int rotation,
> - struct intel_flip_work *work)
> -{
> - struct drm_device *dev = intel_crtc->base.dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
> - const enum pipe pipe = intel_crtc->pipe;
> - u32 ctl, stride, tile_height;
> -
> - ctl = I915_READ(PLANE_CTL(pipe, 0));
> - ctl &= ~PLANE_CTL_TILED_MASK;
> - switch (fb->modifier[0]) {
> - case DRM_FORMAT_MOD_NONE:
> - break;
> - case I915_FORMAT_MOD_X_TILED:
> - ctl |= PLANE_CTL_TILED_X;
> - break;
> - case I915_FORMAT_MOD_Y_TILED:
> - ctl |= PLANE_CTL_TILED_Y;
> - break;
> - case I915_FORMAT_MOD_Yf_TILED:
> - ctl |= PLANE_CTL_TILED_YF;
> - break;
> - default:
> - MISSING_CASE(fb->modifier[0]);
> - }
> -
> - /*
> - * The stride is either expressed as a multiple of 64 bytes chunks for
> - * linear buffers or in number of tiles for tiled buffers.
> - */
> - if (intel_rotation_90_or_270(rotation)) {
> - /* stride = Surface height in tiles */
> - tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
> - stride = DIV_ROUND_UP(fb->height, tile_height);
> - } else {
> - stride = fb->pitches[0] /
> - intel_fb_stride_alignment(dev_priv, fb->modifier[0],
> - fb->pixel_format);
> - }
> -
> - /*
> - * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
> - * PLANE_SURF updates, the update is then guaranteed to be atomic.
> - */
> - I915_WRITE(PLANE_CTL(pipe, 0), ctl);
> - I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
> -
> - I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
> - POSTING_READ(PLANE_SURF(pipe, 0));
> -}
> -
> -static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
> - struct intel_flip_work *work)
> -{
> - struct drm_device *dev = intel_crtc->base.dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_framebuffer *intel_fb =
> - to_intel_framebuffer(intel_crtc->base.primary->fb);
> - struct drm_i915_gem_object *obj = intel_fb->obj;
> - i915_reg_t reg = DSPCNTR(intel_crtc->plane);
> - u32 dspcntr;
> -
> - dspcntr = I915_READ(reg);
> -
> - if (obj->tiling_mode != I915_TILING_NONE)
> - dspcntr |= DISPPLANE_TILED;
> - else
> - dspcntr &= ~DISPPLANE_TILED;
> -
Re: [Intel-gfx] [PATCH v2 07/21] Revert "drm/i915: Avoid stalling on pending flips for legacy cursor updates"
On Tue, May 17, 2016 at 03:07:50PM +0200, Maarten Lankhorst wrote:
> This reverts commit acf4e84d6167317ff21be5c03e1ea76ea5783701.
> Unfortunately this breaks the next commit with a use-after-free, so
> temporarily revert until we can apply a solution.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index d349a8118a56..6526bb5a7afb 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13397,9 +13397,6 @@ static int intel_atomic_prepare_commit(struct
> drm_device *dev,
> }
>
> for_each_crtc_in_state(state, crtc, crtc_state, i) {
> - if (state->legacy_cursor_update)
> - continue;
> -
> ret = intel_crtc_wait_for_pending_flips(crtc);
> if (ret)
> return ret;
> --
> 2.5.5
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
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Sweden Registration Number: 556189-6027
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Re: [Intel-gfx] [PATCH v2 06/21] drm/i915: Unify unpin_work and mmio_work into flip_work, v2.
On Tue, May 17, 2016 at 03:07:49PM +0200, Maarten Lankhorst wrote:
> Rename intel_unpin_work to intel_flip_work and use it for mmio flips
> and unpinning. Use flip_queued_req to hold the wait request in the
> mmio case, and the vblank counter from intel_crtc_get_vblank_counter.
>
> MMIO flips get their own path through intel_finish_page_flip_mmio,
> handled on vblank. CS page flips go through *_cs.
>
> Changes since v1:
> - Clean up destinction between MMIO and CS flips.
>
> Signed-off-by: Maarten Lankhorst
Much nicer with the cs / mmio split.
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 6 +-
> drivers/gpu/drm/i915/i915_irq.c | 20 ++-
> drivers/gpu/drm/i915/intel_display.c | 282
> +++
> drivers/gpu/drm/i915/intel_drv.h | 22 ++-
> drivers/gpu/drm/i915/intel_sprite.c | 8 +-
> 5 files changed, 185 insertions(+), 153 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 6bff6b4daf99..0a4bedb96d65 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -607,10 +607,10 @@ static int i915_gem_pageflip_info(struct seq_file *m,
> void *data)
> for_each_intel_crtc(dev, crtc) {
> const char pipe = pipe_name(crtc->pipe);
> const char plane = plane_name(crtc->plane);
> - struct intel_unpin_work *work;
> + struct intel_flip_work *work;
>
> spin_lock_irq(&dev->event_lock);
> - work = crtc->unpin_work;
> + work = crtc->flip_work;
> if (work == NULL) {
> seq_printf(m, "No flip due on pipe %c (plane %c)\n",
> pipe, plane);
> @@ -640,7 +640,7 @@ static int i915_gem_pageflip_info(struct seq_file *m,
> void *data)
> seq_printf(m, "Flip queued on frame %d, (was ready on
> frame %d), now %d\n",
> work->flip_queued_vblank,
> work->flip_ready_vblank,
> -drm_crtc_vblank_count(&crtc->base));
> +intel_crtc_get_vblank_counter(crtc));
> seq_printf(m, "%d prepares\n",
> atomic_read(&work->pending));
>
> if (INTEL_INFO(dev)->gen >= 4)
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 148741646fb0..3242a37fb304 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1634,7 +1634,13 @@ static void gen6_rps_irq_handler(struct
> drm_i915_private *dev_priv, u32 pm_iir)
> static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
>enum pipe pipe)
> {
> - return drm_handle_vblank(dev_priv->dev, pipe);
> + bool ret;
> +
> + ret = drm_handle_vblank(dev_priv->dev, pipe);
> + if (ret)
> + intel_finish_page_flip_mmio(dev_priv, pipe);
> +
> + return ret;
> }
>
> static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
> @@ -1706,7 +1712,7 @@ static void valleyview_pipestat_irq_handler(struct
> drm_i915_private *dev_priv,
> intel_check_page_flip(dev_priv, pipe);
>
> if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
> - intel_finish_page_flip(dev_priv, pipe);
> + intel_finish_page_flip_cs(dev_priv, pipe);
>
> if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
> i9xx_pipe_crc_irq_handler(dev_priv, pipe);
> @@ -2161,7 +2167,7 @@ static void ilk_display_irq_handler(struct
> drm_i915_private *dev_priv,
>
> /* plane/pipes map 1:1 on ilk+ */
> if (de_iir & DE_PLANE_FLIP_DONE(pipe))
> - intel_finish_page_flip(dev_priv, pipe);
> + intel_finish_page_flip_cs(dev_priv, pipe);
> }
>
> /* check event from PCH */
> @@ -2206,7 +2212,7 @@ static void ivb_display_irq_handler(struct
> drm_i915_private *dev_priv,
>
> /* plane/pipes map 1:1 on ilk+ */
> if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
> - intel_finish_page_flip(dev_priv, pipe);
> + intel_finish_page_flip_cs(dev_priv, pipe);
> }
>
> /* check event from PCH */
> @@ -2412,7 +2418,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv,
> u32 master_ctl)
>
Re: [Intel-gfx] [PATCH v2 05/21] drm/i915: Add support for detecting vblanks when hw frame counter is unavailable.
On Tue, May 17, 2016 at 03:07:48PM +0200, Maarten Lankhorst wrote:
> This uses the newly created drm_accurate_vblank_count_and_time to accurately
> get a vblank count when the hw counter is unavailable.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 10 ++
> drivers/gpu/drm/i915/intel_drv.h | 3 +++
> drivers/gpu/drm/i915/intel_sprite.c | 8 ++--
> 3 files changed, 15 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index d6e90fa888cf..316913414f85 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13415,6 +13415,16 @@ static int intel_atomic_prepare_commit(struct
> drm_device *dev,
> return ret;
> }
>
> +u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
> +{
> + struct drm_device *dev = crtc->base.dev;
> +
> + if (!dev->max_vblank_count)
> + return drm_accurate_vblank_count(&crtc->base);
> +
> + return dev->driver->get_vblank_counter(dev, crtc->pipe);
> +}
> +
> static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
> struct drm_i915_private *dev_priv,
> unsigned crtc_mask)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index e2d732af74bb..6a2f546be903 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1178,6 +1178,9 @@ intel_wait_for_vblank_if_active(struct drm_device *dev,
> int pipe)
> if (crtc->active)
> intel_wait_for_vblank(dev, pipe);
> }
> +
> +u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
> +
> int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
> void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
>struct intel_digital_port *dport,
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 57eef129c597..728b924ce82f 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -80,9 +80,7 @@ static int usecs_to_scanlines(const struct drm_display_mode
> *adjusted_mode,
> */
> void intel_pipe_update_start(struct intel_crtc *crtc)
> {
> - struct drm_device *dev = crtc->base.dev;
> const struct drm_display_mode *adjusted_mode =
> &crtc->config->base.adjusted_mode;
> - enum pipe pipe = crtc->pipe;
> long timeout = msecs_to_jiffies_timeout(1);
> int scanline, min, max, vblank_start;
> wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
> @@ -139,8 +137,7 @@ void intel_pipe_update_start(struct intel_crtc *crtc)
>
> crtc->debug.scanline_start = scanline;
> crtc->debug.start_vbl_time = ktime_get();
> - crtc->debug.start_vbl_count =
> - dev->driver->get_vblank_counter(dev, pipe);
> + crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
>
> trace_i915_pipe_update_vblank_evaded(crtc);
> }
> @@ -156,10 +153,9 @@ void intel_pipe_update_start(struct intel_crtc *crtc)
> */
> void intel_pipe_update_end(struct intel_crtc *crtc)
> {
> - struct drm_device *dev = crtc->base.dev;
> enum pipe pipe = crtc->pipe;
> int scanline_end = intel_get_crtc_scanline(crtc);
> - u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
> + u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
> ktime_t end_vbl_time = ktime_get();
>
> trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
> --
> 2.5.5
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Sweden Registration Number: 556189-6027
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Re: [Intel-gfx] [PATCH v2 04/21] drm/i915: Remove intel_prepare_page_flip, v3.
On Tue, May 17, 2016 at 03:07:47PM +0200, Maarten Lankhorst wrote:
> Instead of calling prepare_flip right before calling finish_page_flip
> do everything from prepare_page_flip in finish_page_flip.
>
> Putting prepare and finish page_flip in a single step removes the need
> for INTEL_FLIP_COMPLETE, so it can be removed. This simplifies the code
> slightly.
>
> Changes since v1:
> - Invert if case to simplify code.
> - Add missing barrier.
> - Reword commit message.
> Changes since v2:
> - intel_page_flip_plane is removed.
> - work->pending is turned into a bool.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 5 +--
> drivers/gpu/drm/i915/i915_irq.c | 18 ++---
> drivers/gpu/drm/i915/intel_display.c | 72
> +++-
> drivers/gpu/drm/i915/intel_drv.h | 4 --
> 4 files changed, 26 insertions(+), 73 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index f23b119a365d..6bff6b4daf99 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -619,12 +619,9 @@ static int i915_gem_pageflip_info(struct seq_file *m,
> void *data)
> u32 addr;
>
> pending = atomic_read(&work->pending);
> - if (pending == INTEL_FLIP_INACTIVE) {
> + if (pending) {
> seq_printf(m, "Flip ioctl preparing on pipe %c
> (plane %c)\n",
> pipe, plane);
> - } else if (pending >= INTEL_FLIP_COMPLETE) {
> - seq_printf(m, "Flip queued on pipe %c (plane
> %c)\n",
> -pipe, plane);
> } else {
> seq_printf(m, "Flip pending (waiting for vsync)
> on pipe %c (plane %c)\n",
> pipe, plane);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 920a5e4abb70..148741646fb0 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1705,10 +1705,8 @@ static void valleyview_pipestat_irq_handler(struct
> drm_i915_private *dev_priv,
> intel_pipe_handle_vblank(dev_priv, pipe))
> intel_check_page_flip(dev_priv, pipe);
>
> - if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
> - intel_prepare_page_flip(dev_priv, pipe);
> + if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
> intel_finish_page_flip(dev_priv, pipe);
> - }
>
> if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
> i9xx_pipe_crc_irq_handler(dev_priv, pipe);
> @@ -2162,10 +2160,8 @@ static void ilk_display_irq_handler(struct
> drm_i915_private *dev_priv,
> i9xx_pipe_crc_irq_handler(dev_priv, pipe);
>
> /* plane/pipes map 1:1 on ilk+ */
> - if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
> - intel_prepare_page_flip(dev_priv, pipe);
> + if (de_iir & DE_PLANE_FLIP_DONE(pipe))
> intel_finish_page_flip(dev_priv, pipe);
> - }
> }
>
> /* check event from PCH */
> @@ -2209,10 +2205,8 @@ static void ivb_display_irq_handler(struct
> drm_i915_private *dev_priv,
> intel_check_page_flip(dev_priv, pipe);
>
> /* plane/pipes map 1:1 on ilk+ */
> - if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
> - intel_prepare_page_flip(dev_priv, pipe);
> + if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
> intel_finish_page_flip(dev_priv, pipe);
> - }
> }
>
> /* check event from PCH */
> @@ -2417,10 +2411,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv,
> u32 master_ctl)
> else
> flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
>
> - if (flip_done) {
> - intel_prepare_page_flip(dev_priv, pipe);
> + if (flip_done)
> intel_finish_page_flip(dev_priv, pipe);
> - }
>
> if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
> hsw_pipe_crc_irq_handler(dev_priv, pipe);
> @@ -3998,7 +3990,6 @@ static bool i8xx_handle_vblank(struct drm_i915_private
> *dev_priv,
> if (I915_READ1
Re: [Intel-gfx] [PATCH v2 03/21] drm/i915: Remove intel_finish_page_flip_plane.
On Tue, May 17, 2016 at 03:07:46PM +0200, Maarten Lankhorst wrote:
> This function is duplicated with intel_finish_page_flip,
> and is only ever used from planes that could use the
> other function anyway.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_irq.c | 6 +++---
> drivers/gpu/drm/i915/intel_display.c | 18 --
> drivers/gpu/drm/i915/intel_drv.h | 1 -
> 3 files changed, 7 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index f0d941455bed..920a5e4abb70 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2164,7 +2164,7 @@ static void ilk_display_irq_handler(struct
> drm_i915_private *dev_priv,
> /* plane/pipes map 1:1 on ilk+ */
> if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
> intel_prepare_page_flip(dev_priv, pipe);
> - intel_finish_page_flip_plane(dev_priv, pipe);
> + intel_finish_page_flip(dev_priv, pipe);
> }
> }
>
> @@ -2211,7 +2211,7 @@ static void ivb_display_irq_handler(struct
> drm_i915_private *dev_priv,
> /* plane/pipes map 1:1 on ilk+ */
> if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
> intel_prepare_page_flip(dev_priv, pipe);
> - intel_finish_page_flip_plane(dev_priv, pipe);
> + intel_finish_page_flip(dev_priv, pipe);
> }
> }
>
> @@ -2419,7 +2419,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv,
> u32 master_ctl)
>
> if (flip_done) {
> intel_prepare_page_flip(dev_priv, pipe);
> - intel_finish_page_flip_plane(dev_priv, pipe);
> + intel_finish_page_flip(dev_priv, pipe);
> }
>
> if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 3bcab21e67d3..535f20ab2870 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3110,14 +3110,11 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc,
> struct drm_framebuffer *fb,
>
> static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
> {
> - struct drm_crtc *crtc;
> -
> - for_each_crtc(dev_priv->dev, crtc) {
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - enum plane plane = intel_crtc->plane;
> + struct intel_crtc *crtc;
>
> - intel_prepare_page_flip(dev_priv, plane);
> - intel_finish_page_flip_plane(dev_priv, plane);
> + for_each_intel_crtc(dev_priv->dev, crtc) {
> + intel_prepare_page_flip(dev_priv, crtc->plane);
> + intel_finish_page_flip(dev_priv, crtc->pipe);
> }
> }
>
> @@ -10905,13 +10902,6 @@ void intel_finish_page_flip(struct drm_i915_private
> *dev_priv, int pipe)
> do_intel_finish_page_flip(dev_priv, crtc);
> }
>
> -void intel_finish_page_flip_plane(struct drm_i915_private *dev_priv, int
> plane)
> -{
> - struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
> -
> - do_intel_finish_page_flip(dev_priv, crtc);
> -}
> -
> /* Is 'a' after or equal to 'b'? */
> static bool g4x_flip_count_after_eq(u32 a, u32 b)
> {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index f19e755bb16f..d3081aafac8d 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1201,7 +1201,6 @@ __intel_framebuffer_create(struct drm_device *dev,
> struct drm_i915_gem_object *obj);
> void intel_prepare_page_flip(struct drm_i915_private *dev_priv, int plane);
> void intel_finish_page_flip(struct drm_i915_private *dev_priv, int pipe);
> -void intel_finish_page_flip_plane(struct drm_i915_private *dev_priv, int
> plane);
> void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
> int intel_prepare_plane_fb(struct drm_plane *plane,
> const struct drm_plane_state *new_state);
> --
> 2.5.5
>
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Re: [Intel-gfx] [PATCH v2 02/21] drm/i915: Remove stallcheck special handling, v3.
On Tue, May 17, 2016 at 03:07:45PM +0200, Maarten Lankhorst wrote:
> Both intel_unpin_work.pending and intel_unpin_work.enable_stall_check
> were used to see if work should be enabled. By only using pending
> some special cases are gone, and access to unpin_work can be simplified.
>
> A flip could previously be queued before
> stallcheck was active. With the addition of the pending member
> enable_stall_check became obsolete and can thus be removed.
>
> Use this to only access work members untilintel_mark_page_flip_active
> is called, or intel_queue_mmio_flip is used. This will prevent
> use-after-free, and makes it easier to verify accesses.
>
> Changes since v1:
> - Reword commit message.
> - Do not access unpin_work after intel_mark_page_flip_active.
> - Add the right memory barriers.
> Changes since v2:
> - atomic_read() needs a full smp_rmb.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 11 +++---
> drivers/gpu/drm/i915/intel_display.c | 71
> ++--
> drivers/gpu/drm/i915/intel_drv.h | 1 -
> 3 files changed, 34 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 24f4105b910f..f23b119a365d 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -615,9 +615,14 @@ static int i915_gem_pageflip_info(struct seq_file *m,
> void *data)
> seq_printf(m, "No flip due on pipe %c (plane %c)\n",
> pipe, plane);
> } else {
> + u32 pending;
> u32 addr;
>
> - if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
> + pending = atomic_read(&work->pending);
> + if (pending == INTEL_FLIP_INACTIVE) {
> + seq_printf(m, "Flip ioctl preparing on pipe %c
> (plane %c)\n",
> +pipe, plane);
> + } else if (pending >= INTEL_FLIP_COMPLETE) {
> seq_printf(m, "Flip queued on pipe %c (plane
> %c)\n",
> pipe, plane);
> } else {
> @@ -639,10 +644,6 @@ static int i915_gem_pageflip_info(struct seq_file *m,
> void *data)
> work->flip_queued_vblank,
> work->flip_ready_vblank,
> drm_crtc_vblank_count(&crtc->base));
> - if (work->enable_stall_check)
> - seq_puts(m, "Stall check enabled, ");
> - else
> - seq_puts(m, "Stall check waiting for page flip
> ioctl, ");
> seq_printf(m, "%d prepares\n",
> atomic_read(&work->pending));
>
> if (INTEL_INFO(dev)->gen >= 4)
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 4777087326f6..3bcab21e67d3 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3813,8 +3813,6 @@ static void page_flip_completed(struct intel_crtc
> *intel_crtc)
> struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> struct intel_unpin_work *work = intel_crtc->unpin_work;
>
> - /* ensure that the unpin work is consistent wrt ->pending. */
> - smp_rmb();
> intel_crtc->unpin_work = NULL;
>
> if (work->event)
> @@ -10890,16 +10888,13 @@ static void do_intel_finish_page_flip(struct
> drm_i915_private *dev_priv,
> spin_lock_irqsave(&dev->event_lock, flags);
> work = intel_crtc->unpin_work;
>
> - /* Ensure we don't miss a work->pending update ... */
> - smp_rmb();
> + if (work && atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) {
> + /* ensure that the unpin work is consistent wrt ->pending. */
> + smp_rmb();
>
> - if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
> - spin_unlock_irqrestore(&dev->event_lock, flags);
> - return;
> + page_flip_completed(intel_crtc);
> }
>
> - page_flip_completed(intel_crtc);
> -
> spin_unlock_irqrestore(&dev->event_lock, flags);
> }
>
> @@ -10995,10 +10990,8 @@ void intel_prepare_page_flip(struct d
[Intel-gfx] [PATCH v2] drm/i915/dmc: Step away from symbolic links
Load specific firmware versions for the DMC instead of using symbolic
links. The currently recommended versions are: SKL 1.26, KBL 1.01 and
BXT 1.07.
Certain DMC versions need workarounds in the driver which forces us to
have a tight dependency between firmware and driver. In order to be able
to provide a tested and known working configuration we must lock down on
a specific DMC firmware version.
Cc: Rodrigo Vivi
Cc: Imre Deak
Cc: Mika Kuoppala
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/intel_csr.c | 29 ++---
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 2b3b428..ea047cd 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -41,15 +41,15 @@
* be moved to FW_FAILED.
*/
-#define I915_CSR_KBL "i915/kbl_dmc_ver1.bin"
+#define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin"
MODULE_FIRMWARE(I915_CSR_KBL);
#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1)
-#define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
+#define I915_CSR_SKL "i915/skl_dmc_ver1_26.bin"
MODULE_FIRMWARE(I915_CSR_SKL);
-#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23)
+#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 26)
-#define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
+#define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin"
MODULE_FIRMWARE(I915_CSR_BXT);
#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
@@ -286,7 +286,7 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
*dev_priv,
uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
uint32_t i;
uint32_t *dmc_payload;
- uint32_t required_min_version;
+ uint32_t required_version;
if (!fw)
return NULL;
@@ -303,24 +303,23 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
*dev_priv,
csr->version = css_header->version;
if (IS_KABYLAKE(dev_priv)) {
- required_min_version = KBL_CSR_VERSION_REQUIRED;
+ required_version = KBL_CSR_VERSION_REQUIRED;
} else if (IS_SKYLAKE(dev_priv)) {
- required_min_version = SKL_CSR_VERSION_REQUIRED;
+ required_version = SKL_CSR_VERSION_REQUIRED;
} else if (IS_BROXTON(dev_priv)) {
- required_min_version = BXT_CSR_VERSION_REQUIRED;
+ required_version = BXT_CSR_VERSION_REQUIRED;
} else {
MISSING_CASE(INTEL_REVID(dev_priv));
- required_min_version = 0;
+ required_version = 0;
}
- if (csr->version < required_min_version) {
- DRM_INFO("Refusing to load old DMC firmware v%u.%u,"
-" please upgrade to v%u.%u or later"
- " [" FIRMWARE_URL "].\n",
+ if (csr->version != required_version) {
+ DRM_INFO("Refusing to load DMC firmware v%u.%u,"
+" please use v%u.%u [" FIRMWARE_URL "].\n",
CSR_VERSION_MAJOR(csr->version),
CSR_VERSION_MINOR(csr->version),
-CSR_VERSION_MAJOR(required_min_version),
-CSR_VERSION_MINOR(required_min_version));
+CSR_VERSION_MAJOR(required_version),
+CSR_VERSION_MINOR(required_version));
return NULL;
}
--
2.5.0
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Re: [Intel-gfx] [PATCH 15/19] drm/i915: Prepare MST connector removal for async unpin.
On Tue, Apr 19, 2016 at 09:52:35AM +0200, Maarten Lankhorst wrote:
> check_connector_state might get called from unpin_work, which means
verify_connector_state and not check_connector_state?
Otherwise looks good
Reviewed-by: Patrik Jakobsson
> that the mst removal function has to flush it, and it has to use
> for_each_intel_connector because it cannot check if connection_mutex
> is held.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_display.c | 12 ++--
> drivers/gpu/drm/i915/intel_dp_mst.c | 11 +++
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 3 files changed, 18 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 5d60b3a8f06c..6feb8c6ccb8c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3900,7 +3900,7 @@ static void page_flip_completed(struct intel_crtc
> *intel_crtc, struct intel_flip
> queue_work(dev_priv->wq, &work->unpin_work);
> }
>
> -static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
> +int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
> {
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -12458,16 +12458,16 @@ static void verify_wm_state(struct drm_crtc *crtc,
> static void
> verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
> {
> - struct drm_connector *connector;
> + struct intel_connector *connector;
>
> - drm_for_each_connector(connector, dev) {
> - struct drm_encoder *encoder = connector->encoder;
> - struct drm_connector_state *state = connector->state;
> + for_each_intel_connector(dev, connector) {
> + struct drm_connector_state *state = connector->base.state;
> + struct drm_encoder *encoder = connector->base.encoder;
>
> if (state->crtc != crtc)
> continue;
>
> - intel_connector_verify_state(to_intel_connector(connector));
> + intel_connector_verify_state(connector);
>
> I915_STATE_WARN(state->best_encoder != encoder,
>"connector's atomic encoder doesn't match legacy
> encoder\n");
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 94b4e833dadd..ab24f3ea08bc 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -501,6 +501,7 @@ static void intel_dp_destroy_mst_connector(struct
> drm_dp_mst_topology_mgr *mgr,
> {
> struct intel_connector *intel_connector = to_intel_connector(connector);
> struct drm_device *dev = connector->dev;
> + struct drm_crtc *crtc;
>
> intel_connector->unregister(intel_connector);
>
> @@ -518,6 +519,16 @@ static void intel_dp_destroy_mst_connector(struct
> drm_dp_mst_topology_mgr *mgr,
> WARN(ret, "Disabling mst crtc failed with %i\n", ret);
> }
>
> + /* Ensure any hw state checker call is completed */
> + for_each_crtc(dev, crtc)
> + intel_crtc_wait_for_pending_flips(crtc);
> +
> + /*
> + * Before removing the connector, make sure all work is flushed
> + * because it may traverse the connector list.
> + */
> + flush_workqueue(to_i915(dev)->wq);
> +
> intel_connector_remove_from_fbdev(intel_connector);
> drm_connector_cleanup(connector);
> drm_modeset_unlock_all(dev);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 0ec81df35710..d2cfb50332be 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1145,6 +1145,7 @@ intel_wait_for_vblank_if_active(struct drm_device *dev,
> int pipe)
> if (crtc->active)
> intel_wait_for_vblank(dev, pipe);
> }
> +int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
>
> u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
>
> --
> 2.1.0
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 14/19] drm/i915: Pass atomic states to fbc update functions.
On Tue, Apr 19, 2016 at 09:52:34AM +0200, Maarten Lankhorst wrote:
> This is required to let fbc updates run async. It has a lot of
> checks whether certain locks are taken, which can be removed when
> the relevant states are passed in as pointers.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 8 +---
> drivers/gpu/drm/i915/intel_drv.h | 8 ++--
> drivers/gpu/drm/i915/intel_fbc.c | 39
> +---
> 3 files changed, 29 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index cb899befb96b..5d60b3a8f06c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4699,7 +4699,7 @@ static void intel_pre_plane_update(struct
> intel_crtc_state *old_crtc_state)
> struct intel_plane_state *old_primary_state =
> to_intel_plane_state(old_pri_state);
>
> - intel_fbc_pre_update(crtc);
> + intel_fbc_pre_update(crtc, pipe_config, primary_state);
>
> if (old_primary_state->visible &&
> (modeset || !primary_state->visible))
> @@ -11329,7 +11329,9 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
> if (obj->base.dma_buf)
> work->old_plane_state[0]->base.fence =
> intel_get_excl_fence(obj);
>
> - intel_fbc_pre_update(intel_crtc);
> + intel_fbc_pre_update(intel_crtc,
> + to_intel_crtc_state(new_crtc_state),
> + to_intel_plane_state(new_state));
>
> intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
> schedule_work(&work->mmio_work);
> @@ -13293,7 +13295,7 @@ static int intel_atomic_commit(struct drm_device *dev,
>
> if (crtc->state->active &&
> drm_atomic_get_existing_plane_state(state, crtc->primary))
> - intel_fbc_enable(intel_crtc);
> + intel_fbc_enable(intel_crtc, pipe_config,
> to_intel_plane_state(crtc->primary->state));
>
> if (crtc->state->active &&
> (crtc->state->planes_changed || update_pipe))
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index b18a0d117820..0ec81df35710 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1375,11 +1375,15 @@ static inline void intel_fbdev_restore_mode(struct
> drm_device *dev)
> void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
> struct drm_atomic_state *state);
> bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
> -void intel_fbc_pre_update(struct intel_crtc *crtc);
> +void intel_fbc_pre_update(struct intel_crtc *crtc,
> + struct intel_crtc_state *crtc_state,
> + struct intel_plane_state *plane_state);
> void intel_fbc_post_update(struct intel_crtc *crtc);
> void intel_fbc_init(struct drm_i915_private *dev_priv);
> void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
> -void intel_fbc_enable(struct intel_crtc *crtc);
> +void intel_fbc_enable(struct intel_crtc *crtc,
> + struct intel_crtc_state *crtc_state,
> + struct intel_plane_state *plane_state);
> void intel_fbc_disable(struct intel_crtc *crtc);
> void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
> void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c
> b/drivers/gpu/drm/i915/intel_fbc.c
> index d5a7cfec589b..f8c182382d66 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -480,10 +480,10 @@ static void intel_fbc_deactivate(struct
> drm_i915_private *dev_priv)
> intel_fbc_hw_deactivate(dev_priv);
> }
>
> -static bool multiple_pipes_ok(struct intel_crtc *crtc)
> +static bool multiple_pipes_ok(struct intel_crtc *crtc,
> + struct intel_plane_state *plane_state)
> {
> - struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
> - struct drm_plane *primary = crtc->base.primary;
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_fbc *fbc = &dev_priv->fbc;
> enum pipe pipe = crtc->pipe;
>
> @@ -491,9 +491,7 @@ static bool multiple_pipes_ok(struct intel_crtc *crtc)
> if (!no_fbc_on_multiple_pipes(dev_priv))
> ret
Re: [Intel-gfx] [PATCH 13/19] drm/i915: Remove queue_flip pointer.
On Tue, Apr 19, 2016 at 09:52:33AM +0200, Maarten Lankhorst wrote:
> With the removal of cs support this is no longer reachable.
> Can be revived if needed.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_drv.h | 5 -
> drivers/gpu/drm/i915/intel_display.c | 259
> ---
> 2 files changed, 264 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fb19fee24584..22068d00c80e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -607,11 +607,6 @@ struct drm_i915_display_funcs {
> void (*audio_codec_disable)(struct intel_encoder *encoder);
> void (*fdi_link_train)(struct drm_crtc *crtc);
> void (*init_clock_gating)(struct drm_device *dev);
> - int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
> - struct drm_framebuffer *fb,
> - struct drm_i915_gem_object *obj,
> - struct drm_i915_gem_request *req,
> - uint64_t gtt_offset);
> void (*hpd_irq_setup)(struct drm_device *dev);
> /* clock updates for mode set */
> /* cursor updates */
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index b6e1b34bf6dd..cb899befb96b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11074,237 +11074,6 @@ void intel_finish_page_flip_plane(struct drm_device
> *dev, int plane)
> do_intel_finish_page_flip(dev, crtc);
> }
>
> -static int intel_gen2_queue_flip(struct drm_device *dev,
> - struct drm_crtc *crtc,
> - struct drm_framebuffer *fb,
> - struct drm_i915_gem_object *obj,
> - struct drm_i915_gem_request *req,
> - uint64_t gtt_offset)
> -{
> - struct intel_engine_cs *engine = req->engine;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - u32 flip_mask;
> - int ret;
> -
> - ret = intel_ring_begin(req, 6);
> - if (ret)
> - return ret;
> -
> - /* Can't queue multiple flips, so wait for the previous
> - * one to finish before executing the next.
> - */
> - if (intel_crtc->plane)
> - flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
> - else
> - flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
> - intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
> - intel_ring_emit(engine, MI_NOOP);
> - intel_ring_emit(engine, MI_DISPLAY_FLIP |
> - MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
> - intel_ring_emit(engine, fb->pitches[0]);
> - intel_ring_emit(engine, gtt_offset);
> - intel_ring_emit(engine, 0); /* aux display base address, unused */
> -
> - return 0;
> -}
> -
> -static int intel_gen3_queue_flip(struct drm_device *dev,
> - struct drm_crtc *crtc,
> - struct drm_framebuffer *fb,
> - struct drm_i915_gem_object *obj,
> - struct drm_i915_gem_request *req,
> - uint64_t gtt_offset)
> -{
> - struct intel_engine_cs *engine = req->engine;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - u32 flip_mask;
> - int ret;
> -
> - ret = intel_ring_begin(req, 6);
> - if (ret)
> - return ret;
> -
> - if (intel_crtc->plane)
> - flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
> - else
> - flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
> - intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
> - intel_ring_emit(engine, MI_NOOP);
> - intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
> - MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
> - intel_ring_emit(engine, fb->pitches[0]);
> - intel_ring_emit(engine, gtt_offset);
> - intel_ring_emit(engine, MI_NOOP);
> -
> - return 0;
> -}
> -
> -static int intel_gen4_queue_flip(struct drm_device *dev,
> - struct drm_crtc *crtc,
> - struct drm_framebuffer *fb,
> - struct drm_i915_gem_object *obj,
> - struct drm_i915_gem_request *req,
> - uint64_t gtt_offset)
> -{
> - struct intel_engine_cs *engine = req->engine;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> -
Re: [Intel-gfx] [PATCH 12/19] drm/i915: Remove use_mmio_flip kernel parameter.
On Tue, Apr 19, 2016 at 09:52:32AM +0200, Maarten Lankhorst wrote:
> With the removal of cs flips this is always force enabled.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_params.c | 5 -
> drivers/gpu/drm/i915/i915_params.h | 1 -
> drivers/gpu/drm/i915/intel_lrc.c | 3 +--
> 3 files changed, 1 insertion(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_params.c
> b/drivers/gpu/drm/i915/i915_params.c
> index 80ce581793dc..765a37376860 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -50,7 +50,6 @@ struct i915_params i915 __read_mostly = {
> .invert_brightness = 0,
> .disable_display = 0,
> .enable_cmd_parser = 1,
> - .use_mmio_flip = 0,
> .mmio_debug = 0,
> .verbose_state_checks = 1,
> .nuclear_pageflip = 0,
> @@ -179,10 +178,6 @@ module_param_named_unsafe(enable_cmd_parser,
> i915.enable_cmd_parser, int, 0600);
> MODULE_PARM_DESC(enable_cmd_parser,
>"Enable command parsing (1=enabled [default], 0=disabled)");
>
> -module_param_named_unsafe(use_mmio_flip, i915.use_mmio_flip, int, 0600);
> -MODULE_PARM_DESC(use_mmio_flip,
> - "use MMIO flips (-1=never, 0=driver discretion [default],
> 1=always)");
> -
> module_param_named(mmio_debug, i915.mmio_debug, int, 0600);
> MODULE_PARM_DESC(mmio_debug,
> "Enable the MMIO debug code for the first N failures (default: off). "
> diff --git a/drivers/gpu/drm/i915/i915_params.h
> b/drivers/gpu/drm/i915/i915_params.h
> index 3934c4300427..dae2dbd87147 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -46,7 +46,6 @@ struct i915_params {
> int invert_brightness;
> int enable_cmd_parser;
> int guc_log_level;
> - int use_mmio_flip;
> int mmio_debug;
> int edp_vswing;
> unsigned int inject_load_failure;
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 1562a75ac9d1..a62e1d9f21ef 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -256,8 +256,7 @@ int intel_sanitize_enable_execlists(struct drm_device
> *dev, int enable_execlists
> if (enable_execlists == 0)
> return 0;
>
> - if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
> - i915.use_mmio_flip >= 0)
> + if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev))
> return 1;
>
> return 0;
> --
> 2.1.0
>
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Re: [Intel-gfx] [PATCH] drm/i915/dmc: Step away from symbolic links
On Tue, May 10, 2016 at 03:52:02PM +0300, Mika Kuoppala wrote:
> Patrik Jakobsson writes:
>
> > [ text/plain ]
> > Load specific firmware versions for the DMC instead of using symbolic
> > links. The currently recommended versions are: SKL 1.26, KBL 1.01 and
> > BXT 1.07.
> >
>
> We should augment the commit message to answer the 'why' part.
>
> Otherwise, looks good.
Yes I agree. Where did this discussion take place? I don't believe I was
part of it. Rodrigo told me we've reached consensus on the decision but
that's all I know.
-Patrik
>
> -Mika
>
>
> > Cc: Rodrigo Vivi
> > Cc: Imre Deak
> > Cc: Mika Kuoppala
> > Signed-off-by: Patrik Jakobsson
> > ---
> > drivers/gpu/drm/i915/intel_csr.c | 29 ++---
> > 1 file changed, 14 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_csr.c
> > b/drivers/gpu/drm/i915/intel_csr.c
> > index 2b3b428..ea047cd 100644
> > --- a/drivers/gpu/drm/i915/intel_csr.c
> > +++ b/drivers/gpu/drm/i915/intel_csr.c
> > @@ -41,15 +41,15 @@
> > * be moved to FW_FAILED.
> > */
> >
> > -#define I915_CSR_KBL "i915/kbl_dmc_ver1.bin"
> > +#define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin"
> > MODULE_FIRMWARE(I915_CSR_KBL);
> > #define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1)
> >
> > -#define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
> > +#define I915_CSR_SKL "i915/skl_dmc_ver1_26.bin"
> > MODULE_FIRMWARE(I915_CSR_SKL);
> > -#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23)
> > +#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 26)
> >
> > -#define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
> > +#define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin"
> > MODULE_FIRMWARE(I915_CSR_BXT);
> > #define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
> >
> > @@ -286,7 +286,7 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
> > *dev_priv,
> > uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
> > uint32_t i;
> > uint32_t *dmc_payload;
> > - uint32_t required_min_version;
> > + uint32_t required_version;
> >
> > if (!fw)
> > return NULL;
> > @@ -303,24 +303,23 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
> > *dev_priv,
> > csr->version = css_header->version;
> >
> > if (IS_KABYLAKE(dev_priv)) {
> > - required_min_version = KBL_CSR_VERSION_REQUIRED;
> > + required_version = KBL_CSR_VERSION_REQUIRED;
> > } else if (IS_SKYLAKE(dev_priv)) {
> > - required_min_version = SKL_CSR_VERSION_REQUIRED;
> > + required_version = SKL_CSR_VERSION_REQUIRED;
> > } else if (IS_BROXTON(dev_priv)) {
> > - required_min_version = BXT_CSR_VERSION_REQUIRED;
> > + required_version = BXT_CSR_VERSION_REQUIRED;
> > } else {
> > MISSING_CASE(INTEL_REVID(dev_priv));
> > - required_min_version = 0;
> > + required_version = 0;
> > }
> >
> > - if (csr->version < required_min_version) {
> > - DRM_INFO("Refusing to load old DMC firmware v%u.%u,"
> > -" please upgrade to v%u.%u or later"
> > - " [" FIRMWARE_URL "].\n",
> > + if (csr->version != required_version) {
> > + DRM_INFO("Refusing to load DMC firmware v%u.%u,"
> > +" please use v%u.%u [" FIRMWARE_URL "].\n",
> > CSR_VERSION_MAJOR(csr->version),
> > CSR_VERSION_MINOR(csr->version),
> > -CSR_VERSION_MAJOR(required_min_version),
> > -CSR_VERSION_MINOR(required_min_version));
> > +CSR_VERSION_MAJOR(required_version),
> > +CSR_VERSION_MINOR(required_version));
> > return NULL;
> > }
> >
> > --
> > 2.5.0
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Re: [Intel-gfx] [PATCH 06/19] Revert "drm/i915: Avoid stalling on pending flips for legacy cursor updates"
On Tue, Apr 19, 2016 at 09:52:26AM +0200, Maarten Lankhorst wrote:
> This reverts commit acf4e84d6167317ff21be5c03e1ea76ea5783701.
> Unfortunately this breaks the next commit with a use-after-free, so
> temporarily revert until we can apply a solution.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 1d7ef9fb526c..8b61a07c4c52 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13461,9 +13461,6 @@ static int intel_atomic_prepare_commit(struct
> drm_device *dev,
> }
>
> for_each_crtc_in_state(state, crtc, crtc_state, i) {
> - if (state->legacy_cursor_update)
> - continue;
> -
> ret = intel_crtc_wait_for_pending_flips(crtc);
> if (ret)
> return ret;
> --
> 2.1.0
>
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Re: [Intel-gfx] [PATCH 04/19] drm/i915: Add support for detecting vblanks when hw frame counter is unavailable.
On Wed, Apr 27, 2016 at 05:23:06PM +0300, Ville Syrjälä wrote:
> On Wed, Apr 27, 2016 at 04:06:16PM +0200, Patrik Jakobsson wrote:
> > On Tue, Apr 19, 2016 at 09:52:24AM +0200, Maarten Lankhorst wrote:
> > > This uses the newly created drm_accurate_vblank_count_and_time to
> > > accurately
> > > get a vblank count when the hw counter is unavailable.
> > > ---
> > > drivers/gpu/drm/i915/intel_display.c | 10 ++
> > > drivers/gpu/drm/i915/intel_drv.h | 3 +++
> > > drivers/gpu/drm/i915/intel_sprite.c | 8 ++--
> > > 3 files changed, 15 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index ccbc2a448258..2086e8bd10da 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -13530,6 +13530,16 @@ static int intel_atomic_prepare_commit(struct
> > > drm_device *dev,
> > > return ret;
> > > }
> > >
> > > +u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
> > > +{
> > > + struct drm_device *dev = crtc->base.dev;
> > > +
> > > + if (!dev->max_vblank_count)
> > > + return drm_accurate_vblank_count(&crtc->base);
> > > +
> > > + return dev->driver->get_vblank_counter(dev, crtc->pipe);
> > > +}
> > > +
> > > static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
> > > struct drm_i915_private *dev_priv,
> > > unsigned crtc_mask)
> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > b/drivers/gpu/drm/i915/intel_drv.h
> > > index fecc89600667..8efeb90eac07 100644
> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > @@ -1146,6 +1146,9 @@ intel_wait_for_vblank_if_active(struct drm_device
> > > *dev, int pipe)
> > > if (crtc->active)
> > > intel_wait_for_vblank(dev, pipe);
> > > }
> > > +
> > > +u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
> > > +
> > > int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
> > > void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
> > >struct intel_digital_port *dport,
> > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > > b/drivers/gpu/drm/i915/intel_sprite.c
> > > index 0f3e2303e0e9..e2de6b0df5a8 100644
> > > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > > @@ -80,9 +80,7 @@ static int usecs_to_scanlines(const struct
> > > drm_display_mode *adjusted_mode,
> > > */
> > > void intel_pipe_update_start(struct intel_crtc *crtc)
> > > {
> > > - struct drm_device *dev = crtc->base.dev;
> > > const struct drm_display_mode *adjusted_mode =
> > > &crtc->config->base.adjusted_mode;
> > > - enum pipe pipe = crtc->pipe;
> > > long timeout = msecs_to_jiffies_timeout(1);
> > > int scanline, min, max, vblank_start;
> > > wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
> > > @@ -139,8 +137,7 @@ void intel_pipe_update_start(struct intel_crtc *crtc)
> > >
> > > crtc->debug.scanline_start = scanline;
> > > crtc->debug.start_vbl_time = ktime_get();
> > > - crtc->debug.start_vbl_count =
> > > - dev->driver->get_vblank_counter(dev, pipe);
> > > + crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
> > >
> > > trace_i915_pipe_update_vblank_evaded(crtc);
> > > }
> > > @@ -156,10 +153,9 @@ void intel_pipe_update_start(struct intel_crtc *crtc)
> > > */
> > > void intel_pipe_update_end(struct intel_crtc *crtc)
> > > {
> > > - struct drm_device *dev = crtc->base.dev;
> > > enum pipe pipe = crtc->pipe;
> > > int scanline_end = intel_get_crtc_scanline(crtc);
> > > - u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
> > > + u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
> > > ktime_t end_vbl_time = ktime_get();
> > >
> > > trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
> >
> > Do we need to use intel_crtc_get_vblank_counter() in
> > display_pipe_crc_irq_handler() as well?
>
>
[Intel-gfx] [PATCH] drm/i915/dmc: Step away from symbolic links
Load specific firmware versions for the DMC instead of using symbolic
links. The currently recommended versions are: SKL 1.26, KBL 1.01 and
BXT 1.07.
Cc: Rodrigo Vivi
Cc: Imre Deak
Cc: Mika Kuoppala
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/intel_csr.c | 29 ++---
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 2b3b428..ea047cd 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -41,15 +41,15 @@
* be moved to FW_FAILED.
*/
-#define I915_CSR_KBL "i915/kbl_dmc_ver1.bin"
+#define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin"
MODULE_FIRMWARE(I915_CSR_KBL);
#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1)
-#define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
+#define I915_CSR_SKL "i915/skl_dmc_ver1_26.bin"
MODULE_FIRMWARE(I915_CSR_SKL);
-#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23)
+#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 26)
-#define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
+#define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin"
MODULE_FIRMWARE(I915_CSR_BXT);
#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
@@ -286,7 +286,7 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
*dev_priv,
uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
uint32_t i;
uint32_t *dmc_payload;
- uint32_t required_min_version;
+ uint32_t required_version;
if (!fw)
return NULL;
@@ -303,24 +303,23 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
*dev_priv,
csr->version = css_header->version;
if (IS_KABYLAKE(dev_priv)) {
- required_min_version = KBL_CSR_VERSION_REQUIRED;
+ required_version = KBL_CSR_VERSION_REQUIRED;
} else if (IS_SKYLAKE(dev_priv)) {
- required_min_version = SKL_CSR_VERSION_REQUIRED;
+ required_version = SKL_CSR_VERSION_REQUIRED;
} else if (IS_BROXTON(dev_priv)) {
- required_min_version = BXT_CSR_VERSION_REQUIRED;
+ required_version = BXT_CSR_VERSION_REQUIRED;
} else {
MISSING_CASE(INTEL_REVID(dev_priv));
- required_min_version = 0;
+ required_version = 0;
}
- if (csr->version < required_min_version) {
- DRM_INFO("Refusing to load old DMC firmware v%u.%u,"
-" please upgrade to v%u.%u or later"
- " [" FIRMWARE_URL "].\n",
+ if (csr->version != required_version) {
+ DRM_INFO("Refusing to load DMC firmware v%u.%u,"
+" please use v%u.%u [" FIRMWARE_URL "].\n",
CSR_VERSION_MAJOR(csr->version),
CSR_VERSION_MINOR(csr->version),
-CSR_VERSION_MAJOR(required_min_version),
-CSR_VERSION_MINOR(required_min_version));
+CSR_VERSION_MAJOR(required_version),
+CSR_VERSION_MINOR(required_version));
return NULL;
}
--
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Re: [Intel-gfx] [PATCH 02/19] drm/i915: Remove stallcheck special handling, v2.
On Thu, Apr 28, 2016 at 12:20:09PM +0200, Maarten Lankhorst wrote:
> Op 28-04-16 om 11:54 schreef Patrik Jakobsson:
> > On Thu, Apr 28, 2016 at 10:48:55AM +0200, Maarten Lankhorst wrote:
> >> Op 27-04-16 om 15:24 schreef Patrik Jakobsson:
> >>> On Tue, Apr 19, 2016 at 09:52:22AM +0200, Maarten Lankhorst wrote:
> >>>> Both intel_unpin_work.pending and intel_unpin_work.enable_stall_check
> >>>> were used to see if work should be enabled. By only using pending
> >>>> some special cases are gone, and access to unpin_work can be simplified.
> >>>>
> >>>> Use this to only access work members untilintel_mark_page_flip_active
> >>>> is called, or intel_queue_mmio_flip is used. This will prevent
> >>>> use-after-free, and makes it easier to verify accesses.
> >>>>
> >>>> Changes since v1:
> >>>> - Reword commit message.
> >>>> - Do not access unpin_work after intel_mark_page_flip_active.
> >>>> - Add the right memory barriers.
> >>>>
> >>>> Signed-off-by: Maarten Lankhorst
> >>>> ---
> >>>> drivers/gpu/drm/i915/i915_debugfs.c | 11 +++---
> >>>> drivers/gpu/drm/i915/intel_display.c | 71
> >>>> ++--
> >>>> drivers/gpu/drm/i915/intel_drv.h | 1 -
> >>>> 3 files changed, 34 insertions(+), 49 deletions(-)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> >>>> b/drivers/gpu/drm/i915/i915_debugfs.c
> >>>> index 931dc6086f3b..0092aaf47c43 100644
> >>>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> >>>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> >>>> @@ -612,9 +612,14 @@ static int i915_gem_pageflip_info(struct seq_file
> >>>> *m, void *data)
> >>>> seq_printf(m, "No flip due on pipe %c (plane
> >>>> %c)\n",
> >>>> pipe, plane);
> >>>> } else {
> >>>> +u32 pending;
> >>>> u32 addr;
> >>>>
> >>>> -if (atomic_read(&work->pending) <
> >>>> INTEL_FLIP_COMPLETE) {
> >>>> +pending = atomic_read(&work->pending);
> >>>> +if (pending == INTEL_FLIP_INACTIVE) {
> >>>> +seq_printf(m, "Flip ioctl preparing on
> >>>> pipe %c (plane %c)\n",
> >>>> + pipe, plane);
> >>>> +} else if (pending >= INTEL_FLIP_COMPLETE) {
> >>>> seq_printf(m, "Flip queued on pipe %c
> >>>> (plane %c)\n",
> >>>> pipe, plane);
> >>>> } else {
> >>>> @@ -636,10 +641,6 @@ static int i915_gem_pageflip_info(struct seq_file
> >>>> *m, void *data)
> >>>> work->flip_queued_vblank,
> >>>> work->flip_ready_vblank,
> >>>> drm_crtc_vblank_count(&crtc->base));
> >>>> -if (work->enable_stall_check)
> >>>> -seq_puts(m, "Stall check enabled, ");
> >>>> -else
> >>>> -seq_puts(m, "Stall check waiting for
> >>>> page flip ioctl, ");
> >>>> seq_printf(m, "%d prepares\n",
> >>>> atomic_read(&work->pending));
> >>>>
> >>>> if (INTEL_INFO(dev)->gen >= 4)
> >>>> diff --git a/drivers/gpu/drm/i915/intel_display.c
> >>>> b/drivers/gpu/drm/i915/intel_display.c
> >>>> index 4cb830e2a62e..97a8418f6539 100644
> >>>> --- a/drivers/gpu/drm/i915/intel_display.c
> >>>> +++ b/drivers/gpu/drm/i915/intel_display.c
> >>>> @@ -3896,8 +3896,6 @@ static void page_flip_completed(struct intel_crtc
> >>>> *intel_crtc)
> >>>> struct drm_i915_private *dev_priv =
> >>>> to_i915(intel_crtc->base.dev);
Re: [Intel-gfx] [PATCH 09/19] drm/i915: Add the exclusive fence to plane_state.
On Tue, Apr 19, 2016 at 09:52:29AM +0200, Maarten Lankhorst wrote:
> Set plane_state->base.fence to the dma_buf exclusive fence,
> and add a wait to the mmio function. This will make it easier
> to unify plane updates later on.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_atomic_plane.c | 1 +
> drivers/gpu/drm/i915/intel_display.c | 54
> +++
> 2 files changed, 42 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index 7de7721f65bc..2ab45f16fa65 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -102,6 +102,7 @@ intel_plane_destroy_state(struct drm_plane *plane,
> struct drm_plane_state *state)
> {
> WARN_ON(state && to_intel_plane_state(state)->wait_req);
> + WARN_ON(state && state->fence);
> drm_atomic_helper_plane_destroy_state(plane, state);
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index a2b4be06eb84..0586f1235ae3 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13411,6 +13411,15 @@ static int intel_atomic_prepare_commit(struct
> drm_device *dev,
> struct intel_plane_state *intel_plane_state =
> to_intel_plane_state(plane_state);
>
> + if (plane_state->fence) {
> + long lret = fence_wait(plane_state->fence,
> true);
> +
> + if (lret < 0) {
> + ret = lret;
> + break;
> + }
> + }
> +
> if (!intel_plane_state->wait_req)
> continue;
>
> @@ -13735,6 +13744,33 @@ static const struct drm_crtc_funcs intel_crtc_funcs
> = {
> .atomic_destroy_state = intel_crtc_destroy_state,
> };
>
> +static struct fence *intel_get_excl_fence(struct drm_i915_gem_object *obj)
> +{
> + struct reservation_object *resv;
> +
> +
> + if (!obj->base.dma_buf)
> + return NULL;
> +
> + resv = obj->base.dma_buf->resv;
> +
> + /* For framebuffer backed by dmabuf, wait for fence */
> + while (1) {
> + struct fence *fence_excl, *ret = NULL;
> +
> + rcu_read_lock();
> +
> + fence_excl = rcu_dereference(resv->fence_excl);
> + if (fence_excl)
> + ret = fence_get_rcu(fence_excl);
> +
> + rcu_read_unlock();
> +
> + if (ret == fence_excl)
> + return ret;
> + }
> +}
> +
> /**
> * intel_prepare_plane_fb - Prepare fb for usage on plane
> * @plane: drm plane to prepare for
> @@ -13787,19 +13823,6 @@ intel_prepare_plane_fb(struct drm_plane *plane,
> }
> }
>
> - /* For framebuffer backed by dmabuf, wait for fence */
> - if (obj && obj->base.dma_buf) {
> - long lret;
> -
> - lret =
> reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
> -false, true,
> -
> MAX_SCHEDULE_TIMEOUT);
> - if (lret == -ERESTARTSYS)
> - return lret;
> -
> - WARN(lret < 0, "waiting returns %li\n", lret);
> - }
> -
> if (!obj) {
> ret = 0;
> } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
> @@ -13819,6 +13842,8 @@ intel_prepare_plane_fb(struct drm_plane *plane,
>
> i915_gem_request_assign(&plane_state->wait_req,
> obj->last_write_req);
> +
> + plane_state->base.fence = intel_get_excl_fence(obj);
> }
>
> i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
> @@ -13861,6 +13886,9 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
> i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
>
> i915_gem_request_assign(&old_intel_state->wait_req, NULL);
> +
> + fence_put(old_intel_state->base.fence);
> + old_intel_state->base.fence = NULL;
> }
>
> int
> --
> 2.1.0
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Intel Sweden AB Registered Office: Knarrarnasgatan 15, 164 40 Kista, Stockholm,
Sweden Registration Number: 556189-6027
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/19] drm/i915: Convert flip_work to a list.
On Tue, Apr 19, 2016 at 09:52:28AM +0200, Maarten Lankhorst wrote:
> This will be required to allow more than 1 update in the future.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 90 +-
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 105
> ---
> drivers/gpu/drm/i915/intel_drv.h | 4 +-
> 4 files changed, 114 insertions(+), 87 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index aabd7a13cec7..513c7da24c3d 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -589,6 +589,53 @@ static int i915_gem_gtt_info(struct seq_file *m, void
> *data)
> return 0;
> }
>
> +static void i915_dump_pageflip(struct seq_file *m,
> +struct drm_i915_private *dev_priv,
> +struct intel_crtc *crtc,
> +struct intel_flip_work *work)
> +{
> + const char pipe = pipe_name(crtc->pipe);
> + const char plane = plane_name(crtc->plane);
> + u32 pending;
> + u32 addr;
> +
> + pending = atomic_read(&work->pending);
> + if (pending == INTEL_FLIP_INACTIVE) {
> + seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
> +pipe, plane);
> + } else {
> + seq_printf(m, "Flip pending (waiting for vsync) on pipe %c
> (plane %c)\n",
> +pipe, plane);
> + }
> + if (work->flip_queued_req) {
> + struct intel_engine_cs *engine =
> i915_gem_request_get_engine(work->flip_queued_req);
> +
> + seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x
> [current breadcrumb %x], completed? %d\n",
> +engine->name,
> +i915_gem_request_get_seqno(work->flip_queued_req),
> +dev_priv->next_seqno,
> +engine->get_seqno(engine),
> +i915_gem_request_completed(work->flip_queued_req,
> true));
> + } else
> + seq_printf(m, "Flip not associated with any ring\n");
> + seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now
> %d\n",
> +work->flip_queued_vblank,
> +work->flip_ready_vblank,
> +intel_crtc_get_vblank_counter(crtc));
> + seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
> +
> + if (INTEL_INFO(dev_priv)->gen >= 4)
> + addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
> + else
> + addr = I915_READ(DSPADDR(crtc->plane));
> + seq_printf(m, "Current scanout address 0x%08x\n", addr);
> +
> + if (work->pending_flip_obj) {
> + seq_printf(m, "New framebuffer address 0x%08lx\n",
> (long)work->gtt_offset);
> + seq_printf(m, "MMIO update completed? %d\n", addr ==
> work->gtt_offset);
> + }
> +}
> +
> static int i915_gem_pageflip_info(struct seq_file *m, void *data)
> {
> struct drm_info_node *node = m->private;
> @@ -607,48 +654,13 @@ static int i915_gem_pageflip_info(struct seq_file *m,
> void *data)
> struct intel_flip_work *work;
>
> spin_lock_irq(&dev->event_lock);
> - work = crtc->flip_work;
> - if (work == NULL) {
> + if (list_empty(&crtc->flip_work)) {
> seq_printf(m, "No flip due on pipe %c (plane %c)\n",
> pipe, plane);
> } else {
> - u32 pending;
> - u32 addr;
> -
> - pending = atomic_read(&work->pending);
> - if (pending == INTEL_FLIP_INACTIVE) {
> - seq_printf(m, "Flip ioctl preparing on pipe %c
> (plane %c)\n",
> -pipe, plane);
> - } else {
> - seq_printf(m, "Flip pending (waiting for vsync)
> on pipe %c (plane %c)\n",
> -pipe, plane);
> - }
> - if (work->flip_queued_req) {
> - struct intel_engine_cs *engine =
> i915_gem_request_get_engine(work->flip_queued_req);
> -
> - seq_printf(m, "Flip queued on %s at seqno %x,
> next seqno %x [current breadcrumb %x], completed? %d\n",
> -engine->name,
> -
> i915_gem_request_get_seqno(work->flip_queued_req),
> -dev_priv->next_seqno,
> -engine->get_seqno(engine),
> -
> i915_gem_request_completed(work->flip_queued_req, true));
> - } else
> -
Re: [Intel-gfx] [PATCH 05/19] drm/i915: Unify unpin_work and mmio_work into flip_work.
On Tue, Apr 19, 2016 at 09:52:25AM +0200, Maarten Lankhorst wrote:
> Rename intel_unpin_work to intel_flip_work and use it for mmio flips
> and unpinning. Use flip_queued_req to hold the wait request in the
> mmio case, and the vblank counter from intel_crtc_get_vblank_counter.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 6 +-
> drivers/gpu/drm/i915/intel_display.c | 189
> +++
> drivers/gpu/drm/i915/intel_drv.h | 19 ++--
> drivers/gpu/drm/i915/intel_sprite.c | 8 +-
> 4 files changed, 98 insertions(+), 124 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index def95532d421..aabd7a13cec7 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -604,10 +604,10 @@ static int i915_gem_pageflip_info(struct seq_file *m,
> void *data)
> for_each_intel_crtc(dev, crtc) {
> const char pipe = pipe_name(crtc->pipe);
> const char plane = plane_name(crtc->plane);
> - struct intel_unpin_work *work;
> + struct intel_flip_work *work;
>
> spin_lock_irq(&dev->event_lock);
> - work = crtc->unpin_work;
> + work = crtc->flip_work;
> if (work == NULL) {
> seq_printf(m, "No flip due on pipe %c (plane %c)\n",
> pipe, plane);
> @@ -637,7 +637,7 @@ static int i915_gem_pageflip_info(struct seq_file *m,
> void *data)
> seq_printf(m, "Flip queued on frame %d, (was ready on
> frame %d), now %d\n",
> work->flip_queued_vblank,
> work->flip_ready_vblank,
> -drm_crtc_vblank_count(&crtc->base));
> +intel_crtc_get_vblank_counter(crtc));
> seq_printf(m, "%d prepares\n",
> atomic_read(&work->pending));
>
> if (INTEL_INFO(dev)->gen >= 4)
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 2086e8bd10da..1d7ef9fb526c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -48,6 +48,11 @@
> #include
> #include
>
> +static bool is_mmio_work(struct intel_flip_work *work)
> +{
> + return work->mmio_work.func;
> +}
> +
> /* Primary plane formats for gen <= 3 */
> static const uint32_t i8xx_primary_formats[] = {
> DRM_FORMAT_C8,
> @@ -3302,7 +3307,7 @@ static bool intel_crtc_has_pending_flip(struct drm_crtc
> *crtc)
> return false;
>
> spin_lock_irq(&dev->event_lock);
> - pending = to_intel_crtc(crtc)->unpin_work != NULL;
> + pending = to_intel_crtc(crtc)->flip_work != NULL;
> spin_unlock_irq(&dev->event_lock);
>
> return pending;
> @@ -3881,7 +3886,7 @@ bool intel_has_pending_fb_unpin(struct drm_device *dev)
> if (atomic_read(&crtc->unpin_work_count) == 0)
> continue;
>
> - if (crtc->unpin_work)
> + if (crtc->flip_work)
> intel_wait_for_vblank(dev, crtc->pipe);
>
> return true;
> @@ -3893,9 +3898,9 @@ bool intel_has_pending_fb_unpin(struct drm_device *dev)
> static void page_flip_completed(struct intel_crtc *intel_crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> - struct intel_unpin_work *work = intel_crtc->unpin_work;
> + struct intel_flip_work *work = intel_crtc->flip_work;
>
> - intel_crtc->unpin_work = NULL;
> + intel_crtc->flip_work = NULL;
>
> if (work->event)
> drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
> @@ -3903,7 +3908,7 @@ static void page_flip_completed(struct intel_crtc
> *intel_crtc)
> drm_crtc_vblank_put(&intel_crtc->base);
>
> wake_up_all(&dev_priv->pending_flip_queue);
> - queue_work(dev_priv->wq, &work->work);
> + queue_work(dev_priv->wq, &work->unpin_work);
>
> trace_i915_flip_complete(intel_crtc->plane,
>work->pending_flip_obj);
> @@ -3927,9 +3932,11 @@ static int intel_crtc_wait_for_pending_flips(struct
> drm_crtc *crtc)
>
> if (ret == 0) {
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +
Re: [Intel-gfx] [PATCH 02/19] drm/i915: Remove stallcheck special handling, v2.
On Thu, Apr 28, 2016 at 10:48:55AM +0200, Maarten Lankhorst wrote:
> Op 27-04-16 om 15:24 schreef Patrik Jakobsson:
> > On Tue, Apr 19, 2016 at 09:52:22AM +0200, Maarten Lankhorst wrote:
> >> Both intel_unpin_work.pending and intel_unpin_work.enable_stall_check
> >> were used to see if work should be enabled. By only using pending
> >> some special cases are gone, and access to unpin_work can be simplified.
> >>
> >> Use this to only access work members untilintel_mark_page_flip_active
> >> is called, or intel_queue_mmio_flip is used. This will prevent
> >> use-after-free, and makes it easier to verify accesses.
> >>
> >> Changes since v1:
> >> - Reword commit message.
> >> - Do not access unpin_work after intel_mark_page_flip_active.
> >> - Add the right memory barriers.
> >>
> >> Signed-off-by: Maarten Lankhorst
> >> ---
> >> drivers/gpu/drm/i915/i915_debugfs.c | 11 +++---
> >> drivers/gpu/drm/i915/intel_display.c | 71
> >> ++--
> >> drivers/gpu/drm/i915/intel_drv.h | 1 -
> >> 3 files changed, 34 insertions(+), 49 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> >> b/drivers/gpu/drm/i915/i915_debugfs.c
> >> index 931dc6086f3b..0092aaf47c43 100644
> >> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> >> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> >> @@ -612,9 +612,14 @@ static int i915_gem_pageflip_info(struct seq_file *m,
> >> void *data)
> >>seq_printf(m, "No flip due on pipe %c (plane %c)\n",
> >> pipe, plane);
> >>} else {
> >> + u32 pending;
> >>u32 addr;
> >>
> >> - if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
> >> + pending = atomic_read(&work->pending);
> >> + if (pending == INTEL_FLIP_INACTIVE) {
> >> + seq_printf(m, "Flip ioctl preparing on pipe %c
> >> (plane %c)\n",
> >> + pipe, plane);
> >> + } else if (pending >= INTEL_FLIP_COMPLETE) {
> >>seq_printf(m, "Flip queued on pipe %c (plane
> >> %c)\n",
> >> pipe, plane);
> >>} else {
> >> @@ -636,10 +641,6 @@ static int i915_gem_pageflip_info(struct seq_file *m,
> >> void *data)
> >> work->flip_queued_vblank,
> >> work->flip_ready_vblank,
> >> drm_crtc_vblank_count(&crtc->base));
> >> - if (work->enable_stall_check)
> >> - seq_puts(m, "Stall check enabled, ");
> >> - else
> >> - seq_puts(m, "Stall check waiting for page flip
> >> ioctl, ");
> >>seq_printf(m, "%d prepares\n",
> >> atomic_read(&work->pending));
> >>
> >>if (INTEL_INFO(dev)->gen >= 4)
> >> diff --git a/drivers/gpu/drm/i915/intel_display.c
> >> b/drivers/gpu/drm/i915/intel_display.c
> >> index 4cb830e2a62e..97a8418f6539 100644
> >> --- a/drivers/gpu/drm/i915/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/intel_display.c
> >> @@ -3896,8 +3896,6 @@ static void page_flip_completed(struct intel_crtc
> >> *intel_crtc)
> >>struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> >>struct intel_unpin_work *work = intel_crtc->unpin_work;
> >>
> >> - /* ensure that the unpin work is consistent wrt ->pending. */
> >> - smp_rmb();
> >>intel_crtc->unpin_work = NULL;
> >>
> >>if (work->event)
> >> @@ -10980,16 +10978,13 @@ static void do_intel_finish_page_flip(struct
> >> drm_device *dev,
> >>spin_lock_irqsave(&dev->event_lock, flags);
> >>work = intel_crtc->unpin_work;
> >>
> >> - /* Ensure we don't miss a work->pending update ... */
> >> - smp_rmb();
> >> + if (work && atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) {
> >> + /* ensure that the unpin work is consistent wrt ->pending. */
> >> + smp
Re: [Intel-gfx] [PATCH 04/19] drm/i915: Add support for detecting vblanks when hw frame counter is unavailable.
On Tue, Apr 19, 2016 at 09:52:24AM +0200, Maarten Lankhorst wrote:
> This uses the newly created drm_accurate_vblank_count_and_time to accurately
> get a vblank count when the hw counter is unavailable.
> ---
> drivers/gpu/drm/i915/intel_display.c | 10 ++
> drivers/gpu/drm/i915/intel_drv.h | 3 +++
> drivers/gpu/drm/i915/intel_sprite.c | 8 ++--
> 3 files changed, 15 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index ccbc2a448258..2086e8bd10da 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13530,6 +13530,16 @@ static int intel_atomic_prepare_commit(struct
> drm_device *dev,
> return ret;
> }
>
> +u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
> +{
> + struct drm_device *dev = crtc->base.dev;
> +
> + if (!dev->max_vblank_count)
> + return drm_accurate_vblank_count(&crtc->base);
> +
> + return dev->driver->get_vblank_counter(dev, crtc->pipe);
> +}
> +
> static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
> struct drm_i915_private *dev_priv,
> unsigned crtc_mask)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index fecc89600667..8efeb90eac07 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1146,6 +1146,9 @@ intel_wait_for_vblank_if_active(struct drm_device *dev,
> int pipe)
> if (crtc->active)
> intel_wait_for_vblank(dev, pipe);
> }
> +
> +u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
> +
> int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
> void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
>struct intel_digital_port *dport,
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 0f3e2303e0e9..e2de6b0df5a8 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -80,9 +80,7 @@ static int usecs_to_scanlines(const struct drm_display_mode
> *adjusted_mode,
> */
> void intel_pipe_update_start(struct intel_crtc *crtc)
> {
> - struct drm_device *dev = crtc->base.dev;
> const struct drm_display_mode *adjusted_mode =
> &crtc->config->base.adjusted_mode;
> - enum pipe pipe = crtc->pipe;
> long timeout = msecs_to_jiffies_timeout(1);
> int scanline, min, max, vblank_start;
> wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
> @@ -139,8 +137,7 @@ void intel_pipe_update_start(struct intel_crtc *crtc)
>
> crtc->debug.scanline_start = scanline;
> crtc->debug.start_vbl_time = ktime_get();
> - crtc->debug.start_vbl_count =
> - dev->driver->get_vblank_counter(dev, pipe);
> + crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
>
> trace_i915_pipe_update_vblank_evaded(crtc);
> }
> @@ -156,10 +153,9 @@ void intel_pipe_update_start(struct intel_crtc *crtc)
> */
> void intel_pipe_update_end(struct intel_crtc *crtc)
> {
> - struct drm_device *dev = crtc->base.dev;
> enum pipe pipe = crtc->pipe;
> int scanline_end = intel_get_crtc_scanline(crtc);
> - u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
> + u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
> ktime_t end_vbl_time = ktime_get();
>
> trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
Do we need to use intel_crtc_get_vblank_counter() in
display_pipe_crc_irq_handler() as well?
> --
> 2.1.0
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 02/19] drm/i915: Remove stallcheck special handling, v2.
On Tue, Apr 19, 2016 at 09:52:22AM +0200, Maarten Lankhorst wrote:
> Both intel_unpin_work.pending and intel_unpin_work.enable_stall_check
> were used to see if work should be enabled. By only using pending
> some special cases are gone, and access to unpin_work can be simplified.
>
> Use this to only access work members untilintel_mark_page_flip_active
> is called, or intel_queue_mmio_flip is used. This will prevent
> use-after-free, and makes it easier to verify accesses.
>
> Changes since v1:
> - Reword commit message.
> - Do not access unpin_work after intel_mark_page_flip_active.
> - Add the right memory barriers.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 11 +++---
> drivers/gpu/drm/i915/intel_display.c | 71
> ++--
> drivers/gpu/drm/i915/intel_drv.h | 1 -
> 3 files changed, 34 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 931dc6086f3b..0092aaf47c43 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -612,9 +612,14 @@ static int i915_gem_pageflip_info(struct seq_file *m,
> void *data)
> seq_printf(m, "No flip due on pipe %c (plane %c)\n",
> pipe, plane);
> } else {
> + u32 pending;
> u32 addr;
>
> - if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
> + pending = atomic_read(&work->pending);
> + if (pending == INTEL_FLIP_INACTIVE) {
> + seq_printf(m, "Flip ioctl preparing on pipe %c
> (plane %c)\n",
> +pipe, plane);
> + } else if (pending >= INTEL_FLIP_COMPLETE) {
> seq_printf(m, "Flip queued on pipe %c (plane
> %c)\n",
> pipe, plane);
> } else {
> @@ -636,10 +641,6 @@ static int i915_gem_pageflip_info(struct seq_file *m,
> void *data)
> work->flip_queued_vblank,
> work->flip_ready_vblank,
> drm_crtc_vblank_count(&crtc->base));
> - if (work->enable_stall_check)
> - seq_puts(m, "Stall check enabled, ");
> - else
> - seq_puts(m, "Stall check waiting for page flip
> ioctl, ");
> seq_printf(m, "%d prepares\n",
> atomic_read(&work->pending));
>
> if (INTEL_INFO(dev)->gen >= 4)
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 4cb830e2a62e..97a8418f6539 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3896,8 +3896,6 @@ static void page_flip_completed(struct intel_crtc
> *intel_crtc)
> struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> struct intel_unpin_work *work = intel_crtc->unpin_work;
>
> - /* ensure that the unpin work is consistent wrt ->pending. */
> - smp_rmb();
> intel_crtc->unpin_work = NULL;
>
> if (work->event)
> @@ -10980,16 +10978,13 @@ static void do_intel_finish_page_flip(struct
> drm_device *dev,
> spin_lock_irqsave(&dev->event_lock, flags);
> work = intel_crtc->unpin_work;
>
> - /* Ensure we don't miss a work->pending update ... */
> - smp_rmb();
> + if (work && atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) {
> + /* ensure that the unpin work is consistent wrt ->pending. */
> + smp_mb__after_atomic();
The docs on smp_mb__after/before_atomic() states that they are used with atomic
functions that do not return a value. Why are we using it together with
atomic_read() here?
>
> - if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
> - spin_unlock_irqrestore(&dev->event_lock, flags);
> - return;
> + page_flip_completed(intel_crtc);
> }
>
> - page_flip_completed(intel_crtc);
> -
> spin_unlock_irqrestore(&dev->event_lock, flags);
> }
>
> @@ -11087,10 +11082,8 @@ void intel_prepare_page_flip(struct drm_device *dev,
> int plane)
> static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
> {
> /* Ensure that the work item is consistent when activating it ... */
> - smp_wmb();
> + smp_mb__before_atomic();
> atomic_set(&work->pending, INTEL_FLIP_PENDING);
> - /* and that it is marked active as soon as the irq could fire. */
> - smp_wmb();
> }
>
> static int intel_gen2_queue_flip(struct drm_device *dev,
> @@ -11124,7 +7,6 @@ static int intel_gen2_queue_flip(struct drm_device
> *dev,
> intel_ring_emit(engine, intel_crtc->unp
Re: [Intel-gfx] [PATCH] drm/i915/kbl: Introduce the first official DMC for Kabylake.
On Tue, Apr 26, 2016 at 11:59 PM, Rodrigo Vivi wrote:
> Version 1.01.
>
> This firmware is made for Kabylake platform so it doesn't
> need the stepping workaround that we had before.
>
> v2: Rebased on top of latest nightly with min version
> required change.
> v3: With right CSR_VERSION (Patrik).
>
> Cc: Christophe Prigent
> Cc: Patrik Jakobsson
> Reviewed-by: Ben Widawsky (v1)
> Signed-off-by: Rodrigo Vivi
As discussed on IRC, feel free to push this when satisfied with testing.
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_csr.c | 30 +++---
> 1 file changed, 19 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_csr.c
> b/drivers/gpu/drm/i915/intel_csr.c
> index a34c23e..2b3b428 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -41,16 +41,22 @@
> * be moved to FW_FAILED.
> */
>
> +#define I915_CSR_KBL "i915/kbl_dmc_ver1.bin"
> +MODULE_FIRMWARE(I915_CSR_KBL);
> +#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1)
> +
> #define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
> +MODULE_FIRMWARE(I915_CSR_SKL);
> +#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23)
> +
> #define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
> +MODULE_FIRMWARE(I915_CSR_BXT);
> +#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
>
> #define FIRMWARE_URL
> "https://01.org/linuxgraphics/intel-linux-graphics-firmwares";
>
> -MODULE_FIRMWARE(I915_CSR_SKL);
> -MODULE_FIRMWARE(I915_CSR_BXT);
>
> -#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23)
> -#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
> +
>
> #define CSR_MAX_FW_SIZE0x2FFF
> #define CSR_DEFAULT_FW_OFFSET 0x
> @@ -169,12 +175,10 @@ struct stepping_info {
> char substepping;
> };
>
> -/*
> - * Kabylake derivated from Skylake H0, so SKL H0
> - * is the right firmware for KBL A0 (revid 0).
> - */
> static const struct stepping_info kbl_stepping_info[] = {
> - {'H', '0'}, {'I', '0'}
> + {'A', '0'}, {'B', '0'}, {'C', '0'},
> + {'D', '0'}, {'E', '0'}, {'F', '0'},
> + {'G', '0'}, {'H', '0'}, {'I', '0'},
> };
>
> static const struct stepping_info skl_stepping_info[] = {
> @@ -298,7 +302,9 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
> *dev_priv,
>
> csr->version = css_header->version;
>
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> + if (IS_KABYLAKE(dev_priv)) {
> + required_min_version = KBL_CSR_VERSION_REQUIRED;
> + } else if (IS_SKYLAKE(dev_priv)) {
> required_min_version = SKL_CSR_VERSION_REQUIRED;
> } else if (IS_BROXTON(dev_priv)) {
> required_min_version = BXT_CSR_VERSION_REQUIRED;
> @@ -446,7 +452,9 @@ void intel_csr_ucode_init(struct drm_i915_private
> *dev_priv)
> if (!HAS_CSR(dev_priv))
> return;
>
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> + if (IS_KABYLAKE(dev_priv))
> + csr->fw_path = I915_CSR_KBL;
> + else if (IS_SKYLAKE(dev_priv))
> csr->fw_path = I915_CSR_SKL;
> else if (IS_BROXTON(dev_priv))
> csr->fw_path = I915_CSR_BXT;
> --
> 2.4.3
>
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Re: [Intel-gfx] [PATCH] drm/i915/kbl: Introduce the first official DMC for Kabylake.
On Tue, Apr 26, 2016 at 6:44 PM, Rodrigo Vivi wrote:
> Version 1.01.
>
> This firmware is made for Kabylake platform so it doesn't
> need the stepping workaround that we had before.
>
> v2: Rebased on top of latest nightly with min version
> required change.
>
> Cc: Christophe Prigent
> Cc: Patrik Jakobsson
> Reviewed-by: Ben Widawsky (v1)
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_csr.c | 30 +++---
> 1 file changed, 19 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_csr.c
> b/drivers/gpu/drm/i915/intel_csr.c
> index a34c23e..64cb38f 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -41,16 +41,22 @@
> * be moved to FW_FAILED.
> */
>
> +#define I915_CSR_KBL "i915/kbl_dmc_ver1.bin"
> +MODULE_FIRMWARE(I915_CSR_KBL);
> +#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23)
Shouldn't this be CSR_VERSION(1,1) now that you've released the KBL
DMC firmware?
> +
> #define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
> +MODULE_FIRMWARE(I915_CSR_SKL);
> +#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23)
> +
> #define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
> +MODULE_FIRMWARE(I915_CSR_BXT);
> +#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
>
> #define FIRMWARE_URL
> "https://01.org/linuxgraphics/intel-linux-graphics-firmwares";
>
> -MODULE_FIRMWARE(I915_CSR_SKL);
> -MODULE_FIRMWARE(I915_CSR_BXT);
>
> -#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23)
> -#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
> +
>
> #define CSR_MAX_FW_SIZE0x2FFF
> #define CSR_DEFAULT_FW_OFFSET 0x
> @@ -169,12 +175,10 @@ struct stepping_info {
> char substepping;
> };
>
> -/*
> - * Kabylake derivated from Skylake H0, so SKL H0
> - * is the right firmware for KBL A0 (revid 0).
> - */
> static const struct stepping_info kbl_stepping_info[] = {
> - {'H', '0'}, {'I', '0'}
> + {'A', '0'}, {'B', '0'}, {'C', '0'},
> + {'D', '0'}, {'E', '0'}, {'F', '0'},
> + {'G', '0'}, {'H', '0'}, {'I', '0'},
> };
>
> static const struct stepping_info skl_stepping_info[] = {
> @@ -298,7 +302,9 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
> *dev_priv,
>
> csr->version = css_header->version;
>
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> + if (IS_KABYLAKE(dev_priv)) {
> + required_min_version = KBL_CSR_VERSION_REQUIRED;
> + } else if (IS_SKYLAKE(dev_priv)) {
> required_min_version = SKL_CSR_VERSION_REQUIRED;
> } else if (IS_BROXTON(dev_priv)) {
> required_min_version = BXT_CSR_VERSION_REQUIRED;
> @@ -446,7 +452,9 @@ void intel_csr_ucode_init(struct drm_i915_private
> *dev_priv)
> if (!HAS_CSR(dev_priv))
> return;
>
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> + if (IS_KABYLAKE(dev_priv))
> + csr->fw_path = I915_CSR_KBL;
> + else if (IS_SKYLAKE(dev_priv))
> csr->fw_path = I915_CSR_SKL;
> else if (IS_BROXTON(dev_priv))
> csr->fw_path = I915_CSR_BXT;
> --
> 2.4.3
>
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Re: [Intel-gfx] [PATCH 03/19] drm/i915: Remove intel_prepare_page_flip, v2.
On Tue, Apr 19, 2016 at 09:52:23AM +0200, Maarten Lankhorst wrote:
> Instead of calling prepare_flip right before calling finish_page_flip
> do everything from prepare_page_flip in finish_page_flip.
>
> Putting prepare and finish page_flip in a single step removes the need
> for INTEL_FLIP_COMPLETE, so it can be removed. This simplifies the code
> slightly.
>
> Changes since v1:
> - Invert if case to simplify code.
> - Add missing barrier.
> - Reword commit message.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 3 --
> drivers/gpu/drm/i915/i915_irq.c | 18 ++-
> drivers/gpu/drm/i915/intel_display.c | 92
> ++--
> drivers/gpu/drm/i915/intel_drv.h | 2 -
> 4 files changed, 39 insertions(+), 76 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 0092aaf47c43..def95532d421 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -619,9 +619,6 @@ static int i915_gem_pageflip_info(struct seq_file *m,
> void *data)
> if (pending == INTEL_FLIP_INACTIVE) {
> seq_printf(m, "Flip ioctl preparing on pipe %c
> (plane %c)\n",
> pipe, plane);
> - } else if (pending >= INTEL_FLIP_COMPLETE) {
> - seq_printf(m, "Flip queued on pipe %c (plane
> %c)\n",
> -pipe, plane);
> } else {
> seq_printf(m, "Flip pending (waiting for vsync)
> on pipe %c (plane %c)\n",
> pipe, plane);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 93da4feb3048..86f7060d3ddb 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1721,10 +1721,8 @@ static void valleyview_pipestat_irq_handler(struct
> drm_device *dev,
> intel_pipe_handle_vblank(dev, pipe))
> intel_check_page_flip(dev, pipe);
>
> - if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
> - intel_prepare_page_flip(dev, pipe);
> + if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
> intel_finish_page_flip(dev, pipe);
> - }
>
> if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
> i9xx_pipe_crc_irq_handler(dev, pipe);
> @@ -2182,10 +2180,8 @@ static void ilk_display_irq_handler(struct drm_device
> *dev, u32 de_iir)
> i9xx_pipe_crc_irq_handler(dev, pipe);
>
> /* plane/pipes map 1:1 on ilk+ */
> - if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
> - intel_prepare_page_flip(dev, pipe);
> + if (de_iir & DE_PLANE_FLIP_DONE(pipe))
> intel_finish_page_flip_plane(dev, pipe);
> - }
> }
>
> /* check event from PCH */
> @@ -2229,10 +2225,8 @@ static void ivb_display_irq_handler(struct drm_device
> *dev, u32 de_iir)
> intel_check_page_flip(dev, pipe);
>
> /* plane/pipes map 1:1 on ilk+ */
> - if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
> - intel_prepare_page_flip(dev, pipe);
> + if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
> intel_finish_page_flip_plane(dev, pipe);
> - }
> }
>
> /* check event from PCH */
> @@ -2436,10 +2430,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv,
> u32 master_ctl)
> else
> flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
>
> - if (flip_done) {
> - intel_prepare_page_flip(dev, pipe);
> + if (flip_done)
> intel_finish_page_flip_plane(dev, pipe);
> - }
>
> if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
> hsw_pipe_crc_irq_handler(dev, pipe);
> @@ -4025,7 +4017,6 @@ static bool i8xx_handle_vblank(struct drm_device *dev,
> if (I915_READ16(ISR) & flip_pending)
> goto check_page_flip;
>
> - intel_prepare_page_flip(dev, plane);
> intel_finish_page_flip(dev, pipe);
> return true;
>
> @@ -4216,7 +4207,6 @@ static bool i915_handle_vblank(struct drm_device *dev,
> if (I915_READ(ISR) & flip_pending)
> goto check_page_flip;
>
> - intel_prepare_page_flip(dev, plane);
> intel_finish_page_flip(dev, pipe);
> return true;
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 97a8418f6539..ccbc2a448258 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3118,7 +3118,6 @@ static void intel_complete_page_flips(struct drm_
Re: [Intel-gfx] [PATCH] drm/i915: Make RPS EI/thresholds multiple of 25 on SNB
On Wed, Apr 20, 2016 at 04:43:56PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Somehow my SNB GT1 (Dell XPS 8300) gets very unhappy around
> GPU hangs if the RPS EI/thresholds aren't suitably aligned.
> It seems like scheduling/timer interupts stop working somehow
> and things get stuck eg. in usleep_range().
>
> I bisected the problem down to
> commit 8a5864377b12 ("drm/i915/skl: Restructured the gen6_set_rps_thresholds
> function")
> I observed that before all the values were at least multiples of 25,
> but afterwards they are not. And rounding things up to the next multiple
> of 25 does seem to help, so lets' do that. I also tried roundup(..., 5)
> but that wasn't sufficient. Also I have no idea if we might need this sort of
> thing on gen9+ as well.
Do we need to test for performance regressions on stuff like this? And if so,
who do we ping about this?
OTOH impact should be really small and since this fixes a real problem:
Reviewed-by: Patrik Jakobsson
>
> These are the original EI/thresholds:
> LOW_POWER
> GEN6_RP_UP_EI 12500
> GEN6_RP_UP_THRESHOLD 11800
> GEN6_RP_DOWN_EI25000
> GEN6_RP_DOWN_THRESHOLD 21250
> BETWEEN
> GEN6_RP_UP_EI 10250
> GEN6_RP_UP_THRESHOLD9225
> GEN6_RP_DOWN_EI25000
> GEN6_RP_DOWN_THRESHOLD 18750
> HIGH_POWER
> GEN6_RP_UP_EI 8000
> GEN6_RP_UP_THRESHOLD6800
> GEN6_RP_DOWN_EI25000
> GEN6_RP_DOWN_THRESHOLD 15000
>
> These are after 8a5864377b12:
> LOW_POWER
> GEN6_RP_UP_EI 12500
> GEN6_RP_UP_THRESHOLD 11875
> GEN6_RP_DOWN_EI25000
> GEN6_RP_DOWN_THRESHOLD 21250
> BETWEEN
> GEN6_RP_UP_EI 10156
> GEN6_RP_UP_THRESHOLD9140
> GEN6_RP_DOWN_EI25000
> GEN6_RP_DOWN_THRESHOLD 18750
> HIGH_POWER
> GEN6_RP_UP_EI 7812
> GEN6_RP_UP_THRESHOLD6640
> GEN6_RP_DOWN_EI25000
> GEN6_RP_DOWN_THRESHOLD 15000
>
> And these are what we have after this patch:
> LOW_POWER
> GEN6_RP_UP_EI 12500
> GEN6_RP_UP_THRESHOLD 11875
> GEN6_RP_DOWN_EI25000
> GEN6_RP_DOWN_THRESHOLD 21250
> BETWEEN
> GEN6_RP_UP_EI 10175
> GEN6_RP_UP_THRESHOLD9150
> GEN6_RP_DOWN_EI25000
> GEN6_RP_DOWN_THRESHOLD 18750
> HIGH_POWER
> GEN6_RP_UP_EI 7825
> GEN6_RP_UP_THRESHOLD6650
> GEN6_RP_DOWN_EI25000
> GEN6_RP_DOWN_THRESHOLD 15000
>
> Cc: sta...@vger.kernel.org
> Cc: Akash Goel
> Cc: Chris Wilson
> Testcase: igt/kms_pipe_crc_basic/hang-read-crc-pipe-B
> Fixes: 8a5864377b12 ("drm/i915/skl: Restructured the gen6_set_rps_thresholds
> function")
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_reg.h | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c21b71c86a6b..08f01f4470cd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2948,7 +2948,14 @@ enum skl_disp_power_wells {
> #define GEN6_RP_STATE_CAP_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
> #define BXT_RP_STATE_CAP_MMIO(0x138170)
>
> -#define INTERVAL_1_28_US(us) (((us) * 100) >> 7)
> +/*
> + * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
> + * 8300) freezing up around GPU hangs. Looks as if even
> + * scheduling/timer interrupts start misbehaving if the RPS
> + * EI/thresholds are "bad", leading to a very sluggish or even
> + * frozen machine.
> + */
> +#define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25)
> #define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
> #define INTERVAL_0_833_US(us)(((us) * 6) / 5)
> #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
> --
> 2.7.4
>
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Re: [Intel-gfx] [PATCH] drm/i915/kbl: Don't WARN for expected secondary MISC IO power well request
On Tue, Apr 19, 2016 at 01:00:36PM +0300, Imre Deak wrote:
> In commit 5f304c873634 ("drm/i915/kbl: Reset secondary power well requests
> left on by DMC/KVMR") I forgot about the fact that SKL==KBL most of the
> time and that a secondary MISC IO power well request left on by the DMC is
> "expected". Tune down the corresponding WARN to be a debug message. This
> was caught by CI suspend tests.
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Was just about to bug you about this. You're one step ahead of me :)
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 0ed3ec8..56df7ff 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -635,7 +635,8 @@ gen9_sanitize_power_well_requests(struct drm_i915_private
> *dev_priv,
>* other request bits to be set, so WARN for those.
>*/
> if (power_well_id == SKL_DISP_PW_1 ||
> - (IS_SKYLAKE(dev_priv) && power_well_id == SKL_DISP_PW_MISC_IO))
> + ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> + power_well_id == SKL_DISP_PW_MISC_IO))
> DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on "
>"by DMC\n", power_well->name);
> else
> --
> 2.5.0
>
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Re: [Intel-gfx] [PATCH] drm/i915/kbl: Reset secondary power well requests left on by DMC/KVMR
On Fri, Apr 15, 2016 at 10:32:58PM +0300, Imre Deak wrote:
> The workaround added in c6782b76d31a ("drm/i915/gen9: Reset secondary power
> well requests left on by DMC/KVMR") needs to be applied on Kabylake too as
> shown by the corresponding timeout errors about power well 1 and MISC IO
> power well disabling in the latest CI run.
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Ok, so this seems to affect all DMC firmwares we have so far? Any news on the
bug report?
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 259f66f..1242fb5 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -709,7 +709,7 @@ static void skl_set_power_well(struct drm_i915_private
> *dev_priv,
> DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
> }
>
> - if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> + if (IS_GEN9(dev_priv))
> gen9_sanitize_power_well_requests(dev_priv, power_well);
> }
>
> --
> 2.5.0
>
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Re: [Intel-gfx] [PATCH 2/3] drm/i915: Make sure LP1+ watermarks levels are preserved when going from 1 to 2 pipes
On Fri, Apr 01, 2016 at 09:53:18PM +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Once again ILK is unhappy if we clear out the LP1+ watermark levels > outright, and instead we must disable the levels we don't want while > still leaving the actual programmed watermark levels intact. > > Fixes underruns on the already enabled pipe when programming watermarks > while enabling the second pipe. > > Cc: Daniel Vetter > Cc: Matt Roper > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93787 > Signed-off-by: Ville Syrjälä Reviewed-by: Patrik Jakobsson > --- > drivers/gpu/drm/i915/intel_pm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 9bc9c25423e9..a7fd5d464838 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -2483,7 +2483,7 @@ static void ilk_wm_merge(struct drm_device *dev, > /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ > if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && > config->num_pipes_active > 1) > - return; > + last_enabled_level = 0; > > /* ILK: FBC WM must be disabled always */ > merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; > -- > 2.7.4 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Intel Sweden AB Registered Office: Knarrarnasgatan 15, 164 40 Kista, Stockholm, Sweden Registration Number: 556189-6027 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Replace ILK eDP underrun suppression with something better
On Fri, Apr 01, 2016 at 09:53:19PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The underruns we were seeing when enabling eDP port A on ILK seem to
> have been caused by prematurely clearing the LP1+ watermark values when
> disabling LP1+ watermarks. Now that the watermarks are handled
> properly, we can rip out the underrun suppression around the port A
> enable.
>
> We still need to worry about the underruns on FDI when enabling
> the eDP PLL. But as Bspec tells us, we can avoid that by a vblank
> wait on the pipe driving FDI just prior to enabling the eDP PLL.
>
> Cc: Daniel Vetter
> Signed-off-by: Ville Syrjälä
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_dp.c | 36 +---
> 1 file changed, 9 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 95fe01d55bce..7523558190d1 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2215,6 +2215,15 @@ static void ironlake_edp_pll_on(struct intel_dp
> *intel_dp)
> POSTING_READ(DP_A);
> udelay(500);
>
> + /*
> + * [DevILK] Work around required when enabling DP PLL
> + * while a pipe is enabled going to FDI:
> + * 1. Wait for the start of vertical blank on the enabled pipe going to
> FDI
> + * 2. Program DP PLL enable
> + */
> + if (IS_GEN5(dev_priv))
> + intel_wait_for_vblank_if_active(dev_priv->dev, !crtc->pipe);
> +
> intel_dp->DP |= DP_PLL_ENABLE;
>
> I915_WRITE(DP_A, intel_dp->DP);
> @@ -2630,7 +2639,6 @@ static void intel_enable_dp(struct intel_encoder
> *encoder)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> uint32_t dp_reg = I915_READ(intel_dp->output_reg);
> - enum port port = dp_to_dig_port(intel_dp)->port;
> enum pipe pipe = crtc->pipe;
>
> if (WARN_ON(dp_reg & DP_PORT_EN))
> @@ -2643,17 +2651,6 @@ static void intel_enable_dp(struct intel_encoder
> *encoder)
>
> intel_dp_enable_port(intel_dp);
>
> - if (port == PORT_A && IS_GEN5(dev_priv)) {
> - /*
> - * Underrun reporting for the other pipe was disabled in
> - * g4x_pre_enable_dp(). The eDP PLL and port have now been
> - * enabled, so it's now safe to re-enable underrun reporting.
> - */
> - intel_wait_for_vblank_if_active(dev_priv->dev, !pipe);
> - intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, true);
> - intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, true);
> - }
> -
> edp_panel_vdd_on(intel_dp);
> edp_panel_on(intel_dp);
> edp_panel_vdd_off(intel_dp, true);
> @@ -2699,26 +2696,11 @@ static void vlv_enable_dp(struct intel_encoder
> *encoder)
>
> static void g4x_pre_enable_dp(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> enum port port = dp_to_dig_port(intel_dp)->port;
> - enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
>
> intel_dp_prepare(encoder);
>
> - if (port == PORT_A && IS_GEN5(dev_priv)) {
> - /*
> - * We get FIFO underruns on the other pipe when
> - * enabling the CPU eDP PLL, and when enabling CPU
> - * eDP port. We could potentially avoid the PLL
> - * underrun with a vblank wait just prior to enabling
> - * the PLL, but that doesn't appear to help the port
> - * enable case. Just sweep it all under the rug.
> - */
> - intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, false);
> - intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, false);
> - }
> -
> /* Only ilk+ has port A */
> if (port == PORT_A)
> ironlake_edp_pll_on(intel_dp);
> --
> 2.7.4
>
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Re: [Intel-gfx] [PATCH 1/3] drm/i915: Try to shut up more ILK underruns
On Fri, Apr 01, 2016 at 09:53:17PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Take a bigger hammer to the underrun suppression on ILK. Instead of
> trying to suppress them at specific points in the modeset sequence just
> silence them across the entire sequence. This gets rid of some underruns
> at least on my ILK. Note that this changes SNB and IVB to follow the
> same approach just to keep the code less convoluted. The difference is
> that on those platforms we won't suppress CPU underruns for port A since
> it doesn't seem to be necessary.
>
> My ILK has port A eDP and two PCH HDMI ports, so I can't be sure this is
> as effective on other PCH port types. Perhaps we still need some of
> Daniel's extra vblank waits [2]?
>
> I've still been able to trigger an underrun on the other pipe, but
> fixing that perhaps needs the LP1+ disable trick I implemented here [1]
> which never got merged.
>
> A few details which hamper stress testing on my ILK are that sometimes
> the PCH transcoder gets messed up and refuses to shut down, and sometimes
> even the panel power sequencer apparently gets stuck on the always on
> position.
>
> [1] https://lists.freedesktop.org/archives/intel-gfx/2014-March/041317.html
> [2] https://lists.freedesktop.org/archives/intel-gfx/2016-January/086397.html
>
> v2: Add a note that we also get underruns when enabling PCH ports
>
> Cc: Daniel Vetter
> Signed-off-by: Ville Syrjälä
> Reviewed-by: Daniel Vetter (v1)
I've not been able to find any additional ILK hardware to test this on but LGTM
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 45
> ++--
> drivers/gpu/drm/i915/intel_dp.c | 12 --
> 2 files changed, 23 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index e6b5ee51739b..8d2c547b57ee 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4083,12 +4083,6 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
> I915_WRITE(FDI_RX_TUSIZE1(pipe),
> I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
>
> - /*
> - * Sometimes spurious CPU pipe underruns happen during FDI
> - * training, at least with VGA+HDMI cloning. Suppress them.
> - */
> - intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> -
> /* For PCH output, training FDI link */
> dev_priv->display.fdi_link_train(crtc);
>
> @@ -4123,8 +4117,6 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>
> intel_fdi_normal_train(crtc);
>
> - intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> -
> /* For PCH DP, enable TRANS_DP_CTL */
> if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
> const struct drm_display_mode *adjusted_mode =
> @@ -4727,6 +4719,18 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
> if (WARN_ON(intel_crtc->active))
> return;
>
> + /*
> + * Sometimes spurious CPU pipe underruns happen during FDI
> + * training, at least with VGA+HDMI cloning. Suppress them.
> + *
> + * On ILK we get an occasional spurious CPU pipe underruns
> + * between eDP port A enable and vdd enable. Also PCH port
> + * enable seems to result in the occasional CPU pipe underrun.
> + *
> + * Spurious PCH underruns also occur during PCH enabling.
> + */
> + if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
> + intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> if (intel_crtc->config->has_pch_encoder)
> intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
>
> @@ -4748,8 +4752,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>
> intel_crtc->active = true;
>
> - intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> -
> for_each_encoder_on_crtc(dev, crtc, encoder)
> if (encoder->pre_enable)
> encoder->pre_enable(encoder);
> @@ -4791,6 +4793,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
> /* Must wait for vblank to avoid spurious PCH FIFO underruns */
> if (intel_crtc->config->has_pch_encoder)
> intel_wait_for_vblank(dev, pipe);
> + intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
> }
>
> @@ -4943,8 +4946,15 @@ static void ir
Re: [Intel-gfx] [PATCH v2 04/16] drm/i915/gen9: Reset secondary power well requests left on by DMC/KVMR
On Tue, Apr 05, 2016 at 01:26:05PM +0300, Imre Deak wrote:
> DMC forces on power well 1 and the misc IO power well by setting the
> corresponding request bits both in the BIOS and the DEBUG power well
> request registers. This is somewhat unexpected since the firmware should
> really just save and restore state but not alter it. We also depend on
> being able to disable power well 1, and the misc IO power well before
> entering S3/S4 on BXT and SKL or entering DC9 on BXT. To fix this make
> sure these request bits are cleared whenever we want to disable the
> given power wells.
>
> On SKL there is another twist where the firmware also clears the power
> well 1 request bit in HSW_POWER_WELL_DRIVER (but not that of the misc IO
> power well). This happens to not cause a problem due to the forced-on
> request bits in the other request registers.
>
> I've filed a bug about all this, but fixing that may take a while and
> having this sanity check in place makes sense even for future firmware
> versions.
>
> At the same time also check the KVMR request bits. I haven't seen this
> being altered, but we don't expect any request bits in here either, so
> sanitize this register as well.
>
> v2:
> - apply the workaround on SKL as well
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Hmm, more DMC fun.
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 41
> +
> 1 file changed, 41 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index d189a00..6ffa6ad 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -630,6 +630,44 @@ void skl_disable_dc6(struct drm_i915_private *dev_priv)
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> }
>
> +static void
> +gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + enum skl_disp_power_wells power_well_id = power_well->data;
> + u32 val;
> + u32 mask;
> +
> + mask = SKL_POWER_WELL_REQ(power_well_id);
> +
> + val = I915_READ(HSW_PWR_WELL_KVMR);
> + if (WARN_ONCE(val & mask, "Clearing unexpected KVMR request for %s\n",
> +power_well->name))
> + I915_WRITE(HSW_PWR_WELL_KVMR, val & ~mask);
> +
> + val = I915_READ(HSW_PWR_WELL_BIOS);
> + val |= I915_READ(HSW_PWR_WELL_DEBUG);
> +
> + if (!(val & mask))
> + return;
> +
> + /*
> + * DMC is known to force on the request bits for power well 1 on SKL
> + * and BXT and the misc IO power well on SKL but we don't expect any
> + * other request bits to be set, so WARN for those.
> + */
> + if (power_well_id == SKL_DISP_PW_1 ||
> + (IS_SKYLAKE(dev_priv) && power_well_id == SKL_DISP_PW_MISC_IO))
> + DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on "
> + "by DMC\n", power_well->name);
> + else
> + WARN_ONCE(1, "Clearing unexpected auxiliary requests for %s\n",
> + power_well->name);
> +
> + I915_WRITE(HSW_PWR_WELL_BIOS, val & ~mask);
> + I915_WRITE(HSW_PWR_WELL_DEBUG, val & ~mask);
> +}
> +
> static void skl_set_power_well(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well, bool enable)
> {
> @@ -696,6 +734,9 @@ static void skl_set_power_well(struct drm_i915_private
> *dev_priv,
> POSTING_READ(HSW_PWR_WELL_DRIVER);
> DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
> }
> +
> + if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> + gen9_sanitize_power_well_requests(dev_priv, power_well);
> }
>
> if (check_fuse_status) {
> --
> 2.5.0
>
--
---
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Sweden Registration Number: 556189-6027
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Re: [Intel-gfx] [PATCH 14/16] drm/i915/gen9: Calculate watermarks during atomic 'check'
On Thu, Mar 31, 2016 at 06:46:36PM -0700, Matt Roper wrote:
> Moving watermark calculation into the check phase will allow us to to
> reject display configurations for which there are no valid watermark
> values before we start trying to program the hardware (although those
> tests will come in a subsequent patch).
>
> Another advantage of moving this calculation to the check phase is that
> we can calculate the watermarks in a single shot as part of the atomic
> transaction. The watermark interfaces we inherited from our legacy
> modesetting days are a bit broken in the atomic design because they use
> per-crtc entry points but actually re-calculate and re-program something
> that is really more of a global state. That worked okay in the legacy
> modesetting world because operations only ever updated a single CRTC at
> a time. However in the atomic world, a transaction can involve multiple
> CRTC's, which means we wind up computing and programming the watermarks
> NxN times (where N is the number of CRTC's involved). With this patch
> we eliminate the redundant re-calculation of watermark data for atomic
> states (which was the cause of the WARN_ON(!wm_changed) problems that
> have plagued us for a while).
This one also fixes: https://bugs.freedesktop.org/show_bug.cgi?id=92181
>
> We still need to work on the 'commit' side of watermark handling so that
> we aren't doing redundant NxN programming of watermarks, but that's
> content for future patches.
>
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> drivers/gpu/drm/i915/intel_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 141
> +--
> 3 files changed, 55 insertions(+), 90 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index c514549..f1bea9f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13523,7 +13523,7 @@ static int intel_atomic_commit(struct drm_device *dev,
>
> drm_atomic_helper_swap_state(dev, state);
> dev_priv->wm.config = intel_state->wm_config;
> - dev_priv->wm.skl_results.ddb = intel_state->ddb;
> + dev_priv->wm.skl_results = intel_state->wm_results;
> intel_shared_dpll_commit(state);
>
> if (intel_state->modeset) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 6471f69..3abd394 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -303,7 +303,7 @@ struct intel_atomic_state {
> bool skip_intermediate_wm;
>
> /* Gen9+ only */
> - struct skl_ddb_allocation ddb;
> + struct skl_wm_values wm_results;
> };
>
> struct intel_plane_state {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1bef89a..e4de5aa 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3187,23 +3187,6 @@ static uint32_t skl_wm_method2(uint32_t pixel_rate,
> uint32_t pipe_htotal,
> return ret;
> }
>
> -static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation
> *new_ddb,
> -const struct intel_crtc *intel_crtc)
> -{
> - struct drm_device *dev = intel_crtc->base.dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
> -
> - /*
> - * If ddb allocation of pipes changed, it may require recalculation of
> - * watermarks
> - */
> - if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
> - return true;
> -
> - return false;
> -}
> -
> static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> struct intel_crtc_state *cstate,
> struct intel_plane_state *intel_pstate,
> @@ -3654,72 +3637,16 @@ static int skl_update_pipe_wm(struct drm_crtc_state
> *cstate,
> else
> *changed = true;
>
> - intel_crtc->wm.active.skl = *pipe_wm;
> -
> return 0;
> }
>
> -static void skl_update_other_pipe_wm(struct drm_device *dev,
> - struct drm_crtc *crtc,
> - struct skl_wm_values *r)
> -{
> - struct intel_crtc *intel_crtc;
> - struct intel_crtc *this_crtc = to_intel_crtc(crtc);
> -
> - /*
> - * If the WM update hasn't changed the allocation for this_crtc (the
> - * crtc we are currently computing the new WM values for), other
> - * enabled crtcs will keep the same allocation and we don't need to
> - * recompute anything for them.
> - */
> - if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
> - return;
> -
> - /*
> - * Otherwise, because of this_crtc being freshly enabled/disabled, the
> - * other active pipes need new DDB allocation and
Re: [Intel-gfx] [PATCH 05/16] drm/i915/gen9: Make power well disabling synchronous
On Mon, Apr 04, 2016 at 12:34:30PM +0200, Patrik Jakobsson wrote:
> On Fri, Apr 01, 2016 at 04:02:36PM +0300, Imre Deak wrote:
> > So far we only power well enabling was synchronous not disabling. Since
> > we don't exactly know how the firmware (both DMC and PCU) synchronizes
> > against the actual power well state during DC transitions, make the
> > disabling also synchronous.
> >
> > CC: Mika Kuoppala
> > CC: Patrik Jakobsson
> > Signed-off-by: Imre Deak
>
> Reviewed-by: Patrik Jakobsson
Perhaps I was too quick with the review. I'm getting timeouts when trying to
disable MISC IO and PW1 on SKL. Need to have a closer look at what's going on
here.
-Patrik
>
> > ---
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 9 +
> > 1 file changed, 5 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index d20fd8f..f5f6e89 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -720,10 +720,6 @@ static void skl_set_power_well(struct drm_i915_private
> > *dev_priv,
> >
> > if (!is_enabled) {
> > DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
> > - if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
> > - state_mask), 1))
> > - DRM_ERROR("%s enable timeout\n",
> > - power_well->name);
> > check_fuse_status = true;
> > }
> > } else {
> > @@ -737,6 +733,11 @@ static void skl_set_power_well(struct drm_i915_private
> > *dev_priv,
> > bxt_sanitize_power_well_requests(dev_priv, power_well);
> > }
> >
> > + if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
> > +1))
> > + DRM_ERROR("%s %s timeout\n",
> > + power_well->name, enable ? "enable" : "disable");
> > +
> > if (check_fuse_status) {
> > if (power_well->data == SKL_DISP_PW_1) {
> > if (wait_for((I915_READ(SKL_FUSE_STATUS) &
> > --
> > 2.5.0
> >
>
> --
> ---
> Intel Sweden AB Registered Office: Knarrarnasgatan 15, 164 40 Kista,
> Stockholm, Sweden Registration Number: 556189-6027
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
---
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Sweden Registration Number: 556189-6027
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Re: [Intel-gfx] [PATCH v2 08/16] drm/i915/skl: Unexport skl_pw1_misc_io_init
On Mon, Apr 04, 2016 at 03:42:57PM +0300, Imre Deak wrote:
> On Broxton we need to enable/disable power well 1 during the init/unit display
> sequence similarly to Skylake/Kabylake. The code for this will be added in a
> follow-up patch, but to prepare for that unexport skl_pw1_misc_io_init(). It's
> a simple function called only from a single place and having it inlined in the
> Skylake display core init/unit functions will make it easier to compare it
> with its Broxton counterpart.
>
> No functional change.
>
> v2:
> - Fix incorrect enable vs. disable power well call in
> skl_display_core_uninit() (Patrik)
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/intel_drv.h| 2 --
> drivers/gpu/drm/i915/intel_runtime_pm.c | 49
> -
> 2 files changed, 18 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 9255b56..8ba2ac3 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1460,8 +1460,6 @@ int intel_power_domains_init(struct drm_i915_private *);
> void intel_power_domains_fini(struct drm_i915_private *);
> void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool
> resume);
> void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
> -void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv);
> -void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv);
> void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
> const char *
> intel_display_power_domain_str(enum intel_display_power_domain domain);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index b16315e..8d401bb 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -1921,34 +1921,6 @@ static struct i915_power_well skl_power_wells[] = {
> },
> };
>
> -void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv)
> -{
> - struct i915_power_well *well;
> -
> - if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
> - return;
> -
> - well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> - intel_power_well_enable(dev_priv, well);
> -
> - well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
> - intel_power_well_enable(dev_priv, well);
> -}
> -
> -void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv)
> -{
> - struct i915_power_well *well;
> -
> - if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
> - return;
> -
> - well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> - intel_power_well_disable(dev_priv, well);
> -
> - well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
> - intel_power_well_disable(dev_priv, well);
> -}
> -
> static struct i915_power_well bxt_power_wells[] = {
> {
> .name = "always-on",
> @@ -2139,9 +2111,10 @@ static void intel_power_domains_sync_hw(struct
> drm_i915_private *dev_priv)
> }
>
> static void skl_display_core_init(struct drm_i915_private *dev_priv,
> - bool resume)
> +bool resume)
> {
> struct i915_power_domains *power_domains = &dev_priv->power_domains;
> + struct i915_power_well *well;
> uint32_t val;
>
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> @@ -2152,7 +2125,13 @@ static void skl_display_core_init(struct
> drm_i915_private *dev_priv,
>
> /* enable PG1 and Misc I/O */
> mutex_lock(&power_domains->lock);
> - skl_pw1_misc_io_init(dev_priv);
> +
> + well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> + intel_power_well_enable(dev_priv, well);
> +
> + well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
> + intel_power_well_enable(dev_priv, well);
> +
> mutex_unlock(&power_domains->lock);
>
> if (!resume)
> @@ -2167,6 +2146,7 @@ static void skl_display_core_init(struct
> drm_i915_private *dev_priv,
> static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
> {
> struct i915_power_domains *power_domains = &dev_priv->power_domains;
> + struct i915_power_well *well;
>
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>
> @@ -2174,8 +2154,15 @@ static void skl_display_core_uninit(struct
> drm_i915_private *dev_priv)
>
> /* The spec doesn't call for removing the reset handshake flag */
> /* disable PG1 and Misc I/O */
> +
> mutex_lock(&power_domains-&
Re: [Intel-gfx] [PATCH 08/16] drm/i915/skl: Unexport skl_pw1_misc_io_init
On Fri, Apr 01, 2016 at 04:02:39PM +0300, Imre Deak wrote:
> On Broxton we need to enable/disable power well 1 during the init/unit display
> sequence similarly to Skylake/Kabylake. The code for this will be added in a
> follow-up patch, but to prepare for that unexport skl_pw1_misc_io_init(). It's
> a simple function called only from a single place and having it inlined in the
> Skylake display core init/unit functions will make it easier to compare it
> with its Broxton counterpart.
>
> No functional change.
>
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/intel_drv.h| 2 --
> drivers/gpu/drm/i915/intel_runtime_pm.c | 49
> -
> 2 files changed, 18 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 9255b56..8ba2ac3 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1460,8 +1460,6 @@ int intel_power_domains_init(struct drm_i915_private *);
> void intel_power_domains_fini(struct drm_i915_private *);
> void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool
> resume);
> void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
> -void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv);
> -void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv);
> void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
> const char *
> intel_display_power_domain_str(enum intel_display_power_domain domain);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index b16315e..58ed8bc 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -1921,34 +1921,6 @@ static struct i915_power_well skl_power_wells[] = {
> },
> };
>
> -void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv)
> -{
> - struct i915_power_well *well;
> -
> - if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
> - return;
> -
> - well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> - intel_power_well_enable(dev_priv, well);
> -
> - well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
> - intel_power_well_enable(dev_priv, well);
> -}
> -
> -void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv)
> -{
> - struct i915_power_well *well;
> -
> - if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
> - return;
> -
> - well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> - intel_power_well_disable(dev_priv, well);
> -
> - well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
> - intel_power_well_disable(dev_priv, well);
> -}
> -
> static struct i915_power_well bxt_power_wells[] = {
> {
> .name = "always-on",
> @@ -2139,9 +2111,10 @@ static void intel_power_domains_sync_hw(struct
> drm_i915_private *dev_priv)
> }
>
> static void skl_display_core_init(struct drm_i915_private *dev_priv,
> - bool resume)
> +bool resume)
> {
> struct i915_power_domains *power_domains = &dev_priv->power_domains;
> + struct i915_power_well *well;
> uint32_t val;
>
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> @@ -2152,7 +2125,13 @@ static void skl_display_core_init(struct
> drm_i915_private *dev_priv,
>
> /* enable PG1 and Misc I/O */
> mutex_lock(&power_domains->lock);
> - skl_pw1_misc_io_init(dev_priv);
> +
> + well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> + intel_power_well_enable(dev_priv, well);
> +
> + well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
> + intel_power_well_enable(dev_priv, well);
> +
> mutex_unlock(&power_domains->lock);
>
> if (!resume)
> @@ -2167,6 +2146,7 @@ static void skl_display_core_init(struct
> drm_i915_private *dev_priv,
> static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
> {
> struct i915_power_domains *power_domains = &dev_priv->power_domains;
> + struct i915_power_well *well;
>
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>
> @@ -2174,8 +2154,15 @@ static void skl_display_core_uninit(struct
> drm_i915_private *dev_priv)
>
> /* The spec doesn't call for removing the reset handshake flag */
> /* disable PG1 and Misc I/O */
> +
> mutex_lock(&power_domains->lock);
> - skl_pw1_misc_io_fini(dev_priv);
> +
> + well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
> + intel_power_well_enable(dev_priv, well);
Should be intel_power_well_disable(...)
> +
> + well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> + intel_power_well_enable(dev_priv, well);
Same here.
> +
> mutex_unlock(&power_domains->lock);
> }
>
> --
> 2.5.0
>
> ___
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> https://lists.freedesktop.org/
Re: [Intel-gfx] [PATCH 07/16] drm/i915/bxt: Suspend power domains during suspend-to-idle
On Fri, Apr 01, 2016 at 04:02:38PM +0300, Imre Deak wrote: > On SKL/KBL suspend-to-idle (aka freeze/s0ix) is performed with DMC > firmware assistance where the target display power state is DC6. On > Broxton on the other hand we don't use the firmware for this, but rely > instead on a manual DC9 flow. For this we have to uninitialize the > display following the BSpec display uninit sequence, just as during > S3/S4, so make sure we follow this sequence. > > CC: Patrik Jakobsson > Signed-off-by: Imre Deak Reviewed-by: Patrik Jakobsson > --- > drivers/gpu/drm/i915/i915_drv.c | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 020a31c..aa7df10 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -657,7 +657,8 @@ static int i915_drm_suspend_late(struct drm_device > *drm_dev, bool hibernation) > > disable_rpm_wakeref_asserts(dev_priv); > > - fw_csr = suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload; > + fw_csr = !IS_BROXTON(dev_priv) && > + suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload; > /* >* In case of firmware assisted context save/restore don't manually >* deinit the power domains. This also means the CSR/DMC firmware will > @@ -837,7 +838,8 @@ static int i915_drm_resume_early(struct drm_device *dev) > > intel_uncore_sanitize(dev); > > - if (!(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload)) > + if (IS_BROXTON(dev_priv) || > + !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload)) > intel_power_domains_init_hw(dev_priv, true); > > out: > -- > 2.5.0 > -- --- Intel Sweden AB Registered Office: Knarrarnasgatan 15, 164 40 Kista, Stockholm, Sweden Registration Number: 556189-6027 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 06/16] drm/i915/gen9: Fix DMC/DC state asserts
On Fri, Apr 01, 2016 at 04:02:37PM +0300, Imre Deak wrote:
> The display power well support and DC state management doesn't depend on
> runtime PM support, so remove the incorrect asserts about this.
>
> Also Broxton does support DC5, so the related assert in
> assert_can_enable_dc5() is incorrect. There is a more generic and
> correct assert for this already in gen9_set_dc_state(), so we can remove
> all the other ones.
>
> At the same time convert WARNs to WARN_ONCE for consistency with the
> other DC state asserts.
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 32 +++-
> 1 file changed, 11 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index f5f6e89..b16315e 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -443,15 +443,13 @@ static void hsw_set_power_well(struct drm_i915_private
> *dev_priv,
>
> static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
> {
> - struct drm_device *dev = dev_priv->dev;
> -
> - WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");
> - WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
> - "DC9 already programmed to be enabled.\n");
> - WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
> - "DC5 still not disabled to enable DC9.\n");
> - WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
> - WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
> + WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
> + "DC9 already programmed to be enabled.\n");
> + WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
> + "DC5 still not disabled to enable DC9.\n");
> + WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
> + WARN_ONCE(intel_irqs_enabled(dev_priv),
> + "Interrupts not disabled yet.\n");
>
>/*
> * TODO: check for the following to verify the conditions to enter DC9
> @@ -464,9 +462,10 @@ static void assert_can_enable_dc9(struct
> drm_i915_private *dev_priv)
>
> static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
> {
> - WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
> - WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
> - "DC5 still not disabled.\n");
> + WARN_ONCE(intel_irqs_enabled(dev_priv),
> + "Interrupts not disabled yet.\n");
> + WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
> + "DC5 still not disabled.\n");
>
>/*
> * TODO: check for the following to verify DC9 state was indeed
> @@ -573,13 +572,9 @@ static void assert_csr_loaded(struct drm_i915_private
> *dev_priv)
>
> static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
> {
> - struct drm_device *dev = dev_priv->dev;
> bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
> SKL_DISP_PW_2);
>
> - WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev),
> - "Platform doesn't support DC5.\n");
> - WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
> WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
>
> WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
> @@ -600,11 +595,6 @@ static void gen9_enable_dc5(struct drm_i915_private
> *dev_priv)
>
> static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
> {
> - struct drm_device *dev = dev_priv->dev;
> -
> - WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev),
> - "Platform doesn't support DC6.\n");
> - WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
> WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
> "Backlight is not disabled.\n");
> WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
> --
> 2.5.0
>
--
---
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Re: [Intel-gfx] [PATCH 05/16] drm/i915/gen9: Make power well disabling synchronous
On Fri, Apr 01, 2016 at 04:02:36PM +0300, Imre Deak wrote:
> So far we only power well enabling was synchronous not disabling. Since
> we don't exactly know how the firmware (both DMC and PCU) synchronizes
> against the actual power well state during DC transitions, make the
> disabling also synchronous.
>
> CC: Mika Kuoppala
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index d20fd8f..f5f6e89 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -720,10 +720,6 @@ static void skl_set_power_well(struct drm_i915_private
> *dev_priv,
>
> if (!is_enabled) {
> DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
> - if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
> - state_mask), 1))
> - DRM_ERROR("%s enable timeout\n",
> - power_well->name);
> check_fuse_status = true;
> }
> } else {
> @@ -737,6 +733,11 @@ static void skl_set_power_well(struct drm_i915_private
> *dev_priv,
> bxt_sanitize_power_well_requests(dev_priv, power_well);
> }
>
> + if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
> + 1))
> + DRM_ERROR("%s %s timeout\n",
> + power_well->name, enable ? "enable" : "disable");
> +
> if (check_fuse_status) {
> if (power_well->data == SKL_DISP_PW_1) {
> if (wait_for((I915_READ(SKL_FUSE_STATUS) &
> --
> 2.5.0
>
--
---
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[Intel-gfx] [PATCH] drm/i915/skl: Remove unused skl_disable_dc6 function
Left behind by DC state rework and is no longer needed.
Cc: Imre Deak
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/intel_drv.h| 1 -
drivers/gpu/drm/i915/intel_runtime_pm.c | 7 ---
2 files changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 02b3d22..51c43e7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1240,7 +1240,6 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv);
int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
void skl_enable_dc6(struct drm_i915_private *dev_priv);
-void skl_disable_dc6(struct drm_i915_private *dev_priv);
void intel_dp_get_m_n(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config);
void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 2e88a5e..316f96d 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -617,13 +617,6 @@ void skl_enable_dc6(struct drm_i915_private *dev_priv)
}
-void skl_disable_dc6(struct drm_i915_private *dev_priv)
-{
- DRM_DEBUG_KMS("Disabling DC6\n");
-
- gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
-}
-
static void skl_set_power_well(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well, bool enable)
{
--
2.5.0
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Re: [Intel-gfx] [PATCH igt] igt/pm_rpm: Wait for PCI D3
On Mon, Mar 07, 2016 at 02:19:10PM +, Chris Wilson wrote:
> The transition to PCI device state D3 is not instantaneous and only
> started when runtime suspended. Allow the driver/hardware a little bit
> of time to complete the transition before declaring a test failure.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=93123
> Signed-off-by: Chris Wilson
> ---
> tests/pm_rpm.c | 12
> 1 file changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/tests/pm_rpm.c b/tests/pm_rpm.c
> index e84a9d3..03ef2eb 100644
> --- a/tests/pm_rpm.c
> +++ b/tests/pm_rpm.c
> @@ -1337,15 +1337,13 @@ static void reg_read_ioctl_subtest(void)
>
> static bool device_in_pci_d3(void)
> {
> - struct pci_device *pci_dev;
> - int rc;
> uint16_t val;
> + int rc;
>
> - pci_dev = intel_get_pci_device();
> -
> - rc = pci_device_cfg_read_u16(pci_dev, &val, 0xd4);
> + rc = pci_device_cfg_read_u16(intel_get_pci_device(), &val, 0xd4);
> igt_assert_eq(rc, 0);
>
> + igt_debug("%s: PCI D3 state=%d\n", __func__, val & 0x3);
> return (val & 0x3) == 0x3;
> }
>
> @@ -1354,11 +1352,9 @@ static void pci_d3_state_subtest(void)
> igt_require(has_runtime_pm);
>
> disable_all_screens_and_wait(&ms_data);
> -
> - igt_assert(device_in_pci_d3());
> + igt_assert(igt_wait(device_in_pci_d3(), 2000, 100));
Not sure we need to wait for 2 full secs here but not a big problem if we do.
Reviewed-by: Patrik Jakobsson
>
> enable_one_screen_and_wait(&ms_data);
> -
> igt_assert(!device_in_pci_d3());
> }
>
> --
> 2.7.0
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] Fwd: [PATCH] drm/i915: Avoid vblank counter for gen9+
On Wed, Mar 02, 2016 at 07:13:07PM +0200, Imre Deak wrote: > On Fri, 2016-02-26 at 10:02 -0800, Rodrigo Vivi wrote: > > [...] > > Well, I have this tree: > > https://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=rpm-domains-psr-vblank-counter-full > > with mainly: > > 1 - vblank domain on pre-enable post-disable vblanks hooks as Ville > > had suggested > > 2 - psr domain so we just enable dc state when screen is really in > > idle. > > 3 - restore counter on vblank enable. > > > > From what I understood so far of this problem, only the patch 1 > > should > > be enough, but with only this one I don't get the screen frozen but > > the typying is so slow that is visible that we have something > > wrong Maybe dc state transition with mutexes there are slow? > > I'm not aware of any big latencies caused by toggling DC states alone. According to bspec, any MMIO access when in DC6 have a considerably higher latency. The recommendation from bspec is to disable DC states around longer sequences of MMIO. I don't know if this is the case here but going from DC6 -> DC3 is a quite heavy operation (enable PG0, PG1, CDCLK and do CSR for these). I guess we could measure it to see how long it actually takes? > > > Patch 2 by iitself also doesn't solve this and I still have frozen > > screens, but when combined to patch 1 everything works really > > well... > > In the point that I believe we really don't need patch 3. > > I think something like 1 and 3 is a good idea (and both are needed). > About 2, it's strange that you have to disable DC states when enabling > the panel. Since the pipe is active it should prevent DC5 (and hence > DC6). We wouldn't waste any power with your changes, since you re- > enable DC states before entering PSR, but imo we should find out why > exactly this is needed. > > Some notes/ideas about the patches: > - intel_display_power_get() is called from page_flip_completed(), which > is bad since we can be in interrupt context. > - There is a drm_crtc_vblank_get() in intel_crtc_page_flip(), but there > is no corresponding intel_display_power_get() for it. > - The same goes for the FBC, CRC code, couldn't you just call the new > vblank hooks from drm_vblank_get/put()? > - PIPE_FLIPCOUNT_G4X is also read-only, so it could get corrupted the > same way as the frame counter register. page_flip_finished() depends on > PIPE_FLIPCOUNT_G4X, so isn't this a problem? > > I haven't checked this in detail, but it could be that we need to exit > PSR explicitly when waiting for a vblank or doing a flip. In PSR mode > the pipe may not be running, so I'm not sure how the vblank and flip > interrupts would be delivered. > > --Imre > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- --- Intel Sweden AB Registered Office: Knarrarnasgatan 15, 164 40 Kista, Stockholm, Sweden Registration Number: 556189-6027 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 3/4] drm/i915/gen9: Disable DC states if power well support is disabled
On Mon, Feb 29, 2016 at 10:49:04PM +0200, Imre Deak wrote:
> If power well support is disabled via the i915.disable_power_well module
> option we should never enable DC states. Currently we would enable DC
> states even in this case during system suspend, where we need to disable
> all power wells regardless of the disable_power_well option.
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 30df9de..f0ca5134 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2034,6 +2034,9 @@ static uint32_t get_allowed_dc_mask(const struct
> drm_i915_private *dev_priv,
> mask = 0;
> }
>
> + if (!i915.disable_power_well)
> + max_dc = 0;
> +
> if (enable_dc >= 0 && enable_dc <= max_dc) {
> requested_dc = enable_dc;
> } else if (enable_dc == -1) {
> --
> 2.5.0
>
--
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Re: [Intel-gfx] [PATCH v2 2/4] drm/i915/gen9: Sanitize handling of allowed DC states
On Mon, Feb 29, 2016 at 10:49:03PM +0200, Imre Deak wrote:
> We can simplify the conditions selecting the target DC state during
> runtime by calculating the allowed DC states in advance during driver
> loading. This also makes it easier to disable DC states depending on the
> i915.disable_power_well module option, added in the next patch.
>
> v2:
> - Print a debug message if the requested max DC value was adjusted due
> to a platform limit. Also debug print the calculated mask value. (Patrik)
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_runtime_pm.c | 78
> -
> 2 files changed, 58 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6712955..dc554dd 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -754,6 +754,7 @@ struct intel_csr {
> i915_reg_t mmioaddr[8];
> uint32_t mmiodata[8];
> uint32_t dc_state;
> + uint32_t allowed_dc_mask;
> };
>
> #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 6e54d97..30df9de 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -538,12 +538,8 @@ static void gen9_set_dc_state(struct drm_i915_private
> *dev_priv, uint32_t state)
> else
> mask |= DC_STATE_EN_UPTO_DC6;
>
> - WARN_ON_ONCE(state & ~mask);
> -
> - if (i915.enable_dc == 0)
> - state = DC_STATE_DISABLE;
> - else if (i915.enable_dc == 1 && state > DC_STATE_EN_UPTO_DC5)
> - state = DC_STATE_EN_UPTO_DC5;
> + if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
> + state &= dev_priv->csr.allowed_dc_mask;
>
> val = I915_READ(DC_STATE_EN);
> DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
> @@ -659,8 +655,7 @@ static void gen9_disable_dc5_dc6(struct drm_i915_private
> *dev_priv)
> {
> assert_can_disable_dc5(dev_priv);
>
> - if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> - i915.enable_dc != 0 && i915.enable_dc != 1)
> + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
> assert_can_disable_dc6(dev_priv);
>
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> @@ -839,26 +834,19 @@ static void gen9_dc_off_power_well_enable(struct
> drm_i915_private *dev_priv,
> static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> - i915.enable_dc != 0 && i915.enable_dc != 1)
> + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
> skl_enable_dc6(dev_priv);
> - else
> + else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
> gen9_enable_dc5(dev_priv);
> }
>
> static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - if (power_well->count > 0) {
> - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> - } else {
> - if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> - i915.enable_dc != 0 &&
> - i915.enable_dc != 1)
> - gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
> - else
> - gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
> - }
> + if (power_well->count > 0)
> + gen9_dc_off_power_well_enable(dev_priv, power_well);
> + else
> + gen9_dc_off_power_well_disable(dev_priv, power_well);
> }
>
> static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
> @@ -2023,6 +2011,52 @@ sanitize_disable_power_well_option(const struct
> drm_i915_private *dev_priv,
> return 1;
> }
>
> +static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
> + int enable_dc)
> +{
> + uint32_t mask;
> + int requested_dc;
> + int max_dc;
> +
> + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> + max_dc = 2;
> + mask = 0;
> + } else if (IS_BROXTON(dev_priv)) {
> +
Re: [Intel-gfx] [PATCH 4/4] drm/i915/gen9: Remove state asserts when disabling DC states
On Wed, Feb 24, 2016 at 07:57:46PM +0200, Imre Deak wrote:
> Disabling the DC states when it's already disabled is a valid scenario,
> for example during HW state sanitization during driver loading and
> resuming or when DC states are disabled via the i915.enable_dc or
> disable_power_well option.
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Nice to see these go.
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 41
> +
> 1 file changed, 1 insertion(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 7f65d5f..1661c2a 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -458,8 +458,6 @@ static void assert_can_enable_dc9(struct drm_i915_private
> *dev_priv)
> static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
> {
> WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
> - WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
> - "DC9 already programmed to be disabled.\n");
> WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
> "DC5 still not disabled.\n");
>
> @@ -602,18 +600,6 @@ static void assert_can_enable_dc5(struct
> drm_i915_private *dev_priv)
> assert_csr_loaded(dev_priv);
> }
>
> -static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
> -{
> - /*
> - * During initialization, the firmware may not be loaded yet.
> - * We still want to make sure that the DC enabling flag is cleared.
> - */
> - if (dev_priv->power_domains.initializing)
> - return;
> -
> - assert_rpm_wakelock_held(dev_priv);
> -}
> -
> static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
> {
> assert_can_enable_dc5(dev_priv);
> @@ -638,29 +624,6 @@ static void assert_can_enable_dc6(struct
> drm_i915_private *dev_priv)
> assert_csr_loaded(dev_priv);
> }
>
> -static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
> -{
> - /*
> - * During initialization, the firmware may not be loaded yet.
> - * We still want to make sure that the DC enabling flag is cleared.
> - */
> - if (dev_priv->power_domains.initializing)
> - return;
> -
> - WARN_ONCE(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
> - "DC6 already programmed to be disabled.\n");
> -}
> -
> -static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv)
> -{
> - assert_can_disable_dc5(dev_priv);
> -
> - if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
> - assert_can_disable_dc6(dev_priv);
> -
> - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> -}
> -
> void skl_enable_dc6(struct drm_i915_private *dev_priv)
> {
> assert_can_enable_dc6(dev_priv);
> @@ -673,8 +636,6 @@ void skl_enable_dc6(struct drm_i915_private *dev_priv)
>
> void skl_disable_dc6(struct drm_i915_private *dev_priv)
> {
> - assert_can_disable_dc6(dev_priv);
> -
> DRM_DEBUG_KMS("Disabling DC6\n");
>
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> @@ -828,7 +789,7 @@ static bool gen9_dc_off_power_well_enabled(struct
> drm_i915_private *dev_priv,
> static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - gen9_disable_dc5_dc6(dev_priv);
> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> }
>
> static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
> --
> 2.5.0
>
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Re: [Intel-gfx] [PATCH 3/4] drm/i915/gen9: Disable DC states if power well support is disabled
On Wed, Feb 24, 2016 at 07:57:45PM +0200, Imre Deak wrote:
> If power well support is disabled via the i915.disable_power_well module
> option we should never enable DC states. Currently we would enable DC
> states even in this case during system suspend, where we need to disable
> all power wells regardless of the disable_power_well option.
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 88df99e..7f65d5f 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2030,6 +2030,9 @@ static uint32_t get_allowed_dc_mask(const struct
> drm_i915_private *dev_priv,
> if (!HAS_CSR(dev_priv))
> return mask;
>
> + if (!i915.disable_power_well)
> + return mask;
> +
> mask |= DC_STATE_EN_UPTO_DC5;
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> mask |= DC_STATE_EN_UPTO_DC6;
> --
> 2.5.0
>
--
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Re: [Intel-gfx] [PATCH 2/4] drm/i915/gen9: Sanitize handling of allowed DC states
On Wed, Feb 24, 2016 at 07:57:44PM +0200, Imre Deak wrote:
> We can simplify the conditions selecting the target DC state during
> runtime by calculating the allowed DC states in advance during driver
> loading. This also makes it easier to disable DC states depending on the
> i915.disable_power_well module option, added in the next patch.
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_runtime_pm.c | 74
> +++--
> 2 files changed, 54 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 9e76bfc..b563de5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -750,6 +750,7 @@ struct intel_csr {
> i915_reg_t mmioaddr[8];
> uint32_t mmiodata[8];
> uint32_t dc_state;
> + uint32_t allowed_dc_mask;
> };
>
> #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 8276dc2..88df99e 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -538,12 +538,8 @@ static void gen9_set_dc_state(struct drm_i915_private
> *dev_priv, uint32_t state)
> else
> mask |= DC_STATE_EN_UPTO_DC6;
>
> - WARN_ON_ONCE(state & ~mask);
> -
> - if (i915.enable_dc == 0)
> - state = DC_STATE_DISABLE;
> - else if (i915.enable_dc == 1 && state > DC_STATE_EN_UPTO_DC5)
> - state = DC_STATE_EN_UPTO_DC5;
> + if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
> + state &= dev_priv->csr.allowed_dc_mask;
>
> val = I915_READ(DC_STATE_EN);
> DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
> @@ -659,8 +655,7 @@ static void gen9_disable_dc5_dc6(struct drm_i915_private
> *dev_priv)
> {
> assert_can_disable_dc5(dev_priv);
>
> - if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> - i915.enable_dc != 0 && i915.enable_dc != 1)
> + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
> assert_can_disable_dc6(dev_priv);
>
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> @@ -839,26 +834,19 @@ static void gen9_dc_off_power_well_enable(struct
> drm_i915_private *dev_priv,
> static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> - i915.enable_dc != 0 && i915.enable_dc != 1)
> + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
> skl_enable_dc6(dev_priv);
> - else
> + else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
> gen9_enable_dc5(dev_priv);
> }
>
> static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - if (power_well->count > 0) {
> - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> - } else {
> - if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> - i915.enable_dc != 0 &&
> - i915.enable_dc != 1)
> - gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
> - else
> - gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
> - }
> + if (power_well->count > 0)
> + gen9_dc_off_power_well_enable(dev_priv, power_well);
> + else
> + gen9_dc_off_power_well_disable(dev_priv, power_well);
> }
>
> static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
> @@ -2023,6 +2011,48 @@ sanitize_disable_power_well_option(const struct
> drm_i915_private *dev_priv,
> return 1;
> }
>
> +static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
> + int enable_dc)
> +{
> + uint32_t mask = 0;
> +
> + /*
> + * DC9 has a separate HW flow from the rest of the DC states, not
> + * depending on the DMC firmware. It's needed by system
> + * suspend/resume, so allow it unconditionally.
> + */
> + if (IS_BROXTON(dev_priv))
> + mask |= DC_STATE_EN_DC9;
> +
> + if (!enable_dc)
> + return mask;
> +
> + if (!HAS_CSR(dev_priv))
> + r
Re: [Intel-gfx] [PATCH 1/4] drm/i915/skl: Fix power domain suspend sequence
On Wed, Feb 24, 2016 at 07:57:43PM +0200, Imre Deak wrote:
> During system suspend we need to first disable power wells then
> unitialize the display core. In case power well support is disabled we
> did this in the wrong order, so fix this up.
>
> Fixes: d314cd43 ("drm/i915: fix handling of the disable_power_well module
> option")
> CC: sta...@vger.kernel.org
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index e232976..8276dc2 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2319,15 +2319,15 @@ void intel_power_domains_init_hw(struct
> drm_i915_private *dev_priv, bool resume)
> */
> void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
> {
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> - skl_display_core_uninit(dev_priv);
> -
> /*
>* Even if power well support was disabled we still want to disable
>* power wells while we are system suspended.
>*/
> if (!i915.disable_power_well)
> intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
> +
> + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> + skl_display_core_uninit(dev_priv);
> }
>
> /**
> --
> 2.5.0
>
--
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Re: [Intel-gfx] [PATCH] drm/i915/gen9: Check for DC state mismatch
On Thu, Feb 18, 2016 at 11:22 AM, Patrik Jakobsson
wrote:
> On Thu, Feb 18, 2016 at 12:16:40AM +, Vivi, Rodrigo wrote:
>> I was going to merge here but I saw on patchwork we got some warnings
>> so I'm not sure they are only false positives or this is exactly what
>> this patches wants...
>
> They are unfortunately not false positives. The question is if it's ok
> to clutter CI results with known errors or not? Together with Mika's and
> Imre's patches we shouldn't be seeing this but if we do we know we're
> not out of the deep water yet. Perhaps we can wait with this patch until
> the others are merged?
>
> -Patrik
I just tested Mika's tree (with all the required patches included) and
I see no "DC state mismatch" errors. If we wait with this one until
they are merged we wont unnecessarily clutter CI.
>
>>
>> On Thu, 2016-02-11 at 12:43 +0200, Mika Kuoppala wrote:
>> > Patrik Jakobsson writes:
>> >
>> > > The DMC can incorrectly run off and allow DC states on it's own. We
>> > > don't know the root-cause for this yet but this patch makes it more
>> > > visible.
>> > >
>> > > Signed-off-by: Patrik Jakobsson
>> >
>> > Yes, we definitely need much more state checking and hardening
>> > in this area.
>> >
>> > Reviewed-by: Mika Kuoppala
>> >
>> >
>> > > ---
>> > > drivers/gpu/drm/i915/i915_drv.h | 1 +
>> > > drivers/gpu/drm/i915/intel_csr.c| 2 ++
>> > > drivers/gpu/drm/i915/intel_runtime_pm.c | 8
>> > > 3 files changed, 11 insertions(+)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> > > b/drivers/gpu/drm/i915/i915_drv.h
>> > > index e11eef1..7e33454 100644
>> > > --- a/drivers/gpu/drm/i915/i915_drv.h
>> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
>> > > @@ -746,6 +746,7 @@ struct intel_csr {
>> > > uint32_t mmio_count;
>> > > i915_reg_t mmioaddr[8];
>> > > uint32_t mmiodata[8];
>> > > + uint32_t dc_state;
>> > > };
>> > >
>> > > #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
>> > > diff --git a/drivers/gpu/drm/i915/intel_csr.c
>> > > b/drivers/gpu/drm/i915/intel_csr.c
>> > > index 2a7ec31..b453fcc 100644
>> > > --- a/drivers/gpu/drm/i915/intel_csr.c
>> > > +++ b/drivers/gpu/drm/i915/intel_csr.c
>> > > @@ -243,6 +243,8 @@ void intel_csr_load_program(struct
>> > > drm_i915_private *dev_priv)
>> > > I915_WRITE(dev_priv->csr.mmioaddr[i],
>> > > dev_priv->csr.mmiodata[i]);
>> > > }
>> > > +
>> > > + dev_priv->csr.dc_state = 0;
>> > > }
>> > >
>> > > static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
>> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
>> > > b/drivers/gpu/drm/i915/intel_runtime_pm.c
>> > > index bbca527..e79674b 100644
>> > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
>> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
>> > > @@ -494,10 +494,18 @@ static void gen9_set_dc_state(struct
>> > > drm_i915_private *dev_priv, uint32_t state)
>> > > val = I915_READ(DC_STATE_EN);
>> > > DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
>> > > val & mask, state);
>> > > +
>> > > + /* Check if DMC is ignoring our DC state requests */
>> > > + if ((val & mask) != dev_priv->csr.dc_state)
>> > > + DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
>> > > + dev_priv->csr.dc_state, val & mask);
>> > > +
>> > > val &= ~mask;
>> > > val |= state;
>> > > I915_WRITE(DC_STATE_EN, val);
>> > > POSTING_READ(DC_STATE_EN);
>> > > +
>> > > + dev_priv->csr.dc_state = val & mask;
>> > > }
>> > >
>> > > void bxt_enable_dc9(struct drm_i915_private *dev_priv)
>
> --
> ---
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> Stockholm, Sweden Registration Number: 556189-6027
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Re: [Intel-gfx] [PATCH] drm/i915/gen9: Check for DC state mismatch
On Thu, Feb 18, 2016 at 12:16:40AM +, Vivi, Rodrigo wrote:
> I was going to merge here but I saw on patchwork we got some warnings
> so I'm not sure they are only false positives or this is exactly what
> this patches wants...
They are unfortunately not false positives. The question is if it's ok
to clutter CI results with known errors or not? Together with Mika's and
Imre's patches we shouldn't be seeing this but if we do we know we're
not out of the deep water yet. Perhaps we can wait with this patch until
the others are merged?
-Patrik
>
> On Thu, 2016-02-11 at 12:43 +0200, Mika Kuoppala wrote:
> > Patrik Jakobsson writes:
> >
> > > The DMC can incorrectly run off and allow DC states on it's own. We
> > > don't know the root-cause for this yet but this patch makes it more
> > > visible.
> > >
> > > Signed-off-by: Patrik Jakobsson
> >
> > Yes, we definitely need much more state checking and hardening
> > in this area.
> >
> > Reviewed-by: Mika Kuoppala
> >
> >
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > drivers/gpu/drm/i915/intel_csr.c| 2 ++
> > > drivers/gpu/drm/i915/intel_runtime_pm.c | 8
> > > 3 files changed, 11 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h
> > > index e11eef1..7e33454 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -746,6 +746,7 @@ struct intel_csr {
> > > uint32_t mmio_count;
> > > i915_reg_t mmioaddr[8];
> > > uint32_t mmiodata[8];
> > > + uint32_t dc_state;
> > > };
> > >
> > > #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
> > > diff --git a/drivers/gpu/drm/i915/intel_csr.c
> > > b/drivers/gpu/drm/i915/intel_csr.c
> > > index 2a7ec31..b453fcc 100644
> > > --- a/drivers/gpu/drm/i915/intel_csr.c
> > > +++ b/drivers/gpu/drm/i915/intel_csr.c
> > > @@ -243,6 +243,8 @@ void intel_csr_load_program(struct
> > > drm_i915_private *dev_priv)
> > > I915_WRITE(dev_priv->csr.mmioaddr[i],
> > > dev_priv->csr.mmiodata[i]);
> > > }
> > > +
> > > + dev_priv->csr.dc_state = 0;
> > > }
> > >
> > > static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > index bbca527..e79674b 100644
> > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -494,10 +494,18 @@ static void gen9_set_dc_state(struct
> > > drm_i915_private *dev_priv, uint32_t state)
> > > val = I915_READ(DC_STATE_EN);
> > > DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
> > > val & mask, state);
> > > +
> > > + /* Check if DMC is ignoring our DC state requests */
> > > + if ((val & mask) != dev_priv->csr.dc_state)
> > > + DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
> > > + dev_priv->csr.dc_state, val & mask);
> > > +
> > > val &= ~mask;
> > > val |= state;
> > > I915_WRITE(DC_STATE_EN, val);
> > > POSTING_READ(DC_STATE_EN);
> > > +
> > > + dev_priv->csr.dc_state = val & mask;
> > > }
> > >
> > > void bxt_enable_dc9(struct drm_i915_private *dev_priv)
--
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[Intel-gfx] [PATCH] drm/i915/gen9: Check for DC state mismatch
The DMC can incorrectly run off and allow DC states on it's own. We
don't know the root-cause for this yet but this patch makes it more
visible.
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_csr.c| 2 ++
drivers/gpu/drm/i915/intel_runtime_pm.c | 8
3 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e11eef1..7e33454 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -746,6 +746,7 @@ struct intel_csr {
uint32_t mmio_count;
i915_reg_t mmioaddr[8];
uint32_t mmiodata[8];
+ uint32_t dc_state;
};
#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 2a7ec31..b453fcc 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -243,6 +243,8 @@ void intel_csr_load_program(struct drm_i915_private
*dev_priv)
I915_WRITE(dev_priv->csr.mmioaddr[i],
dev_priv->csr.mmiodata[i]);
}
+
+ dev_priv->csr.dc_state = 0;
}
static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index bbca527..e79674b 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -494,10 +494,18 @@ static void gen9_set_dc_state(struct drm_i915_private
*dev_priv, uint32_t state)
val = I915_READ(DC_STATE_EN);
DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
val & mask, state);
+
+ /* Check if DMC is ignoring our DC state requests */
+ if ((val & mask) != dev_priv->csr.dc_state)
+ DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
+ dev_priv->csr.dc_state, val & mask);
+
val &= ~mask;
val |= state;
I915_WRITE(DC_STATE_EN, val);
POSTING_READ(DC_STATE_EN);
+
+ dev_priv->csr.dc_state = val & mask;
}
void bxt_enable_dc9(struct drm_i915_private *dev_priv)
--
2.5.0
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Re: [Intel-gfx] [PATCH v4] drm/i915: Handle PipeC fused off on IVB/HSW/BDW
On Fri, Jan 22, 2016 at 01:28:45PM +0200, Gabriel Feceoru wrote:
> Some Gen7/8 production parts may have the Display Pipe C fused off.
> In this case, the display hardware will prevent the enable bit in
> PIPE_CONF register (for Pipe C) from being set to 1.
>
> Fixed by adjusting pipe_count to reflect this.
>
> v2: Rename HSW_PIPE_C_DISABLE to IVB_PIPE_C_DISABLE as it already exists
> on ivybridge (Ville)
> v3: Remove unnecessary MMIO read, correct the description (Damien)
> v4: Be more specific in description (Patrick)
>
> Signed-off-by: Gabriel Feceoru
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_dma.c | 3 +++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index d70d96f..91404aa 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -816,6 +816,9 @@ static void intel_device_info_runtime_init(struct
> drm_device *dev)
>!(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
> DRM_INFO("Display fused off, disabling\n");
> info->num_pipes = 0;
> + } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
> + DRM_INFO("PipeC fused off\n");
> + info->num_pipes -= 1;
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0a98889..a182739 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5945,6 +5945,7 @@ enum skl_disp_power_wells {
> #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
> #define ILK_INTERNAL_DISPLAY_DISABLE(1 << 30)
> #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
> +#define IVB_PIPE_C_DISABLE (1 << 28)
> #define ILK_HDCP_DISABLE(1 << 25)
> #define ILK_eDP_A_DISABLE (1 << 24)
> #define HSW_CDCLK_LIMIT (1 << 24)
> --
> 1.9.1
>
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Re: [Intel-gfx] [PATCH] drm/i915/gen9: Probe power well 1 status on dc status query
On Wed, Jan 27, 2016 at 08:18:57PM +0200, Ville Syrjälä wrote:
> On Tue, Jan 26, 2016 at 05:45:31PM +0200, Mika Kuoppala wrote:
> > There has been cases where we read DC_STATE and get something that we
> > did not write there. As DMC owns power well 1, this could be that DMC
> > snoops DC_STATE accesses and needs to wake up power well 1 up to serve
> > the access. But the waking up power well 1 takes time and we might end up
> > reading during unfinished well wakeup.
> >
> > When we want the dc status, wake up DMC and make sure that DMC has
> > properly woken up well 1 before we read for the final value.
I was thinking about PW0 and not PW1 as in this patch. DC_STATE_EN is on PW0 so
this will not work (unless it by accident wakes the DMC). Also, I was under the
assumption we had control over PW0 but that doesn't seem to be the case.
> >
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=93768
> > Suggested-by: Patrik Jakobsson
> > Cc: Patrik Jakobsson
> > Cc: Imre Deak
> > Cc: Chris Wilson
> > Signed-off-by: Mika Kuoppala
> > ---
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 86
> > ++---
> > 1 file changed, 69 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index bbca527184d0..83c24e73cb88 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -418,15 +418,62 @@ static void hsw_set_power_well(struct
> > drm_i915_private *dev_priv,
> > BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
> > BIT(POWER_DOMAIN_INIT))
> >
> > +
> > +static bool __gen9_power_well_enabled(struct drm_i915_private *dev_priv,
> > + const enum skl_disp_power_wells pw,
> > + const bool req)
> > +{
> > + uint32_t mask = SKL_POWER_WELL_STATE(pw);
> > +
> > + if (req)
> > + mask |= SKL_POWER_WELL_REQ(pw);
> > +
> > + return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
> > +}
> > +
> > +static bool gen9_power_well_enabled(struct drm_i915_private *dev_priv,
> > + const enum skl_disp_power_wells pw)
> > +{
> > + return __gen9_power_well_enabled(dev_priv, pw, true);
> > +}
> > +
> > +static bool gen9_power_well_enabled_noreq(struct drm_i915_private
> > *dev_priv,
> > + const enum skl_disp_power_wells pw)
> > +{
> > + return __gen9_power_well_enabled(dev_priv, pw, false);
> > +}
> > +
> > +static bool gen9_pw1_enabled(struct drm_i915_private *dev_priv)
> > +{
> > + /* DMC owns the pw1. Don't check for request */
> > + return gen9_power_well_enabled_noreq(dev_priv, SKL_DISP_PW_1);
> > +}
> > +
> > +static u32 gen9_get_dc_state(struct drm_i915_private *dev_priv)
> > +{
> > + if (gen9_pw1_enabled(dev_priv))
> > + return I915_READ(DC_STATE_EN);
> > +
> > + /* DMC should snoop this and wakeup */
> > + I915_READ(DC_STATE_EN);
>
> Not sure it does. I don't think I've never seen a list of trapped
> registers anywhere.
In order to do what it's supposed to it needs to trap all accesses on PW1 and
possibly PW0. The PCU needs to be able to trap at least PW0. The PCU must trap
PW0 before the DMC since the DMC assumes that PW0 is powered when it's trap
routine for DC6 exit starts (PW0 restore).
>
> Assuming it does, it would quite surprising that it would release
> the trap before it actually woke up the hardware. I guess it might be
> possible if the registers don't actually live inside the power well
> (they'd have to live in power well 0 then I suppose). But that would
> seem to open up races all over the place where we have to touch a
> register also touched by the DMC, so it would seem like a fairly major
> problem to me.
It does trap and hold until it has restored power but powering on can fail and
if that happens it sends an interrupt and flips a few magic bits depending on
the
failure. Not sure if there is a way for us to detect that or if it's only
intended for the PCU. Also not sure if we can recover from that with full DC
state functionality.
>
> If it doesn't trap this, well, then we should just be able to access
> any actually trapped register, and that should kick the DMC out of
> DC5/6.
>
> That DC_STATE_EN seems to change on its own is still baffling me. One
> idea I had is that the pcu might do the save/restore for DC_STATE_EN,
&
[Intel-gfx] [PATCH v3] drm/i915/skl/kbl: Add support for pipe fusing
On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The
pipes must be fused in descending order (e.g. C, B+C, A+B+C). We simply
decrease info->num_pipes if we find a valid fused out config.
v2: Don't store the pipe disabled mask in device info (Damien)
v3: Don't check FUSE_STRAP register for pipe c disabled
Cc: Damien Lespiau
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/i915_dma.c | 31 +++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 44a896c..daaa67f 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -814,6 +814,37 @@ static void intel_device_info_runtime_init(struct
drm_device *dev)
DRM_INFO("Display fused off, disabling\n");
info->num_pipes = 0;
}
+ } else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) {
+ u32 dfsm = I915_READ(SKL_DFSM);
+ u8 disabled_mask = 0;
+ bool invalid;
+ int num_bits;
+
+ if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
+ disabled_mask |= BIT(PIPE_A);
+ if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
+ disabled_mask |= BIT(PIPE_B);
+ if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
+ disabled_mask |= BIT(PIPE_C);
+
+ num_bits = hweight8(disabled_mask);
+
+ switch (disabled_mask) {
+ case BIT(PIPE_A):
+ case BIT(PIPE_B):
+ case BIT(PIPE_A) | BIT(PIPE_B):
+ case BIT(PIPE_A) | BIT(PIPE_C):
+ invalid = true;
+ break;
+ default:
+ invalid = false;
+ }
+
+ if (num_bits > info->num_pipes || invalid)
+ DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
+ disabled_mask);
+ else
+ info->num_pipes -= num_bits;
}
/* Initialize slice/subslice/EU info */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 556a458..c6e6a24 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5991,6 +5991,9 @@ enum skl_disp_power_wells {
#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
+#define SKL_DFSM_PIPE_A_DISABLE(1 << 30)
+#define SKL_DFSM_PIPE_B_DISABLE(1 << 21)
+#define SKL_DFSM_PIPE_C_DISABLE(1 << 28)
#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
#define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
--
2.5.0
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Re: [Intel-gfx] [PATCH] drm/i915/skl/kbl: Add support for pipe fusing
On Mon, Jan 18, 2016 at 06:01:27PM +0200, Ville Syrjälä wrote:
> On Mon, Jan 18, 2016 at 03:11:57PM +0100, Patrik Jakobsson wrote:
> > On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The
> > pipes must be fused in descending order (e.g. C, B+C, A+B+C). There are
> > several registers that can contain fuse settings so to simplify things
> > we keep around a mask in device info with bits for each disabled pipe.
> > This will also come in handy if the rule about the descending order is
> > changed on future platforms.
> >
> > Signed-off-by: Patrik Jakobsson
> > ---
> > drivers/gpu/drm/i915/i915_dma.c | 34 ++
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/i915_reg.h | 4
> > 3 files changed, 39 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_dma.c
> > b/drivers/gpu/drm/i915/i915_dma.c
> > index 988a380..2e9d47d 100644
> > --- a/drivers/gpu/drm/i915/i915_dma.c
> > +++ b/drivers/gpu/drm/i915/i915_dma.c
> > @@ -814,6 +814,40 @@ static void intel_device_info_runtime_init(struct
> > drm_device *dev)
> > DRM_INFO("Display fused off, disabling\n");
> > info->num_pipes = 0;
> > }
> > + } else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) {
> > + u32 fuse_strap = I915_READ(FUSE_STRAP);
> > + u32 dfsm = I915_READ(SKL_DFSM);
> > + bool invalid;
> > + int num_bits;
> > +
> > + if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
> > + info->pipe_disabled_mask |= BIT(PIPE_A);
> > + if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
> > + info->pipe_disabled_mask |= BIT(PIPE_B);
> > + if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
> > + info->pipe_disabled_mask |= BIT(PIPE_C);
> > +
> > + if (fuse_strap & SKL_DISPLAY_PIPE_C_DISABLE)
> > + info->pipe_disabled_mask |= BIT(PIPE_C);
> > +
> > + num_bits = hweight8(info->pipe_disabled_mask);
> > +
> > + switch (info->pipe_disabled_mask) {
> > + case BIT(PIPE_A):
> > + case BIT(PIPE_B):
> > + case BIT(PIPE_A) | BIT(PIPE_B):
> > + case BIT(PIPE_A) | BIT(PIPE_C):
> > + invalid = true;
> > + break;
> > + default:
> > + invalid = false;
> > + }
> > +
> > + if (num_bits > info->num_pipes || invalid)
> > + DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
> > + info->pipe_disabled_mask);
> > + else
> > + info->num_pipes -= num_bits;
> > }
> >
> > /* Initialize slice/subslice/EU info */
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index f0f75d7..2b4783c 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -792,6 +792,7 @@ struct intel_device_info {
> > u8 num_pipes:3;
> > u8 num_sprites[I915_MAX_PIPES];
> > u8 gen;
> > + u8 pipe_disabled_mask;
> > u8 ring_mask; /* Rings supported by the HW */
> > DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
> > /* Register offsets for the various display pipes and transcoders */
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 7510d508..72f07e6 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5940,6 +5940,7 @@ enum skl_disp_power_wells {
> > #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
> > #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
> > #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
> > +#define SKL_DISPLAY_PIPE_C_DISABLE(1 << 28)
>
> Maybe you want to go review the other patch that wants to add this bit?
>
My bad, we shouldn't look at FUSE_STRAP on SKL+. I'll resend without it.
> > #define ILK_HDCP_DISABLE (1 << 25)
> > #define ILK_eDP_A_DISABLE (1 << 24)
> > #define HSW_CDCLK_LIMIT (1 << 24)
> > @@ -5986,6 +5987,9 @@ enum skl_disp_power_wells {
> > #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
> > #define SKL_DFSM_CDCLK_LIMIT_450
Re: [Intel-gfx] [PATCH v3] drm/i915: Handle PipeC fused off on IVB/HSW/BDW
On Wed, Jan 13, 2016 at 06:02:52PM +0200, Gabriel Feceoru wrote:
> Some Gen7/8 production parts may have the Display Pipe C fused off.
> In this case, the display hardware will prevent the Pipe C register bit
> from being set to 1.
Please elaborate on what pipe c register bit is prevented from being set.
Thanks
Patrik
>
> Fixed by adjusting pipe_count to reflect this.
>
> v2: Rename HSW_PIPE_C_DISABLE to IVB_PIPE_C_DISABLE as it already exists
> on ivybridge (Ville)
> v3: Remove unnecessary MMIO read, correct the description (Damien)
>
> Signed-off-by: Gabriel Feceoru
> ---
> drivers/gpu/drm/i915/i915_dma.c | 3 +++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 44a896c..dd0d100 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -813,6 +813,9 @@ static void intel_device_info_runtime_init(struct
> drm_device *dev)
>!(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
> DRM_INFO("Display fused off, disabling\n");
> info->num_pipes = 0;
> + } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
> + DRM_INFO("PipeC fused off\n");
> + info->num_pipes -= 1;
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0a98889..a182739 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5945,6 +5945,7 @@ enum skl_disp_power_wells {
> #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
> #define ILK_INTERNAL_DISPLAY_DISABLE(1 << 30)
> #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
> +#define IVB_PIPE_C_DISABLE (1 << 28)
> #define ILK_HDCP_DISABLE(1 << 25)
> #define ILK_eDP_A_DISABLE (1 << 24)
> #define HSW_CDCLK_LIMIT (1 << 24)
> --
> 1.9.1
>
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Re: [Intel-gfx] [PATCH] drm/i915/skl/kbl: Add support for pipe fusing
On Mon, Jan 18, 2016 at 06:01:27PM +0200, Ville Syrjälä wrote:
> On Mon, Jan 18, 2016 at 03:11:57PM +0100, Patrik Jakobsson wrote:
> > On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The
> > pipes must be fused in descending order (e.g. C, B+C, A+B+C). There are
> > several registers that can contain fuse settings so to simplify things
> > we keep around a mask in device info with bits for each disabled pipe.
> > This will also come in handy if the rule about the descending order is
> > changed on future platforms.
> >
> > Signed-off-by: Patrik Jakobsson
> > ---
> > drivers/gpu/drm/i915/i915_dma.c | 34 ++
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/i915_reg.h | 4
> > 3 files changed, 39 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_dma.c
> > b/drivers/gpu/drm/i915/i915_dma.c
> > index 988a380..2e9d47d 100644
> > --- a/drivers/gpu/drm/i915/i915_dma.c
> > +++ b/drivers/gpu/drm/i915/i915_dma.c
> > @@ -814,6 +814,40 @@ static void intel_device_info_runtime_init(struct
> > drm_device *dev)
> > DRM_INFO("Display fused off, disabling\n");
> > info->num_pipes = 0;
> > }
> > + } else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) {
> > + u32 fuse_strap = I915_READ(FUSE_STRAP);
> > + u32 dfsm = I915_READ(SKL_DFSM);
> > + bool invalid;
> > + int num_bits;
> > +
> > + if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
> > + info->pipe_disabled_mask |= BIT(PIPE_A);
> > + if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
> > + info->pipe_disabled_mask |= BIT(PIPE_B);
> > + if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
> > + info->pipe_disabled_mask |= BIT(PIPE_C);
> > +
> > + if (fuse_strap & SKL_DISPLAY_PIPE_C_DISABLE)
> > + info->pipe_disabled_mask |= BIT(PIPE_C);
> > +
> > + num_bits = hweight8(info->pipe_disabled_mask);
> > +
> > + switch (info->pipe_disabled_mask) {
> > + case BIT(PIPE_A):
> > + case BIT(PIPE_B):
> > + case BIT(PIPE_A) | BIT(PIPE_B):
> > + case BIT(PIPE_A) | BIT(PIPE_C):
> > + invalid = true;
> > + break;
> > + default:
> > + invalid = false;
> > + }
> > +
> > + if (num_bits > info->num_pipes || invalid)
> > + DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
> > + info->pipe_disabled_mask);
> > + else
> > + info->num_pipes -= num_bits;
> > }
> >
> > /* Initialize slice/subslice/EU info */
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index f0f75d7..2b4783c 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -792,6 +792,7 @@ struct intel_device_info {
> > u8 num_pipes:3;
> > u8 num_sprites[I915_MAX_PIPES];
> > u8 gen;
> > + u8 pipe_disabled_mask;
> > u8 ring_mask; /* Rings supported by the HW */
> > DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
> > /* Register offsets for the various display pipes and transcoders */
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 7510d508..72f07e6 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5940,6 +5940,7 @@ enum skl_disp_power_wells {
> > #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
> > #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
> > #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
> > +#define SKL_DISPLAY_PIPE_C_DISABLE(1 << 28)
>
> Maybe you want to go review the other patch that wants to add this bit?
>
Thanks for the heads up, I hadn't seen that one from Gabriel. I'll let his patch
land first.
> > #define ILK_HDCP_DISABLE (1 << 25)
> > #define ILK_eDP_A_DISABLE (1 << 24)
> > #define HSW_CDCLK_LIMIT (1 << 24)
> > @@ -5986,6 +5987,9 @@ enum skl_disp_power_wells {
> > #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
> > #define SKL_DF
[Intel-gfx] [PATCH] drm/i915/skl: Tune down DC6 already enabled warning
For unknown reasons the DMC firmware overwrites our DC5/6 bits in
the DC_STATE_EN register. This happens from time to time during the
igt@kms_flip@basic-flip-vs-dpms test. We manually fix up the register
when this occurs and so far that seems to work. This patch demotes the
warning to a debug message to not clutter our CI results.
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=93697
Cc: Daniel Vetter
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 89a7dd8..68e213c 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -574,8 +574,10 @@ static void assert_can_enable_dc6(struct drm_i915_private
*dev_priv)
WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
"Backlight is not disabled.\n");
- WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
- "DC6 already programmed to be enabled.\n");
+
+ /* Sometimes fw incorrectly modify our bits so just debug print this */
+ if ((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6))
+ DRM_DEBUG_KMS("DC6 already programmed to be enabled.\n");
assert_csr_loaded(dev_priv);
}
--
2.5.0
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[Intel-gfx] [PATCH v2] drm/i915/skl/kbl: Add support for pipe fusing
On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The
pipes must be fused in descending order (e.g. C, B+C, A+B+C). We simply
decrease info->num_pipes if we find a valid fused out config.
v2: Don't store the pipe disabled mask in device info (Damien)
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/i915_dma.c | 35 +++
drivers/gpu/drm/i915/i915_reg.h | 4
2 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 44a896c..852b49a 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -814,6 +814,41 @@ static void intel_device_info_runtime_init(struct
drm_device *dev)
DRM_INFO("Display fused off, disabling\n");
info->num_pipes = 0;
}
+ } else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) {
+ u32 fuse_strap = I915_READ(FUSE_STRAP);
+ u32 dfsm = I915_READ(SKL_DFSM);
+ u8 disabled_mask = 0;
+ bool invalid;
+ int num_bits;
+
+ if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
+ disabled_mask |= BIT(PIPE_A);
+ if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
+ disabled_mask |= BIT(PIPE_B);
+ if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
+ disabled_mask |= BIT(PIPE_C);
+
+ if (fuse_strap & SKL_DISPLAY_PIPE_C_DISABLE)
+ disabled_mask |= BIT(PIPE_C);
+
+ num_bits = hweight8(disabled_mask);
+
+ switch (disabled_mask) {
+ case BIT(PIPE_A):
+ case BIT(PIPE_B):
+ case BIT(PIPE_A) | BIT(PIPE_B):
+ case BIT(PIPE_A) | BIT(PIPE_C):
+ invalid = true;
+ break;
+ default:
+ invalid = false;
+ }
+
+ if (num_bits > info->num_pipes || invalid)
+ DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
+ disabled_mask);
+ else
+ info->num_pipes -= num_bits;
}
/* Initialize slice/subslice/EU info */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 556a458..39a965b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5945,6 +5945,7 @@ enum skl_disp_power_wells {
#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
+#define SKL_DISPLAY_PIPE_C_DISABLE(1 << 28)
#define ILK_HDCP_DISABLE (1 << 25)
#define ILK_eDP_A_DISABLE (1 << 24)
#define HSW_CDCLK_LIMIT (1 << 24)
@@ -5991,6 +5992,9 @@ enum skl_disp_power_wells {
#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
+#define SKL_DFSM_PIPE_A_DISABLE(1 << 30)
+#define SKL_DFSM_PIPE_B_DISABLE(1 << 21)
+#define SKL_DFSM_PIPE_C_DISABLE(1 << 28)
#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
#define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
--
2.5.0
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[Intel-gfx] [PATCH] drm/i915/skl/kbl: Add support for pipe fusing
On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The
pipes must be fused in descending order (e.g. C, B+C, A+B+C). There are
several registers that can contain fuse settings so to simplify things
we keep around a mask in device info with bits for each disabled pipe.
This will also come in handy if the rule about the descending order is
changed on future platforms.
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/i915_dma.c | 34 ++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 4
3 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 988a380..2e9d47d 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -814,6 +814,40 @@ static void intel_device_info_runtime_init(struct
drm_device *dev)
DRM_INFO("Display fused off, disabling\n");
info->num_pipes = 0;
}
+ } else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) {
+ u32 fuse_strap = I915_READ(FUSE_STRAP);
+ u32 dfsm = I915_READ(SKL_DFSM);
+ bool invalid;
+ int num_bits;
+
+ if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
+ info->pipe_disabled_mask |= BIT(PIPE_A);
+ if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
+ info->pipe_disabled_mask |= BIT(PIPE_B);
+ if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
+ info->pipe_disabled_mask |= BIT(PIPE_C);
+
+ if (fuse_strap & SKL_DISPLAY_PIPE_C_DISABLE)
+ info->pipe_disabled_mask |= BIT(PIPE_C);
+
+ num_bits = hweight8(info->pipe_disabled_mask);
+
+ switch (info->pipe_disabled_mask) {
+ case BIT(PIPE_A):
+ case BIT(PIPE_B):
+ case BIT(PIPE_A) | BIT(PIPE_B):
+ case BIT(PIPE_A) | BIT(PIPE_C):
+ invalid = true;
+ break;
+ default:
+ invalid = false;
+ }
+
+ if (num_bits > info->num_pipes || invalid)
+ DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
+ info->pipe_disabled_mask);
+ else
+ info->num_pipes -= num_bits;
}
/* Initialize slice/subslice/EU info */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f0f75d7..2b4783c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -792,6 +792,7 @@ struct intel_device_info {
u8 num_pipes:3;
u8 num_sprites[I915_MAX_PIPES];
u8 gen;
+ u8 pipe_disabled_mask;
u8 ring_mask; /* Rings supported by the HW */
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
/* Register offsets for the various display pipes and transcoders */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7510d508..72f07e6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5940,6 +5940,7 @@ enum skl_disp_power_wells {
#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
+#define SKL_DISPLAY_PIPE_C_DISABLE(1 << 28)
#define ILK_HDCP_DISABLE (1 << 25)
#define ILK_eDP_A_DISABLE (1 << 24)
#define HSW_CDCLK_LIMIT (1 << 24)
@@ -5986,6 +5987,9 @@ enum skl_disp_power_wells {
#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
+#define SKL_DFSM_PIPE_A_DISABLE(1 << 30)
+#define SKL_DFSM_PIPE_B_DISABLE(1 << 21)
+#define SKL_DFSM_PIPE_C_DISABLE(1 << 28)
#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
#define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
--
2.5.0
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Re: [Intel-gfx] [PATCH 08/22] drm/gma500: Remove empty preclose hook
On Mon, Jan 11, 2016 at 10:41 PM, Daniel Vetter wrote:
> I'm auditing them all, empty ones just confuse ...
>
> Cc: Patrik Jakobsson
> Acked-by: Daniel Stone
> Reviewed-by: Alex Deucher
> Signed-off-by: Daniel Vetter
Acked-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/gma500/psb_drv.c | 9 -
> 1 file changed, 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/gma500/psb_drv.c
> b/drivers/gpu/drm/gma500/psb_drv.c
> index 92e7e5795398..4e1c6850520e 100644
> --- a/drivers/gpu/drm/gma500/psb_drv.c
> +++ b/drivers/gpu/drm/gma500/psb_drv.c
> @@ -442,14 +442,6 @@ static long psb_unlocked_ioctl(struct file *filp,
> unsigned int cmd,
> /* FIXME: do we need to wrap the other side of this */
> }
>
> -/*
> - * When a client dies:
> - *- Check for and clean up flipped page state
> - */
> -static void psb_driver_preclose(struct drm_device *dev, struct drm_file
> *priv)
> -{
> -}
> -
> static int psb_pci_probe(struct pci_dev *pdev, const struct pci_device_id
> *ent)
> {
> return drm_get_pci_dev(pdev, ent, &driver);
> @@ -495,7 +487,6 @@ static struct drm_driver driver = {
> .load = psb_driver_load,
> .unload = psb_driver_unload,
> .lastclose = psb_driver_lastclose,
> - .preclose = psb_driver_preclose,
> .set_busid = drm_pci_set_busid,
>
> .num_ioctls = ARRAY_SIZE(psb_ioctls),
> --
> 2.6.4
>
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[Intel-gfx] [PATCH] drm/i915/skl: Use alternate aux power domain for port E
There is no dedicated aux channel for port E on SKL. Instead the VBT
describes which of the other aux channels to use. When grabbing an aux
power domain for port E we need to take this into account.
Cc: Ville Syrjälä
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/intel_display.c | 19 +++
drivers/gpu/drm/i915/intel_dp.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 0743337..86c89d4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5212,8 +5212,11 @@ static enum intel_display_power_domain
port_to_power_domain(enum port port)
}
}
-static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
+static enum intel_display_power_domain port_to_aux_power_domain(
+ struct drm_i915_private *dev_priv, enum port port)
{
+ enum port alternate_port;
+
switch (port) {
case PORT_A:
return POWER_DOMAIN_AUX_A;
@@ -5224,7 +5227,14 @@ static enum intel_display_power_domain
port_to_aux_power_domain(enum port port)
case PORT_D:
return POWER_DOMAIN_AUX_D;
case PORT_E:
- /* FIXME: Check VBT for actual wiring of PORT E */
+ if (IS_SKYLAKE(dev_priv)) {
+ alternate_port = skl_porte_aux_port(dev_priv);
+ if (alternate_port != PORT_E)
+ return port_to_aux_power_domain(dev_priv,
+ alternate_port);
+ WARN_ON_ONCE(alternate_port == PORT_E);
+ }
+
return POWER_DOMAIN_AUX_D;
default:
MISSING_CASE(port);
@@ -5263,6 +5273,7 @@ enum intel_display_power_domain
intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
{
struct drm_device *dev = intel_encoder->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_digital_port *intel_dig_port;
switch (intel_encoder->type) {
@@ -5279,10 +5290,10 @@ intel_display_port_aux_power_domain(struct
intel_encoder *intel_encoder)
case INTEL_OUTPUT_DISPLAYPORT:
case INTEL_OUTPUT_EDP:
intel_dig_port = enc_to_dig_port(&intel_encoder->base);
- return port_to_aux_power_domain(intel_dig_port->port);
+ return port_to_aux_power_domain(dev_priv, intel_dig_port->port);
case INTEL_OUTPUT_DP_MST:
intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
- return port_to_aux_power_domain(intel_dig_port->port);
+ return port_to_aux_power_domain(dev_priv, intel_dig_port->port);
default:
MISSING_CASE(intel_encoder->type);
return POWER_DOMAIN_AUX_A;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f2bfca0..81eb558 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1070,7 +1070,7 @@ static i915_reg_t ilk_aux_data_reg(struct
drm_i915_private *dev_priv,
* On SKL we don't have Aux for port E so we rely
* on VBT to set a proper alternate aux channel.
*/
-static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
+enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
{
const struct ddi_vbt_port_info *info =
&dev_priv->vbt.ddi_port_info[PORT_E];
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8fae824..1ef2c0e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1248,6 +1248,7 @@ void intel_dp_hot_plug(struct intel_encoder
*intel_encoder);
void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
void intel_plane_destroy(struct drm_plane *plane);
+enum port skl_porte_aux_port(struct drm_i915_private *dev_priv);
void intel_edp_drrs_enable(struct intel_dp *intel_dp);
void intel_edp_drrs_disable(struct intel_dp *intel_dp);
void intel_edp_drrs_invalidate(struct drm_device *dev,
--
2.5.0
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Re: [Intel-gfx] [PATCH v4 2/5] drm: Add private data field to trace control block
On Tue, Nov 24, 2015 at 6:46 AM, Dmitry V. Levin wrote:
> On Mon, Sep 07, 2015 at 08:23:57PM +0200, Patrik Jakobsson wrote:
>> On Mon, Sep 7, 2015 at 6:51 PM, Dmitry V. Levin wrote:
>> > On Mon, Aug 31, 2015 at 02:37:07PM +0200, Patrik Jakobsson wrote:
>> > [...]
>> >> Here's my take on it (I assume it needs some discussion):
>> >>
>> >> int
>> >> set_tcb_priv_data(struct tcb *tcp, void *priv_data)
>> >> {
>> >> /* A free callback is required before setting private data and
>> >> private
>> >>* data must be set back to NULL before being set again.
>> >>*/
>> >
>> > I think a single function initializing both _priv_data and _free_priv_data
>> > would suffice:
>> >
>> > int
>> > set_tcb_priv_data(struct tcb *tcp, void *priv_data,
>> > void (*free_priv_data)(void *))
>> > {
>> > if (tcp->_priv_data)
>> > return -1;
>> >
>> > tcp->_free_priv_data = free_priv_data;
>> > tcp->_priv_data = priv_data;
>> >
>> > return 0;
>> > }
>>
>> Sure, and since they always come in a pairs it might be even better. If it
>> turns
>> out we need it split up it is easily done later.
>
> The discussion seems to be stalled.
> Patrik, would you like to prepare a patch?
Hi Dmitry
I'll send you new patches this weekend. Thanks for reminding me.
-Patrik
>
>
> --
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Re: [Intel-gfx] [PATCH] drm/i915: Add some more bits to CURSOR_POS_MASK
On Wed, Nov 25, 2015 at 1:54 PM, Robert Fekete
wrote:
> On ons, 2015-11-18 at 10:17 +0100, Daniel Vetter wrote:
>> On Wed, Nov 04, 2015 at 10:59:28AM +0100, Patrik Jakobsson wrote:
>> > On Wed, Nov 04, 2015 at 10:35:19AM +0100, Robert Fekete wrote:
>> > > The old value of 0x7FF will wrap the position at 2048 giving wrong
>> > > coordinate values on panels larger than 2048 pixels in any direction.
>> > > Used in i915_debugfs atm. Looking at all hw specs available at 01.org
>> > > shows that X position is bit 0:11, and even 0:12 on some hw where
>> > > remaining bits up to bit 14 is MBZ. For Y position it is bits 16-27
>> > > where bits 28:30 is MBZ. It should be safe to increase CURSOR_POS_MASK
>> > > to 13 bits (0x1FFF) making 8192 as a new wrap around value still getting
>> > > valid cursor positions on platforms with only 12bits available thanks to
>> > > MBZ on adjacent bits above.
>> >
>> > I cannot find documentation for older hardware and this only touches
>> > debugfs, so in worst case we get wrong values for really old hardware but
>> > good
>> > ones for newer. I think that's a fair tradeoff.
>> >
>> > Reviewed-by: Patrik Jakobsson
>>
>> If it's only used in debugfs then imo just drop it. Having a _MASK which
>> isn't valid on all platforms, but where we don't have differnt #defines
>> for the different platforms is really confusing.
>> -Daniel
Yes, seems fair.
>
> Well, not the most important patch around, but still the value of 0x7ff
> is still too conservative and gives wrong cursor pos values on large
> panels. I have hard times digging up really old register specs so I
> still can't see which Intel platform this new value of mine isn't valid
> on.
I think Daniel meant that we can remove the define altogether and
hardcode a sane mask in debugfs instead. Keeping the define around
might give people the wrong idea what the bspec actually says. Also
adding a comment along with the hardcoded mask in debugfs would be
nice.
-Patrik
>
> It is this patch by Chris in debugfs that is broken on large panels
> wrapping coords at (x_pos/y_pos > 2048)
> http://marc.info/?l=git-commits-head&m=139697989108096&w=1
>
>> >
>> > >
>> > > Signed-off-by: Robert Fekete
>> > > ---
>> > > drivers/gpu/drm/i915/i915_reg.h | 2 +-
>> > > 1 file changed, 1 insertion(+), 1 deletion(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> > > b/drivers/gpu/drm/i915/i915_reg.h
>> > > index 894253228947..f351f46f8cb9 100644
>> > > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > > @@ -4883,7 +4883,7 @@ enum skl_disp_power_wells {
>> > > #define CURSOR_TRICKLE_FEED_DISABLE(1 << 14)
>> > > #define _CURABASE0x70084
>> > > #define _CURAPOS 0x70088
>> > > -#define CURSOR_POS_MASK 0x007FF
>> > > +#define CURSOR_POS_MASK 0x01FFF
>> > > #define CURSOR_POS_SIGN 0x8000
>> > > #define CURSOR_X_SHIFT0
>> > > #define CURSOR_Y_SHIFT16
>> > > --
>> > > 1.9.1
>> > >
>> > > ___
>> > > Intel-gfx mailing list
>> > > Intel-gfx@lists.freedesktop.org
>> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> > ___
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>
> --
> BR
> /Robert Fekete
> Intel Open Source Technology Center
>
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Re: [Intel-gfx] [PATCH] drm/i915/skl: re-enable power well support
On Wed, Nov 18, 2015 at 07:53:50PM +0200, Imre Deak wrote:
> Now that the known DMC/DC issues are fixed, let's try again and
> re-enable the power well support.
>
> Signed-off-by: Imre Deak
Together with the PC9/10 fix this is:
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 5 -
> 1 file changed, 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index a1dc815..10154a7 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -1841,11 +1841,6 @@ sanitize_disable_power_well_option(const struct
> drm_i915_private *dev_priv,
> if (disable_power_well >= 0)
> return !!disable_power_well;
>
> - if (IS_SKYLAKE(dev_priv)) {
> - DRM_DEBUG_KMS("Disabling display power well support\n");
> - return 0;
> - }
> -
> return 1;
> }
>
> --
> 2.5.0
>
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Re: [Intel-gfx] [PATCH] drm/i915/skl: enable PC9/10 power states during suspend-to-idle
On Thu, Nov 19, 2015 at 04:06:47PM +0200, Imre Deak wrote:
> On to, 2015-11-19 at 14:34 +0100, Patrik Jakobsson wrote:
> > On Wed, Nov 18, 2015 at 06:44:43PM +0200, Imre Deak wrote:
> > > On ke, 2015-11-18 at 17:33 +0100, Daniel Vetter wrote:
> > > > On Wed, Nov 18, 2015 at 05:32:30PM +0200, Imre Deak wrote:
> > > > > During suspend-to-idle we need to keep the DMC firmware active and DC6
> > > > > enabled, since otherwise we won't reach deep system power states like
> > > > > PC9/10. The lead for this came from Nivedita who noticed that the
> > > > > kernel's turbostat tool didn't report any PC9/10 residency change
> > > > > across an 'echo freeze > /sys/power/state'.
> > > > >
> > > > > Reported-by: Nivedita Swaminathan
> > > > > Signed-off-by: Imre Deak
> > > > > ---
> > > > > drivers/gpu/drm/i915/i915_drv.c | 44
> > > > > +++--
> > > > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > > > 2 files changed, 35 insertions(+), 10 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > > > > b/drivers/gpu/drm/i915/i915_drv.c
> > > > > index 6344dfb..649e20a 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > > > @@ -624,6 +624,14 @@ static int vlv_resume_prepare(struct
> > > > > drm_i915_private *dev_priv,
> > > > > bool rpm_resume);
> > > > > static int bxt_resume_prepare(struct drm_i915_private *dev_priv);
> > > > >
> > > > > +static bool suspend_to_idle(struct drm_i915_private *dev_priv)
> > > > > +{
> > > > > +#if IS_ENABLED(CONFIG_ACPI_SLEEP)
> > > > > + if (acpi_target_system_state() < ACPI_STATE_S3)
> > > > > + return true;
> > > > > +#endif
> > > > > + return false;
> > > > > +}
> > > > >
> > > > > static int i915_drm_suspend(struct drm_device *dev)
> > > > > {
> > > > > @@ -676,11 +684,7 @@ static int i915_drm_suspend(struct drm_device
> > > > > *dev)
> > > > >
> > > > > i915_save_state(dev);
> > > > >
> > > > > - opregion_target_state = PCI_D3cold;
> > > > > -#if IS_ENABLED(CONFIG_ACPI_SLEEP)
> > > > > - if (acpi_target_system_state() < ACPI_STATE_S3)
> > > > > - opregion_target_state = PCI_D1;
> > > > > -#endif
> > > > > + opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 :
> > > > > PCI_D3cold;
> > > > > intel_opregion_notify_adapter(dev, opregion_target_state);
> > > > >
> > > > > intel_uncore_forcewake_reset(dev, false);
> > > > > @@ -701,15 +705,26 @@ static int i915_drm_suspend(struct drm_device
> > > > > *dev)
> > > > > static int i915_drm_suspend_late(struct drm_device *drm_dev, bool
> > > > > hibernation)
> > > > > {
> > > > > struct drm_i915_private *dev_priv = drm_dev->dev_private;
> > > > > + bool fw_csr;
> > > > > int ret;
> > > > >
> > > > > - intel_power_domains_suspend(dev_priv);
> > > > > + fw_csr = suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
> > > > > + /*
> > > > > + * In case of firmware assisted context save/restore don't
> > > > > manually
> > > > > + * deinit the power domains. This also means the CSR/DMC
> > > > > firmware will
> > > > > + * stay active, it will power down any HW resources as required
> > > > > and
> > > > > + * also enable deeper system power states that would be blocked
> > > > > if the
> > > > > + * firmware was inactive.
> > > > > + */
> > > > > + if (!fw_csr)
> > > > > + intel_power_domains_suspend(dev_priv);
> > > > >
> > > > > ret = intel_suspend_complete(dev_priv);
> > > > >
> > > > > if (ret) {
> > > > > DRM_ERROR("Suspend complete faile
Re: [Intel-gfx] [PATCH] drm/i915/skl: enable PC9/10 power states during suspend-to-idle
On Wed, Nov 18, 2015 at 06:44:43PM +0200, Imre Deak wrote:
> On ke, 2015-11-18 at 17:33 +0100, Daniel Vetter wrote:
> > On Wed, Nov 18, 2015 at 05:32:30PM +0200, Imre Deak wrote:
> > > During suspend-to-idle we need to keep the DMC firmware active and DC6
> > > enabled, since otherwise we won't reach deep system power states like
> > > PC9/10. The lead for this came from Nivedita who noticed that the
> > > kernel's turbostat tool didn't report any PC9/10 residency change
> > > across an 'echo freeze > /sys/power/state'.
> > >
> > > Reported-by: Nivedita Swaminathan
> > > Signed-off-by: Imre Deak
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.c | 44
> > > +++--
> > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > 2 files changed, 35 insertions(+), 10 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > > b/drivers/gpu/drm/i915/i915_drv.c
> > > index 6344dfb..649e20a 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -624,6 +624,14 @@ static int vlv_resume_prepare(struct
> > > drm_i915_private *dev_priv,
> > > bool rpm_resume);
> > > static int bxt_resume_prepare(struct drm_i915_private *dev_priv);
> > >
> > > +static bool suspend_to_idle(struct drm_i915_private *dev_priv)
> > > +{
> > > +#if IS_ENABLED(CONFIG_ACPI_SLEEP)
> > > + if (acpi_target_system_state() < ACPI_STATE_S3)
> > > + return true;
> > > +#endif
> > > + return false;
> > > +}
> > >
> > > static int i915_drm_suspend(struct drm_device *dev)
> > > {
> > > @@ -676,11 +684,7 @@ static int i915_drm_suspend(struct drm_device *dev)
> > >
> > > i915_save_state(dev);
> > >
> > > - opregion_target_state = PCI_D3cold;
> > > -#if IS_ENABLED(CONFIG_ACPI_SLEEP)
> > > - if (acpi_target_system_state() < ACPI_STATE_S3)
> > > - opregion_target_state = PCI_D1;
> > > -#endif
> > > + opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
> > > intel_opregion_notify_adapter(dev, opregion_target_state);
> > >
> > > intel_uncore_forcewake_reset(dev, false);
> > > @@ -701,15 +705,26 @@ static int i915_drm_suspend(struct drm_device *dev)
> > > static int i915_drm_suspend_late(struct drm_device *drm_dev, bool
> > > hibernation)
> > > {
> > > struct drm_i915_private *dev_priv = drm_dev->dev_private;
> > > + bool fw_csr;
> > > int ret;
> > >
> > > - intel_power_domains_suspend(dev_priv);
> > > + fw_csr = suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
> > > + /*
> > > + * In case of firmware assisted context save/restore don't manually
> > > + * deinit the power domains. This also means the CSR/DMC firmware will
> > > + * stay active, it will power down any HW resources as required and
> > > + * also enable deeper system power states that would be blocked if the
> > > + * firmware was inactive.
> > > + */
> > > + if (!fw_csr)
> > > + intel_power_domains_suspend(dev_priv);
> > >
> > > ret = intel_suspend_complete(dev_priv);
> > >
> > > if (ret) {
> > > DRM_ERROR("Suspend complete failed: %d\n", ret);
> > > - intel_power_domains_init_hw(dev_priv, true);
> > > + if (!fw_csr)
> > > + intel_power_domains_init_hw(dev_priv, true);
> > >
> > > return ret;
> > > }
> > > @@ -730,6 +745,8 @@ static int i915_drm_suspend_late(struct drm_device
> > > *drm_dev, bool hibernation)
> > > if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
> > > pci_set_power_state(drm_dev->pdev, PCI_D3hot);
> > >
> > > + dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
> > > +
> > > return 0;
> > > }
> > >
> > > @@ -842,8 +859,10 @@ static int i915_drm_resume_early(struct drm_device
> > > *dev)
> > > * FIXME: This should be solved with a special hdmi sink device or
> > > * similar so that power domains can be employed.
> > > */
> > > - if (pci_enable_device(dev->pdev))
> > > - return -EIO;
> > > + if (pci_enable_device(dev->pdev)) {
> > > + ret = -EIO;
> > > + goto out;
> > > + }
> > >
> > > pci_set_master(dev->pdev);
> > >
> > > @@ -861,7 +880,12 @@ static int i915_drm_resume_early(struct drm_device
> > > *dev)
> > > hsw_disable_pc8(dev_priv);
> > >
> > > intel_uncore_sanitize(dev);
> > > - intel_power_domains_init_hw(dev_priv, true);
> > > +
> > > + if (!(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
> > > + intel_power_domains_init_hw(dev_priv, true);
> >
> > This doesn't work when e.g. system suspend to S3 fails, in which case dmc
> > will also survive. We need the pm core to tell us what really happened,
> > and Rafael Wyzocki was working on patches for that:
> >
> > http://lkml.iu.edu/hypermail/linux/kernel/1510.0/04266.html
> >
> > Specifically we need the pm_suspend/resume_via_firmware helpers.
> > Unfortunately these didn't make it into 4.4, so we need to pick Rafael.
>
> I think it does work. We deactivate
