Re: [Intel-gfx] [PATCH 05/40] drm/i915: Don't disable PPGTT for CHV based in PCI rev
On Saturday 28 June 2014 04:33 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
In
commit 62942ed7279d3e06dc15ae3d47665eff3b373327
Author: Jesse Barnes jbar...@virtuousgeek.org
Date: Fri Jun 13 09:28:33 2014 -0700
drm/i915/vlv: disable PPGTT on early revs v3
we forgot about CHV. IS_VALLEYVIEW() is true for CHV, so we need to
explicitly avoid disabling PPGTT on CHV.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a4153ee..5188936 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -64,7 +64,8 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int
enable_ppgtt)
#endif
/* Early VLV doesn't have this */
- if (IS_VALLEYVIEW(dev) dev-pdev-revision 0xb) {
+ if (IS_VALLEYVIEW(dev) !IS_CHERRYVIEW(dev)
+ dev-pdev-revision 0xb) {
DRM_DEBUG_DRIVER(disabling PPGTT on pre-B3 step VLV\n);
return 0;
}
Reviewed-by: Deepak S deepa...@linux.intel.com
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Re: [Intel-gfx] [PATCH 3/7] drm/i915: keep freq/opcode conversion function more generic
On Thursday 10 July 2014 11:58 AM, Daniel Vetter wrote: On Fri, Jul 11, 2014 at 09:56:35AM +0530, Deepak S wrote: On Wednesday 09 July 2014 05:33 PM, Daniel Vetter wrote: On Thu, Jul 10, 2014 at 01:16:23PM +0530, deepa...@linux.intel.com wrote: From: Deepak S deepa...@linux.intel.com Since freq/encode conversion formula changes from platform to platform, create a generic wrapper function and having platform check inside this help to simpilfy adding newer platform freq/opcode conversion. Signed-off-by: Deepak S deepa...@linux.intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 14 +- drivers/gpu/drm/i915/i915_drv.h | 4 +-- drivers/gpu/drm/i915/i915_sysfs.c | 18 ++--- drivers/gpu/drm/i915/intel_pm.c | 52 +++-- 4 files changed, 56 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index b3b56c4..dd7078d 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1140,14 +1140,14 @@ static int i915_frequency_info(struct seq_file *m, void *unused) val = valleyview_rps_max_freq(dev_priv); seq_printf(m, max GPU freq: %d MHz\n, - vlv_gpu_freq(dev_priv, val)); + intel_gpu_freq(dev_priv, val)); intel_ is a bit too generic a prefix for a function which seems to be only used on byt+chv. I'd just add a if (IS_CHERRYVIEW) ... else /* vlv code */ to both functions and not extract further. Aside: Since marketing stopped using vlv and switched to byt we're using vlv for code shared by byt and chv and byt_ for byt-only code. Helps a bit to keep things appart. -Daniel Ok. Will it be Ok to use vlv_gpu_freq and have BYT and CHV check under this function? Yeah, that's my idea. The reason why i made more generic is it will help us to add conversion logic for future platforms We can look at this again when it happpens. With the current code this doesn't include desktop rps so the intel_ prefix was a bit confusing. -Daniel Ok. Thanks for the feedback. I will update and send new patch set ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/7] drm/i915: Add RP0/RP1/RPn render P state thresholds in VLV sysfs
From: Deepak S deepa...@linux.intel.com
This is useful for userspace utilities to verify and micromanaging the
increase/decrease frequncy.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_sysfs.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index 86ce39a..b15c8ce 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -461,11 +461,20 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct
device_attribute *attr
mutex_unlock(dev-struct_mutex);
if (attr == dev_attr_gt_RP0_freq_mhz) {
- val = ((rp_state_cap 0xff) 0) *
GT_FREQUENCY_MULTIPLIER;
+ if (IS_VALLEYVIEW(dev))
+ val = vlv_gpu_freq(dev_priv, dev_priv-rps.rp0_freq);
+ else
+ val = ((rp_state_cap 0xff) 0) *
GT_FREQUENCY_MULTIPLIER;
} else if (attr == dev_attr_gt_RP1_freq_mhz) {
- val = ((rp_state_cap 0x00ff00) 8) *
GT_FREQUENCY_MULTIPLIER;
+ if (IS_VALLEYVIEW(dev))
+ val = vlv_gpu_freq(dev_priv, dev_priv-rps.rp1_freq);
+ else
+ val = ((rp_state_cap 0x00ff00) 8) *
GT_FREQUENCY_MULTIPLIER;
} else if (attr == dev_attr_gt_RPn_freq_mhz) {
- val = ((rp_state_cap 0xff) 16) *
GT_FREQUENCY_MULTIPLIER;
+ if (IS_VALLEYVIEW(dev))
+ val = vlv_gpu_freq(dev_priv, dev_priv-rps.min_freq);
+ else
+ val = ((rp_state_cap 0xff) 16) *
GT_FREQUENCY_MULTIPLIER;
} else {
BUG();
}
@@ -486,6 +495,9 @@ static const struct attribute *vlv_attrs[] = {
dev_attr_gt_cur_freq_mhz.attr,
dev_attr_gt_max_freq_mhz.attr,
dev_attr_gt_min_freq_mhz.attr,
+ dev_attr_gt_RP0_freq_mhz.attr,
+ dev_attr_gt_RP1_freq_mhz.attr,
+ dev_attr_gt_RPn_freq_mhz.attr,
dev_attr_vlv_rpe_freq_mhz.attr,
NULL,
};
--
1.9.1
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[Intel-gfx] [PATCH 0/7] Enable RP1/RPn/RP0 sysfs and enable CHV PM interrupt
From: Deepak S deepa...@linux.intel.com Enable RP1/RPn/RP0 sysfs and enable CHV PM interrupt for verifying the freq on VLV and CHV Deepak S (7): drm/i915: Read guaranteed freq for valleyview drm/i915: Add RP0/RP1/RPn render P state thresholds in VLV sysfs drm/i915: keep freq/opcode conversion function more generic drm/i915: populate mem_freq/cz_clock for chv drm/i915: CHV GPU frequency to opcode functions drm/i915/chv: Add basic PM interrupt support for CHV drm/i915: Add RP1 render P state thresholds in CHV drivers/gpu/drm/i915/i915_debugfs.c | 14 +-- drivers/gpu/drm/i915/i915_drv.h | 5 +- drivers/gpu/drm/i915/i915_irq.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 6 ++ drivers/gpu/drm/i915/i915_sysfs.c | 30 +-- drivers/gpu/drm/i915/intel_pm.c | 164 +--- 6 files changed, 189 insertions(+), 32 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/7] drm/i915: populate mem_freq/cz_clock for chv
From: Deepak S deepa...@linux.intel.com
We need mem_freq or cz clock for freq/opcode conversion
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_pm.c | 29 +
3 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bce4654..568b39c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -932,6 +932,7 @@ struct intel_gen6_power_mgmt {
u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
u8 rp1_freq;/* less than RP0 power/freqency */
u8 rp0_freq;/* Non-overclocked max frequency. */
+ u32 cz_freq;
u32 ei_interrupt_count;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 490f031..e533efa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5541,6 +5541,12 @@ enum punit_power_well {
GEN6_PM_RP_DOWN_THRESHOLD | \
GEN6_PM_RP_DOWN_TIMEOUT)
+#define CHV_CZ_CLOCK_FREQ_MODE_200 200
+#define CHV_CZ_CLOCK_FREQ_MODE_267 267
+#define CHV_CZ_CLOCK_FREQ_MODE_320 320
+#define CHV_CZ_CLOCK_FREQ_MODE_333 333
+#define CHV_CZ_CLOCK_FREQ_MODE_400 400
+
#define GEN7_GT_SCRATCH_BASE 0x4F100
#define GEN7_GT_SCRATCH_REG_NUM8
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9dfebab..6c19ce5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5706,6 +5706,35 @@ static void valleyview_init_clock_gating(struct
drm_device *dev)
static void cherryview_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
+ u32 val;
+
+ mutex_lock(dev_priv-rps.hw_lock);
+ val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
+ mutex_unlock(dev_priv-rps.hw_lock);
+ switch ((val 2) 0x7) {
+ case 0:
+ case 1:
+ dev_priv-rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_200;
+ dev_priv-mem_freq = 1600;
+ break;
+ case 2:
+ dev_priv-rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_267;
+ dev_priv-mem_freq = 1600;
+ break;
+ case 3:
+ dev_priv-rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_333;
+ dev_priv-mem_freq = 2000;
+ break;
+ case 4:
+ dev_priv-rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_320;
+ dev_priv-mem_freq = 1600;
+ break;
+ case 5:
+ dev_priv-rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_400;
+ dev_priv-mem_freq = 1600;
+ break;
+ }
+ DRM_DEBUG_DRIVER(DDR speed: %d MHz, dev_priv-mem_freq);
I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
--
1.9.1
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[Intel-gfx] [PATCH 3/7] drm/i915: keep freq/opcode conversion function more generic
From: Deepak S deepa...@linux.intel.com
Since freq/encode conversion formula changes from platform to platform,
create a generic wrapper function and having platform check inside this
help to simpilfy adding newer platform freq/opcode conversion.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 14 +-
drivers/gpu/drm/i915/i915_drv.h | 4 +--
drivers/gpu/drm/i915/i915_sysfs.c | 18 ++---
drivers/gpu/drm/i915/intel_pm.c | 52 +++--
4 files changed, 56 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index b3b56c4..dd7078d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1140,14 +1140,14 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
val = valleyview_rps_max_freq(dev_priv);
seq_printf(m, max GPU freq: %d MHz\n,
- vlv_gpu_freq(dev_priv, val));
+ intel_gpu_freq(dev_priv, val));
val = valleyview_rps_min_freq(dev_priv);
seq_printf(m, min GPU freq: %d MHz\n,
- vlv_gpu_freq(dev_priv, val));
+ intel_gpu_freq(dev_priv, val));
seq_printf(m, current GPU freq: %d MHz\n,
- vlv_gpu_freq(dev_priv, (freq_sts 8) 0xff));
+ intel_gpu_freq(dev_priv, (freq_sts 8) 0xff));
mutex_unlock(dev_priv-rps.hw_lock);
} else {
seq_puts(m, no P-state info available\n);
@@ -3667,7 +3667,7 @@ i915_max_freq_get(void *data, u64 *val)
return ret;
if (IS_VALLEYVIEW(dev))
- *val = vlv_gpu_freq(dev_priv, dev_priv-rps.max_freq_softlimit);
+ *val = intel_gpu_freq(dev_priv,
dev_priv-rps.max_freq_softlimit);
else
*val = dev_priv-rps.max_freq_softlimit *
GT_FREQUENCY_MULTIPLIER;
mutex_unlock(dev_priv-rps.hw_lock);
@@ -3698,7 +3698,7 @@ i915_max_freq_set(void *data, u64 val)
* Turbo will still be enabled, but won't go above the set value.
*/
if (IS_VALLEYVIEW(dev)) {
- val = vlv_freq_opcode(dev_priv, val);
+ val = intel_freq_opcode(dev_priv, val);
hw_max = valleyview_rps_max_freq(dev_priv);
hw_min = valleyview_rps_min_freq(dev_priv);
@@ -3748,7 +3748,7 @@ i915_min_freq_get(void *data, u64 *val)
return ret;
if (IS_VALLEYVIEW(dev))
- *val = vlv_gpu_freq(dev_priv, dev_priv-rps.min_freq_softlimit);
+ *val = intel_gpu_freq(dev_priv,
dev_priv-rps.min_freq_softlimit);
else
*val = dev_priv-rps.min_freq_softlimit *
GT_FREQUENCY_MULTIPLIER;
mutex_unlock(dev_priv-rps.hw_lock);
@@ -3779,7 +3779,7 @@ i915_min_freq_set(void *data, u64 val)
* Turbo will still be enabled, but won't go below the set value.
*/
if (IS_VALLEYVIEW(dev)) {
- val = vlv_freq_opcode(dev_priv, val);
+ val = intel_freq_opcode(dev_priv, val);
hw_max = valleyview_rps_max_freq(dev_priv);
hw_min = valleyview_rps_min_freq(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 90216bb..bce4654 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2749,8 +2749,8 @@ void intel_sbi_write(struct drm_i915_private *dev_priv,
u16 reg, u32 value,
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
-int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
-int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
+int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
+int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
#define FORCEWAKE_RENDER (1 0)
#define FORCEWAKE_MEDIA(1 1)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index b15c8ce..adfc4b9 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -269,7 +269,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
if (IS_VALLEYVIEW(dev_priv-dev)) {
u32 freq;
freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
- ret = vlv_gpu_freq(dev_priv, (freq 8) 0xff);
+ ret = intel_gpu_freq(dev_priv, (freq 8) 0xff);
} else {
ret = dev_priv-rps.cur_freq * GT_FREQUENCY_MULTIPLIER;
}
@@ -288,7 +288,7 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
struct drm_i915_private *dev_priv = dev-dev_private;
return snprintf(buf, PAGE_SIZE, %d\n,
- vlv_gpu_freq
[Intel-gfx] [PATCH 6/7] drm/i915/chv: Add basic PM interrupt support for CHV
From: Deepak S deepa...@linux.intel.com
Enabled PM interrupt programming for CHV. Re-using gen8 code and extending same
for CHV.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 4
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 38e6de1..ae6246c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1403,7 +1403,7 @@ static void gen6_pm_rps_work(struct work_struct *work)
spin_lock_irq(dev_priv-irq_lock);
pm_iir = dev_priv-rps.pm_iir;
dev_priv-rps.pm_iir = 0;
- if (IS_BROADWELL(dev_priv-dev))
+ if (IS_BROADWELL(dev_priv-dev) || IS_CHERRYVIEW(dev_priv-dev))
bdw_enable_pm_irq(dev_priv, dev_priv-pm_rps_events);
else {
/* Make sure not to corrupt PMIMR state used by ringbuffer */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6abd05b..7da3719 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3398,6 +3398,8 @@ static void cherryview_disable_rps(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev-dev_private;
I915_WRITE(GEN6_RC_CONTROL, 0);
+
+ gen8_disable_rps_interrupts(dev);
}
static void valleyview_disable_rps(struct drm_device *dev)
@@ -4115,6 +4117,8 @@ static void cherryview_enable_rps(struct drm_device *dev)
valleyview_set_rps(dev_priv-dev, dev_priv-rps.efficient_freq);
+ gen8_enable_rps_interrupts(dev);
+
gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
}
--
1.9.1
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[Intel-gfx] [PATCH 1/7] drm/i915: Read guaranteed freq for valleyview
From: Deepak S deepa...@linux.intel.com
Reading RP1 for valleyview to help us enable pm_rps i-g-t testcase
execution.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d1af641..b8e7afc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3816,6 +3816,17 @@ int cherryview_rps_min_freq(struct drm_i915_private
*dev_priv)
return rpn;
}
+int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rp1;
+
+ val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
+
+ rp1 = (val FB_GFX_FGUARANTEED_FREQ_FUSE_MASK)
FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
+
+ return rp1;
+}
+
int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
{
u32 val, rp0;
@@ -3958,6 +3969,11 @@ static void valleyview_init_gt_powersave(struct
drm_device *dev)
vlv_gpu_freq(dev_priv, dev_priv-rps.efficient_freq),
dev_priv-rps.efficient_freq);
+ dev_priv-rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
+ DRM_DEBUG_DRIVER(RP1(Guar Freq) GPU freq: %d MHz (%u)\n,
+vlv_gpu_freq(dev_priv, dev_priv-rps.rp1_freq),
+dev_priv-rps.rp1_freq);
+
dev_priv-rps.min_freq = valleyview_rps_min_freq(dev_priv);
DRM_DEBUG_DRIVER(min GPU freq: %d MHz (%u)\n,
vlv_gpu_freq(dev_priv, dev_priv-rps.min_freq),
--
1.9.1
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[Intel-gfx] [PATCH 5/7] drm/i915: CHV GPU frequency to opcode functions
From: Deepak S deepa...@linux.intel.com
Adding chv specific fre/encode conversion.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 68 +++--
1 file changed, 59 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6c19ce5..6abd05b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6975,26 +6975,76 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv,
int val)
return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv-mem_freq) + 0xbd - 6;
}
-int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
+int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
{
- int ret;
+ int div, freq;
- if (!IS_VALLEYVIEW(dev_priv-dev))
+ switch (dev_priv-rps.cz_freq) {
+ case 200:
+ div = 5;
+ break;
+ case 267:
+ div = 6;
+ break;
+ case 320:
+ case 333:
+ case 400:
+ div = 8;
+ break;
+ default:
return -1;
+ }
- ret = vlv_gpu_freq(dev_priv, val);
+ freq = (DIV_ROUND_CLOSEST((dev_priv-rps.cz_freq * val), 2 * div) / 2);
- return ret;
+ return freq;
}
-int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
+int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
{
- int ret;
+ int mul, opcode;
- if (!IS_VALLEYVIEW(dev_priv-dev))
+ switch (dev_priv-rps.cz_freq) {
+ case 200:
+ mul = 5;
+ break;
+ case 267:
+ mul = 6;
+ break;
+ case 320:
+ case 333:
+ case 400:
+ mul = 8;
+ break;
+ default:
return -1;
+ }
+
+ opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv-rps.cz_freq) *
2);
+
+ return opcode;
+}
+
+int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
+{
+ int ret = -1;
+
+ if (IS_CHERRYVIEW(dev_priv-dev))
+ ret = chv_gpu_freq(dev_priv, val);
+ else if (IS_VALLEYVIEW(dev_priv-dev))
+ ret = vlv_gpu_freq(dev_priv, val);
+
+ return ret;
+}
+
+int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
+{
+ int ret = -1;
- ret = vlv_freq_opcode(dev_priv, val);
+ if (IS_CHERRYVIEW(dev_priv-dev))
+ ret = chv_freq_opcode(dev_priv, val);
+ else if (IS_VALLEYVIEW(dev_priv-dev))
+ ret = vlv_freq_opcode(dev_priv, val);
return ret;
}
--
1.9.1
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[Intel-gfx] [PATCH 7/7] drm/i915: Add RP1 render P state thresholds in CHV
From: Deepak S deepa...@linux.intel.com
This is useful for userspace utilities to verify and micromanaging
the increase/decrease frequncy.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7da3719..733505a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3809,6 +3809,16 @@ static int cherryview_rps_rpe_freq(struct
drm_i915_private *dev_priv)
return rpe;
}
+int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rp1;
+
+ val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ rp1 = (val PUNIT_GPU_STATUS_MAX_FREQ_SHIFT)
PUNIT_GPU_STATUS_MAX_FREQ_MASK;
+
+ return rp1;
+}
+
int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
{
u32 val, rpn;
@@ -4010,6 +4020,11 @@ static void cherryview_init_gt_powersave(struct
drm_device *dev)
intel_gpu_freq(dev_priv, dev_priv-rps.efficient_freq),
dev_priv-rps.efficient_freq);
+ dev_priv-rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
+ DRM_DEBUG_DRIVER(RP1(Guar) GPU freq: %d MHz (%u)\n,
+intel_gpu_freq(dev_priv, dev_priv-rps.rp1_freq),
+dev_priv-rps.rp1_freq);
+
dev_priv-rps.min_freq = cherryview_rps_min_freq(dev_priv);
DRM_DEBUG_DRIVER(min GPU freq: %d MHz (%u)\n,
intel_gpu_freq(dev_priv, dev_priv-rps.min_freq),
--
1.9.1
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Re: [Intel-gfx] [PATCH 3/7] drm/i915: keep freq/opcode conversion function more generic
On Wednesday 09 July 2014 05:33 PM, Daniel Vetter wrote:
On Thu, Jul 10, 2014 at 01:16:23PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Since freq/encode conversion formula changes from platform to platform,
create a generic wrapper function and having platform check inside this
help to simpilfy adding newer platform freq/opcode conversion.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 14 +-
drivers/gpu/drm/i915/i915_drv.h | 4 +--
drivers/gpu/drm/i915/i915_sysfs.c | 18 ++---
drivers/gpu/drm/i915/intel_pm.c | 52 +++--
4 files changed, 56 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index b3b56c4..dd7078d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1140,14 +1140,14 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
val = valleyview_rps_max_freq(dev_priv);
seq_printf(m, max GPU freq: %d MHz\n,
- vlv_gpu_freq(dev_priv, val));
+ intel_gpu_freq(dev_priv, val));
intel_ is a bit too generic a prefix for a function which seems to be only
used on byt+chv. I'd just add a if (IS_CHERRYVIEW) ... else /* vlv code */
to both functions and not extract further.
Aside: Since marketing stopped using vlv and switched to byt we're using
vlv for code shared by byt and chv and byt_ for byt-only code. Helps a bit
to keep things appart.
-Daniel
Ok. Will it be Ok to use vlv_gpu_freq and have BYT and CHV check under this
function?
The reason why i made more generic is it will help us to add conversion logic
for future platforms
Thanks
Deepak
val = valleyview_rps_min_freq(dev_priv);
seq_printf(m, min GPU freq: %d MHz\n,
- vlv_gpu_freq(dev_priv, val));
+ intel_gpu_freq(dev_priv, val));
seq_printf(m, current GPU freq: %d MHz\n,
- vlv_gpu_freq(dev_priv, (freq_sts 8) 0xff));
+ intel_gpu_freq(dev_priv, (freq_sts 8) 0xff));
mutex_unlock(dev_priv-rps.hw_lock);
} else {
seq_puts(m, no P-state info available\n);
@@ -3667,7 +3667,7 @@ i915_max_freq_get(void *data, u64 *val)
return ret;
if (IS_VALLEYVIEW(dev))
- *val = vlv_gpu_freq(dev_priv, dev_priv-rps.max_freq_softlimit);
+ *val = intel_gpu_freq(dev_priv,
dev_priv-rps.max_freq_softlimit);
else
*val = dev_priv-rps.max_freq_softlimit *
GT_FREQUENCY_MULTIPLIER;
mutex_unlock(dev_priv-rps.hw_lock);
@@ -3698,7 +3698,7 @@ i915_max_freq_set(void *data, u64 val)
* Turbo will still be enabled, but won't go above the set value.
*/
if (IS_VALLEYVIEW(dev)) {
- val = vlv_freq_opcode(dev_priv, val);
+ val = intel_freq_opcode(dev_priv, val);
hw_max = valleyview_rps_max_freq(dev_priv);
hw_min = valleyview_rps_min_freq(dev_priv);
@@ -3748,7 +3748,7 @@ i915_min_freq_get(void *data, u64 *val)
return ret;
if (IS_VALLEYVIEW(dev))
- *val = vlv_gpu_freq(dev_priv, dev_priv-rps.min_freq_softlimit);
+ *val = intel_gpu_freq(dev_priv,
dev_priv-rps.min_freq_softlimit);
else
*val = dev_priv-rps.min_freq_softlimit *
GT_FREQUENCY_MULTIPLIER;
mutex_unlock(dev_priv-rps.hw_lock);
@@ -3779,7 +3779,7 @@ i915_min_freq_set(void *data, u64 val)
* Turbo will still be enabled, but won't go below the set value.
*/
if (IS_VALLEYVIEW(dev)) {
- val = vlv_freq_opcode(dev_priv, val);
+ val = intel_freq_opcode(dev_priv, val);
hw_max = valleyview_rps_max_freq(dev_priv);
hw_min = valleyview_rps_min_freq(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 90216bb..bce4654 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2749,8 +2749,8 @@ void intel_sbi_write(struct drm_i915_private *dev_priv,
u16 reg, u32 value,
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
-int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
-int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
+int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
+int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
#define FORCEWAKE_RENDER (1 0)
#define FORCEWAKE_MEDIA (1 1)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index b15c8ce..adfc4b9 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
Re: [Intel-gfx] [PATCH] drm/i915: Restrict GPU boost to the RCS engine
On Monday 07 July 2014 02:35 PM, Daniel Vetter wrote:
On Tue, Jun 24, 2014 at 05:22:17PM +0530, Deepak S wrote:
Hi Chris/Daniel,
The patch is helping in some of the side-effects due to gpu boost. I
still need to get more data. I will keep the thread updated.
Ping. Might as well review it, too.
-Daniel
Thanks
Deepak
On Thursday 12 June 2014 03:02 PM, Daniel Vetter wrote:
Adding Deepak for testing, this hopefully alleviates the bad
side-effects of the gpu booster he's seeing.
-Daniel
On Thu, Jun 12, 2014 at 11:28 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
Make the assumption that media workloads are not as latency sensitive
for __wait_seqno, and that upclocking the GPU does not affect the BLT
engine. Under that assumption, we only wait to forcibly upclock the GPU
when we are stalling for results from the render pipeline.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5951618a6b08..242b595a0403 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1409,7 +1409,7 @@ static int __wait_seqno(struct intel_engine_cs *ring, u32
seqno,
timeout_expire = timeout ? jiffies +
timespec_to_jiffies_timeout(timeout) : 0;
- if (INTEL_INFO(dev)-gen = 6 can_wait_boost(file_priv)) {
+ if (INTEL_INFO(dev)-gen = 6 ring-id == RCS
can_wait_boost(file_priv)) {
gen6_rps_boost(dev_priv);
if (file_priv)
mod_delayed_work(dev_priv-wq,
--
2.0.0
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Sorry for the delayed response. I am fine with this patch. This is helping us
in some of the workload senarios.
Just one concern here. Since we are avoiding boost for Media related workload,
we might end up running GPU at RPn. Which might impact media workload.
I think we need another patch to run GPU at RPe if the boost is not enabled for
media.
Reviewed-by: Deepak Sdeepa...@linux.intel.com
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Re: [Intel-gfx] [PATCH v2 1/3] drm/i915: gmch: factor out intel_set_memory_cxsr
On Friday 13 June 2014 05:24 PM, Imre Deak wrote:
This functionality will be also needed by an upcoming patch, so factor
it out. As a bonus this also makes things a bit more uniform across
platforms. Note that this also changes the register read-modify-write
to a simple write during disabling. This is what we do during enabling
anyway and according to the spec all the relevant bits are reserved-MBZ
or reserved with a 0 default value.
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 75 -
2 files changed, 39 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f36d9eb..211a173 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2590,6 +2590,8 @@ extern void gen6_set_rps(struct drm_device *dev, u8 val);
extern void valleyview_set_rps(struct drm_device *dev, u8 val);
extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
+extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
+ bool enable);
extern void intel_detect_pch(struct drm_device *dev);
extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
extern int intel_enable_rc6(const struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0b088fe..e55622e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -789,12 +789,33 @@ static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop,
return NULL;
}
-static void pineview_disable_cxsr(struct drm_device *dev)
+void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
{
- struct drm_i915_private *dev_priv = dev-dev_private;
+ struct drm_device *dev = dev_priv-dev;
+ u32 val;
- /* deactivate cxsr */
- I915_WRITE(DSPFW3, I915_READ(DSPFW3) ~PINEVIEW_SELF_REFRESH_EN);
+ if (IS_VALLEYVIEW(dev)) {
+ I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
+ } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
+ I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
+ } else if (IS_PINEVIEW(dev)) {
+ val = I915_READ(DSPFW3) ~PINEVIEW_SELF_REFRESH_EN;
+ val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
+ I915_WRITE(DSPFW3, val);
+ } else if (IS_I945G(dev) || IS_I945GM(dev)) {
+ val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
+ _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
+ I915_WRITE(FW_BLC_SELF, val);
+ } else if (IS_I915GM(dev)) {
+ val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
+ _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
+ I915_WRITE(INSTPM, val);
+ } else {
+ return;
+ }
+
+ DRM_DEBUG_KMS(memory self-refresh is %s\n,
+ enable ? enabled : disabled);
}
/*
@@ -1033,7 +1054,7 @@ static void pineview_update_wm(struct drm_crtc
*unused_crtc)
dev_priv-fsb_freq,
dev_priv-mem_freq);
if (!latency) {
DRM_DEBUG_KMS(Unknown FSB/MEM found, disable CxSR\n);
- pineview_disable_cxsr(dev);
+ intel_set_memory_cxsr(dev_priv, false);
return;
}
@@ -1085,12 +1106,7 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc)
DRM_DEBUG_KMS(DSPFW3 register is %x\n, reg);
/* activate cxsr */
- I915_WRITE(DSPFW3,
- I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
- DRM_DEBUG_KMS(Self-refresh is enabled\n);
- } else {
- pineview_disable_cxsr(dev);
- DRM_DEBUG_KMS(Self-refresh is disabled\n);
+ intel_set_memory_cxsr(dev_priv, true);
I think we need to pass false here to disable cxsr right?
Apart for this everything else looks good.
Reviewed-by: Deepak Sdeepa...@linux.intel.com
}
}
@@ -1342,10 +1358,9 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
valleyview_wm_info,
valleyview_cursor_wm_info,
ignore_plane_sr, cursor_sr)) {
- I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
+ intel_set_memory_cxsr(dev_priv, true);
} else {
- I915_WRITE(FW_BLC_SELF_VLV,
- I915_READ(FW_BLC_SELF_VLV) ~FW_CSPWRDWNEN);
+ intel_set_memory_cxsr(dev_priv, false);
plane_sr = cursor_sr = 0;
}
@@ -1394,10 +1409,9 @@ static void g4x_update_wm(struct drm_crtc *crtc)
g4x_wm_info,
Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: gmch: set SR WMs to valid values before enabling them
On Friday 13 June 2014 05:24 PM, Imre Deak wrote:
Atm it's possible that we enable the memory self-refresh mode before the
watermark levels used by this mode are programmed with valid values. So
move the enabling after we programmed the WM levels.
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e55622e..c9ee1aa 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1332,6 +1332,7 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
int plane_sr, cursor_sr;
int ignore_plane_sr, ignore_cursor_sr;
unsigned int enabled = 0;
+ bool cxsr_enabled;
vlv_update_drain_latency(dev);
@@ -1358,8 +1359,9 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
valleyview_wm_info,
valleyview_cursor_wm_info,
ignore_plane_sr, cursor_sr)) {
- intel_set_memory_cxsr(dev_priv, true);
+ cxsr_enabled = true;
} else {
+ cxsr_enabled = false;
intel_set_memory_cxsr(dev_priv, false);
plane_sr = cursor_sr = 0;
}
@@ -1380,6 +1382,9 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
I915_WRITE(DSPFW3,
(I915_READ(DSPFW3) ~DSPFW_CURSOR_SR_MASK) |
(cursor_sr DSPFW_CURSOR_SR_SHIFT));
+
+ if (cxsr_enabled)
+ intel_set_memory_cxsr(dev_priv, true);
}
static void g4x_update_wm(struct drm_crtc *crtc)
@@ -1390,6 +1395,7 @@ static void g4x_update_wm(struct drm_crtc *crtc)
int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
int plane_sr, cursor_sr;
unsigned int enabled = 0;
+ bool cxsr_enabled;
if (g4x_compute_wm0(dev, PIPE_A,
g4x_wm_info, latency_ns,
@@ -1409,8 +1415,9 @@ static void g4x_update_wm(struct drm_crtc *crtc)
g4x_wm_info,
g4x_cursor_wm_info,
plane_sr, cursor_sr)) {
- intel_set_memory_cxsr(dev_priv, true);
+ cxsr_enabled = true;
} else {
+ cxsr_enabled = false;
intel_set_memory_cxsr(dev_priv, false);
plane_sr = cursor_sr = 0;
}
@@ -1432,6 +1439,9 @@ static void g4x_update_wm(struct drm_crtc *crtc)
I915_WRITE(DSPFW3,
(I915_READ(DSPFW3) ~(DSPFW_HPLL_SR_EN |
DSPFW_CURSOR_SR_MASK)) |
(cursor_sr DSPFW_CURSOR_SR_SHIFT));
+
+ if (cxsr_enabled)
+ intel_set_memory_cxsr(dev_priv, true);
}
static void i965_update_wm(struct drm_crtc *unused_crtc)
@@ -1441,6 +1451,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
struct drm_crtc *crtc;
int srwm = 1;
int cursor_sr = 16;
+ bool cxsr_enabled;
/* Calc sr entries for one plane configs */
crtc = single_enabled_crtc(dev);
@@ -1482,8 +1493,9 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
DRM_DEBUG_KMS(self-refresh watermark: display plane %d
cursor %d\n, srwm, cursor_sr);
- intel_set_memory_cxsr(dev_priv, true);
+ cxsr_enabled = true;
} else {
+ cxsr_enabled = false;
/* Turn off self refresh if both pipes are enabled */
intel_set_memory_cxsr(dev_priv, false);
}
@@ -1497,6 +1509,9 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
I915_WRITE(DSPFW2, (8 8) | (8 0));
/* update cursor SR watermark */
I915_WRITE(DSPFW3, (cursor_sr DSPFW_CURSOR_SR_SHIFT));
+
+ if (cxsr_enabled)
+ intel_set_memory_cxsr(dev_priv, true);
}
static void i9xx_update_wm(struct drm_crtc *unused_crtc)
Reviewed-by: Deepak Sdeepa...@linux.intel.com
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Re: [Intel-gfx] [PATCH v2 3/3] drm/i915: gmch: fix stuck primary plane due to memory self-refresh mode
On Friday 13 June 2014 05:24 PM, Imre Deak wrote: Blanking/unblanking the console in a loop on an Asus T100 sometimes leaves the console blank. After some digging I found that applying commit 61bc95c1fbbb6a08b55bbe161fdf1ea5493fc595 Author: Egbert Eich e...@suse.com Date: Mon Mar 4 09:24:38 2013 -0500 DRM/i915: On G45 enable cursor plane briefly after enabling the display plane. fixed VLV too. In my case the problem seemed to happen already during the previous crtc disabling and went away if I disabled self-refresh mode before disabling the primary plane. The root cause for this is that updates from the shadow to live plane control register are blocked at vblank time if the memory self-refresh mode (aka max-fifo mode on VLV) is active at that moment. The controller checks at frame start time if the CPU is in C0 and the self-refresh mode enable bit is set and if so activates self-reresh mode, otherwise deactivates it. So to make sure that the plane truly gets disabled before pipe-off we have to: 1. disable memory self-refresh mode 2. disable plane 3. wait for vblank 4. disable pipe 5. wait for pipe-off v2: - add explanation for the root cause from HW team (Cesar Mancini et al) - remove note about the CPU C7S state, in my latest tests disabling it alone didn't make a difference - add vblank between disabling plane and pipe (Ville) - apply the same workaround for all gmch platforms (Ville) Signed-off-by: Imre Deak imre.d...@intel.com --- drivers/gpu/drm/i915/intel_display.c | 15 +-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b9251c8..5eb8afe 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4799,6 +4799,16 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc) if (IS_GEN2(dev)) intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); + /* +* Vblank time updates from the shadow to live plane control register +* are blocked if the memory self-refresh mode is active at that +* moment. So to make sure the plane gets truly disabled, disable +* first the self-refresh mode. The self-refresh enable bit in turn +* will be checked/applied by the HW only at the next frame start +* event which is after the vblank start event, so we need to have a +* wait-for-vblank between disabling the plane and the pipe. +*/ + intel_set_memory_cxsr(dev_priv, false); intel_crtc_disable_planes(crtc); for_each_encoder_on_crtc(dev, crtc, encoder) @@ -4807,9 +4817,10 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc) /* * On gen2 planes are double buffered but the pipe isn't, so we must * wait for planes to fully turn off before disabling the pipe. +* We also need to wait on all gmch platforms because of the +* self-refresh mode constraint explained above. */ - if (IS_GEN2(dev)) - intel_wait_for_vblank(dev, pipe); + intel_wait_for_vblank(dev, pipe); intel_disable_pipe(dev_priv, pipe); Reviewed-by: Deepak Sdeepa...@linux.intel.com ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/chv: Drop WaGsvBringDownFreqInRc6
From: Deepak S deepa...@linux.intel.com
Drop WaGsvBringDownFreq on CHV.
When in RC6 requesting the min freq should be fine to bring the
voltage down.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6b6cfd4..4875f745 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3253,7 +3253,9 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
mutex_lock(dev_priv-rps.hw_lock);
if (dev_priv-rps.enabled) {
- if (IS_VALLEYVIEW(dev))
+ if (IS_CHERRYVIEW(dev))
+ valleyview_set_rps(dev_priv-dev,
dev_priv-rps.min_freq_softlimit);
+ else if (IS_VALLEYVIEW(dev))
vlv_set_rps_idle(dev_priv);
else
gen6_set_rps(dev_priv-dev,
dev_priv-rps.min_freq_softlimit);
--
1.9.1
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[Intel-gfx] [PATCH v2] drm/i915: Drop WA to fix Voltage not getting dropped to Vmin when Gfx is power gated for latest VLV revision
From: Deepak S deepa...@linux.intel.com
Workaround fixed in Latest VLV revision. Forcing Gfx clk up not needed, and
Requesting the
min freq should bring bring the voltage Vnn.
v2: Drop WA for Latest VLV revision (Ville)
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a90fdbd..6b6cfd4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3212,6 +3212,14 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
*/
static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
{
+ struct drm_device *dev = dev_priv-dev;
+
+ /* Latest VLV doesn't need Vnn WA*/
+ if (dev-pdev-revision = 0xd) {
+ valleyview_set_rps(dev_priv-dev,
dev_priv-rps.min_freq_softlimit);
+ return;
+ }
+
/*
* When we are idle. Drop to min voltage state.
*/
--
1.9.1
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Re: [Intel-gfx] [PATCH] drm/i915: Restrict GPU boost to the RCS engine
Hi Chris/Daniel,
The patch is helping in some of the side-effects due to gpu boost. I still
need to get more data. I will keep the thread updated.
Thanks
Deepak
On Thursday 12 June 2014 03:02 PM, Daniel Vetter wrote:
Adding Deepak for testing, this hopefully alleviates the bad
side-effects of the gpu booster he's seeing.
-Daniel
On Thu, Jun 12, 2014 at 11:28 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
Make the assumption that media workloads are not as latency sensitive
for __wait_seqno, and that upclocking the GPU does not affect the BLT
engine. Under that assumption, we only wait to forcibly upclock the GPU
when we are stalling for results from the render pipeline.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5951618a6b08..242b595a0403 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1409,7 +1409,7 @@ static int __wait_seqno(struct intel_engine_cs *ring, u32
seqno,
timeout_expire = timeout ? jiffies +
timespec_to_jiffies_timeout(timeout) : 0;
- if (INTEL_INFO(dev)-gen = 6 can_wait_boost(file_priv)) {
+ if (INTEL_INFO(dev)-gen = 6 ring-id == RCS
can_wait_boost(file_priv)) {
gen6_rps_boost(dev_priv);
if (file_priv)
mod_delayed_work(dev_priv-wq,
--
2.0.0
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[Intel-gfx] [PATCH v3] drm/i915: Force GPU Freq to lowest while suspending.
From: Deepak S deepa...@linux.intel.com We might be leaving the GPU Frequency (and thus vnn) high during the suspend. Force gt to move to lowest freq while suspending. v2: Fixed typo in commit message (Deepak) v3: Force gt to lowest freq in suspend_gt_powersave (Daniel) Signed-off-by: Deepak S deepa...@linux.intel.com --- drivers/gpu/drm/i915/intel_pm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2043c4b..6bbb90b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4881,6 +4881,9 @@ void intel_suspend_gt_powersave(struct drm_device *dev) /* Interrupts should be disabled already to avoid re-arming. */ WARN_ON(dev-irq_enabled); + /* Force GPU to min freq during suspend */ + gen6_rps_idle(dev_priv); + flush_delayed_work(dev_priv-rps.delayed_resume_work); cancel_work_sync(dev_priv-rps.work); -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3] drm/i915: Force GPU Freq to lowest while suspending.
On Thursday 19 June 2014 06:04 PM, Daniel Vetter wrote: On Fri, Jun 20, 2014 at 1:59 PM, deepa...@linux.intel.com wrote: diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2043c4b..6bbb90b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4881,6 +4881,9 @@ void intel_suspend_gt_powersave(struct drm_device *dev) /* Interrupts should be disabled already to avoid re-arming. */ WARN_ON(dev-irq_enabled); + /* Force GPU to min freq during suspend */ + gen6_rps_idle(dev_priv); + Shouldn't this be _after_ we've cancelled the rps works? Otherwise the work item might sneak in and undo the idling between the idle and work cancelling. -Daniel My mistake sending updated patch, -Deepak ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4] drm/i915: Force GPU Freq to lowest while suspending.
From: Deepak S deepa...@linux.intel.com We might be leaving the GPU Frequency (and thus vnn) high during the suspend. Force gt to move to lowest freq while suspending. v2: Fixed typo in commit message (Deepak) v3: Force gt to lowest freq in suspend_gt_powersave (Daniel) v4: Add GPU min freq set _after_ we've cancelled the rps works (Daniel) Signed-off-by: Deepak S deepa...@linux.intel.com --- drivers/gpu/drm/i915/intel_pm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2043c4b..0543407 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4884,6 +4884,9 @@ void intel_suspend_gt_powersave(struct drm_device *dev) flush_delayed_work(dev_priv-rps.delayed_resume_work); cancel_work_sync(dev_priv-rps.work); + + /* Force GPU to min freq during suspend */ + gen6_rps_idle(dev_priv); } void intel_disable_gt_powersave(struct drm_device *dev) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Restrict GPU boost to the RCS engine
On Thursday 12 June 2014 03:02 PM, Daniel Vetter wrote:
Adding Deepak for testing, this hopefully alleviates the bad
side-effects of the gpu booster he's seeing.
-Daniel
On Thu, Jun 12, 2014 at 11:28 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
Make the assumption that media workloads are not as latency sensitive
for __wait_seqno, and that upclocking the GPU does not affect the BLT
engine. Under that assumption, we only wait to forcibly upclock the GPU
when we are stalling for results from the render pipeline.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5951618a6b08..242b595a0403 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1409,7 +1409,7 @@ static int __wait_seqno(struct intel_engine_cs *ring, u32
seqno,
timeout_expire = timeout ? jiffies +
timespec_to_jiffies_timeout(timeout) : 0;
- if (INTEL_INFO(dev)-gen = 6 can_wait_boost(file_priv)) {
+ if (INTEL_INFO(dev)-gen = 6 ring-id == RCS
can_wait_boost(file_priv)) {
gen6_rps_boost(dev_priv);
if (file_priv)
mod_delayed_work(dev_priv-wq,
--
2.0.0
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Thanks Daniel. Apologies for delayed response.
Yup the changes make sense. I will test and share the results.
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[Intel-gfx] [PATCH] drm/i915: Bring GPU Freq to min while suspending.
From: Deepak S deepa...@linux.intel.com We might be leaving the PGU Frequency (and thus vnn) high during the suspend. Flusing the delayed work queue should take care of this. Signed-off-by: Deepak S deepa...@linux.intel.com --- drivers/gpu/drm/i915/i915_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 7f643db..8d5ae82 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4541,7 +4541,7 @@ i915_gem_suspend(struct drm_device *dev) del_timer_sync(dev_priv-gpu_error.hangcheck_timer); cancel_delayed_work_sync(dev_priv-mm.retire_work); - cancel_delayed_work_sync(dev_priv-mm.idle_work); + flush_delayed_work(dev_priv-mm.idle_work); return 0; -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: Bring GPU Freq to min while suspending.
From: Deepak S deepa...@linux.intel.com We might be leaving the GPU Frequency (and thus vnn) high during the suspend. Flush the delayed work queue should take care of this. v2: Fixed typo in commit message (Deepak) Signed-off-by: Deepak S deepa...@linux.intel.com --- drivers/gpu/drm/i915/i915_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 7f643db..8d5ae82 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4541,7 +4541,7 @@ i915_gem_suspend(struct drm_device *dev) del_timer_sync(dev_priv-gpu_error.hangcheck_timer); cancel_delayed_work_sync(dev_priv-mm.retire_work); - cancel_delayed_work_sync(dev_priv-mm.idle_work); + flush_delayed_work(dev_priv-mm.idle_work); return 0; -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Bring GPU Freq to min while suspending.
On Wednesday 18 June 2014 03:47 AM, Daniel Vetter wrote: On Wed, Jun 18, 2014 at 05:30:53AM +0530, deepa...@linux.intel.com wrote: From: Deepak S deepa...@linux.intel.com We might be leaving the GPU Frequency (and thus vnn) high during the suspend. Flush the delayed work queue should take care of this. v2: Fixed typo in commit message (Deepak) Signed-off-by: Deepak S deepa...@linux.intel.com --- drivers/gpu/drm/i915/i915_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 7f643db..8d5ae82 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4541,7 +4541,7 @@ i915_gem_suspend(struct drm_device *dev) del_timer_sync(dev_priv-gpu_error.hangcheck_timer); cancel_delayed_work_sync(dev_priv-mm.retire_work); - cancel_delayed_work_sync(dev_priv-mm.idle_work); + flush_delayed_work(dev_priv-mm.idle_work); Shouldn't we do that in suspend_gt_powersave instead? Also if we cancel the retire work the idle work won't necessarily get armed and we might miss the window. Just forcing the gt to the lowest freq in suspend_gt_powersave should be more reliable. -Daniel Since we a calling suspend_gt_powersave after i915_gem_suspend, i added the flush in suspend. Yes i agree forcing the gt freq us more reliable ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Drop WA to fix Voltage not getting dropped to Vmin when Gfx is power gated.
On Friday 13 June 2014 07:24 PM, Daniel Vetter wrote:
On Fri, Jun 13, 2014 at 05:56:41PM +0530, Deepak S wrote:
On Friday 13 June 2014 05:27 PM, Ville Syrjälä wrote:
On Fri, Jun 13, 2014 at 02:33:44PM +0300, Ville Syrjälä wrote:
On Fri, Jun 13, 2014 at 03:46:14PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Workaround fixed in BYT. Forcing Gfx clk up not needed, and Requesting the
min freq should bring bring the voltage Vnn.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 40 +---
1 file changed, 1 insertion(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0b088fe..9aee28b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3198,44 +3198,6 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
trace_intel_gpu_freq_change(val * 50);
}
-/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
- *
- * * If Gfx is Idle, then
- * 1. Mask Turbo interrupts
- * 2. Bring up Gfx clock
- * 3. Change the freq to Rpn and wait till P-Unit updates freq
- * 4. Clear the Force GFX CLK ON bit so that Gfx can down
- * 5. Unmask Turbo interrupts
-*/
-static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
-{
- /*
-* When we are idle. Drop to min voltage state.
-*/
-
- if (dev_priv-rps.cur_freq = dev_priv-rps.min_freq_softlimit)
- return;
-
- /* Mask turbo interrupt so that they will not come in between */
- I915_WRITE(GEN6_PMINTRMSK, 0x);
-
- vlv_force_gfx_clock(dev_priv, true);
-
- dev_priv-rps.cur_freq = dev_priv-rps.min_freq_softlimit;
-
- vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
- dev_priv-rps.min_freq_softlimit);
-
- if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
-GENFREQSTATUS) == 0, 5))
- DRM_ERROR(timed out waiting for Punit\n);
-
- vlv_force_gfx_clock(dev_priv, false);
-
- I915_WRITE(GEN6_PMINTRMSK,
- gen6_rps_pm_mask(dev_priv, dev_priv-rps.cur_freq));
-}
-
void gen6_rps_idle(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = dev_priv-dev;
@@ -3243,7 +3205,7 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
mutex_lock(dev_priv-rps.hw_lock);
if (dev_priv-rps.enabled) {
if (IS_VALLEYVIEW(dev))
- vlv_set_rps_idle(dev_priv);
+ valleyview_set_rps(dev_priv-dev,
dev_priv-rps.min_freq_softlimit);
This should take care of https://bugs.freedesktop.org/show_bug.cgi?id=75244
I don't know when the hardware got fixed so I'm hesitant to r-b it, but
at least my C0 works fine without this stuff, so:
Acked-by: Ville Syrjälä ville.syrj...@linux.intel.com
However to avoid future mishaps I think we should have some kind of a
comment before the valleyview_set_rps() call to let the reader know that
we really need this on VLV to drop the voltage.
hmm, Yes we might need this for other stepping. I will add a comment
Please don't put the stepping info in the comment or commit message
though, that freaks out people ;-) Usually we go with pre-production or
early revisions or something non-specific.
Ok Sure :)
Thanks for the review
Also it now occurs to me that we might be leaving the GPU frequency (and
thus Vnn) high during a system suspend. I think we need an explicit
rps_idle() call in the suspend path somewhere. Runtime suspend should be
fine already since it depends on intel_mark_idle() getting called before
the last rpm reference is dropped.
Maybe this is all we need?
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3768199..fabd852 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4530,7 +4530,7 @@ i915_gem_suspend(struct drm_device *dev)
del_timer_sync(dev_priv-gpu_error.hangcheck_timer);
cancel_delayed_work_sync(dev_priv-mm.retire_work);
- cancel_delayed_work_sync(dev_priv-mm.idle_work);
+ flush_delayed_work(dev_priv-mm.idle_work);
return 0;
Yes, while suspending we need move GPU to min_freq. flush_delayed_work
should be fine. Let me create a patch for this.
Since this is gt powersave related can you please also check whether we
shouldn't move this to the intel_suspend_gt_powersave function Jesse
recently added to -nightly?
Thanks, Daniel
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[Intel-gfx] [PATCH] drm/i915: Drop WA to fix Voltage not getting dropped to Vmin when Gfx is power gated.
From: Deepak S deepa...@linux.intel.com
Workaround fixed in BYT. Forcing Gfx clk up not needed, and Requesting the
min freq should bring bring the voltage Vnn.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 40 +---
1 file changed, 1 insertion(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0b088fe..9aee28b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3198,44 +3198,6 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
trace_intel_gpu_freq_change(val * 50);
}
-/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
- *
- * * If Gfx is Idle, then
- * 1. Mask Turbo interrupts
- * 2. Bring up Gfx clock
- * 3. Change the freq to Rpn and wait till P-Unit updates freq
- * 4. Clear the Force GFX CLK ON bit so that Gfx can down
- * 5. Unmask Turbo interrupts
-*/
-static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
-{
- /*
-* When we are idle. Drop to min voltage state.
-*/
-
- if (dev_priv-rps.cur_freq = dev_priv-rps.min_freq_softlimit)
- return;
-
- /* Mask turbo interrupt so that they will not come in between */
- I915_WRITE(GEN6_PMINTRMSK, 0x);
-
- vlv_force_gfx_clock(dev_priv, true);
-
- dev_priv-rps.cur_freq = dev_priv-rps.min_freq_softlimit;
-
- vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
- dev_priv-rps.min_freq_softlimit);
-
- if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
-GENFREQSTATUS) == 0, 5))
- DRM_ERROR(timed out waiting for Punit\n);
-
- vlv_force_gfx_clock(dev_priv, false);
-
- I915_WRITE(GEN6_PMINTRMSK,
- gen6_rps_pm_mask(dev_priv, dev_priv-rps.cur_freq));
-}
-
void gen6_rps_idle(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = dev_priv-dev;
@@ -3243,7 +3205,7 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
mutex_lock(dev_priv-rps.hw_lock);
if (dev_priv-rps.enabled) {
if (IS_VALLEYVIEW(dev))
- vlv_set_rps_idle(dev_priv);
+ valleyview_set_rps(dev_priv-dev,
dev_priv-rps.min_freq_softlimit);
else
gen6_set_rps(dev_priv-dev,
dev_priv-rps.min_freq_softlimit);
dev_priv-rps.last_adj = 0;
--
1.9.1
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Re: [Intel-gfx] [PATCH] drm/i915: Drop WA to fix Voltage not getting dropped to Vmin when Gfx is power gated.
On Friday 13 June 2014 05:27 PM, Ville Syrjälä wrote:
On Fri, Jun 13, 2014 at 02:33:44PM +0300, Ville Syrjälä wrote:
On Fri, Jun 13, 2014 at 03:46:14PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Workaround fixed in BYT. Forcing Gfx clk up not needed, and Requesting the
min freq should bring bring the voltage Vnn.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 40 +---
1 file changed, 1 insertion(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0b088fe..9aee28b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3198,44 +3198,6 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
trace_intel_gpu_freq_change(val * 50);
}
-/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
- *
- * * If Gfx is Idle, then
- * 1. Mask Turbo interrupts
- * 2. Bring up Gfx clock
- * 3. Change the freq to Rpn and wait till P-Unit updates freq
- * 4. Clear the Force GFX CLK ON bit so that Gfx can down
- * 5. Unmask Turbo interrupts
-*/
-static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
-{
- /*
-* When we are idle. Drop to min voltage state.
-*/
-
- if (dev_priv-rps.cur_freq = dev_priv-rps.min_freq_softlimit)
- return;
-
- /* Mask turbo interrupt so that they will not come in between */
- I915_WRITE(GEN6_PMINTRMSK, 0x);
-
- vlv_force_gfx_clock(dev_priv, true);
-
- dev_priv-rps.cur_freq = dev_priv-rps.min_freq_softlimit;
-
- vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
- dev_priv-rps.min_freq_softlimit);
-
- if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
-GENFREQSTATUS) == 0, 5))
- DRM_ERROR(timed out waiting for Punit\n);
-
- vlv_force_gfx_clock(dev_priv, false);
-
- I915_WRITE(GEN6_PMINTRMSK,
- gen6_rps_pm_mask(dev_priv, dev_priv-rps.cur_freq));
-}
-
void gen6_rps_idle(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = dev_priv-dev;
@@ -3243,7 +3205,7 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
mutex_lock(dev_priv-rps.hw_lock);
if (dev_priv-rps.enabled) {
if (IS_VALLEYVIEW(dev))
- vlv_set_rps_idle(dev_priv);
+ valleyview_set_rps(dev_priv-dev,
dev_priv-rps.min_freq_softlimit);
This should take care of https://bugs.freedesktop.org/show_bug.cgi?id=75244
I don't know when the hardware got fixed so I'm hesitant to r-b it, but
at least my C0 works fine without this stuff, so:
Acked-by: Ville Syrjälä ville.syrj...@linux.intel.com
However to avoid future mishaps I think we should have some kind of a
comment before the valleyview_set_rps() call to let the reader know that
we really need this on VLV to drop the voltage.
hmm, Yes we might need this for other stepping. I will add a comment
Thanks for the review
Also it now occurs to me that we might be leaving the GPU frequency (and
thus Vnn) high during a system suspend. I think we need an explicit
rps_idle() call in the suspend path somewhere. Runtime suspend should be
fine already since it depends on intel_mark_idle() getting called before
the last rpm reference is dropped.
Maybe this is all we need?
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3768199..fabd852 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4530,7 +4530,7 @@ i915_gem_suspend(struct drm_device *dev)
del_timer_sync(dev_priv-gpu_error.hangcheck_timer);
cancel_delayed_work_sync(dev_priv-mm.retire_work);
- cancel_delayed_work_sync(dev_priv-mm.idle_work);
+ flush_delayed_work(dev_priv-mm.idle_work);
return 0;
Yes, while suspending we need move GPU to min_freq. flush_delayed_work should
be fine. Let me create a patch for this.
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[Intel-gfx] [PATCH v6] drm/i915/chv: Enable RPS (Turbo) for Cherryview
From: Deepak S deepa...@linux.intel.com
v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
v3: Mass rename of the dev_priv-rps variables in upstream.
v4: Rebase against latest code. (Deepak)
v5: Rebase against latest nightly code. (Deepak)
v6: Rename the variables to match the spec (Mika)
Signed-off-by: Deepak S deepa...@linux.intel.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_reg.h | 11 +
drivers/gpu/drm/i915/intel_pm.c | 95 -
2 files changed, 105 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1f36a5..7e8968b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -529,6 +529,16 @@ enum punit_power_well {
#define PUNIT_FUSE_BUS20xf6 /* bits 47:40 */
#define PUNIT_FUSE_BUS10xf5 /* bits 55:48 */
+#define CHV_IOSF_PUNIT_FB_GFX_FREQ_REG 0xdb
+#define CHV_FB_GFX_MAX_FREQ_SHIFT 16
+#define CHV_FB_GFX_MAX_FREQ_MASK 0xff
+#define CHV_FB_GFX_MIN_FREQ_SHIFT 8
+#define CHV_FB_GFX_MIN_FREQ_MASK 0xff
+
+#define CHV_IOSF_PUNIT_FB_GFX_RPE_REG 0xdf
+#define CHV_FB_GFX_RPE_FREQ_SHIFT 8
+#define CHV_FB_GFX_RPE_FREQ_MASK 0xff
+
#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
#define FB_GFX_MAX_FREQ_FUSE_MASK0x07f8
@@ -933,6 +943,7 @@ enum punit_power_well {
#define SANDYBRIDGE_FENCE_PITCH_SHIFT32
#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
+
/* control register for cpu gtt access */
#define TILECTL0x101000
#define TILECTL_SWZCTL (1 0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1816c52..d4a84b3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3731,6 +3731,38 @@ void gen6_update_ring_freq(struct drm_device *dev)
mutex_unlock(dev_priv-rps.hw_lock);
}
+int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rp0;
+
+ val = vlv_punit_read(dev_priv, CHV_IOSF_PUNIT_FB_GFX_FREQ_REG);
+
+ rp0 = (val CHV_FB_GFX_MAX_FREQ_SHIFT)
+ CHV_FB_GFX_MAX_FREQ_MASK;
+
+ return rp0;
+}
+
+static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rpe;
+
+ val = vlv_punit_read(dev_priv, CHV_IOSF_PUNIT_FB_GFX_RPE_REG);
+ rpe = (val CHV_FB_GFX_RPE_FREQ_SHIFT) CHV_FB_GFX_RPE_FREQ_MASK;
+
+ return rpe;
+}
+
+int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rpn;
+
+ val = vlv_punit_read(dev_priv, CHV_IOSF_PUNIT_FB_GFX_FREQ_REG);
+ rpn = (val CHV_FB_GFX_MIN_FREQ_SHIFT) CHV_FB_GFX_MIN_FREQ_MASK;
+
+ return rpn;
+}
+
int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
{
u32 val, rp0;
@@ -3890,7 +3922,36 @@ static void valleyview_init_gt_powersave(struct
drm_device *dev)
static void cherryview_init_gt_powersave(struct drm_device *dev)
{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
cherryview_setup_pctx(dev);
+
+ mutex_lock(dev_priv-rps.hw_lock);
+
+ dev_priv-rps.max_freq = cherryview_rps_max_freq(dev_priv);
+ dev_priv-rps.rp0_freq = dev_priv-rps.max_freq;
+ DRM_DEBUG_DRIVER(max GPU freq: %d MHz (%u)\n,
+vlv_gpu_freq(dev_priv, dev_priv-rps.max_freq),
+dev_priv-rps.max_freq);
+
+ dev_priv-rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
+ DRM_DEBUG_DRIVER(RPe GPU freq: %d MHz (%u)\n,
+vlv_gpu_freq(dev_priv, dev_priv-rps.efficient_freq),
+dev_priv-rps.efficient_freq);
+
+ dev_priv-rps.min_freq = cherryview_rps_min_freq(dev_priv);
+ DRM_DEBUG_DRIVER(min GPU freq: %d MHz (%u)\n,
+vlv_gpu_freq(dev_priv, dev_priv-rps.min_freq),
+dev_priv-rps.min_freq);
+
+ /* Preserve min/max settings in case of re-init */
+ if (dev_priv-rps.max_freq_softlimit == 0)
+ dev_priv-rps.max_freq_softlimit = dev_priv-rps.max_freq;
+
+ if (dev_priv-rps.min_freq_softlimit == 0)
+ dev_priv-rps.min_freq_softlimit = dev_priv-rps.min_freq;
+
+ mutex_unlock(dev_priv-rps.hw_lock);
}
static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
@@ -3902,7 +3963,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_engine_cs *ring;
- u32 gtfifodbg, rc6_mode = 0, pcbr;
+ u32 gtfifodbg, val, rc6_mode = 0, pcbr;
int i;
WARN_ON(!mutex_is_locked(dev_priv-rps.hw_lock));
@@ -3949,6
[Intel-gfx] [PATCH v7] drm/i915/chv: Enable RPS (Turbo) for Cherryview
From: Deepak S deepa...@linux.intel.com
v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
v3: Mass rename of the dev_priv-rps variables in upstream.
v4: Rebase against latest code. (Deepak)
v5: Rebase against latest nightly code. (Deepak)
v6: Rename the variables to match the spec (Mika)
v7: change min/max freq variable naming to match spec (Mika)
Signed-off-by: Deepak S deepa...@linux.intel.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_reg.h | 11 +
drivers/gpu/drm/i915/intel_pm.c | 92 -
2 files changed, 102 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1f36a5..8a935cf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -529,6 +529,16 @@ enum punit_power_well {
#define PUNIT_FUSE_BUS20xf6 /* bits 47:40 */
#define PUNIT_FUSE_BUS10xf5 /* bits 55:48 */
+#define PUNIT_GPU_STATUS_REG 0xdb
+#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT16
+#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
+#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT8
+#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
+
+#define PUNIT_GPU_DUTYCYCLE_REG0xdf
+#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
+#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
+
#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
#define FB_GFX_MAX_FREQ_FUSE_MASK0x07f8
@@ -933,6 +943,7 @@ enum punit_power_well {
#define SANDYBRIDGE_FENCE_PITCH_SHIFT32
#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
+
/* control register for cpu gtt access */
#define TILECTL0x101000
#define TILECTL_SWZCTL (1 0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1816c52..0f36405 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3731,6 +3731,35 @@ void gen6_update_ring_freq(struct drm_device *dev)
mutex_unlock(dev_priv-rps.hw_lock);
}
+int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rp0;
+
+ val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
+ rp0 = (val PUNIT_GPU_STATUS_MAX_FREQ_SHIFT)
PUNIT_GPU_STATUS_MAX_FREQ_MASK;
+
+ return rp0;
+}
+
+static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rpe;
+
+ val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
+ rpe = (val PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT)
PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
+
+ return rpe;
+}
+
+int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rpn;
+
+ val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
+ rpn = (val PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT)
PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
+ return rpn;
+}
+
int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
{
u32 val, rp0;
@@ -3890,7 +3919,36 @@ static void valleyview_init_gt_powersave(struct
drm_device *dev)
static void cherryview_init_gt_powersave(struct drm_device *dev)
{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
cherryview_setup_pctx(dev);
+
+ mutex_lock(dev_priv-rps.hw_lock);
+
+ dev_priv-rps.max_freq = cherryview_rps_max_freq(dev_priv);
+ dev_priv-rps.rp0_freq = dev_priv-rps.max_freq;
+ DRM_DEBUG_DRIVER(max GPU freq: %d MHz (%u)\n,
+vlv_gpu_freq(dev_priv, dev_priv-rps.max_freq),
+dev_priv-rps.max_freq);
+
+ dev_priv-rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
+ DRM_DEBUG_DRIVER(RPe GPU freq: %d MHz (%u)\n,
+vlv_gpu_freq(dev_priv, dev_priv-rps.efficient_freq),
+dev_priv-rps.efficient_freq);
+
+ dev_priv-rps.min_freq = cherryview_rps_min_freq(dev_priv);
+ DRM_DEBUG_DRIVER(min GPU freq: %d MHz (%u)\n,
+vlv_gpu_freq(dev_priv, dev_priv-rps.min_freq),
+dev_priv-rps.min_freq);
+
+ /* Preserve min/max settings in case of re-init */
+ if (dev_priv-rps.max_freq_softlimit == 0)
+ dev_priv-rps.max_freq_softlimit = dev_priv-rps.max_freq;
+
+ if (dev_priv-rps.min_freq_softlimit == 0)
+ dev_priv-rps.min_freq_softlimit = dev_priv-rps.min_freq;
+
+ mutex_unlock(dev_priv-rps.hw_lock);
}
static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
@@ -3902,7 +3960,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_engine_cs *ring;
- u32 gtfifodbg, rc6_mode = 0, pcbr;
+ u32 gtfifodbg, val, rc6_mode = 0, pcbr;
int i;
WARN_ON
Re: [Intel-gfx] [PATCH 6/7] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
On Tuesday 27 May 2014 05:29 PM, Ville Syrjälä wrote: On Tue, May 27, 2014 at 01:42:50PM +0200, Daniel Vetter wrote: On Mon, May 26, 2014 at 06:19:07PM +0300, Mika Kuoppala wrote: deepa...@linux.intel.com writes: From: Deepak S deepa...@linux.intel.com Signed-off-by: Deepak S deepa...@linux.intel.com [vsyrjala: Fix merge fubmle where the code ended up in g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()] Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Acked-by: Ben Widawsky b...@bwidawsk.net --- drivers/gpu/drm/i915/intel_pm.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 08dcdc5..0b73a6d 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4026,7 +4026,18 @@ static void cherryview_enable_rps(struct drm_device *dev) GEN6_RP_UP_BUSY_AVG | GEN6_RP_DOWN_IDLE_AVG); + /* ToDo: Update the mem freq based on latest spec [CHV]*/ Please do and consider fixing the vlv decoding. It seems to be off too. Poke about this one here. Iirc the situation on vlv is simply terminal confusion, and iirc the current code matches reality of shipping vbiosen, but not any spec. Yeah changed back here: commit f6d519481b662d9fc52836e6e6107520f03e0122 Author: Deepak S deepa...@linux.intel.com Date: Thu Apr 3 21:01:28 2014 +0530 Revert drm/i915/vlv: fixup DDR freq detection per Punit spec As per the inputs provided by hardware team we still use DDR Rates as 0,1=800, 2=1066, 3=1333. With this change, Turbo freqs used on current machines matches. I think what we need is a comment there which states why we're going against the spec, just to avoid future confusion and someone accidentally changing it back again. I hope we're bettter for chv. One can dream. Problem is the spec is not update to latest. Based on the communication from the HW team i update the proper value. For CHV, I have updated based on the values i got from HW team. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 6/7] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
On Tuesday 27 May 2014 05:12 PM, Daniel Vetter wrote:
On Mon, May 26, 2014 at 06:19:07PM +0300, Mika Kuoppala wrote:
deepa...@linux.intel.com writes:
From: Deepak S deepa...@linux.intel.com
Signed-off-by: Deepak S deepa...@linux.intel.com
[vsyrjala: Fix merge fubmle where the code ended up in
g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Acked-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 08dcdc5..0b73a6d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4026,7 +4026,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
GEN6_RP_UP_BUSY_AVG |
GEN6_RP_DOWN_IDLE_AVG);
+ /* ToDo: Update the mem freq based on latest spec [CHV]*/
Please do and consider fixing the vlv decoding. It seems to be off
too.
Poke about this one here. Iirc the situation on vlv is simply terminal
confusion, and iirc the current code matches reality of shipping vbiosen,
but not any spec. I hope we're bettter for chv.
-Daniel
I am trying to get proper values updated in the spec so that we dont have
confusion. Once it is available I will update the code accordingly.
-Mika
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ switch ((val 6) 3) {
+ case 0:
+ case 1:
+ case 2:
+ dev_priv-mem_freq = 1600;
+ break;
+ case 3:
+ dev_priv-mem_freq = 2000;
+ break;
+ }
DRM_DEBUG_DRIVER(GPLL enabled? %s\n, val 0x10 ? yes : no);
DRM_DEBUG_DRIVER(GPU status: 0x%08x\n, val);
--
1.9.1
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Re: [Intel-gfx] [PATCH 3/7] drm/i915/chv: Enable RPS (Turbo) for Cherryview
On Monday 26 May 2014 07:00 PM, Mika Kuoppala wrote:
Hi Deepak,
deepa...@linux.intel.com writes:
From: Deepak S deepa...@linux.intel.com
v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
v3: Mass rename of the dev_priv-rps variables in upstream.
v4: Rebase against latest code. (Deepak)
v5: Rebase against latest nightly code. (Deepak)
Signed-off-by: Deepak S deepa...@linux.intel.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 10
drivers/gpu/drm/i915/intel_pm.c | 95 ++-
drivers/gpu/drm/i915/intel_sideband.c | 14 ++
4 files changed, 119 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0412b12..5f0e338 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2621,6 +2621,7 @@ int sandybridge_pcode_write(struct drm_i915_private
*dev_priv, u8 mbox, u32 val)
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
+u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1f36a5..37f4b12 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -487,6 +487,7 @@
#define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
#define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
+#define CHV_IOSF_PORT_NC 0x04
Use IOSF_PORT_PUNIT instead of defining this?
Yes, Agreed, I will address this
/* See configdb bunit SB addr map */
#define BUNIT_REG_BISOC 0x11
@@ -529,6 +530,14 @@ enum punit_power_well {
#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
+#define CHV_IOSF_NC_FB_GFX_FREQ_FUSE 0xdb
+#define CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT 16
+#define CHV_FB_GFX_MAX_FREQ_FUSE_MASK 0xff
+
+#define CHV_IOSF_NC_FB_GFX_RPE_FUSE0xdf
+#define CHV_FB_RPE_FREQ_SHIFT 8
+#define CHV_FB_RPE_FREQ_MASK 0xff
+
These seem to be also part of punit space so I would prefer:
PUNIT_REG_GPU_STATUS0xdb
PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
PUNIT_REG_GPU_DUTYCYCLE 0xdf
etc...
I can change. Q? don't we want to identify the register with CHV?
#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
#define FB_GFX_MAX_FREQ_FUSE_MASK 0x07f8
@@ -933,6 +942,7 @@ enum punit_power_well {
#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
#define GEN7_FENCE_MAX_PITCH_VAL0x0800
+
/* control register for cpu gtt access */
#define TILECTL 0x101000
#define TILECTL_SWZCTL (1 0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1816c52..08dcdc5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3731,6 +3731,38 @@ void gen6_update_ring_freq(struct drm_device *dev)
mutex_unlock(dev_priv-rps.hw_lock);
}
+int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rp0;
+
+ val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
+
I didn't find any reason we couldn't use vlv_punit_read().
I am adding separate function to be inline with VLV. If needed we can modify
both VLV and CHV
I would prefer to keep distinguish between fuse and punit read.
+ rp0 = (val CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT)
+ CHV_FB_GFX_MAX_FREQ_FUSE_MASK;
+
+ return rp0;
+}
+
+static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rpe;
+
+ val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_RPE_FUSE);
+ rpe = (val CHV_FB_RPE_FREQ_SHIFT) CHV_FB_RPE_FREQ_MASK;
+
+ return rpe;
+}
+
+int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rpn;
+
+ val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
+ rpn = (val CHV_FB_RPE_FREQ_SHIFT) CHV_FB_RPE_FREQ_MASK;
+
Please don't reuse mask/shift from other register even tho
they happen to be identical. This confuses the reader alot.
Define new ones with proper naming.
+ return rpn;
+}
+
int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
{
u32 val, rp0
Re: [Intel-gfx] [PATCH 3/7] drm/i915/chv: Enable RPS (Turbo) for Cherryview
Thanks for the Review. I will address the comments
On Monday 26 May 2014 08:07 PM, Mika Kuoppala wrote:
Deepak S deepa...@linux.intel.com writes:
On Monday 26 May 2014 07:00 PM, Mika Kuoppala wrote:
Hi Deepak,
deepa...@linux.intel.com writes:
From: Deepak S deepa...@linux.intel.com
v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
v3: Mass rename of the dev_priv-rps variables in upstream.
v4: Rebase against latest code. (Deepak)
v5: Rebase against latest nightly code. (Deepak)
Signed-off-by: Deepak S deepa...@linux.intel.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 10
drivers/gpu/drm/i915/intel_pm.c | 95
++-
drivers/gpu/drm/i915/intel_sideband.c | 14 ++
4 files changed, 119 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0412b12..5f0e338 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2621,6 +2621,7 @@ int sandybridge_pcode_write(struct drm_i915_private
*dev_priv, u8 mbox, u32 val)
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
+u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1f36a5..37f4b12 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -487,6 +487,7 @@
#define VLV_IOSF_DATA(VLV_DISPLAY_BASE +
0x2104)
#define VLV_IOSF_ADDR(VLV_DISPLAY_BASE +
0x2108)
+#define CHV_IOSF_PORT_NC 0x04
Use IOSF_PORT_PUNIT instead of defining this?
Yes, Agreed, I will address this
/* See configdb bunit SB addr map */
#define BUNIT_REG_BISOC 0x11
@@ -529,6 +530,14 @@ enum punit_power_well {
#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
+#define CHV_IOSF_NC_FB_GFX_FREQ_FUSE 0xdb
+#define CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT 16
+#define CHV_FB_GFX_MAX_FREQ_FUSE_MASK 0xff
+
+#define CHV_IOSF_NC_FB_GFX_RPE_FUSE0xdf
+#define CHV_FB_RPE_FREQ_SHIFT 8
+#define CHV_FB_RPE_FREQ_MASK 0xff
+
These seem to be also part of punit space so I would prefer:
PUNIT_REG_GPU_STATUS0xdb
PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
PUNIT_REG_GPU_DUTYCYCLE 0xdf
etc...
I can change. Q? don't we want to identify the register with CHV?
If you like, add /* chv */ after those punit regs you add.
I would not globber the namespace more. As in this case only chv
code will use these inside cherryview_* named functions.
#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
#define FB_GFX_MAX_FREQ_FUSE_MASK 0x07f8
@@ -933,6 +942,7 @@ enum punit_power_well {
#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
+
/* control register for cpu gtt access */
#define TILECTL 0x101000
#define TILECTL_SWZCTL (1 0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1816c52..08dcdc5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3731,6 +3731,38 @@ void gen6_update_ring_freq(struct drm_device *dev)
mutex_unlock(dev_priv-rps.hw_lock);
}
+int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rp0;
+
+ val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
+
I didn't find any reason we couldn't use vlv_punit_read().
I am adding separate function to be inline with VLV. If needed we can modify
both VLV and CHV
I would prefer to keep distinguish between fuse and punit read.
+ rp0 = (val CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT)
+ CHV_FB_GFX_MAX_FREQ_FUSE_MASK;
+
+ return rp0;
+}
+
+static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rpe;
+
+ val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_RPE_FUSE);
+ rpe = (val CHV_FB_RPE_FREQ_SHIFT) CHV_FB_RPE_FREQ_MASK;
+
+ return rpe;
+}
+
+int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rpn;
+
+ val = chv_nc_read(dev_priv
Re: [Intel-gfx] [PATCH 3/7] drm/i915/chv: Enable RPS (Turbo) for Cherryview
On Monday 26 May 2014 08:02 PM, Ville Syrjälä wrote:
On Mon, May 26, 2014 at 07:24:21PM +0530, Deepak S wrote:
On Monday 26 May 2014 07:00 PM, Mika Kuoppala wrote:
Hi Deepak,
deepa...@linux.intel.com writes:
From: Deepak S deepa...@linux.intel.com
v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
v3: Mass rename of the dev_priv-rps variables in upstream.
v4: Rebase against latest code. (Deepak)
v5: Rebase against latest nightly code. (Deepak)
Signed-off-by: Deepak S deepa...@linux.intel.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 10
drivers/gpu/drm/i915/intel_pm.c | 95
++-
drivers/gpu/drm/i915/intel_sideband.c | 14 ++
4 files changed, 119 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0412b12..5f0e338 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2621,6 +2621,7 @@ int sandybridge_pcode_write(struct drm_i915_private
*dev_priv, u8 mbox, u32 val)
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
+u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1f36a5..37f4b12 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -487,6 +487,7 @@
#define VLV_IOSF_DATA(VLV_DISPLAY_BASE +
0x2104)
#define VLV_IOSF_ADDR(VLV_DISPLAY_BASE +
0x2108)
+#define CHV_IOSF_PORT_NC 0x04
Use IOSF_PORT_PUNIT instead of defining this?
Yes, Agreed, I will address this
/* See configdb bunit SB addr map */
#define BUNIT_REG_BISOC 0x11
@@ -529,6 +530,14 @@ enum punit_power_well {
#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
+#define CHV_IOSF_NC_FB_GFX_FREQ_FUSE 0xdb
+#define CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT 16
+#define CHV_FB_GFX_MAX_FREQ_FUSE_MASK 0xff
+
+#define CHV_IOSF_NC_FB_GFX_RPE_FUSE0xdf
+#define CHV_FB_RPE_FREQ_SHIFT 8
+#define CHV_FB_RPE_FREQ_MASK 0xff
+
These seem to be also part of punit space so I would prefer:
PUNIT_REG_GPU_STATUS0xdb
PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
PUNIT_REG_GPU_DUTYCYCLE 0xdf
etc...
I can change. Q? don't we want to identify the register with CHV?
#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
#define FB_GFX_MAX_FREQ_FUSE_MASK 0x07f8
@@ -933,6 +942,7 @@ enum punit_power_well {
#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
+
/* control register for cpu gtt access */
#define TILECTL 0x101000
#define TILECTL_SWZCTL (1 0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1816c52..08dcdc5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3731,6 +3731,38 @@ void gen6_update_ring_freq(struct drm_device *dev)
mutex_unlock(dev_priv-rps.hw_lock);
}
+int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rp0;
+
+ val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
+
I didn't find any reason we couldn't use vlv_punit_read().
I am adding separate function to be inline with VLV. If needed we can modify
both VLV and CHV
I would prefer to keep distinguish between fuse and punit read.
If the register is in the punit you should use the punit funcs. If
there's something special about those registers just add a comment
which explains it.
The whole nc unit seems to have disappeared in CHV, so it's rather
confusing when you see NC being mentioned and then you go digging
through the docs and can't find anything like it.
Reading the latest Docs, I will address the comments.
___
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[Intel-gfx] [PATCH 7/7] drm/i915/chv: Freq(opcode) request for CHV.
From: Deepak S deepa...@linux.intel.com
On CHV, All the freq request should be even. So, we need to make sure we
request the opcode accordingly.
v2: Avoid vairable for freq request (ville)
Signed-off-by: Deepak S deepa...@linux.intel.com
Reviewed-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_irq.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 28bae6e..671d751 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1258,8 +1258,10 @@ static void gen6_pm_rps_work(struct work_struct *work)
if (pm_iir GEN6_PM_RP_UP_THRESHOLD) {
if (adj 0)
adj *= 2;
- else
- adj = 1;
+ else {
+ /* CHV needs even encode values */
+ adj = IS_CHERRYVIEW(dev_priv-dev) ? 2 : 1;
+ }
new_delay = dev_priv-rps.cur_freq + adj;
/*
@@ -1277,8 +1279,10 @@ static void gen6_pm_rps_work(struct work_struct *work)
} else if (pm_iir GEN6_PM_RP_DOWN_THRESHOLD) {
if (adj 0)
adj *= 2;
- else
- adj = -1;
+ else {
+ /* CHV needs even encode values */
+ adj = IS_CHERRYVIEW(dev_priv-dev) ? -2 : -1;
+ }
new_delay = dev_priv-rps.cur_freq + adj;
} else { /* unknown event */
new_delay = dev_priv-rps.cur_freq;
--
1.9.1
___
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/7] Enable RC6/Turbo on CHV
From: Deepak S deepa...@linux.intel.com Squashed some of the patches and rebased the patches on latest nightly. Deepak S (5): drm/i915/chv: Enable Render Standby (RC6) for Cherryview drm/i915/chv: Added CHV specific register read and write and Streamline CHV forcewake stuff drm/i915/chv: Enable RPS (Turbo) for Cherryview drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating drm/i915/chv: Freq(opcode) request for CHV. Ville Syrjälä (2): drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0 drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_irq.c | 12 +- drivers/gpu/drm/i915/i915_reg.h | 12 ++ drivers/gpu/drm/i915/intel_pm.c | 219 +- drivers/gpu/drm/i915/intel_sideband.c | 14 +++ drivers/gpu/drm/i915/intel_uncore.c | 146 +++ 6 files changed, 372 insertions(+), 32 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/7] drm/i915/chv: Enable RPS (Turbo) for Cherryview
From: Deepak S deepa...@linux.intel.com
v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
v3: Mass rename of the dev_priv-rps variables in upstream.
v4: Rebase against latest code. (Deepak)
v5: Rebase against latest nightly code. (Deepak)
Signed-off-by: Deepak S deepa...@linux.intel.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 10
drivers/gpu/drm/i915/intel_pm.c | 95 ++-
drivers/gpu/drm/i915/intel_sideband.c | 14 ++
4 files changed, 119 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0412b12..5f0e338 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2621,6 +2621,7 @@ int sandybridge_pcode_write(struct drm_i915_private
*dev_priv, u8 mbox, u32 val)
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
+u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1f36a5..37f4b12 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -487,6 +487,7 @@
#define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
#define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
+#define CHV_IOSF_PORT_NC 0x04
/* See configdb bunit SB addr map */
#define BUNIT_REG_BISOC0x11
@@ -529,6 +530,14 @@ enum punit_power_well {
#define PUNIT_FUSE_BUS20xf6 /* bits 47:40 */
#define PUNIT_FUSE_BUS10xf5 /* bits 55:48 */
+#define CHV_IOSF_NC_FB_GFX_FREQ_FUSE 0xdb
+#define CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT 16
+#define CHV_FB_GFX_MAX_FREQ_FUSE_MASK 0xff
+
+#define CHV_IOSF_NC_FB_GFX_RPE_FUSE0xdf
+#define CHV_FB_RPE_FREQ_SHIFT 8
+#define CHV_FB_RPE_FREQ_MASK 0xff
+
#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
#define FB_GFX_MAX_FREQ_FUSE_MASK0x07f8
@@ -933,6 +942,7 @@ enum punit_power_well {
#define SANDYBRIDGE_FENCE_PITCH_SHIFT32
#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
+
/* control register for cpu gtt access */
#define TILECTL0x101000
#define TILECTL_SWZCTL (1 0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1816c52..08dcdc5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3731,6 +3731,38 @@ void gen6_update_ring_freq(struct drm_device *dev)
mutex_unlock(dev_priv-rps.hw_lock);
}
+int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rp0;
+
+ val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
+
+ rp0 = (val CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT)
+ CHV_FB_GFX_MAX_FREQ_FUSE_MASK;
+
+ return rp0;
+}
+
+static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rpe;
+
+ val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_RPE_FUSE);
+ rpe = (val CHV_FB_RPE_FREQ_SHIFT) CHV_FB_RPE_FREQ_MASK;
+
+ return rpe;
+}
+
+int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rpn;
+
+ val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
+ rpn = (val CHV_FB_RPE_FREQ_SHIFT) CHV_FB_RPE_FREQ_MASK;
+
+ return rpn;
+}
+
int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
{
u32 val, rp0;
@@ -3890,7 +3922,36 @@ static void valleyview_init_gt_powersave(struct
drm_device *dev)
static void cherryview_init_gt_powersave(struct drm_device *dev)
{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
cherryview_setup_pctx(dev);
+
+ mutex_lock(dev_priv-rps.hw_lock);
+
+ dev_priv-rps.max_freq = cherryview_rps_max_freq(dev_priv);
+ dev_priv-rps.rp0_freq = dev_priv-rps.max_freq;
+ DRM_DEBUG_DRIVER(max GPU freq: %d MHz (%u)\n,
+vlv_gpu_freq(dev_priv, dev_priv-rps.max_freq),
+dev_priv-rps.max_freq);
+
+ dev_priv-rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
+ DRM_DEBUG_DRIVER(RPe GPU freq: %d MHz (%u)\n,
+vlv_gpu_freq(dev_priv, dev_priv-rps.efficient_freq),
+dev_priv-rps.efficient_freq);
+
+ dev_priv
[Intel-gfx] [PATCH 4/7] drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0
From: Ville Syrjälä ville.syrj...@linux.intel.com Skip __gen6_gt_wait_for_thread_c0() on CHV. Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_uncore.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 7409de0..5f9200a 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -231,8 +231,8 @@ static void __vlv_force_wake_get(struct drm_i915_private *dev_priv, } /* WaRsForcewakeWaitTC0:vlv */ - __gen6_gt_wait_for_thread_c0(dev_priv); - + if (!IS_CHERRYVIEW(dev_priv-dev)) + __gen6_gt_wait_for_thread_c0(dev_priv); } static void __vlv_force_wake_put(struct drm_i915_private *dev_priv, -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/7] drm/i915/chv: Added CHV specific register read and write and Streamline CHV forcewake stuff
From: Deepak S deepa...@linux.intel.com
Support to individually control Media/Render well based on the register access.
Add CHV specific write function to habdle difference between registers
that are sadowed vs those that need forcewake even for writes.
Streamline the CHV forcewake functions just like was done for VLV.
This will also fix a bug in accessing the common well registers,
where we'd end up trying to wake up the wells too many times
since we'd call force_wake_get/put twice per register access, with
FORCEFAKE_ALL both times.
v2: Drop write FIFO for CHV and add comman well forcewake (Ville)
Re-factor CHV/VLV Forcewake offsets (Ben)
v3: Fix for decrementing fw count in chv read/write. (Deepak)
v4: Squash the patches (Mika)
Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com
[vsyrjala: Move the register range macros into intel_uncore.c]
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_uncore.c | 135 +++-
1 file changed, 118 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 2f5d5d3..7409de0 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -486,16 +486,43 @@ void assert_force_wake_inactive(struct drm_i915_private
*dev_priv)
#define NEEDS_FORCE_WAKE(dev_priv, reg) \
((reg) 0x4 (reg) != FORCEWAKE)
-#define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
- (((reg) = 0x2000 (reg) 0x4000) ||\
- ((reg) = 0x5000 (reg) 0x8000) ||\
- ((reg) = 0xB000 (reg) 0x12000) ||\
- ((reg) = 0x2E000 (reg) 0x3))
+#define REG_RANGE(reg, start, end) ((reg) = (start) (reg) (end))
-#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\
- (((reg) = 0x12000 (reg) 0x14000) ||\
- ((reg) = 0x22000 (reg) 0x24000) ||\
- ((reg) = 0x3 (reg) 0x4))
+#define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
+ (REG_RANGE((reg), 0x2000, 0x4000) || \
+REG_RANGE((reg), 0x5000, 0x8000) || \
+REG_RANGE((reg), 0xB000, 0x12000) || \
+REG_RANGE((reg), 0x2E000, 0x3))
+
+#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
+ (REG_RANGE((reg), 0x12000, 0x14000) || \
+REG_RANGE((reg), 0x22000, 0x24000) || \
+REG_RANGE((reg), 0x3, 0x4))
+
+#define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
+ (REG_RANGE((reg), 0x2000, 0x4000) || \
+REG_RANGE((reg), 0x5000, 0x8000) || \
+REG_RANGE((reg), 0x8300, 0x8500) || \
+REG_RANGE((reg), 0xB000, 0xC000) || \
+REG_RANGE((reg), 0xE000, 0xE800))
+
+#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
+ (REG_RANGE((reg), 0x8800, 0x8900) || \
+REG_RANGE((reg), 0xD000, 0xD800) || \
+REG_RANGE((reg), 0x12000, 0x14000) || \
+REG_RANGE((reg), 0x1A000, 0x1C000) || \
+REG_RANGE((reg), 0x1E800, 0x1EA00) || \
+REG_RANGE((reg), 0x3, 0x4))
+
+#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
+ (REG_RANGE((reg), 0x4000, 0x5000) || \
+REG_RANGE((reg), 0x8000, 0x8300) || \
+REG_RANGE((reg), 0x8500, 0x8600) || \
+REG_RANGE((reg), 0x9000, 0xB000) || \
+REG_RANGE((reg), 0xC000, 0xC800) || \
+REG_RANGE((reg), 0xF000, 0x1) || \
+REG_RANGE((reg), 0x14000, 0x14400) || \
+REG_RANGE((reg), 0x22000, 0x24000))
static void
ilk_dummy_write(struct drm_i915_private *dev_priv)
@@ -590,7 +617,35 @@ vlv_read##x(struct drm_i915_private *dev_priv, off_t reg,
bool trace) { \
REG_READ_FOOTER; \
}
+#define __chv_read(x) \
+static u##x \
+chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
+ unsigned fwengine = 0; \
+ REG_READ_HEADER(x); \
+ if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
+ if (dev_priv-uncore.fw_rendercount == 0) \
+ fwengine = FORCEWAKE_RENDER; \
+ } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
+ if (dev_priv-uncore.fw_mediacount == 0) \
+ fwengine = FORCEWAKE_MEDIA; \
+ } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
+ if (dev_priv-uncore.fw_rendercount == 0) \
+ fwengine |= FORCEWAKE_RENDER; \
+ if (dev_priv-uncore.fw_mediacount == 0) \
+ fwengine |= FORCEWAKE_MEDIA; \
+ } \
+ if (fwengine) \
+ dev_priv-uncore.funcs.force_wake_get(dev_priv, fwengine); \
+ val = __raw_i915_read##x(dev_priv, reg); \
+ if (fwengine) \
+ dev_priv-uncore.funcs.force_wake_put(dev_priv, fwengine); \
+ REG_READ_FOOTER; \
+}
+__chv_read(8)
+__chv_read(16)
+__chv_read(32)
+__chv_read(64)
__vlv_read(8)
__vlv_read(16)
__vlv_read(32)
@@ -608,6 +663,7 @@ __gen4_read(16)
__gen4_read(32)
__gen4_read(64)
+#undef __chv_read
#undef __vlv_read
#undef __gen6_read
[Intel-gfx] [PATCH 5/7] drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV
From: Ville Syrjälä ville.syrj...@linux.intel.com CHV uses the gen8 shadow register mechanism so we shouldn't be checking the GT FIFO status. This effectively removes the posting read, so add an explicit posting read using FORCEWAKE_ACK_VLV (which is what use in vlv_forcewake_reset()). Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_uncore.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 5f9200a..d44941b 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -250,9 +250,10 @@ static void __vlv_force_wake_put(struct drm_i915_private *dev_priv, __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); - /* The below doubles as a POSTING_READ */ - gen6_gt_check_fifodbg(dev_priv); - + /* something from same cacheline, but !FORCEWAKE_VLV */ + __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); + if (!IS_CHERRYVIEW(dev_priv-dev)) + gen6_gt_check_fifodbg(dev_priv); } static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/7] drm/i915/chv: Enable Render Standby (RC6) for Cherryview
From: Deepak S deepa...@linux.intel.com
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
v3: Fix PCBR condition check during CHV RC6 Enable flag set
v4: Fixup PCBR comment msg. (Chris)
Rebase against latest code (Deak)
Fixup Spurious hunk (Ben)
v5: Fix PCBR and commentis msg (mika)
v6: Rebase patch on latest nightly (Deepak)
Signed-off-by: Deepak S deepa...@linux.intel.com
Acked-by: Ben Widawsky b...@bwidawsk.net
Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/intel_pm.c | 115 +---
2 files changed, 111 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5122254..c1f36a5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1167,6 +1167,8 @@ enum punit_power_well {
#define VLV_IMR(VLV_DISPLAY_BASE + 0x20a8)
#define VLV_ISR(VLV_DISPLAY_BASE + 0x20ac)
#define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
+#define VLV_PCBR_ADDR_SHIFT12
+
#define DISPLAY_PLANE_FLIP_PENDING(plane) (1(11-(plane))) /* A and B only
*/
#define EIR0x020b0
#define EMR0x020b4
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 906d06f..1816c52 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3341,6 +3341,13 @@ static void gen6_disable_rps(struct drm_device *dev)
gen6_disable_rps_interrupts(dev);
}
+static void cherryview_disable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ I915_WRITE(GEN6_RC_CONTROL, 0);
+}
+
static void valleyview_disable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -3763,6 +3770,35 @@ static void valleyview_check_pctx(struct
drm_i915_private *dev_priv)
dev_priv-vlv_pctx-stolen-start);
}
+
+/* Check that the pcbr address is not empty. */
+static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
+{
+ unsigned long pctx_addr = I915_READ(VLV_PCBR) ~4095;
+
+ WARN_ON((pctx_addr VLV_PCBR_ADDR_SHIFT) == 0);
+}
+
+static void cherryview_setup_pctx(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ unsigned long pctx_paddr, paddr;
+ struct i915_gtt *gtt = dev_priv-gtt;
+ u32 pcbr;
+ int pctx_size = 32*1024;
+
+ WARN_ON(!mutex_is_locked(dev-struct_mutex));
+
+ pcbr = I915_READ(VLV_PCBR);
+ if ((pcbr VLV_PCBR_ADDR_SHIFT) == 0) {
+ paddr = (dev_priv-mm.stolen_base +
+(gtt-stolen_size - pctx_size));
+
+ pctx_paddr = (paddr (~4095));
+ I915_WRITE(VLV_PCBR, pctx_paddr);
+ }
+}
+
static void valleyview_setup_pctx(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -3852,11 +3888,70 @@ static void valleyview_init_gt_powersave(struct
drm_device *dev)
mutex_unlock(dev_priv-rps.hw_lock);
}
+static void cherryview_init_gt_powersave(struct drm_device *dev)
+{
+ cherryview_setup_pctx(dev);
+}
+
static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
{
valleyview_cleanup_pctx(dev);
}
+static void cherryview_enable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_engine_cs *ring;
+ u32 gtfifodbg, rc6_mode = 0, pcbr;
+ int i;
+
+ WARN_ON(!mutex_is_locked(dev_priv-rps.hw_lock));
+
+ gtfifodbg = I915_READ(GTFIFODBG);
+ if (gtfifodbg) {
+ DRM_DEBUG_DRIVER(GT fifo had a previous error %x\n,
+gtfifodbg);
+ I915_WRITE(GTFIFODBG, gtfifodbg);
+ }
+
+ cherryview_check_pctx(dev_priv);
+
+ /* 1a 1b: Get forcewake during program sequence. Although the driver
+* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
+ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+
+ /* 2a: Program RC6 thresholds.*/
+ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 16);
+ I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
+ I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
+
+ for_each_ring(ring, dev_priv, i)
+ I915_WRITE(RING_MAX_IDLE(ring-mmio_base), 10);
+ I915_WRITE(GEN6_RC_SLEEP, 0);
+
+ I915_WRITE(GEN6_RC6_THRESHOLD, 5); /* 50/125ms per EI */
+
+ /* allows RC6 residency counter to work */
+ I915_WRITE(VLV_COUNTER_CONTROL,
+ _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
+ VLV_MEDIA_RC6_COUNT_EN |
+ VLV_RENDER_RC6_COUNT_EN));
+
+ /* For now we assume BIOS is allocating and populating the PCBR */
+ pcbr
[Intel-gfx] [PATCH 6/7] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
From: Deepak S deepa...@linux.intel.com
Signed-off-by: Deepak S deepa...@linux.intel.com
[vsyrjala: Fix merge fubmle where the code ended up in
g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Acked-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 08dcdc5..0b73a6d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4026,7 +4026,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
GEN6_RP_UP_BUSY_AVG |
GEN6_RP_DOWN_IDLE_AVG);
+ /* ToDo: Update the mem freq based on latest spec [CHV]*/
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ switch ((val 6) 3) {
+ case 0:
+ case 1:
+ case 2:
+ dev_priv-mem_freq = 1600;
+ break;
+ case 3:
+ dev_priv-mem_freq = 2000;
+ break;
+ }
DRM_DEBUG_DRIVER(GPLL enabled? %s\n, val 0x10 ? yes : no);
DRM_DEBUG_DRIVER(GPU status: 0x%08x\n, val);
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5] drm/i915/chv: Enable Render Standby (RC6) for Cherryview
From: Deepak S deepa...@linux.intel.com
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
v3: Fix PCBR condition check during CHV RC6 Enable flag set
v4: Fixup PCBR comment msg. (Chris)
Rebase against latest code (Deak)
Fixup Spurious hunk (Ben)
v5: Fix PCBR and commentis msg (mika)
Signed-off-by: Deepak S deepa...@linux.intel.com
Acked-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/intel_pm.c | 115 +---
2 files changed, 111 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c850254..b4074fd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -962,6 +962,8 @@ enum punit_power_well {
#define VLV_IMR(VLV_DISPLAY_BASE + 0x20a8)
#define VLV_ISR(VLV_DISPLAY_BASE + 0x20ac)
#define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
+#define VLV_PCBR_ADDR_SHIFT12
+
#define DISPLAY_PLANE_FLIP_PENDING(plane) (1(11-(plane))) /* A and B only
*/
#define EIR0x020b0
#define EMR0x020b4
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 270b659..7a6e50e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3301,6 +3301,13 @@ static void gen6_disable_rps(struct drm_device *dev)
gen6_disable_rps_interrupts(dev);
}
+static void cherryview_disable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ I915_WRITE(GEN6_RC_CONTROL, 0);
+}
+
static void valleyview_disable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -3723,6 +3730,35 @@ static void valleyview_check_pctx(struct
drm_i915_private *dev_priv)
dev_priv-vlv_pctx-stolen-start);
}
+
+/* Check that the pcbr address is not empty. */
+static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
+{
+ unsigned long pctx_addr = I915_READ(VLV_PCBR) ~4095;
+
+ WARN_ON((pctx_addr VLV_PCBR_ADDR_SHIFT) == 0);
+}
+
+static void cherryview_setup_pctx(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ unsigned long pctx_paddr, paddr;
+ struct i915_gtt *gtt = dev_priv-gtt;
+ u32 pcbr;
+ int pctx_size = 32*1024;
+
+ WARN_ON(!mutex_is_locked(dev-struct_mutex));
+
+ pcbr = I915_READ(VLV_PCBR);
+ if ((pcbr VLV_PCBR_ADDR_SHIFT) == 0) {
+ paddr = (dev_priv-mm.stolen_base +
+(gtt-stolen_size - pctx_size));
+
+ pctx_paddr = (paddr (~4095));
+ I915_WRITE(VLV_PCBR, pctx_paddr);
+ }
+}
+
static void valleyview_setup_pctx(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -3812,11 +3848,70 @@ static void valleyview_init_gt_powersave(struct
drm_device *dev)
mutex_unlock(dev_priv-rps.hw_lock);
}
+static void cherryview_init_gt_powersave(struct drm_device *dev)
+{
+ cherryview_setup_pctx(dev);
+}
+
static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
{
valleyview_cleanup_pctx(dev);
}
+static void cherryview_enable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_ring_buffer *ring;
+ u32 gtfifodbg, rc6_mode = 0, pcbr;
+ int i;
+
+ WARN_ON(!mutex_is_locked(dev_priv-rps.hw_lock));
+
+ gtfifodbg = I915_READ(GTFIFODBG);
+ if (gtfifodbg) {
+ DRM_DEBUG_DRIVER(GT fifo had a previous error %x\n,
+gtfifodbg);
+ I915_WRITE(GTFIFODBG, gtfifodbg);
+ }
+
+ cherryview_check_pctx(dev_priv);
+
+ /* 1a 1b: Get forcewake during program sequence. Although the driver
+* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
+ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+
+ /* 2a: Program RC6 thresholds.*/
+ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 16);
+ I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
+ I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
+
+ for_each_ring(ring, dev_priv, i)
+ I915_WRITE(RING_MAX_IDLE(ring-mmio_base), 10);
+ I915_WRITE(GEN6_RC_SLEEP, 0);
+
+ I915_WRITE(GEN6_RC6_THRESHOLD, 5); /* 50/125ms per EI */
+
+ /* allows RC6 residency counter to work */
+ I915_WRITE(VLV_COUNTER_CONTROL,
+ _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
+ VLV_MEDIA_RC6_COUNT_EN |
+ VLV_RENDER_RC6_COUNT_EN));
+
+ /* For now we assume BIOS is allocating and populating the PCBR */
+ pcbr = I915_READ(VLV_PCBR);
+
+ DRM_DEBUG_DRIVER(PCBR offset : 0x%x\n, pcbr);
+
+ /* 3: Enable
Re: [Intel-gfx] [PATCH v5] drm/i915/chv: Enable Render Standby (RC6) for Cherryview
Hi Mika,
On the PCBR check comment. I will create a separate patch to address both VLV
and CHV
Thanks
Deepak
On Thursday 15 May 2014 03:27 PM, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
v3: Fix PCBR condition check during CHV RC6 Enable flag set
v4: Fixup PCBR comment msg. (Chris)
Rebase against latest code (Deak)
Fixup Spurious hunk (Ben)
v5: Fix PCBR and commentis msg (mika)
Signed-off-by: Deepak S deepa...@linux.intel.com
Acked-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/intel_pm.c | 115 +---
2 files changed, 111 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c850254..b4074fd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -962,6 +962,8 @@ enum punit_power_well {
#define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
#define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
#define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
+#define VLV_PCBR_ADDR_SHIFT12
+
#define DISPLAY_PLANE_FLIP_PENDING(plane) (1(11-(plane))) /* A and B only
*/
#define EIR 0x020b0
#define EMR 0x020b4
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 270b659..7a6e50e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3301,6 +3301,13 @@ static void gen6_disable_rps(struct drm_device *dev)
gen6_disable_rps_interrupts(dev);
}
+static void cherryview_disable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ I915_WRITE(GEN6_RC_CONTROL, 0);
+}
+
static void valleyview_disable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -3723,6 +3730,35 @@ static void valleyview_check_pctx(struct
drm_i915_private *dev_priv)
dev_priv-vlv_pctx-stolen-start);
}
+
+/* Check that the pcbr address is not empty. */
+static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
+{
+ unsigned long pctx_addr = I915_READ(VLV_PCBR) ~4095;
+
+ WARN_ON((pctx_addr VLV_PCBR_ADDR_SHIFT) == 0);
+}
+
+static void cherryview_setup_pctx(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ unsigned long pctx_paddr, paddr;
+ struct i915_gtt *gtt = dev_priv-gtt;
+ u32 pcbr;
+ int pctx_size = 32*1024;
+
+ WARN_ON(!mutex_is_locked(dev-struct_mutex));
+
+ pcbr = I915_READ(VLV_PCBR);
+ if ((pcbr VLV_PCBR_ADDR_SHIFT) == 0) {
+ paddr = (dev_priv-mm.stolen_base +
+(gtt-stolen_size - pctx_size));
+
+ pctx_paddr = (paddr (~4095));
+ I915_WRITE(VLV_PCBR, pctx_paddr);
+ }
+}
+
static void valleyview_setup_pctx(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -3812,11 +3848,70 @@ static void valleyview_init_gt_powersave(struct
drm_device *dev)
mutex_unlock(dev_priv-rps.hw_lock);
}
+static void cherryview_init_gt_powersave(struct drm_device *dev)
+{
+ cherryview_setup_pctx(dev);
+}
+
static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
{
valleyview_cleanup_pctx(dev);
}
+static void cherryview_enable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_ring_buffer *ring;
+ u32 gtfifodbg, rc6_mode = 0, pcbr;
+ int i;
+
+ WARN_ON(!mutex_is_locked(dev_priv-rps.hw_lock));
+
+ gtfifodbg = I915_READ(GTFIFODBG);
+ if (gtfifodbg) {
+ DRM_DEBUG_DRIVER(GT fifo had a previous error %x\n,
+gtfifodbg);
+ I915_WRITE(GTFIFODBG, gtfifodbg);
+ }
+
+ cherryview_check_pctx(dev_priv);
+
+ /* 1a 1b: Get forcewake during program sequence. Although the driver
+* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
+ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+
+ /* 2a: Program RC6 thresholds.*/
+ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 16);
+ I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
+ I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
+
+ for_each_ring(ring, dev_priv, i)
+ I915_WRITE(RING_MAX_IDLE(ring-mmio_base), 10);
+ I915_WRITE(GEN6_RC_SLEEP, 0);
+
+ I915_WRITE(GEN6_RC6_THRESHOLD, 5); /* 50/125ms per EI */
+
+ /* allows RC6 residency counter to work */
+ I915_WRITE(VLV_COUNTER_CONTROL,
+ _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
+ VLV_MEDIA_RC6_COUNT_EN
[Intel-gfx] [PATCH v5 1/8] drm/i915/chv: Enable Render Standby (RC6) for Cherryview
From: Deepak S deepa...@linux.intel.com
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
v3: Fix PCBR condition check during CHV RC6 Enable flag set
v4: Fixup PCBR comment msg. (Chris)
Rebase against latest code (Deak)
Fixup Spurious hunk (Ben)
v5: Fix PCBR and commentis msg (mika)
Signed-off-by: Deepak S deepa...@linux.intel.com
Acked-by: Ben Widawsky b...@bwidawsk.net
Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/intel_pm.c | 115 +---
2 files changed, 111 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c850254..b4074fd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -962,6 +962,8 @@ enum punit_power_well {
#define VLV_IMR(VLV_DISPLAY_BASE + 0x20a8)
#define VLV_ISR(VLV_DISPLAY_BASE + 0x20ac)
#define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
+#define VLV_PCBR_ADDR_SHIFT12
+
#define DISPLAY_PLANE_FLIP_PENDING(plane) (1(11-(plane))) /* A and B only
*/
#define EIR0x020b0
#define EMR0x020b4
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 270b659..7a6e50e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3301,6 +3301,13 @@ static void gen6_disable_rps(struct drm_device *dev)
gen6_disable_rps_interrupts(dev);
}
+static void cherryview_disable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ I915_WRITE(GEN6_RC_CONTROL, 0);
+}
+
static void valleyview_disable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -3723,6 +3730,35 @@ static void valleyview_check_pctx(struct
drm_i915_private *dev_priv)
dev_priv-vlv_pctx-stolen-start);
}
+
+/* Check that the pcbr address is not empty. */
+static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
+{
+ unsigned long pctx_addr = I915_READ(VLV_PCBR) ~4095;
+
+ WARN_ON((pctx_addr VLV_PCBR_ADDR_SHIFT) == 0);
+}
+
+static void cherryview_setup_pctx(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ unsigned long pctx_paddr, paddr;
+ struct i915_gtt *gtt = dev_priv-gtt;
+ u32 pcbr;
+ int pctx_size = 32*1024;
+
+ WARN_ON(!mutex_is_locked(dev-struct_mutex));
+
+ pcbr = I915_READ(VLV_PCBR);
+ if ((pcbr VLV_PCBR_ADDR_SHIFT) == 0) {
+ paddr = (dev_priv-mm.stolen_base +
+(gtt-stolen_size - pctx_size));
+
+ pctx_paddr = (paddr (~4095));
+ I915_WRITE(VLV_PCBR, pctx_paddr);
+ }
+}
+
static void valleyview_setup_pctx(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -3812,11 +3848,70 @@ static void valleyview_init_gt_powersave(struct
drm_device *dev)
mutex_unlock(dev_priv-rps.hw_lock);
}
+static void cherryview_init_gt_powersave(struct drm_device *dev)
+{
+ cherryview_setup_pctx(dev);
+}
+
static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
{
valleyview_cleanup_pctx(dev);
}
+static void cherryview_enable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_ring_buffer *ring;
+ u32 gtfifodbg, rc6_mode = 0, pcbr;
+ int i;
+
+ WARN_ON(!mutex_is_locked(dev_priv-rps.hw_lock));
+
+ gtfifodbg = I915_READ(GTFIFODBG);
+ if (gtfifodbg) {
+ DRM_DEBUG_DRIVER(GT fifo had a previous error %x\n,
+gtfifodbg);
+ I915_WRITE(GTFIFODBG, gtfifodbg);
+ }
+
+ cherryview_check_pctx(dev_priv);
+
+ /* 1a 1b: Get forcewake during program sequence. Although the driver
+* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
+ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+
+ /* 2a: Program RC6 thresholds.*/
+ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 16);
+ I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
+ I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
+
+ for_each_ring(ring, dev_priv, i)
+ I915_WRITE(RING_MAX_IDLE(ring-mmio_base), 10);
+ I915_WRITE(GEN6_RC_SLEEP, 0);
+
+ I915_WRITE(GEN6_RC6_THRESHOLD, 5); /* 50/125ms per EI */
+
+ /* allows RC6 residency counter to work */
+ I915_WRITE(VLV_COUNTER_CONTROL,
+ _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
+ VLV_MEDIA_RC6_COUNT_EN |
+ VLV_RENDER_RC6_COUNT_EN));
+
+ /* For now we assume BIOS is allocating and populating the PCBR */
+ pcbr = I915_READ(VLV_PCBR);
+
+ DRM_DEBUG_DRIVER
[Intel-gfx] [PATCH v3] drm/i915: Enable PM Interrupts target via Display Interface.
From: Deepak S deepa...@linux.intel.com
In BDW, Apart from unmasking up/down threshold interrupts. we need
to umask bit 32 of PM_INTRMASK to route interrupts to target via Display
Interface.
v2: Add (131) mask (Ville)
v3: Add Gen check for the mask (ville)
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ca4f8b9..c850254 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5112,6 +5112,7 @@ enum punit_power_well {
#define GEN6_RC6p_THRESHOLD0xA0BC
#define GEN6_RC6pp_THRESHOLD 0xA0C0
#define GEN6_PMINTRMSK 0xA168
+#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (131)
#define GEN6_PMISR 0x44020
#define GEN6_PMIMR 0x44024 /* rps_lock */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0e69c97..270b659 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3114,6 +3114,9 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private
*dev_priv, u8 val)
if (INTEL_INFO(dev_priv-dev)-gen = 7 !IS_HASWELL(dev_priv-dev))
mask |= GEN6_PM_RP_UP_EI_EXPIRED;
+ if (IS_GEN8(dev_priv-dev))
+ mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+
return ~mask;
}
--
1.9.1
___
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Re: [Intel-gfx] [PATCH 03/10] drm/i915/chv: Enable Render Standby (RC6) for Cherryview
On Friday 09 May 2014 06:49 PM, Mika Kuoppala wrote:
Hi Deepak,
deepa...@linux.intel.com writes:
From: Deepak S deepa...@linux.intel.com
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
v3: Fix PCBR condition check during CHV RC6 Enable flag set
v4: Fixup PCBR comment msg. (Chris)
Rebase against latest code (Deak)
Fixup Spurious hunk (Ben)
Signed-off-by: Deepak S deepa...@linux.intel.com
Acked-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/intel_pm.c | 115 +---
2 files changed, 111 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c850254..b4074fd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -962,6 +962,8 @@ enum punit_power_well {
#define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
#define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
#define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
+#define VLV_PCBR_ADDR_SHIFT12
+
#define DISPLAY_PLANE_FLIP_PENDING(plane) (1(11-(plane))) /* A and B only
*/
#define EIR 0x020b0
#define EMR 0x020b4
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ebb5c88..f0359b6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3300,6 +3300,13 @@ static void gen6_disable_rps(struct drm_device *dev)
gen6_disable_rps_interrupts(dev);
}
+static void cherryview_disable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ I915_WRITE(GEN6_RC_CONTROL, 0);
+}
+
static void valleyview_disable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -3722,6 +3729,33 @@ static void valleyview_check_pctx(struct
drm_i915_private *dev_priv)
dev_priv-vlv_pctx-stolen-start);
}
+
+/* Check that the pcbr address is not empty. */
+static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
+{
+ unsigned long pctx_addr = I915_READ(VLV_PCBR) ~4095;
+
+ WARN_ON((pctx_addr VLV_PCBR_ADDR_SHIFT) == 0);
+}
+
+static void cherryview_setup_pctx(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ unsigned long pctx_paddr;
+ struct i915_gtt *gtt = dev_priv-gtt;
+ u32 pcbr;
+ int pctx_size = 32*1024;
+
+ WARN_ON(!mutex_is_locked(dev-struct_mutex));
+
+ pcbr = I915_READ(VLV_PCBR);
+ if ((pcbr VLV_PCBR_ADDR_SHIFT) == 0) {
I admit that address zero locked by bios is prolly in
realms of paranoia. But I would still omit shift here to
get lock bit taken into consideration.
Agreed, But verifying address is more important right? We are more concerned
with address than lock bit right?
+ pctx_paddr = (dev_priv-mm.stolen_base +
+ (gtt-stolen_size - pctx_size));
+ I915_WRITE(VLV_PCBR, pctx_paddr);
In here tho I would mask the low bits out, just to be on
the safe side. If we get off by one on stolen calculation we end up
writing the lock bit.
I will add the mask bit
I am thinking that we should just sanity check that bios
has set this up and that it seems to be in correct place. If not, spit a
warning and leave rc6 disabled.
The BIOS should have setup everything for us. Why do we need this
PCBR setup?
Nice Point, We need to make sure BIOS is setting up the PCBR properly.
+ }
+}
+
static void valleyview_setup_pctx(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -3811,11 +3845,72 @@ static void valleyview_init_gt_powersave(struct
drm_device *dev)
mutex_unlock(dev_priv-rps.hw_lock);
}
+static void cherryview_init_gt_powersave(struct drm_device *dev)
+{
+ cherryview_setup_pctx(dev);
+}
+
static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
{
valleyview_cleanup_pctx(dev);
}
+static void cherryview_enable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_ring_buffer *ring;
+ u32 gtfifodbg, rc6_mode = 0, pcbr;
+ int i;
+
+ WARN_ON(!mutex_is_locked(dev_priv-rps.hw_lock));
+
+ gtfifodbg = I915_READ(GTFIFODBG);
+ if (gtfifodbg) {
+ DRM_DEBUG_DRIVER(GT fifo had a previous error %x\n,
+gtfifodbg);
+ I915_WRITE(GTFIFODBG, gtfifodbg);
+ }
+
+ cherryview_check_pctx(dev_priv);
+
+ /* 1a 1b: Get forcewake during program sequence. Although the driver
+* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
+ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+
I915_WRITE(GEN6_RC_CONTROL, 0);
+ /* 2a: Program RC6 thresholds.*/
+ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 16
[Intel-gfx] [PATCH v2] drm/i915/chv: Freq(opcode) request for CHV.
From: Deepak S deepa...@linux.intel.com
On CHV, All the freq request should be even. So, we need to make sure we
request the opcode accordingly.
v2: Avoid vairable for freq request (ville)
Signed-off-by: Deepak S deepa...@linux.intel.com
Reviewed-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_irq.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6af51ad..56e93e8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1161,8 +1161,10 @@ static void gen6_pm_rps_work(struct work_struct *work)
if (pm_iir GEN6_PM_RP_UP_THRESHOLD) {
if (adj 0)
adj *= 2;
- else
- adj = 1;
+ else {
+ /* CHV needs even encode values */
+ adj = IS_CHERRYVIEW(dev_priv-dev) ? 2 : 1;
+ }
new_delay = dev_priv-rps.cur_freq + adj;
/*
@@ -1180,8 +1182,10 @@ static void gen6_pm_rps_work(struct work_struct *work)
} else if (pm_iir GEN6_PM_RP_DOWN_THRESHOLD) {
if (adj 0)
adj *= 2;
- else
- adj = -1;
+ else {
+ /* CHV needs even encode values */
+ adj = IS_CHERRYVIEW(dev_priv-dev) ? -2 : -1;
+ }
new_delay = dev_priv-rps.cur_freq + adj;
} else { /* unknown event */
new_delay = dev_priv-rps.cur_freq;
--
1.9.1
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Re: [Intel-gfx] [PATCH v3] drm/i915: Debugfs disable RPS boost and idle
On Tuesday 06 May 2014 03:20 AM, Daisy Sun wrote:
RP frequency request is affected by 2 modules: normal turbo
algorithm and RPS boost algorithm. By adding RPS boost algorithm
to the mix, the final frequency becomes relatively unpredictable.
Add a switch to enable/disable RPS boost functionality. When
disabled, RP frequency will follow the normal turbo algorithm only.
Intention: when boost and idle are disabled, we have a clear vision
of turbo algorithm. It‘s very helpful to verify if the turbo
algorithm is working as expected.
Without debugfs hooks, the RPS boost or idle may kick in at
anytime and any circumstances.
V1-V2: Follow Daniel's comment to explain the intention.
V2-V3: Abandon flush_delayed work, abandon lock of rps.hw_lock
during get/set of rps.debugfs_disable_boost
Signed-off-by: Daisy Sun daisy@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 29 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 8 ++--
3 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 1e83ae4..685f7e5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3486,6 +3486,34 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
i915_drop_caches_get, i915_drop_caches_set,
0x%08llx\n);
+static int i915_rps_disable_boost_get(void *data, u64 *val)
+{
+ struct drm_device *dev = data;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ *val = dev_priv-rps.debugfs_disable_boost;
+
+ return 0;
+}
+
+static int i915_rps_disable_boost_set(void *data, u64 val)
+{
+ struct drm_device *dev = data;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ int ret;
+
+ DRM_DEBUG_DRIVER(%s RPS Boost-Idle mode\n,
+val ? Disable : Enable);
+
+ dev_priv-rps.debugfs_disable_boost = val;
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_rps_disable_boost_fops,
+ i915_rps_disable_boost_get, i915_rps_disable_boost_set,
+ %llu\n);
+
static int
i915_max_freq_get(void *data, u64 *val)
{
@@ -3821,6 +3849,7 @@ static const struct i915_debugfs_files {
{i915_wedged, i915_wedged_fops},
{i915_max_freq, i915_max_freq_fops},
{i915_min_freq, i915_min_freq_fops},
+ {i915_rps_disable_boost, i915_rps_disable_boost_fops},
{i915_cache_sharing, i915_cache_sharing_fops},
{i915_ring_stop, i915_ring_stop_fops},
{i915_ring_missed_irq, i915_ring_missed_irq_fops},
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 272aa7a..9c427da 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -847,6 +847,7 @@ struct intel_gen6_power_mgmt {
int last_adj;
enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
+ bool debugfs_disable_boost;
bool enabled;
struct delayed_work delayed_resume_work;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 75c1c76..6acac14 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3163,7 +3163,9 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
struct drm_device *dev = dev_priv-dev;
mutex_lock(dev_priv-rps.hw_lock);
- if (dev_priv-rps.enabled) {
+
+ if (dev_priv-rps.enabled
+!dev_priv-rps.debugfs_disable_boost) {
On VLV, when system is idle we wont get down threshold interrupts. So
disabling this will not help you to test the algorithm. I think we need to
retain gen6_rps_idle
if (IS_VALLEYVIEW(dev))
vlv_set_rps_idle(dev_priv);
else
@@ -3178,7 +3180,9 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv)
struct drm_device *dev = dev_priv-dev;
mutex_lock(dev_priv-rps.hw_lock);
- if (dev_priv-rps.enabled) {
+
+ if (dev_priv-rps.enabled
+!dev_priv-rps.debugfs_disable_boost) {
if (IS_VALLEYVIEW(dev))
valleyview_set_rps(dev_priv-dev,
dev_priv-rps.max_freq_softlimit);
else
___
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[Intel-gfx] [PATCH 01/10] drm/i915/bdw: Implement a basic PM interrupt handler
From: Ben Widawsky benjamin.widaw...@intel.com
Almost all of it is reusable from the existing code. The primary
difference is we need to do even less in the interrupt handler, since
interrupts are not shared in the same way.
The patch is mostly a copy-paste of the existing snb+ code, with updates
to the relevant parts requiring changes to the interrupt handling. As
such it /should/ be relatively trivial. It's highly likely that I missed
some places where I need a gen8 version of the PM interrupts, but it has
become invisible to me by now.
This patch could probably be split into adding the new functions,
followed by actually handling the interrupts. Since the code is
currently disabled (and broken) I think the patch stands better by
itself.
v2: Move the commit about not touching the ringbuffer interrupt to the
snb_* function where it belongs (Rodrigo)
v3: Rebased on Paulo's runtime PM changes
v4: Not well validated, but rebase on
commit 730488b2eddded4497f63f70867b1256cd9e117c
Author: Paulo Zanoni paulo.r.zan...@intel.com
Date: Fri Mar 7 20:12:32 2014 -0300
drm/i915: kill dev_priv-pm.regsave
v5: Rebased on latest code base. (Deepak)
v6: Remove conflict markers, Unnecessary empty line and use right
IIR interrupt (Ville)
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 75 ++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 38 ++--
4 files changed, 112 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2d76183..6af51ad 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -248,6 +248,49 @@ static bool ivb_can_enable_err_int(struct drm_device *dev)
return true;
}
+/**
+ * bdw_update_pm_irq - update GT interrupt 2
+ * @dev_priv: driver private
+ * @interrupt_mask: mask of interrupt bits to update
+ * @enabled_irq_mask: mask of interrupt bits to enable
+ *
+ * Copied from the snb function, updated with relevant register offsets
+ */
+static void bdw_update_pm_irq(struct drm_i915_private *dev_priv,
+ uint32_t interrupt_mask,
+ uint32_t enabled_irq_mask)
+{
+ uint32_t new_val;
+
+ assert_spin_locked(dev_priv-irq_lock);
+
+ if (dev_priv-pm.irqs_disabled) {
+ WARN(1, IRQs disabled\n);
+ return;
+ }
+
+ new_val = dev_priv-pm_irq_mask;
+ new_val = ~interrupt_mask;
+ new_val |= (~enabled_irq_mask interrupt_mask);
+
+ if (new_val != dev_priv-pm_irq_mask) {
+ dev_priv-pm_irq_mask = new_val;
+ I915_WRITE(GEN8_GT_IMR(2), I915_READ(GEN8_GT_IMR(2)) |
+ dev_priv-pm_irq_mask);
+ POSTING_READ(GEN8_GT_IMR(2));
+ }
+}
+
+void bdw_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
+{
+ bdw_update_pm_irq(dev_priv, mask, mask);
+}
+
+void bdw_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
+{
+ bdw_update_pm_irq(dev_priv, mask, 0);
+}
+
static bool cpt_can_enable_serr_int(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -1098,8 +1141,12 @@ static void gen6_pm_rps_work(struct work_struct *work)
spin_lock_irq(dev_priv-irq_lock);
pm_iir = dev_priv-rps.pm_iir;
dev_priv-rps.pm_iir = 0;
- /* Make sure not to corrupt PMIMR state used by ringbuffer code */
- snb_enable_pm_irq(dev_priv, dev_priv-pm_rps_events);
+ if (IS_BROADWELL(dev_priv-dev))
+ bdw_enable_pm_irq(dev_priv, dev_priv-pm_rps_events);
+ else {
+ /* Make sure not to corrupt PMIMR state used by ringbuffer */
+ snb_enable_pm_irq(dev_priv, dev_priv-pm_rps_events);
+ }
spin_unlock_irq(dev_priv-irq_lock);
/* Make sure we didn't queue anything we're not going to process. */
@@ -1296,6 +1343,19 @@ static void snb_gt_irq_handler(struct drm_device *dev,
ivybridge_parity_error_irq_handler(dev, gt_iir);
}
+static void gen8_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
+{
+ if ((pm_iir dev_priv-pm_rps_events) == 0)
+ return;
+
+ spin_lock(dev_priv-irq_lock);
+ dev_priv-rps.pm_iir |= pm_iir dev_priv-pm_rps_events;
+ bdw_disable_pm_irq(dev_priv, pm_iir dev_priv-pm_rps_events);
+ spin_unlock(dev_priv-irq_lock);
+
+ queue_work(dev_priv-wq, dev_priv-rps.work);
+}
+
static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
struct drm_i915_private *dev_priv,
u32 master_ctl)
@@ -1334,6 +1394,17 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_device
*dev
[Intel-gfx] [PATCH 04/10] drm/i915/chv: Added CHV specific register read and write
From: Deepak S deepa...@linux.intel.com
Support to individually control Media/Render well based on the register access.
Add CHV specific write function to habdle difference between registers
that are sadowed vs those that need forcewake even for writes.
v2: Drop write FIFO for CHV and add comman well forcewake (Ville)
v3: Fix for decrementing fw count in chv read/write. (Deepak)
Signed-off-by: Deepak S deepa...@linux.intel.com
[vsyrjala: Move the register range macros into intel_uncore.c]
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_uncore.c | 133 +---
1 file changed, 125 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 76dc185..4f1f199 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -495,6 +495,31 @@ void assert_force_wake_inactive(struct drm_i915_private
*dev_priv)
((reg) = 0x22000 (reg) 0x24000) ||\
((reg) = 0x3 (reg) 0x4))
+#define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
+ (((reg) = 0x2000 (reg) 0x4000) ||\
+ ((reg) = 0x5000 (reg) 0x8000) ||\
+ ((reg) = 0x8300 (reg) 0x8500) ||\
+ ((reg) = 0xB000 (reg) 0xC000) ||\
+ ((reg) = 0xE000 (reg) 0xE800))
+
+#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)\
+ (((reg) = 0x8800 (reg) 0x8900) ||\
+ ((reg) = 0xD000 (reg) 0xD800) ||\
+ ((reg) = 0x12000 (reg) 0x14000) ||\
+ ((reg) = 0x1A000 (reg) 0x1C000) ||\
+ ((reg) = 0x1E800 (reg) 0x1EA00) ||\
+ ((reg) = 0x3 (reg) 0x4))
+
+#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)\
+ (((reg) = 0x4000 (reg) 0x5000) ||\
+ ((reg) = 0x8000 (reg) 0x8300) ||\
+ ((reg) = 0x8500 (reg) 0x8600) ||\
+ ((reg) = 0x9000 (reg) 0xB000) ||\
+ ((reg) = 0xC000 (reg) 0xc800) ||\
+ ((reg) = 0xF000 (reg) 0x1) ||\
+ ((reg) = 0x14000 (reg) 0x14400) ||\
+ ((reg) = 0x22000 (reg) 0x24000))
+
static void
ilk_dummy_write(struct drm_i915_private *dev_priv)
{
@@ -588,7 +613,45 @@ vlv_read##x(struct drm_i915_private *dev_priv, off_t reg,
bool trace) { \
REG_READ_FOOTER; \
}
+#define __chv_read(x) \
+static u##x \
+chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
+ unsigned fwengine = 0; \
+ REG_READ_HEADER(x); \
+ if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
+ fwengine = FORCEWAKE_RENDER; \
+ else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
+ fwengine = FORCEWAKE_MEDIA; \
+ else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
+ fwengine = FORCEWAKE_ALL; \
+ if (FORCEWAKE_RENDER fwengine) { \
+ if (dev_priv-uncore.fw_rendercount++ == 0) \
+ (dev_priv)-uncore.funcs.force_wake_get(dev_priv, \
+ fwengine); \
+ } \
+ if (FORCEWAKE_MEDIA fwengine) { \
+ if (dev_priv-uncore.fw_mediacount++ == 0) \
+ (dev_priv)-uncore.funcs.force_wake_get(dev_priv, \
+ fwengine); \
+ } \
+ val = __raw_i915_read##x(dev_priv, reg); \
+ if (FORCEWAKE_RENDER fwengine) { \
+ if (--dev_priv-uncore.fw_rendercount == 0) \
+ (dev_priv)-uncore.funcs.force_wake_put(dev_priv, \
+ fwengine); \
+ } \
+ if (FORCEWAKE_MEDIA fwengine) { \
+ if (--dev_priv-uncore.fw_mediacount == 0) \
+ (dev_priv)-uncore.funcs.force_wake_put(dev_priv, \
+ fwengine); \
+ } \
+ REG_READ_FOOTER; \
+}
+__chv_read(8)
+__chv_read(16)
+__chv_read(32)
+__chv_read(64)
__vlv_read(8)
__vlv_read(16)
__vlv_read(32)
@@ -606,6 +669,7 @@ __gen4_read(16)
__gen4_read(32)
__gen4_read(64)
+#undef __chv_read
#undef __vlv_read
#undef __gen6_read
#undef __gen5_read
@@ -710,6 +774,46 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t
reg, u##x val, bool trace
REG_WRITE_FOOTER; \
}
+#define __chv_write(x) \
+static void \
+chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool
trace) { \
+ unsigned fwengine = 0; \
+ bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \
+ REG_WRITE_HEADER; \
+ if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
+ fwengine = FORCEWAKE_RENDER; \
+ else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
+ fwengine = FORCEWAKE_MEDIA; \
+ else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
+ fwengine = FORCEWAKE_ALL; \
+ if (__needs_put (FORCEWAKE_RENDER fwengine)) { \
+ if (dev_priv-uncore.fw_rendercount++ == 0
[Intel-gfx] [PATCH 02/10] drm/i915: Enable PM Interrupts target via Display Interface.
From: Deepak S deepa...@linux.intel.com
In BDW, Apart from unmasking up/down threshold interrupts. we need
to umask bit 32 of PM_INTRMASK to route interrupts to target via Display
Interface.
v2: Add (131) mask (Ville)
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ca4f8b9..c850254 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5112,6 +5112,7 @@ enum punit_power_well {
#define GEN6_RC6p_THRESHOLD0xA0BC
#define GEN6_RC6pp_THRESHOLD 0xA0C0
#define GEN6_PMINTRMSK 0xA168
+#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (131)
#define GEN6_PMISR 0x44020
#define GEN6_PMIMR 0x44024 /* rps_lock */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0e69c97..ebb5c88 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3114,6 +3114,8 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private
*dev_priv, u8 val)
if (INTEL_INFO(dev_priv-dev)-gen = 7 !IS_HASWELL(dev_priv-dev))
mask |= GEN6_PM_RP_UP_EI_EXPIRED;
+ mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+
return ~mask;
}
--
1.9.1
___
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[Intel-gfx] [PATCH 00/10] Enable RC6/Turbo on CHV
From: Deepak S deepa...@linux.intel.com Squashed some of the patches and created a new patch series. Addressed review comments on most of the patches. Ben Widawsky (1): drm/i915/bdw: Implement a basic PM interrupt handler Deepak S (7): drm/i915: Enable PM Interrupts target via Display Interface. drm/i915/chv: Enable Render Standby (RC6) for Cherryview drm/i915/chv: Added CHV specific register read and write drm/i915/chv: Streamline CHV forcewake stuff drm/i915/chv: Enable RPS (Turbo) for Cherryview drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating drm/i915/chv: Freq(opcode) request for CHV. Ville Syrjälä (2): drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0 drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_irq.c | 84 ++- drivers/gpu/drm/i915/i915_reg.h | 17 +++ drivers/gpu/drm/i915/intel_drv.h | 2 + drivers/gpu/drm/i915/intel_pm.c | 259 -- drivers/gpu/drm/i915/intel_sideband.c | 15 ++ drivers/gpu/drm/i915/intel_uncore.c | 146 --- 7 files changed, 491 insertions(+), 34 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/10] drm/i915/chv: Enable Render Standby (RC6) for Cherryview
From: Deepak S deepa...@linux.intel.com
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
v3: Fix PCBR condition check during CHV RC6 Enable flag set
v4: Fixup PCBR comment msg. (Chris)
Rebase against latest code (Deak)
Fixup Spurious hunk (Ben)
Signed-off-by: Deepak S deepa...@linux.intel.com
Acked-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/intel_pm.c | 115 +---
2 files changed, 111 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c850254..b4074fd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -962,6 +962,8 @@ enum punit_power_well {
#define VLV_IMR(VLV_DISPLAY_BASE + 0x20a8)
#define VLV_ISR(VLV_DISPLAY_BASE + 0x20ac)
#define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
+#define VLV_PCBR_ADDR_SHIFT12
+
#define DISPLAY_PLANE_FLIP_PENDING(plane) (1(11-(plane))) /* A and B only
*/
#define EIR0x020b0
#define EMR0x020b4
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ebb5c88..f0359b6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3300,6 +3300,13 @@ static void gen6_disable_rps(struct drm_device *dev)
gen6_disable_rps_interrupts(dev);
}
+static void cherryview_disable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ I915_WRITE(GEN6_RC_CONTROL, 0);
+}
+
static void valleyview_disable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -3722,6 +3729,33 @@ static void valleyview_check_pctx(struct
drm_i915_private *dev_priv)
dev_priv-vlv_pctx-stolen-start);
}
+
+/* Check that the pcbr address is not empty. */
+static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
+{
+ unsigned long pctx_addr = I915_READ(VLV_PCBR) ~4095;
+
+ WARN_ON((pctx_addr VLV_PCBR_ADDR_SHIFT) == 0);
+}
+
+static void cherryview_setup_pctx(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ unsigned long pctx_paddr;
+ struct i915_gtt *gtt = dev_priv-gtt;
+ u32 pcbr;
+ int pctx_size = 32*1024;
+
+ WARN_ON(!mutex_is_locked(dev-struct_mutex));
+
+ pcbr = I915_READ(VLV_PCBR);
+ if ((pcbr VLV_PCBR_ADDR_SHIFT) == 0) {
+ pctx_paddr = (dev_priv-mm.stolen_base +
+ (gtt-stolen_size - pctx_size));
+ I915_WRITE(VLV_PCBR, pctx_paddr);
+ }
+}
+
static void valleyview_setup_pctx(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -3811,11 +3845,72 @@ static void valleyview_init_gt_powersave(struct
drm_device *dev)
mutex_unlock(dev_priv-rps.hw_lock);
}
+static void cherryview_init_gt_powersave(struct drm_device *dev)
+{
+ cherryview_setup_pctx(dev);
+}
+
static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
{
valleyview_cleanup_pctx(dev);
}
+static void cherryview_enable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_ring_buffer *ring;
+ u32 gtfifodbg, rc6_mode = 0, pcbr;
+ int i;
+
+ WARN_ON(!mutex_is_locked(dev_priv-rps.hw_lock));
+
+ gtfifodbg = I915_READ(GTFIFODBG);
+ if (gtfifodbg) {
+ DRM_DEBUG_DRIVER(GT fifo had a previous error %x\n,
+gtfifodbg);
+ I915_WRITE(GTFIFODBG, gtfifodbg);
+ }
+
+ cherryview_check_pctx(dev_priv);
+
+ /* 1a 1b: Get forcewake during program sequence. Although the driver
+* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
+ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+
+ /* 2a: Program RC6 thresholds.*/
+ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 16);
+ I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
+ I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
+
+ for_each_ring(ring, dev_priv, i)
+ I915_WRITE(RING_MAX_IDLE(ring-mmio_base), 10);
+
+ I915_WRITE(GEN6_RC6_THRESHOLD, 5); /* 50/125ms per EI */
+
+ /* allows RC6 residency counter to work */
+ I915_WRITE(VLV_COUNTER_CONTROL,
+ _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
+ VLV_MEDIA_RC6_COUNT_EN |
+ VLV_RENDER_RC6_COUNT_EN));
+
+ /* Todo: If BIOS has not configured PCBR
+* then allocate in BIOS Reserved */
+
+ /* For now we assume BIOS is allocating and populating the PCBR */
+ pcbr = I915_READ(VLV_PCBR);
+
+ DRM_DEBUG_DRIVER(PCBR offset : 0x%x\n, pcbr);
+
+ /* 3: Enable RC6
[Intel-gfx] [PATCH 10/10] drm/i915/chv: Freq(opcode) request for CHV.
From: Deepak S deepa...@linux.intel.com
On CHV, All the freq request should be even. So, we need to make sure we
request the opcode accordingly.
Signed-off-by: Deepak S deepa...@linux.intel.com
Reviewed-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 9 +++--
drivers/gpu/drm/i915/i915_reg.h | 3 +++
3 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e70a9f0..3966ff2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1318,6 +1318,7 @@ struct drm_i915_private {
u32 gt_irq_mask;
u32 pm_irq_mask;
u32 pm_rps_events;
+ u32 pm_rps_freq_req;
u32 pipestat_irq_mask[I915_MAX_PIPES];
struct work_struct hotplug_work;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6af51ad..3e8bcca 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1162,7 +1162,7 @@ static void gen6_pm_rps_work(struct work_struct *work)
if (adj 0)
adj *= 2;
else
- adj = 1;
+ adj = dev_priv-pm_rps_freq_req;
new_delay = dev_priv-rps.cur_freq + adj;
/*
@@ -1181,7 +1181,7 @@ static void gen6_pm_rps_work(struct work_struct *work)
if (adj 0)
adj *= 2;
else
- adj = -1;
+ adj = -1 * dev_priv-pm_rps_freq_req;
new_delay = dev_priv-rps.cur_freq + adj;
} else { /* unknown event */
new_delay = dev_priv-rps.cur_freq;
@@ -4088,6 +4088,11 @@ void intel_irq_init(struct drm_device *dev)
/* Let's track the enabled rps events */
dev_priv-pm_rps_events = GEN6_PM_RPS_EVENTS;
+ if (IS_CHERRYVIEW(dev))
+ dev_priv-pm_rps_freq_req = CHV_GPU_FREQ_REQ;
+ else
+ dev_priv-pm_rps_freq_req = GEN6_GPU_FREQ_REQ;
+
setup_timer(dev_priv-gpu_error.hangcheck_timer,
i915_hangcheck_elapsed,
(unsigned long) dev);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3ff34c4..4998d6b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -529,6 +529,9 @@ enum punit_power_well {
#define CHV_FB_RPE_FREQ_SHIFT 8
#define CHV_FB_RPE_FREQ_MASK 0xff
+#define CHV_GPU_FREQ_REQ 2
+#define GEN6_GPU_FREQ_REQ 1
+
#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
#define FB_GFX_MAX_FREQ_FUSE_MASK0x07f8
--
1.9.1
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[Intel-gfx] [PATCH 07/10] drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0
From: Ville Syrjälä ville.syrj...@linux.intel.com Skip __gen6_gt_wait_for_thread_c0() on CHV. Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_uncore.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index d1a8c72..b719c51 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -229,8 +229,8 @@ static void __vlv_force_wake_get(struct drm_i915_private *dev_priv, } /* WaRsForcewakeWaitTC0:vlv */ - __gen6_gt_wait_for_thread_c0(dev_priv); - + if (!IS_CHERRYVIEW(dev_priv-dev)) + __gen6_gt_wait_for_thread_c0(dev_priv); } static void __vlv_force_wake_put(struct drm_i915_private *dev_priv, -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/10] drm/i915/chv: Enable RPS (Turbo) for Cherryview
From: Deepak S deepa...@linux.intel.com
v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
v3: Mass rename of the dev_priv-rps variables in upstream.
v4: Rebase against latest code. (Deepak)
Signed-off-by: Deepak S deepa...@linux.intel.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 10
drivers/gpu/drm/i915/intel_pm.c | 95 ++-
drivers/gpu/drm/i915/intel_sideband.c | 15 ++
4 files changed, 120 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5f4f631..e70a9f0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2552,6 +2552,7 @@ int sandybridge_pcode_write(struct drm_i915_private
*dev_priv, u8 mbox, u32 val)
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
+u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b4074fd..3ff34c4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -475,6 +475,7 @@
#define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
#define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
+#define CHV_IOSF_PORT_NC 0x04
/* See configdb bunit SB addr map */
#define BUNIT_REG_BISOC0x11
@@ -520,6 +521,14 @@ enum punit_power_well {
#define PUNIT_FUSE_BUS20xf6 /* bits 47:40 */
#define PUNIT_FUSE_BUS10xf5 /* bits 55:48 */
+#define CHV_IOSF_NC_FB_GFX_FREQ_FUSE 0xdb
+#define CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT 16
+#define CHV_FB_GFX_MAX_FREQ_FUSE_MASK 0xff
+
+#define CHV_IOSF_NC_FB_GFX_RPE_FUSE0xdf
+#define CHV_FB_RPE_FREQ_SHIFT 8
+#define CHV_FB_RPE_FREQ_MASK 0xff
+
#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
#define FB_GFX_MAX_FREQ_FUSE_MASK0x07f8
@@ -747,6 +756,7 @@ enum punit_power_well {
#define SANDYBRIDGE_FENCE_PITCH_SHIFT32
#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
+
/* control register for cpu gtt access */
#define TILECTL0x101000
#define TILECTL_SWZCTL (1 0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f0359b6..dedbdf3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3690,6 +3690,38 @@ void gen6_update_ring_freq(struct drm_device *dev)
mutex_unlock(dev_priv-rps.hw_lock);
}
+int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rp0;
+
+ val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
+
+ rp0 = (val CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT)
+ CHV_FB_GFX_MAX_FREQ_FUSE_MASK;
+
+ return rp0;
+}
+
+static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rpe;
+
+ val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_RPE_FUSE);
+ rpe = (val CHV_FB_RPE_FREQ_SHIFT) CHV_FB_RPE_FREQ_MASK;
+
+ return rpe;
+}
+
+int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rpn;
+
+ val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
+ rpn = (val CHV_FB_RPE_FREQ_SHIFT) CHV_FB_RPE_FREQ_MASK;
+
+ return rpn;
+}
+
int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
{
u32 val, rp0;
@@ -3847,7 +3879,36 @@ static void valleyview_init_gt_powersave(struct
drm_device *dev)
static void cherryview_init_gt_powersave(struct drm_device *dev)
{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
cherryview_setup_pctx(dev);
+
+ mutex_lock(dev_priv-rps.hw_lock);
+
+ dev_priv-rps.max_freq = cherryview_rps_max_freq(dev_priv);
+ dev_priv-rps.rp0_freq = dev_priv-rps.max_freq;
+ DRM_DEBUG_DRIVER(max GPU freq: %d MHz (%u)\n,
+vlv_gpu_freq(dev_priv, dev_priv-rps.max_freq),
+dev_priv-rps.max_freq);
+
+ dev_priv-rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
+ DRM_DEBUG_DRIVER(RPe GPU freq: %d MHz (%u)\n,
+vlv_gpu_freq(dev_priv, dev_priv-rps.efficient_freq),
+dev_priv-rps.efficient_freq);
+
+ dev_priv-rps.min_freq = cherryview_rps_min_freq(dev_priv
[Intel-gfx] [PATCH 09/10] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
From: Deepak S deepa...@linux.intel.com
Signed-off-by: Deepak S deepa...@linux.intel.com
[vsyrjala: Fix merge fubmle where the code ended up in
g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Acked-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index dedbdf3..0d9b831 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3985,7 +3985,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
GEN6_RP_UP_BUSY_AVG |
GEN6_RP_DOWN_IDLE_AVG);
+ /* ToDo: Update the mem freq based on latest spec [CHV]*/
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ switch ((val 6) 3) {
+ case 0:
+ case 1:
+ case 2:
+ dev_priv-mem_freq = 1600;
+ break;
+ case 3:
+ dev_priv-mem_freq = 2000;
+ break;
+ }
DRM_DEBUG_DRIVER(GPLL enabled? %s\n, val 0x10 ? yes : no);
DRM_DEBUG_DRIVER(GPU status: 0x%08x\n, val);
--
1.9.1
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[Intel-gfx] [PATCH 05/10] drm/i915/chv: Streamline CHV forcewake stuff
From: Deepak S deepa...@linux.intel.com
Streamline the CHV forcewake functions just like was done for VLV.
This will also fix a bug in accessing the common well registers,
where we'd end up trying to wake up the wells too many times
since we'd call force_wake_get/put twice per register access, with
FORCEFAKE_ALL both times.
v2: Re-factor CHV/VLV Forcewake offsets (Ben)
Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_uncore.c | 148
1 file changed, 66 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 4f1f199..d1a8c72 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -484,41 +484,43 @@ void assert_force_wake_inactive(struct drm_i915_private
*dev_priv)
#define NEEDS_FORCE_WAKE(dev_priv, reg) \
((reg) 0x4 (reg) != FORCEWAKE)
+#define REG_RANGE(reg, start, end) ((reg) = (start) (reg) (end))
+
#define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
- (((reg) = 0x2000 (reg) 0x4000) ||\
- ((reg) = 0x5000 (reg) 0x8000) ||\
- ((reg) = 0xB000 (reg) 0x12000) ||\
- ((reg) = 0x2E000 (reg) 0x3))
+ (REG_RANGE((reg), 0x2000, 0x4000) || \
+REG_RANGE((reg), 0x5000, 0x8000) || \
+REG_RANGE((reg), 0xB000, 0x12000) || \
+REG_RANGE((reg), 0x2E000, 0x3))
-#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\
- (((reg) = 0x12000 (reg) 0x14000) ||\
- ((reg) = 0x22000 (reg) 0x24000) ||\
- ((reg) = 0x3 (reg) 0x4))
+#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
+ (REG_RANGE((reg), 0x12000, 0x14000) || \
+REG_RANGE((reg), 0x22000, 0x24000) || \
+REG_RANGE((reg), 0x3, 0x4))
#define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
- (((reg) = 0x2000 (reg) 0x4000) ||\
- ((reg) = 0x5000 (reg) 0x8000) ||\
- ((reg) = 0x8300 (reg) 0x8500) ||\
- ((reg) = 0xB000 (reg) 0xC000) ||\
- ((reg) = 0xE000 (reg) 0xE800))
-
-#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)\
- (((reg) = 0x8800 (reg) 0x8900) ||\
- ((reg) = 0xD000 (reg) 0xD800) ||\
- ((reg) = 0x12000 (reg) 0x14000) ||\
- ((reg) = 0x1A000 (reg) 0x1C000) ||\
- ((reg) = 0x1E800 (reg) 0x1EA00) ||\
- ((reg) = 0x3 (reg) 0x4))
-
-#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)\
- (((reg) = 0x4000 (reg) 0x5000) ||\
- ((reg) = 0x8000 (reg) 0x8300) ||\
- ((reg) = 0x8500 (reg) 0x8600) ||\
- ((reg) = 0x9000 (reg) 0xB000) ||\
- ((reg) = 0xC000 (reg) 0xc800) ||\
- ((reg) = 0xF000 (reg) 0x1) ||\
- ((reg) = 0x14000 (reg) 0x14400) ||\
- ((reg) = 0x22000 (reg) 0x24000))
+ (REG_RANGE((reg), 0x2000, 0x4000) || \
+REG_RANGE((reg), 0x5000, 0x8000) || \
+REG_RANGE((reg), 0x8300, 0x8500) || \
+REG_RANGE((reg), 0xB000, 0xC000) || \
+REG_RANGE((reg), 0xE000, 0xE800))
+
+#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
+ (REG_RANGE((reg), 0x8800, 0x8900) || \
+REG_RANGE((reg), 0xD000, 0xD800) || \
+REG_RANGE((reg), 0x12000, 0x14000) || \
+REG_RANGE((reg), 0x1A000, 0x1C000) || \
+REG_RANGE((reg), 0x1E800, 0x1EA00) || \
+REG_RANGE((reg), 0x3, 0x4))
+
+#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
+ (REG_RANGE((reg), 0x4000, 0x5000) || \
+REG_RANGE((reg), 0x8000, 0x8300) || \
+REG_RANGE((reg), 0x8500, 0x8600) || \
+REG_RANGE((reg), 0x9000, 0xB000) || \
+REG_RANGE((reg), 0xC000, 0xC800) || \
+REG_RANGE((reg), 0xF000, 0x1) || \
+REG_RANGE((reg), 0x14000, 0x14400) || \
+REG_RANGE((reg), 0x22000, 0x24000))
static void
ilk_dummy_write(struct drm_i915_private *dev_priv)
@@ -618,33 +620,23 @@ static u##x \
chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
unsigned fwengine = 0; \
REG_READ_HEADER(x); \
- if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
- fwengine = FORCEWAKE_RENDER; \
- else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
- fwengine = FORCEWAKE_MEDIA; \
- else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
- fwengine = FORCEWAKE_ALL; \
- if (FORCEWAKE_RENDER fwengine) { \
- if (dev_priv-uncore.fw_rendercount++ == 0) \
- (dev_priv)-uncore.funcs.force_wake_get(dev_priv, \
- fwengine); \
- } \
- if (FORCEWAKE_MEDIA fwengine) { \
- if (dev_priv-uncore.fw_mediacount++ == 0) \
- (dev_priv)-uncore.funcs.force_wake_get(dev_priv, \
- fwengine
[Intel-gfx] [PATCH 08/10] drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV
From: Ville Syrjälä ville.syrj...@linux.intel.com CHV uses the gen8 shadow register mechanism so we shouldn't be checking the GT FIFO status. This effectively removes the posting read, so add an explicit posting read using FORCEWAKE_ACK_VLV (which is what use in vlv_forcewake_reset()). Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_uncore.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index b719c51..fa6e01e 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -248,9 +248,10 @@ static void __vlv_force_wake_put(struct drm_i915_private *dev_priv, __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); - /* The below doubles as a POSTING_READ */ - gen6_gt_check_fifodbg(dev_priv); - + /* something from same cacheline, but !FORCEWAKE_VLV */ + __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); + if (!IS_CHERRYVIEW(dev_priv-dev)) + gen6_gt_check_fifodbg(dev_priv); } static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 04/10] drm/i915/chv: Added CHV specific register read and write
Thanks Ben. Apologies for delayed response.
I am incorporating the review comment changes next set of patch review.
On Saturday 26 April 2014 03:24 AM, Ben Widawsky wrote:
On Mon, Apr 21, 2014 at 01:34:08PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Support to individually control Media/Render well based on the register access.
Add CHV specific write function to habdle difference between registers
that are sadowed vs those that need forcewake even for writes.
v2: Drop write FIFO for CHV and add comman well forcewake (Ville)
v3: Fix for decrementing fw count in chv read/write. (Deepak)
Signed-off-by: Deepak S deepa...@linux.intel.com
[vsyrjala: Move the register range macros into intel_uncore.c]
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
I left some comments on the first sending of this patch, and it's not
clear if you ignored them intentionally or not. Inquiring minds would
like to know.
I'll repeat some of the ones I feel are more important below.
---
drivers/gpu/drm/i915/intel_uncore.c | 139 +---
1 file changed, 131 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 2a72bab..11741e4 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -495,6 +495,31 @@ void assert_force_wake_inactive(struct drm_i915_private
*dev_priv)
((reg) = 0x22000 (reg) 0x24000) ||\
((reg) = 0x3 (reg) 0x4))
+#define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
+ (((reg) = 0x2000 (reg) 0x4000) ||\
+ ((reg) = 0x5000 (reg) 0x8000) ||\
+ ((reg) = 0x8300 (reg) 0x8500) ||\
+ ((reg) = 0xB000 (reg) 0xC000) ||\
+ ((reg) = 0xE000 (reg) 0xE800))
+
+#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)\
+ (((reg) = 0x8800 (reg) 0x8900) ||\
+ ((reg) = 0xD000 (reg) 0xD800) ||\
+ ((reg) = 0x12000 (reg) 0x14000) ||\
+ ((reg) = 0x1A000 (reg) 0x1C000) ||\
+ ((reg) = 0x1E800 (reg) 0x1EA00) ||\
+ ((reg) = 0x3 (reg) 0x4))
+
+#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)\
+ (((reg) = 0x4000 (reg) 0x5000) ||\
+ ((reg) = 0x8000 (reg) 0x8300) ||\
+ ((reg) = 0x8500 (reg) 0x8600) ||\
+ ((reg) = 0x9000 (reg) 0xB000) ||\
+ ((reg) = 0xC000 (reg) 0xc800) ||\
+ ((reg) = 0xF000 (reg) 0x1) ||\
+ ((reg) = 0x14000 (reg) 0x14400) ||\
+ ((reg) = 0x22000 (reg) 0x24000))
+
static void
ilk_dummy_write(struct drm_i915_private *dev_priv)
{
@@ -588,7 +613,48 @@ vlv_read##x(struct drm_i915_private *dev_priv, off_t reg,
bool trace) { \
REG_READ_FOOTER; \
}
+#define __chv_read(x) \
+static u##x \
+chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
+ unsigned fwengine = 0; \
+ REG_READ_HEADER(x); \
+ if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
+ fwengine = FORCEWAKE_RENDER; \
+ } \
+ else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
+ fwengine = FORCEWAKE_MEDIA; \
+ } \
+ else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
+ fwengine = FORCEWAKE_ALL; \
+ } \
These don't following linux kernel coding style
+ if (FORCEWAKE_RENDER fwengine) { \
+ if (dev_priv-uncore.fw_rendercount++ == 0) \
+ (dev_priv)-uncore.funcs.force_wake_get(dev_priv, \
+ fwengine); \
+ } \
+ if (FORCEWAKE_MEDIA fwengine) { \
+ if (dev_priv-uncore.fw_mediacount++ == 0) \
+ (dev_priv)-uncore.funcs.force_wake_get(dev_priv, \
+ fwengine); \
+ } \
+ val = __raw_i915_read##x(dev_priv, reg); \
+ if (FORCEWAKE_RENDER fwengine) { \
+ if (--dev_priv-uncore.fw_rendercount == 0) \
+ (dev_priv)-uncore.funcs.force_wake_put(dev_priv, \
+ fwengine); \
+ } \
+ if (FORCEWAKE_MEDIA fwengine) { \
+ if (--dev_priv-uncore.fw_mediacount == 0) \
+ (dev_priv)-uncore.funcs.force_wake_put(dev_priv, \
+ fwengine); \
+ } \
+ REG_READ_FOOTER; \
+}
It seems like it makes a lot more sense to pass register offset to
force_wake_put() and let the logic occur there instead of making a big
ugly macro. We can cheat and use the existing functions since fw_engine
was defined as an int, and the register range fits within that.
+__chv_read(8)
+__chv_read(16)
+__chv_read(32)
+__chv_read(64)
__vlv_read(8)
__vlv_read(16)
__vlv_read(32)
@@ -606,6 +672,7 @@ __gen4_read(16)
__gen4_read(32)
__gen4_read(64)
+#undef __chv_read
#undef __vlv_read
#undef
Re: [Intel-gfx] [PATCH v3] drm/i915: Add boot paramter to control rps boost at boot time.
On Monday 28 April 2014 08:42 PM, Daniel Vetter wrote: On Mon, Apr 28, 2014 at 4:47 PM, deepa...@linux.intel.com wrote: From: Deepak S deepa...@linux.intel.com We are adding a module paramter to control rps boost. By default, we enable the boost for better performace. Based on the need (perf/power) we can either enable/disable. v2: Addressed rps default comment (Jani) v3: Use bool to represent the boot parameter (Ville). Signed-off-by: Deepak S deepa...@linux.intel.com Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com I'm still unhappy about this since it feels like cheating in benchmarks and it gives me the impression that you guys frob this at runtime on Android ;-) A few more ideas: 1. light-boost: We add some hysteris (either time or whether we're still above rpe or something like that) and don't boost if this is the case. I expect that we won't be able to have the full boost benefits without the downside. 2. eco-boost. We try to boost just enough to not miss the next frame. For that the app needs to tell us (with two new execbuf flag) whether it hit or missed the last deadline. Once an app used those flags for the first time we decrease the boost target freq once per HIT_DEADLINE and until we get the first MISS_DEADLINE. The we only try to sporadically test the limit again. TCP flow control theory might be interesting for copying ideas. 3. runtime-boost-control. The workloads with very predictable regular loads seem to be known. We can just add a new execbuf NO_BOOST flag which libva uses on all execbufs but the first one (since we don't want to drop the first frame really). Approach 3 should be the simplest to implement and also the simplest to demonstrate in the open-source libva (since that's always a merge criteria). Aside: If you really use this at runtime then you essentially create a new ABI with this patch. Which means we need open-source userspace for it anyway. -Daniel Thanks for the review. Agreed. option 3 is better. I will work on this. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3] drm/i915: Add boot paramter to control rps boost at boot time.
From: Deepak S deepa...@linux.intel.com
We are adding a module paramter to control rps boost. By default, we
enable the boost for better performace. Based on the need (perf/power)
we can either enable/disable.
v2: Addressed rps default comment (Jani)
v3: Use bool to represent the boot parameter (Ville).
Signed-off-by: Deepak S deepa...@linux.intel.com
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/i915_gem.c| 2 +-
drivers/gpu/drm/i915/i915_params.c | 5 +
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e81feab..6136aab 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1945,6 +1945,7 @@ struct i915_params {
bool reset;
bool disable_display;
bool disable_vtd_wa;
+ bool enable_rps_boost;
};
extern struct i915_params i915 __read_mostly;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b00a77e..f2b3262 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1049,7 +1049,7 @@ static int __wait_seqno(struct intel_ring_buffer *ring,
u32 seqno,
timeout_expire = timeout ? jiffies +
timespec_to_jiffies_timeout(timeout) : 0;
- if (INTEL_INFO(dev)-gen = 6 can_wait_boost(file_priv)) {
+ if (INTEL_INFO(dev)-gen = 6 can_wait_boost(file_priv)
i915.enable_rps_boost) {
gen6_rps_boost(dev_priv);
if (file_priv)
mod_delayed_work(dev_priv-wq,
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index d05a2af..b51da7c 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -48,6 +48,7 @@ struct i915_params i915 __read_mostly = {
.disable_display = 0,
.enable_cmd_parser = 1,
.disable_vtd_wa = 0,
+ .enable_rps_boost = true,
};
module_param_named(modeset, i915.modeset, int, 0400);
@@ -156,3 +157,7 @@ MODULE_PARM_DESC(disable_vtd_wa, Disable all VT-d
workarounds (default: false)
module_param_named(enable_cmd_parser, i915.enable_cmd_parser, int, 0600);
MODULE_PARM_DESC(enable_cmd_parser,
Enable command parsing (1=enabled [default], 0=disabled));
+
+module_param_named(enable_rps_boost, i915.enable_rps_boost, bool, 0600);
+MODULE_PARM_DESC(enable_rps_boost,
+Enable/Disable boost RPS frequency (default: true));
--
1.8.5.2
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[Intel-gfx] [PATCH v6] drm/i915/vlv: WA for Turbo and RC6 to work together.
From: Deepak S deepa...@linux.intel.com
With RC6 enabled, BYT has an HW issue in determining the right
Gfx busyness.
WA for Turbo + RC6: Use SW based Gfx busy-ness detection to decide
on increasing/decreasing the freq. This logic will monitor C0
counters of render/media power-wells over EI period and takes
necessary action based on these values
v2: Refactor duplicate code. (Ville)
v3: Reformat the comments. (Ville)
v4: Enable required counters and remove unwanted code (Ville)
v5: Added frequency change acceleration support and remove kernel-doc
style comments. (Ville)
v6: Updated comment section and Fix w/a comment. (Ville)
Signed-off-by: Deepak S deepa...@linux.intel.com
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 15 +
drivers/gpu/drm/i915/i915_irq.c | 133 +++-
drivers/gpu/drm/i915/i915_reg.h | 11
drivers/gpu/drm/i915/intel_pm.c | 12 +++-
4 files changed, 167 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6136aab..5251946 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -819,6 +819,12 @@ struct i915_suspend_saved_registers {
u32 savePCH_PORT_HOTPLUG;
};
+struct intel_rps_ei_calc {
+ u32 cz_ts_ei;
+ u32 render_ei_c0;
+ u32 media_ei_c0;
+};
+
struct intel_gen6_power_mgmt {
/* work and pm_iir are protected by dev_priv-irq_lock */
struct work_struct work;
@@ -843,6 +849,8 @@ struct intel_gen6_power_mgmt {
u8 rp1_freq;/* less than RP0 power/freqency */
u8 rp0_freq;/* Non-overclocked max frequency. */
+ u32 ei_interrupt_count;
+
int last_adj;
enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
@@ -1414,6 +1422,13 @@ struct drm_i915_private {
/* gen6+ rps state */
struct intel_gen6_power_mgmt rps;
+ /* rps wa up ei calculation */
+ struct intel_rps_ei_calc rps_up_ei;
+
+ /* rps wa down ei calculation */
+ struct intel_rps_ei_calc rps_down_ei;
+
+
/* ilk-only ips/rps state. Everything in here is protected by the global
* mchdev_lock in intel_pm.c */
struct intel_ilk_power_mgmt ips;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2446e61..7d2efc8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1116,6 +1116,131 @@ static void notify_ring(struct drm_device *dev,
i915_queue_hangcheck(dev);
}
+static u32 vlv_c0_residency(struct drm_i915_private *dev_priv,
+ struct intel_rps_ei_calc *rps_ei)
+{
+ u32 cz_ts, cz_freq_khz;
+ u32 render_count, media_count;
+ u32 elapsed_render, elapsed_media, elapsed_time;
+ u32 residency = 0;
+
+ cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
+ cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv-mem_freq * 1000, 4);
+
+ render_count = I915_READ(VLV_RENDER_C0_COUNT_REG);
+ media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG);
+
+ if (rps_ei-cz_ts_ei == 0) {
+ rps_ei-cz_ts_ei = cz_ts;
+ rps_ei-render_ei_c0 = render_count;
+ rps_ei-media_ei_c0 = media_count;
+
+ return dev_priv-rps.cur_freq;
+ }
+
+ elapsed_time = cz_ts - rps_ei-cz_ts_ei;
+ rps_ei-cz_ts_ei = cz_ts;
+
+ elapsed_render = render_count - rps_ei-render_ei_c0;
+ rps_ei-render_ei_c0 = render_count;
+
+ elapsed_media = media_count - rps_ei-media_ei_c0;
+ rps_ei-media_ei_c0 = media_count;
+
+ /* Convert all the counters into common unit of milli sec */
+ elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC;
+ elapsed_render /= cz_freq_khz;
+ elapsed_media /= cz_freq_khz;
+
+ /*
+* Calculate overall C0 residency percentage
+* only if elapsed time is non zero
+*/
+ if (elapsed_time) {
+ residency =
+ ((max(elapsed_render, elapsed_media) * 100)
+ / elapsed_time);
+ }
+
+ return residency;
+}
+
+/**
+ * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU
+ * busy-ness calculated from C0 counters of render media power wells
+ * @dev_priv: DRM device private
+ *
+ */
+static u32 vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv)
+{
+ u32 residency_C0_up = 0, residency_C0_down = 0;
+ u8 new_delay, adj;
+
+ dev_priv-rps.ei_interrupt_count++;
+
+ WARN_ON(!mutex_is_locked(dev_priv-rps.hw_lock));
+
+
+ if (dev_priv-rps_up_ei.cz_ts_ei == 0) {
+ vlv_c0_residency(dev_priv, dev_priv-rps_up_ei);
+ vlv_c0_residency(dev_priv, dev_priv-rps_down_ei);
+ return dev_priv-rps.cur_freq;
+ }
+
+
+ /*
+* To down throttle, C0 residency should be less than down
Re: [Intel-gfx] [PATCH 03/10] drm/i915/chv: Enable Render Standby (RC6) for Cheeryview
On Monday 28 April 2014 08:15 PM, Daniel Vetter wrote:
On Mon, Apr 28, 2014 at 05:29:46PM +0300, Imre Deak wrote:
+static void cherryview_setup_pctx(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ unsigned long pctx_paddr;
+ struct i915_gtt *gtt = dev_priv-gtt;
+ u32 pcbr;
+ int pctx_size = 32*1024;
+
+ pcbr = I915_READ(VLV_PCBR);
+ if ((pcbr VLV_PCBR_ADDR_SHIFT) == 0) {
+ /*
+* From the Gunit register HAS:
+* The Gfx driver is expected to program this register and
ensure
+* proper allocation within Gfx stolen memory. For example,
this
+* register should be programmed such than the PCBR range does
not
+* overlap with other relevant ranges.
+*/
+ pctx_paddr = (dev_priv-mm.stolen_base + gtt-stolen_size -
pctx_size);
This area should be reserved.
We've had a really lengthy discussion internally about the bios-reserved
chunk in stolen. It was stalled due to (imo unjustified) fear to leak
information what the bios actually uses this for.
If we need to reserve more of stolen than we currently do we need to pick
up that approach again instead of adding more bandaids.
-Daniel
Agreed. Will change accordingly.
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Re: [Intel-gfx] [PATCH 03/10] drm/i915/chv: Enable Render Standby (RC6) for Cheeryview
Thanks for the review. I will address the comments
On Saturday 26 April 2014 03:12 AM, Ben Widawsky wrote:
On Mon, Apr 21, 2014 at 01:34:07PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
v3: Fix PCBR condition check during CHV RC6 Enable flag set
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 100 +++-
2 files changed, 99 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b951d61..7090b42 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5134,6 +5134,7 @@ enum punit_power_well {
#define GEN6_GT_GFX_RC6 0x138108
#define GEN6_GT_GFX_RC6p 0x13810C
#define GEN6_GT_GFX_RC6pp 0x138110
+#define VLV_PCBR_ADDR_SHIFT12
#define GEN6_PCODE_MAILBOX 0x138124
#define GEN6_PCODE_READY(131)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f3c5bce..421a4cc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3264,6 +3264,18 @@ static void gen6_disable_rps(struct drm_device *dev)
gen6_disable_rps_interrupts(dev);
}
+static void cherryview_disable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ I915_WRITE(GEN6_RC_CONTROL, 0);
+
+ if (dev_priv-vlv_pctx) {
+ drm_gem_object_unreference(dev_priv-vlv_pctx-base);
+ dev_priv-vlv_pctx = NULL;
+ }
+}
+
static void valleyview_disable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -3642,6 +3654,28 @@ static void valleyview_check_pctx(struct
drm_i915_private *dev_priv)
dev_priv-vlv_pctx-stolen-start);
}
+static void cherryview_setup_pctx(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ unsigned long pctx_paddr;
+ struct i915_gtt *gtt = dev_priv-gtt;
+ u32 pcbr;
+ int pctx_size = 32*1024;
+
+ pcbr = I915_READ(VLV_PCBR);
+ if ((pcbr VLV_PCBR_ADDR_SHIFT) == 0) {
+ /*
+* From the Gunit register HAS:
+* The Gfx driver is expected to program this register and
ensure
+* proper allocation within Gfx stolen memory. For example,
this
+* register should be programmed such than the PCBR range does
not
+* overlap with other relevant ranges.
+*/
+ pctx_paddr = (dev_priv-mm.stolen_base + gtt-stolen_size -
pctx_size);
+ I915_WRITE(VLV_PCBR, pctx_paddr);
+ }
+}
+
Is there a reason we did not follow the same idioms as Valleyview?
Shouldn't we be building a stolen object like we do there, and then
using that?
Furthermore, we need to make sure we make the stolen allocator aware for
the case where pcbr is not zero, like we do for valleyview.
I think the best solution here is to try to combine the valleyview and
cherryview logic for this function. Extract out size, and most of the
rest looks pretty similar.
For enabling, I am fine with it as is though provided it's hidden by
preliminary flag.
static void valleyview_setup_pctx(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -3697,6 +3731,61 @@ static void valleyview_cleanup_pctx(struct drm_device
*dev)
dev_priv-vlv_pctx = NULL;
}
+static void cherryview_enable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_ring_buffer *ring;
+ u32 gtfifodbg, rc6_mode = 0, pcbr;
+ int i;
+
+ WARN_ON(!mutex_is_locked(dev_priv-rps.hw_lock));
+
+ if ((gtfifodbg = I915_READ(GTFIFODBG))) {
+ DRM_DEBUG_DRIVER(GT fifo had a previous error %x\n,
+gtfifodbg);
+ I915_WRITE(GTFIFODBG, gtfifodbg);
+ }
+
+ cherryview_setup_pctx(dev);
+
+ /* 1a 1b: Get forcewake during program sequence. Although the driver
+* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
+ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+
+ /* 2a: Program RC6 thresholds.*/
+ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 16);
+ I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
+ I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
+
+ for_each_ring(ring, dev_priv, i)
+ I915_WRITE(RING_MAX_IDLE(ring-mmio_base), 10);
+
+ I915_WRITE(GEN6_RC6_THRESHOLD, 5); /* 50/125ms per EI */
+
+ /* allows RC6 residency counter to work */
+ I915_WRITE
Re: [Intel-gfx] [PATCH 03/10] drm/i915/chv: Enable Render Standby (RC6) for Cheeryview
Thanks for the review. I will address the comments
On Monday 28 April 2014 07:59 PM, Imre Deak wrote:
On Mon, 2014-04-21 at 13:34 +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
v3: Fix PCBR condition check during CHV RC6 Enable flag set
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 100 +++-
2 files changed, 99 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b951d61..7090b42 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5134,6 +5134,7 @@ enum punit_power_well {
#define GEN6_GT_GFX_RC6 0x138108
#define GEN6_GT_GFX_RC6p 0x13810C
#define GEN6_GT_GFX_RC6pp 0x138110
+#define VLV_PCBR_ADDR_SHIFT12
#define GEN6_PCODE_MAILBOX 0x138124
#define GEN6_PCODE_READY(131)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f3c5bce..421a4cc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3264,6 +3264,18 @@ static void gen6_disable_rps(struct drm_device *dev)
gen6_disable_rps_interrupts(dev);
}
+static void cherryview_disable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ I915_WRITE(GEN6_RC_CONTROL, 0);
+
+ if (dev_priv-vlv_pctx) {
+ drm_gem_object_unreference(dev_priv-vlv_pctx-base);
+ dev_priv-vlv_pctx = NULL;
+ }
+}
+
static void valleyview_disable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -3642,6 +3654,28 @@ static void valleyview_check_pctx(struct
drm_i915_private *dev_priv)
dev_priv-vlv_pctx-stolen-start);
}
+static void cherryview_setup_pctx(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ unsigned long pctx_paddr;
+ struct i915_gtt *gtt = dev_priv-gtt;
+ u32 pcbr;
+ int pctx_size = 32*1024;
+
+ pcbr = I915_READ(VLV_PCBR);
+ if ((pcbr VLV_PCBR_ADDR_SHIFT) == 0) {
+ /*
+* From the Gunit register HAS:
+* The Gfx driver is expected to program this register and
ensure
+* proper allocation within Gfx stolen memory. For example,
this
+* register should be programmed such than the PCBR range does
not
+* overlap with other relevant ranges.
+*/
+ pctx_paddr = (dev_priv-mm.stolen_base + gtt-stolen_size -
pctx_size);
This area should be reserved.
+ I915_WRITE(VLV_PCBR, pctx_paddr);
+ }
+}
+
static void valleyview_setup_pctx(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -3697,6 +3731,61 @@ static void valleyview_cleanup_pctx(struct drm_device
*dev)
dev_priv-vlv_pctx = NULL;
}
+static void cherryview_enable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_ring_buffer *ring;
+ u32 gtfifodbg, rc6_mode = 0, pcbr;
+ int i;
+
+ WARN_ON(!mutex_is_locked(dev_priv-rps.hw_lock));
+
+ if ((gtfifodbg = I915_READ(GTFIFODBG))) {
+ DRM_DEBUG_DRIVER(GT fifo had a previous error %x\n,
+gtfifodbg);
+ I915_WRITE(GTFIFODBG, gtfifodbg);
+ }
+
+ cherryview_setup_pctx(dev);
This should be called from intel_init_gt_powersave().
+
+ /* 1a 1b: Get forcewake during program sequence. Although the driver
+* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
+ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+
+ /* 2a: Program RC6 thresholds.*/
+ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 16);
+ I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
+ I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
+
+ for_each_ring(ring, dev_priv, i)
+ I915_WRITE(RING_MAX_IDLE(ring-mmio_base), 10);
+
+ I915_WRITE(GEN6_RC6_THRESHOLD, 5); /* 50/125ms per EI */
+
+ /* allows RC6 residency counter to work */
+ I915_WRITE(VLV_COUNTER_CONTROL,
+ _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
+ VLV_MEDIA_RC6_COUNT_EN |
+ VLV_RENDER_RC6_COUNT_EN));
+
+ /* Todo: If BIOS has not configured PCBR
+* then allocate in BIOS Reserved */
+
+ /* For now we assume BIOS is allocating and populating the PCBR */
+ pcbr = I915_READ(VLV_PCBR);
+
+ DRM_DEBUG_DRIVER(PCBR offset : 0x
Re: [Intel-gfx] [PATCH 00/10] Enable RC6/Turbo on CHV
On Wednesday 23 April 2014 01:49 AM, Daniel Vetter wrote: On Mon, Apr 21, 2014 at 07:28:54PM +0530, Deepak S wrote: Hi Ville, let me know if you want some of other small patches to be squashed. Quick aside: Something seems to have gone with git send-email thread - the patches aren't in-reply-to the cover letter. No idea how that happened though ... -Daniel Not Sure :( I can resend the patches again Thanks Deepak On Monday 21 April 2014 01:23 PM, deepa...@linux.intel.com wrote: From: Deepak S deepa...@linux.intel.com Squashed some of the patches and created a new patch series. ToDo: Address the comments on some the patches. Changes will be shared in next series. Ben Widawsky (1): drm/i915/bdw: Implement a basic PM interrupt handler Deepak S (6): drm/i915: Enable PM Interrupts target via Display Interface. drm/i915/chv: Enable Render Standby (RC6) for Cheeryview drm/i915/chv: Added CHV specific register read and write drm/i915/chv: Enable RPS (Turbo) for Cheeryview drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating drm/i915/chv: Freq(opcode) request value for CHV. Ville Syrjälä (3): drm/i915/chv: Streamline CHV forcewake stuff drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0 drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV drivers/gpu/drm/i915/i915_drv.h | 10 ++ drivers/gpu/drm/i915/i915_irq.c | 79 +++- drivers/gpu/drm/i915/i915_reg.h | 13 ++ drivers/gpu/drm/i915/intel_drv.h | 2 + drivers/gpu/drm/i915/intel_pm.c | 231 +- drivers/gpu/drm/i915/intel_sideband.c | 15 +++ drivers/gpu/drm/i915/intel_uncore.c | 126 +-- 7 files changed, 455 insertions(+), 21 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 00/10] Enable RC6/Turbo on CHV
From: Deepak S deepa...@linux.intel.com Squashed some of the patches and created a new patch series. ToDo: Address the comments on some the patches. Changes will be shared in next series. Ben Widawsky (1): drm/i915/bdw: Implement a basic PM interrupt handler Deepak S (6): drm/i915: Enable PM Interrupts target via Display Interface. drm/i915/chv: Enable Render Standby (RC6) for Cheeryview drm/i915/chv: Added CHV specific register read and write drm/i915/chv: Enable RPS (Turbo) for Cheeryview drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating drm/i915/chv: Freq(opcode) request value for CHV. Ville Syrjälä (3): drm/i915/chv: Streamline CHV forcewake stuff drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0 drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV drivers/gpu/drm/i915/i915_drv.h | 10 ++ drivers/gpu/drm/i915/i915_irq.c | 79 +++- drivers/gpu/drm/i915/i915_reg.h | 13 ++ drivers/gpu/drm/i915/intel_drv.h | 2 + drivers/gpu/drm/i915/intel_pm.c | 231 +- drivers/gpu/drm/i915/intel_sideband.c | 15 +++ drivers/gpu/drm/i915/intel_uncore.c | 126 +-- 7 files changed, 455 insertions(+), 21 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 09/10] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
From: Deepak S deepa...@linux.intel.com
Signed-off-by: Deepak S deepa...@linux.intel.com
[vsyrjala: Fix merge fubmle where the code ended up in
g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b37d108..fdb66aa 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3831,7 +3831,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
GEN6_RP_UP_BUSY_AVG |
GEN6_RP_DOWN_IDLE_AVG);
+ /* ToDo: Update the mem freq based on latest spec [CHV]*/
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ switch ((val 6) 3) {
+ case 0:
+ case 1:
+ case 2:
+ dev_priv-mem_freq = 1600;
+ break;
+ case 3:
+ dev_priv-mem_freq = 2000;
+ break;
+ }
DRM_DEBUG_DRIVER(GPLL enabled? %s\n, val 0x10 ? yes : no);
DRM_DEBUG_DRIVER(GPU status: 0x%08x\n, val);
--
1.9.1
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[Intel-gfx] [PATCH 07/10] drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0
From: Ville Syrjälä ville.syrj...@linux.intel.com Skip __gen6_gt_wait_for_thread_c0() on CHV. Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_uncore.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index f1264e2..b0f0651 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -229,8 +229,8 @@ static void __vlv_force_wake_get(struct drm_i915_private *dev_priv, } /* WaRsForcewakeWaitTC0:vlv */ - __gen6_gt_wait_for_thread_c0(dev_priv); - + if (!IS_CHERRYVIEW(dev_priv-dev)) + __gen6_gt_wait_for_thread_c0(dev_priv); } static void __vlv_force_wake_put(struct drm_i915_private *dev_priv, -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/10] drm/i915/chv: Enable Render Standby (RC6) for Cheeryview
From: Deepak S deepa...@linux.intel.com
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
v3: Fix PCBR condition check during CHV RC6 Enable flag set
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 100 +++-
2 files changed, 99 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b951d61..7090b42 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5134,6 +5134,7 @@ enum punit_power_well {
#define GEN6_GT_GFX_RC60x138108
#define GEN6_GT_GFX_RC6p 0x13810C
#define GEN6_GT_GFX_RC6pp 0x138110
+#define VLV_PCBR_ADDR_SHIFT12
#define GEN6_PCODE_MAILBOX 0x138124
#define GEN6_PCODE_READY (131)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f3c5bce..421a4cc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3264,6 +3264,18 @@ static void gen6_disable_rps(struct drm_device *dev)
gen6_disable_rps_interrupts(dev);
}
+static void cherryview_disable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ I915_WRITE(GEN6_RC_CONTROL, 0);
+
+ if (dev_priv-vlv_pctx) {
+ drm_gem_object_unreference(dev_priv-vlv_pctx-base);
+ dev_priv-vlv_pctx = NULL;
+ }
+}
+
static void valleyview_disable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -3642,6 +3654,28 @@ static void valleyview_check_pctx(struct
drm_i915_private *dev_priv)
dev_priv-vlv_pctx-stolen-start);
}
+static void cherryview_setup_pctx(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ unsigned long pctx_paddr;
+ struct i915_gtt *gtt = dev_priv-gtt;
+ u32 pcbr;
+ int pctx_size = 32*1024;
+
+ pcbr = I915_READ(VLV_PCBR);
+ if ((pcbr VLV_PCBR_ADDR_SHIFT) == 0) {
+ /*
+* From the Gunit register HAS:
+* The Gfx driver is expected to program this register and
ensure
+* proper allocation within Gfx stolen memory. For example,
this
+* register should be programmed such than the PCBR range does
not
+* overlap with other relevant ranges.
+*/
+ pctx_paddr = (dev_priv-mm.stolen_base + gtt-stolen_size -
pctx_size);
+ I915_WRITE(VLV_PCBR, pctx_paddr);
+ }
+}
+
static void valleyview_setup_pctx(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -3697,6 +3731,61 @@ static void valleyview_cleanup_pctx(struct drm_device
*dev)
dev_priv-vlv_pctx = NULL;
}
+static void cherryview_enable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_ring_buffer *ring;
+ u32 gtfifodbg, rc6_mode = 0, pcbr;
+ int i;
+
+ WARN_ON(!mutex_is_locked(dev_priv-rps.hw_lock));
+
+ if ((gtfifodbg = I915_READ(GTFIFODBG))) {
+ DRM_DEBUG_DRIVER(GT fifo had a previous error %x\n,
+gtfifodbg);
+ I915_WRITE(GTFIFODBG, gtfifodbg);
+ }
+
+ cherryview_setup_pctx(dev);
+
+ /* 1a 1b: Get forcewake during program sequence. Although the driver
+* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
+ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+
+ /* 2a: Program RC6 thresholds.*/
+ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 16);
+ I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
+ I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
+
+ for_each_ring(ring, dev_priv, i)
+ I915_WRITE(RING_MAX_IDLE(ring-mmio_base), 10);
+
+ I915_WRITE(GEN6_RC6_THRESHOLD, 5); /* 50/125ms per EI */
+
+ /* allows RC6 residency counter to work */
+ I915_WRITE(VLV_COUNTER_CONTROL,
+ _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
+ VLV_MEDIA_RC6_COUNT_EN |
+ VLV_RENDER_RC6_COUNT_EN));
+
+ /* Todo: If BIOS has not configured PCBR
+* then allocate in BIOS Reserved */
+
+ /* For now we assume BIOS is allocating and populating the PCBR */
+ pcbr = I915_READ(VLV_PCBR);
+
+ DRM_DEBUG_DRIVER(PCBR offset : 0x%x\n, pcbr);
+
+ /* 3: Enable RC6 */
+ if ((intel_enable_rc6(dev) INTEL_RC6_ENABLE)
+ (pcbr VLV_PCBR_ADDR_SHIFT))
+ rc6_mode = GEN6_RC_CTL_EI_MODE(1) | VLV_RC_CTL_CTX_RST_PARALLEL
[Intel-gfx] [PATCH 02/10] drm/i915: Enable PM Interrupts target via Display Interface.
From: Deepak S deepa...@linux.intel.com
In BDW, Apart from unmasking up/down threshold interrupts. we need
to umask bit 32 of PM_INTRMASK to route interrupts to target via Display
Interface.
v2: Add (131) mask (Ville)
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c2dd436..b951d61 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5105,6 +5105,7 @@ enum punit_power_well {
#define GEN6_RC6p_THRESHOLD0xA0BC
#define GEN6_RC6pp_THRESHOLD 0xA0C0
#define GEN6_PMINTRMSK 0xA168
+#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (131)
#define GEN6_PMISR 0x44020
#define GEN6_PMIMR 0x44024 /* rps_lock */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3dccee6..f3c5bce 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3066,6 +3066,8 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private
*dev_priv, u8 val)
if (INTEL_INFO(dev_priv-dev)-gen = 7 !IS_HASWELL(dev_priv-dev))
mask |= GEN6_PM_RP_UP_EI_EXPIRED;
+ mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+
return ~mask;
}
--
1.9.1
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[Intel-gfx] [PATCH 06/10] drm/i915/chv: Streamline CHV forcewake stuff
From: Ville Syrjälä ville.syrj...@linux.intel.com
Streamline the CHV forcewake functions just like was done for VLV.
This will also fix a bug in accessing the common well registers,
where we'd end up trying to wake up the wells too many times
since we'd call force_wake_get/put twice per register access, with
FORCEFAKE_ALL both times.
Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_uncore.c | 88 ++---
1 file changed, 32 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 11741e4..f1264e2 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -619,35 +619,22 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg,
bool trace) { \
unsigned fwengine = 0; \
REG_READ_HEADER(x); \
if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
- fwengine = FORCEWAKE_RENDER; \
- } \
- else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
- fwengine = FORCEWAKE_MEDIA; \
- } \
- else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
- fwengine = FORCEWAKE_ALL; \
- } \
- if (FORCEWAKE_RENDER fwengine) { \
- if (dev_priv-uncore.fw_rendercount++ == 0) \
- (dev_priv)-uncore.funcs.force_wake_get(dev_priv, \
- fwengine); \
- } \
- if (FORCEWAKE_MEDIA fwengine) { \
- if (dev_priv-uncore.fw_mediacount++ == 0) \
- (dev_priv)-uncore.funcs.force_wake_get(dev_priv, \
- fwengine); \
+ if (dev_priv-uncore.fw_rendercount == 0) \
+ fwengine = FORCEWAKE_RENDER; \
+ } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
+ if (dev_priv-uncore.fw_mediacount == 0) \
+ fwengine = FORCEWAKE_MEDIA; \
+ } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
+ if (dev_priv-uncore.fw_rendercount == 0) \
+ fwengine |= FORCEWAKE_RENDER; \
+ if (dev_priv-uncore.fw_mediacount == 0) \
+ fwengine |= FORCEWAKE_MEDIA; \
} \
+ if (fwengine) \
+ dev_priv-uncore.funcs.force_wake_get(dev_priv, fwengine); \
val = __raw_i915_read##x(dev_priv, reg); \
- if (FORCEWAKE_RENDER fwengine) { \
- if (--dev_priv-uncore.fw_rendercount == 0) \
- (dev_priv)-uncore.funcs.force_wake_put(dev_priv, \
- fwengine); \
- } \
- if (FORCEWAKE_MEDIA fwengine) { \
- if (--dev_priv-uncore.fw_mediacount == 0) \
- (dev_priv)-uncore.funcs.force_wake_put(dev_priv, \
- fwengine); \
- } \
+ if (fwengine) \
+ dev_priv-uncore.funcs.force_wake_put(dev_priv, fwengine); \
REG_READ_FOOTER; \
}
@@ -781,38 +768,27 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t
reg, u##x val, bool trace
static void \
chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool
trace) { \
unsigned fwengine = 0; \
- bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \
+ bool shadowed = is_gen8_shadowed(dev_priv, reg); \
REG_WRITE_HEADER; \
- if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
- fwengine = FORCEWAKE_RENDER; \
- } \
- else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
- fwengine = FORCEWAKE_MEDIA; \
- } \
- else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
- fwengine = FORCEWAKE_ALL; \
- } \
- if (__needs_put (FORCEWAKE_RENDER fwengine)) { \
- if (dev_priv-uncore.fw_rendercount++ == 0) \
-
(dev_priv)-uncore.funcs.force_wake_get(dev_priv, \
-
fwengine); \
- } \
- if (__needs_put (FORCEWAKE_MEDIA fwengine)) { \
- if (dev_priv-uncore.fw_mediacount++ == 0) \
- (dev_priv)-uncore.funcs.force_wake_get(dev_priv, \
- fwengine); \
+ if (!shadowed) { \
+ if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
+ if (dev_priv-uncore.fw_rendercount == 0) \
+ fwengine = FORCEWAKE_RENDER; \
+ } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
+ if (dev_priv-uncore.fw_mediacount == 0) \
+ fwengine = FORCEWAKE_MEDIA; \
+ } else if
[Intel-gfx] [PATCH 08/10] drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV
From: Ville Syrjälä ville.syrj...@linux.intel.com CHV uses the gen8 shadow register mechanism so we shouldn't be checking the GT FIFO status. This effectively removes the posting read, so add an explicit posting read using FORCEWAKE_ACK_VLV (which is what use in vlv_forcewake_reset()). Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_uncore.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index b0f0651..7170506 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -248,9 +248,10 @@ static void __vlv_force_wake_put(struct drm_i915_private *dev_priv, __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); - /* The below doubles as a POSTING_READ */ - gen6_gt_check_fifodbg(dev_priv); - + /* something from same cacheline, but !FORCEWAKE_VLV */ + __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); + if (!IS_CHERRYVIEW(dev_priv-dev)) + gen6_gt_check_fifodbg(dev_priv); } static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/10] drm/i915/bdw: Implement a basic PM interrupt handler
From: Ben Widawsky benjamin.widaw...@intel.com
Almost all of it is reusable from the existing code. The primary
difference is we need to do even less in the interrupt handler, since
interrupts are not shared in the same way.
The patch is mostly a copy-paste of the existing snb+ code, with updates
to the relevant parts requiring changes to the interrupt handling. As
such it /should/ be relatively trivial. It's highly likely that I missed
some places where I need a gen8 version of the PM interrupts, but it has
become invisible to me by now.
This patch could probably be split into adding the new functions,
followed by actually handling the interrupts. Since the code is
currently disabled (and broken) I think the patch stands better by
itself.
v2: Move the commit about not touching the ringbuffer interrupt to the
snb_* function where it belongs (Rodrigo)
v3: Rebased on Paulo's runtime PM changes
v4: Not well validated, but rebase on
commit 730488b2eddded4497f63f70867b1256cd9e117c
Author: Paulo Zanoni paulo.r.zan...@intel.com
Date: Fri Mar 7 20:12:32 2014 -0300
drm/i915: kill dev_priv-pm.regsave
v5: Rebased on latest code base. (Deepak)
v6: Remove conflict markers, Unnecessary empty line and use right
IIR interrupt (Ville)
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 75 ++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 38 ++--
4 files changed, 112 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7a4d3ae..cf29668 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -248,6 +248,49 @@ static bool ivb_can_enable_err_int(struct drm_device *dev)
return true;
}
+/**
+ * bdw_update_pm_irq - update GT interrupt 2
+ * @dev_priv: driver private
+ * @interrupt_mask: mask of interrupt bits to update
+ * @enabled_irq_mask: mask of interrupt bits to enable
+ *
+ * Copied from the snb function, updated with relevant register offsets
+ */
+static void bdw_update_pm_irq(struct drm_i915_private *dev_priv,
+ uint32_t interrupt_mask,
+ uint32_t enabled_irq_mask)
+{
+ uint32_t new_val;
+
+ assert_spin_locked(dev_priv-irq_lock);
+
+ if (dev_priv-pm.irqs_disabled) {
+ WARN(1, IRQs disabled\n);
+ return;
+ }
+
+ new_val = dev_priv-pm_irq_mask;
+ new_val = ~interrupt_mask;
+ new_val |= (~enabled_irq_mask interrupt_mask);
+
+ if (new_val != dev_priv-pm_irq_mask) {
+ dev_priv-pm_irq_mask = new_val;
+ I915_WRITE(GEN8_GT_IMR(2), I915_READ(GEN8_GT_IMR(2)) |
+ dev_priv-pm_irq_mask);
+ POSTING_READ(GEN8_GT_IMR(2));
+ }
+}
+
+void bdw_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
+{
+ bdw_update_pm_irq(dev_priv, mask, mask);
+}
+
+void bdw_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
+{
+ bdw_update_pm_irq(dev_priv, mask, 0);
+}
+
static bool cpt_can_enable_serr_int(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -1126,8 +1169,12 @@ static void gen6_pm_rps_work(struct work_struct *work)
spin_lock_irq(dev_priv-irq_lock);
pm_iir = dev_priv-rps.pm_iir;
dev_priv-rps.pm_iir = 0;
- /* Make sure not to corrupt PMIMR state used by ringbuffer code */
- snb_enable_pm_irq(dev_priv, dev_priv-pm_rps_events);
+ if (IS_BROADWELL(dev_priv-dev))
+ bdw_enable_pm_irq(dev_priv, dev_priv-pm_rps_events);
+ else {
+ /* Make sure not to corrupt PMIMR state used by ringbuffer */
+ snb_enable_pm_irq(dev_priv, dev_priv-pm_rps_events);
+ }
spin_unlock_irq(dev_priv-irq_lock);
/* Make sure we didn't queue anything we're not going to process. */
@@ -1324,6 +1371,19 @@ static void snb_gt_irq_handler(struct drm_device *dev,
ivybridge_parity_error_irq_handler(dev, gt_iir);
}
+static void gen8_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
+{
+ if ((pm_iir dev_priv-pm_rps_events) == 0)
+ return;
+
+ spin_lock(dev_priv-irq_lock);
+ dev_priv-rps.pm_iir |= pm_iir dev_priv-pm_rps_events;
+ bdw_disable_pm_irq(dev_priv, pm_iir dev_priv-pm_rps_events);
+ spin_unlock(dev_priv-irq_lock);
+
+ queue_work(dev_priv-wq, dev_priv-rps.work);
+}
+
static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
struct drm_i915_private *dev_priv,
u32 master_ctl)
@@ -1359,6 +1419,17 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_device
*dev
[Intel-gfx] [PATCH 05/10] drm/i915/chv: Enable RPS (Turbo) for Cheeryview
From: Deepak S deepa...@linux.intel.com
v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
v3: Mass rename of the dev_priv-rps variables in upstream.
Signed-off-by: Deepak S deepa...@linux.intel.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 10 +
drivers/gpu/drm/i915/intel_pm.c | 82 ++-
drivers/gpu/drm/i915/intel_sideband.c | 15 +++
4 files changed, 107 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7d6acb4..ead2714 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2542,6 +2542,7 @@ int sandybridge_pcode_write(struct drm_i915_private
*dev_priv, u8 mbox, u32 val)
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
+u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7090b42..f3042bb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -475,6 +475,7 @@
#define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
#define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
+#define CHV_IOSF_PORT_NC 0x04
/* See configdb bunit SB addr map */
#define BUNIT_REG_BISOC0x11
@@ -520,6 +521,14 @@ enum punit_power_well {
#define PUNIT_FUSE_BUS20xf6 /* bits 47:40 */
#define PUNIT_FUSE_BUS10xf5 /* bits 55:48 */
+#define CHV_IOSF_NC_FB_GFX_FREQ_FUSE 0xdb
+#define CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT 16
+#define CHV_FB_GFX_MAX_FREQ_FUSE_MASK 0xff
+
+#define CHV_IOSF_NC_FB_GFX_RPE_FUSE0xdf
+#define CHV_FB_RPE_FREQ_SHIFT 8
+#define CHV_FB_RPE_FREQ_MASK 0xff
+
#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
#define FB_GFX_MAX_FREQ_FUSE_MASK0x07f8
@@ -747,6 +756,7 @@ enum punit_power_well {
#define SANDYBRIDGE_FENCE_PITCH_SHIFT32
#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
+
/* control register for cpu gtt access */
#define TILECTL0x101000
#define TILECTL_SWZCTL (1 0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 421a4cc..b37d108 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3615,6 +3615,38 @@ void gen6_update_ring_freq(struct drm_device *dev)
}
}
+int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rp0;
+
+ val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
+
+ rp0 = (val CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT)
+ CHV_FB_GFX_MAX_FREQ_FUSE_MASK;
+
+ return rp0;
+}
+
+static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rpe;
+
+ val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_RPE_FUSE);
+ rpe = (val CHV_FB_RPE_FREQ_SHIFT) CHV_FB_RPE_FREQ_MASK;
+
+ return rpe;
+}
+
+int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
+{
+ u32 val, rpn;
+
+ val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
+ rpn = (val CHV_FB_RPE_FREQ_SHIFT) CHV_FB_RPE_FREQ_MASK;
+
+ return rpn;
+}
+
int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
{
u32 val, rp0;
@@ -3735,7 +3767,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_ring_buffer *ring;
- u32 gtfifodbg, rc6_mode = 0, pcbr;
+ u32 gtfifodbg, val, rc6_mode = 0, pcbr;
int i;
WARN_ON(!mutex_is_locked(dev_priv-rps.hw_lock));
@@ -3783,6 +3815,54 @@ static void cherryview_enable_rps(struct drm_device *dev)
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
+ /* 4 Program defaults and thresholds for RPS*/
+ I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
+ I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+ I915_WRITE(GEN6_RP_UP_EI, 66000);
+ I915_WRITE(GEN6_RP_DOWN_EI, 35);
+
+ I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+
+ /* 5: Enable RPS */
+ I915_WRITE(GEN6_RP_CONTROL,
+ GEN6_RP_MEDIA_HW_NORMAL_MODE |
+ GEN6_RP_MEDIA_IS_GFX |
+ GEN6_RP_ENABLE |
+ GEN6_RP_UP_BUSY_AVG
[Intel-gfx] [PATCH 10/10] drm/i915/chv: Freq(opcode) request value for CHV.
From: Deepak S deepa...@linux.intel.com
On CHV, All the freq request should be even. S0, we need to make sure we
request the opcode accordingly.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 9 +
drivers/gpu/drm/i915/i915_irq.c | 4 ++--
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ead2714..5435d87 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2641,6 +2641,15 @@ timespec_to_jiffies_timeout(const struct timespec *value)
return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}
+/* rps/turbo related */
+static inline int i915_rps_freq_change(struct drm_device *dev)
+{
+ if (IS_CHERRYVIEW(dev))
+ return 2;
+
+ return 1;
+}
+
/*
* If you need to wait X milliseconds between events A and B, but event B
* doesn't happen exactly after event A, you record the timestamp (jiffies) of
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index cf29668..11538fe 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1190,7 +1190,7 @@ static void gen6_pm_rps_work(struct work_struct *work)
if (adj 0)
adj *= 2;
else
- adj = 1;
+ adj = i915_rps_freq_change(dev_priv-dev);
new_delay = dev_priv-rps.cur_freq + adj;
/*
@@ -1209,7 +1209,7 @@ static void gen6_pm_rps_work(struct work_struct *work)
if (adj 0)
adj *= 2;
else
- adj = -1;
+ adj = -1 * i915_rps_freq_change(dev_priv-dev);
new_delay = dev_priv-rps.cur_freq + adj;
} else { /* unknown event */
new_delay = dev_priv-rps.cur_freq;
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/10] drm/i915/chv: Added CHV specific register read and write
From: Deepak S deepa...@linux.intel.com
Support to individually control Media/Render well based on the register access.
Add CHV specific write function to habdle difference between registers
that are sadowed vs those that need forcewake even for writes.
v2: Drop write FIFO for CHV and add comman well forcewake (Ville)
v3: Fix for decrementing fw count in chv read/write. (Deepak)
Signed-off-by: Deepak S deepa...@linux.intel.com
[vsyrjala: Move the register range macros into intel_uncore.c]
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_uncore.c | 139 +---
1 file changed, 131 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 2a72bab..11741e4 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -495,6 +495,31 @@ void assert_force_wake_inactive(struct drm_i915_private
*dev_priv)
((reg) = 0x22000 (reg) 0x24000) ||\
((reg) = 0x3 (reg) 0x4))
+#define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
+ (((reg) = 0x2000 (reg) 0x4000) ||\
+ ((reg) = 0x5000 (reg) 0x8000) ||\
+ ((reg) = 0x8300 (reg) 0x8500) ||\
+ ((reg) = 0xB000 (reg) 0xC000) ||\
+ ((reg) = 0xE000 (reg) 0xE800))
+
+#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)\
+ (((reg) = 0x8800 (reg) 0x8900) ||\
+ ((reg) = 0xD000 (reg) 0xD800) ||\
+ ((reg) = 0x12000 (reg) 0x14000) ||\
+ ((reg) = 0x1A000 (reg) 0x1C000) ||\
+ ((reg) = 0x1E800 (reg) 0x1EA00) ||\
+ ((reg) = 0x3 (reg) 0x4))
+
+#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)\
+ (((reg) = 0x4000 (reg) 0x5000) ||\
+ ((reg) = 0x8000 (reg) 0x8300) ||\
+ ((reg) = 0x8500 (reg) 0x8600) ||\
+ ((reg) = 0x9000 (reg) 0xB000) ||\
+ ((reg) = 0xC000 (reg) 0xc800) ||\
+ ((reg) = 0xF000 (reg) 0x1) ||\
+ ((reg) = 0x14000 (reg) 0x14400) ||\
+ ((reg) = 0x22000 (reg) 0x24000))
+
static void
ilk_dummy_write(struct drm_i915_private *dev_priv)
{
@@ -588,7 +613,48 @@ vlv_read##x(struct drm_i915_private *dev_priv, off_t reg,
bool trace) { \
REG_READ_FOOTER; \
}
+#define __chv_read(x) \
+static u##x \
+chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
+ unsigned fwengine = 0; \
+ REG_READ_HEADER(x); \
+ if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
+ fwengine = FORCEWAKE_RENDER; \
+ } \
+ else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
+ fwengine = FORCEWAKE_MEDIA; \
+ } \
+ else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
+ fwengine = FORCEWAKE_ALL; \
+ } \
+ if (FORCEWAKE_RENDER fwengine) { \
+ if (dev_priv-uncore.fw_rendercount++ == 0) \
+ (dev_priv)-uncore.funcs.force_wake_get(dev_priv, \
+ fwengine); \
+ } \
+ if (FORCEWAKE_MEDIA fwengine) { \
+ if (dev_priv-uncore.fw_mediacount++ == 0) \
+ (dev_priv)-uncore.funcs.force_wake_get(dev_priv, \
+ fwengine); \
+ } \
+ val = __raw_i915_read##x(dev_priv, reg); \
+ if (FORCEWAKE_RENDER fwengine) { \
+ if (--dev_priv-uncore.fw_rendercount == 0) \
+ (dev_priv)-uncore.funcs.force_wake_put(dev_priv, \
+ fwengine); \
+ } \
+ if (FORCEWAKE_MEDIA fwengine) { \
+ if (--dev_priv-uncore.fw_mediacount == 0) \
+ (dev_priv)-uncore.funcs.force_wake_put(dev_priv, \
+ fwengine); \
+ } \
+ REG_READ_FOOTER; \
+}
+__chv_read(8)
+__chv_read(16)
+__chv_read(32)
+__chv_read(64)
__vlv_read(8)
__vlv_read(16)
__vlv_read(32)
@@ -606,6 +672,7 @@ __gen4_read(16)
__gen4_read(32)
__gen4_read(64)
+#undef __chv_read
#undef __vlv_read
#undef __gen6_read
#undef __gen5_read
@@ -710,6 +777,49 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t
reg, u##x val, bool trace
REG_WRITE_FOOTER; \
}
+#define __chv_write(x) \
+static void \
+chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool
trace) { \
+ unsigned fwengine = 0; \
+ bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \
+ REG_WRITE_HEADER; \
+ if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
+ fwengine = FORCEWAKE_RENDER; \
+ } \
+ else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
+ fwengine = FORCEWAKE_MEDIA; \
+ } \
+ else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
+ fwengine = FORCEWAKE_ALL; \
+ } \
+ if (__needs_put (FORCEWAKE_RENDER
Re: [Intel-gfx] [PATCH 00/10] Enable RC6/Turbo on CHV
Hi Ville, let me know if you want some of other small patches to be squashed. Thanks Deepak On Monday 21 April 2014 01:23 PM, deepa...@linux.intel.com wrote: From: Deepak S deepa...@linux.intel.com Squashed some of the patches and created a new patch series. ToDo: Address the comments on some the patches. Changes will be shared in next series. Ben Widawsky (1): drm/i915/bdw: Implement a basic PM interrupt handler Deepak S (6): drm/i915: Enable PM Interrupts target via Display Interface. drm/i915/chv: Enable Render Standby (RC6) for Cheeryview drm/i915/chv: Added CHV specific register read and write drm/i915/chv: Enable RPS (Turbo) for Cheeryview drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating drm/i915/chv: Freq(opcode) request value for CHV. Ville Syrjälä (3): drm/i915/chv: Streamline CHV forcewake stuff drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0 drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV drivers/gpu/drm/i915/i915_drv.h | 10 ++ drivers/gpu/drm/i915/i915_irq.c | 79 +++- drivers/gpu/drm/i915/i915_reg.h | 13 ++ drivers/gpu/drm/i915/intel_drv.h | 2 + drivers/gpu/drm/i915/intel_pm.c | 231 +- drivers/gpu/drm/i915/intel_sideband.c | 15 +++ drivers/gpu/drm/i915/intel_uncore.c | 126 +-- 7 files changed, 455 insertions(+), 21 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 28/71] drm/i915/chv: Added CHV specific register read and write
On Friday 18 April 2014 05:58 AM, Ben Widawsky wrote:
On Wed, Apr 09, 2014 at 01:28:26PM +0300, ville.syrj...@linux.intel.com wrote:
From: Deepak S deepa...@intel.com
Support to individually control Media/Render well based on the register access.
Add CHV specific write function to habdle difference between registers
that are sadowed vs those that need forcewake even for writes.
v2: Drop write FIFO for CHV and add comman well forcewake (Ville)
Signed-off-by: Deepak S deepa...@intel.com
[vsyrjala: Move the register range macros into intel_uncore.c]
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_uncore.c | 139 +---
1 file changed, 131 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 823d699..8e3c686 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -495,6 +495,31 @@ void assert_force_wake_inactive(struct drm_i915_private
*dev_priv)
((reg) = 0x22000 (reg) 0x24000) ||\
((reg) = 0x3 (reg) 0x4))
+#define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
+ (((reg) = 0x2000 (reg) 0x4000) ||\
+ ((reg) = 0x5000 (reg) 0x8000) ||\
+ ((reg) = 0x8300 (reg) 0x8500) ||\
+ ((reg) = 0xB000 (reg) 0xC000) ||\
+ ((reg) = 0xE000 (reg) 0xE800))
+
+#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)\
+ (((reg) = 0x8800 (reg) 0x8900) ||\
+ ((reg) = 0xD000 (reg) 0xD800) ||\
+ ((reg) = 0x12000 (reg) 0x14000) ||\
+ ((reg) = 0x1A000 (reg) 0x1C000) ||\
+ ((reg) = 0x1E800 (reg) 0x1EA00) ||\
+ ((reg) = 0x3 (reg) 0x4))
+
+#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)\
+ (((reg) = 0x4000 (reg) 0x5000) ||\
+ ((reg) = 0x8000 (reg) 0x8300) ||\
+ ((reg) = 0x8500 (reg) 0x8600) ||\
+ ((reg) = 0x9000 (reg) 0xB000) ||\
+ ((reg) = 0xC000 (reg) 0xc800) ||\
+ ((reg) = 0xF000 (reg) 0x1) ||\
+ ((reg) = 0x14000 (reg) 0x14400) ||\
+ ((reg) = 0x22000 (reg) 0x24000))
+
To satisfy both Chris, and Ville, how about:
#define REG_RANGE(reg, start, end) ((reg) = (start) (reg) 0x5000)
REG_RANGE(reg, 0x4000, 0x5000) || \
REG_RANGE(reg, 0x8000, 0x8300) || \
...
By the way, I spent my due diligence trying to find where these ranges
come from, and have been unable. Doc name? I should have all the docs
from Ville.
I can't speak for the code generated, either.
hmm Ok, I will try to re factor this code. I will send the doc name
static void
ilk_dummy_write(struct drm_i915_private *dev_priv)
{
@@ -587,7 +612,48 @@ vlv_read##x(struct drm_i915_private *dev_priv, off_t reg,
bool trace) { \
REG_READ_FOOTER; \
}
+#define __chv_read(x) \
+static u##x \
+chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
+ unsigned fwengine = 0; \
+ REG_READ_HEADER(x); \
+ if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
+ fwengine = FORCEWAKE_RENDER; \
+ } \
+ else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
+ fwengine = FORCEWAKE_MEDIA; \
+ } \
+ else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
+ fwengine = FORCEWAKE_ALL; \
+ } \
+ if (FORCEWAKE_RENDER fwengine) { \
+ if (dev_priv-uncore.fw_rendercount++ == 0) \
+ (dev_priv)-uncore.funcs.force_wake_get(dev_priv, \
+ fwengine); \
+ } \
+ if (FORCEWAKE_MEDIA fwengine) { \
+ if (dev_priv-uncore.fw_mediacount++ == 0) \
+ (dev_priv)-uncore.funcs.force_wake_get(dev_priv, \
+ fwengine); \
+ } \
+ val = __raw_i915_read##x(dev_priv, reg); \
+ if (FORCEWAKE_RENDER fwengine) { \
+ if (dev_priv-uncore.fw_rendercount++ == 0) \
+ (dev_priv)-uncore.funcs.force_wake_put(dev_priv, \
+ fwengine); \
+ } \
+ if (FORCEWAKE_MEDIA fwengine) { \
+ if (dev_priv-uncore.fw_mediacount++ == 0) \
+ (dev_priv)-uncore.funcs.force_wake_put(dev_priv, \
+ fwengine); \
+ } \
+ REG_READ_FOOTER; \
+}
+__chv_read(8)
+__chv_read(16)
+__chv_read(32)
+__chv_read(64)
__vlv_read(8)
__vlv_read(16)
__vlv_read(32)
@@ -605,6 +671,7 @@ __gen4_read(16)
__gen4_read(32)
__gen4_read(64)
+#undef __chv_read
#undef __vlv_read
#undef __gen6_read
#undef __gen5_read
@@ -709,6 +776,49 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t
reg, u##x val, bool trace
REG_WRITE_FOOTER; \
}
+#define __chv_write(x) \
+static void \
+chv_write##x(struct drm_i915_private
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Enable PM Interrupts target via Display Interface.
On Wednesday 16 April 2014 07:02 PM, Ville Syrjälä wrote:
On Mon, Apr 14, 2014 at 10:36:55PM +0300, Ville Syrjälä wrote:
On Mon, Apr 14, 2014 at 10:41:15PM +0530, deepa...@intel.com wrote:
From: Deepak S deepa...@intel.com
In BDW, Apart from unmasking up/down threshold interrupts. we need
to umask bit 32 of PM_INTRMASK to route interrupts to target via Display
Interface.
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c2dd436..8c7841b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5105,6 +5105,7 @@ enum punit_power_well {
#define GEN6_RC6p_THRESHOLD 0xA0BC
#define GEN6_RC6pp_THRESHOLD 0xA0C0
#define GEN6_PMINTRMSK0xA168
+#define GEN8_PMINTR_REDIRECT_TO_NON_DISP 0x7FFF
Defining is as (131) would make more sense to me.
#define GEN6_PMISR0x44020
#define GEN6_PMIMR0x44024 /* rps_lock */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 27b64ab..6b123cd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3066,6 +3066,8 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private
*dev_priv, u8 val)
if (INTEL_INFO(dev_priv-dev)-gen = 7 !IS_HASWELL(dev_priv-dev))
mask |= GEN6_PM_RP_UP_EI_EXPIRED;
+ mask = GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+
return ~mask;
Oh and just noticed this doesn't actually do anything.
must come after ~ to get the expected result.
}
--
1.8.5.2
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--
Ville Syrjälä
Intel OTC
Thanks for review
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[Intel-gfx] [PATCH 0/2] Enable PM Interrupts for BDW
From: Deepak S deepa...@intel.com Added patch to enable PM Interrupts Ben Widawsky (1): drm/i915/bdw: Implement a basic PM interrupt handler Deepak S (1): drm/i915: Enable PM Interrupts target via Display Interface. drivers/gpu/drm/i915/i915_irq.c | 81 +--- drivers/gpu/drm/i915/i915_reg.h | 2 + drivers/gpu/drm/i915/intel_drv.h | 3 +- drivers/gpu/drm/i915/intel_pm.c | 40 +++- 4 files changed, 118 insertions(+), 8 deletions(-) -- 1.8.5.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/bdw: Implement a basic PM interrupt handler
From: Ben Widawsky benjamin.widaw...@intel.com
Almost all of it is reusable from the existing code. The primary
difference is we need to do even less in the interrupt handler, since
interrupts are not shared in the same way.
The patch is mostly a copy-paste of the existing snb+ code, with updates
to the relevant parts requiring changes to the interrupt handling. As
such it /should/ be relatively trivial. It's highly likely that I missed
some places where I need a gen8 version of the PM interrupts, but it has
become invisible to me by now.
This patch could probably be split into adding the new functions,
followed by actually handling the interrupts. Since the code is
currently disabled (and broken) I think the patch stands better by
itself.
v2: Move the commit about not touching the ringbuffer interrupt to the
snb_* function where it belongs (Rodrigo)
v3: Rebased on Paulo's runtime PM changes
v4: Not well validated, but rebase on
commit 730488b2eddded4497f63f70867b1256cd9e117c
Author: Paulo Zanoni paulo.r.zan...@intel.com
Date: Fri Mar 7 20:12:32 2014 -0300
drm/i915: kill dev_priv-pm.regsave
v5: Rebased on latest code base. (Deepak)
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Conflicts:
drivers/gpu/drm/i915/i915_irq.c
---
drivers/gpu/drm/i915/i915_irq.c | 81 +---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 3 +-
drivers/gpu/drm/i915/intel_pm.c | 38 ++-
4 files changed, 115 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7a4d3ae..96c459a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -248,6 +248,50 @@ static bool ivb_can_enable_err_int(struct drm_device *dev)
return true;
}
+/**
+ * bdw_update_pm_irq - update GT interrupt 2
+ * @dev_priv: driver private
+ * @interrupt_mask: mask of interrupt bits to update
+ * @enabled_irq_mask: mask of interrupt bits to enable
+ *
+ * Copied from the snb function, updated with relevant register offsets
+ */
+static void bdw_update_pm_irq(struct drm_i915_private *dev_priv,
+ uint32_t interrupt_mask,
+ uint32_t enabled_irq_mask)
+{
+ uint32_t new_val;
+
+ assert_spin_locked(dev_priv-irq_lock);
+
+ if (dev_priv-pm.irqs_disabled) {
+ WARN(1, IRQs disabled\n);
+ return;
+ }
+
+ new_val = dev_priv-pm_irq_mask;
+ new_val = ~interrupt_mask;
+ new_val |= (~enabled_irq_mask interrupt_mask);
+
+ if (new_val != dev_priv-pm_irq_mask) {
+ dev_priv-pm_irq_mask = new_val;
+ I915_WRITE(GEN8_GT_IMR(2), I915_READ(GEN8_GT_IMR(2)) |
+ dev_priv-pm_irq_mask);
+ POSTING_READ(GEN8_GT_IMR(2));
+ }
+}
+
+void bdw_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
+{
+ bdw_update_pm_irq(dev_priv, mask, mask);
+}
+
+void bdw_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
+{
+ bdw_update_pm_irq(dev_priv, mask, 0);
+}
+
+
static bool cpt_can_enable_serr_int(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -1126,13 +1170,17 @@ static void gen6_pm_rps_work(struct work_struct *work)
spin_lock_irq(dev_priv-irq_lock);
pm_iir = dev_priv-rps.pm_iir;
dev_priv-rps.pm_iir = 0;
- /* Make sure not to corrupt PMIMR state used by ringbuffer code */
- snb_enable_pm_irq(dev_priv, dev_priv-pm_rps_events);
+ if (IS_BROADWELL(dev_priv-dev))
+ bdw_enable_pm_irq(dev_priv, dev_priv-pm_rps_events);
+ else {
+ /* Make sure not to corrupt PMIMR state used by ringbuffer */
+ snb_enable_pm_irq(dev_priv, dev_priv-pm_rps_events);
+ /* Make sure we didn't queue anything we're not going to
+* process. */
+ WARN_ON(pm_iir ~dev_priv-pm_rps_events);
+ }
spin_unlock_irq(dev_priv-irq_lock);
- /* Make sure we didn't queue anything we're not going to process. */
- WARN_ON(pm_iir ~dev_priv-pm_rps_events);
-
if ((pm_iir dev_priv-pm_rps_events) == 0)
return;
@@ -1324,6 +1372,19 @@ static void snb_gt_irq_handler(struct drm_device *dev,
ivybridge_parity_error_irq_handler(dev, gt_iir);
}
+static void gen8_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
+{
+ if ((pm_iir dev_priv-pm_rps_events) == 0)
+ return;
+
+ spin_lock(dev_priv-irq_lock);
+ dev_priv-rps.pm_iir |= pm_iir dev_priv-pm_rps_events;
+ bdw_disable_pm_irq(dev_priv, pm_iir dev_priv-pm_rps_events);
+ spin_unlock(dev_priv-irq_lock);
+
+ queue_work(dev_priv-wq, dev_priv-rps.work);
+}
+
static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
[Intel-gfx] [PATCH 2/2] drm/i915: Enable PM Interrupts target via Display Interface.
From: Deepak S deepa...@intel.com
In BDW, Apart from unmasking up/down threshold interrupts. we need
to umask bit 32 of PM_INTRMASK to route interrupts to target via Display
Interface.
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c2dd436..8c7841b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5105,6 +5105,7 @@ enum punit_power_well {
#define GEN6_RC6p_THRESHOLD0xA0BC
#define GEN6_RC6pp_THRESHOLD 0xA0C0
#define GEN6_PMINTRMSK 0xA168
+#define GEN8_PMINTR_REDIRECT_TO_NON_DISP 0x7FFF
#define GEN6_PMISR 0x44020
#define GEN6_PMIMR 0x44024 /* rps_lock */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 27b64ab..6b123cd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3066,6 +3066,8 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private
*dev_priv, u8 val)
if (INTEL_INFO(dev_priv-dev)-gen = 7 !IS_HASWELL(dev_priv-dev))
mask |= GEN6_PM_RP_UP_EI_EXPIRED;
+ mask = GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+
return ~mask;
}
--
1.8.5.2
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Re: [Intel-gfx] [PATCH 27/71] drm/i915/chv: Enable Render Standby (RC6) for Cheeryview
Thanks for the feedback. I will address all the comments
and I will post cherryview rc6/turbo updated patches within couple of days.
I think the patches need little bit of cleanup.
Thanks
Deepak
On Thursday 10 April 2014 10:36 PM, Ville Syrjälä wrote:
On Thu, Apr 10, 2014 at 07:51:03PM +0300, Jani Nikula wrote:
On Wed, 09 Apr 2014, ville.syrj...@linux.intel.com wrote:
From: Deepak S deepa...@intel.com
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 101 ++--
1 file changed, 98 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0889af7..909cc0a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3184,6 +3184,18 @@ static void gen6_disable_rps(struct drm_device *dev)
gen6_disable_rps_interrupts(dev);
}
+static void cherryview_disable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ I915_WRITE(GEN6_RC_CONTROL, 0);
+
+ if (dev_priv-vlv_pctx) {
+ drm_gem_object_unreference(dev_priv-vlv_pctx-base);
+ dev_priv-vlv_pctx = NULL;
+ }
+}
+
static void valleyview_disable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -3551,6 +3563,29 @@ int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv)
return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) 0xff;
}
+static void cherryview_setup_pctx(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ unsigned long pctx_paddr;
+ struct i915_gtt *gtt = dev_priv-gtt;
+ u32 pcbr;
+ int pctx_size = 32*1024;
+
+ pcbr = I915_READ(VLV_PCBR);
+ if (pcbr 12 == 0) {
+ /*
+* From the Gunit register HAS:
+* The Gfx driver is expected to program this register and
ensure
+* proper allocation within Gfx stolen memory. For example,
this
+* register should be programmed such than the PCBR range does
not
+* overlap with other relevant ranges.
+*/
+ pctx_paddr = (dev_priv-mm.stolen_base + gtt-stolen_size -
pctx_size);
+ I915_WRITE(VLV_PCBR, pctx_paddr);
+ }
+}
+
+
static void valleyview_setup_pctx(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -3595,6 +3630,61 @@ out:
dev_priv-vlv_pctx = pctx;
}
+static void cherryview_enable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_ring_buffer *ring;
+ u32 gtfifodbg, rc6_mode = 0, pcbr;
+ int i;
+
+ WARN_ON(!mutex_is_locked(dev_priv-rps.hw_lock));
+
+ if ((gtfifodbg = I915_READ(GTFIFODBG))) {
Please no assignment within if; this one's easy to split.
There's a bunch of other checkpatch issues in the series; I don't
personally care about most of them but you might want to run it and see
if you want to do something about it.
Looks like it's a straight up copy-paste from the gen6 and vlv code. So
someone might want to clean those out as well.
And maybe we should just drop this check for CHV since the GT wake FIFO
isn't used anymore. But I'm not sure if the register still hold something
sensible or not.
BR,
Jani.
+ DRM_DEBUG_DRIVER(GT fifo had a previous error %x\n,
+gtfifodbg);
+ I915_WRITE(GTFIFODBG, gtfifodbg);
+ }
+
+ cherryview_setup_pctx(dev);
+
+ /* 1a 1b: Get forcewake during program sequence. Although the driver
+* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
+ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+
+ /* 2a: Program RC6 thresholds.*/
+ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 16);
+ I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
+ I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
+
+ for_each_ring(ring, dev_priv, i)
+ I915_WRITE(RING_MAX_IDLE(ring-mmio_base), 10);
+
+ I915_WRITE(GEN6_RC6_THRESHOLD, 5); /* 50/125ms per EI */
+
+ /* allows RC6 residency counter to work */
+ I915_WRITE(VLV_COUNTER_CONTROL,
+ _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
+ VLV_MEDIA_RC6_COUNT_EN |
+ VLV_RENDER_RC6_COUNT_EN));
+
+ /* Todo: If BIOS has not configured PCBR
+* then allocate in BIOS Reserved */
+
+ /* For now we assume BIOS is allocating and populating the PCBR */
+ pcbr = I915_READ(VLV_PCBR);
+
+ DRM_DEBUG_DRIVER(PCBR offset : 0x%x\n, pcbr);
+
+ /* 3: Enable RC6 */
+ if (intel_enable_rc6(dev) INTEL_RC6_ENABLE (pcbr 12
Re: [Intel-gfx] [PATCH 30/71] drm/i915/chv: Enable PM interrupts when we in CHV turbo initialize sequence.
On Thursday 10 April 2014 04:03 AM, Ben Widawsky wrote:
On Thu, Apr 10, 2014 at 12:47:01AM +0530, Deepak S wrote:
On Wednesday 09 April 2014 06:36 PM, Chris Wilson wrote:
On Wed, Apr 09, 2014 at 01:28:28PM +0300, ville.syrj...@linux.intel.com wrote:
+static void gen8_enable_rps_interrupts(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ /* Clear out any stale interrupts first */
+ spin_lock_irq(dev_priv-irq_lock);
+ WARN_ON(dev_priv-rps.pm_iir);
+ I915_WRITE(GEN8_GT_IIR(2), I915_READ(GEN8_GT_IIR(2)));
+ dev_priv-pm_irq_mask = ~GEN6_PM_RPS_EVENTS;
+ I915_WRITE(GEN8_GT_IMR(2), dev_priv-pm_irq_mask);
+ spin_unlock_irq(dev_priv-irq_lock);
+
+ I915_WRITE(GEN8_GT_IER(2), GEN6_PM_RPS_EVENTS);
+ /* only unmask PM interrupts we need. Mask all others. */
+ I915_WRITE(GEN6_PMINTRMSK, ~GEN6_PM_RPS_EVENTS);
PMINTRMSK handling is now a part of set_rps (and so this line is
redundant).
-Chris
Thanks Chris. I will make the changes based on the current nightly code
I think my patch kept up with this, but I too am not sure. In either
case feel free to reuse, copy, or review that one.
I don't think I've mailed out the very latest version, but I am pretty
sure I mailed out after the last painful rebase (and it's tested on
BDW).
http://cgit.freedesktop.org/~bwidawsk/drm-intel/commit/?h=bdw-rc6id=80fbe001fc4ba38c41db3cec177c9157b2613c3c
Thanks Ben. I will reuse the patches submitted by you
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Re: [Intel-gfx] [PATCH 45/71] drm/i915/chv: Streamline CHV forcewake stuff
On Wednesday 09 April 2014 11:17 PM, Ville Syrjälä wrote:
On Wed, Apr 09, 2014 at 06:02:36PM +0200, Daniel Vetter wrote:
On Wed, Apr 09, 2014 at 01:28:43PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Streamline the CHV forcewake functions just like was done for VLV.
This will also fix a bug in accessing the common well registers,
where we'd end up trying to wake up the wells too many times
since we'd call force_wake_get/put twice per register access, with
FORCEFAKE_ALL both times.
Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Ugh ... any chance this would make sense squashed in as a fixup into an
earlier patch? If it's too hairy I'm ok with this as-is.
It could be squashed into patch 28 which introduces this code. I don't
think there were other patches that touch this piece code. I have no
objection to squashing. Deepak, any objections?
Nope. I am Ok with squashing the patch.
-Daniel
---
drivers/gpu/drm/i915/intel_uncore.c | 88 ++---
1 file changed, 32 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index ccad770..59293b3 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -618,35 +618,22 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg,
bool trace) { \
unsigned fwengine = 0; \
REG_READ_HEADER(x); \
if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
- fwengine = FORCEWAKE_RENDER; \
- } \
- else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
- fwengine = FORCEWAKE_MEDIA; \
- } \
- else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
- fwengine = FORCEWAKE_ALL; \
- } \
- if (FORCEWAKE_RENDER fwengine) { \
- if (dev_priv-uncore.fw_rendercount++ == 0) \
- (dev_priv)-uncore.funcs.force_wake_get(dev_priv, \
- fwengine); \
- } \
- if (FORCEWAKE_MEDIA fwengine) { \
- if (dev_priv-uncore.fw_mediacount++ == 0) \
- (dev_priv)-uncore.funcs.force_wake_get(dev_priv, \
- fwengine); \
+ if (dev_priv-uncore.fw_rendercount == 0) \
+ fwengine = FORCEWAKE_RENDER; \
+ } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
+ if (dev_priv-uncore.fw_mediacount == 0) \
+ fwengine = FORCEWAKE_MEDIA; \
+ } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
+ if (dev_priv-uncore.fw_rendercount == 0) \
+ fwengine |= FORCEWAKE_RENDER; \
+ if (dev_priv-uncore.fw_mediacount == 0) \
+ fwengine |= FORCEWAKE_MEDIA; \
} \
+ if (fwengine) \
+ dev_priv-uncore.funcs.force_wake_get(dev_priv, fwengine); \
val = __raw_i915_read##x(dev_priv, reg); \
- if (FORCEWAKE_RENDER fwengine) { \
- if (--dev_priv-uncore.fw_rendercount == 0) \
- (dev_priv)-uncore.funcs.force_wake_put(dev_priv, \
- fwengine); \
- } \
- if (FORCEWAKE_MEDIA fwengine) { \
- if (--dev_priv-uncore.fw_mediacount == 0) \
- (dev_priv)-uncore.funcs.force_wake_put(dev_priv, \
- fwengine); \
- } \
+ if (fwengine) \
+ dev_priv-uncore.funcs.force_wake_put(dev_priv, fwengine); \
REG_READ_FOOTER; \
}
@@ -780,38 +767,27 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
static void \
chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool
trace) { \
unsigned fwengine = 0; \
- bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \
+ bool shadowed = is_gen8_shadowed(dev_priv, reg); \
REG_WRITE_HEADER; \
- if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
- fwengine = FORCEWAKE_RENDER; \
- } \
- else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
- fwengine = FORCEWAKE_MEDIA; \
- } \
- else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
- fwengine = FORCEWAKE_ALL; \
- } \
- if (__needs_put (FORCEWAKE_RENDER fwengine)) { \
- if (dev_priv-uncore.fw_rendercount++ == 0) \
-
(dev_priv)-uncore.funcs.force_wake_get(dev_priv, \
-
fwengine); \
- } \
- if (__needs_put (FORCEWAKE_MEDIA fwengine)) { \
- if (dev_priv-uncore.fw_mediacount++ == 0) \
-
Re: [Intel-gfx] [PATCH 1/6] drm/i915: Bring UP Power Wells before disabling RC6.
On Wednesday 09 April 2014 06:32 PM, Daniel Vetter wrote:
On Wed, Apr 09, 2014 at 09:51:38AM +0530, S, Deepak wrote:
On 4/9/2014 9:43 AM, Ben Widawsky wrote:
On Tue, Apr 08, 2014 at 06:22:52PM +0530, S, Deepak wrote:
On 4/8/2014 6:13 PM, Ville Syrjälä wrote:
On Mon, Apr 07, 2014 at 02:36:20PM -0700, Ben Widawsky wrote:
On Mon, Apr 07, 2014 at 05:01:46PM -0300, Rodrigo Vivi wrote:
From: Deepak S deepa...@intel.com
We need do forcewake before Disabling RC6, This is what the BIOS
expects while going into suspend.
v2: updated commit message. (Daniel)
Signed-off-by: Deepak S deepa...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 04af065..ad2ff99 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3198,8 +3198,14 @@ static void valleyview_disable_rps(struct drm_device
*dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
+ /* we're doing forcewake before Disabling RC6,
+* This what the BIOS expects when going into suspend */
+ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+
I915_WRITE(GEN6_RC_CONTROL, 0);
+ gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
+
gen6_disable_rps_interrupts(dev);
}
Isn't the forcewake done as part of I915_WRITE sufficient?
Writes don't do forcewake, nor is the register even part of the
VLV forcewake ranges.
I guess the rationale for this patche is still a bit vague. But if it's
really needed, I wonder whether we should do this same dance for !VLV
too? Do we have any GPU stuck in wrong power state after suspend type of
bugs still around?
One of suggestion form the HW team was to Bring the wells up before we
disable RC6 at run-time. We did see some issue when we enabled D0ix.
I think the is a good practice to make sure we bring-up the wells before we
disable RC6. At least this avoids the cases where wells are not up before we
can access the Next register after disable.
Ville was totally right. I do think a POSTING_READ is still sufficient.
Don't care much either way.
If feel this patch is not adding any value. I OK dropping this patch.
I think it makes a lot of sense - on the enable side we also grab the
wells (in case the bios has enabled rc6 already) to make sure we change
the rc6/rps state while everything is around.
Can you please update your patch to also roll this out for gen6/8 rps
disable functions?
Thanks, Daniel
Sure Daniel, I will add this to gen6/8 and submit the patch
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Re: [Intel-gfx] [PATCH 30/71] drm/i915/chv: Enable PM interrupts when we in CHV turbo initialize sequence.
On Wednesday 09 April 2014 06:36 PM, Chris Wilson wrote:
On Wed, Apr 09, 2014 at 01:28:28PM +0300, ville.syrj...@linux.intel.com wrote:
+static void gen8_enable_rps_interrupts(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ /* Clear out any stale interrupts first */
+ spin_lock_irq(dev_priv-irq_lock);
+ WARN_ON(dev_priv-rps.pm_iir);
+ I915_WRITE(GEN8_GT_IIR(2), I915_READ(GEN8_GT_IIR(2)));
+ dev_priv-pm_irq_mask = ~GEN6_PM_RPS_EVENTS;
+ I915_WRITE(GEN8_GT_IMR(2), dev_priv-pm_irq_mask);
+ spin_unlock_irq(dev_priv-irq_lock);
+
+ I915_WRITE(GEN8_GT_IER(2), GEN6_PM_RPS_EVENTS);
+ /* only unmask PM interrupts we need. Mask all others. */
+ I915_WRITE(GEN6_PMINTRMSK, ~GEN6_PM_RPS_EVENTS);
PMINTRMSK handling is now a part of set_rps (and so this line is
redundant).
-Chris
Thanks Chris. I will make the changes based on the current nightly code
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[Intel-gfx] [PATCH v2] Revert drm/i915/vlv: fixup DDR freq detection per Punit spec
From: Deepak S deepa...@linux.intel.com
As per the inputs provided by hardware team we still use DDR
Rates as 0,1=800, 2=1066, 3=1333.
With this change, Turbo freqs used on current machines matches.
This reverts commit f64a28a7c5ab2fc342326de9e126acf3cc0f91d6.
commit f64a28a7c5ab2fc342326de9e126acf3cc0f91d6
Author: Jesse Barnes jbar...@virtuousgeek.org
Date: Mon Nov 4 16:07:00 2013 -0800
drm/i915/vlv: fixup DDR freq detection per Punit spec
v2: Add reference to previous commit which changed this. (Daniel)
Acked-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e9a9aef..55dcda6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5037,13 +5037,11 @@ static void valleyview_init_clock_gating(struct
drm_device *dev)
mutex_unlock(dev_priv-rps.hw_lock);
switch ((val 6) 3) {
case 0:
- dev_priv-mem_freq = 800;
- break;
case 1:
- dev_priv-mem_freq = 1066;
+ dev_priv-mem_freq = 800;
break;
case 2:
- dev_priv-mem_freq = 1333;
+ dev_priv-mem_freq = 1066;
break;
case 3:
dev_priv-mem_freq = 1333;
--
1.9.1
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[Intel-gfx] [PATCH v2] drm/i915: Match debugfs interface name to new RPS naming
From: Deepak S deepa...@linux.intel.com
Let's change the i915_cur_delayinfo to i915_frequency_info to be in sync
with new RPS naming convention.
v2: Add i915_frequency_info as debugfs interface name (Ben)
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 1a35215..e5d9a902 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -966,7 +966,7 @@ static int i915_rstdby_delays(struct seq_file *m, void
*unused)
return 0;
}
-static int i915_cur_delayinfo(struct seq_file *m, void *unused)
+static int i915_frequency_info(struct seq_file *m, void *unused)
{
struct drm_info_node *node = (struct drm_info_node *) m-private;
struct drm_device *dev = node-minor-dev;
@@ -3786,7 +3786,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{i915_gem_hws_bsd, i915_hws_info, 0, (void *)VCS},
{i915_gem_hws_vebox, i915_hws_info, 0, (void *)VECS},
{i915_rstdby_delays, i915_rstdby_delays, 0},
- {i915_cur_delayinfo, i915_cur_delayinfo, 0},
+ {i915_frequency_info, i915_frequency_info, 0},
{i915_delayfreq_table, i915_delayfreq_table, 0},
{i915_inttoext_table, i915_inttoext_table, 0},
{i915_drpc_info, i915_drpc_info, 0},
--
1.9.1
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Re: [Intel-gfx] [PATCH v5] drm/i915/vlv: WA for Turbo and RC6 to work together.
On Friday 28 March 2014 06:36 PM, Chris Wilson wrote:
On Fri, Mar 28, 2014 at 02:53:48PM +0200, Ville Syrjälä wrote:
On Thu, Mar 27, 2014 at 12:05:01PM +0530, deepa...@linux.intel.com wrote:
@@ -1403,6 +1411,13 @@ typedef struct drm_i915_private {
/* gen6+ rps state */
struct intel_gen6_power_mgmt rps;
+ /* rps wa up ei calculation */
+ struct intel_rps_ei_calc rps_up_ei;
+
+ /* rps wa down ei calculation */
+ struct intel_rps_ei_calc rps_down_ei;
I could have sworn there was a field for holding all the interesting rps
state together.
-Chris
Hi Chris,
Earlier i was using the rps structure to hold the wa rps state, but there was
not of duplicated code to avoid that i created a separate structure.
We can still re-factor and use rps structure to hold the wa state. Let me know
if we need to created a separate patch to re-factor or add to the WA patch
itself.
I a thinking of adding a new patch on top this.
Thanks
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[Intel-gfx] [PATCH v6] drm/i915/vlv: WA for Turbo and RC6 to work together.
From: Deepak S deepa...@linux.intel.com
With RC6 enabled, BYT has an HW issue in determining the right
Gfx busyness.
WA for Turbo + RC6: Use SW based Gfx busy-ness detection to decide
on increasing/decreasing the freq. This logic will monitor C0
counters of render/media power-wells over EI period and takes
necessary action based on these values
v2: Refactor duplicate code. (Ville)
v3: Reformat the comments. (Ville)
v4: Enable required counters and remove unwanted code (Ville)
v5: Added frequency change acceleration support and remove kernel-doc
style comments. (Ville)
v6: Updated comment section and Fix w/a comment. (Ville)
Signed-off-by: Deepak S deepa...@linux.intel.com
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 15 +
drivers/gpu/drm/i915/i915_irq.c | 135 +++-
drivers/gpu/drm/i915/i915_reg.h | 12 +++-
drivers/gpu/drm/i915/intel_pm.c | 13 +++-
4 files changed, 170 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7c212f3..c48ea93 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -816,6 +816,12 @@ struct i915_suspend_saved_registers {
u32 savePCH_PORT_HOTPLUG;
};
+struct intel_rps_ei_calc {
+ u32 cz_ts_ei;
+ u32 render_ei_c0;
+ u32 media_ei_c0;
+};
+
struct intel_gen6_power_mgmt {
/* work and pm_iir are protected by dev_priv-irq_lock */
struct work_struct work;
@@ -843,6 +849,8 @@ struct intel_gen6_power_mgmt {
bool rp_up_masked;
bool rp_down_masked;
+ u32 ei_interrupt_count;
+
int last_adj;
enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
@@ -1403,6 +1411,13 @@ typedef struct drm_i915_private {
/* gen6+ rps state */
struct intel_gen6_power_mgmt rps;
+ /* rps wa up ei calculation */
+ struct intel_rps_ei_calc rps_up_ei;
+
+ /* rps wa down ei calculation */
+ struct intel_rps_ei_calc rps_down_ei;
+
+
/* ilk-only ips/rps state. Everything in here is protected by the global
* mchdev_lock in intel_pm.c */
struct intel_ilk_power_mgmt ips;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 300f127..341843d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1121,6 +1121,132 @@ void gen6_set_pm_mask(struct drm_i915_private *dev_priv,
}
}
+static u32 vlv_c0_residency(struct drm_i915_private *dev_priv,
+ struct intel_rps_ei_calc *rps_ei)
+{
+ u32 cz_ts, cz_freq_khz;
+ u32 render_count, media_count;
+ u32 elapsed_render, elapsed_media, elapsed_time;
+ u32 residency = 0;
+
+ cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
+ cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv-mem_freq * 1000, 4);
+
+ render_count = I915_READ(VLV_RENDER_C0_COUNT_REG);
+ media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG);
+
+ if (rps_ei-cz_ts_ei == 0) {
+ rps_ei-cz_ts_ei = cz_ts;
+ rps_ei-render_ei_c0 = render_count;
+ rps_ei-media_ei_c0 = media_count;
+
+ return dev_priv-rps.cur_freq;
+ }
+
+ elapsed_time = cz_ts - rps_ei-cz_ts_ei;
+ rps_ei-cz_ts_ei = cz_ts;
+
+ elapsed_render = render_count - rps_ei-render_ei_c0;
+ rps_ei-render_ei_c0 = render_count;
+
+ elapsed_media = media_count - rps_ei-media_ei_c0;
+ rps_ei-media_ei_c0 = media_count;
+
+ /* Convert all the counters into common unit of milli sec */
+ elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC;
+ elapsed_render /= cz_freq_khz;
+ elapsed_media /= cz_freq_khz;
+
+ /*
+* Calculate overall C0 residency percentage
+* only if elapsed time is non zero
+*/
+ if (elapsed_time) {
+ residency =
+ ((max(elapsed_render, elapsed_media) * 100)
+ / elapsed_time);
+ }
+
+ return residency;
+}
+
+
+/**
+ * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU
+ * busy-ness calculated from C0 counters of render media power wells
+ * @dev_priv: DRM device private
+ *
+ */
+static u32 vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv)
+{
+ u32 residency_C0_up = 0, residency_C0_down = 0;
+ u8 new_delay, adj;
+
+ dev_priv-rps.ei_interrupt_count++;
+
+ WARN_ON(!mutex_is_locked(dev_priv-rps.hw_lock));
+
+
+ if (dev_priv-rps_up_ei.cz_ts_ei == 0) {
+ vlv_c0_residency(dev_priv, dev_priv-rps_up_ei);
+ vlv_c0_residency(dev_priv, dev_priv-rps_down_ei);
+ return dev_priv-rps.cur_freq;
+ }
+
+
+ /*
+* To down throttle, C0 residency should be less than down threshold
+* for continous EI intervals. So calculate down EI counters
Re: [Intel-gfx] [PATCH] drm/i915: Mask PM/RPS interrupt generation based on activity
On Friday 28 March 2014 01:33 PM, Chris Wilson wrote:
The speculation is that we can conserve more power by masking off
the interrupts at source (PMINTRMSK) rather than filtering them by the
up/down thresholds (RPINTLIM). We can select which events we know will
be active based on the current frequency versus our imposed range, i.e.
if at minimum, we know we will not want to generate any more
down-interrupts and vice versa.
v2: We only need the TIMEOUT when above min frequency.
v3: Tweak VLV at the same time
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Deepak S deepa...@linux.intel.com
---
I see your point that I cannot remove PMINTRMSK from enable_interrupts
without tweaking VLV at the same time. I did consider making this 4
patches (factor out gen6_rps_pm_mask, tweak gen6+, tweak, vlv, remove it
from enable_interrupts) but decided that was just being silly and
squashed the two patches together instead.
---
drivers/gpu/drm/i915/intel_pm.c | 41 +
1 file changed, 25 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 154aa07d51a7..35a7b5b65883 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3006,6 +3006,24 @@ static void gen6_set_rps_thresholds(struct
drm_i915_private *dev_priv, u8 val)
dev_priv-rps.last_adj = 0;
}
+static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
+{
+ u32 mask = 0;
+
+ if (val dev_priv-rps.min_freq_softlimit)
+ mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
+ if (val dev_priv-rps.max_freq_softlimit)
+ mask |= GEN6_PM_RP_UP_THRESHOLD;
+
+ /* IVB and SNB hard hangs on looping batchbuffer
+* if GEN6_PM_UP_EI_EXPIRED is masked.
+*/
+ if (INTEL_INFO(dev_priv-dev)-gen = 7 !IS_HASWELL(dev_priv-dev))
+ mask |= GEN6_PM_RP_UP_EI_EXPIRED;
+
+ return ~mask;
+}
+
/* gen6_set_rps is called to update the frequency request, but should also be
* called when the range (min_delay and max_delay) is modified so that we can
* update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
@@ -3037,6 +3055,7 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
* until we hit the minimum or maximum frequencies.
*/
I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
+ I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
POSTING_READ(GEN6_RPNSWREQ);
@@ -3089,6 +3108,9 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
I915_WRITE(VLV_GTLC_SURVIVABILITY_REG,
I915_READ(VLV_GTLC_SURVIVABILITY_REG)
~VLV_GFX_CLK_FORCE_ON_BIT);
+
+ I915_WRITE(GEN6_PMINTRMSK,
+ gen6_rps_pm_mask(dev_priv, dev_priv-rps.cur_freq));
}
void gen6_rps_idle(struct drm_i915_private *dev_priv)
@@ -3134,13 +3156,12 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
dev_priv-rps.cur_freq,
vlv_gpu_freq(dev_priv, val), val);
- if (val == dev_priv-rps.cur_freq)
- return;
+ if (val != dev_priv-rps.cur_freq)
+ vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
- vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
+ I915_WRITE(GEN6_PMINTRMSK, val);
dev_priv-rps.cur_freq = val;
-
trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
}
@@ -3220,24 +3241,12 @@ int intel_enable_rc6(const struct drm_device *dev)
static void gen6_enable_rps_interrupts(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
- u32 enabled_intrs;
spin_lock_irq(dev_priv-irq_lock);
WARN_ON(dev_priv-rps.pm_iir);
snb_enable_pm_irq(dev_priv, dev_priv-pm_rps_events);
I915_WRITE(GEN6_PMIIR, dev_priv-pm_rps_events);
spin_unlock_irq(dev_priv-irq_lock);
-
- /* only unmask PM interrupts we need. Mask all others. */
- enabled_intrs = dev_priv-pm_rps_events;
-
- /* IVB and SNB hard hangs on looping batchbuffer
-* if GEN6_PM_UP_EI_EXPIRED is masked.
-*/
- if (INTEL_INFO(dev)-gen = 7 !IS_HASWELL(dev))
- enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
-
- I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
}
static void gen8_enable_rps(struct drm_device *dev)
Reviewed-by:Deepak S deepa...@linux.intel.com
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Re: [Intel-gfx] [PATCH 2/3] drm/i915: Refactor gen6_set_rps
On Thursday 27 March 2014 01:54 PM, Chris Wilson wrote:
What used to be a short-circuit now needs to adjust interrupt masking in
response to user requests for changing the min/max allowed frequencies.
This is currently done by a special case and early return, but the next
patch adds another common action to take, so refactor the code to reduce
duplication.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_pm.c | 34 ++
1 file changed, 14 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index edf1b29d9856..3ad590924062 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3017,36 +3017,30 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
WARN_ON(val dev_priv-rps.max_freq_softlimit);
WARN_ON(val dev_priv-rps.min_freq_softlimit);
- if (val == dev_priv-rps.cur_freq) {
- /* min/max delay may still have been modified so be sure to
-* write the limits value */
- I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
- gen6_rps_limits(dev_priv, val));
+ /* min/max delay may still have been modified so be sure to
+* write the limits value.
+*/
+ if (val != dev_priv-rps.cur_freq) {
+ gen6_set_rps_thresholds(dev_priv, val);
- return;
+ if (IS_HASWELL(dev))
+ I915_WRITE(GEN6_RPNSWREQ,
+ HSW_FREQUENCY(val));
+ else
+ I915_WRITE(GEN6_RPNSWREQ,
+ GEN6_FREQUENCY(val) |
+ GEN6_OFFSET(0) |
+ GEN6_AGGRESSIVE_TURBO);
}
- gen6_set_rps_thresholds(dev_priv, val);
-
- if (IS_HASWELL(dev))
- I915_WRITE(GEN6_RPNSWREQ,
- HSW_FREQUENCY(val));
- else
- I915_WRITE(GEN6_RPNSWREQ,
- GEN6_FREQUENCY(val) |
- GEN6_OFFSET(0) |
- GEN6_AGGRESSIVE_TURBO);
-
/* Make sure we continue to get interrupts
* until we hit the minimum or maximum frequencies.
*/
- I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
- gen6_rps_limits(dev_priv, val));
+ I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
POSTING_READ(GEN6_RPNSWREQ);
dev_priv-rps.cur_freq = val;
-
trace_intel_gpu_freq_change(val * 50);
}
Reviewed-by:Deepak S deepa...@linux.intel.com
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Re: [Intel-gfx] [PATCH 1/3] Revert drm/i915: Disable/Enable PM Intrrupts based on the current freq.
On Thursday 27 March 2014 01:54 PM, Chris Wilson wrote:
This reverts commit 2754436913b94626a5414d82f0996489628c513d.
Conflicts:
drivers/gpu/drm/i915/i915_irq.c
The partial application of interrupt masking without regard to other
pathways for adjusting the RPS frequency results in completely disabling
the PM interrupts. This leads to excessive power consumption as the GPU
is kept at max clocks (until the failsafe mechanism fires of explicitly
downclocking the GPU when all requests are idle). Or equally as bad for
the UX, the GPU is kept at minimum clocks and prevented from upclocking
in response to a requirement for more power.
Testcase: pm_rps/blocking
Cc: Deepak S deepa...@intel.com
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h | 3 ---
drivers/gpu/drm/i915/i915_irq.c | 38 --
drivers/gpu/drm/i915/intel_pm.c | 8
3 files changed, 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cf214a4b8fdc..0eae9cd8347e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -846,9 +846,6 @@ struct intel_gen6_power_mgmt {
u8 rp1_freq;/* less than RP0 power/freqency */
u8 rp0_freq;/* Non-overclocked max frequency. */
- bool rp_up_masked;
- bool rp_down_masked;
-
int last_adj;
enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6e37580de4bc..8df8876f557c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1098,43 +1098,6 @@ static void notify_ring(struct drm_device *dev,
i915_queue_hangcheck(dev);
}
-void gen6_set_pm_mask(struct drm_i915_private *dev_priv,
-u32 pm_iir, int new_delay)
-{
- if (pm_iir GEN6_PM_RP_UP_THRESHOLD) {
- if (new_delay = dev_priv-rps.max_freq_softlimit) {
- /* Mask UP THRESHOLD Interrupts */
- I915_WRITE(GEN6_PMINTRMSK,
- I915_READ(GEN6_PMINTRMSK) |
- GEN6_PM_RP_UP_THRESHOLD);
- dev_priv-rps.rp_up_masked = true;
- }
- if (dev_priv-rps.rp_down_masked) {
- /* UnMask DOWN THRESHOLD Interrupts */
- I915_WRITE(GEN6_PMINTRMSK,
- I915_READ(GEN6_PMINTRMSK)
- ~GEN6_PM_RP_DOWN_THRESHOLD);
- dev_priv-rps.rp_down_masked = false;
- }
- } else if (pm_iir GEN6_PM_RP_DOWN_THRESHOLD) {
- if (new_delay = dev_priv-rps.min_freq_softlimit) {
- /* Mask DOWN THRESHOLD Interrupts */
- I915_WRITE(GEN6_PMINTRMSK,
- I915_READ(GEN6_PMINTRMSK) |
- GEN6_PM_RP_DOWN_THRESHOLD);
- dev_priv-rps.rp_down_masked = true;
- }
-
- if (dev_priv-rps.rp_up_masked) {
- /* UnMask UP THRESHOLD Interrupts */
- I915_WRITE(GEN6_PMINTRMSK,
- I915_READ(GEN6_PMINTRMSK)
- ~GEN6_PM_RP_UP_THRESHOLD);
- dev_priv-rps.rp_up_masked = false;
- }
- }
-}
-
static void gen6_pm_rps_work(struct work_struct *work)
{
drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
@@ -1194,7 +1157,6 @@ static void gen6_pm_rps_work(struct work_struct *work)
dev_priv-rps.min_freq_softlimit,
dev_priv-rps.max_freq_softlimit);
- gen6_set_pm_mask(dev_priv, pm_iir, new_delay);
dev_priv-rps.last_adj = new_delay - dev_priv-rps.cur_freq;
if (IS_VALLEYVIEW(dev_priv-dev))
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 22134558c452..edf1b29d9856 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3095,11 +3095,6 @@ static void vlv_set_rps_idle(struct drm_i915_private
*dev_priv)
I915_WRITE(VLV_GTLC_SURVIVABILITY_REG,
I915_READ(VLV_GTLC_SURVIVABILITY_REG)
~VLV_GFX_CLK_FORCE_ON_BIT);
-
- /* Unmask Up interrupts */
- dev_priv-rps.rp_up_masked = true;
- gen6_set_pm_mask(dev_priv, GEN6_PM_RP_DOWN_THRESHOLD,
-
dev_priv-rps.min_freq_softlimit);
}
void gen6_rps_idle(struct drm_i915_private *dev_priv)
@@ -3694,9 +3689,6 @@ static void valleyview_enable_rps(struct drm_device *dev)
valleyview_set_rps(dev_priv-dev, dev_priv-rps.efficient_freq
[Intel-gfx] [PATCH] Revert drm/i915/vlv: fixup DDR freq detection per Punit spec
From: Deepak S deepa...@linux.intel.com
This reverts commit f64a28a7c5ab2fc342326de9e126acf3cc0f91d6.
As per the inputs provided by hardware team we still use DDR
Rates as 0,1=800, 2=1066, 3=1333.
With this change, Turbo freqs used on current machines matches.
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 30730be..2c8c7da 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5049,13 +5049,11 @@ static void valleyview_init_clock_gating(struct
drm_device *dev)
mutex_unlock(dev_priv-rps.hw_lock);
switch ((val 6) 3) {
case 0:
- dev_priv-mem_freq = 800;
- break;
case 1:
- dev_priv-mem_freq = 1066;
+ dev_priv-mem_freq = 800;
break;
case 2:
- dev_priv-mem_freq = 1333;
+ dev_priv-mem_freq = 1066;
break;
case 3:
dev_priv-mem_freq = 1333;
--
1.9.1
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[Intel-gfx] [PATCH] drm/i915: Match debugfs interface name to new RPS naming
From: Deepak S deepa...@intel.com
Let's change the i915_cur_delayinfo to i915_cur_freqinfo to be in sync
with new RPS naming convention.
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 049dcb5..3cfc35c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -966,7 +966,7 @@ static int i915_rstdby_delays(struct seq_file *m, void
*unused)
return 0;
}
-static int i915_cur_delayinfo(struct seq_file *m, void *unused)
+static int i915_cur_freqinfo(struct seq_file *m, void *unused)
{
struct drm_info_node *node = (struct drm_info_node *) m-private;
struct drm_device *dev = node-minor-dev;
@@ -3772,7 +3772,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{i915_gem_hws_bsd, i915_hws_info, 0, (void *)VCS},
{i915_gem_hws_vebox, i915_hws_info, 0, (void *)VECS},
{i915_rstdby_delays, i915_rstdby_delays, 0},
- {i915_cur_delayinfo, i915_cur_delayinfo, 0},
+ {i915_cur_freqinfo, i915_cur_freqinfo, 0},
{i915_delayfreq_table, i915_delayfreq_table, 0},
{i915_inttoext_table, i915_inttoext_table, 0},
{i915_drpc_info, i915_drpc_info, 0},
--
1.8.5.2
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