Re: Test Result Summary for Calendar Week 49.
Add STE Snowball Linux Linaro Quantal Test Result 8) STE Snowball + Linux Linaro Quantal (Column C): https://docs.google.com/a/linaro.org/spreadsheet/ccc?key=0AroPySpr4FnEdFJ4X0NjWjJteVlXLVJFSHFuOHo1c2c#gid=1 Boot failed, then it blocked all rest test. Thanks. On Fri, Dec 7, 2012 at 3:49 PM, Botao Sun botao@linaro.org wrote: Calendar Week 49: Here is test result summary for Linaro ubuntu image on following boards: 1) ARM Versatile Express A9; 2) Samsung Origen; 3) TI Panda 4430; 4) TI Panda 4460; 5) Open Embedded SDK; 6) Open Embedded LAMP; 7) Open Embedded Minimum; Synopsis: All ubuntu images have been upgraded to command based Linux Linaro Quantal images; All UI related test cases have been ignored; Open Embedded remains the exactly same status as last week. 1. ARM Versatile Express A9 + Linux Linaro Quantal (Column C): https://docs.google.com/a/linaro.org/spreadsheet/ccc?key=0AroPySpr4FnEdFNmV3gyZWRGVS12YUhqeW9rdkVZdmc#gid=1 Data streaming failed in DS-5, Gator daemon doesn't exist in image. Device Tree is still unavailable, and Halt test failed either. All other features work well, 2. Samsung Origen + Linux Linaro Quantal (Column C): https://docs.google.com/a/linaro.org/spreadsheet/ccc?key=0AroPySpr4FnEdEowNWhZRi1zbDNNVUw1amhXTUdPcVE#gid=1 Data streaming failed in DS-5, lava-test is not pre-installed in image, and this cause test pwrmgmt blocked. Also, powertop test will cause segmentation fault and kernel panic. No Internet connection on this image, neither Ethernet nor WiFi works. Both reboot halt test failed. 3. TI Panda 4430 + Linux Linaro Quantal (Column C): https://docs.google.com/a/linaro.org/spreadsheet/ccc?key=0AroPySpr4FnEdEwwZkhrZ1VYUEg2LTlQZzR0RlhzM3c#gid=3 Data streaming failed in DS-5, the directory of device tree is empty, although the boot log shows it had been enabled during boot process. lava-test doesn't exist in image. All other feature work well. 4. TI Panda 4460 + Linux Linaro Quantal (Column C): https://docs.google.com/a/linaro.org/spreadsheet/ccc?key=0AroPySpr4FnEdEwwZkhrZ1VYUEg2LTlQZzR0RlhzM3c#gid=4 Exactly same as TI Panda 4430 above. 5. Open Embedded SDK in Fast Model (Column D): https://docs.google.com/a/linaro.org/spreadsheet/ccc?key=0AgB-fT5LL31CdDhwRFBoQ0NZODFFbUsxSHRKUjhBeGc#gid=0 All test passed. 6. Open Embedded LAMP in Fast Model (Column D): Same issue as previous week, kernel exception message occurred if show any PHP web page. All other test passed. 7. Open Embedded Minimum in Fast Model (Column D): https://docs.google.com/a/linaro.org/spreadsheet/ccc?key=0AgB-fT5LL31CdDhwRFBoQ0NZODFFbUsxSHRKUjhBeGc#gid=2 All test cases passed. For the previous week (Calendar week 48) summary, please refer to attachment. Thank you. Best Regards Botao Sun ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
[Resend Patch v2 1/3] EXYNOS: EXYNOS4X12: Populate Exynos4x12 register addresses
This patch populates base addresses of Exynos4x12 registers.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
---
arch/arm/include/asm/arch-exynos/cpu.h | 48 +++-
1 file changed, 41 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h
b/arch/arm/include/asm/arch-exynos/cpu.h
index d1b2ea8..86c7905 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -27,7 +27,7 @@
#define EXYNOS_CPU_NAMEExynos
#define EXYNOS4_ADDR_BASE 0x1000
-/* EXYNOS4 */
+/* EXYNOS4 Common*/
#define EXYNOS4_GPIO_PART3_BASE0x0386
#define EXYNOS4_PRO_ID 0x1000
#define EXYNOS4_SYSREG_BASE0x1001
@@ -61,7 +61,37 @@
#define EXYNOS4_DP_BASEDEVICE_NOT_AVAILABLE
#define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
-/* EXYNOS5 */
+/* EXYNOS4X12 */
+#define EXYNOS4X12_GPIO_PART3_BASE 0x0386
+#define EXYNOS4X12_PRO_ID 0x1000
+#define EXYNOS4X12_SYSREG_BASE 0x1001
+#define EXYNOS4X12_POWER_BASE 0x1002
+#define EXYNOS4X12_SWRESET 0x10020400
+#define EXYNOS4X12_USBPHY_CONTROL 0x10020704
+#define EXYNOS4X12_CLOCK_BASE 0x1003
+#define EXYNOS4X12_SYSTIMER_BASE 0x1005
+#define EXYNOS4X12_WATCHDOG_BASE 0x1006
+#define EXYNOS4X12_DMC0_BASE 0x1060
+#define EXYNOS4X12_DMC1_BASE 0x1061
+#define EXYNOS4X12_GPIO_PART4_BASE 0x106E
+#define EXYNOS4X12_GPIO_PART2_BASE 0x1100
+#define EXYNOS4X12_GPIO_PART1_BASE 0x1140
+#define EXYNOS4X12_FIMD_BASE 0x11C0
+#define EXYNOS4X12_MIPI_DSIM_BASE 0x11C8
+#define EXYNOS4X12_USBOTG_BASE 0x1248
+#define EXYNOS4X12_MMC_BASE0x1251
+#define EXYNOS4X12_SROMC_BASE 0x1257
+#define EXYNOS4X12_USB_HOST_EHCI_BASE 0x1258
+#define EXYNOS4X12_USBPHY_BASE 0x125B
+#define EXYNOS4X12_UART_BASE 0x1380
+#define EXYNOS4X12_I2C_BASE0x1386
+#define EXYNOS4X12_PWMTIMER_BASE 0x139D
+
+#define EXYNOS4X12_ADC_BASEDEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE
+
+/* EXYNOS5 Common*/
#define EXYNOS5_I2C_SPACING0x1
#define EXYNOS5_GPIO_PART4_BASE0x0386
@@ -152,17 +182,21 @@ static inline int proid_is_##type(void)
\
}
IS_EXYNOS_TYPE(exynos4210, 0x4210)
+IS_EXYNOS_TYPE(exynos4412, 0x4412)
IS_EXYNOS_TYPE(exynos5250, 0x5250)
#define SAMSUNG_BASE(device, base) \
static inline unsigned int samsung_get_base_##device(void) \
{ \
- if (cpu_is_exynos4()) \
- return EXYNOS4_##base; \
- else if (cpu_is_exynos5()) \
+ if (cpu_is_exynos4()) { \
+ if (proid_is_exynos4412()) \
+ return EXYNOS4X12_##base; \
+ else\
+ return EXYNOS4_##base; \
+ } else if (cpu_is_exynos5()) { \
return EXYNOS5_##base; \
- else\
- return 0; \
+ } \
+ return 0; \
}
SAMSUNG_BASE(adc, ADC_BASE)
--
1.7.9.5
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[Resend Patch v2 2/3] EXYNOS: EXYNOS4X12: Add clock structure for EXYNOS4X12
This patch adds clock structure for Exynos4x12.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
---
arch/arm/include/asm/arch-exynos/clock.h | 276 ++
1 file changed, 276 insertions(+)
diff --git a/arch/arm/include/asm/arch-exynos/clock.h
b/arch/arm/include/asm/arch-exynos/clock.h
index ff6781a..9b56b4e 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -251,6 +251,282 @@ struct exynos4_clock {
unsigned intdiv_iem_l1;
};
+struct exynos4x12_clock {
+ unsigned char res1[0x4200];
+ unsigned intsrc_leftbus;
+ unsigned char res2[0x1fc];
+ unsigned intmux_stat_leftbus;
+ unsigned char res3[0xfc];
+ unsigned intdiv_leftbus;
+ unsigned char res4[0xfc];
+ unsigned intdiv_stat_leftbus;
+ unsigned char res5[0x1fc];
+ unsigned intgate_ip_leftbus;
+ unsigned char res6[0x12c];
+ unsigned intgate_ip_image;
+ unsigned char res7[0xcc];
+ unsigned intclkout_leftbus;
+ unsigned intclkout_leftbus_div_stat;
+ unsigned char res8[0x37f8];
+ unsigned intsrc_rightbus;
+ unsigned char res9[0x1fc];
+ unsigned intmux_stat_rightbus;
+ unsigned char res10[0xfc];
+ unsigned intdiv_rightbus;
+ unsigned char res11[0xfc];
+ unsigned intdiv_stat_rightbus;
+ unsigned char res12[0x1fc];
+ unsigned intgate_ip_rightbus;
+ unsigned char res13[0x15c];
+ unsigned intgate_ip_perir;
+ unsigned char res14[0x9c];
+ unsigned intclkout_rightbus;
+ unsigned intclkout_rightbus_div_stat;
+ unsigned char res15[0x3608];
+ unsigned intepll_lock;
+ unsigned char res16[0xc];
+ unsigned intvpll_lock;
+ unsigned char res17[0xec];
+ unsigned intepll_con0;
+ unsigned intepll_con1;
+ unsigned intepll_con2;
+ unsigned char res18[0x4];
+ unsigned intvpll_con0;
+ unsigned intvpll_con1;
+ unsigned intvpll_con2;
+ unsigned char res19[0xe4];
+ unsigned intsrc_top0;
+ unsigned intsrc_top1;
+ unsigned char res20[0x8];
+ unsigned intsrc_cam;
+ unsigned intsrc_tv;
+ unsigned intsrc_mfc;
+ unsigned intsrc_g3d;
+ unsigned char res21[0x4];
+ unsigned intsrc_lcd;
+ unsigned intsrc_isp;
+ unsigned intsrc_maudio;
+ unsigned intsrc_fsys;
+ unsigned char res22[0xc];
+ unsigned intsrc_peril0;
+ unsigned intsrc_peril1;
+ unsigned intsrc_cam1;
+ unsigned char res23[0xb4];
+ unsigned intsrc_mask_top;
+ unsigned char res24[0xc];
+ unsigned intsrc_mask_cam;
+ unsigned intsrc_mask_tv;
+ unsigned char res25[0xc];
+ unsigned intsrc_mask_lcd;
+ unsigned intsrc_mask_isp;
+ unsigned intsrc_mask_maudio;
+ unsigned intsrc_mask_fsys;
+ unsigned char res26[0xc];
+ unsigned intsrc_mask_peril0;
+ unsigned intsrc_mask_peril1;
+ unsigned char res27[0xb8];
+ unsigned intmux_stat_top0;
+ unsigned intmux_stat_top1;
+ unsigned char res28[0x10];
+ unsigned intmux_stat_mfc;
+ unsigned intmux_stat_g3d;
+ unsigned char res29[0x28];
+ unsigned intmux_stat_cam1;
+ unsigned char res30[0xb4];
+ unsigned intdiv_top;
+ unsigned char res31[0xc];
+ unsigned intdiv_cam;
+ unsigned intdiv_tv;
+ unsigned intdiv_mfc;
+ unsigned intdiv_g3d;
+ unsigned char res32[0x4];
+ unsigned intdiv_lcd;
+ unsigned intdiv_isp;
+ unsigned intdiv_maudio;
+ unsigned intdiv_fsys0;
+ unsigned intdiv_fsys1;
+ unsigned intdiv_fsys2;
+ unsigned intdiv_fsys3;
+ unsigned intdiv_peril0;
+ unsigned intdiv_peril1;
+ unsigned intdiv_peril2;
+ unsigned intdiv_peril3;
+ unsigned intdiv_peril4;
+ unsigned intdiv_peril5;
+ unsigned intdiv_cam1;
+ unsigned char res33[0x14];
+ unsigned intdiv2_ratio;
+ unsigned char res34[0x8c];
+ unsigned intdiv_stat_top;
+ unsigned char res35[0xc];
+ unsigned intdiv_stat_cam;
+ unsigned intdiv_stat_tv;
+ unsigned intdiv_stat_mfc;
+ unsigned intdiv_stat_g3d;
+ unsigned char res36[0x4];
+ unsigned intdiv_stat_lcd;
+ unsigned intdiv_stat_isp;
+ unsigned intdiv_stat_maudio;
+ unsigned intdiv_stat_fsys0;
+ unsigned intdiv_stat_fsys1;
+ unsigned intdiv_stat_fsys2;
+ unsigned intdiv_stat_fsys3;
+ unsigned int
[Resend Patch v2 3/3] EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12
This patch adds gpio structure for Exynos4x12.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
---
arch/arm/include/asm/arch-exynos/gpio.h | 85 +++
1 file changed, 85 insertions(+)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm/include/asm/arch-exynos/gpio.h
index 4db8fd6..cfe1024 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -79,6 +79,67 @@ struct exynos4_gpio_part3 {
struct s5p_gpio_bank z;
};
+struct exynos4x12_gpio_part1 {
+ struct s5p_gpio_bank a0;
+ struct s5p_gpio_bank a1;
+ struct s5p_gpio_bank b;
+ struct s5p_gpio_bank c0;
+ struct s5p_gpio_bank c1;
+ struct s5p_gpio_bank d0;
+ struct s5p_gpio_bank d1;
+ struct s5p_gpio_bank res1[0x5];
+ struct s5p_gpio_bank f0;
+ struct s5p_gpio_bank f1;
+ struct s5p_gpio_bank f2;
+ struct s5p_gpio_bank f3;
+ struct s5p_gpio_bank res2[0x2];
+ struct s5p_gpio_bank j0;
+ struct s5p_gpio_bank j1;
+};
+
+struct exynos4x12_gpio_part2 {
+ struct s5p_gpio_bank res1[0x2];
+ struct s5p_gpio_bank k0;
+ struct s5p_gpio_bank k1;
+ struct s5p_gpio_bank k2;
+ struct s5p_gpio_bank k3;
+ struct s5p_gpio_bank l0;
+ struct s5p_gpio_bank l1;
+ struct s5p_gpio_bank l2;
+ struct s5p_gpio_bank y0;
+ struct s5p_gpio_bank y1;
+ struct s5p_gpio_bank y2;
+ struct s5p_gpio_bank y3;
+ struct s5p_gpio_bank y4;
+ struct s5p_gpio_bank y5;
+ struct s5p_gpio_bank y6;
+ struct s5p_gpio_bank res2[0x3];
+ struct s5p_gpio_bank m0;
+ struct s5p_gpio_bank m1;
+ struct s5p_gpio_bank m2;
+ struct s5p_gpio_bank m3;
+ struct s5p_gpio_bank m4;
+ struct s5p_gpio_bank res3[0x48];
+ struct s5p_gpio_bank x0;
+ struct s5p_gpio_bank x1;
+ struct s5p_gpio_bank x2;
+ struct s5p_gpio_bank x3;
+};
+
+struct exynos4x12_gpio_part3 {
+ struct s5p_gpio_bank z;
+};
+
+struct exynos4x12_gpio_part4 {
+ struct s5p_gpio_bank v0;
+ struct s5p_gpio_bank v1;
+ struct s5p_gpio_bank res1[0x1];
+ struct s5p_gpio_bank v2;
+ struct s5p_gpio_bank v3;
+ struct s5p_gpio_bank res2[0x1];
+ struct s5p_gpio_bank v4;
+};
+
struct exynos5_gpio_part1 {
struct s5p_gpio_bank a0;
struct s5p_gpio_bank a1;
@@ -163,6 +224,30 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int
gpio, int mode);
- EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX)
+#define exynos4x12_gpio_part1_get_nr(bank, pin) \
+ ((unsigned int) (((struct exynos4x12_gpio_part1 *) \
+ EXYNOS4X12_GPIO_PART1_BASE)-bank)) \
+ - EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
+ * GPIO_PER_BANK) + pin)
+
+#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \
+ / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
+
+#define exynos4x12_gpio_part2_get_nr(bank, pin) \
+ (((unsigned int) (((struct exynos4x12_gpio_part2 *) \
+ EXYNOS4X12_GPIO_PART2_BASE)-bank)) \
+ - EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
+ * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX)
+
+#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \
+ / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
+
+#define exynos4x12_gpio_part3_get_nr(bank, pin) \
+ (((unsigned int) (((struct exynos4x12_gpio_part3 *) \
+ EXYNOS4X12_GPIO_PART3_BASE)-bank)) \
+ - EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
+ * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX)
+
#define exynos5_gpio_part1_get_nr(bank, pin) \
((unsigned int) (((struct exynos5_gpio_part1 *) \
EXYNOS5_GPIO_PART1_BASE)-bank)) \
--
1.7.9.5
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[Resend Patch v2 0/3] EXYNOS: Add support for Exynos4x12
This patch series popultes Register addresses, clock structure and gpio structure for Exynos4x12. Rebase to latest u-boot-samsung tree. Chander Kashyap (3): EXYNOS: EXYNOS4X12: Populate Exynos4x12 register addresses EXYNOS: EXYNOS4X12: Add clock structure for EXYNOS4X12 EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12 arch/arm/include/asm/arch-exynos/clock.h | 276 ++ arch/arm/include/asm/arch-exynos/cpu.h | 48 +- arch/arm/include/asm/arch-exynos/gpio.h | 85 + 3 files changed, 402 insertions(+), 7 deletions(-) -- 1.7.9.5 ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
Re: [PATCH v2 0/3] EXYNOS: Add support for Exynos4x12
Dear Chander, On 02/11/12 19:51, Chander Kashyap wrote: ping On 2 October 2012 15:16, Chander Kashyap chander.kash...@linaro.org wrote: This patch series popultes Register addresses, clock structure and gpio structure for Exynos4x12. Changes in v2: - Fixed the GPIO base address macro for exynos4x12_gpio_part3_get_nr in arch/arm/include/asm/arch-exynos/gpio.h Chander Kashyap (3): EXYNOS: EXYNOS4X12: Populate Exynos4x12 register addresses EXYNOS: EXYNOS4X12: Add clock structure for EXYNOS4X12 EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12 arch/arm/include/asm/arch-exynos/clock.h | 276 ++ arch/arm/include/asm/arch-exynos/cpu.h | 48 +- arch/arm/include/asm/arch-exynos/gpio.h | 85 + 3 files changed, 402 insertions(+), 7 deletions(-) Patches are looks good. Please rebase this patchset. Thanks. Minkyu Kang. ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
[PATCH] bootwrapper: CPU hotplug aware boot protocol
To enable CPU hotplug the need to provide some boot code at the reset
vector and which survives after the kernel has booted without being
overwritten. We achieve this by the getting the linker script to place
the code in boot.S at address zero. This now means we can delete the
code that relocates the secondary CPU pen code to a location less
likely to be overridden.
We then modify the boot protocol slightly to allow hot-plugging of any
CPU, including CPU #0, when the system is already booted. This is done
by checking if SYS_FLAGS is already set before the normal check for CPU0
and the boot-or-wait decision made.
This patch is based on work by Nicolas Pitre.
Signed-off-by: Nicolas Pitre n...@linaro.org
Signed-off-by: Jon Medhurst t...@linaro.org
---
boot.S | 41 -
model.lds.S |3 ++-
2 files changed, 26 insertions(+), 18 deletions(-)
diff --git a/boot.S b/boot.S
index dd453e3..fb56693 100644
--- a/boot.S
+++ b/boot.S
@@ -12,6 +12,8 @@
.arch_extension virt
.text
+ b start @ Must be first instruction for power on reset vector
+
.macro enter_hyp
@ We assume we're entered in Secure Supervisor mode. To
@ get to Hyp mode we have to pass through Monitor mode
@@ -119,27 +121,32 @@ start:
orr r0, r0, r1
mcr p15, 0, r0, c1, c1, 2
- @ Check CPU nr again
- mrc p15, 0, r0, c0, c0, 5 @ MPIDR (ARMv7 only)
- bfc r0, #24, #8 @ CPU number, taking
multicluster into account
- cmp r0, #0 @ primary CPU?
- beq 2f
-
- @
- @ Secondary CPUs (following the RealView SMP booting protocol)
- @
- enter_hyp
-
- ldr r1, =fs_start - 0x100
- adr r2, 1f
- ldmia r2, {r3 - r7} @ move the code to a location
- stmia r1, {r3 - r7} @ less likely to be overridden
+ /*
+* If SYS_FLAGS is already set, this is a warm boot and we blindly
+* branch to the indicated address right away, irrespective of the
+* CPU we are.
+*/
#ifdef VEXPRESS
ldr r0, =0x1c010030 @ VE SYS_FLAGS register
#else
ldr r0, =0x1030 @ RealView SYS_FLAGS register
#endif
- mov pc, r1 @ branch to the relocated code
+ ldr r1, [r0]
+ cmp r1, #0
+ beq 1f
+ enter_hyp
+ bx r1
+1:
+ /*
+* Otherwise this is a cold boot. In this case it depends if
+* we are the primary CPU or not. The primary CPU boots the system
+* while the secondaries wait for the primary to set SYS_FLAGS.
+*/
+ mrc p15, 0, r1, c0, c0, 5
+ bicsr1, #0xff00
+ beq 2f
+
+ enter_hyp
1:
#ifdef VEXPRESS
wfe
@@ -147,7 +154,7 @@ start:
ldr r1, [r0]
cmp r1, #0
beq 1b
- mov pc, r1 @ branch to the given address
+ bx r1 @ branch to the given address
#endif
2:
diff --git a/model.lds.S b/model.lds.S
index 793df89..f37824e 100644
--- a/model.lds.S
+++ b/model.lds.S
@@ -27,7 +27,8 @@ STACKTOP = 0xff00;
SECTIONS
{
- . = PHYS_OFFSET;
+ . = 0;
+ .boot : { boot.o }
. = PHYS_OFFSET + 0x8000 - 0x40;
--
1.7.10.4
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[HMP][PATCH 0/1] Global balance
Hi Viresh, Here is a patch that introduces global load balancing on top of the existing HMP patch set. It depends on the HMP patches already present in your task-placement-v2 branch. It can be applied on top of the HMP sysfs patches if needed. The fix should be trivial. Could you include in the MP branch for the 12.12 release? Testing with sysbench and coremark show significant performance improvements for parallel workloads as all cpus can now be used for cpu intensive tasks. Thanks, Morten Morten Rasmussen (1): sched: Basic global balancing support for HMP kernel/sched/fair.c | 101 +-- 1 file changed, 97 insertions(+), 4 deletions(-) -- 1.7.9.5 ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
[HMP][PATCH 1/1] sched: Basic global balancing support for HMP
This patch introduces an extra-check at task up-migration to
prevent overloading the cpus in the faster hmp_domain while the
slower hmp_domain is not fully utilized. The patch also introduces
a periodic balance check that can down-migrate tasks if the faster
domain is oversubscribed and the slower is under-utilized.
Signed-off-by: Morten Rasmussen morten.rasmus...@arm.com
---
kernel/sched/fair.c | 101 +--
1 file changed, 97 insertions(+), 4 deletions(-)
diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
index 1cfe112..7ac47c9 100644
--- a/kernel/sched/fair.c
+++ b/kernel/sched/fair.c
@@ -3249,6 +3249,80 @@ static inline void hmp_next_down_delay(struct
sched_entity *se, int cpu)
se-avg.hmp_last_down_migration = cfs_rq_clock_task(cfs_rq);
se-avg.hmp_last_up_migration = 0;
}
+
+static inline unsigned int hmp_domain_min_load(struct hmp_domain *hmpd,
+ int *min_cpu)
+{
+ int cpu;
+ int min_load = INT_MAX;
+ int min_cpu_temp = NR_CPUS;
+
+ for_each_cpu_mask(cpu, hmpd-cpus) {
+ if (cpu_rq(cpu)-cfs.tg_load_contrib min_load) {
+ min_load = cpu_rq(cpu)-cfs.tg_load_contrib;
+ min_cpu_temp = cpu;
+ }
+ }
+
+ if (min_cpu)
+ *min_cpu = min_cpu_temp;
+
+ return min_load;
+}
+
+/*
+ * Calculate the task starvation
+ * This is the ratio of actually running time vs. runnable time.
+ * If the two are equal the task is getting the cpu time it needs or
+ * it is alone on the cpu and the cpu is fully utilized.
+ */
+static inline unsigned int hmp_task_starvation(struct sched_entity *se)
+{
+ u32 starvation;
+
+ starvation = se-avg.usage_avg_sum * scale_load_down(NICE_0_LOAD);
+ starvation /= (se-avg.runnable_avg_sum + 1);
+
+ return scale_load(starvation);
+}
+
+static inline unsigned int hmp_offload_down(int cpu, struct sched_entity *se)
+{
+ int min_usage;
+ int dest_cpu = NR_CPUS;
+
+ if (hmp_cpu_is_slowest(cpu))
+ return NR_CPUS;
+
+ /* Is the current domain fully loaded? */
+ /* load ~94% */
+ min_usage = hmp_domain_min_load(hmp_cpu_domain(cpu), NULL);
+ if (min_usage NICE_0_LOAD-64)
+ return NR_CPUS;
+
+ /* Is the cpu oversubscribed? */
+ /* load ~194% */
+ if (cpu_rq(cpu)-cfs.tg_load_contrib 2*NICE_0_LOAD-64)
+ return NR_CPUS;
+
+ /* Is the task alone on the cpu? */
+ if (cpu_rq(cpu)-cfs.nr_running 2)
+ return NR_CPUS;
+
+ /* Is the task actually starving? */
+ if (hmp_task_starvation(se) 768) /* 25% waiting */
+ return NR_CPUS;
+
+ /* Does the slower domain have spare cycles? */
+ min_usage = hmp_domain_min_load(hmp_slower_domain(cpu), dest_cpu);
+ /* load 50% */
+ if (min_usage NICE_0_LOAD/2)
+ return NR_CPUS;
+
+ if (cpumask_test_cpu(dest_cpu, hmp_slower_domain(cpu)-cpus))
+ return dest_cpu;
+ return NR_CPUS;
+}
#endif /* CONFIG_SCHED_HMP */
/*
@@ -5643,10 +5717,14 @@ static unsigned int hmp_up_migration(int cpu, struct
sched_entity *se)
hmp_next_up_threshold)
return 0;
- if (se-avg.load_avg_ratio hmp_up_threshold
- cpumask_intersects(hmp_faster_domain(cpu)-cpus,
- tsk_cpus_allowed(p))) {
- return 1;
+ if (se-avg.load_avg_ratio hmp_up_threshold) {
+ /* Target domain load ~94% */
+ if (hmp_domain_min_load(hmp_faster_domain(cpu), NULL)
+NICE_0_LOAD-64)
+ return 0;
+ if (cpumask_intersects(hmp_faster_domain(cpu)-cpus,
+ tsk_cpus_allowed(p)))
+ return 1;
}
return 0;
}
@@ -5868,6 +5946,21 @@ static void hmp_force_up_migration(int this_cpu)
hmp_next_up_delay(p-se, target-push_cpu);
}
}
+ if (!force !target-active_balance) {
+ /*
+* For now we just check the currently running task.
+* Selecting the lightest task for offloading will
+* require extensive book keeping.
+*/
+ target-push_cpu = hmp_offload_down(cpu, curr);
+ if (target-push_cpu NR_CPUS) {
+ target-active_balance = 1;
+ target-migrate_task = p;
+ force = 1;
+ trace_sched_hmp_migrate(p, target-push_cpu, 2);
+ hmp_next_down_delay(p-se,
Re: [HMP][PATCH 0/1] Global balance
On Fri, Dec 7, 2012 at 5:33 PM, Morten Rasmussen morten.rasmus...@arm.com wrote: Hi Viresh, Here is a patch that introduces global load balancing on top of the existing HMP patch set. It depends on the HMP patches already present in your task-placement-v2 branch. It can be applied on top of the HMP sysfs patches if needed. The fix should be trivial. Could you include in the MP branch for the 12.12 release? Testing with sysbench and coremark show significant performance improvements for parallel workloads as all cpus can now be used for cpu intensive tasks. Morten, Can you share some performance number improvements and/or kernelshark-type graphs with and without this patch? It'd be very interesting to see the changes. Monday is the deadline to get this merged into the MP tree to make it to the release. It is end of week now. Not sure how much testing and review can be done before Monday. Your numbers might make a compelling argument. Regards, Amit Thanks, Morten Morten Rasmussen (1): sched: Basic global balancing support for HMP kernel/sched/fair.c | 101 +-- 1 file changed, 97 insertions(+), 4 deletions(-) -- 1.7.9.5 ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
[PATCH] configs: linaro-base: Set CONFIG_PROC_DEVICETREE=y
Both the Android and Ubuntu have QA tests which expect to be able to validate device-tree booting by looking in /proc/device-tree, so we should enable this for all Linaro builds. At the same time we can remove this option from ubuntu.conf as it's not an Ubuntu specific requirement. Signed-off-by: Jon Medhurst t...@linaro.org --- I'll push this out to the configs branch soon, but mailing this patch out for visibility and to give some time for any comments... linaro/configs/linaro-base.conf |1 + linaro/configs/ubuntu.conf |1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/linaro/configs/linaro-base.conf b/linaro/configs/linaro-base.conf index eaf0196..23638c3 100644 --- a/linaro/configs/linaro-base.conf +++ b/linaro/configs/linaro-base.conf @@ -87,3 +87,4 @@ CONFIG_CRC7=y CONFIG_HW_PERF_EVENTS=y CONFIG_FUNCTION_TRACER=y CONFIG_ENABLE_DEFAULT_TRACERS=y +CONFIG_PROC_DEVICETREE=y diff --git a/linaro/configs/ubuntu.conf b/linaro/configs/ubuntu.conf index fafabe1..b65be64 100644 --- a/linaro/configs/ubuntu.conf +++ b/linaro/configs/ubuntu.conf @@ -721,7 +721,6 @@ CONFIG_MTD_LPDDR=m CONFIG_MTD_QINFO_PROBE=m CONFIG_DTC=y CONFIG_OF=y -CONFIG_PROC_DEVICETREE=y CONFIG_OF_FLATTREE=y CONFIG_OF_EARLY_FLATTREE=y CONFIG_OF_ADDRESS=y -- 1.7.10.4 ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
Re: [HMP][PATCH 0/1] Global balance
Hi Amit, I should have included the numbers in the cover letter. Here are numbers for TC2. sysbench (normalized execution time, lower is better) threads 2 4 8 HMP 1.00 1.00 1.00 HMP+GB1.00 0.67 0.58 coremark (normalized iterations per second, higher is better) threads 2 4 8 HMP 1.00 1.00 1.00 HMP+GB 1.00 1.39 1.73 So there is clear benefit of utilizing the A7s. It actually saves energy too as the whole benchmark completes faster. Regards, Morten On Fri, Dec 7, 2012 at 12:14 PM, Amit Kucheria amit.kuche...@linaro.org wrote: On Fri, Dec 7, 2012 at 5:33 PM, Morten Rasmussen morten.rasmus...@arm.com wrote: Hi Viresh, Here is a patch that introduces global load balancing on top of the existing HMP patch set. It depends on the HMP patches already present in your task-placement-v2 branch. It can be applied on top of the HMP sysfs patches if needed. The fix should be trivial. Could you include in the MP branch for the 12.12 release? Testing with sysbench and coremark show significant performance improvements for parallel workloads as all cpus can now be used for cpu intensive tasks. Morten, Can you share some performance number improvements and/or kernelshark-type graphs with and without this patch? It'd be very interesting to see the changes. Monday is the deadline to get this merged into the MP tree to make it to the release. It is end of week now. Not sure how much testing and review can be done before Monday. Your numbers might make a compelling argument. Regards, Amit Thanks, Morten Morten Rasmussen (1): sched: Basic global balancing support for HMP kernel/sched/fair.c | 101 +-- 1 file changed, 97 insertions(+), 4 deletions(-) -- 1.7.9.5 ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
Re: [PATCH] configs: linaro-base: Set CONFIG_PROC_DEVICETREE=y
Both the Android and Ubuntu have QA tests which expect to be able to validate device-tree booting by looking in /proc/device-tree, so we should enable this for all Linaro builds. At the same time we can remove this option from ubuntu.conf as it's not an Ubuntu specific requirement. Signed-off-by: Jon Medhurst t...@linaro.org Acked-by: Fathi Boudra fathi.bou...@linaro.org --- I'll push this out to the configs branch soon, but mailing this patch out for visibility and to give some time for any comments... linaro/configs/linaro-base.conf |1 + linaro/configs/ubuntu.conf |1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/linaro/configs/linaro-base.conf b/linaro/configs/linaro-base.conf index eaf0196..23638c3 100644 --- a/linaro/configs/linaro-base.conf +++ b/linaro/configs/linaro-base.conf @@ -87,3 +87,4 @@ CONFIG_CRC7=y CONFIG_HW_PERF_EVENTS=y CONFIG_FUNCTION_TRACER=y CONFIG_ENABLE_DEFAULT_TRACERS=y +CONFIG_PROC_DEVICETREE=y diff --git a/linaro/configs/ubuntu.conf b/linaro/configs/ubuntu.conf index fafabe1..b65be64 100644 --- a/linaro/configs/ubuntu.conf +++ b/linaro/configs/ubuntu.conf @@ -721,7 +721,6 @@ CONFIG_MTD_LPDDR=m CONFIG_MTD_QINFO_PROBE=m CONFIG_DTC=y CONFIG_OF=y -CONFIG_PROC_DEVICETREE=y CONFIG_OF_FLATTREE=y CONFIG_OF_EARLY_FLATTREE=y CONFIG_OF_ADDRESS=y -- 1.7.10.4 ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
Re: [HMP][PATCH 0/1] Global balance
On 7 December 2012 18:43, Morten Rasmussen morten.rasmus...@arm.com wrote: I should have included the numbers in the cover letter. Here are numbers for TC2. sysbench (normalized execution time, lower is better) threads 2 4 8 HMP 1.00 1.00 1.00 HMP+GB1.00 0.67 0.58 coremark (normalized iterations per second, higher is better) threads 2 4 8 HMP 1.00 1.00 1.00 HMP+GB 1.00 1.39 1.73 So there is clear benefit of utilizing the A7s. It actually saves energy too as the whole benchmark completes faster. Hi Morten, I have applied your patch now and pushed v13. Please cross-check v13 to see if everything is correct. ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
Re: [HMP][PATCH 0/1] Global balance
On 07/12/12 14:54, Viresh Kumar wrote: On 7 December 2012 18:43, Morten Rasmussen morten.rasmus...@arm.com wrote: I should have included the numbers in the cover letter. Here are numbers for TC2. sysbench (normalized execution time, lower is better) threads 2 4 8 HMP 1.00 1.00 1.00 HMP+GB1.00 0.67 0.58 coremark (normalized iterations per second, higher is better) threads 2 4 8 HMP 1.00 1.00 1.00 HMP+GB 1.00 1.39 1.73 So there is clear benefit of utilizing the A7s. It actually saves energy too as the whole benchmark completes faster. Hi Morten, I have applied your patch now and pushed v13. Please cross-check v13 to see if everything is correct. It looks right to me. Morten -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
