Re: ASUS P5W motherboard PMP

2007-08-03 Thread David Madsen
Yes, I patched the 2.6.22.1 vanilla kernel with the libata patch from here.

http://home-tj.org/files/libata-tj-stable/libata-tj-2.6.22.1-20070803.tar.bz2

--David Madsen

On 8/3/07, Tejun Heo <[EMAIL PROTECTED]> wrote:
> David Madsen wrote:
> > * The long boot delay on ASUS boards with on-board PMP chips should be
> >   fixed by this patchset but I don't have such a board or Sil4723
> >   which is used on those boards, so I'm not sure.  Anyone up for
> >
> >   testing?
> >
> > Hi Tejun,
> >
> >   I have one of the above mentioned ASUS motherboards that has a PMP device 
> > connected
> > to one of the SATA ports on the ICH7R southbridge.  I came across your 
> > libata patches
> > and mention of a tester for this motherboard so I downloaded the patchset 
> > and tried it
> >
> > on my motherboard.  Booting with the new kernel appears to have the same 
> > errors and delay
> > that the previous kernel had.
> >
> > I have attached a tar file with the dmesg output as well as my kernel's 
> > .config.  I'm not
> >
> > sure what else may be of use to you to help with the debugging so let me 
> > know if I can
> > provide you with any more info.
>
> Please cc linux-ide@vger.kernel.org next time.
>
> You patched the kernel with PMP patches, right?
>
> --
> tejun
>
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Re: ICH8 CF timeout (regression)...

2007-08-03 Thread Tejun Heo
Daniel J Blueman wrote:
> Tejun,
> 
> On 03/08/07, Tejun Heo <[EMAIL PROTECTED]> wrote:
>> Daniel J Blueman wrote:
>>> The ICH8 south-bridge I have is the mobile variant and does come
>>> equipped with native parallel IDE - see page 447:
>>> http://download.intel.com/design/chipsets/datashts/31305603.pdf . I do
>>> see 35MB/s with DMA enabled from my CF on the 1 in 15 times the
>>> libata-kernel does work.
>>>
>>> I can dump off and decode the configuration registers for the timing
>>> and bus master registers in the working and non-working libata cases,
>>> and the legacy ATA working case and see what's different.
>> Does the attached patch change anything?
> 
> This addresses the issue 100%!
> 
> Due to the differences between the ICH8 non-mobile and mobile
> variants, I've cooked the change into a new initialisation structure
> for the ICH8M in the attached patch, if that helps at all.
> 
> The changes thus affect (correct) behaviour on the ICH8M in IDE mode
> only...so should be safe for inclusion. There may be a similar
> situation with ICH9Ms also.

[cc'ing Kristen, hello]

I think [P0 P2 IDE IDE] is correct for MAP 01b but can't find anything
about it in the datasheet or spec update.  Kristen, can you please
verify this.  The following bug is also fixed by using [P0 P2 IDE IDE].

http://bugzilla.kernel.org/show_bug.cgi?id=8809

Thanks.

-- 
tejun
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Re: [PATCH -mm] libata: add human-readable error value decoding v3

2007-08-03 Thread Chuck Ebbert
On 08/03/2007 02:00 PM, Robert Hancock wrote:
> This adds human-readable decoding of the ATA status and error registers
> (similar to what drivers/ide does) as well as the SATA Serror register to
> libata error handling output.  This prevents the need to pore through
> standards documents to figure out the meaning of the bits in these
> registers when looking at error reports.  Some bits that drivers/ide
> decoded are not decoded here, since the bits are either command-dependent
> or obsolete, and properly parsing them would add too much complexity.
> 

This is really nice.

Maybe make it configurable, though?
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Re: 2.6.23-rc1: pata_via cable detection differs from via82cxxx

2007-08-03 Thread Bartlomiej Zolnierkiewicz
On Saturday 04 August 2007, Alan Cox wrote:
> On Fri, 3 Aug 2007 20:28:39 +0200 (MEST)
> Mikael Pettersson <[EMAIL PROTECTED]> wrote:
> 
> > The machine is an Athlon64 laptop with a K8T800 chipset. With the IDE
> > VIA driver the disk is detected as udma/100:
> 
> Currently old IDE via driver has a hack in it which goes 'did the BIOS
> set UDMA3+' then I guess the cable is 80 wire regardless. libata doesn't
> do that as it breaks with hotplug, breaks with suspend/resume before the
> driver is loaded and other bits.
> 
> Instead we have two things - an ACPI snoop and a table of wonky laptops
> (eg those that use 40 wire ultrashort cables which are valid for UDMA133
> but not detected as 80 wire). If your laptop is done that way then it
> just needs adding to the magic list and/or 2.6.23-rc1-mm should spot it
> by ACPI. I'd prefer the table entry anyway as I don't like relying on ACPI
> so an lspci -vvxx would be appreciated

Please also add it to the laptop table in IDE VIA driver.

Thanks,
Bart
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Re: [PATCH] ide: move ide_config_drive_speed() calls to upper layers

2007-08-03 Thread Bartlomiej Zolnierkiewicz

Hi,

On Saturday 28 July 2007, Sergei Shtylyov wrote:
> Hello.
> 
> Bartlomiej Zolnierkiewicz wrote:
> 
> >>On Fri, 27 Jul 2007 02:22:27 +0200
> >>Bartlomiej Zolnierkiewicz <[EMAIL PROTECTED]> wrote:
> 
> >>>* Convert {ide_hwif_t,ide_pci_device_t}->host_flag to be u16.
> 
> >>>* Add IDE_HFLAG_POST_SET_MODE host to indicate the need to program the
> >>>  host for the transfer mode after programming the device.  Set it in
> >>>  au1xxx-ide/cs5530/cs5535/pdc202xx_new/sc1200/via82cxxx host drivers.
> 
> >>The CS5530 at least shouldn't care what order changes are done. I don't
> 
> And neither CS5535. And Au1200 static bus controller shouldn't care about 
> the order too, so au1xxx-ide hardly needs that.
> 
> Here's the datasheet, BTW:
> 
> http://www.razamicroelectronics.com/documents/32798e_Au1200_db.pdf
> 
> >>think the SC1200 does either but I don't have the docs to hand.
> 
> It seems pretty much alike CS553x except it's accessed via PCI config. 
> space, not MSRs... Here's the datasheet:
> 
> http://www.amd.com/files/connectivitysolutions/geode/32579B_sc1200_ds.pdf

Thanks for links to specs.

> I have a feeling that only pdc202xx_new and jmicron drivers actually need 
> this flag (and the latter one actually doesn't care as its methods are empty 
> anyway).  Well, AMD/VIA chips enable UltraDMA mode by snooping Set Features 
> command (as the drivers tell them to do so), so the order seems important 
> unless that is changed.

Since changing of order affects the way in which hardware is accessed
I prefer to keep such changes out of this patch (which is just a cleanup).

Could you please handle them in pre or post patch(es)?

Bart
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Re: ICH8 CF timeout (regression)...

2007-08-03 Thread Daniel J Blueman
Tejun,

On 03/08/07, Tejun Heo <[EMAIL PROTECTED]> wrote:
> Daniel J Blueman wrote:
> > The ICH8 south-bridge I have is the mobile variant and does come
> > equipped with native parallel IDE - see page 447:
> > http://download.intel.com/design/chipsets/datashts/31305603.pdf . I do
> > see 35MB/s with DMA enabled from my CF on the 1 in 15 times the
> > libata-kernel does work.
> >
> > I can dump off and decode the configuration registers for the timing
> > and bus master registers in the working and non-working libata cases,
> > and the legacy ATA working case and see what's different.
>
> Does the attached patch change anything?

This addresses the issue 100%!

Due to the differences between the ICH8 non-mobile and mobile
variants, I've cooked the change into a new initialisation structure
for the ICH8M in the attached patch, if that helps at all.

The changes thus affect (correct) behaviour on the ICH8M in IDE mode
only...so should be safe for inclusion. There may be a similar
situation with ICH9Ms also.

Thanks once again to all who helped!
  Daniel
-- 
Daniel J Blueman
diff -urN linux-2.6.23-rc1.orig/drivers/ata/ata_piix.c linux-2.6.23-rc1/drivers/ata/ata_piix.c
--- linux-2.6.23-rc1.orig/drivers/ata/ata_piix.c	2007-08-03 21:29:02.0 +0100
+++ linux-2.6.23-rc1/drivers/ata/ata_piix.c	2007-08-03 21:24:53.0 +0100
@@ -128,7 +128,8 @@
 	ich6_sata_ahci		= 7,
 	ich6m_sata_ahci		= 8,
 	ich8_sata_ahci		= 9,
-	piix_pata_mwdma		= 10,	/* PIIX3 MWDMA only */
+	ich8m_sata_ahci		= 10,
+	piix_pata_mwdma		= 11,	/* PIIX3 MWDMA only */
 
 	/* constants for mapping table */
 	P0			= 0,  /* port 0 */
@@ -232,7 +233,7 @@
 	/* SATA Controller 2 IDE (ICH8) */
 	{ 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
 	/* Mobile SATA Controller IDE (ICH8M) */
-	{ 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
+	{ 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8m_sata_ahci },
 	/* SATA Controller IDE (ICH9) */
 	{ 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
 	/* SATA Controller IDE (ICH9) */
@@ -428,7 +429,19 @@
 		/* PM   PS   SM   SS   MAP */
 		{  P0,  P2,  P1,  P3 }, /* 00b (hardwired when in AHCI) */
 		{  RV,  RV,  RV,  RV },
-		{  IDE,  IDE,  NA,  NA }, /* 10b (IDE mode) */
+		{ IDE, IDE,  NA,  NA }, /* 10b (IDE mode) */
+		{  RV,  RV,  RV,  RV },
+	},
+};
+
+static const struct piix_map_db ich8m_map_db = {
+	.mask = 0x3,
+	.port_enable = 0x3,
+	.map = {
+		/* PM   PS   SM   SS   MAP */
+		{  P0,  P2,  P1,  P3 }, /* 00b (hardwired when in AHCI) */
+		{  RV,  RV,  RV,  RV },
+		{  P0,  P2, IDE, IDE }, /* 10b (IDE mode) */
 		{  RV,  RV,  RV,  RV },
 	},
 };
@@ -439,6 +452,7 @@
 	[ich6_sata_ahci]	= &ich6_map_db,
 	[ich6m_sata_ahci]	= &ich6m_map_db,
 	[ich8_sata_ahci]	= &ich8_map_db,
+	[ich8m_sata_ahci]	= &ich8m_map_db,
 };
 
 static struct ata_port_info piix_port_info[] = {
@@ -544,7 +558,18 @@
 		.port_ops	= &piix_sata_ops,
 	},
 
-	/* piix_pata_mwdma: 10:  PIIX3 MWDMA only */
+	/* ich8m_sata_ahci: 10 */
+	{
+		.sht		= &piix_sht,
+		.flags		= PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
+  PIIX_FLAG_AHCI,
+		.pio_mask	= 0x1f,	/* pio0-4 */
+		.mwdma_mask	= 0x07, /* mwdma0-2 */
+		.udma_mask	= ATA_UDMA6,
+		.port_ops	= &piix_sata_ops,
+	},
+
+	/* piix_pata_mwdma: 11:  PIIX3 MWDMA only */
 	{
 		.sht		= &piix_sht,
 		.flags		= PIIX_PATA_FLAGS,


Re: 2.6.23-rc1: pata_via cable detection differs from via82cxxx

2007-08-03 Thread Alan Cox
On Fri, 3 Aug 2007 20:28:39 +0200 (MEST)
Mikael Pettersson <[EMAIL PROTECTED]> wrote:

> The machine is an Athlon64 laptop with a K8T800 chipset. With the IDE
> VIA driver the disk is detected as udma/100:

Currently old IDE via driver has a hack in it which goes 'did the BIOS
set UDMA3+' then I guess the cable is 80 wire regardless. libata doesn't
do that as it breaks with hotplug, breaks with suspend/resume before the
driver is loaded and other bits.

Instead we have two things - an ACPI snoop and a table of wonky laptops
(eg those that use 40 wire ultrashort cables which are valid for UDMA133
but not detected as 80 wire). If your laptop is done that way then it
just needs adding to the magic list and/or 2.6.23-rc1-mm should spot it
by ACPI. I'd prefer the table entry anyway as I don't like relying on ACPI
so an lspci -vvxx would be appreciated
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Re: [PATCH -mm] libata: add human-readable error value decoding v3

2007-08-03 Thread Alan Cox
On Fri, 03 Aug 2007 12:00:57 -0600
Robert Hancock <[EMAIL PROTECTED]> wrote:

> This adds human-readable decoding of the ATA status and error registers
> (similar to what drivers/ide does) as well as the SATA Serror register to
> libata error handling output.  This prevents the need to pore through
> standards documents to figure out the meaning of the bits in these
> registers when looking at error reports.  Some bits that drivers/ide
> decoded are not decoded here, since the bits are either command-dependent
> or obsolete, and properly parsing them would add too much complexity.

Not sure its really worth it. Does "ABRT IDNF" actually tell you any more
than the hex code ? In fact I find the hex code clearer because its
usually the combination of state (0x51) etc that tells the story.

No objection to it going in and on a correctness basis

Acked-by: Alan Cox <[EMAIL PROTECTED]>
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2.6.23-rc1: pata_via cable detection differs from via82cxxx

2007-08-03 Thread Mikael Pettersson
The machine is an Athlon64 laptop with a K8T800 chipset. With the IDE
VIA driver the disk is detected as udma/100:

VP_IDE: IDE controller at PCI slot :00:11.1
ACPI: PCI Interrupt Link [ALKA] disabled and referenced, BIOS bug
ACPI: PCI Interrupt Link [ALKA] BIOS reported IRQ 0, using IRQ 23
ACPI: PCI Interrupt Link [ALKA] enabled at IRQ 23
ACPI: PCI Interrupt :00:11.1[A] -> Link [ALKA] -> GSI 23 (level, low) -> 
IRQ 17
VP_IDE: chipset revision 6
VP_IDE: not 100% native mode: will probe irqs later
VP_IDE: VIA vt8235 (rev 00) IDE UDMA133 controller on pci:00:11.1
ide0: BM-DMA at 0x1ce0-0x1ce7, BIOS settings: hda:DMA, hdb:pio
ide1: BM-DMA at 0x1ce8-0x1cef, BIOS settings: hdc:DMA, hdd:pio
Probing IDE interface ide0...
hda: TOSHIBA MK6021GAS, ATA DISK drive
hda: selected mode 0x45
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
Probing IDE interface ide1...
hdc: TOSHIBA ODD-DVD SD-R6372, ATAPI CD/DVD-ROM drive
hdc: selected mode 0x42
ide1 at 0x170-0x177,0x376 on irq 15
hda: max request size: 128KiB
hda: 117210240 sectors (60011 MB), CHS=65535/16/63, UDMA(100)
hda: cache flushes supported
 hda: hda1 hda2 hda3 hda4 < hda5 hda6 hda7 hda8 hda9 >

However, the libata pata_via driver complains about the cable and
drops the disk to udma/33:

pata_via :00:11.1: version 0.3.1
ACPI: PCI Interrupt Link [ALKA] disabled and referenced, BIOS bug
ACPI: PCI Interrupt Link [ALKA] BIOS reported IRQ 0, using IRQ 23
ACPI: PCI Interrupt Link [ALKA] enabled at IRQ 23
ACPI: PCI Interrupt :00:11.1[A] -> Link [ALKA] -> GSI 23 (level, low) -> 
IRQ 17
scsi0 : pata_via
scsi1 : pata_via
ata1: PATA max UDMA/133 cmd 0x000101f0 ctl 0x000103f6 bmdma 0x00011ce0 irq 14
ata2: PATA max UDMA/133 cmd 0x00010170 ctl 0x00010376 bmdma 0x00011ce8 irq 15
ata1.00: ATA-5: TOSHIBA MK6021GAS, GA024A, max UDMA/100
ata1.00: 117210240 sectors, multi 16: LBA 
ata1.00: limited to UDMA/33 due to 40-wire cable
ata1.00: configured for UDMA/33
ata2.00: ATAPI: TOSHIBA ODD-DVD SD-R6372, 1030, max UDMA/33
ata2.00: configured for UDMA/33
scsi 0:0:0:0: Direct-Access ATA  TOSHIBA MK6021GA GA02 PQ: 0 ANSI: 5
sd 0:0:0:0: [sda] 117210240 512-byte hardware sectors (60012 MB)
sd 0:0:0:0: [sda] Write Protect is off
sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support 
DPO or FUA
sd 0:0:0:0: [sda] 117210240 512-byte hardware sectors (60012 MB)
sd 0:0:0:0: [sda] Write Protect is off
sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support 
DPO or FUA
 sda: sda1 sda2 sda3 sda4 < sda5 sda6 sda7 sda8 sda9 >
sd 0:0:0:0: [sda] Attached SCSI disk
scsi 1:0:0:0: CD-ROMTOSHIBA  ODD-DVD SD-R6372 1030 PQ: 0 ANSI: 5

hdparm -i confirms this: with the IDE driver it lists udma5 as
the current mode, with pata_via it lists udma2 as the current mode.

/Mikael
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Re: [PATCH] slc90e66: always tune PIO

2007-08-03 Thread Sergei Shtylyov

Hello.

Bartlomiej Zolnierkiewicz wrote:


Signed-off-by: Bartlomiej Zolnierkiewicz <[EMAIL PROTECTED]>


   Note that setting DMA modes will set the chipset to PIO4.

Acked-by: Sergei Shtylyov <[EMAIL PROTECTED]>

MBR, Sergei
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[PATCH -mm] libata: add human-readable error value decoding v3

2007-08-03 Thread Robert Hancock
This adds human-readable decoding of the ATA status and error registers
(similar to what drivers/ide does) as well as the SATA Serror register to
libata error handling output.  This prevents the need to pore through
standards documents to figure out the meaning of the bits in these
registers when looking at error reports.  Some bits that drivers/ide
decoded are not decoded here, since the bits are either command-dependent
or obsolete, and properly parsing them would add too much complexity.

Signed-off-by: Robert Hancock <[EMAIL PROTECTED]>

---

Rebased to apply to 2.6.23-rc1-mm2.

--- linux-2.6.23-rc1-mm2/include/linux/ata.h2007-08-02 16:13:24.0 
-0600
+++ linux-2.6.23-rc1-mm2edit/include/linux/ata.h2007-08-02 
16:37:23.0 -0600
@@ -274,6 +274,15 @@ enum {
SERR_PROTOCOL   = (1 << 10), /* protocol violation */
SERR_INTERNAL   = (1 << 11), /* host internal error */
SERR_PHYRDY_CHG = (1 << 16), /* PHY RDY changed */
+   SERR_PHY_INT_ERR= (1 << 17), /* PHY internal error */
+   SERR_COMM_WAKE  = (1 << 18), /* Comm wake */
+   SERR_10B_8B_ERR = (1 << 19), /* 10b to 8b decode error */
+   SERR_DISPARITY  = (1 << 20), /* Disparity */
+   SERR_CRC= (1 << 21), /* CRC error */
+   SERR_HANDSHAKE  = (1 << 22), /* Handshake error */
+   SERR_LINK_SEQ_ERR   = (1 << 23), /* Link sequence error */
+   SERR_TRANS_ST_ERROR = (1 << 24), /* Transport state trans. error */
+   SERR_UNRECOG_FIS= (1 << 25), /* Unrecognized FIS */
SERR_DEV_XCHG   = (1 << 26), /* device exchanged */
 
/* struct ata_taskfile flags */
--- linux-2.6.23-rc1-mm2/drivers/ata/libata-eh.c2007-08-02 
16:13:11.0 -0600
+++ linux-2.6.23-rc1-mm2edit/drivers/ata/libata-eh.c2007-08-02 
16:35:58.0 -0600
@@ -1698,6 +1698,27 @@ static void ata_eh_report(struct ata_por
ata_port_printk(ap, KERN_ERR, "%s\n", desc);
}
 
+   if (ehc->i.serror)
+   ata_port_printk(ap, KERN_ERR,
+ "SError: {%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s}\n",
+ ehc->i.serror & SERR_DATA_RECOVERED ? "RecovData " : "",
+ ehc->i.serror & SERR_COMM_RECOVERED ? "RecovComm " : "",
+ ehc->i.serror & SERR_DATA ? "UnrecovData " : "",
+ ehc->i.serror & SERR_PERSISTENT ? "Persist " : "",
+ ehc->i.serror & SERR_PROTOCOL ? "Proto " : "",
+ ehc->i.serror & SERR_INTERNAL ? "HostInt " : "",
+ ehc->i.serror & SERR_PHYRDY_CHG ? "PHYRdyChg " : "",
+ ehc->i.serror & SERR_PHY_INT_ERR ? "PHYInt " : "",
+ ehc->i.serror & SERR_COMM_WAKE ? "CommWake " : "",
+ ehc->i.serror & SERR_10B_8B_ERR ? "10B8B " : "",
+ ehc->i.serror & SERR_DISPARITY ? "Dispar " : "",
+ ehc->i.serror & SERR_CRC ? "BadCRC " : "",
+ ehc->i.serror & SERR_HANDSHAKE ? "Handshk " : "",
+ ehc->i.serror & SERR_LINK_SEQ_ERR ? "LinkSeq " : "",
+ ehc->i.serror & SERR_TRANS_ST_ERROR ? "TrStaTrns " : "",
+ ehc->i.serror & SERR_UNRECOG_FIS ? "UnrecFIS " : "",
+ ehc->i.serror & SERR_DEV_XCHG ? "DevExch " : "" );
+
for (tag = 0; tag < ATA_MAX_QUEUE; tag++) {
static const char *dma_str[] = {
[DMA_BIDIRECTIONAL] = "bidi",
@@ -1728,6 +1749,30 @@ static void ata_eh_report(struct ata_por
res->hob_lbal, res->hob_lbam, res->hob_lbah,
res->device, qc->err_mask, ata_err_string(qc->err_mask),
qc->err_mask & AC_ERR_NCQ ? " " : "");
+
+   if (res->command & (ATA_BUSY | ATA_DRDY | ATA_DF | ATA_DRQ |
+   ATA_ERR) ) {
+   if (res->command & ATA_BUSY)
+   ata_dev_printk(qc->dev, KERN_ERR,
+ "status: {Busy}\n" );
+   else
+   ata_dev_printk(qc->dev, KERN_ERR,
+ "status: {%s%s%s%s}\n",
+ res->command & ATA_DRDY ? "DRDY " : "",
+ res->command & ATA_DF ? "DF " : "",
+ res->command & ATA_DRQ ? "DRQ " : "",
+ res->command & ATA_ERR ? "ERR " : "" );
+   }
+
+   if (cmd->command != ATA_CMD_PACKET &&
+   (res->feature & (ATA_ICRC | ATA_UNC | ATA_IDNF |
+ATA_ABORTED)))
+   ata_dev_printk(qc->dev, KERN_ERR,
+ "error: {%s%s%s%s}\n",
+ res->feature & ATA_ICRC ? "ICRC " : "",
+ res->feature & ATA_UNC ? "UNC " : "",
+   

Re: libata git tree, mbox queue status and contents

2007-08-03 Thread Alan Cox
> * Alan: IORDY handling -- upstream whenever Alan is happy

I'm happy with it from testing. Just a little worried about it going
upstream mid -rc as it could have a weird side effect somewhere. I've
verified an original pre ATA IDE drive with it too now 8)

> * Alan: ACPI checks for 80wire cable -- upstream whenever Alan is happy

Happy

> * Albert: irq_on/off.  Really need to give this some thought.  Not sure 
> I like where this model is going.  Polling and twiddling irq on/off 
> should be kept to a minimum, because it's sorta an admission that the 
> host state machine has broken down, and we need to bandaid.  Its a 
> bandaid not a root-cause solution.

I think of it more as an admission that the IDE design is lacking in a
few areas. No suprise as its an emulation of a 15 year old interface that
was normally used polled.

> * Ben Collins: cleanup HPA support.  Need to review and see what's 
> needed today, from this patch.

We need to track the HPA case Bartlomiej is working on with old IDE - one
drive out there is reporting its geometry wrong.
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libata git tree, mbox queue status and contents

2007-08-03 Thread Jeff Garzik
This is a quick guide to current libata work that is queued or in 
progress in some way, shape or form.


First, a guide to the branches currently in use in 
git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev.git


  ALL

Everything that is exported for testing (and akpm's -mm tree). 
Currently consists of upstream-fixes + upstream + sil680-mmio branches.



  master

Vanilla upstream linux-2.6.git tree.


  mv-ahci-pata

Marvell 6121/6141 PATA support.  Needs fixing in the 'PATA controller 
command' area before it is usable, and can go upstream.



  mv-ncq

sata_mv NCQ support.  Code is complete and /should/ be working, but it 
does nothing but timeout and fallback to non-NCQ here.  Needs debugging 
before can go upstream.



  new-eh

Convert sata_qstor and sata_sx4 to new EH.  Each needs 
testing/verification before it can go upstream.



  pmask

Add proto_mask to LLDDs, alongside pio_mask, udma_mask, etc.


  sii-lbt

Enable Large Block Transfer mode on sata_sil.  Verified to work locally, 
but some bug reports on the 'net need to be tracked down before this can 
go upstream.



  sil680-mmio

BenH's MMIO patch for pata_sil680.  Some MMIO/flushing type issues were 
raised on the list, a solution was reached.  That solution must be coded 
before this can go upstream.



  upstream

Everything queued for 2.6.24.  Includes everything in upstream-fixes.


  upstream-fixes

Everything queued for 2.6.23-rc.  This tends to go upstream rapidly.




mbox queue, prefixed by author:

* Kristen: ALPM patches.  We definitely want them, as they save a ton of 
power.


* Tony Vroon: LED trigger  hmmm

* Alan: IORDY handling -- upstream whenever Alan is happy

* Tejun: improved probe info printout.  Want to test and review in 
depth, but probably OK


* Alan: ACPI checks for 80wire cable -- upstream whenever Alan is happy

* Tejun:  Port Multiplier Support -- I still need to review in depth, 
but would like go ahead and push ata_link in


* NVIDIA: sata_nv SW NCQ: need to review WRT FIS state machine, though I 
saw some flaws in there.  OK if that is OK.


* Albert: irq_on/off.  Really need to give this some thought.  Not sure 
I like where this model is going.  Polling and twiddling irq on/off 
should be kept to a minimum, because it's sorta an admission that the 
host state machine has broken down, and we need to bandaid.  Its a 
bandaid not a root-cause solution.


* Albert: minor PIO fixes.  Need to review in depth.

* Kristen: AN: it seems that things got stuck once Al Viro voiced an 
objection?


* Ben Collins: cleanup HPA support.  Need to review and see what's 
needed today, from this patch.


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Re: [PATCH] sata_qstor, pdc_adma, sata_sx4: convert to new EH

2007-08-03 Thread Jeff Garzik

Tejun Heo wrote:

Jeff Garzik wrote:

This is just a refresh of the existing libata-dev.git#new-eh patches
that convert all remaining old-EH drivers to new EH, against 2.6.23-rc1.

All three conversions are completely untested.  pdc_adma and sata_qstor
need reviewing by someone with docs, in addition to testing.

Even "it still works" or "this patch breaks stuff" feedback from users
is useful.


pdc_adma works fine.  Tested both a harddrive and a cdrom.  ATAPI check
sense seems to work and harddrive was successfully recovered from
timeout induced by shaking the harddisk for 30s.  :-)


Thanks!  I'll push pdc_adma new-EH conversion into #upstream.

Jeff



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Re: [PATCH] sata_qstor, pdc_adma, sata_sx4: convert to new EH

2007-08-03 Thread Tejun Heo
Jeff Garzik wrote:
> This is just a refresh of the existing libata-dev.git#new-eh patches
> that convert all remaining old-EH drivers to new EH, against 2.6.23-rc1.
> 
> All three conversions are completely untested.  pdc_adma and sata_qstor
> need reviewing by someone with docs, in addition to testing.
> 
> Even "it still works" or "this patch breaks stuff" feedback from users
> is useful.

pdc_adma works fine.  Tested both a harddrive and a cdrom.  ATAPI check
sense seems to work and harddrive was successfully recovered from
timeout induced by shaking the harddisk for 30s.  :-)

-- 
tejun
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Re: Boot fails on Intel SATA controller

2007-08-03 Thread Tejun Heo
Quel Qun wrote:
> ATA device, with non-removable media
> powers-up in standby; SET FEATURES subcmd spins-up.
> Model Number:   HDS724040KLSA80 
> Serial Number:  KRFS11RAGT2EZC
> Firmware Revision:  KFAOA20N
> Standards:
> Used: ATA/ATAPI-7 T13 1532D revision 1 
> Supported: 7 6 5 4 
> Configuration:
> Logical max current
> cylinders   16383   16383
> heads   16  16
> sectors/track   63  63
> --
> CHS current addressable sectors:   16514064
> LBAuser addressable sectors:  268435455
> LBA48  user addressable sectors:  781422768
> device size with M = 1024*1024:  381554 MBytes
> device size with M = 1000*1000:  400088 MBytes (400 GB)
> Capabilities:
> LBA, IORDY(can be disabled)
> Standby timer values: spec'd by Standard, no device specific minimum
> R/W multiple sector transfer: Max = 16  Current = 8
> Advanced power management level: unknown setting (0x)
> Recommended acoustic management value: 128, current value: 128
> DMA: mdma0 mdma1 mdma2 udma0 udma1 udma2 udma3 udma4 udma5 *udma6 
>  Cycle time: min=120ns recommended=120ns
> PIO: pio0 pio1 pio2 pio3 pio4 
>  Cycle time: no flow control=240ns  IORDY flow control=120ns
> Commands/features:
> Enabled Supported:
>*SMART feature set
> Security Mode feature set
>*Power Management feature set
>*Write cache
>*Look-ahead
>*Host Protected Area feature set

This is weird.  HPA is supported && enabled but
read_native_max_address_ext times out.  Can you post the result of
'hdparm --Istdout /dev/sda'?

-- 
tejun
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Re: ICH8 CF timeout (regression)...

2007-08-03 Thread Tejun Heo
Daniel J Blueman wrote:
> The ICH8 south-bridge I have is the mobile variant and does come
> equipped with native parallel IDE - see page 447:
> http://download.intel.com/design/chipsets/datashts/31305603.pdf . I do
> see 35MB/s with DMA enabled from my CF on the 1 in 15 times the
> libata-kernel does work.
> 
> I can dump off and decode the configuration registers for the timing
> and bus master registers in the working and non-working libata cases,
> and the legacy ATA working case and see what's different.

Does the attached patch change anything?

-- 
tejun
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c
index ad07086..47a344b 100644
--- a/drivers/ata/ata_piix.c
+++ b/drivers/ata/ata_piix.c
@@ -436,7 +436,7 @@ static const struct piix_map_db ich8_map_db = {
 		/* PM   PS   SM   SS   MAP */
 		{  P0,  P2,  P1,  P3 }, /* 00b (hardwired when in AHCI) */
 		{  RV,  RV,  RV,  RV },
-		{  IDE,  IDE,  NA,  NA }, /* 10b (IDE mode) */
+		{  P0,  P2, IDE, IDE }, /* 10b (IDE mode) */
 		{  RV,  RV,  RV,  RV },
 	},
 };


Re: ICH8 CF timeout (regression)...

2007-08-03 Thread Daniel J Blueman
On 02/08/07, Mark Lord <[EMAIL PROTECTED]> wrote:
> Daniel J Blueman wrote:
> > On 02/08/07, Tejun Heo <[EMAIL PROTECTED]> wrote:
> >> Daniel J Blueman wrote:
> >>> I'll grab kernel logs from the legacy ATA boot; what else can help
> >>> debug this issue? No problem testing patches too.
> >> Yeap, please post the old log.
> >
> > Not much actually - perhaps I need to enable some debugging:
> >
> > Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
> > ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
> > hdc: SanDisk SDCFX-4096, CFA DISK drive
> > ide1 at 0x170-0x177,0x376 on irq 15
> > hdc: max request size: 128KiB
> > hdc: 8027712 sectors (4110 MB) w/1KiB Cache, CHS=7964/16/63
> >  hdc: hdc1 hdc2 hdc3
> >
> >>> --- [2]
> >>> ata2.00: limiting speed to UDMA/33:PIO4
> >>> ata2.00: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x2 frozen
> >>> ata2.00: cmd c8/00:08:00:00:00/00:00:00:00:00/e0 tag 0 cdb 0x0 data 4096 
> >>> in
> >>>  res 40/00:00:00:00:00/00:00:00:00:00/00 Emask 0x4 (timeout)
> >>> ata2: soft resetting port
> >>> ata2.00: configured for UDMA/33
> >>> ata2: EH complete
> >> What happens after this?
> >
> > More EH occurs - I've left it for ~5 mins, but let me know if longer
> > would give more information, eg if it converges on a lower speed.
> >
> > Would it be useful to compare some of the port setup registers in the
> > working and non-working cases? Or any other debug I can grab?
>
> I'm betting that this is the exact same problem we recently debugged
> for someone else here:  there's a Marvell PATA->SATA bridge chip between
> that CF card and the SATA controller, and it only works with PIO modes.
>
> Tejun.. perhaps (for debugging) a simple patch to disallow DMA completely,
> just to see if PIO works?

The ICH8 south-bridge I have is the mobile variant and does come
equipped with native parallel IDE - see page 447:
http://download.intel.com/design/chipsets/datashts/31305603.pdf . I do
see 35MB/s with DMA enabled from my CF on the 1 in 15 times the
libata-kernel does work.

I can dump off and decode the configuration registers for the timing
and bus master registers in the working and non-working libata cases,
and the legacy ATA working case and see what's different.

Dan
-- 
Daniel J Blueman
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RE: [PATCH] ide-cris: always tune PIO

2007-08-03 Thread Mikael Starvik
Yes, thanks!

Acked-by: Mikael Starvik <[EMAIL PROTECTED]>

-Original Message-
From: Bartlomiej Zolnierkiewicz [mailto:[EMAIL PROTECTED] 
Sent: Friday, August 03, 2007 12:46 AM
To: linux-ide@vger.kernel.org
Cc: Mikael Starvik
Subject: [PATCH] ide-cris: always tune PIO



Cc: Mikael Starvik <[EMAIL PROTECTED]>
Signed-off-by: Bartlomiej Zolnierkiewicz <[EMAIL PROTECTED]>
---
 drivers/ide/cris/ide-cris.c |2 ++
 1 file changed, 2 insertions(+)

Index: b/drivers/ide/cris/ide-cris.c
===
--- a/drivers/ide/cris/ide-cris.c
+++ b/drivers/ide/cris/ide-cris.c
@@ -808,6 +808,8 @@ init_e100_ide (void)
hwif->dma_off_quietly = &cris_dma_off;
hwif->cbl = ATA_CBL_PATA40;
hwif->pio_mask = ATA_PIO4,
+   hwif->drives[0].autotune = 1;
+   hwif->drives[1].autotune = 1;
hwif->ultra_mask = cris_ultra_mask;
hwif->mwdma_mask = 0x07; /* Multiword DMA 0-2 */
hwif->autodma = 1;

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